WO2022250722A1 - Procédé et appareil de mise en œuvre d'une lecture d'une mémoire flash au moyen de valeurs d'écart de décalage de tension de seuil compensées en temps de rétention et perturbation de lecture prédites - Google Patents

Procédé et appareil de mise en œuvre d'une lecture d'une mémoire flash au moyen de valeurs d'écart de décalage de tension de seuil compensées en temps de rétention et perturbation de lecture prédites Download PDF

Info

Publication number
WO2022250722A1
WO2022250722A1 PCT/US2021/053276 US2021053276W WO2022250722A1 WO 2022250722 A1 WO2022250722 A1 WO 2022250722A1 US 2021053276 W US2021053276 W US 2021053276W WO 2022250722 A1 WO2022250722 A1 WO 2022250722A1
Authority
WO
WIPO (PCT)
Prior art keywords
tvso
values
read
rrd
flash memory
Prior art date
Application number
PCT/US2021/053276
Other languages
English (en)
Inventor
Rino Micheloni
Lorenzo Zuolo
Original Assignee
Microchip Technology Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US17/385,857 external-priority patent/US11699493B2/en
Application filed by Microchip Technology Inc. filed Critical Microchip Technology Inc.
Priority to DE112021007027.4T priority Critical patent/DE112021007027T5/de
Priority to CN202180096618.0A priority patent/CN117157711A/zh
Publication of WO2022250722A1 publication Critical patent/WO2022250722A1/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/021—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters

Definitions

  • SSD Solid State Drives
  • standard read instructions e.g., READ or READ PAGE instruction
  • READ or READ PAGE instruction perform a read of a memory cell at a default threshold voltage within each threshold voltage region required to define a bit of the memory cell.
  • SLC Single Level Cell
  • flash memory devices store a single bit of information in each cell and only require a read in a single threshold voltage region (the threshold voltage region is the region that extends between the center of the voltage distribution for a 1 and the center of the voltage distribution for a 0) to identify the value of a bit (whether the cell is storing a 1 or a 0).
  • Multi-level cell (MLC) flash memory devices store two bits of information in each cell
  • triple level cell (TLC) flash memory devices store three bits of information in each cell
  • quad level cell (QLC) flash memory devices store four bits of information in each cell
  • penta level cell (PLC) flash memory devices store five bits of information in each cell.
  • Some SSD’s use threshold-voltage-shift reads for reading flash memory devices to obtain low levels of Uncorrectable Bit Error Rate (UBER) required for client and enterprise SSD’s.
  • Threshold-voltage-shift reads are performed by sending a threshold-voltage-shift read instruction to a flash memory device that is to be read.
  • One or more threshold-Voltage-Shift Offset (TVSO) value is sent with the threshold-voltage-shift read instruction.
  • the TVSO value indicates the amount by which the threshold voltage that is used to perform the read is to be offset from a corresponding default threshold voltage that is specified by the manufacturer of the flash memory device.
  • Threshold-voltage-shift read instructions for MLC, TLC, QLC and PLC flash memory devices require that multiple TVSO values be sent to the flash memory device in order to perform each read.
  • a method for identifying TVSO values to be used for reading a flash memory includes storing configuration files for a plurality of retention-and-read-disturb (RRD) -compensating regression neural networks (RNNs); identifying a current number of program and erase (PE) cycles of the flash memory; identifying TVSO values corresponding to the identified current number of PE cycles and identifying a current retention time and a current number of read disturbs for the flash memory.
  • the configuration file of the RRD-compensating RNN corresponding to the current number of PE cycles, the current retention time and the current number of read disturbs for the flash memory is selected and is loaded into a neural network engine to form an RNN core in the neural network engine.
  • a neural network operation of the RNN core is performed to predict RRD-compensated TVSO values.
  • the input to the neural network operation includes the identified TVSO values corresponding to the current number of PE cycles of the flash memory.
  • the predicted RRD-compensated TVSO values are optionally stored.
  • a read of the flash memory is performed using the predicted RRD-compensated TVSO values.
  • a flash controller includes a data storage; a neural network engine coupled to the data storage; and a status module configured for identifying a current number of PE cycles, a current retention time and a current number of read disturbs for a flash memory.
  • a control module is coupled to the neural network engine, the data storage and the status module.
  • the control module to identify TVSO values corresponding to a current number of PE cycles of the flash memory, the control module further to select a configuration file of a RRD-compensating RNN corresponding to the current number of PE cycles, the current retention time and the current read disturb of the flash memory; and to load the selected configuration file of the RRD-compensating RNN into the neural network engine to form a RNN core in the neural network engine.
  • the neural network engine to perform a neural network operation of the RNN core to predict RRD- compensated TVSO values, the input to the neural network operation including the identified TVSO values corresponding to the current number of PE cycles of the flash memory.
  • a read module is coupled to the status module and to the neural network engine. The read module to perform a read of the flash memory using the predicted RRD-compensated TVSO values.
  • the method and apparatus of the present invention provides a simple and accurate process for identifying TVSO values to be used in reads of a flash memory device and does not require background reads for identifying the TVSO values. Thereby the bandwidth that would have been consumed in performing background reads is available for host-requested read, program and erase operations.
  • FIG. 1 is a graph illustrating an SSD that includes a flash controller, flash memory devices and a memory device.
  • FIG. 2 is a diagram illustrating a method for performing a read of a flash memory using predicted RRD-compensated TVSO values.
  • FIG. 3 is a block diagram illustrating an RRD-compensating RNN.
  • FIG. 4A-4E are diagrams that illustrate reliability states.
  • FIG. 5 is a block diagram illustrating data records to be used for training an RRD- compensating RNN.
  • FIG. 6A-6E are block diagrams illustrating generation of RRD-compensating RNN’s corresponding to the reliability states shown in FIGS. 4A-4E.
  • FIG. 7 is a block diagram illustrating a neural network operation of an RRD- compensating RNN.
  • FIG. 1 shows an SSD 1 that includes a flash controller 3, a plurality of flash memory devices 2 (each of which are referred to herein singularly as a flash memory 2) and memory device 13.
  • Flash controller 3 is coupled to flash memory devices 2 for storing data and for reading data using threshold voltage shift reads of flash memory devices 2.
  • flash memory devices 2 are NAND devices and flash controller 3
  • flash memory devices 2 and memory device 13 are mounted to a circuit board (not shown).
  • Memory device 13 is a volatile memory device such as a Dynamic Random Access Memory (DRAM) that is electrically coupled to flash controller 3.
  • DRAM Dynamic Random Access Memory
  • Flash controller 3 includes data storage 4, status module 5, read module 6, decode module 7, write module 8, control module 9, neural network engine 10 and input and output (I/O) module 11.
  • Control module 9 is coupled to data storage 4, status module 5, read module 6, decode module 7, write module 8, neural network engine 10 and input and output (I/O) module 11.
  • Decode module 7 is further coupled to read module 6.
  • Status module 5 is further coupled to data storage 4, read module 6, write module 8 and neural network engine 10.
  • Read module 6 is further coupled to data storage 4, neural network engine 10 and I/O module 11.
  • Neural network engine 10 is further coupled to data storage 4.
  • Input and output (I/O) module 11 is further coupled to data storage 4 and write module 8.
  • modules 5-11 include circuits that are dedicated circuits for performing operations, and some or all of modules 5-11 can be firmware that includes instructions that are performed on one or more processor for performing operations of flash controller 3, with the instructions stored in registers of one or more of modules 5-11 and/or stored in data storage 4 or memory device 13. Some of all of modules 5-11 include processors for performing instructions and instructions are loaded into flash controller 3 prior to operation of flash controller 3 by a user.
  • Flash controller 3 is configured to receive read and write instructions from a host computer at I/O module 11 and to perform program operations, erase operations and read operations on memory cells of flash memory devices 2 to complete the instructions from the host computer. For example, upon receiving a write instruction from a host computer, write module 8 is operable to program codewords into one or more of flash memory devices 2.
  • Flash memory devices 2 are performed by sending a threshold-voltage-shift read instruction to the flash memory device 2 that is to be read. One or more TVSO value are sent with the threshold-voltage-shift read instruction.
  • Flash memory devices 2 can be MLC flash memory devices, TLC flash memory devices, QLC flash memory devices or PLC flash memory devices.
  • Status module 5 is operable to track the status and the operations of flash controller 3 and flash memory devices 2.
  • Data storage module 4 is a structure in flash controller 3 that is capable of storing data, and may include cache memory and/or static random-access memory (SRAM).
  • Neural network engine 11 includes a specialized hardware module (e.g., a specialized configurable accelerator/processing circuit) specifically configured to perform a neural network operation.
  • FIG. 2 illustrates a method (100) for reading a flash memory using TVSO values identified using RRD-compensating RNNs.
  • Configuration files for a plurality of RRD- compensating RNNs are stored (101).
  • each of a plurality of RRD-compensating RNN’s is represented by a configuration file 23 that is stored in data storage 4 (FIG. 1).
  • configuration files 23 for some or all of the RRD-compensating RNNs are stored in memory device 13 and/or in one or more flash memory devices 2.
  • FIG. 2 illustrates a method (100) for reading a flash memory using TVSO values identified using RRD-compensating RNNs.
  • Configuration files for a plurality of RRD-compensating RNNs are stored (101).
  • each of a plurality of RRD-compensating RNN’s is represented by a configuration file 23 that is stored in data storage 4 (FIG. 1).
  • configuration files 23 for some or all of the RRD-compensating RNNs are stored
  • the configuration file for each RRD-compensating RNN includes a set of hyperparameters including weight and bias values.
  • the configuration file specifies the architecture of the particular RRD-compensating RNN such as, for example, the number of input neurons, number of output neurons, a number of layers of hidden neurons, a number of hidden neurons in each layer of hidden neurons and a type of activation function module (AFM) to be used.
  • AMF activation function module
  • FIG. 3 illustrates an RRD-compensating RNN 30 that includes an input layer 31 that includes input neurons 31a-c that receive respective inputs XI through Xn, hidden layers 32-33 that include hidden neurons and an output layer 34 that includes output neurons 34a-34c that generate respective outputs Yl-Yn. It is appreciated that RRD-compensating RNN 30 is an example and that many other combinations of input layer 31, hidden layers 32-33 and output layer 34 are possible, including layers with different connections between individual neurons, more hidden layers 32-33 and more or fewer neurons in each of the layers 31-34 of RRD- compensating RNN 30.
  • RRD-compensating RNN 30 shows each neuron coupled to all of the neurons of the following layer, alternatively, each neuron in a particular layer is coupled to only some of the neurons in the following layer.
  • RNN 30 includes a number of input neurons 3 la-3 lc equal to the number of TVSO values required for reading the flash memory and includes a number of output neurons 34a-34c equal to the number of TVSO values required for reading the flash memory.
  • RRD-compensating RNN 30 is generated by performing flash characterization testing to identify how the representative flash memory devices that are being tested perform under varying retention-time conditions and varying read-disturb conditions (together referred to as “transitory conditions”), where the varying retention-time and read- disturb conditions, i.e. the varying transitory conditions, are represented by corresponding transitory-reliability-states.
  • the term “transitory-reliability-state’ ” as used in the present application refers to a reliability state that includes the transitory characteristics of the flash memory devices, and specifically includes a reliability state in which the current number of program erase (PE) cycles, the retention time (RT) and the number of read disturbs (RD) are specified.
  • the term “reliability state,” as used in the present application is an interval relating to age and usage of a memory location (e.g. a particular wordline/block/page) of a flash memory device that can be defined using measurements such as the number of PE cycles, RT and RD.
  • the lifetime of each flash memory 2 is divided into a plurality of periods based on the number of PE cycles in the lifetime of the flash memory and a set of RRD- compensating RNN’s is associated with each of the plurality of periods.
  • the lifetime of each flash memory 2 is divided into five periods based on lifetime, include a first period corresponding to 0 ⁇ PE ⁇ 1000 that is shown in FIG. 4A, a second period corresponding to 1000 ⁇ PE ⁇ 2000 that is shown in FIG. 4B, a third period corresponding to 2000 ⁇ PE ⁇ 3000 that is shown in FIG. 4C, a fourth period corresponding to 3000 ⁇ PE ⁇ 4000 that is shown in FIG.
  • a set of RRD-compensating RNN’s is generated corresponding to each of the different periods, with each set of RRD-compensating RNN’s trained using data records corresponding to the particular period.
  • retention time is divided into four retention-time (RT) categories and the number of read disturbs (RD) is divided into four categories. It is appreciated that these categories are illustrative and that more or fewer categories could be used.
  • FIG. 4A these exemplary categories are used to define non-transitory- reliability-state 41-1 and transitory-reliability-states 42-1 through 56-1 shown in FIG. 4A that correspond to the first period.
  • FIGURES 4A-4E denote PE, RT AND RD value ranges using parenthesis and brackets, where parentheses are used to denote exclusive values and brackets are used to denote inclusive values.
  • each of transitory-reliability- states 42-1 through 56-1 is represented by a single neural network that is stored as an RDD- compensating configuration file 23 in FIG. 1.
  • FIG. 4C shows non-transitory-reliability-state 41-3 in which 2000 ⁇ PE ⁇ 3000 and transitory-reliability-states 42-3 through 56-3 that correspond to the third period.
  • FIG. 4D shows non-transitory-reliability-state 41-4 in which 3000 ⁇ PE ⁇ 4000 and transitory-reliability-states 42-4 through 56-4 that correspond to the fourth period.
  • FIG. 4E shows non-transitory-reliability-state 41-5 in which 4000 ⁇ PE ⁇ 5000 and transitory-reliability- states 42-5 through 56-5 that correspond to the fifth period.
  • one or more representative NAND flash memory is cycled to reach one of the non-transitory-reliability-states and the TVSO values minimizing the raw bit error rate (RBER) are calculated for all of the wordlines of all the blocks to generate a training dataset.
  • the one or more representative NAND flash memory is then stressed through all the corresponding transitory-reliability-states and, for each transitory- reliability-state, TVSO values minimizing the RBER are calculated for all the wordlines of all the blocks.
  • the representative flash memory device is cycled to a number of PE cycles “x” within a respective non-transitory reliability state and testing is performed at each wordline of all the blocks to identify TVSO values minimizing RBER to generate a data record 61 for the particular wordline and block.
  • 384 wordlines of 100 blocks are tested to generate 38,400 data records 61 for the non-transitory- reliability-state and RT and RD are cycled through the respective transitory reliability states to generate data records 62-76.
  • a set of data records 61-76 will be generated for each of the periods illustrated in FIGS. 4A-4E.
  • the data records 61 - 76 each show 7 TVSO values which is representative of the number of TVSO values needed for a triple level cell, however this is not meant to be limiting in any way.
  • FIG. 4A Following is an example of data records generated for the first period shown in FIG. 4A.
  • the representative flash memory device is cycled to a number of PE cycles equal to 500 (the midpoint for the non-transitory reliability state) and testing is performed at each wordline of all the blocks to identify TVSO values minimizing RBER to generate a data record 61 for the particular wordline and block (e.g., a total of 38,400 data records 61).
  • the number of read disturbs is cycled to 500 (the midpoint for the transitory-reliability-state 42-1 of FIG.
  • the TVSO values minimizing RBER in respective data records 61-76 for non-transitory-reliability-state 41-1 and transitory-reliability-states 42-1 through 56-1 are illustrated respectively as 61a, 62a, 63a, 64a, 65a, 66a, 67a, 68a, 69a, 70a, 71a, 72a, 73a, 74a, 75a and 76a in FIG. 6A.
  • 61a is repeated adjacent each of 62a, 63a, 64a, 65a, 66a, 67a, 68a, 69a, 70a, 71a, 72a, 73a, 74a, 75a and 76a for ease of understanding.
  • the TVSO values minimizing RBER in respective data records 61-76 for non- transitory-reliability-state 41-2 and transitory-reliability-states 42-2 through 56-2 of FIG. 4B are illustrated respectively as 61b, 62b, 63b, 64b, 65b, 66b, 67b, 68b, 69b, 70b, 71b, 72b, 73b, 74b, 75b and 76b in FIG. 6B.
  • the TVSO values minimizing RBER in respective data records 61-76 for non-transitory-reliability-state 41-3 and transitory-reliability-states 42-3 through 56-3 of FIG. 4C are illustrated respectively as 61c, 62c, 63c, 64c, 65c, 66c, 67c, 68c, 69c, 70c, 71c, 72c, 73c, 74c, 75c and 76c in FIG. 6C.
  • the TVSO values minimizing RBER in respective data records 61- 76 for non-transitory-reliability-state 41-4 and transitory-reliability-states 42-4 through 56-4 of FIG. 4D are illustrated respectively as 61d, 62d, 63d, 64d, 65d, 66d, 67d, 68d, 69d, 70d, 71d,
  • the TVSO values minimizing RBER in respective data records 61-76 for non-transitory-reliability-state 41-5 and transitory-reliability-states 42-5 through 56-5 of FIG. 4E are illustrated respectively as 61e, 62e, 63e, 64e, 65e, 66e, 67e, 68e,
  • the data record corresponding to the non-transitory-reliability-state is used to train each of the RRD-compensating RNN’s and the data records corresponding to one of the transitory-reliability-states is used as the target data set in the training.
  • some of the records corresponding to the particular transitory-reliability state are used for verification and after the RRD-compensating RNN’s are trained and verified a configuration file 23 for the trained RRD-compensating RNN is stored.
  • the configuration file 23 includes hyperparameters (bias values and weighting values) corresponding to the trained RRD-compensating RNN 30.
  • the configuration file 23 can also indicate the architecture of the neural network.
  • training uses TVSO values 61a from data records 61 as a training data set to train a first neural network 42- lm (that corresponds to reliability state 42-1) using TVSO values 62a from data records 62 as a target data set.
  • the training can use a stochastic gradient descent (SGD) training process, performed to achieve predetermined performance criteria (e.g., a min-squared error value) for TVSO values responsive to perturbance of the transitory conditions.
  • SGD stochastic gradient descent
  • ADAM adaptive moment estimation
  • second neural network 43- lm is trained using TVSO values 61a from data records 61 as a training data set and using TVSO values 63a from data records 63 as a target data set
  • third neural network 44-lm is trained using TVSO values 61a from data records 61 as a training data set and using TVSO values 64a from data records 64 as a target data set
  • fourth neural network 45- lm is trained using TVSO values 61a from data records 61 as a training data set and using TVSO values 65a from data records 65 as a target data set
  • fifth neural network 46- lm is trained using TVSO values 61a from data records 61 as a training data set and using TVSO values 66a from data records 66 as a target data set
  • sixth neural network 47- lm is trained using TVSO values 61a from data records 61 as a training data set and using TVSO values
  • RRD-compensating RNN’s 75b and 76b corresponding to transitory-reliability-states are used to train RRD-compensating RNN’s in the same manner as discussed with reference to FIG. 6A, forming RRD-compensating RNN’s 42-2m through 56-2m, each of which is stored as a configuration file 23.
  • TVSO values 61c corresponding to non-transitory-reliability- state 41-3 and TVSO values 62c, 63c, 64c, 65c, 66c, 67c, 68c, 69c, 70c, 71c, 72c, 73c, 74c, 75c and 76c corresponding to transitory-reliability-states are used to train RRD-compensating RNN’s in the same manner as discussed with reference to FIG. 6A-6B, forming RRD-compensating RNN’s 42-3m through 56-3m, each of which is stored as a configuration file 23.
  • FIG. 6C TVSO values 61c corresponding to non-transitory-reliability- state 41-3 and TVSO values 62c, 63c, 64c, 65c, 66c, 67c, 68c, 69c, 70c, 71c, 72c, 73c, 74c, 75c and 76c corresponding to transitory-reliability-states are used to train
  • TVSO values 61d corresponding to non-transitory-reliability-state 41-4 and TVSO values 62d, 63d, 64d, 65d, 66d, 67d, 68d, 69d, 70d, 71d, 72d, 73d, 74d, 75d and 76d corresponding to transitory-reliability-states are used to train RRD-compensating RNN’s in the same manner as discussed with reference to FIG. 6A-6C, forming RRD-compensating RNN’s 42-4m through 56-4m, each of which is stored as a configuration file 23. Referring now to FIG.
  • TVSO values 61e corresponding to non-transitory-reliability-state 41-5 and TVSO values 62e, 63e, 64e, 65e, 66e, 67e, 68e, 69e, 70e, 71e, 72e, 73e, 74e, 75e and 76e corresponding to transitory-reliability-states are used to train RRD-compensating RNN’s in the same manner as discussed with reference to FIG. 6A-6D, forming RRD-compensating RNN’s 42-5m through 56- 5m, each of which is stored as a configuration file 23.
  • a current number of PE cycles of the flash memory is identified (102).
  • Status module 5 of FIG. 1 is configured to identify the current number of PE cycle values by maintaining a count of the current number of PE cycles for the flash memory device 2 (e.g., for each block of each flash memory device 2) and store the current number of PE cycles (e.g., for each block of each flash memory device 2) in registers of status module 5 or in a table stored in data storage 4 or in memory device 13.
  • TVSO values corresponding to the current number of PE cycles are identified (103).
  • the identified TVSO values can be the TVSO values specified by the manufacturer of the flash memory for the current number of PE cycles of the flash memory 2.
  • the identified TVSO values are the TVSO values specified by the manufacturer for the current number of PE cycles and for a particular block and/or wordline and/or page of flash memory device 2.
  • step 103 is performed using a PE-TVSO lookup table that includes PE cycle values and associated TVSO values.
  • the PE-TVSO table can also specify TVSO values corresponding to blocks and/or pages and/or wordlines or groups of blocks and/or groups of wordlines and/or groups of pages as is known in the art.
  • a PE-TVSO lookup table 24 is stored in data storage 4 of FIG. 1 or in memory device 13.
  • the TVSO values identified in step 103 that may be referred to as “non-transitory TVSO values” corresponding to the age/usage of the flash memory device 2.
  • non-transitory TVSO values includes TVSO values that correspond to the number of PE cycles, and that do not take into account transitory characteristics such as retention time and read disturb.
  • the five periods corresponding to non-transitory-reliability- states 41-1, 41-2, 41-3, 41-4 and 41-5 shown in FIGS. 5A-5E are also used to build the PE- TVSO lookup table 24 shown in FIG. 1, which is stored in data storage 4. More particularly, during flash characterization, representative flash devices that are similar to flash memory devices 2 are tested under a variety of conditions to determine the best TVSO values to use to perform a read during each of the periods.
  • a current retention time and a current number of read disturbs for the flash memory are identified (104).
  • Status module 5 of FIG. 1 is configured for identifying a current retention time and a current number of read disturbs for a flash memory 2.
  • the current retention time and current number of read disturbs represent the transitory characteristics of each location that is to be read in the flash memory device 2.
  • each time that a block is closed status module 5 is operable to count the number of reads of the block while the block is closed and the number of reads of the block while the block is closed is stored as a read disturb value. When a block is erased, the read disturb value of the erased block is reset to zero.
  • the current retention time is a closed-block retention time
  • status module 5 is operable to start a timer to determine the amount of time that has elapsed since the block was closed. The elapsed time as determined by the timer at any point in time is defined as the current retention time for the particular block.
  • control module 9 is operable to send a query to status module 5 indicating a block number and in response status module 5 is operable to indicate the current retention time and current number of read disturbs for the particular block.
  • the configuration file of the RRD-compensating RNN corresponding to the current number of PE cycles, the current retention time and current number of read disturbs for the flash memory is selected (105) and the selected configuration file of the RRD-compensating RNN is loaded (106) into a neural network engine to form an RNN core in the neural network engine.
  • control module 9 of FIG. 1 is configured to select the configuration file of the RRD-compensating RNN 23 associated with the current number of PE cycles, the current RT and the current RD and load the selected RRD-compensating RNN configuration file 23 into the neural network engine 10 to form an RNN core in the neural network engine 10.
  • the RRD-compensating RNN configuration file 23 corresponding to one of transitory-reliability states 42-1 through 56-1, 42-2 through 56-2, 42-3 through 56-3, 42-4 through 56-4 or 42-15 through 56-5 is selected in step 105 and loaded in step 106.
  • a configuration-file-lookup table 26 is stored in data storage 4 that includes an indication of a number of PE cycles, a RT and RD and indicates, for each particular indication of a number of PE cycles, RT and RD, an identifier of an associated RRD-compensating RNN configuration file 23.
  • the identifier of the associated RRD-compensating RNN configuration file 23 can be in the form of an index that identifies the RRD-compensating RNN configuration file 23 or an address indicating where the RRD-compensating RNN configuration file 23 is stored.
  • control module 9 is operable in step 105 to performing a lookup in configuration- file-lookup table 26 using the current number of PE cycles, the current retention time and the current number of read disturbs of a particular block to identify the address in data storage 4 where the RRD-compensating RNN configuration file 23 to use is stored and the address in data storage 4 is utilized to obtain the RRD-compensating RNN configuration file 23 to be loaded into neural network engine 10.
  • configuration-file-lookup table 26 includes an indication of a number of PE cycles, RT and RD and indicates, for each particular indication of the number of PE cycles, RT and RD an identifier of an associated RRD-compensating RNN configuration file 23.
  • the identifier of the associated RRD-compensating RNN configuration file 23 can be in the form of an index that identifies the RRD-compensating RNN configuration file 23 or an address indicating where the RRD-compensating configuration file 23 is stored.
  • control module 9 is operable in step 105 to performing a lookup in configuration-file-lookup table 26 using the current number of PE cycles, the current RT and the current RD of a particular block to identify the address in data storage 4 where the configuration file 23 to use is stored and the address in data storage 4 is utilized to obtain the RRD-compensating RNN configuration file 23 to be loaded into the neural network engine 10.
  • the architecture of the neural network engine 10 is fixed, predetermined, or is otherwise established prior to starting method 100 and each of the stored RRD- compensating RNNs have the same number of input neurons, output neurons, connections between neurons and use the same activation functions such that the selecting and loading of steps 105-106 require only the selection and loading of bias values and weighting values into neural network 10.
  • neural network engine 10 includes configurable logic and the neural network engine is configured in accordance with an architecture that is common to each of the RRD-compensating RNNs prior to performing step 101.
  • a neural network operation of the RNN core is performed (107) to predict RRD- compensated TVSO values, the input to the neural network operation including the identified TVSO values corresponding to the current number of PE cycles of the flash memory.
  • neural network engine 10 is operable to perform a neural network operation of the RNN core to predict RRD-compensated TVSO values, the input to the neural network operation comprising the identified TVSO values corresponding to the current number of PE cycles of the flash memory 2.
  • step 107 shows an example of step 107 in which input 81 into the neural network operation of RNN core 82 includes seven TVSO values (TVSOl, TVS02, TVS03, TVS04, TVS05, TVS06 and TVS07) to generate seven predicted RRD-compensated TVSO values 83 at the output neurons of RNN core 82, where y represents the retention time and z represents the number of read disturbs that were compensated for in the neural network operation.
  • the perturbance of the transitory conditions i.e. the retention time and read disturbs, is taken into account by the selection of the appropriate RRD-compensating RNN, i.e. the selection in step 105 of the appropriate RRD-compensating RNN configuration file 23.
  • the predicted RRD-compensated TVSO values 83 are stored (108).
  • control module 9 is optionally operable to store the predicted RRD-compensated TVSO values 83 in data storage 4 or in memory device 13.
  • the predicted RRD- compensated TVSO values 83 are stored in a TVSO-read lookup table 25 that is stored in data storage 4.
  • TVSO-read lookup table 25 includes an indication of a wordline index, a block number (and optionally a page indicator) and, for each indication of a wordline index and block number (and optional page indicator), the associated RRD-compensated TVSO values to be used for reading that wordline/block/page.
  • Steps 102-108 are optionally repeated (109). In one example, steps 102-108 are repeated each time that the current number of PE cycles reaches a predetermined PE cycle threshold, RT reaches a predetermined retention-time threshold, or the current RD reaches a read-disturb threshold.
  • control module 9 is configured to determine when the current number of PE cycles reaches a predetermined PE cycle threshold, when the current RT reaches a predetermined retention-time threshold and when the current RD reaches a read-disturb threshold, and each time the current number of PE cycles reaches a predetermined PE cycle threshold, the current RT reaches a predetermined retention-time threshold or the current RD reaches a read-disturb threshold: the control module 9 is operable to repeat the identifying a current number of PE cycles, the identifying TVSO values, the identifying a current RT and RD, the selecting the configuration file 23 and the loading the selected configuration file 23, the neural network engine 10 is operable to repeat the performing a neural network operation of the RNN core to predict the RRD-compensated TVSO values, and the control module is configured to repeat the updating the TVSO values to be used for reading the flash memory 2 by replacing at least some of the TVSO values to be used for reading the flash memory 2 stored in the TVSO- read lookup table 25 with the predicted
  • a plurality of PE cycle thresholds are used, including a PE cycle threshold corresponding to each of the periods used to generate the RRD-compensating RNN’s (corresponding to the non-transitory-reliability-states used to generate the RDD-compensating RNN’s) such that the predicted RRD-compensated TVSO values stored in the TVSO-read lookup table correspond to the current period in the lifetime of the flash memory 2.
  • a plurality of retention time thresholds are used (including a retention time threshold corresponding to the retention time limits of each of the transitory-reliability states) and a plurality of read disturb thresholds are used (including a read-disturb threshold corresponding to the read disturb limits of each of the transitory-reliability states used to generate the RRD- compensating RNN’s) such that the predicted RRD-compensated TVSO values stored in the TVSO-read lookup table correspond to the current transitory-reliability-state of the flash memory 2.
  • a read of the flash memory is performed (110) using the predicted RRD-compensated TVSO values.
  • read module 6 of FIG. 1 is configured to perform a read of the flash memory 2 using the predicted RRD-compensated TVSO values.
  • step 103 includes identifying at the flash controller TVSO values corresponding to the current number of PE cycles for a page of the flash memory 2 that is to be read in step 110 such that the RRD- compensated TVSO values predicted in step 107 and used to perform the read of step 110 are RRD-compensated TVSO values for the page of the flash memory to be read.
  • the status module 5 is operable to identify a current number of PE cycles, current RT and current RD corresponding to the read address
  • the read module 6 is configured to perform a lookup in the TVSO-read lookup table 25 to identify a current set of TVSO values corresponding to the read address, the current number of PE cycles, the current RT, and the current RD
  • the read module is configured to perform the read of the flash memory 2 in step 110 using the identified current set of TVSO values.
  • the present method and apparatus does not require background reads of flash memories 2 to identify the TVSO values to be used for performing reads of flash memories 2. Accordingly, the bandwidth that conventional SSDs that require reads of flash memories 2 require for performing background reads is available to flash memory devices 2, resulting in performance improvement as compared to conventional SSD’s that require background reads for identifying TVSO values to be used for performing reads.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Health & Medical Sciences (AREA)
  • Computing Systems (AREA)
  • Biomedical Technology (AREA)
  • Biophysics (AREA)
  • Computational Linguistics (AREA)
  • Data Mining & Analysis (AREA)
  • Evolutionary Computation (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Molecular Biology (AREA)
  • Artificial Intelligence (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Health & Medical Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

Procédé de mise en œuvre d'une lecture d'une mémoire flash comprenant le stockage de fichiers de configuration pour une pluralité de RNN à compensation de RRD. Un nombre courant de cycles PE pour une mémoire flash est identifié et des valeurs TVSO sont identifiées correspondant au nombre courant de cycles PE. Un temps de rétention courant et un nombre courant de perturbations de lecture pour la mémoire flash sont identifiés. Le fichier de configuration du RNN à compensation de RRD correspondant au nombre courant de cycles PE, le temps de rétention courant et le nombre courant de perturbations de lecture sont sélectionnés et sont chargés dans un moteur de réseau neuronal afin de former un cœur RNN dans le moteur de réseau neuronal. Une opération de réseau neuronal du cœur RNN est mise en œuvre afin de prédire des valeurs TVSO compensées en RRD. L'entrée dans l'opération de réseau neuronal comprend les valeurs TVSO identifiées. Une lecture de la mémoire flash est mise en œuvre au moyen des valeurs TVSO compensées en RRD prédites.
PCT/US2021/053276 2021-05-24 2021-10-02 Procédé et appareil de mise en œuvre d'une lecture d'une mémoire flash au moyen de valeurs d'écart de décalage de tension de seuil compensées en temps de rétention et perturbation de lecture prédites WO2022250722A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE112021007027.4T DE112021007027T5 (de) 2021-05-24 2021-10-02 Verfahren und vorrichtung zum durchführen eines lesevorgangs von einem flash-speicher unter verwendung vorhergesagter retentions- und lesestörungs- kompensierter schwellenspannungsverschiebungs-versatzwerte
CN202180096618.0A CN117157711A (zh) 2021-05-24 2021-10-02 用于使用预测的经保留与读取干扰补偿的阈值电压偏移补偿值来执行对闪存存储器的读取的方法和装置

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US202163192543P 2021-05-24 2021-05-24
US63/192,543 2021-05-24
US17/385,857 US11699493B2 (en) 2021-05-24 2021-07-26 Method and apparatus for performing a read of a flash memory using predicted retention-and-read-disturb-compensated threshold voltage shift offset values
US17/385,857 2021-07-26

Publications (1)

Publication Number Publication Date
WO2022250722A1 true WO2022250722A1 (fr) 2022-12-01

Family

ID=78599207

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2021/053276 WO2022250722A1 (fr) 2021-05-24 2021-10-02 Procédé et appareil de mise en œuvre d'une lecture d'une mémoire flash au moyen de valeurs d'écart de décalage de tension de seuil compensées en temps de rétention et perturbation de lecture prédites

Country Status (1)

Country Link
WO (1) WO2022250722A1 (fr)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9251909B1 (en) * 2014-09-29 2016-02-02 International Business Machines Corporation Background threshold voltage shifting using base and delta threshold voltage shift values in flash memory
US20200210831A1 (en) * 2018-12-31 2020-07-02 SK Hynix Inc. Storage device performance optimization using deep learning

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9251909B1 (en) * 2014-09-29 2016-02-02 International Business Machines Corporation Background threshold voltage shifting using base and delta threshold voltage shift values in flash memory
US20200210831A1 (en) * 2018-12-31 2020-07-02 SK Hynix Inc. Storage device performance optimization using deep learning

Similar Documents

Publication Publication Date Title
CN111009280B (zh) 存储装置以及存储装置的操作方法
US11699493B2 (en) Method and apparatus for performing a read of a flash memory using predicted retention-and-read-disturb-compensated threshold voltage shift offset values
US10152273B2 (en) Nonvolatile memory controller and method for erase suspend management that increments the number of program and erase cycles after erase suspend
US20220027083A1 (en) Regression Neural Network for Identifying Threshold Voltages to be Used in Reads of Flash Memory Devices
US10291263B2 (en) Auto-learning log likelihood ratio
US20220058488A1 (en) Partitionable Neural Network for Solid State Drives
US11514992B2 (en) Method and apparatus for reading a flash memory device
CN108108810A (zh) 包括非易失性存储器件的存储装置及访问方法
US20220165348A1 (en) Method and apparatus for determining when actual wear of a flash memory device differs from reliability states for the flash memory device
US11514994B1 (en) Method and apparatus for outlier management
CN108847267A (zh) 一种基于错误模式的闪存寿命测试方法
CN108694989A (zh) 存储设备及其坏块指派方法
US7277981B2 (en) Scratch control memory array in a flash memory device
US11216338B2 (en) Storage device that performs state shaping of data
WO2022250722A1 (fr) Procédé et appareil de mise en œuvre d'une lecture d'une mémoire flash au moyen de valeurs d'écart de décalage de tension de seuil compensées en temps de rétention et perturbation de lecture prédites
KR102491655B1 (ko) 에러 카운트를 결정하는 스토리지 컨트롤러, 그것의 동작하는 방법, 및 그것을 포함하는 스토리지 장치의 동작하는 방법
KR20240033792A (ko) 읽기 정보 및 디코딩 정보에 기초하여 연판정 디코딩을 위한 읽기 레벨을 생성하는 스토리지 컨트롤러, 이를 포함하는 스토리지 장치, 및 이의 동작 방법
CN117980994A (zh) 存储器中经改进的ecc配置
WO2017075747A1 (fr) Procédés, systèmes et supports pour programmer un dispositif de stockage
CN115458027A (zh) 一种测试存储器地址保持时间的方法、装置、设备及介质
CN116830200A (zh) 用于读取闪存存储器设备的方法和装置
EP4198988A1 (fr) Contrôleur de stockage utilisant des données d'historique, son procédé de fonctionnement et procédé de fonctionnement de dispositif de stockage le comprenant
EP4160603A1 (fr) Contrôleur de stockage déterminant le nombre d'erreurs, son procédé de fonctionnement, et procédé de fonctionnement d'un dispositif de stockage le comprenant
EP3783611A1 (fr) Mémoire procédant à la mise en forme de l'état des données
WO2022182374A1 (fr) Procédé et appareil de lecture d'un dispositif de mémoire flash

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21806526

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 112021007027

Country of ref document: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21806526

Country of ref document: EP

Kind code of ref document: A1