WO2022247488A1

WO2022247488A1 - Automated test equipment system and automated test equipment method therefor

Info

Publication number: WO2022247488A1
Application number: PCT/CN2022/085894
Authority: WO
Inventors: 王祎; 王家敏; 方延奋; 郭峻
Original assignee: 爱德万测试股份有限公司
Priority date: 2021-05-25
Filing date: 2022-04-08
Publication date: 2022-12-01
Also published as: CN115391108A

Abstract

An automated test equipment method, applicable to an automated test equipment system. The automated test equipment method comprises: receiving, by a first-in first-out memory, a register value of a device under test, receiving an input value of an automated test equipment by the first-in first-out memory, and receiving a selection signal of the automated test equipment by the first-in first-out memory, to write the register value or the input value into the device under test for testing. Therefore, the automated test equipment and the device under test only communicate once, such that the execution efficiency of a test program of read-modify-write is improved, and then the test time is reduced.

Description

Automatic test equipment system and automatic test equipment method thereof

This application claims the priority of Chinese patent application 2021105730570 with a filing date of 2021/5/25. This application cites the full text of the above-mentioned Chinese patent application.

technical field

The invention relates to an automatic testing equipment system and an automatic testing equipment method thereof.

Background technique

The Automated Test Equipment (ATE) is configured to test the Device Under Test (DUT). The automatic test equipment stores program description language programs. In the field of semiconductor testing, automatic test equipment needs to execute programming-based programs to implement test design (Device For Test, DFT) specifications. Register operations are widely used in test design, and one of the well-known operations is Read-Modify-Write (Read-Modify-Write, RMW). The described operation requires the automatic test equipment to write a dedicated value from the register while leaving the remaining values unchanged. Therefore, automatic test equipment needs to first read the registers, modify some values, and then write the new values back to the device under test. The three steps of the automatic test equipment consume a lot of communication work between the automatic test equipment and the device under test. With thousands or even millions of read-modify-write operations throughout the test program, the overhead of communication can significantly impact production throughput.

Contents of the invention

In order to overcome the above-mentioned problems, the object of the present invention is to introduce a new test procedure implementing read-modify-write. The present invention uses a hardware first-in-first-out (FIFO) memory to take over the role of communication between the automatic test equipment and the device to be tested. The FIFO memory can first store the entire register value read from the device under test and then combined with the input value to be written back to the device under test under automatic test equipment control. The entire process requires no interruption between the automatic test equipment and the device under test, and is done transparently in real time like template execution. If the register operation requires a high-speed protocol (greater than 40MHz), the propagation delay time of the hardware's first-in-first-out memory can be compensated by automatic test equipment to calibrate the position of the signal edge. In addition, automatic test equipment can attach register compare operations to double-assure read-modify-write operations. That is, high reliability applications are often required to do so.

A preferred embodiment of the present invention provides an automatic test equipment method, which is suitable for an automatic test equipment system. The above automatic test equipment method includes: receiving a register value of a device under test through a first-in-first-out memory; receiving an input value of an automatic test equipment through the above-mentioned first-in-first-out memory; and receiving the above-mentioned automatic test equipment through the above-mentioned first-in-first-out memory. A signal is selected to write the above-mentioned register value or the above-mentioned input value to the above-mentioned device under test.

A preferred embodiment of the present invention provides an automatic test equipment system, which is characterized in that it includes: a device under test, an automatic test equipment, and a first-in first-out memory. The above-mentioned device under test is used for outputting register values. The above-mentioned automatic test equipment is used to output the input value. The above-mentioned first-in-first-out memory is connected to the above-mentioned device under test and the above-mentioned automatic test equipment, and is used to receive the above-mentioned register value of the above-mentioned device under test, receive the above-mentioned input value of the above-mentioned automatic test equipment, and receive the selection signal of the above-mentioned automatic test equipment to write The above-mentioned register value or the above-mentioned input value is sent to the above-mentioned device under test.

In an embodiment of the present invention, the above-mentioned automatic test equipment method further includes: receiving the test value of the above-mentioned automatic test equipment through the above-mentioned first-in-first-out memory, and outputting the result value according to the above-mentioned test value to the above-mentioned automatic test equipment through the above-mentioned first-in-first-out memory In order to provide the above-mentioned automatic test equipment to judge whether the above-mentioned first-in-first-out memory is operating normally.

In an embodiment of the present invention, the FIFO memory includes: a shift register and a multiplexer. The shift register receives the register value of the device under test. The multiplexer is connected to the shift register and receives the register value, the input value and the selection signal.

In an embodiment of the present invention, the shift register generates a 64-bit dummy cycle to reset the shift register.

In an embodiment of the present invention, the shift register is 74HC7731, and the multiplexer is 74HC157.

In an embodiment of the present invention, the above-mentioned FIFO memory includes 74HC7403.

The automatic test equipment system and the automatic test equipment method provided by the present invention enable the automatic test equipment to communicate with the device under test only once, reduce the test time of read-modify-write operation by more than 80%, and develop the test program Programming effort is also reduced, which in turn reduces testing time. In addition, the present invention further provides a diagnostic program to ensure the hardware quality of the FIFO memory. In addition, hardware FIFO can be realized by independent digital IC, CPLD/FPGA or even by internal hardware design of automatic test equipment.

The above description is only an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable , the following preferred embodiments are specifically cited, and in conjunction with the accompanying drawings, the detailed description is as follows.

Description of drawings

FIG. 1 is a block diagram of an automatic test equipment system according to an embodiment of the present invention.

FIG. 2 is a flowchart of an automatic test equipment method according to an embodiment of the present invention.

FIG. 3 is a detailed flowchart of an automatic test equipment method according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of a first-in-first-out memory according to an example of the present invention.

FIG. 5 is a schematic diagram of a first-in-first-out memory according to another example of the present invention.

Detailed ways

Please refer to Fig. 1, the automatic test equipment system 1 of an embodiment of the present invention comprises a device under test 2, an automatic test device 3, and a first-in-first-out memory 4, wherein the first-in-first-out memory 4 is connected to the device under test 2 and the automatic Test equipment3.

In addition, the automatic test equipment 3 is used to output control signals to control the operation of the FIFO memory 4 and output test values, input values, and selection signals to the FIFO memory 4.

The first-in first-out memory 4 is used to receive the test value of the automatic test equipment 3, output the result value to the automatic test equipment 3 according to the test value to provide the automatic test equipment 3 to judge whether the first-in first-out memory 4 is operating normally, and receive the register of the device under test 2 value, receiving the input value of the automatic test equipment 3 , and receiving the selection signal of the automatic test equipment 3 to write the register value or input the value to the device under test 2 .

The device under test 2 is used for outputting the register value to the FIFO memory 4 and receiving the register value or the input value written into the FIFO memory 4 .

Please refer to FIGS. 1 to 3 at the same time. The automatic test equipment method according to an embodiment of the present invention is applicable to the automatic test equipment system 1 . The automatic test equipment method of the present invention includes a FIFO memory test program S1 and a device under test test program S2. Among them, the first-in-first-out memory test program S1 is used to ensure the hardware quality of the first-in first-out memory, and the device under test test program S2 is used to enable the automatic test equipment 3 to communicate with the device under test 2 only once, so that read-modify-write The test time for input operation is reduced by more than 80%, and the programming effort to develop the test program is also reduced, which in turn reduces the test time.

Wherein, the first-in-first-out memory test program S1 includes step S11: receiving the test value of the automatic test equipment 3 through the first-in first-out memory 4, and step S13: outputting the result value to the automatic test equipment 3 through the first-in first-out memory 4 according to the test value An automatic test device 3 is provided to judge whether the FIFO memory 4 is operating normally. If the automatic test equipment 3 judges that the first-in-first-out memory 4 is operating normally, then carry out the device under test test procedure S2; Avoid wasting testing time.

The device under test test program S2 includes step S21: receiving the register value of the device under test 2 through the first-in-first-out memory 4, step S23: receiving the input value of the automatic test equipment 3 through the first-in-first-out memory 4, and step S25: through the first-in-first-out memory 4 The output memory 4 receives the selection signal of the automatic test equipment 3 to write the register value or input the value to the device under test 2 .

Please refer to FIGS. 1 to 4 , in an example, the FIFO memory 4 includes a shift register 41 and a multiplexer 42, wherein the multiplexer 42 is connected to the shift register 41. In addition, the shift register 41 is used to receive the register value of the device under test 2 . The multiplexer 42 is used for receiving the register value of the shift register 41 , and the input value and selection signal of the automatic test equipment 3 . Preferably, the shift register 41 is a 74HC7731 register, and the multiplexer is a 74HC157 multiplexer, but those skilled in the art can choose different shift registers and multiplexers according to actual needs, so the present invention is not limited thereto.

First, the automatic test equipment 3 outputs a control signal to control the shift register 41 so that the shift register 41 generates a 64-bit long dummy cycle to reset the D flip-flop array in the shift register 41 . Then, the automatic test equipment method of the present invention can be executed, or the device under test test program S2 in the automatic test equipment method of the present invention can be executed.

Wherein, in step S21, the automatic test equipment 3 outputs the control signal to the control pin CPn of the shift register 4 in the FIFO memory 4 to control the shift register 4, so that the shift register 4 in the FIFO memory 4 The register value of the device under test 2 is received through the input pin Dn and sequentially shifted to the D flip-flop array in the shift register 4, and the D flip-flop array is sequentially output through the output pin Qn of the shift register 4 Register values in the array. The multiplexer 42 in the FIFO memory 4 receives the register values sequentially output by the output pin Qn of the shift register 4 through the input pin nI0.

In step S23 , the multiplexer 42 in the FIFO memory 4 receives the input value output by the automatic test equipment 3 through the input pin nI1 .

In step S25, the multiplexer 42 in the FIFO memory 4 receives the selection signal output by the automatic test equipment 3 through the selection pin S to write the register value through the output pin nY of the multiplexer 42 or input the value to Device under test 2. For example, when the selection signal is 1, the FIFO memory 4 writes the input value to the device under test 2 through the output pin nY of the multiplexer 42 . When the selection signal is 0, the FIFO memory 4 writes the register value to the device under test 2 through the output pin nY of the multiplexer 42 . The value received by the device under test 2 is like a written value.

Please refer to FIGS. 1 to 3 and 5 at the same time. In another example, the first-in-first-out memory 4 preferably includes a 74HC7403 register, and the output pin Qn of the register is connected to the automatic test equipment 3 so that the register value is provided by the register or by The automatic test equipment 3 provides input values to the device under test 2, but those skilled in the art can select different registers according to actual needs, so the present invention is not limited thereto.

In step S21, the automatic test equipment 3 outputs a control signal to the control pin SI of the register in the first-in-first-out memory 4 to control the register, so that the register receives and stores the register value of the device under test 2 sequentially through the input pin Dn, And the automatic test equipment 3 outputs a control signal to the control pin SO of the register to control the register, so that the register sequentially outputs the register values in the register through the input pin Qn.

In step S23, the automatic test equipment 3 is connected to the output pin Qn of the FIFO memory 4 to provide an input value.

In step S25, the automatic test equipment 3 outputs a selection signal to the control pin OE of the register in the FIFO memory 4 to control the register, so that the register enables or disables the output pin Qn, so that when the output pin Qn is enabled When enabled, the first-in-first-out memory 4 provides the register value to the device under test 2, and when the output pin Qn is disabled, the automatic test equipment 3 provides the input value to the device under test 2.

In summary, the automatic test equipment system and the automatic test equipment method provided by the present invention enable the automatic test equipment to communicate with the device under test only once, and reduce the test time of the read-modify-write operation by more than 80%. And the programming effort to develop the test program is also reduced, thereby reducing the test time. In addition, the present invention also provides a test and diagnosis program of the FIFO memory to ensure the hardware quality and high reliability of the FIFO memory.

Claims

An automatic test equipment method is characterized in that it is applicable to an automatic test equipment system, and the automatic test equipment method comprises:

receiving a register value of a device under test through a first-in-first-out memory;

receiving input values from an automatic test equipment via said FIFO memory; and

Through the first-in-first-out memory, a selection signal of the automatic test equipment is received to write the register value or the input value to the device under test.
The automatic test equipment method according to claim 1, further comprising:

receiving test values from the automatic test equipment via the first-in-first-out memory; and

Through the FIFO memory, output a result value to the automatic test equipment according to the test value to provide the automatic test equipment to judge whether the FIFO memory is operating normally.
The automatic test equipment method according to claim 1, wherein the first-in-first-out memory comprises:

a shift register for receiving said register value of said device under test; and

A multiplexer is connected to the shift register and receives the register value, the input value and the selection signal.
3. The automatic test equipment method of claim 3, wherein said shift register generates a 64-bit long dummy cycle to reset said shift register.
The automatic test equipment method according to claim 3, wherein the shift register is 74HC7731, and the multiplexer is 74HC157.
The automatic test equipment method of claim 1, wherein the first-in-first-out memory comprises a 74HC7403.
A kind of automatic test equipment system, it is characterized in that, comprises:

A device under test, used to output register values;

an automatic test equipment for outputting input values; and

A first-in-first-out memory, connected to the device under test and the automatic test equipment, for receiving the register value of the device under test, receiving the input value of the automatic test equipment, and receiving the automatic test equipment The selection signal of the test equipment is used to write the register value or the input value to the device under test.
The automatic test equipment system according to claim 7, wherein the first-in-first-out memory further receives test values of the automatic test equipment, and outputs result values to the automatic test equipment according to the test values to provide The automatic test equipment judges whether the first-in-first-out memory is functioning normally.
The automatic test equipment system according to claim 7, wherein the first-in-first-out memory comprises:

a shift register for receiving said register value of said device under test; and

A multiplexer is connected to the shift register and receives the register value, the input value and the selection signal.
9. The automatic test equipment system of claim 9, wherein said shift register generates a 64-bit long dummy cycle to reset said shift register.
The automatic test equipment system according to claim 9, wherein the shift register is a 74HC7731, and the multiplexer is a 74HC157.
The automatic test equipment system according to claim 7, wherein the first-in-first-out memory comprises a 74HC7403.