WO2022247369A1 - High-reliability in-chip power switching circuit - Google Patents

High-reliability in-chip power switching circuit Download PDF

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Publication number
WO2022247369A1
WO2022247369A1 PCT/CN2022/077864 CN2022077864W WO2022247369A1 WO 2022247369 A1 WO2022247369 A1 WO 2022247369A1 CN 2022077864 W CN2022077864 W CN 2022077864W WO 2022247369 A1 WO2022247369 A1 WO 2022247369A1
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Prior art keywords
switch
power
low
terminal
output
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PCT/CN2022/077864
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French (fr)
Chinese (zh)
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江向阳
林玲
王文泽
丁燕
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杭州万高科技股份有限公司
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Priority to KR1020227042860A priority Critical patent/KR20230100700A/en
Publication of WO2022247369A1 publication Critical patent/WO2022247369A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/263—Arrangements for using multiple switchable power supplies, e.g. battery and AC
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/14—Time supervision arrangements, e.g. real time clock
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the invention relates to a power switching circuit, in particular to a high-reliability on-chip power switching circuit.
  • the power structure of the main control chip is divided into two parts, one is the main power domain, and most functional modules such as CPU, storage, and peripherals are placed in this area; the other is the RTC power domain, which mainly houses the crystal oscillator clock, RTC modules, etc. circuit.
  • the main power domain In addition to entering the RTC-Only mode, the main power domain is always powered. When it is powered by the mains, it is powered by the mains. When there is no mains, it is switched to the battery. Usually, this switching is done outside the chip. Referring to Figure 3, in order to prevent backflow, the mains power (generally passed through the rectifier bridge and then converted by the LDO for power supply) and the battery are each connected in series with a diode to supply the chip power input VDD.
  • the mains power is higher than the battery voltage, so it will be powered by the mains under normal circumstances.
  • this structure also has an irreversible disadvantage, that is, the conduction voltage drop of the diode, which will significantly reduce the battery voltage. of durability.
  • the technical problem to be solved by the present invention is to provide a high-reliability on-chip power switching circuit for the deficiencies of the prior art.
  • the present invention discloses a high-reliability on-chip power switching circuit, including a power detection circuit, a low-power control module, a main power control module, a low-power power switch, a main power switch, Loads in low power consumption areas and loads in main power areas;
  • the input end of the power detection circuit is respectively connected to the mains power supply VDD and the battery power supply BATRTC, and detects the two kinds of power supplies;
  • the power detection circuit has two outputs, one of which is connected to the input terminal of the low-power control module, the output of the low-power control module is connected to the input terminal of the low-power switch, and the output of the low-power switch is connected to the low-power switch. consumption area load;
  • the other output of the power detection circuit is connected to the input end of the main power control module, the output of the main power control module is connected to the input end of the main power switch, and the output of the main power switch is connected to the load in the main power area.
  • the power detection circuit of the present invention includes a first resistor R0, a second resistor R1 and a comparator COMP;
  • the positive terminal of the first resistor R0 is connected to the commercial power supply VDD, and the negative terminal is connected to the positive input terminal of the comparator COMP;
  • the positive terminal of the second resistor R1 is connected to the battery power supply BATRTC, and the negative terminal is connected to the negative input terminal of the comparator COMP.
  • the low power consumption control module of the present invention includes a first inverter INV to generate a non-overlapping control signal;
  • the input end of the first inverter INV is connected to the output end of the comparator COMP, and the output end of the first inverter INV is connected to the low power consumption switch.
  • the main power control module of the present invention includes a two-phase non-overlapping timing generator S1, a second inverter INV1, and a third inverter INV2;
  • the input terminal of the two-phase non-overlapping timing generator S1 is connected to the output terminal LP_SEL of the comparator, and the output of the two-phase non-overlapping timing generator S1 is connected to the input terminals of the second inverter INV1 and the third inverter INV2 ;
  • the output end of the second inverter is connected to the third switch SW2;
  • the output end of the third inverter is connected to the fourth switch SW3.
  • the low power consumption power switching switch of the present invention includes a first switch SW0 and a second switch SW1;
  • the gate terminal of the first switch SW0 is connected to the output terminal of the comparator COMP, the source terminal of the first switch SW0 is connected to the battery power supply BATRTC, the substrate and the drain terminal of the first switch SW0 are connected to the low power consumption area load and the second switch SW1 The drain and substrate;
  • the gate terminal of the second switch SW1 is connected to the output terminal of the first inverter INV, and the source terminal of the second switch SW1 is connected to the commercial power supply VDD.
  • the switching switch of the main power supply in the present invention includes a third switch SW2 and a fourth switch SW3;
  • the gate terminal of the third switch SW2 is connected to the output terminal of the main power control module, the source terminal of the third switch SW2 is connected to the battery power supply BATRTC, and the substrate and drain terminal of the third switch SW2 are connected to the main power area load and the drain terminal of SW3 and Substrate;
  • the gate terminal of the fourth switch SW3 is connected to the main power control module, and the source terminal of the fourth switch SW3 is connected to the commercial power supply VDD.
  • the low power consumption area load of the present invention includes a minimum system working reference voltage generation circuit BGR, a low power consumption reference circuit LPVERF, a clock generation module CLK_GEN and a power-on reset POR module;
  • the load in the main power area includes a main voltage regulator MainLDO, an input and output IO, an analog-to-digital converter ADC and a phase-locked loop PLL module.
  • the first switch SW0 and the second switch SW1 in the present invention are MOS switches
  • the size of the first switch SW0 and the second switch SW1 is set according to the current, so that the on-resistance of the switches is the largest when the load in the low power consumption region works normally.
  • the control signals of the first switch SW0 and the second switch SW1 in the present invention are non-overlapping signals, which are generated by the low power consumption control module.
  • the first resistor R0 and the second resistor R1 are electrostatic protection ESD resistors to prevent the gate terminal of the comparator COMP from being damaged.
  • the high-reliability on-chip power switching circuit proposed by the present invention does not require external diodes for power switching, and the power switching circuit is completed in the chip, reducing BOM costs;
  • the high-reliability on-chip power switching circuit proposed by the present invention does not have an external diode, and the battery’s durability will not be reduced due to the voltage drop of the diode;
  • the internal high-current switch adopts non-overlapping control sequence to ensure that the high-current switches will not be turned on at the same time, avoiding the large current backflow of VDD to the battery, thereby avoiding the reduction of battery life , and the internal needs to be normally open, etc. to ensure that the smallest system part adopts an either-or design to ensure the reliability of internal conduction.
  • Fig. 1 is a schematic diagram of the circuit module of the present invention.
  • Fig. 2 is a schematic circuit diagram of the present invention.
  • FIG. 3 is a schematic diagram of a traditional power switching circuit.
  • FIG. 4 is a schematic diagram of an existing on-chip power switching circuit.
  • Fig. 5 is a schematic circuit diagram of the main electric control module.
  • the invention divides the system power supply into two voltage domains, a low power consumption area and a high power consumption area. Place the power switching module and modules such as the bandgap reference-BGR, power-on reset-POR, and RCOSC in the low power domain ), and put those high-power, power insensitive main voltage regulator (Main low dropout regulator-MAIN LDO), input and output PAD (Input/Output-IO), phase-locked loop (Phase Locked Loop-PLL) and other modules in the Main Power Domain.
  • the power switching module and modules such as the bandgap reference-BGR, power-on reset-POR, and RCOSC in the low power domain ), and put those high-power, power insensitive main voltage regulator (Main low dropout regulator-MAIN LDO), input and output PAD (Input/Output-IO), phase-locked loop (Phase Locked Loop-PLL) and other modules in the Main Power Domain.
  • the main power supply is input to VDD, and the battery is input to BATRTC to generate a low power consumption power supply VDDLP through MOS switches SW1 and SW0.
  • the size of the switch SW0 and the switch SW1 is designed according to the magnitude of the current.
  • control signals LP_SEL and LP_SELN of SW0 and SW1 are designed to be non-overlapping, so that no matter what the output result of the comparator COMP is, All the way power supply is selected.
  • R0 and R1 are ESD protection resistors to prevent the gate terminal (GATE) of the comparator COMP from being damaged.
  • the two-phase non-overlapping control signals LP_SEL and LP_SELN are directly generated by an inverter INV.
  • the above-mentioned generating circuit is only one implementation manner, and non-overlapping control logic can be generated in other implementation manners.
  • the comparator output LP_SEL is high level and LPSELN is low level, SW1 is turned on, SW0 is turned off, and the Low Power part is powered through VDD; when VDD ⁇ BATRTC, the comparator output is low, SW0 is turned on, SW1 is closed, and the Low Power part is powered through BATRTC. Because the two phases of LP_SEL and LP_SELN are non-overlapping, when the control logic changes, LP_SEL and LP_SELN are low at the same time, and SW0 and SW1 are turned on at the same time to ensure the reliability of the control logic.
  • the on-resistance of the switches SW0 and SW1 is relatively large, the current poured by the main power supply to the battery is relatively small, and the loss to the battery is relatively small. Because the current in the Mian area is relatively large, the design requires that the on-resistance of SW2 and SW3 be as small as possible. If SW2 and SW3 are turned on at the same time, a very large backflow current will be generated.
  • the function of Control Logic is to realize the two-phase overlapping clock, so that SW2 and SW3 will not be turned on at the same time, so as to avoid the large current backflow of VDD to BATRTC.
  • VDD>BATRTC the output of the comparator is high, SW3 is turned on, SW2 is turned off, and power is supplied to the Main Power part through VDD; Main Power is partially powered.
  • a high-reliability on-chip power switching circuit includes a power detection circuit, a low-power control module, a main power control module, a low-power power switch, a main power switch, and a low-power area Load and load in the main power area; wherein, the input terminals of the power detection circuit are respectively connected to the mains power supply VDD and the battery power supply BATRTC, and detect the two power sources; the power detection circuit has two outputs, one of which is connected to the low-power The input terminal of the control module and the output of the low-power control module are connected to the input terminal of the low-power power switch, and the output of the low-power switch is connected to the load in the low-power area; the other output of the power detection circuit is connected to the main power control The input end of the module and the output of the main power control module are connected to the input end of the main power switch, and the output of the main power switch is connected to the load in the main power area.
  • the power detection circuit includes a first resistor R0, a second resistor R1, and a comparator COMP; wherein, the positive terminal of the first resistor R0 is connected to the commercial power supply VDD, and the negative terminal is connected to the positive terminal of the comparator COMP. Input terminal; the positive terminal of the second resistor R1 is connected to the battery power supply BATRTC, and the negative terminal is connected to the negative input terminal of the comparator COMP.
  • the low power consumption control module includes a first inverter INV to generate a non-overlapping control signal; wherein, the input terminal of the first inverter INV is connected to the output terminal of the comparator COMP, and the output terminal of the first inverter INV Connect a low-power power toggle switch.
  • the main power control module includes a two-phase non-overlapping timing generator S1, a second inverter INV1 and a third inverter INV2; wherein, the input of the two-phase non-overlapping timing generator S1 terminal is connected to the output terminal LP_SEL of the comparator, the output SELN of the two-phase non-overlapping timing generator S1 is connected to the input terminal of the second inverter INV1, and the other output SEL of S1 is connected to the input terminal of the third inverter INV2;
  • the output terminal MAIN-SEL of the second inverter is connected to the third switch SW2; the output terminal MAIN-SELN of the third inverter is connected to the fourth switch SW3.
  • the low power consumption power switch includes a first switch SW0 and a second switch SW1; wherein, the gate terminal of the first switch SW0 is connected to the output terminal of the comparator COMP, the source terminal of the first switch SW0 is connected to the battery power supply BATRTC, and the first switch SW0 is connected to the battery power supply BATRTC.
  • the substrate and drain of the switch SW0 are connected to the load in the low power consumption area and the drain and the substrate of the second switch SW1; the gate of the second switch SW1 is connected to the output terminal LP_SELN of the first inverter INV, and the second switch SW1
  • the source terminal is connected to the commercial power supply VDD.
  • the main power supply switching switch includes a third switch SW2 and a fourth switch SW3; wherein the gate terminal of the third switch SW2 is connected to the output terminal of the main power control module, the source terminal of the third switch SW2 is connected to the battery power supply BATRTC, and the third switch SW2
  • the substrate and drain of SW2 are connected to the load in the main power area and the drain and substrate of SW3; the gate of the fourth switch SW3 is connected to the main power control module, and the source of the fourth switch SW3 is connected to the commercial power supply VDD.
  • the low-power area load includes the minimum system operating reference voltage generation circuit BGR, the low-power reference circuit LPVERF, the clock generation module CLK_GEN, and the power-on reset POR module;
  • the main power area load includes the main voltage regulator MainLDO, input and output IO, analog-to-digital converter ADC and phase-locked loop PLL module.
  • the first switch SW0 and the second switch SW1 are MOS switches; the size of the first switch SW0 and the second switch SW1 is set according to the current, so that the on-resistance of the switches is the largest when the load in the low power consumption region works normally.
  • the control signals of the first switch SW0 and the second switch SW1 are non-overlapping signals, which are generated by the low power consumption control module.
  • the first resistor R0 and the second resistor R1 in the circuit are electrostatic protection ESD resistors to prevent the gate terminal of the comparator COMP from being damaged.
  • the present invention provides an idea and method of a high-reliability on-chip power switching circuit. There are many methods and approaches for realizing the technical solution. The above description is only a preferred implementation mode of the present invention. Those of ordinary skill may make some improvements and modifications without departing from the principle of the present invention, and these improvements and modifications shall also be regarded as the protection scope of the present invention. All components that are not specified in this embodiment can be realized by existing technologies.

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Abstract

Disclosed in the present invention is a high-reliability in-chip power supply switching circuit, comprising a power supply detection circuit, a low-power-consumption control module, a main power supply control module, a low-power-consumption power supply transfer switch, a main power supply transfer switch, a low-power-consumption area load, and a main power supply area load; wherein an input end of the power supply detection circuit is respectively connected to a mains electricity supply and a battery power supply, and detects the two power supplies; one output path of the power supply detection circuit is connected to an input end of the low-power-consumption control module, an output of the low-power-consumption control module is connected to an input end of the low-power-consumption power supply transfer switch, and an output of the low-power-consumption power supply transfer switch is connected to the low-power-consumption area load; the other output path is connected to an input end of the main power supply control module, an output of the main power supply control module is connected to an input end of the main power supply transfer switch, and an output of the main power supply transfer switch is connected to the main power supply area load.

Description

一种高可靠性片内电源切换电路A high-reliability on-chip power switching circuit 技术领域technical field
本发明涉及一种电源切换电路，特别是一种高可靠性片内电源切换电路。The invention relates to a power switching circuit, in particular to a high-reliability on-chip power switching circuit.
背景技术Background technique
主控芯片电源架构上划分为两块，一块主电源域，CPU、存储、外设等大部分功能模块都放在这个区域；另一块RTC电源域，主要放晶振时钟、RTC模块等需要常开的电路。除了进入RTC-Only模式，主电源域一直保持有电，由市电时由市电供电，没有市电时则切换到电池供电，通常这个切换是在芯片外部完成。参见图3，为了防止倒灌，市电(一般经过整流桥后再由LDO转换后进行供电)和电池各自串接一个二极管再供给芯片电源输入VDD。一般，市电高于电池电压，所以正常情况下都会由市电进行供电，但是这个结构除了二极管的BOM成本，还有一个无法消除的弊端，即二极管的导通压降，这将显著降低电池的耐用度。The power structure of the main control chip is divided into two parts, one is the main power domain, and most functional modules such as CPU, storage, and peripherals are placed in this area; the other is the RTC power domain, which mainly houses the crystal oscillator clock, RTC modules, etc. circuit. In addition to entering the RTC-Only mode, the main power domain is always powered. When it is powered by the mains, it is powered by the mains. When there is no mains, it is switched to the battery. Usually, this switching is done outside the chip. Referring to Figure 3, in order to prevent backflow, the mains power (generally passed through the rectifier bridge and then converted by the LDO for power supply) and the battery are each connected in series with a diode to supply the chip power input VDD. Generally, the mains power is higher than the battery voltage, so it will be powered by the mains under normal circumstances. However, in addition to the BOM cost of the diode, this structure also has an irreversible disadvantage, that is, the conduction voltage drop of the diode, which will significantly reduce the battery voltage. of durability.
为了节约BOM成本，现在有方案将电源切换放到芯片内部实现，如图4所示，通过内部两个开关直接实现电源的切换，既能解决BOM成本增加的问题，也能解决二极管导通压降的问题。In order to save BOM cost, there is now a solution to put the power switching inside the chip, as shown in Figure 4, the power switching is directly realized through two internal switches, which can not only solve the problem of increasing BOM cost, but also solve the problem of diode conduction voltage. drop problem.
但是这个设计可靠性很难保证，当电池电源控制信号VBAT_SEL和市电电源控制信号VDD_SEL做成交叠时序，会出现VDDRTC电压下降导致系统复位；如果VBAT_SEL和VDD_SEL做成非交叠时许，会存在SW0和SW1同时导通的可能性，因为SW0和SW1流过的电流比较大，通常10mA以上，这样要求SW0和SW1的导通阻抗做的比较小，而VDD和BATRTC电压差存在非常大的情况，这样会导致VDD的电源有一个非常大的倒灌到电池中，导致电池的损伤，影响电池寿命。However, the reliability of this design is difficult to guarantee. When the battery power control signal VBAT_SEL and the mains power control signal VDD_SEL are overlapped, the VDDRTC voltage will drop and the system will be reset; if VBAT_SEL and VDD_SEL are not overlapped, there will be The possibility of SW0 and SW1 being turned on at the same time, because the current flowing through SW0 and SW1 is relatively large, usually more than 10mA, so the on-resistance of SW0 and SW1 is required to be relatively small, and the voltage difference between VDD and BATRTC is very large. , This will cause a very large backflow of the VDD power supply into the battery, causing damage to the battery and affecting battery life.
发明内容Contents of the invention
发明目的：本发明所要解决的技术问题是针对现有技术的不足，提供一种高可靠性片内电源切换电路。Purpose of the invention: The technical problem to be solved by the present invention is to provide a high-reliability on-chip power switching circuit for the deficiencies of the prior art.
为了解决上述技术问题，本发明公开了一种高可靠性片内电源切换电路，包括电源检测电路、低功耗控制模块、主电控制模块、低功耗电源切换开关、主电电源切换开关、低功耗区域负载以及主电区域负载；In order to solve the above technical problems, the present invention discloses a high-reliability on-chip power switching circuit, including a power detection circuit, a low-power control module, a main power control module, a low-power power switch, a main power switch, Loads in low power consumption areas and loads in main power areas;
其中，电源检测电路输入端分别连接市电电源VDD和电池电源BATRTC，并对所述两种电源进行检测；Wherein, the input end of the power detection circuit is respectively connected to the mains power supply VDD and the battery power supply BATRTC, and detects the two kinds of power supplies;
电源检测电路有两路输出，其中一路输出连接低功耗控制模块的输入端，低功耗控制模块的输出连接低功耗电源切换开关的输入端，低功耗电源切换开关的输出连接低功耗区域负载；The power detection circuit has two outputs, one of which is connected to the input terminal of the low-power control module, the output of the low-power control module is connected to the input terminal of the low-power switch, and the output of the low-power switch is connected to the low-power switch. consumption area load;
电源检测电路的另一路输出连接主电控制模块的输入端，主电控制模块的输出连接主电电源切换开关的输入端，主电电源切换开关的输出连接主电区域负载。The other output of the power detection circuit is connected to the input end of the main power control module, the output of the main power control module is connected to the input end of the main power switch, and the output of the main power switch is connected to the load in the main power area.
本发明所述电源检测电路包括第一电阻R0、第二电阻R1和比较器COMP；The power detection circuit of the present invention includes a first resistor R0, a second resistor R1 and a comparator COMP;
其中，第一电阻R0的正端连接市电电源VDD，负端连接比较器COMP的正向输入端；Wherein, the positive terminal of the first resistor R0 is connected to the commercial power supply VDD, and the negative terminal is connected to the positive input terminal of the comparator COMP;
第二电阻R1的正端连接电池电源BATRTC，负端连接比较器COMP的负向输入端。The positive terminal of the second resistor R1 is connected to the battery power supply BATRTC, and the negative terminal is connected to the negative input terminal of the comparator COMP.
本发明所述低功耗控制模块包括第一反相器INV，产生非交叠控制信号；The low power consumption control module of the present invention includes a first inverter INV to generate a non-overlapping control signal;
其中，第一反相器INV的输入端连接比较器COMP的输出端，第一反相器INV的输出端连接低功耗电源切换开关。Wherein, the input end of the first inverter INV is connected to the output end of the comparator COMP, and the output end of the first inverter INV is connected to the low power consumption switch.
本发明所述主电控制模块包括两相非交叠时序产生器S1和第二反相器INV1和第三反相器INV2；The main power control module of the present invention includes a two-phase non-overlapping timing generator S1, a second inverter INV1, and a third inverter INV2;
其中，两相非交叠时序产生器S1的输入端连接比较器的输出端LP_SEL，两相非交叠时序产生器S1的输出连接第二反相器INV1和第三反相器INV2的输入端；Wherein, the input terminal of the two-phase non-overlapping timing generator S1 is connected to the output terminal LP_SEL of the comparator, and the output of the two-phase non-overlapping timing generator S1 is connected to the input terminals of the second inverter INV1 and the third inverter INV2 ;
第二反相器输出端连接第三开关SW2；The output end of the second inverter is connected to the third switch SW2;
第三反相器输出端连接第四开关SW3。The output end of the third inverter is connected to the fourth switch SW3.
本发明所述低功耗电源切换开关包括第一开关SW0和第二开关SW1；The low power consumption power switching switch of the present invention includes a first switch SW0 and a second switch SW1;
其中，第一开关SW0的栅端连接比较器COMP的输出端，第一开关SW0的源端连接电池电源BATRTC，第一开关SW0的衬底和漏端连接低功耗区域负载和第二开关SW1的漏端和衬底；Wherein, the gate terminal of the first switch SW0 is connected to the output terminal of the comparator COMP, the source terminal of the first switch SW0 is connected to the battery power supply BATRTC, the substrate and the drain terminal of the first switch SW0 are connected to the low power consumption area load and the second switch SW1 The drain and substrate;
第二开关SW1的栅端连接第一反相器INV的输出端，第二开关SW1的源端连接市电电源VDD。The gate terminal of the second switch SW1 is connected to the output terminal of the first inverter INV, and the source terminal of the second switch SW1 is connected to the commercial power supply VDD.
本发明所述主电电源切换开关包括第三开关SW2和第四开关SW3；The switching switch of the main power supply in the present invention includes a third switch SW2 and a fourth switch SW3;
其中第三开关SW2的栅端连接主电控制模块的输出端，第三开关SW2的源端连接 电池电源BATRTC，第三开关SW2的衬底和漏端连接主电区域负载和SW3的漏端和衬底；The gate terminal of the third switch SW2 is connected to the output terminal of the main power control module, the source terminal of the third switch SW2 is connected to the battery power supply BATRTC, and the substrate and drain terminal of the third switch SW2 are connected to the main power area load and the drain terminal of SW3 and Substrate;
第四开关SW3的栅端连主电控制模块，第四开关SW3的源端接市电电源VDD。The gate terminal of the fourth switch SW3 is connected to the main power control module, and the source terminal of the fourth switch SW3 is connected to the commercial power supply VDD.
本发明所述低功耗区域负载包括最小系统工作参考电压产生电路BGR、低功耗参考电路LPVERF、时钟产生模块CLK_GEN和上电复位POR模块；The low power consumption area load of the present invention includes a minimum system working reference voltage generation circuit BGR, a low power consumption reference circuit LPVERF, a clock generation module CLK_GEN and a power-on reset POR module;
所述主电区域负载包括主稳压源MainLDO、输入输出IO、模数转换器ADC和锁相环PLL模块。The load in the main power area includes a main voltage regulator MainLDO, an input and output IO, an analog-to-digital converter ADC and a phase-locked loop PLL module.
本发明所述第一开关SW0和第二开关SW1为MOS开关；The first switch SW0 and the second switch SW1 in the present invention are MOS switches;
第一开关SW0和第二开关SW1的尺寸根据电流设置，使低功耗区域负载正常工作时所述开关的导通阻抗最大。The size of the first switch SW0 and the second switch SW1 is set according to the current, so that the on-resistance of the switches is the largest when the load in the low power consumption region works normally.
本发明所述第一开关SW0和第二开关SW1的控制信号为非交叠信号，由低功耗控制模块产生。The control signals of the first switch SW0 and the second switch SW1 in the present invention are non-overlapping signals, which are generated by the low power consumption control module.
本发明所述电路中第一电阻R0和第二电阻R1是静电防护ESD电阻，防止比较器COMP的栅端被损伤。In the circuit of the present invention, the first resistor R0 and the second resistor R1 are electrostatic protection ESD resistors to prevent the gate terminal of the comparator COMP from being damaged.
有益效果：Beneficial effect:
1、本发明提出的高可靠性片内电源切换电路，不需要外部增加电源切换的二极管，电源切换电路在芯片内完成，降低BOM成本；1. The high-reliability on-chip power switching circuit proposed by the present invention does not require external diodes for power switching, and the power switching circuit is completed in the chip, reducing BOM costs;
2、本发明提出的高可靠性片内电源切换电路，没有外部二极管，不会出现因为二极管的压降降低电池的耐用度；2. The high-reliability on-chip power switching circuit proposed by the present invention does not have an external diode, and the battery’s durability will not be reduced due to the voltage drop of the diode;
3、本发明提出的高可靠性片内电源切换电路，内部大电流开关采用非交叠控制时序保证大电流开关不会同时导通，避免了VDD对电池的大电流倒灌，从而避免降低电池寿命，而内部需要常开等保证最小系统部分采用非此即彼的设计，保证内部导通的可靠。3. In the high-reliability on-chip power switching circuit proposed by the present invention, the internal high-current switch adopts non-overlapping control sequence to ensure that the high-current switches will not be turned on at the same time, avoiding the large current backflow of VDD to the battery, thereby avoiding the reduction of battery life , and the internal needs to be normally open, etc. to ensure that the smallest system part adopts an either-or design to ensure the reliability of internal conduction.
附图说明Description of drawings
下面结合附图和具体实施方式对本发明做更进一步的具体说明，本发明的上述和/或其他方面的优点将会变得更加清楚。The advantages of the above and/or other aspects of the present invention will become clearer as the present invention will be further described in detail in conjunction with the accompanying drawings and specific embodiments.
图1为本发明电路模块示意图。Fig. 1 is a schematic diagram of the circuit module of the present invention.
图2为本发明电路示意图。Fig. 2 is a schematic circuit diagram of the present invention.
图3为传统电源切换电路示意图。FIG. 3 is a schematic diagram of a traditional power switching circuit.
图4为现有片内电源切换电路示意图。FIG. 4 is a schematic diagram of an existing on-chip power switching circuit.
图5为主电控制模块电路示意图。Fig. 5 is a schematic circuit diagram of the main electric control module.
具体实施方式Detailed ways
本发明将系统电源分成两个电压域，低功耗和高功耗区域。将电源切换模块以及保证最小系统工作参考电压产生电路(Bandgap Reference-BGR)、上电复位(Power On Reset-POR)、电阻电容振荡器(RCOSC)等模块放在低功耗区域(low power domain)，而把那些大功率、电源不敏感主稳压源(Main low dropout regulator-MAIN LDO)、输入输出PAD(Input/Output-IO)、锁相环(Phase Locked Loop-PLL)等模块放在Main Power Domain。The invention divides the system power supply into two voltage domains, a low power consumption area and a high power consumption area. Place the power switching module and modules such as the bandgap reference-BGR, power-on reset-POR, and RCOSC in the low power domain ), and put those high-power, power insensitive main voltage regulator (Main low dropout regulator-MAIN LDO), input and output PAD (Input/Output-IO), phase-locked loop (Phase Locked Loop-PLL) and other modules in the Main Power Domain.
低功耗区域通过将主电源输入VDD，电池输入BATRTC通过MOS开关SW1和SW0来产生低功耗供电电源VDDLP。设计中，根据电流大小设计开关SW0和开关SW1的尺寸，主要原则是保证Low Power Domain各模块正常工作同时开关的导通阻抗最大。例如当low power domain所有模块电流在10uA时候，所有模块最低供电电压1.8V，要求电池或主电源2V系统正常，则设计SW0和SW1的导通阻抗(2-1.8)/10u＝20k。为了保证VDDLP电源常开,不会因为电源切换导致切换逻辑没电导致VDDLP掉电或者电压下降太多，设计SW0和SW1的控制信号LP_SEL和LP_SELN非交叠，使得不管比较器COMP输出结果什么，都有一路电源被选择。上述电路中R0、R1是ESD保护电阻，防止比较器COMP的栅端(GATE)被损伤。两相非交叠控制信号LP_SEL和LP_SELN直接通过一个反相器INV产生，上述产生电路只是其中一种实现方式，可以别的实现方式产生非交叠控制逻辑。当VDD>BATRTC时候，比较器输出LP_SEL为高电平LPSELN为低电平，SW1导通，SW0关闭，通过VDD给Low Power部分供电；当VDD<BATRTC时，比较器输出低，SW0导通，SW1关闭，通过BATRTC给Low Power部分供电，因为LP_SEL和LP_SELN两相非交叠，所以存在控制逻辑发生变化时LP_SEL和LP_SELN同时为低，SW0和SW1同时导通，保证控制逻辑的可靠性，由于开关SW0和SW1的导通阻抗比较大，主电源对电池倒灌的电流比较小，对电池的损失比较小。因为Mian区域的电流比较大，所以设计要求SW2和SW3的导通电阻尽量小，如果SW2和SW3同时导通，将会产生非常大的倒灌电流。Control Logic作用 是实现两相交叠时钟，使得SW2和SW3不会同时导通，避免VDD对BATRTC的大电流倒灌。同理，当VDD>BATRTC时候，比较器输出高，SW3导通，SW2关闭，通过VDD给Main Power部分供电；当VDD<BATRTC时，比较器输出低，SW2导通，SW3关闭，通过BATRTC给Main Power部分供电。In the low power consumption area, the main power supply is input to VDD, and the battery is input to BATRTC to generate a low power consumption power supply VDDLP through MOS switches SW1 and SW0. In the design, the size of the switch SW0 and the switch SW1 is designed according to the magnitude of the current. The main principle is to ensure that each module of the Low Power Domain works normally and the on-resistance of the switch is the largest. For example, when the current of all modules in the low power domain is 10uA, the minimum power supply voltage of all modules is 1.8V, and the battery or main power supply is required to be normal at 2V, then design the on-resistance of SW0 and SW1 (2-1.8)/10u=20k. In order to ensure that the VDDLP power supply is always on, VDDLP will not be powered off or the voltage drops too much due to the power switching and the switching logic will not be powered off. The control signals LP_SEL and LP_SELN of SW0 and SW1 are designed to be non-overlapping, so that no matter what the output result of the comparator COMP is, All the way power supply is selected. In the above circuit, R0 and R1 are ESD protection resistors to prevent the gate terminal (GATE) of the comparator COMP from being damaged. The two-phase non-overlapping control signals LP_SEL and LP_SELN are directly generated by an inverter INV. The above-mentioned generating circuit is only one implementation manner, and non-overlapping control logic can be generated in other implementation manners. When VDD>BATRTC, the comparator output LP_SEL is high level and LPSELN is low level, SW1 is turned on, SW0 is turned off, and the Low Power part is powered through VDD; when VDD<BATRTC, the comparator output is low, SW0 is turned on, SW1 is closed, and the Low Power part is powered through BATRTC. Because the two phases of LP_SEL and LP_SELN are non-overlapping, when the control logic changes, LP_SEL and LP_SELN are low at the same time, and SW0 and SW1 are turned on at the same time to ensure the reliability of the control logic. The on-resistance of the switches SW0 and SW1 is relatively large, the current poured by the main power supply to the battery is relatively small, and the loss to the battery is relatively small. Because the current in the Mian area is relatively large, the design requires that the on-resistance of SW2 and SW3 be as small as possible. If SW2 and SW3 are turned on at the same time, a very large backflow current will be generated. The function of Control Logic is to realize the two-phase overlapping clock, so that SW2 and SW3 will not be turned on at the same time, so as to avoid the large current backflow of VDD to BATRTC. Similarly, when VDD>BATRTC, the output of the comparator is high, SW3 is turned on, SW2 is turned off, and power is supplied to the Main Power part through VDD; Main Power is partially powered.
如图1所示，一种高可靠性片内电源切换电路，包括电源检测电路、低功耗控制模块、主电控制模块、低功耗电源切换开关、主电电源切换开关、低功耗区域负载以及主电区域负载；其中，电源检测电路输入端分别连接市电电源VDD和电池电源BATRTC，并对所述两种电源进行检测；电源检测电路有两路输出，其中一路输出连接低功耗控制模块的输入端，低功耗控制模块的输出连接低功耗电源切换开关的输入端，低功耗电源切换开关的输出连接低功耗区域负载；电源检测电路的另一路输出连接主电控制模块的输入端，主电控制模块的输出连接主电电源切换开关的输入端，主电电源切换开关的输出连接主电区域负载。As shown in Figure 1, a high-reliability on-chip power switching circuit includes a power detection circuit, a low-power control module, a main power control module, a low-power power switch, a main power switch, and a low-power area Load and load in the main power area; wherein, the input terminals of the power detection circuit are respectively connected to the mains power supply VDD and the battery power supply BATRTC, and detect the two power sources; the power detection circuit has two outputs, one of which is connected to the low-power The input terminal of the control module and the output of the low-power control module are connected to the input terminal of the low-power power switch, and the output of the low-power switch is connected to the load in the low-power area; the other output of the power detection circuit is connected to the main power control The input end of the module and the output of the main power control module are connected to the input end of the main power switch, and the output of the main power switch is connected to the load in the main power area.
如图2所示，所述电源检测电路包括第一电阻R0、第二电阻R1和比较器COMP；其中，第一电阻R0的正端连接市电电源VDD，负端连接比较器COMP的正向输入端；第二电阻R1的正端连接电池电源BATRTC，负端连接比较器COMP的负向输入端。所述低功耗控制模块包括第一反相器INV，产生非交叠控制信号；其中，第一反相器INV的输入端连接比较器COMP的输出端，第一反相器INV的输出端连接低功耗电源切换开关。As shown in Figure 2, the power detection circuit includes a first resistor R0, a second resistor R1, and a comparator COMP; wherein, the positive terminal of the first resistor R0 is connected to the commercial power supply VDD, and the negative terminal is connected to the positive terminal of the comparator COMP. Input terminal; the positive terminal of the second resistor R1 is connected to the battery power supply BATRTC, and the negative terminal is connected to the negative input terminal of the comparator COMP. The low power consumption control module includes a first inverter INV to generate a non-overlapping control signal; wherein, the input terminal of the first inverter INV is connected to the output terminal of the comparator COMP, and the output terminal of the first inverter INV Connect a low-power power toggle switch.
如图5所示，所述主电控制模块包括两相非交叠时序产生器S1和第二反相器INV1和第三反相器INV2；其中，两相非交叠时序产生器S1的输入端连接比较器的输出端LP_SEL，两相非交叠时序产生器S1的输出SELN连接第二反相器INV1的输入端,S1的另一个输出SEL连接第三反相器INV2的输入端；第二反相器输出端MAIN-SEL连接第三开关SW2；第三反相器输出端MAIN-SELN连接第四开关SW3。As shown in Figure 5, the main power control module includes a two-phase non-overlapping timing generator S1, a second inverter INV1 and a third inverter INV2; wherein, the input of the two-phase non-overlapping timing generator S1 terminal is connected to the output terminal LP_SEL of the comparator, the output SELN of the two-phase non-overlapping timing generator S1 is connected to the input terminal of the second inverter INV1, and the other output SEL of S1 is connected to the input terminal of the third inverter INV2; The output terminal MAIN-SEL of the second inverter is connected to the third switch SW2; the output terminal MAIN-SELN of the third inverter is connected to the fourth switch SW3.
所述低功耗电源切换开关包括第一开关SW0和第二开关SW1；其中，第一开关SW0的栅端连接比较器COMP的输出端，第一开关SW0的源端连接电池电源BATRTC，第一开关SW0的衬底和漏端连接低功耗区域负载和第二开关SW1的漏端和衬底；第二开关SW1的栅端连接第一反相器INV的输出端LP_SELN，第二开关SW1的源端连接市电电源VDD。The low power consumption power switch includes a first switch SW0 and a second switch SW1; wherein, the gate terminal of the first switch SW0 is connected to the output terminal of the comparator COMP, the source terminal of the first switch SW0 is connected to the battery power supply BATRTC, and the first switch SW0 is connected to the battery power supply BATRTC. The substrate and drain of the switch SW0 are connected to the load in the low power consumption area and the drain and the substrate of the second switch SW1; the gate of the second switch SW1 is connected to the output terminal LP_SELN of the first inverter INV, and the second switch SW1 The source terminal is connected to the commercial power supply VDD.
所述主电电源切换开关包括第三开关SW2和第四开关SW3；其中第三开关SW2的栅端连接主电控制模块的输出端，第三开关SW2的源端连接电池电源BATRTC，第三开关SW2的衬底和漏端连接主电区域负载和SW3的漏端和衬底；第四开关SW3的栅端连主电控制模块，第四开关SW3的源端接市电电源VDD。The main power supply switching switch includes a third switch SW2 and a fourth switch SW3; wherein the gate terminal of the third switch SW2 is connected to the output terminal of the main power control module, the source terminal of the third switch SW2 is connected to the battery power supply BATRTC, and the third switch SW2 The substrate and drain of SW2 are connected to the load in the main power area and the drain and substrate of SW3; the gate of the fourth switch SW3 is connected to the main power control module, and the source of the fourth switch SW3 is connected to the commercial power supply VDD.
所述低功耗区域负载包括最小系统工作参考电压产生电路BGR、低功耗参考电路LPVERF、时钟产生模块CLK_GEN和上电复位POR模块；所述主电区域负载包括主稳压源MainLDO、输入输出IO、模数转换器ADC和锁相环PLL模块。所述第一开关SW0和第二开关SW1为MOS开关；第一开关SW0和第二开关SW1的尺寸根据电流设置，使低功耗区域负载正常工作时所述开关的导通阻抗最大。所述第一开关SW0和第二开关SW1的控制信号为非交叠信号，由低功耗控制模块产生。所述电路中第一电阻R0和第二电阻R1是静电防护ESD电阻，防止比较器COMP的栅端被损伤。The low-power area load includes the minimum system operating reference voltage generation circuit BGR, the low-power reference circuit LPVERF, the clock generation module CLK_GEN, and the power-on reset POR module; the main power area load includes the main voltage regulator MainLDO, input and output IO, analog-to-digital converter ADC and phase-locked loop PLL module. The first switch SW0 and the second switch SW1 are MOS switches; the size of the first switch SW0 and the second switch SW1 is set according to the current, so that the on-resistance of the switches is the largest when the load in the low power consumption region works normally. The control signals of the first switch SW0 and the second switch SW1 are non-overlapping signals, which are generated by the low power consumption control module. The first resistor R0 and the second resistor R1 in the circuit are electrostatic protection ESD resistors to prevent the gate terminal of the comparator COMP from being damaged.
本发明提供了一种高可靠性片内电源切换电路的思路及方法，具体实现该技术方案的方法和途径很多，以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。本实施例中未明确的各组成部分均可用现有技术加以实现。The present invention provides an idea and method of a high-reliability on-chip power switching circuit. There are many methods and approaches for realizing the technical solution. The above description is only a preferred implementation mode of the present invention. Those of ordinary skill may make some improvements and modifications without departing from the principle of the present invention, and these improvements and modifications shall also be regarded as the protection scope of the present invention. All components that are not specified in this embodiment can be realized by existing technologies.

Claims (10)

  1. 一种高可靠性片内电源切换电路，其特征在于，包括电源检测电路、低功耗控制模块、主电控制模块、低功耗电源切换开关、主电电源切换开关、低功耗区域负载以及主电区域负载；A high-reliability on-chip power switching circuit, characterized in that it includes a power detection circuit, a low power consumption control module, a main power control module, a low power power switching switch, a main power switching switch, a low power consumption area load and Load in the main power area;
    其中，电源检测电路输入端分别连接市电电源VDD和电池电源BATRTC，并对所述两种电源进行检测；Wherein, the input end of the power detection circuit is respectively connected to the mains power supply VDD and the battery power supply BATRTC, and detects the two kinds of power supplies;
    电源检测电路有两路输出，其中一路输出连接低功耗控制模块的输入端，低功耗控制模块的输出连接低功耗电源切换开关的输入端，低功耗电源切换开关的输出连接低功耗区域负载；The power detection circuit has two outputs, one of which is connected to the input terminal of the low-power control module, the output of the low-power control module is connected to the input terminal of the low-power switch, and the output of the low-power switch is connected to the low-power switch. consumption area load;
    电源检测电路的另一路输出连接主电控制模块的输入端，主电控制模块的输出连接主电电源切换开关的输入端，主电电源切换开关的输出连接主电区域负载。The other output of the power detection circuit is connected to the input end of the main power control module, the output of the main power control module is connected to the input end of the main power switch, and the output of the main power switch is connected to the load in the main power area.
  2. 根据权利要求1所述的一种高可靠性片内电源切换电路，其特征在于，所述电源检测电路包括第一电阻R0、第二电阻R1和比较器COMP；A high-reliability on-chip power switching circuit according to claim 1, wherein the power detection circuit comprises a first resistor R0, a second resistor R1 and a comparator COMP;
    其中，第一电阻R0的正端连接市电电源VDD，负端连接比较器COMP的正向输入端；Wherein, the positive terminal of the first resistor R0 is connected to the commercial power supply VDD, and the negative terminal is connected to the positive input terminal of the comparator COMP;
    第二电阻R1的正端连接电池电源BATRTC，负端连接比较器COMP的负向输入端。The positive terminal of the second resistor R1 is connected to the battery power supply BATRTC, and the negative terminal is connected to the negative input terminal of the comparator COMP.
  3. 根据权利要求2所述的一种高可靠性片内电源切换电路，其特征在于，所述低功耗控制模块包括第一反相器INV，产生非交叠控制信号；The high-reliability on-chip power switching circuit according to claim 2, wherein the low power consumption control module includes a first inverter INV to generate a non-overlapping control signal;
    其中，第一反相器INV的输入端连接比较器COMP的输出端，第一反相器INV的输出端连接低功耗电源切换开关。Wherein, the input end of the first inverter INV is connected to the output end of the comparator COMP, and the output end of the first inverter INV is connected to the low power consumption switch.
  4. 根据权利要求3所述的一种高可靠性片内电源切换电路，其特征在于，所述主电控制模块包括两相非交叠时序产生器S1和第二反相器INV1和第三反相器INV2；A high-reliability on-chip power switching circuit according to claim 3, wherein the main power control module includes a two-phase non-overlapping timing generator S1, a second inverter INV1 and a third inverter device INV2;
    其中，两相非交叠时序产生器S1的输入端连接比较器的输出端LP_SEL，两相非交叠时序产生器S1的输出连接第二反相器INV1和第三反相器INV2的输入端；Wherein, the input terminal of the two-phase non-overlapping timing generator S1 is connected to the output terminal LP_SEL of the comparator, and the output of the two-phase non-overlapping timing generator S1 is connected to the input terminals of the second inverter INV1 and the third inverter INV2 ;
    第二反相器输出端连接第三开关SW2；The output end of the second inverter is connected to the third switch SW2;
    第三反相器输出端连接第四开关SW3。The output end of the third inverter is connected to the fourth switch SW3.
  5. 根据权利要求4所述的一种高可靠性片内电源切换电路，其特征在于，所述低功耗电源切换开关包括第一开关SW0和第二开关SW1；A high-reliability on-chip power switching circuit according to claim 4, wherein the low-power power switching switch comprises a first switch SW0 and a second switch SW1;
    其中，第一开关SW0的栅端连接比较器COMP的输出端，第一开关SW0的源端 连接电池电源BATRTC，第一开关SW0的衬底和漏端连接低功耗区域负载和第二开关SW1的漏端和衬底；Wherein, the gate terminal of the first switch SW0 is connected to the output terminal of the comparator COMP, the source terminal of the first switch SW0 is connected to the battery power supply BATRTC, the substrate and the drain terminal of the first switch SW0 are connected to the low power consumption area load and the second switch SW1 The drain and substrate;
    第二开关SW1的栅端连接第一反相器INV的输出端，第二开关SW1的源端连接市电电源VDD。The gate terminal of the second switch SW1 is connected to the output terminal of the first inverter INV, and the source terminal of the second switch SW1 is connected to the commercial power supply VDD.
  6. 根据权利要求5所述的一种高可靠性片内电源切换电路，其特征在于，所述主电电源切换开关包括第三开关SW2和第四开关SW3；The high-reliability on-chip power switching circuit according to claim 5, wherein the main power switching switch includes a third switch SW2 and a fourth switch SW3;
    其中第三开关SW2的栅端连接主电控制模块的输出端，第三开关SW2的源端连接电池电源BATRTC，第三开关SW2的衬底和漏端连接主电区域负载和SW3的漏端和衬底；The gate terminal of the third switch SW2 is connected to the output terminal of the main power control module, the source terminal of the third switch SW2 is connected to the battery power supply BATRTC, and the substrate and drain terminal of the third switch SW2 are connected to the main power area load and the drain terminal of SW3 and Substrate;
    第四开关SW3的栅端连主电控制模块，第四开关SW3的源端接市电电源VDD。The gate terminal of the fourth switch SW3 is connected to the main power control module, and the source terminal of the fourth switch SW3 is connected to the commercial power supply VDD.
  7. 根据权利要求6所述的一种高可靠性片内电源切换电路，其特征在于，所述低功耗区域负载包括最小系统工作参考电压产生电路BGR、低功耗参考电路LPVERF、时钟产生模块CLK_GEN和上电复位POR模块；A high-reliability on-chip power switching circuit according to claim 6, wherein the load in the low-power consumption area includes a minimum system operating reference voltage generation circuit BGR, a low-power consumption reference circuit LPVERF, and a clock generation module CLK_GEN and power-on reset POR module;
    所述主电区域负载包括主稳压源MainLDO、输入输出IO、模数转换器ADC和锁相环PLL模块。The load in the main power area includes a main voltage regulator MainLDO, an input and output IO, an analog-to-digital converter ADC and a phase-locked loop PLL module.
  8. 根据权利要求7所述的一种高可靠性片内电源切换电路，其特征在于，所述第一开关SW0和第二开关SW1为MOS开关；The high-reliability on-chip power switching circuit according to claim 7, wherein the first switch SW0 and the second switch SW1 are MOS switches;
    第一开关SW0和第二开关SW1的尺寸根据电流设置，使低功耗区域负载正常工作时所述开关的导通阻抗最大。The size of the first switch SW0 and the second switch SW1 is set according to the current, so that the on-resistance of the switches is the largest when the load in the low power consumption region works normally.
  9. 根据权利要求8所述的一种高可靠性片内电源切换电路，其特征在于，所述第一开关SW0和第二开关SW1的控制信号为非交叠信号，由低功耗控制模块产生。The high-reliability on-chip power switching circuit according to claim 8, wherein the control signals of the first switch SW0 and the second switch SW1 are non-overlapping signals and are generated by a low power consumption control module.
  10. 根据权利要求9所述的一种高可靠性片内电源切换电路，其特征在于，所述电路中第一电阻R0和第二电阻R1是静电防护ESD电阻，防止比较器COMP的栅端被损伤。A high-reliability on-chip power switching circuit according to claim 9, wherein the first resistor R0 and the second resistor R1 in the circuit are electrostatic protection ESD resistors to prevent the gate terminal of the comparator COMP from being damaged .
PCT/CN2022/077864 2021-12-28 2022-02-25 High-reliability in-chip power switching circuit WO2022247369A1 (en)

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CN108092403A (en) * 2017-12-28 2018-05-29 上海胤祺集成电路有限公司 Power supply automatic switchover circuit and intelligent electric meter microcontroller chip
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