WO2022246761A1

WO2022246761A1 - Deadlock recovery method and on-chip system

Info

Publication number: WO2022246761A1
Application number: PCT/CN2021/096511
Authority: WO
Inventors: 夏晶; 蔡春晓; 王堃
Original assignee: 华为技术有限公司
Priority date: 2021-05-27
Filing date: 2021-05-27
Publication date: 2022-12-01
Also published as: CN117397214A

Abstract

A deadlock recovery method and an on-chip system, relating to the technical field of chips. The method comprises: when a first node detects that there is a possibility that deadlock occurs in the first node, data, in each slot of a first ring network, the destination of which is not the first ring network enters a reserved cache of a first egress cache area of the first node by means of the first slot. In this way, an empty slot may appear in the first ring network, and data in a first ingress cache area can enter the first ring network, such that data of an egress cache area in a second node can enter the first ingress cache area, data in a second ring network can enter the egress cache area of the second node, and data in the ingress cache area of the second node can enter the second ring network, thereby recovering deadlock by means of such circulation.

Description

Deadlock release method and system on chip

technical field

The present application relates to the field of chip technology, in particular to a deadlock release method and a system on chip.

Background technique

With the continuous development of semiconductor process technology, the size of transistors is continuously reduced, so that a large number of modules can be integrated on a single chip. The interconnection between the nodes, the data transmission between the modules can be carried out through the ring network. Wherein, the module may be a central processing unit (central processing unit, CPU), a double data rate synchronous dynamic random access memory (double data rate synchronous dynamic random access memory, DDR) and the like.

With the expansion of the chip scale, more and more modules need to be connected to the ring, and the chip design has begun to develop from a single ring to multiple rings. That is, there may be multiple rings in a single chip, and connections between the rings are established, so that data transmission can be performed between modules corresponding to different rings in the chip. In addition, the chip system may include multiple chips, and rings on different chips may also establish connections, so that data transmission may also be performed between modules corresponding to rings on different chips.

A ring includes multiple slots, each slot can be connected to a node, and the node is connected to one or more modules. Each node includes an egress buffer and an ingress buffer. When a node needs to send data to other modules, it first sends the data to the entry buffer in the connected node. When the slot connected to the node is empty, the entry buffer sends the data to the slot. Slots transmit data to adjacent downstream slots in a clockwise or counterclockwise direction. When the data is transmitted to the slot of the destination pair, the slot sends the data to the egress buffer of the connected node, and then the module obtains the data in the egress buffer. In this way, the data transmission between the two modules is completed. The two rings can be connected through a bridge. If a module needs to send data to other modules corresponding to the ring, the data needs to be sent to the export buffer in the connected node through the slot at the connection between the two rings, and then It is sent from the egress buffer to the buffer of the bridge, and then enters the ingress buffer of another ring, and then enters another ring, and then the ring transmits the data to the destination.

If a large amount of data is transmitted between multiple rings, the buffer area between the two rings may be full, and there is no vacancy in the slot on the ring. In this way, data transmission cannot be performed between multiple rings, and this situation is usually called a deadlock. The occurrence of deadlock causes data transmission in the chip system to be blocked, thereby affecting the operation of the entire electronic device. Therefore, there is an urgent need for a method for deadlock removal.

Contents of the invention

Embodiments of the present application provide a method, device and system-on-a-chip for deadlock release, so as to overcome the deadlock problem that occurs when multiple rings are interconnected in the related art.

In the first aspect, a deadlock release method is provided, the method is applied to the first node corresponding to the first ring network, the first node is connected to the first slot in the first ring network, the first node and the first slot are connected The second node connection corresponding to the two ring networks, the method includes: detecting that the first node is in a first state, wherein the first state is a state where there is a possibility of deadlock. Controlling the first slot to send the first data in the first ring network to the reserved buffer in the first egress buffer of the first node, wherein the destination of the first data is not a module corresponding to the first ring network. Send the data in the first entry buffer area to the first slot.

In the scheme shown in the embodiment of the present application, when the first node detects that the first node has the possibility of deadlock, it can set the slots in the first ring network to those whose destination is not the first ring network. The data enters the reserved buffer of the first egress buffer of the first node through the first slot. In this way, an empty slot can appear in the first ring network, and the data in the first entry buffer can enter the first ring network. Furthermore, the data in the egress cache in the second node can enter the first ingress cache, the data in the second ring network can enter the egress cache in the second node, and the data in the ingress cache in the second node can Enter the second ring network, and cycle through this to remove the deadlock.

In a possible implementation manner, the data in the first entry buffer needs to be sent to the first slot when the first slot is empty. Specifically, the first slot sends data to the reserved buffer of the first egress buffer in the first clock cycle, then, the first slot is empty during the remaining time of the first clock cycle. Then, the first node may send the data in the first entry buffer area to the first slot in the first clock cycle.

In a possible implementation manner, if the first node cannot send the data in the first entry buffer to the first slot in the first clock cycle, then the first node needs to wait for the first slot to be empty again, Only then can the data in the first entry buffer be sent to the first slot. In this way, it is necessary to ensure that the vacancy is not occupied by data sent by other nodes. Specifically, the following method can be used to realize that the vacancy is not occupied by data sent by other nodes except the first node.

The first node sends a vacancy reservation signal to the first slot. Wherein, the slot reservation signal is used to instruct the first slot to send a slot occupation signal to the second slot in the next clock cycle. The second slot is a downstream slot adjacent to the first slot, and the vacancy occupancy signal is used to indicate that the node connected to the second slot is not allowed to send data to the second slot, and instruct the second slot to send data to the downstream slot adjacent to the second slot Slot occupied signal. In this way, after the slots other than the first slot receive the vacancy occupancy signal, they no longer receive the data sent by the connected nodes, so that the vacancy can be reserved and not occupied.

In this way, at the Nth clock cycle after the first clock cycle, the first slot is empty again, then, within this clock cycle, the first node can send the data in the first entry buffer area to the first slot. Wherein, N is the number of slots in the first ring network.

In a possible implementation, a pre-judgment mechanism may be set in the ring network, and correspondingly, the method for sending data in the first ring network whose destination is not the first ring network to the reserved buffer may be as follows:

The first node sends a deadlock indication signal to the third slot. Wherein, the third slot is an upstream slot adjacent to the first slot, and the deadlock indication signal is used to indicate that the third slot judges that the destination of the first data currently cached is not the module corresponding to the first ring network In this case, an arrival signal is sent to the first slot. Wherein, the arrival signal is used to instruct the first slot to send the first data to the reserved buffer in the first egress buffer of the first node when receiving the first data.

In a possible implementation manner, the method for detecting the possibility of deadlock in the first node may be as follows:

The first node detects that the number of consecutive failures for data in the first entry buffer to enter the first slot is greater than a first threshold.

In a possible implementation manner, the method for detecting the possibility of deadlock in the first node may also be as follows:

The first node detects that the available cache occupancy rate of the first entry cache area is greater than a second threshold.

The first node detects that the available buffer occupancy rate of the first egress buffer area is greater than a third threshold.

In the scheme shown in the embodiment of this application, the above three methods for detecting the possibility of deadlock in the first node can be used in combination, that is, when the first node meets any of the conditions of the above three methods, it can be considered that the first node exists deadlock possibility.

In a possible implementation manner, when detecting that the first node has returned to a state of normal data transmission, the first node may control each slot in the first ring network to return to a normal working state.

In a possible implementation manner, the method for detecting that the first node returns to the state of normal data transmission may be as follows:

The first node detects that the available cache occupancy rate of the first entry cache area is less than a fourth threshold.

The first node detects that the available buffer occupancy rate of the first egress buffer area is less than a fifth threshold.

In the second aspect, a deadlock release method is provided, the method is applied to the first node corresponding to the first ring network, the first node is connected to the first slot in the first ring network, and the first node and the first slot are connected to each other. The second node connection corresponding to the two-ring network, the method includes:

The first node detects that the first node is in a first state, wherein the first state is a state in which deadlock may occur. Sending a vacancy reservation signal to the second slot, and controlling the data buffered in the second slot to enter the reserved buffer corresponding to the first ring network when there is data buffered in the second slot. Wherein, the vacancy reservation signal is used to instruct the second slot to send a vacancy occupancy signal to the adjacent downstream third slot, and the vacancy occupancy signal is used to indicate that the node connected to the third slot is not allowed to send data to the third slot, and to indicate that the third slot is not allowed to send data to the third slot. The three slots send the vacancy occupancy signal to a downstream slot adjacent to the third slot.

In the solution shown in the embodiment of the present application, the data cached in at least one slot in the first ring network can be entered into the reserved cache, so that an empty slot can appear in the first ring network, and the first The data in the ingress buffer can enter the first ring network. Furthermore, the data in the egress cache in the second node can enter the first ingress cache, the data in the second ring network can enter the egress cache in the second node, and the data in the ingress cache in the second node can Enter the second ring network, and cycle through this to remove the deadlock.

In a possible implementation manner, the first ring network belongs to the first chip, the second ring network belongs to the second chip, the first chip further includes a third ring network, and the first ring network further includes a second ring network. Four slots, the fifth slot and the third node, the fifth slot is a downstream slot adjacent to the fourth slot, the fifth slot is connected to the second node, and the second node is connected to the fourth node corresponding to the third ring network . In this case, when the first node has data cached in the second slot, the data cached in the second slot is controlled to enter the reserved cache corresponding to the first ring network, and the reserved cache can be the third node Reserved cache in the egress cache.

In the case that data is buffered in the second slot, a deadlock indication signal is sent to the fourth slot. Wherein, the deadlock indication information is used to instruct the fourth slot to send an arrival signal and data to the fifth slot in the next clock cycle when the fourth slot receives the vacancy occupancy signal and data sent by the adjacent upstream slot, and the arrival signal is used to indicate The fifth slot sends the data to the reserved buffer of the egress buffer of the third node when receiving the data and the arrival signal in one clock cycle.

The first node detects that the number of consecutive failures for data in the first entry buffer to enter the first slot reaches a first threshold.

The first node detects that the occupancy rate of the available cache in the first ingress cache reaches a second threshold.

In a possible implementation manner, when it is detected that the first node returns to the state of normal data transmission, the first node may control each slot in the first ring network to return to the normal working state.

In a possible implementation manner, the method for detecting that the first node returns to the state of normal data transmission may be as follows: the first node detects that the available buffer occupancy rate of the first egress buffer area is less than the fifth threshold.

In a third aspect, a system on chip is provided, the system on chip includes a first ring network and a second ring network, the first ring network includes a first node, and the second ring network includes a second node, The first node is connected to the second node, and the first node is configured to execute the deadlock removal method described in the first aspect or the second aspect.

In the solution shown in the embodiment of the present application, when the first node detects that there is a possibility of deadlock in the first node, it can pass the data whose destination is not the first ring network in each slot of the first ring network The first slot enters the reserved buffer of the first egress buffer of the first node. In this way, an empty slot can appear in the first ring network, and the data in the first entry buffer can enter the first ring network. Furthermore, the data in the egress cache in the second node can enter the first ingress cache, the data in the second ring network can enter the egress cache in the second node, and the data in the ingress cache in the second node can Enter the second ring network, and cycle through this to remove the deadlock.

Description of drawings

FIG. 1 is a schematic diagram of a system-on-a-chip provided by an embodiment of the present application;

FIG. 2 is a schematic diagram of a system-on-a-chip provided by an embodiment of the present application;

FIG. 3 is a schematic diagram of a system-on-a-chip provided by an embodiment of the present application;

FIG. 4 is a flow chart of a deadlock release method provided in an embodiment of the present application;

FIG. 5 is a flowchart of a deadlock release method provided in an embodiment of the present application;

FIG. 6 is a schematic diagram of a system on a chip provided by an embodiment of the present application.

Detailed ways

The embodiment of the present application provides a method for deadlock release, which can be applied in a system on chip (System on Chip, SoC). This application is applicable to any system-on-chip including multiple ring networks. Multiple ring networks can be on different chips or on the same chip. Several SoCs are exemplarily listed below.

The system on chip as shown in Figure 1 comprises a first ring network and a second ring network, the first node of the first ring network and the first slot connection in the first ring network, the first node and the second ring network The second nodes corresponding to the ring network are connected through the ring network connection device, and the ring network connection device includes a buffer zone. Each slot in the ring network is connected to a node, and then the node is connected to a module. The module can be a central processing unit (central processing unit, CPU), a double data rate synchronous dynamic random access memory (DDR), Last level cache (last level cache, LLC), etc.

A deadlock processing module is set in the first node, and a reserved cache is set in the first egress buffer area of the first node. The deadlock removal method provided in the embodiment of the present application may be executed by the deadlock processing module. In a possible implementation, each node connected to other ring networks can be provided with a deadlock processing module and a reserved cache, as shown in Figure 1, both the first node and the second node can be provided with The deadlock processing module and the reserved cache, both of the deadlock processing modules can execute the deadlock removal method provided by the embodiment of the present application.

The system on chip shown in FIG. 2 includes four ring networks, and the four ring networks are located on two chips. FIG. 2 only exemplarily shows the relationship between multiple ring networks, and does not show the nodes and modules connected by slots. Specifically, each ring network and connected nodes and modules can be referred to as shown in FIG. 1 .

The system on chip shown in FIG. 3 includes six ring networks, the six ring networks are located on three chips, and the six ring networks form another ring. FIG. 3 also only exemplarily shows the relationship between multiple ring networks, and does not show the nodes and modules connected by slots. Specifically, each ring network and connected nodes and modules can be referred to as shown in FIG. 1 .

In order to facilitate readers' understanding of this application, some terms involved in this application are explained below.

One, slot

Slot is the storage medium of data on the ring network. Data can be transmitted between the slots, and the data can be transmitted between the slots of the ring network in a clockwise or counterclockwise direction.

2. Node

A node includes an entry buffer and an exit buffer. One side of the node is connected to the slot in the ring network. Among the nodes connected to the ring network, except the nodes connected to other ring networks, all other nodes can be connected to at least one module. The module can be a central processing unit (central processing unit, CPU), double data rate synchronous dynamic random access memory (double data rate synchronous dynamic random access memory, DDR), etc. Among the nodes connected to the ring network, nodes connected to other ring networks are connected to ring network connection devices such as bridges. The ring network connection device includes a cache area.

3. Entry cache

The entry cache is used to cache data.

The source of the data in the entry buffer: the entry cache in the node connected to the module, and the cached data comes from the connected module. The entry cache in the node connected to the ring network connection device, the data in the cache comes from the buffer in the ring network connection device.

Destination of data in the entry cache: the slot connected to the node where the entry cache is located.

4. Export buffer area

The egress buffer is used to cache data.

The source of the data in the export buffer: the slot connected to the node where the export buffer is located.

Destination of the data in the export buffer area: the export buffer in the node connected to the module, the cached data is sent to the connected module. The egress buffer in the node connected to the ring network connection device sends the buffered data to the buffer in the connected ring network connection device.

The following describes the data transmission mechanism in the ring network:

When a module needs to send data to other modules, it first sends the data to the entry buffer of the connected node. Then, in the case that the slot connected to the node is empty, data is sent to the slot. The data carries the identification of the destination (the module that finally processes the data), the identification of the ring network where the destination is located, and the identification of the chip where the destination is located. In the next clock cycle after receiving the data, the slot sends the data to the adjacent downstream slot in a predetermined direction. When the slot corresponding to the destination receives the data, the slot corresponding to the destination sends the data to the egress buffer of the connected node, and the destination can obtain the data in the egress buffer and perform subsequent processing.

When the destination of the data is a module corresponding to another ring network, the data will be transmitted to the first slot (the slot connected to the node connected to the other ring network). After the first slot receives the data, it sends the data to the entry buffer of the connected node. Then the entry buffer is sent to the buffer area of the ring network connection device, and then sent from the buffer to the entry buffer of another node connected to the ring network connection device, and then enters another ring network .

In addition, during the data transmission process, the ring network is also equipped with an in-place pre-judgment mechanism. Specifically, the in-place pre-judgment mechanism can be as follows:

When a slot receives the data sent by the upstream slot, it judges whether the destination of the data is itself according to the identifier of the destination in the data, the identifier of the ring network corresponding to the destination, and the identifier of the chip where the destination is located. The module corresponding to the adjacent downstream slot. If the destination of the data is the module corresponding to its adjacent downstream slot, when the data is sent to the adjacent downstream slot, an arrival (arrival) signal is sent at the same time. When the adjacent downstream slot receives the data and the corresponding arrive signal, it sends the data to the corresponding egress buffer, and the corresponding module acquires the data in the egress buffer for processing.

A method for releasing a deadlock provided in the embodiment of the present application will be described below with reference to FIG. 1 . Referring to Figure 4, the processing flow of the method may include the following steps:

Step 101. Detect that the first node is in a first state, where the first state is a state in which deadlock may occur.

In implementation, the deadlock processing module in the first node can detect the state of the first node based on various parameters. For example, the number of consecutive failures for data in the first entry buffer to enter the first slot, the available cache occupancy rate of the first entry buffer area, and the available cache occupancy rate of the first egress buffer area, etc.

Specifically, when the deadlock detection module detects that the first node meets one or more of the following conditions, it may be considered that the first node is in the first state.

Condition one:

The number of consecutive failures for data in the first entry buffer to enter the first slot is greater than a first threshold. Wherein, the first threshold may be set according to actual conditions, for example, the value range of the first threshold may be between 400 times and 600 times.

Condition two:

The available cache occupancy rate of the first entry cache area is greater than the second threshold. Wherein, the second threshold can be set according to the actual situation. For example, in order to predict the occurrence of deadlock, the second threshold can be set relatively small, such as between 70% and 80%.

Condition three:

The available buffer occupancy rate of the first egress buffer is greater than the third threshold. Wherein, the third threshold can be set according to the actual situation. For example, in order to predict the occurrence of deadlock, the third threshold can be set relatively small, such as between 70% and 80%.

For condition 1, before the data in the first entry cache enters the first slot, the first entry cache needs to send a data sending request to the first slot. If the first slot is already occupied, it cannot receive the data sent by the first entry cache. , the first slot returns a rejection message to the first entry cache. If the first slot is not occupied and can receive the data sent by the first entry cache, a permission message is returned to the first entry cache. Here, the data sending request, the rejection message and the permission message can all be forwarded via the deadlock processing module, therefore, the deadlock processing module can know the quantity of the rejection message and the permission message, and then can use the quantity of the rejection message received continuously as The number of consecutive failures for data in the first entry buffer to enter the first slot.

It should be noted that the above-mentioned rejection messages received continuously means that after receiving a rejection message, the rejection message is received again without receiving the permission message, and the two rejection messages are considered to be received continuously.

For the second condition, the deadlock processing module can detect the occupied available buffer in the first entry buffer according to the preset detection period, and calculate the ratio of the occupied available buffer to the total available buffer in the first entry buffer, and obtain The available cache occupancy of the first entry cache.

For the third condition, the deadlock processing module can detect the occupied available buffer in the first egress buffer according to the preset detection cycle, and calculate the ratio of the occupied available buffer to the total available buffer in the first egress buffer, The available buffer occupancy rate of the first egress buffer area is obtained. Here, the total available buffer of the first egress buffer does not include the reserved buffer specified in the first egress buffer in this application for deadlock release.

Step 102, controlling the first slot to send the first data in the first ring network to the reserved buffer in the first egress buffer of the first node, wherein the destination of the first data is not the first ring The corresponding module of the network.

In implementation, when the ring network is configured with the above-mentioned pre-judgment mechanism in place, the processing of step 102 can be as follows:

The deadlock processing module sends a deadlock indication signal to the third slot, where the third slot is an upstream slot adjacent to the first slot. Specifically, the deadlock processing module can be electrically connected to the third slot, and when the deadlock processing module detects that the first node is in the first state, it sends a deadlock indication signal to the third slot, and the deadlock indication signal It can be a high level signal or a low level signal. For example, when it is not detected that the first node is in the first state, the deadlock processing module can always send a low level signal to the third slot, and when it detects that the first node is in the first state, it starts to send a low level signal to the third slot A high-level signal is sent, and the high-level signal is the above-mentioned deadlock indication signal.

After receiving the deadlock indication information sent by the deadlock processing module, the third slot enters the deadlock release working mode from the normal working mode. In the deadlock release mode, the operation of the third slot is as follows:

The third slot may store the identifier of the first ring network, and if the third slot judges that the identifier of the ring network corresponding to the destination carried in the received first data is not the identifier of the first ring network, then determine the The destination of the first data is not the module corresponding to the first ring network. Then, the third slot sends the first data to the first slot, and at the same time sends an arrive signal.

If the first slot also receives the arrive signal when receiving the first data sent by the third slot, it sends the first data to the reserved buffer of the first egress buffer of the first node.

It should be noted here that, when the first node is not in the first state, the reserved buffer in the first egress buffer is in an inactive state, that is, the slot is not allowed to send data to it. When the first node is in the first state, the reserved buffer area in the first egress buffer area changes from an unopened state to an open state, that is, the first slot is allowed to send data thereto.

What needs to be explained here is that in the deadlock release working mode, as long as the destination of the first data is not the first ring network, regardless of whether the destination is the second ring network, the first data must be in the second ring network. The first slot is sent to the reserved buffer of the egress buffer.

For example, the destination of the first data is the module corresponding to the third ring network, and the third ring network is another ring network connected to the first ring network, and the access to the third ring network does not need to pass through the third ring network. Two ring networks. In this case, relative to changing the route of the first data, it enters the reserved cache of the egress buffer at the first slot, and then enters the second ring network. Of course, the first data will eventually return to the first ring network through the transmission of each slot, and enter the third ring network according to a normal route after the deadlock is released.

Step 103, sending the data in the first entry buffer area to the first slot.

In an implementation, after the first slot sends the first data to the reserved buffer in the first egress buffer, the first ingress buffer of the first node can send the buffered data to the first slot. Because the chip mechanism is different, the timing when the data in the first entry buffer enters the first slot can also be different.

In a possible implementation manner, in the first clock cycle, the first slot sends the buffered data to the reserved buffer of the first egress buffer, and also in the first clock cycle, the first ingress buffer sends the buffered data Send to the first slot.

At the first moment in the first clock cycle, the first slot sends the first data to the reserved buffer in the first egress buffer, then, in the first clock cycle and after the first moment, the first slot One slot is empty. In this case, the first entry cache can send the cached data to the first slot.

In yet another possible implementation manner, in the first clock cycle, the first slot sends the buffered data to the reserved buffer of the first egress buffer, and the first ingress buffer does not send the cached data to the buffer in the first clock cycle If the data is sent to the first slot, then the first entry buffer can send the cached data to the first slot when the first slot is empty again.

In this case, according to the data transmission rules of the ring network, in the next clock cycle of the first clock cycle, the upstream slot adjacent to the first slot sends the buffered data to the first slot, and the downstream slot adjacent to the first slot becomes for vacancies. In order to make the slot only allow the data in the first entry buffer area to enter, it is necessary to restrict that all nodes corresponding to the ring network except the node where the first entry buffer area is located are not allowed to send data to the slot. There are many specific restriction methods, some of which are listed below for illustration:

method one,

When the deadlock processing module detects that the first node is in the first state, it sends a vacancy reservation signal to the first slot, and after the first slot receives the vacancy reservation message, it sends a message to the second slot (the first slot phase The adjacent downstream slot) sends a vacancy occupancy signal, and after receiving the vacancy occupancy signal, the second slot no longer receives data sent by the corresponding node, and the second slot is empty within this clock cycle. In the next clock cycle, the second slot sends a vacancy occupancy signal to the downstream slot adjacent to the second slot. After receiving the vacancy occupancy signal, the downstream slot adjacent to the second slot no longer receives the data sent by the corresponding node. Then, within this clock cycle, the downstream slot adjacent to the second slot is empty. By analogy, until the Nth clock cycle after the first clock cycle, the first slot is empty again, where N is the number of slots in the first ring network. Different from other slots, even if the first slot also receives the vacancy occupancy signal, it allows the first entry buffer to send the buffered data to the first slot.

Method two,

When the deadlock processing module detects that the first node is in the first state, it sends an entry blocking message to each node in the ring network corresponding to the first node except the first node, and after each node receives the entry blocking message, it does not Then send data to the corresponding slot. In this way, the first slot is empty in the first clock cycle, and the second slot (the downstream slot adjacent to the first slot) is empty in the next clock cycle, and the second solt will not be occupied in this clock cycle, and the second slot will not be occupied in the next clock cycle. The downstream slot adjacent to the second slot is empty in one clock cycle, and the downstream slot adjacent to the second slot will not be occupied in this clock cycle. By analogy, until the Nth clock cycle after the first clock cycle, the first slot is empty again, and the first entry buffer can send the cached data to the first slot, where N is the slot in the ring network quantity.

Through the above processing, the data in the first ring network can enter the reserved buffer, so that the first ring network leaves a space, and the data in the first entry buffer can enter the first ring network, and then the second The data in the egress buffer in the node can enter the first ingress buffer, the data in the second ring network can enter the egress buffer in the second node, and the data in the ingress buffer in the second node can enter the second ring In the shape network, the deadlock can be resolved by this cycle.

In the case that the first node is in the first state, the above process can be continuously executed, so that during the period when the first node is in the first state, empty slots will continuously appear in the first ring network, so that the first node The data in the entry buffer of can enter the first ring network.

Until the deadlock processing module in the first node detects that the first node is in the second state, the deadlock processing module controls each slot in the ring network to return to a normal working state, and closes the reserved buffer in the first egress buffer area , does not allow data to enter.

The condition for detecting that the first node is in the second state may be: detecting that the available cache occupancy rate of the first ingress buffer area is less than the fourth threshold, or detecting that the available cache occupancy rate of the first egress buffer area is less than the fifth threshold value. Wherein, the fourth threshold and the fifth threshold can be set according to actual needs, for example, they can be 30% to 40%.

Another deadlock release method provided by the embodiment of the present application will be described below with reference to FIG. 1 . Referring to Figure 5, the processing flow of the method may include the following steps:

Step 201. Detect that the first node is in a first state, where the first state is a state where there is a possibility of deadlock.

In implementation, the deadlock processing module in the first node detects that the first node is in the first state based on various parameters, such as the number of consecutive failures that the data in the first entry buffer area enters the first slot, the first entry buffer area The available cache occupancy rate of , the available cache occupancy rate of the first egress buffer area, etc.

Condition one:

Condition two:

Condition three:

It should be noted that the foregoing rejection messages received continuously mean that after receiving a rejection message, the rejection message is received again without receiving the permission message, and the two rejection messages are considered to be received consecutively.

For the second condition, the deadlock processing module can detect the occupied available buffer in the first entry buffer according to the preset detection period, and calculate the ratio of the occupied available buffer to the total available buffer in the first entry buffer, and obtain Available cache occupancy of the first entry cache.

Step 202: Send a vacancy reservation signal to the second slot, and control the data buffered in the second slot to enter the reserved buffer corresponding to the first ring network when the second slot has data buffered.

In an implementation, when the deadlock processing module detects that the first node is in the first state, it may first enable the reserved buffer in the first egress buffer of the first node. And a vacancy reservation signal may be sent to at least one slot in the first ring network. Wherein, at least one slot may be any slot in the pre-designated first ring network, and the second slot may be any slot in the at least one slot. The deadlock processing module is electrically connected to the at least one slot. The slot reservation signal can be a high level signal or a low level signal.

The data in the second slot cache needs to enter the reserved buffer corresponding to the first ring network, so that an empty slot appears in the first ring network, and then the data in the entry buffer of the first node can enter the first ring network in a ring network. The following describes how the data in the second slot enters the reserved buffer corresponding to the first ring network in combination with different scenarios.

In a possible scenario, the first ring network is connected to at least one ring network, and the ring networks connected to the first ring network are all in the same chip as the first ring network, or in different chips. The nodes connected to the first ring network and each ring network may be provided with deadlock processing modules, and the egress buffer areas of these nodes may be provided with reserved buffers. In this scenario, the data in the second slot enters the reserved cache of the corresponding node according to the normal route.

For example, the three ring networks shown in FIG. 6 are located on the same chip or respectively located on three chips. In this scenario, the data in the second slot enters the reserved buffer corresponding to the first ring network in combination with FIG. 6 .

After the second slot receives the vacancy reservation signal, in the next clock cycle, the second slot sends a vacancy occupation signal to the fourth slot, wherein the fourth slot is a downstream slot adjacent to the second slot. If there is data cached in the second slot, the data can be routed normally and enter the enabled reserved cache.

Specifically, if the destination of the data in the second slot is the second ring network, the data enters the reserved buffer in the egress buffer of the first node at the first slot. If the destination of the data in the second slot is the third ring network, the data enters the reserved buffer in the egress buffer of the third node at the sixth slot. Wherein, the reserved cache in the first node and the reserved cache in the third node are reserved caches corresponding to the first ring network.

In yet another possible scenario, the first ring network is connected to a ring network in the same chip, and is also connected to a ring network in a different chip. The nodes connected to the first ring network and each ring network can be equipped with a deadlock processing module, and there can be reserved buffers in the egress buffer areas of these nodes. In this scenario, the data in the second slot does not need to be transmitted according to the normal route, but enters the reserved buffer of the node connected to the ring network in the chip.

For example, among the three ring networks shown in FIG. 6 , the first ring network and the third ring network are located on the same chip, and the second ring network is located separately on another chip. In this scenario, the data in the second slot enters the reserved buffer corresponding to the first ring network in combination with FIG. 6 .

After the second slot receives the vacancy reservation signal, in the next clock cycle, the second slot sends a vacancy occupation signal to the fourth slot, wherein the fourth slot is a downstream slot adjacent to the second slot. At the same time, the second slot also sends the cached first data to the fourth slot.

If there is a pre-judgment mechanism in place, the deadlock processing module sends a deadlock indication signal to the fifth slot, where the fifth slot is an upstream slot adjacent to the sixth slot. After the fifth slot receives the deadlock indication information sent by the deadlock processing module, it enters the deadlock release working mode from the normal working mode.

The fifth slot may store the identifier of the first ring network, and if the fifth slot receives a vacancy occupancy signal in a certain clock cycle, it is judged whether the identifier of the ring network corresponding to the destination carried in the first data is stored If the identifier of the first ring network corresponding to the destination carried in the first data is not the stored first ring network identifier, it is determined that the destination of the first data is not the first ring The module corresponding to the shape network. Then, the fifth slot sends the first data and the vacancy occupancy signal to the sixth slot, and simultaneously sends an arrive signal.

If the sixth slot also receives the arrive signal when receiving the first data, the first data is sent to the reserved buffer of the egress buffer of the first node. In the next clock cycle, the sixth slot sends a vacancy occupancy signal to the adjacent downstream slots, and the downstream slots adjacent to the sixth slot are empty in this clock cycle. Until a certain clock cycle, the first slot is empty, and the first slot receives a vacancy occupancy signal during the clock cycle, the entry buffer of the first node is allowed to send data to the first slot.

In addition, it should be noted that, in the system on chip, any node connecting any ring network to other ring networks may be provided with a deadlock processing module, and the embodiment of the present application may be deployed in the deadlock processing module Either of the two deadlock release methods provided. Of course, the same deadlock removal method may be deployed in the deadlock processing modules of different nodes, and different deadlock removal methods may also be deployed.

In a possible deployment manner, for each ring network of the SoC, the first deadlock removal method may be deployed in a deadlock processing module of a node connecting the ring network to other ring networks.

In yet another possible deployment manner, for each ring network of the SoC, the second deadlock removal method may be deployed in the deadlock processing module of the node connecting the ring network to other ring networks.

In another possible deployment mode, for each ring network of the system on chip, if a node of the ring network is connected to another ring network of the same chip, the first deadlock release method is deployed on the node Methods. If a node of the ring network is connected to another ring network of a different chip, the second deadlock removal method is deployed on the node.

For example, in FIG. 2 , the first deadlock removal method may be deployed in the deadlock processing module of the nodes connected to ring network 1 and ring network 2 . The second deadlock removal method may be deployed in the deadlock processing module of the nodes connected by the ring network 2 and the ring network 3 . The first deadlock removal method can be deployed in the deadlock processing module of the nodes connected by the ring network 3 and the ring network 4 .

For another example, in FIG. 3, in the deadlock processing module of the nodes connected to the ring network 1 and the ring network 2, in the deadlock processing module of the nodes connected to the ring network 3 and the ring network 4, in the ring network 5 The first deadlock removal method can be deployed in the deadlock processing module of the nodes connected to the ring network 6 . In the deadlock processing module of the nodes connected by ring network 1 and ring network 3, in the deadlock processing module of the nodes connected by ring network 2 and ring network 6, the nodes connected by ring network 4 and ring network 5 The second deadlock removal method can be deployed in the deadlock processing module of .

In the above-mentioned embodiments, all or part may be implemented by software, hardware, firmware or any combination thereof, and when software is used, all or part may be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the device, all or part of the processes or functions according to the embodiments of the present application will be generated. The computer-readable storage medium may be any available medium that can be accessed by the device, or a data storage device such as a server or a data center integrated with one or more available media. The available medium may be a magnetic medium (such as a floppy disk, a hard disk, and a magnetic tape, etc.), an optical medium (such as a digital video disk (Digital Video Disk, DVD), etc.), or a semiconductor medium (such as a solid-state hard disk, etc.).

Those of ordinary skill in the art can understand that all or part of the steps for implementing the above embodiments can be completed by hardware, and can also be completed by instructing related hardware through a program. The program can be stored in a computer-readable storage medium. The above-mentioned The storage medium mentioned may be a read-only memory, a magnetic disk or an optical disk, and the like.

The above is only an embodiment of the application, and is not intended to limit the application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the application shall be included in the protection scope of the application. Inside.

Claims

A method for deadlock release, characterized in that the method is applied to a first node corresponding to a first ring network, the first node is connected to a first slot in the first ring network, and the The first node is connected to the second node corresponding to the second ring network, and the method includes:

Detecting that the first node is in a first state, wherein the first state is a state where there is a possibility of deadlock;

controlling the first slot to send the first data in the first ring network to the reserved buffer in the first egress buffer of the first node, wherein the destination of the first data is not the first A module corresponding to the ring network;

sending the data in the first entry buffer area to the first slot.
The method according to claim 1, wherein the sending the data in the first entry buffer area to the first slot comprises:

Sending the data in the first entry buffer area to the first slot in a first clock cycle, wherein the first clock cycle is a clock cycle when the first data enters the reserved buffer.
The method according to claim 1, further comprising:

sending a vacancy reservation signal to the first slot, wherein the vacancy reservation signal is used to instruct the first slot to send a vacancy occupancy signal to a second slot in the next clock cycle, wherein the second slot is the a downstream slot adjacent to the first slot, the vacancy occupancy signal is used to indicate that the node connected to the second slot is not allowed to send data to the second slot, and instruct the second slot to send data to the second slot The downstream slot adjacent to the slot sends the vacancy occupancy signal;

The sending the data in the first entry buffer area to the first slot includes:

Sending the data in the first entry buffer area to the first slot in a second clock cycle, wherein the second clock cycle is when the first slot sends the first data to the reserved buffer Nth clock cycle after the clock cycle, where N is the number of slots in the first ring network.
The method according to claim 1-3, wherein the first slot of the control sends the first buffer in the first ring network to the reserved buffer in the first egress buffer of the first node. - Data, including:

Sending a deadlock indication signal to a third slot, wherein the third slot is an upstream slot adjacent to the first slot, and the deadlock indication signal is used to indicate that the third slot is judging the current cached first If the destination of the data is not the module corresponding to the first ring network, sending an arrival signal to the first slot, where the arrival signal is used to indicate that the first slot receives the first data, sending the first data to the reserved buffer in the first egress buffer of the first node.
The method according to any one of claims 1-4, wherein the detecting that the first node is in the first state comprises:

The number of consecutive failures to detect that data in the first entry buffer area enters the first slot is greater than a first threshold.
The method according to any one of claims 1-5, wherein the detecting that the first node is in the first state comprises:

Detecting that the available cache occupancy rate of the first entry cache area is greater than a second threshold.
The method according to any one of claims 1-6, wherein the detecting that the first node is in the first state comprises:

Detecting that the available buffer occupancy rate of the first egress buffer area is greater than a third threshold.
The method according to any one of claims 1-7, further comprising:

Detecting that the first node is in a second state, wherein the second state is a state in which data transmission is normal;

Controlling each slot in the first ring network to return to a normal working state.
The method according to claim 8, wherein the detecting that the first node is in the second state comprises:

Detecting that the available cache occupancy rate of the first entry cache area is less than a fourth threshold.
The method according to claim 8 or 9, wherein the detecting that the first node is in the second state comprises:

Detecting that the available buffer occupancy rate of the first egress buffer area is less than a fifth threshold.
A method for deadlock release, characterized in that the method is applied to a first node corresponding to a first ring network, the first node is connected to a first slot in the first ring network, and the The first node is connected to the second node corresponding to the second ring network, and the method includes:

Detecting that the first node is in a first state, wherein the first state is a state where there is a possibility of deadlock;

sending a vacancy reservation signal to the second slot, and controlling the data buffered in the second slot to enter the reserved buffer corresponding to the first ring network when there is data buffered in the second slot, Wherein, the vacancy reservation signal is used to instruct the second slot to send a vacancy occupancy signal to an adjacent downstream third slot, and the vacancy occupancy signal is used to indicate that the node connected to the third slot is not allowed to send The third slot sends data, and instructs the third slot to send the vacancy occupancy signal to a downstream slot adjacent to the third slot.
The method according to claim 11, wherein the first ring network belongs to the first chip, the second ring network belongs to the second chip, and the first chip further includes a third ring network , the first ring network also includes a fourth slot, a fifth slot and a third node, the fifth slot is a downstream slot adjacent to the fourth slot, the fifth slot and the third node connection, the third node is connected to the fourth node corresponding to the third ring network;

In the case where data is cached in the second slot, controlling the data cached in the second slot to enter the reserved cache corresponding to the first ring network includes:

In the case that data is cached in the second slot, a deadlock indication signal is sent to the fourth slot, wherein the deadlock indication information is used to indicate that the fourth slot receives an adjacent upstream slot In the case of sending the vacancy occupancy signal and data, an arrival signal and the data are sent to the fifth slot in the next clock cycle, and the arrival signal is used to indicate that the fifth slot receives the In the case of the data and the arrival signal, sending the data to the reserved buffer of the egress buffer of the third node.
The method according to claim 11 or 12, wherein the detecting that the first node is in the first state comprises:

Detecting that the number of consecutive failures for data in the first entry buffer to enter the first slot reaches a first threshold.
The method according to any one of claims 11-13, wherein the detecting that the first node is in the first state comprises:

Detecting that the available cache occupancy rate in the first entry cache reaches a second threshold.
The method according to any one of claims 11-14, wherein the detecting that the first node is in the first state comprises:

Detecting that the available buffer occupancy rate of the first egress buffer area is greater than a third threshold.
The method according to any one of claims 11-15, wherein the method further comprises:

Detecting that the first node is in a second state, wherein the second state is a state in which data transmission is normal;

Controlling each slot in the first ring network to return to a normal working state.
The method according to claim 11-16, wherein the detecting that the first node is in the second state comprises:

Detecting that the available cache occupancy rate of the first entry cache area is less than a fourth threshold.
The method according to claim 16 or 17, wherein the detecting that the first node is in the second state comprises:

Detecting that the available buffer occupancy rate of the first egress buffer area is less than a fifth threshold.
A system on chip, characterized in that the system on chip includes a first ring network and a second ring network, the first ring network includes a first node, and the second ring network includes a second node, The first node is connected to the second node, and the first node is configured to execute the deadlock removal method according to any one of claims 1-18.