WO2022245531A1 - High-rate decimation filter with low hardware complexity - Google Patents
High-rate decimation filter with low hardware complexity Download PDFInfo
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- WO2022245531A1 WO2022245531A1 PCT/US2022/027286 US2022027286W WO2022245531A1 WO 2022245531 A1 WO2022245531 A1 WO 2022245531A1 US 2022027286 W US2022027286 W US 2022027286W WO 2022245531 A1 WO2022245531 A1 WO 2022245531A1
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- 238000004891 communication Methods 0.000 claims description 7
- 238000005070 sampling Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 description 8
- 230000008520 organization Effects 0.000 description 5
- 230000006870 function Effects 0.000 description 4
- 238000013459 approach Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
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- 230000008859 change Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/06—Non-recursive filters
- H03H17/0621—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing
- H03H17/0635—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies
- H03H17/065—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies the ratio being integer
- H03H17/0664—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies the ratio being integer where the output-delivery frequency is lower than the input sampling frequency, i.e. decimation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0248—Filters characterised by a particular frequency response or filtering method
- H03H17/0264—Filter sets with mutual related characteristics
- H03H17/0273—Polyphase filters
- H03H17/0275—Polyphase filters comprising non-recursive filters
Definitions
- ADC Analog-to-Digital Converter
- CIC filters do not require MAC units but work with high resolution accumulators for integration and further decimation. While this implementation has the least hardware complexity the filter performance in rejection of out-of-band signals is not easily controlled.
- a conventional implementation of a poly -phase filter uses a large set of samples saved in a delay line of registers and use a low rate clock to multiply-and-accumulate (MAC) the values for each coefficient of the FIR filter designed. Further such an implementation uses multiple MAC units to parallelize the operations.
- MAC multiply-and-accumulate
- the disclosure and claims herein are directed to an improved Finite Impulse Response (FIR) filter that reduces the complexity of the hardware required for a filter with a high decimation factor while achieving similar performance of prior art poly-phase filters of greater complexity.
- the FIR filter described herein includes a small number of multiply-and- accumulate (MAC) units connected in parallel to each other between an input stream and an output stream.
- the MAC units are provided with coefficients from a memory.
- the memory is addressed by a counter and the output of the memory selected by a multiplexer for suppling the coefficients.
- a FIR filter including a plurality of MAC units connected in parallel to each other and between an input stream and an output stream, where each of the plurality of MAC unit includes a multiplier connected in series with an adder and an accumulator; a memory with coefficients for the MAC units; and a first multiplexer connected to the plurality of the MAC units and configured to receive an output of the MAC units and provide one output of one of the MAC units to the output stream, wherein: the multiplier is configured to receive an input sample and coefficients from the memory and multiply the input sample with the coefficients to produce a multiplier output to the adder, the adder is configured to add the multiplier output from the multiplier with a last value stored in a register of the accumulator to produce an accumulator output to the first multiplexer, the plurality of MAC units are configured to operate in parallel with each other and an output is generated for the output stream periodically using one of the MAC units based on a decimation factor.
- a FIR filter comprising, a plurality of MAC units connected in parallel to each other between an input stream and an output stream, where each of the plurality of MAC unit includes a multiplier connected in series with an adder and an accumulator; a memory with N rows of coefficients for the MAC units with each row of the N rows including a number of coefficients for each of the MAC units, where N is an integer equal to the decimation factor; and a first multiplexer connected to the plurality of the MAC units and configured to receive an output of the MAC units and provide an output of one of the MAC units to the output stream, wherein: the multiplier is configured to receive an input sample and coefficients from the memory and multiply the input sample with the coefficients to produce a multiplier output to the adder, wherein the first multiplexer selects one accumulator periodically based on the decimation factor to provide the output of the selected one accumulator to the output stream, and the one selected accumulator resets its register, the add
- a FIR filter comprising, a plurality of MAC units connected in parallel to each other between an input stream and an output stream, where each of the plurality' of MAC unit includes a multiplier connected in series with an adder and an accumulator; a memory with N rows of coefficients for the MAC units with each row of the N rows including a number of coefficients for each of the MAC units, where N is an integer equal to the decimation factor; a coefficient generation circuit that controls the generation of coefficients from the memory comprising a counter and a second multiplexer, wherein: the counter has C total bits equal to L least significant bits plus M most significant bits, where C, L and M are integers, the L least significant bits are applied to address the memory and the M most significant bits are applied to the second multiplexer to select a set of coefficients stored at a current address of the memory indicated by the L least significant bits to apply to the set of coefficients to the MAC units; and a first multiplexer connected to the plurality of
- FIG. 1 illustrates a prior art implementation of a poly phase Finite Impulse Response (“FIR”) filter.
- FIR Finite Impulse Response
- FIG. 2 illustrates an example implementation an improved FIR filter that reduces the complexity of the hardware required for a filter with a 64 decimation factor using 4 multiply- and-accumulate (“MAC”) units connected in parallel to each other.
- MAC multiply- and-accumulate
- FIG. 3 illustrates an example circuit for generation of coefficients for each MAC unit of the FIR filter of FIG. 2.
- FIG. 4 illustrates an example of organization of coefficients in the RAM memory of the FIR filter of FIG. 2.
- FIG. 5 illustrates an example satellite system that utilizes a FIR filter for multi data rate communication.
- FIG. 1 illustrates an implementation of a poly-phase FIR filter 100 according to the prior art.
- the FIR filter 100 includes a long delay line 110 and a set of coefficients chosen to meet certain in-band and out-of-band filter characteristics. This implementation involves the storage of all values in the registers of the delay line 110 and a number of multiplier units 112 to perform the vector multiplication followed by an adder 114. The output of the adder is then decimated by 64 by decimation function 116 and the samples output at the reduced rate of 932kHz. Not all the outputs of the FIR filter are required for a decimation filter where samples are dropped based on decimation factor; hence most of the computations may not be used. For example, the FIR filter of order 256 will involve a vector multiplication of a delay line of 256 samples multiplied by the 256 coefficients of the filter.
- FIG. 2 illustrates an example of an improved FIR filter 200 with reduced hardware complexity.
- This improved FIR filter 200 provides a multi sample rate filter with high decimation without the need for an extensive number of registers used in prior art filters such as the FIR filter shown in FIG. 1.
- the FIR filter 200 includes 4 MAC units 214 connected in parallel with each other between an input stream 210 and output stream 212.
- Each MAC unit 214 includes a multiplier 216 connected in series with an adder 218 and accumulator 220.
- the accumulator 220 is typically a register.
- the multiplier 216 multiplies an input sample with the relevant coefficient provided to each MAC unit from the circuit shown in FIG. 3.
- the result from the multiplier 216 is then added to the last stored value (represented by the arrow 222) of the accumulator register 220, and the result is stored in the accumulator register 220.
- An output is generated by selecting one of the accumulator outputs with the multiplexer 224 where one accumulator 220 is selected by the multiplexer 224 every 64 clock cycles as described below.
- the FIR filter 200 may include configurable rounding, shifting and saturating function block 226 which is then supplied the Z 1 block at 230.
- the configurable rounding, shifting and saturation block 226 reduces the number of bits in the accumulator 220 to a required number of bits as per the modulation and dynamic range requirements of the signal.
- a 40-bit accumulator in 220 could be reduced 12-bits after the operation of block 226.
- the Z 1 block 230 is a hardware register to save the final output after rounding, shifting and saturation in block 226 at the output clock rate of 936kHz. This output is available on the next 936kHz processing clock for other blocks that follow (not shown).
- the Z 1 block 228 is a hardware register to save the input sample received at the input 210 with a clock rate of 59.904MHz. This data is available on the next processing clock for the multiplication in multiplier 216.
- These registers 228, 230 are often used in a design to meet the timing constraints in the hardware synthesis.
- the wideband input sample rate is 59.904MHz applied at input 210.
- the final decimated output at 212 is at a 936KHz sample rate. Therefore, the decimation factor is 64 (e.g., 59904/936).
- the output is generated using one of the accumulators by scaling and saturating the value. The accumulator that provided the output will then be reset before next set of values are accumulated. Specifically, every time a new sample comes at the sample rate of 59.904MHz, each MAC unit in parallel receives a coefficient and multiplies it with a relevant portion of the input stream as shown and described further with respect to FIG. 3.
- the multiplied result is then added to last stored value of the accumulator register and then the added result is stored in the accumulator register.
- the FIR filter 200 described does not store all the samples of the delay line required in filter computations like was done in the prior art example shown in FIG. 1
- a 256 taps equivalent FIR filter show in FIG. 2 is implemented with just 4 MAC units to decimate by a factor of 64.
- the number of MAC units may vary depending on the sample size and the decimation factor.
- a 256 taps equivalent FIR filter may be used to achieve a rejection of more than 75dB on an out-of-band signal.
- the 4 MAC units will stagger the computation in such a way that every 64 samples one of the MAC units will output a sample and reset its own accumulator. Therefore, unlike the FIR filter shown in FIG. 1, the FIR filter of FIG. 2 does not have to store the 256 samples because the computations are performed as the new sample comes in.
- These four MAC units take the new sample whenever a new sample comes, it multiplies with the coefficient and adds the result to respective the accumulator.
- the MAC units 214 continue to operate in this way for 256 samples. Significantly, the computations are staggered by 64 samples, and each MAC unit 214 uses different coefficients 322 (FIG.3) out of the 256 coefficients from the RAM 314. With such staggered computation of the four MAC units, every 64 clocks of the input, one output is selected from the Mux 224 ( Figure 2).
- coefficients are supplied to the MAC units 214 from a coefficient memory 314 as shown in FIG. 3.
- the coefficient memory 314 is organized in 4 columns configured to retrieve 4 coefficient values (4 sets of coefficients) each clock, where each MAC unit uses a different set of coefficients to multiply and accumulate.
- the same set of coefficients are used by the MAC units of “in-phase” and “quadrate-phase” sample filters.
- the described FIR filter uses minimal hardware (without any pipelined storage of samples in register) and can be operated by a simple fmite-state-machine (not shown) to retrieve coefficients for the operation and generate output samples (with scaling and saturation).
- FIG. 3 illustrates a coefficient generation circuit 300 for generation of coefficients used by the MAC units 214 in FIG.2 on each clock (or input sample).
- a counter in the coefficient generation circuit 300 is clocked at the input 312 with an input sample rate.
- the counter 310 is used to count the sample currently used, fetch from memory the correct row of coefficients to select correct output samples for each MAC unit as described above.
- the lower significant bits (LSB) of the counter are used to access the memory 314 and the upper or most significant bits (MSB) are used to select the coefficients from the row of memory.
- the FIR filter has an output sample rate of 936kHZ
- the counter 310 is an 8-bit counter clocked by a 936kHZ clock at the input 312.
- the 6 LSB bits 316 of the counter 310 are applied to a memory referenced as coefficients ram 314.
- the 2 upper or MSB significant bits 318 are applied to the data selector or multiplexer 320.
- the coefficients RAM 314 is organized into a 64x48 bit array described further below. In this example, each coefficient is a 12-bit value.
- the selector 320 inputs the 48 bits from the coefficient RAM 314 for the current value of the counter 310.
- the 48 bits are applied to the coefficients (Coef_0, Coef_l, Coef2, Coef3) depending on the 2 MSB bits as shown and described herein.
- FIG. 4 illustrates the coefficient organization in the RAM 314.
- RAM 314 provides a correct set of coefficients for each MAC unit on each clock (or input sample) as described above.
- coefficients RAM 314 includes 64 rows (addressed by 6 LSB bits) with 48 bits of data for each row. For each 6 bit address (64 rows), 48 bits of data corresponding to each row are output from the memory to the 4 MAC units as shown in FIG. 3.
- the memory of RAM 314 can be logically represented as shown with 64 rows (AO through A63) with 48 bits.
- the 48 bits are divided into four addresses as shown and selected by the 2 MSBs of the counter as described above.
- the RAM 314 organization can also be viewed as the coefficients for Coef_0 using the addresses A0-A63.
- the other coefficients Coef_l through Coef_3 will get a set of coefficients from the same row in the RAM 314 as Coef_0.
- the coefficients thus get the same data from RAM 314 but in a different order.
- the order of the data for the coefficients is reflected in the outputs from Mux 320 as shown and described in the following paragraph.
- each MAC unit 214 will receive a different portion of the 48 bits data (e.g., coefficient values) from the RAM 314 based on the 2 MSBs of the counter 310.
- the Coef_0 of the FIR filter would correspond to data bits 11:00 located in cell A0 of the memory as shown in FIG. 3.
- coefficient 1 (coef_l) of the FIR filter would correspond to data 47:36 of the first row (also cell A192); coef_2 would correspond to data 35:24 of the first row (cell A128); and coef_3 would correspond to data bits 23:12 of the first row (cell A64).
- the 48 bits data from the second row are fed to the MAC units.
- the order of the bits supplied to the coefficients is different.
- the data bits 23:12 would correspond to the coef_0; the data bits 11:0 would correspond to coef_l; and the data bits 47 : 36 would correspond to Coef_2 and the data bits 23 : 12 would correspond to Coef_3.
- all MAC units are working together at the same time but use different columns or different entries of the coefficients RAM 314.
- FIG. 5 illustrates a satellite communication system 500 that may incorporate the FIR filter described herein.
- the satellite system 500 includes a user terminal 510 that communicates with a gateway 512 over a satellite 514.
- the user terminal 510 communicates with the satellite 514 over a user link 516.
- the satellite 514 communicates with the gateway 512 over a gateway link 518.
- the gateway 512 includes a receiver (not shown) that can receive multiple data rates using the FIR filter 520 as described herein to receive multi rate data with a high decimation rate.
- the user terminal and the satellite may also include a FIR filter 520 (not shown) for communicating with multi data rates as described herein.
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Application Number | Priority Date | Filing Date | Title |
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EP22724580.0A EP4342085A1 (en) | 2021-05-19 | 2022-05-02 | High-rate decimation filter with low hardware complexity |
CA3219296A CA3219296A1 (en) | 2021-05-19 | 2022-05-02 | High-rate decimation filter with low hardware complexity |
BR112023024224A BR112023024224A2 (en) | 2021-05-19 | 2022-05-02 | HIGH RATE DECIMATION FILTER WITH LOW HARDWARE COMPLEXITY |
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US202163190721P | 2021-05-19 | 2021-05-19 | |
US63/190,721 | 2021-05-19 | ||
US17/510,607 | 2021-10-26 | ||
US17/510,607 US11979131B2 (en) | 2021-05-19 | 2021-10-26 | High-rate decimation filter with low hardware complexity |
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4802111A (en) * | 1986-03-10 | 1989-01-31 | Zoran Corporation | Cascadable digital filter processor employing moving coefficients |
US20080114821A1 (en) * | 2006-11-09 | 2008-05-15 | Yokogawa Electric Corporation | Decimation filter |
US20130110898A1 (en) * | 2011-10-28 | 2013-05-02 | Stmicroelectronics International Nv | Apparatus for signal processing |
US20160182014A1 (en) * | 2014-12-17 | 2016-06-23 | Stmicroelectronics International N.V. | Polyphase decimation fir filters and methods |
US20170063575A1 (en) * | 2015-08-24 | 2017-03-02 | Texas Instruments Incorporated | Analog-digital compatible re-sampling |
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- 2022-05-02 WO PCT/US2022/027286 patent/WO2022245531A1/en active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4802111A (en) * | 1986-03-10 | 1989-01-31 | Zoran Corporation | Cascadable digital filter processor employing moving coefficients |
US20080114821A1 (en) * | 2006-11-09 | 2008-05-15 | Yokogawa Electric Corporation | Decimation filter |
US20130110898A1 (en) * | 2011-10-28 | 2013-05-02 | Stmicroelectronics International Nv | Apparatus for signal processing |
US20160182014A1 (en) * | 2014-12-17 | 2016-06-23 | Stmicroelectronics International N.V. | Polyphase decimation fir filters and methods |
US20170063575A1 (en) * | 2015-08-24 | 2017-03-02 | Texas Instruments Incorporated | Analog-digital compatible re-sampling |
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