WO2022241782A1 - 一种集成电路的电路单元布局方法及装置 - Google Patents

一种集成电路的电路单元布局方法及装置 Download PDF

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Publication number
WO2022241782A1
WO2022241782A1 PCT/CN2021/095299 CN2021095299W WO2022241782A1 WO 2022241782 A1 WO2022241782 A1 WO 2022241782A1 CN 2021095299 W CN2021095299 W CN 2021095299W WO 2022241782 A1 WO2022241782 A1 WO 2022241782A1
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Prior art keywords
layout
legal placement
area
circuit unit
legal
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PCT/CN2021/095299
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English (en)
French (fr)
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陈翰轩
王智生
许若圣
戴方明
张锐
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华为技术有限公司
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Priority to CN202180093965.8A priority Critical patent/CN116888599A/zh
Priority to PCT/CN2021/095299 priority patent/WO2022241782A1/zh
Publication of WO2022241782A1 publication Critical patent/WO2022241782A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions

Definitions

  • the present application relates to the technical field of integrated circuit layout planning, in particular to a circuit unit layout method and device for integrated circuits.
  • Integrated circuit layout is a step in the physical design of a very large integrated circuit (VLSI), which mainly determines the placement of each circuit unit in the integrated circuit, and can be further subdivided into macro-cell placement (macro-cell placement, MP), overall layout and detailed layout, among them, MP is the first step in the layout stage, and its layout quality has a significant impact on the final physical design index.
  • VLSI very large integrated circuit
  • the embodiment of the present application provides a circuit unit layout method and device of an integrated circuit. Based on the first condition, the legal placement position of the circuit unit is obtained in the layout area of the integrated circuit, which can improve the layout of the integrated circuit. Efficiency and quality of layout results.
  • the embodiment of the present application provides a circuit unit layout method of an integrated circuit, the method comprising: obtaining the current layout of the integrated circuit; the current layout includes: a first area where no circuit units are laid out; in the first area Determining multiple legal placement positions for placing the first circuit unit; the layout prediction model outputs a prediction result based on the current layout and the multiple legal placement positions; according to the prediction result, determine the placement position of the first circuit unit in the first area Location.
  • multiple legal placement positions where the first circuit unit can be placed are obtained in the unlayouted area, and the position where the first circuit unit is placed is obtained based on the prediction results of the multiple legal placement positions according to the layout prediction model, Placing the first circuit unit in a legal position can improve the legitimacy of the layout of the first circuit unit, thereby improving the layout quality of the integrated circuit; using multiple legal placement positions as the prediction basis of the layout prediction model, compared with Searching for the position of the first circuit unit in this layout area narrows the search range and improves the layout efficiency of the integrated circuit.
  • the legal placement position includes: the legal placement position is located at a corner position of the first area and/or at an edge position of the first area.
  • the corner position and/or the edge position of the first region is used as a legal placement position, which can achieve the purpose of placing the circuit units sideways or corners, and can improve the layout quality.
  • the angular position includes an angular position formed based on vertices of circuit units already placed in the current layout and/or an angular position formed by vertices of the first region.
  • the angular position formed by the vertices of the circuit units that have been laid out and/or the vertices of the first region is taken as the legal placement position, which can realize the purpose of placing the circuit units by the side or by the corner, and can improve the layout quality; wherein, Taking the angular position formed by the vertices of the laid out circuit units as the legal placement position, when the angular position formed by the vertices of the first region is occupied, the circuit units can be placed in an orderly manner, thereby improving the quality of the circuit layout.
  • the legal placement position also includes a position that satisfies at least one of the following: after the first circuit unit is placed in the legal placement position, the first circuit unit and the circuit units that have been placed in the current layout No overlapping; after the first circuit unit is placed in the legal placement position, no suspended area will be generated in the first area; after the first circuit unit is placed in the legal placement position, no closed area will be generated in the first area; or the legal placement position is in the second In a region, the angular position formed by the vertices of the laid-out circuit units belonging to the same group as the first circuit unit; wherein, the functions of the multiple circuit units in the same group are correlated.
  • the position where the circuit units do not overlap and the placement area does not generate vacant and closed areas is taken as the legal placement position, which can avoid overlapping circuit units, vacant areas, and closed areas in the integrated circuit after layout, and reduce Layout quality; the angular position formed by the vertices of the layout circuit units belonging to the same group can be used as the legal placement position, which can realize the purpose of placing the units of the same group together.
  • the circuit can be Units are placed more rationally, thereby improving the quality of circuit layout.
  • the output of the layout prediction model is the probability of each legal placement position in the plurality of legal placement positions, and according to the prediction result, determining the position to place the first circuit unit in the first region includes: according to The probability of each legal placement position in the plurality of legal placement positions determines the position where the first circuit unit is placed in the first area.
  • the placement probability of each legal placement position is predicted by the layout prediction model, and then the position of the first circuit unit is determined according to each probability, which can make the position of the first circuit unit in the layout more reasonable.
  • determining the position where the first circuit unit is placed in the first area includes: selecting the position with the highest probability among the plurality of legal placement positions The legal placement position of is determined as the position where the first circuit unit is placed.
  • the legal placement position with the highest probability is selected as the position of the first circuit unit, so that the placement position of the first circuit unit in the area is more reasonable, thereby improving the layout quality.
  • determining the position where the first circuit unit is placed in the first area includes: according to the probability of each legal placement position in the plurality of legal placement positions The probability of placing a position is to extract a plurality of legal placement positions to obtain a legal placement position for placing the first circuit unit.
  • the legal placement positions are sampled based on the probability of each legal placement position to obtain the position of the first circuit unit, thereby obtaining the position of the first circuit unit.
  • the first circuit unit includes a macro unit.
  • an embodiment of the present application further provides a circuit unit layout device for an integrated circuit, the device comprising: an acquisition module, configured to acquire the current layout of the integrated circuit; the current layout includes: a first area where circuit units are not laid out; The first determination module is configured to determine a plurality of legal placement positions for placing the first circuit unit in the first area; the prediction module is used for the layout prediction model to output prediction results based on the current layout and the plurality of legal placement positions ; A second determination module, configured to determine the position of the first circuit unit in the first area according to the prediction result.
  • the legal placement position includes: the legal placement position is located at a corner position of the first area or at an edge position of the first area.
  • the angular position includes an angular position formed based on vertices of circuit units already placed in the current layout and/or an angular position formed by vertices of the first region.
  • the legal placement position also includes a position that satisfies at least one of the following: after the first circuit unit is placed in the legal placement position, the first circuit unit and the circuit units that have been placed in the current layout No overlapping; after the first circuit unit is placed in the legal placement position, no suspended area will be generated in the first area; after the first circuit unit is placed in the legal placement position, no closed area will be generated in the first area; or the legal placement position is in the second In a region, the angular position formed by the vertices of the laid-out circuit units belonging to the same group as the first circuit unit; wherein, the functions of the multiple circuit units in the same group are correlated.
  • the output of the layout prediction model is the probability of each legal placement position in the plurality of legal placement positions
  • the second determining module is specifically configured to: according to the probability of each legal placement position in the plurality of legal placement positions The probability of the location determines the location of the first circuit unit in the first area.
  • the second determination module is specifically configured to: determine the legal placement position with the highest probability among the plurality of legal placement positions as the position where the first circuit unit is placed.
  • the second determination module is specifically configured to: extract a plurality of legal placement positions according to the probability of each legal placement position in the plurality of legal placement positions, and obtain the placement of the first circuit unit legal placement.
  • the first circuit unit includes a macro unit.
  • the embodiment of the present application also provides an integrated circuit layout device, the device includes: a processor and a transmission interface, the processor is configured to call the program instructions stored in the memory, so that the integrated circuit layout device described in the first aspect and methods in its alternative implementations.
  • the embodiment of the present application also provides a computing device, the computing device includes: a memory and a processor, the memory stores computer instructions, and when the processor executes the computer instructions, the above first aspect and its alternative implementations can be realized. Methods.
  • the embodiment of the present application also provides a computer-readable storage medium, the computer-readable storage medium stores computer program code, and when the computer program code is executed by a computing device, the above-mentioned first aspect and its optional implementations are realized methods in methods.
  • the embodiments of the present application further provide a computer program product containing instructions, which, when executed by a computer or a processor, enable the computer or the processor to implement the above-mentioned first aspect and its optional implementation manners. Methods.
  • Fig. 1 is a schematic diagram of a macrocell layout result provided by the present application
  • FIG. 2 is a schematic diagram of reinforcement learning training provided by the present application
  • FIG. 3 is a schematic diagram of a macrocell layout provided by the present application.
  • FIG. 4 is a flow chart of an integrated circuit layout method provided in an embodiment of the present application.
  • FIG. 5 is a flow chart of a method for training a layout prediction model provided in an embodiment of the present application
  • Fig. 6a and Fig. 6b are schematic diagrams of a legal placement position at an edge position in a blank layout provided by an embodiment of the present application;
  • Fig. 6c is a schematic diagram of corner positions in a blank layout provided by an embodiment of the present application.
  • Fig. 6d is a schematic diagram of a legal placement position in a corner position in a blank layout provided by an embodiment of the present application;
  • Fig. 6e is a schematic diagram of corner positions in a non-blank layout provided by an embodiment of the present application.
  • Fig. 6f and Fig. 6g are schematic diagrams of legal placement positions in a non-blank layout provided by the embodiment of the present application.
  • Fig. 7a is a schematic diagram of the layout of the macro units provided by the embodiment of the present application without overlapping;
  • Fig. 7b is a schematic diagram of the layout of overlapping macro-units provided by the embodiment of the present application.
  • Fig. 8 is a schematic layout diagram of the floating area provided by the embodiment of the present application.
  • FIG. 9 is a schematic layout diagram of a closed area provided by an embodiment of the present application.
  • FIG. 10 is a schematic layout diagram of two macro-units belonging to the same group provided by the embodiment of the present application.
  • Fig. 11a is a schematic diagram of changes in height lines before and after placing macro units provided by the embodiment of the present application.
  • Figure 11b is a schematic diagram of the layout of the floating area after the macro unit provided by the embodiment of the present application
  • Fig. 12a and Fig. 12b are schematic diagrams of the layout of the closed area generated by two macro-units provided by the embodiment of the present application;
  • Figure 12c is a schematic diagram of the layout of two macro-units provided by the embodiment of the present application without generating a closed area
  • Fig. 13 is a schematic diagram of marking the legal placement provided by the embodiment of the present application.
  • Fig. 14 is a schematic diagram of the placement position obtained by sampling according to the probability distribution provided by the embodiment of the present application.
  • FIG. 15 is a flow chart of a method for circuit unit layout using a layout prediction model provided by an embodiment of the present application.
  • Fig. 16 is a schematic diagram of a device structure of a layout device provided by an embodiment of the present application.
  • FIG. 17 is a schematic structural diagram of a computing device provided by an embodiment of the present application.
  • words such as “exemplary”, “for example” or “for example” are used to represent examples, illustrations or illustrations. Any embodiment or design described as “exemplary”, “for example” or “for example” in the embodiments of the present application shall not be construed as being more preferred or more advantageous than other embodiments or designs. Rather, the use of words such as “exemplary”, “for example” or “for example” is intended to present related concepts in a specific manner.
  • the term "and/or" is only an association relationship describing associated objects, indicating that there may be three relationships, for example, A and/or B may indicate: A exists alone, A exists alone There is B, and there are three cases of A and B at the same time.
  • the term "plurality" means two or more.
  • multiple systems refer to two or more systems
  • multiple screen terminals refer to two or more screen terminals.
  • At least one of the following or similar expressions refer to any combination of these items, including any combination of single or plural items.
  • At least one item (piece) of a, b or c can mean: a, b, c, "a and b", “a and c", “b and c", or "a and b and c ", where a, b, c can be single or multiple.
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying indicated technical features. Thus, a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features.
  • the terms “including”, “comprising”, “having” and variations thereof mean “including but not limited to”, unless specifically stated otherwise.
  • Netlist data is the data describing the connection of each unit in the integrated circuit. Wherein, it may include a macro-cell to be placed, a standard-cell, a connection relationship and a layout area between the macro-cell and the standard-cell. Optionally, the netlist data may also include information such as process parameters of the integrated circuit.
  • a macro-cell is a predefined logic function implementation unit composed of flip-flops, arithmetic logic units, hardware temporary registers, etc. with a higher level of abstraction than logic gates. In VLSI design, these logic units are used as a macro The cell as a whole is placed on a silicon wafer. Each macro-unit corresponds to a different logic function, and each macro-unit can also correspond to a different size.
  • Macro-cell placement is the process of placing macro-cells in the layout area.
  • the schematic diagram of the macrocell layout results shown in Figure 1.
  • the layout area is regarded as a rectangular area, including the upper edge (Top), the lower edge (Bottom), the left edge (Left) and the right edge (Right).
  • the macrocell number is b1 , b2, ..., b17, represented by small rectangles in the layout area.
  • the macro-unit layout can be understood as placing the macro-units b1, b2, ..., b17 in a rectangular area surrounded by the Top side, the Bottom side, the Left side and the Right side.
  • a standard unit is a tiny basic circuit unit that can include various units such as an inverter, an AND gate, a register, a selector, and a full adder. Similarly, each standard unit corresponds to one or more macrounits. It can be understood that the size and driving capability of each macrounit in a plurality of macrounits can be the same or different, and the size of each macrounit can be the basic size Or an integer multiple of the minimum size standard cell layout refers to the process of placing the standard cells in the area where the macro is not arranged in the layout area after the macro cell layout is completed.
  • Routing is to connect macro-cell and standard-cell with wires according to the connection relationship.
  • the evaluation index is used to evaluate the layout result of the layout area. Specifically, it can include: wire length: refers to the total length of the lines connecting macro-cell and standard-cell in the layout area; congestion: refers to the line density of the densest area in the layout area, and the layout area The lines in it should not be too dense; timing (timing): after the macro and standard cell are connected, the delay of each path, including the maximum delay (WNS) and the total delay (TNS); it should be understood that the aforementioned indicators The smaller the data value, the better the layout quality of the current layout.
  • a neural network is a mathematical model. After training, the neural network can output corresponding results under a given input.
  • a neural network is specifically a mathematical algorithm model that imitates the structure and function of a biological neural network (the central nervous system of an animal).
  • a neural network can include multiple neural network layers with different functions, and each layer includes parameters and calculation formulas. According to different calculation formulas or different functions, different layers in the neural network have different names. For example, a layer that performs convolutional calculations is called a convolutional layer, and a convolutional layer is often used to extract features from an input signal (such as an image).
  • a neural network model can also be composed of multiple existing neural network models.
  • Neural network models with different structures can be used in different scenarios (such as classification, recognition, etc.) or provide different effects when used in the same scenario.
  • the different structure of the neural network model specifically includes one or more of the following: the number of network layers in the neural network model is different, the order of each network layer is different, and the weights, parameters or calculation formulas in each network layer are different.
  • Reinforcement learning also known as reinforcement learning, evaluation learning or reinforcement learning
  • reinforcement learning is a method of machine learning that maximizes the return of the agent through the continuous learning of the agent in the interaction with the environment.
  • the reinforcement learning algorithm adopted may adopt policy gradient (policy gradient) algorithm, Q learning (Q-learning) algorithm, deep Q network (deep Q network) algorithm and actor critic (actor critic) any algorithm.
  • Fig. 2 is a schematic flow diagram of a reinforcement learning provided by the present application. As shown in Fig.
  • the current state of the environment is input into the prediction model; then, according to the output of the prediction model, the obtained The current action of the agent; then, update the current state of the environment based on the current action of the agent to complete an interaction between the agent and the environment; where, before inputting the state into the prediction model, according to the reward and reinforcement of the last action of the agent Learning the set loss function updates the parameters of the prediction model, so that the next action of the agent can get a higher reward.
  • the rewards of the agent are accumulated according to the reward value of the environment feedback in each interaction, and one reinforcement learning of the agent is ended, and the agent performs reinforcement learning for many times until it satisfies When the termination condition is reached, the training of the prediction model ends.
  • the prediction model can be a policy network, which is used to generate an action strategy for the agent according to the state of the environment, and the agent selects an action from the action set corresponding to the action strategy; optionally, the action strategy can be an action set
  • the probability distribution corresponding to each action in the agent randomly samples each action from the probability distribution to obtain the current action.
  • a softmax classification layer may be included in the policy network to output the corresponding probability.
  • the prediction model may also include a value network, which is used to calculate rewards for the agent to perform actions according to the state of the environment, and after obtaining the rewards of the agent, update the parameters of the prediction model according to the rewards of the agent.
  • mixed-size is used for integrated circuit layout.
  • the method converts the layout problem of an integrated circuit into a mathematical programming problem, and optimizes and solves the placement positions of macro cells and standard cells.
  • the two evaluation indexes of the line length and line density between two circuit units are approximated as an optimization function, and the stochastic optimization algorithm is used for planning and solving, so as to obtain the macro-unit that meets the design conditions Placement and placement of standard units.
  • WL(e,x,y) represents the length of the e-th line between unit x and unit y in the layout
  • E represents the total number of lines between x and y
  • D(x,y) Indicates the line density between unit x and unit y in the layout
  • ⁇ 1 and ⁇ 2 are the line length index and the weight of line density respectively.
  • This related technology is to search and verify the placement positions of macro cells and standard cells in the entire layout area, and the search range is large, the layout efficiency is low, and the quality of the obtained layout is poor.
  • a neural network trained by reinforcement learning is used to obtain a probability distribution of placement positions to implement macrocell placement. Specifically, before each macro unit is placed, the neural network is used to obtain the probability distribution of the placement position in the current layout, and the placement position is sampled from the probability distribution to obtain the current macro unit placement position.
  • the neural network is used to obtain the probability distribution of the placement positions used to place the macro units in the blank layout S0 , and then each placement position is sampled from the probability distribution to obtain a placement position and place
  • the macro unit (the black square in the S 1 layout in Figure 3), so that the blank layout S 0 is immediately updated to the layout S 1 , and then the next macro unit is placed in the same way to obtain the layout S 2 , and this process is repeated.
  • FIG. 4 is a flowchart of an integrated circuit layout method provided by an embodiment of the present application, and the method is applied to the layout device 100 . As shown in FIG. 4 , the method predicts the placement position of each circuit unit in the integrated circuit through a layout prediction model, so as to realize the layout design of the integrated circuit. The following steps S401-S403 are included.
  • step S401 the netlist data of the integrated circuit is obtained.
  • the netlist data of the integrated circuit refers to the foregoing introduction, and will not be introduced here;
  • the integrated circuit may be a circuit component used for integrated chip design, or may be a circuit of a complete integrated chip.
  • a circuit component or an integrated chip may include multiple circuit devices, such as transistors, resistors, capacitors and other devices.
  • an integrated circuit may be a circuit that realizes any functional purpose, for example, it may be an application-specific integrated circuit for machine learning calculation, video processing, encryption, or other calculation-intensive functions.
  • step S402 the layout prediction model is trained according to the netlist data of the integrated circuit.
  • the layout prediction model can be obtained through reinforcement learning algorithm training, and the layout prediction model can be as the prediction model introduced in the reinforcement learning section above, and the specific training process of the layout prediction model will be combined in the following introduction Figure 5 describes in detail.
  • step S403 the layout of the integrated circuit is determined using the trained layout prediction model.
  • the layout prediction model is used to predict the placement position of the first circuit unit in the integrated circuit, so as to realize the layout design of the integrated circuit, wherein the first circuit unit can be integrated Circuit macrocells.
  • the specific process of this step will be described in detail in conjunction with FIG. 13 in the following introduction.
  • FIG. 5 is a flow chart of a method for training a layout prediction model using a reinforcement learning algorithm provided by an embodiment of the present application, and the method is applied to the layout device 100 .
  • the method performs model training based on circuit units (including macro cells and standard cells), unit connection relations and layout area parameters in the netlist data of integrated circuits.
  • circuit units including macro cells and standard cells
  • unit connection relations and layout area parameters in the netlist data of integrated circuits.
  • the placement of the first circuit unit is regarded as intelligent
  • the action of the body, the legal placement in the current layout is regarded as the action set of the agent
  • the layout of the integrated circuit is regarded as the state of the environment
  • the evaluation index of the layout is regarded as the reward and return of the agent.
  • the model training process of the embodiment of the present application will be described in detail below.
  • the method includes the following steps S501 to S507.
  • step S501 the current layout of the integrated circuit is acquired.
  • the current layout refers to the layout result after placing a macro unit in the layout area of the integrated circuit, and the current layout may include the first area and the second area, wherein the first area may be the current layout In the area where macro cells are not laid out, the second area may be an area where macro cells are laid out in the current layout.
  • the current layout is the first layout of the integrated circuit, it means that the current layout is a blank layout, that is, the current layout only includes the aforementioned first region; if the current layout is not the first layout of the integrated circuit, the current layout The layout includes the aforementioned first area and second area.
  • step S502 in the current layout of the integrated circuit, a plurality of legal placement positions are obtained as candidates, and the legal placement positions are used to place the macro-units to be placed.
  • this step may be that the layout device 100 judges each layout position in the first area one by one based on the preset first condition, so as to obtain the macro units for placing the macro units to be laid out that meet the first condition. legal placement. Specifically, the obtained shape and size of the legal placement position match the shape and size of the macro unit to be placed.
  • the macro unit is in a fixed form, that is, the shape and size of the macro unit cannot be adjusted, and the macro unit cannot be rotated and mirrored.
  • the shape of the macro unit can be a rectangular area, or a polygonal area of other types. In the subsequent introduction of this application, the macro unit is regarded as a rectangular area for description.
  • the first condition may be set according to the placement rules or placement requirements of the macro units. It can be understood that the number of finally obtained legal placement positions may be one or multiple. In an example, when only one legal placement position is obtained, the legal placement position may be directly used as the position for placing the macro unit.
  • the first condition may include at least one of the following conditions 1-5.
  • the legal placement position is at the corner position of the first area or the edge position of the first area.
  • the angular position may include the angular position formed based on the vertices of the macro units already laid out in the current layout and the angular position formed by the vertices of the first region.
  • the legal placement position is at an edge position, one side of the legal placement position coincides with the edge position.
  • a vertex of the legal placement position coincides with the intersection point of the corner position, and at least one side of the legal placement position coincides with an intersection line constituting the corner position. It can be understood that an angular position includes an intersection point and at least two intersection lines.
  • one edge position can correspond to one legal placement position for placing macrounits, and can also correspond to multiple legal placement positions for placing macrounits.
  • the specific number can be determined according to the length and edge position of the macrounit. The length is determined.
  • the edge position corresponds to at most one legal placement position for placing the macro unit;
  • the current layout is a In the square area shown in 1, in the current layout, when the length of the macro unit A is equal to the length of the Top side, the Top side corresponds to at most one legal placement position for placing the macro unit A.
  • the edge position when the length of the macrounit is less than the length of the edge position, can correspond to multiple legal placement positions for the macrounit; as shown in Figure 6b, when the length of the macrounit A is less than the length of the Top side When the length is , the Top side can correspond to a plurality of legal placement positions for placing the macrounit A (three positions are only given as an example in FIG. 6 b ).
  • the angular position when the angular position is the angular position formed by the vertices of the first area, the angular position corresponds to at most one legal placement position for placing the macrocell; When forming an angular position, the angular position may correspond to multiple legal placement positions for placing the macrounit.
  • the angular position of the first area when the current layout is a blank layout, the angular position of the first area only includes the angular position formed by the vertices of the first area; correspondingly, when the current layout is not a blank layout, the angular position of the first area may also include the aforementioned The angular position formed by the vertices of the macro units already placed in the current layout and the angular position formed by the vertices of the first region.
  • the blank layout can be a square area as shown in Figure 1 above, and when the blank layout is the current layout, the first area of the current layout can be a gray area as shown in Figure 6c , the first area not only includes four edge positions, but also includes corner positions (pentagonal marks) formed by its own four vertices, and there can only be one corner position for arranging macrocells to be laid out at each corner position legal placement.
  • the legal placement positions dashed.
  • the blank layout shown in FIG. 6c is updated to a non-blank layout as shown in FIG. 6e.
  • the number of edge positions and the number of corner positions of the first area in the current layout shown in Figure 6e have changed; where the edge positions include the first area (gray area) as shown in Figure 6e
  • the corner position formed by the vertices of the macro unit A is added, that is, the corner positions marked 1-7 in Figure 6e. It can be understood that the lower left vertex of macrocell A in FIG.
  • Condition 2 After the macro unit is placed in the legal placement position, the macro unit does not overlap with the macro units already placed in the current layout. This condition applies in instances where the current layout is not a blank layout.
  • An exemplary illustration is made with reference to Fig. 7a and Fig. 7b.
  • macrocell A is a macrocell that has been laid out, and the layout position (dotted box B) where macrocell B is placed is located at the corner position formed by a vertex of cell A (the pentagonal mark in Fig.
  • Condition 3 After the macro unit is placed in the legal placement position, there will be no floating area in the first area. This condition also applies to examples where the current layout is a non-blank layout. Referring to Figure 8, the layout position (dotted line box B) is located at the corner position shown in Figure 8, after the macro unit B is placed in the layout position (dashed line box B), a floating area will be generated below unit B and on the right side of unit A , therefore, this layout position (dashed box B) is not a legal placement position.
  • Condition 4 After the macro unit is placed in the legal placement position, no closed area is generated in the first area.
  • This condition also applies to examples where the current layout is a non-blank layout. Referring to Fig. 9, the layout position (dotted line box C) is located at the corner position shown in Fig. 8, after the macrounit C is placed in the layout position (dotted line box C), a closed area will be generated under the macrounit C and on the right side of the macrounit A area, therefore, this layout position (dotted box C) is not a legal placement position.
  • Condition 5 The legal placement position is located in the first area, which is the corner position formed by the placed macro cells belonging to the same group as the macro cells to be placed, wherein the functions of the macro cells in the same group are correlated.
  • This condition also applies to examples where the current layout is a non-blank layout.
  • the function correlation of the macro-units means that when one of the two circuit units realizes its own function, it needs the data or information of the other macro-unit.
  • two macrocells in the same group can perform the same function.
  • the grouping may be the classification of macro-units according to their functional relationship and/or mutual connection relationship during integrated circuit design.
  • the connection relationship may include direct connection and indirect connection, and when two macrounits need to be directly connected, the two macrounits may be divided into a group; wherein, the direct connection refers to the connection point of two macrounits Directly connected, not through connection points of other macrocells or other common nodes; indirect connection means that two macrocells need to be connected through other circuit cells.
  • the macrocells in the netlist data can be divided into multiple groups, and each group includes one or more macrocells. Referring to FIG. 10 , in the current layout shown in FIG. 10 , macrocell A and macrocell B have been laid out.
  • the obtained legal placement positions can include the three shown in FIG. 10 .
  • the angular position marked by 3 is formed by the vertices of the macrounit B, the angular position marked by 3 is taken as A legal placement.
  • the macro cells when designing the netlist data of an integrated circuit, can be divided into groups. Therefore, in order to improve the layout quality of the integrated circuit, when selecting the legal placement position of the layout macro cells, select the macro cells belonging to the same group The angular position formed by the vertices of the element.
  • condition 2 it may be determined whether two macrounits overlap according to the distance between the center points of the two macrounits in the current layout. Specifically, the distances D L and D W between the center points of macrocell B and macrocell C in the macrocell length and width directions as shown in Figure 7b can be calculated, when D L is less than the sum of the lengths of the two macrocells When D W is less than half of the sum of the lengths of the two macrounits, it can be determined that macrounit B and macrounit C overlap, and at the same time, it can be determined that the position of macrounit C is not a legal placement position. Wherein, DL and D W can be obtained by calculating the coordinates of the center points of the two macrocells .
  • condition 3 it can be judged whether a floating area is generated by judging whether a side of the macrocell coincides with the height line completely. Specifically, when one side of the macro-unit completely coincides with the height line, the macro-unit does not generate a floating area; otherwise, a floating area is generated.
  • the height line can be determined by the coordinates of the two endpoints.
  • the height line includes the partial line segments of the four sides of the blank layout and the line segments obtained by transforming the coordinates of the partial line segments of the four sides.
  • a height line is included on the Bottom side (the height line is determined according to the coordinates of the two endpoints of the Bottom side, and the thick line represents the height line), when the macro unit A is placed on the Bottom side , when it is judged that the two endpoints of the lower side of the macro unit A fall on the Bottom side, that is, the lower side of the macro unit A coincides with the height line on the Bottom side.
  • the two endpoints below the macro unit A are respectively one endpoint of the left height line and the right height line, and the two endpoints of the middle height line according to The coordinates of the two endpoints of macrounit A and the height of macrounit A are determined, that is, the height line of the overlapping part is moved to the height of macrounit A.
  • the layout position (dotted line frame B) of placing macrounit B is located at the corner position formed by the upper left vertex of macrounit A, when macrounit B is placed at this layout position (dashed line box B), from Fig. It can be seen from 11b that the upper side of the macro unit B does not completely coincide with the middle height line, which indicates that the layout position (dotted line box B) is not a legal placement position.
  • condition 4 it may be determined whether two macro-units form a closed area according to the solid direction or solid area of the two macro-units. Specifically, when the two macrounits have at least one solid direction that is the same, or the solid regions of the two macrounits have a common area, the two macrounits do not generate a closed area; otherwise, the two macrounits generate a closed area.
  • the solid direction of the macrounit refers to the direction of the side where the macrounit coincides with the height line, which can include up, down, left and right; for example, when the lower side of macrounit A overlaps with the height line, the solid direction of macrounit A
  • the direction is down; it can be understood that one or more solid directions can exist in a macro unit, and there are at most four solid directions.
  • the solid area of a macro unit refers to the area between the side where the macro unit coincides with the height line and the side of the first area; for example, when the lower side of macro unit A coincides with the height line of the Bottom side of the first area, the macro unit
  • the solid area of unit A is the area between the lower side of macro unit A and the Bottom side of the first area; it can be understood that one macro unit can have one or more solid areas, and there are at most four solid areas; especially , the macro unit may not have a solid area, that is, one side of the macro unit coincides with any side of the first area.
  • the edges of the first region may include Top edges, Bottom edges, Left edges, and Right edges as shown in FIG. 1 .
  • the solid direction of the macro unit A that has been laid out is down (area a is the solid area of the macro unit A), and when the macro unit C to be laid out is placed in the layout position shown in the dotted line box C, the direction of the macro unit C
  • the solid direction is right (there is no solid area in macro unit C), and if the solid directions of the two macro units are different, it can be judged that macro unit A and macro unit C will form a closed area, and the layout position shown by the dashed box C is not a macro unit The legal placement of C.
  • unit C does not overlap, it can be judged that the two macrounits generate a closed area, and the layout position shown by the dotted box C is not the legal placement position of macrounit C; on the contrary, as shown in Figure 12c, the layout position of macrounit A
  • the solid area a does not overlap with the macro unit C, but the solid area c of the macro unit C (the area between the lower side of the macro unit C and the Bottom side) coincides with the macro unit A, then it can be judged that the macro unit A and the macro unit C do not overlap.
  • a closed area is generated, and the layout position shown by the dotted box C is the legal placement position of the macro unit C.
  • condition 5 it can be determined by the number of the macrocell whether the macrocell that has been placed and the macrocell to be placed belong to the same group, and if they belong to the same group, the angular position formed by the vertices of the macrocell that has been placed is taken as the legal position place.
  • each macrocell included in each group in the netlist data can be numbered. When the number of the macrocell that has been placed and the number of the macrocell to be placed are in one group, it can be considered that the macrocell to be placed is Belongs to the same group as the placed macrocell.
  • step S503 the current layout and multiple legal placement positions are input into the layout prediction model to obtain the output of the layout prediction model.
  • multiple legal placement positions can be marked differently, and then the current layout and the markings corresponding to the multiple legal placement positions can be input into the layout prediction model to obtain the output of the layout prediction model.
  • a probability distribution of multiple legal placement positions wherein the probability distribution includes a placement probability corresponding to each legal placement position.
  • the layout prediction model may include the aforementioned policy network and value network, wherein the policy network and value network may specifically be any type of neural network, such as a convolutional neural network.
  • the type of the network is specifically limited, as long as the function of predicting the probability distribution of legal placement positions in this application can be realized.
  • the evaluation index may include one or more of the aforementioned indexes, for example, in wire length (wire length), congestion (congestion), timing (timing), maximum delay (WNS) and total delay (TNS)
  • wire length wire length
  • congestion congestion
  • timing timing
  • WTS maximum delay
  • TMS total delay
  • One or more may also include other evaluation indicators about integrated circuit layout not disclosed in this application, which are not specifically limited in this embodiment of this application.
  • step S504 based on the output of the layout prediction model, the position of the macro unit to be laid out is obtained.
  • the agent samples each legal placement position as the position of the macro unit to be laid out, that is, the agent's current Actions.
  • the probability distribution includes a placement probability corresponding to each legal placement position, that is, a legal placement position corresponds to a probability value.
  • the command random.choices in the python language can be used to implement position sampling, the parameter population in the command random.choices is set to a list of numbers of legal placement positions, and the parameter weights is set to each legal placement position probability, execute this command to get the serial number of the collected legal placement position, so as to obtain the position of the macrocell to be placed.
  • each legal placement is drawn as The possibilities are different. If the probability of legal placement 5 is the highest, then the probability of legal placement 5 being drawn is the greatest. Referring to FIG. 14 , assuming that the legal placement position 5 is obtained by sampling, the legal placement position 5 is taken as the position of the macro unit to be placed, and the macro unit to be placed is placed at this position. It can be understood that when sampling the 6 legal placement positions based on the probabilities of the aforementioned assumptions, other legal placement positions other than the legal placement position 5 may also be drawn.
  • the embodiment of the present application is not limited to determining the placement position of the macro unit by means of probability sampling, and may also use various decision-making methods to obtain the placement position of the macro unit from legal placement positions.
  • the legal placement position with the highest probability in the probability distribution may be used as the placement position of the macro-unit to be laid out. That is, in one example, after the layout prediction model obtains the probabilities corresponding to the six legal placement positions assumed in Figure 14 above, it is judged that the placement probability of the legal placement position 5 is the highest, that is, the legal placement position 5 can be selected as the waiting position.
  • the placement of layout macrocells is not limited to determining the placement position of the macro unit by means of probability sampling, and may also use various decision-making methods to obtain the placement position of the macro unit from legal placement positions.
  • the legal placement position with the highest probability in the probability distribution may be used as the placement position of the macro-unit to be laid out. That is, in one example, after the layout prediction model obtains the probabilities corresponding to the six legal placement positions assumed in Figure
  • step S505 it is judged whether the layout of the macro-unit is completed, and when the layout is completed, step S606 is performed, and when the layout is not completed, step S501 is performed.
  • this step it may be determined whether the layout of the macrocells of the integrated circuit is completed by comparing the number of macrocells already placed with the number of macrocells in the netlist data. Specifically, when the number of macrocells that have been placed is less than the number of macrocells in the netlist data, it means that the layout of the macrocells has not ended, and there are remaining macrocells that have not been laid out, then return to step S501 to lay out the next macrocell; When the number of cells is equal to the number of macrocells in the netlist data, it indicates that all macrocells in the netlist data have been laid out, and the layout of macrocells is completed, and step S506 is executed.
  • step S506 an evaluation index of the current layout is calculated.
  • index evaluation is performed on the current layout according to the set evaluation index.
  • the standard cell arrangement and routing arrangement are performed in the current layout according to the netlist data, and then the evaluation index of the current layout is calculated.
  • step S507 the parameters of the layout prediction model are updated according to the evaluation index.
  • the obtained evaluation index value is used as the reward of the agent after multiple actions, and the parameters of each node in the layout prediction model are adjusted according to the reward, and then the layout prediction model after the updated parameters is used for the next training , repeat this process until the end of training.
  • the evaluation index of the current layout can be calculated as the reward for the action of the agent, and then the rewards after multiple actions of the agent can be accumulated. Get the agent's reward after multiple actions.
  • the layout device 100 can perform multiple trainings on the layout prediction model, and calculate the evaluation index after each training, and update the layout prediction model according to the layout result of the integrated circuit obtained in this training and its evaluation index. Parameters, when the set number of trainings is completed, among the layout results obtained by multiple trainings, a layout result with the best layout quality is selected according to the evaluation index of each training to output, so as to obtain the layout of the final integrated circuit.
  • the layout apparatus 100 may determine whether to terminate the training of the layout prediction model based on any training termination criterion.
  • the training process of the layout prediction model may be terminated by judging whether the parameter values of each node of the layout prediction model converge.
  • FIG. 15 is a flowchart of a method for layout of circuit units of an integrated circuit using a layout prediction model provided by an embodiment of the present application, and the method is applied to the layout device 100 . As shown in FIG. 15 , the method includes the following steps S1501 to S1504.
  • the layout prediction model outputs a prediction result based on the current layout and multiple legal placement positions.
  • step S1501-step S1504 for the specific introduction of step S1501-step S1504, refer to the description in the foregoing steps S501-S504, and details are not repeated here. Repeat the above step S1501-step S1504 to arrange the layout of each macrocell in the netlist data, and then the macrocell layout of the integrated circuit can be completed.
  • the method steps in the foregoing method embodiments can also be used, the difference lies in the difference of the first condition, wherein the first condition can be set according to actual needs, and this application does not limit the first The details of the conditions.
  • the first condition is used to obtain the legal placement position of the circuit unit (such as a macro unit) to be placed in the layout area, and the placement prediction model corresponding to each legal placement position is obtained by using the layout prediction model trained by reinforcement learning.
  • Putting the probability distribution, so as to sample a position in the legal placement position as the placement position of the current macro unit, can improve the layout quality of the macro unit in the integrated circuit, thereby improving the overall layout quality of the integrated circuit.
  • the present application further provides a layout device 100 , which is configured to implement each step in the above-mentioned method embodiment.
  • the functions of the layout device 100 may be realized by a software system, may also be realized by a hardware device, and may also be realized by a combination of a software system and a hardware device.
  • the layout device 100 When the layout device 100 is a software device, the layout device 100 can be logically divided into multiple modules, and each module can have different functions. Referring to FIG. 16 , the layout device 100 may include: an acquisition module 101 , a first determination module 102 , a prediction module 103 and a second determination module 104 . It can be understood that the embodiment of the present application only exemplifies the division of the structure and function modules of the layout device 100, and does not make any limitation on its specific division. Therefore, in other possible embodiments, the layout device 100 can also be logically divided into Divide into other number of modules.
  • the embodiment of the present application also provides another integrated circuit unit layout device, the device 100 includes: one or more processors and a transmission interface; wherein, the one or more processors are configured to call the The computer instructions cause the device to execute the steps and optional steps in the method embodiments of the present application.
  • the layout apparatus 100 may be a computing device.
  • Fig. 17 is a schematic structural diagram of a computing device provided by an embodiment of the present application.
  • the computing device 200 includes: at least one central processing unit (Central Processing Unit, CPU), memory, and the type of memory may include, for example, Static Random-Access Memory (Static Random-Access Memory, SRAM) and Read-Only Memory (Read-Only Memory). , ROM), microcontroller (Micro controller Unit, MCU), wireless local area network (Wireless Local Area Network, WLAN) subsystem, bus, transmission interface, etc.
  • the computing device 200 may also include other dedicated processors such as an application processor (Application Processor, AP), NPU, and other power management subsystems, clock management subsystems, and power management subsystems. subsystem.
  • the connectors include various interfaces, transmission lines or buses, etc. These interfaces are usually electrical communication interfaces, but may also be mechanical interfaces or other forms of interfaces. This embodiment does not limit it.
  • the CPU can be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor; optionally, the CPU can be a processor group composed of a plurality of processors, and between a plurality of processors are coupled to each other by one or more buses.
  • the CPU implements the circuit unit layout method of the integrated circuit as in the foregoing method embodiments by calling program instructions stored in the on-chip memory or the off-chip memory.
  • the CPU and the MCU jointly implement the circuit unit layout method of any integrated circuit as in the foregoing method embodiments, for example, the CPU completes some steps in the circuit unit layout method, and the MCU completes the circuit unit layout other steps in the method.
  • the AP or other special-purpose processor implements any one of the circuit unit layout methods in the foregoing method embodiments by calling program instructions stored in the on-chip memory or off-chip memory.
  • the transmission interface can be an interface for receiving and sending data of the processor chip, and the transmission interface usually includes multiple interfaces.
  • the transmission interface can include an internal integrated circuit (Inter-Integrated Circuit, I2C) Interface, Serial Peripheral Interface (SPI), Universal asynchronous receiver-transmitter (UART) interface, General-purpose input/output (GPIO) interface, etc. It should be understood that these interfaces may implement different functions by multiplexing the same physical interface.
  • the transmission interface may also include High Definition Multimedia Interface (HDMI), V-By-One interface, Embedded Display Port (EDP), mobile industry processing Interface (Mobile Industry Processor Interface, MIPI) or Display Port (DP), etc.
  • HDMI High Definition Multimedia Interface
  • V-By-One interface V-By-One interface
  • EDP Embedded Display Port
  • MIPI Mobile Industry Processor Interface
  • DP Display Port
  • the above parts are integrated on the same chip; in another optional situation, the memory may be an independent chip.
  • a WLAN subsystem may include, for example, radio frequency circuits and a baseband.
  • the chip involved in the embodiment of this application is a system manufactured on the same semiconductor substrate by an integrated circuit process, also called a semiconductor chip, which can be fabricated on a substrate (usually a semiconductor such as silicon) by using an integrated circuit process.
  • the integrated circuit may include various functional devices, and each type of functional device includes transistors such as logic gate circuits, Metal-Oxide-Semiconductor (MOS) transistors, bipolar transistors or diodes, and may also include capacitors, resistors, etc. or other components such as inductors.
  • MOS Metal-Oxide-Semiconductor
  • bipolar transistors or diodes may also include capacitors, resistors, etc. or other components such as inductors.
  • Each functional device can work independently or under the action of necessary driver software, and can realize various functions such as communication, calculation, or storage.
  • processor in the embodiment of the present application may be a central processing unit (central processing unit, CPU), and may also be other general purpose processors, digital signal processors (digital signal processor, DSP), application specific integrated circuits ( application specific integrated circuit (ASIC), field programmable gate array (field programmable gate array, FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof.
  • CPU central processing unit
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • a general-purpose processor can be a microprocessor, or any conventional processor.
  • the method steps in the embodiments of the present application may be implemented by means of hardware, or may be implemented by means of a processor executing software instructions.
  • the software instructions can be composed of corresponding software modules, and the software modules can be stored in random access memory (random access memory, RAM), flash memory, read-only memory (read-only memory, ROM), programmable read-only memory (programmable rom) , PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrically erasable programmable read-only memory (electrically EPROM, EEPROM), register, hard disk, mobile hard disk, CD-ROM or known in the art any other form of storage medium.
  • An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium.
  • the storage medium may also be a component of the processor.
  • the processor and storage medium can be located in the ASIC.
  • all or part of them may be implemented by software, hardware, firmware or any combination thereof.
  • software When implemented using software, it may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the processes or functions according to the embodiments of the present application will be generated in whole or in part.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in or transmitted via a computer-readable storage medium.
  • the computer instructions may be transmitted from one website site, computer, server, or data center to another website site by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) , computer, server or data center for transmission.
  • the computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server or a data center integrated with one or more available media.
  • the available medium may be a magnetic medium (such as a floppy disk, a hard disk, or a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (solid state disk, SSD)), etc.

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Abstract

本申请提供了一种集成电路的电路单元布局方法及装置，应用于集成电路布局规技术领域。该方法包括：在集成电路的当前布局中获得的可以摆放第一电路单元的合法摆放位置，合法摆放位置需满足第一条件；布局预测模型基于当前布局和合法摆放位置输出预测结果，从而根据该预测结果获得第一区域中摆放第一电路单元的位置；其中，第一条件根据电路单元的摆放规则设定。该方法通过第一条件，获得第一电路单元的合法摆放位置，可提高集成电路的布局质量。

Description

一种集成电路的电路单元布局方法及装置 技术领域
本申请涉及集成电路布局规划技术领域，尤其涉及一种集成电路的电路单元布局方法及装置。
背景技术
集成电路布局是超大规模集成电路(very large integrated circuit，VLSI)的物理设计的一个步骤，主要确定集成电路中各电路单元的摆放位置，进一步可细分为宏单元布局(macro-cell placement，MP)、总体布局和详细布局，其中，MP作为布局阶段的第一步，其布局质量对最终的物理设计指标有着重大的影响。
目前商用MP工具摆放质量较差，其布局结果的评估指标未能满足设计需求。探索自动化、快速且高质量的MP算法对缩短物理设计周期，对提高集成电路的开发效率和布局质量有具有较大意义。
发明内容
为了解决上述的问题，本申请实施例提供了一种集成电路的电路单元布局方法及装置，基于第一条件在集成电路的布局区域中获得电路单元的合法摆放位置，可提高集成电路的布局效率和布局结果质量。
第一方面，本申请实施例提供了一种集成电路的电路单元布局方法，该方法包括：获取集成电路的当前布局；当前布局中包括：未布局电路单元的第一区域；在第一区域中确定用于摆放第一电路单元的多个合法摆放位置；布局预测模型基于当前布局和多个合法摆放位置输出预测结果；根据预测结果，确定第一区域中摆放第一电路单元的位置。
该实施方式，在未布局的区域中获得可以摆放第一电路单元的多个合法摆放位置，根据布局预测模型基于多个合法摆放位置的预测结果获得摆放第一电路单元的位置，把第一电路单元摆放在合法的位置上，可以提高第一电路单元布局的合法性，从而提高集成电路的布局质量；将多个合法摆放位置作为布局预测模型的预测依据，相比于 在这个布局区域中搜寻第一电路单元的位置，缩小了搜寻范围，可以提高集成电路的布局效率。
在一种可能的实施方式中，合法摆放位置包括：合法摆放位置位于第一区域的角位置和/或第一区域的边缘位置。
该实施方式，将第一区域的角位置和/或边缘位置作为合法摆放位置，可以实现电路单元靠边或靠角摆放的目的，可以提升布局质量。
在一种可能的实施方式中，角位置包括基于当前布局中已布局的电路单元的顶点构成的角位置和/或第一区域的顶点构成的角位置。
该实施方式，将已布局电路单元的顶点和/或第一区域的顶点构成的角位置作为合法摆放位置，可以实现电路单元按照靠边或靠角摆放的目的，可以提升布局质量；其中，将已布局电路单元的顶点构成的角位置作为合法摆放位置，当第一区域的顶点构成的角位置被占用时，可以有序摆放电路单元，从而提升电路布局质量。
在一种可能的实施方式中，合法摆放位置还包括满足如下中的至少一项的位置：合法摆放位置摆放第一电路单元后，第一电路单元与当前布局中已布局的电路单元不重叠；合法摆放位置摆放第一电路单元后，第一区域不产生悬空区域；合法摆放位置摆放第一电路单元后，第一区域不产生封闭区域；或合法摆放位置位于第一区域中，与第一电路单元属于同一分组的已布局的电路单元的顶点构成的角位置；其中，同一分组中的多个电路单元的功能具有相关性。
该实施方式，将电路单元不重叠以及摆放区域不产生悬空和不产生封闭的位置作为合法摆放位置，可以避免布局后的集成电路中出现电路单元重叠、悬空区域和封闭区域的情况，降低布局质量；将属于同一分组的已布局电路单元的顶点构成的角位置作为合法摆放位置，可以实现同一分组的单元摆放在一起的目的，当按照电路单元的功能进行分组时，可以使电路单元更加合理摆放，从而提高电路布局质量。
在一种可能的实施方式中，布局预测模型的输出为多个合法摆放位置中各个合法摆放位置的概率，根据预测结果，确定第一区域中摆放第一电路单元的位置包括：根据多个合法摆放位置中各个合法摆放位置的概率，确定第一区域中摆放第一电路单元的位置。
该实施方式，通过布局预测模型预测各个合法摆放位置的摆放概率，进而根据各个概率确定第一电路单元的位置，可以使得第一电路单元在布局中的位置更加合理。
在一种可能的实施方式中，根据多个合法摆放位置中各个合法摆放位置的概率， 确定第一区域中摆放第一电路单元的位置包括：将多个合法摆放位置中概率最大的合法摆放位置确定为摆放第一电路单元的位置。
该实施方式，选择概率最大的合法摆放位置作为第一电路单元的位置，使得第一电路单元在区域中的摆放位置更加合理，从而提升布局质量。
在一种可能的实施方式中，根据多个合法摆放位置中各个合法摆放位置的概率，确定第一区域中摆放第一电路单元的位置包括：根据多个合法摆放位置中各个合法摆放位置的概率，对多个合法摆放位置进行抽取，获得摆放第一电路单元的合法摆放位置。
该实施方式，基于各合法摆放位置的概率对合法摆放位置进行采样，获得第一电路单元的位置，从而获得第一电路单元的位置。
在一种可能的实施方式中，第一电路单元包括宏单元。
第二方面，本申请实施例还提供一种集成电路的电路单元布局装置，该装置包括：获取模块，用于获取集成电路的当前布局；当前布局中包括：未布局电路单元的第一区域；第一确定模块，用于在第一区域中确定用于摆放第一电路单元的多个合法摆放位置；预测模块，用于布局预测模型基于当前布局和多个合法摆放位置输出预测结果；第二确定模块，用于根据预测结果，确定第一区域中摆放第一电路单元的位置。
在一种可能的实施方式中，合法摆放位置包括：合法摆放位置位于第一区域的角位置或者第一区域的边缘位置。
在一种可能的实施方式中，角位置包括基于当前布局中已布局的电路单元的顶点构成的角位置和/或第一区域的顶点构成的角位置。
在一种可能的实施方式中，合法摆放位置还包括满足如下中的至少一项的位置：合法摆放位置摆放第一电路单元后，第一电路单元与当前布局中已布局的电路单元不重叠；合法摆放位置摆放第一电路单元后，第一区域不产生悬空区域；合法摆放位置摆放第一电路单元后，第一区域不产生封闭区域；或合法摆放位置位于第一区域中，与第一电路单元属于同一分组的已布局的电路单元的顶点构成的角位置；其中，同一分组中的多个电路单元的功能具有相关性。
在一种可能的实施方式中，布局预测模型的输出为多个合法摆放位置中各个合法摆放位置的概率，第二确定模块具体用于：根据多个合法摆放位置中各个合法摆放位置的概率，确定第一区域中摆放第一电路单元的位置。
在一种可能的实施方式中，第二确定模块具体用于：将多个合法摆放位置中概率 最大的合法摆放位置确定为摆放第一电路单元的位置。
在一种可能的实施方式中，第二确定模块具体用于：根据多个合法摆放位置中各个合法摆放位置的概率，对多个合法摆放位置进行抽取，获得摆放第一电路单元的合法摆放位置。
在一种可能的实施方式中，第一电路单元包括宏单元。
第三方面，本申请实施例还提供一种集成电路布局装置，装置包括：处理器和传输接口，处理器被配置为调用存储在存储器中的程序指令，以使得集成电路布局装置上述第一方面及其可选实施方式中的方法。
第四方面，本申请实施例还提供一种计算设备，该计算设备包括：存储器和处理器，存储器存储有计算机指令，处理器执行计算机指令时，实现上述第一方面及其可选实施方式中的方法。
第五方面，本申请实施例还提供一种计算机可读存储介质，该计算机可读存储介质存储有计算机程序代码，当计算机程序代码被计算设备执行时，实现上述第一方面及其可选实施方式中的方法。
第六方面，本申请实施例还提供一种包含指令的计算机程序产品，当指令被计算机或处理器执行时，使得所述计算机或所述处理器实现上述第一方面及其可选实施方式中的方法。
上述的第二方面至第六方面所获得的技术效果与第一方面中对应的技术手段获得的技术效果近似，在这里不再赘述。
附图说明
图1是本申请提供的一种宏单元布局结果示意图；
图2是本申请提供的一种强化学习训练示意图；
图3是本申请提供的一种宏单元布局示意图；
图4是本申请实施例提供的一种集成电路布局方法流程图；
图5是本申请实施例提供的一种训练布局预测模型的方法流程图；
图6a和图6b是本申请实施例提供的一种空白布局中合法摆放位置位于边缘位置的示意图；
图6c是本申请实施例提供的一种空白布局中角位置的示意图；
图6d是本申请实施例提供的一种空白布局中合法摆放位置位于角位置的示意图；
图6e是本申请实施例提供的一种非空白布局中角位置的示意图；
图6f和图6g是本申请实施例提供的一种非空白布局中合法摆放位置的示意图；
图7a是本申请实施例提供的宏单元不产生重叠的布局示意图；
图7b是本申请实施例提供的宏单元产生重叠的布局示意图；
图8是本申请实施例提供的悬空区域的布局示意图；
图9是本申请实施例提供的封闭区域的布局示意图；
图10是本申请实施例提供的两个宏单元属于同一分组的布局示意图；
图11a是本申请实施例提供的摆放宏单元前后高度线的变化示意图；
图11b是本申请实施例提供的宏单元后产生悬空区域的布局示意图
图12a和图12b是本申请实施例提供的两个宏单元产生封闭区域的布局示意图；
图12c是本申请实施例提供的两个宏单元不产生封闭区域的布局示意图；
图13是本申请实施例提供的对合法摆放位置进行标记的示意图；
图14是本申请实施例提供的根据概率分布采样得到摆放位置的示意图；
图15是本申请实施例提供的利用布局预测模型进行电路单元布局的方法流程图；
图16是本申请实施例提供的一种布局装置的装置结构示意图；
图17是本申请实施例提供的一种计算设备的结构示意图。
具体实施方式
为了使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本申请实施例中的技术方案进行描述。
在本申请实施例的描述中，“示例性的”、“例如”或者“举例来说”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”、“例如”或者“举例来说”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”、“例如”或者“举例来说”等词旨在以具体方式呈现相关概念。
在本申请实施例的描述中，术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，单独存在B，同时存在A和B这三种情况。另外，除非另有说明，术语“多个”的含义是指两个或两个以上。例如，多个系统是指两个或两个以上的系统，多个屏幕终端是指两个或两个以上的屏幕终端。"以下至少一项(个)"或其类似表达，是指这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，"a和b"，"a和c"，"b和c"，或"a和b和c"，其中a，b，c可以是单个，也可以是多个。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。术语“包括”、“包含”、“具有”及它们的变形都意味着“包括但不限于”，除非是以其他方式另外特别强调。
在介绍本申请实施例的方案之前，先对本申请实施例中出现的网表数据、宏单元、宏单元布局、标准单元、标准单元排布、绕线排布、评估指标、神经网络和强化学习进行解释。
网表数据，是描述集成电路中各单元连接的数据。其中，可以包括待摆放宏单元(macro-cell)、标准单元(standard-cell)，宏单元和标准单元的连接关系和布局区域。可选地，网表数据还可以包括集成电路的工艺参数等信息。
宏单元(macro-cell)，是由相对逻辑门抽象级别更高的触发器、算术逻辑单元、硬件暂存器等组成的预定义逻辑功能实现单元，在VLSI设计中，这些逻辑单元作为一个宏单元整体被安置在硅片上。每一个宏单元对应的不同的逻辑功能，每一个宏单元还可以对应不同的尺寸。
宏单元布局(macro-cell placement，MP)，是将宏单元放置到布局区域的过程。如图1所示的宏单元布局结果示意图，布局区域看做一个矩形区域，包括上边缘(Top)、下边缘(Bottom)、左边缘(Left)和右边缘(Right)，宏单元编号为b1、b2、…、b17，在布局区域中用小矩形表示。宏单元布局具体可以理解为，将宏单元b1、b2、…、b17，摆放到Top边、Bottom边、Left边和Right边围成的矩形区域中。
标准单元，是微小的基本电路单元，可以包括反相器、与门、寄存器、选择器、全加器等多种单元。同样地，每一个标准单元对应着一个或多个宏单元，可以理解到，多个宏单元中各宏单元的尺寸和驱动能力可以相同，也可以不同，而且各宏单元的尺寸可以是基本尺寸或最小尺寸的整数倍标准单元排布，是指在宏单元布局结束之后，将标准单元摆放在布局区域中未排布macro的区域的过程。
绕线(routing)，是将macro-cell和standard-cell根据连接关系用线连接起来。
评估指标，用于对布局区域的布局结果进行评估。具体可以包括：线长(wire length)：是指布局区域中连接macro-cell和standard-cell的线的总长度；拥塞度(congestion)：是指布局区域中最密集区域的线密度，布局区域中的线不能太过密集；时序(timing)：macro和standard cell连接完毕后，各条路径的时延，包括最大时延(WNS)和总时延(TNS)；应当理解，前述这些指标的数据值越小，当前布局的布局质量就越好。
神经网络(neural network)，是一种数学模型，经过训练之后，神经网络可以在给定输入下输出相应的结果。神经网络具体是一类模仿生物神经网络(动物的中枢神经系统)的结构和功能的数学算法模型。一个神经网络可以包括多种不同功能的神经网络层，每层包括参数和计算公式。根据计算公式的不同或功能的不同，神经网络中不同的层有不同的名称。例如，进行卷积计算的层称为卷积层，卷积层常用于对输入信号(如图像)进行特征提取。一个神经网络模型也可以由多个已有的神经网络模型组合构成。不同结构的神经网络模型可用于不同的场景(如分类、识别等)或在用于同一场景时提供不同的效果。神经网络模型结构不同具体包括以下一项或多项：神经网络模型中网络层的层数不同、各个网络层的顺序不同、每个网络层中的权重、参数或计算公式不同。
强化学习(reinforcement learning，RL)，又称为再励学习、评价学习或增强学习，是机器学习的一种方法，通过智能体在与环境的交互中不断学习，实现智能体的回报最大化，从而达到设定的学习目标。可选地，在实际的应用中，采用的强化学习算法可以采用策略梯度(policy gradient)算法、Q学习(Q-learning)算法、深度Q网络(deep Q network)算法和演员评判(actor critic)算法的任意一种。图2是本申请提供的一种强化学习的流程示意图，如图2所示，在智能体与环境的一次交互学习中，将环境当前的状态输入至预测模型；接着，根据预测模型的输出获得智能体当前的动作；然后，基于智能体当前的动作更新环境当前的状态，完成智能体与环境的一次交互；其中，在将状态输入至预测模型之前，根据智能体上一次动作的奖励和强化学习设定的损失函数更新预测模型的参数，使得智能体下一次的动作可以获得更高的奖励。在一个示例中，在满足智能体与环境的交互次数之后，根据每次交互中环境反馈的奖励值累计智能体的回报，结束智能体的一次强化学习，智能体多次进行强化学习，直至满足终止条件时，结束预测模型的训练。
在一个示例中，该预测模型可以是策略网络，用于根据环境的状态生成智能体的动作策略，智能体从该动作策略对应的动作集合中选择动作；可选地，动作策略可以是动作集合中各个动作对应的概率分布，智能体从概率分布中对各个动作随机采样，从而获得当前动作。当策略网络输出的是概率分布时，策略网络中可以包括一个softmax分类层用于输出相应的概率。该预测模型还可以包括价值网络，用于根据环境的状态计算智能体执行动作的奖励，获得智能体的奖励之后，根据智能体的奖励更新预测模型的参数。
在集成电路布局的一种相关技术中，采用mixed-size进行集成电路布局。该方法具体是将集成电路的布局问题转换为数学规划问题，对宏单元和标准单元的摆放位置进行优化求解。在一个示例中，按照公式(1)将两个电路单元之间的线长和线密度两个评估指标近似为一个优化函数，使用随机优化算法进行规划求解，从而获得满足设计条件的宏单元的摆放位置和标准单元的摆放位置。
Figure PCTCN2021095299-appb-000001
公式(1)中，WL(e,x,y)表示布局中单元x和单元y之间第e条连线的长度，E表示x和y之间连线的总数，D(x,y)表示布局中单元x和单元y之间的线密度，λ 1和λ 2分别为线长指标和线密度的权重。
该相关技术是在整个布局的区域中对宏单元和标准单元的摆放位置进行搜寻和验证，搜索范围较大，布局效率低，而且获得的布局质量差。
在集成电路布局的另一种相关技术中，采用强化学习训练的神经网络获得摆放位置的概率分布来实现宏单元布局。具体的，每次摆放宏单元前，采用神经网络获得当前布局中摆放位置的概率分布，从概率分布中对摆放位置进行采样，获得当前宏单元的摆放位置。如图3所示，利用神经网络获得空白布局S 0中用于摆放宏单元的摆放位置的概率分布，然后从概率分布中对各个摆放位置进行采样，获得一个摆放位置并摆放宏单元(图3中S 1布局中的黑色方块)，这样空白布局S 0随即更新为布局S 1，接着采用同样的方法摆放下一个宏单元，获得布局S 2，重复这个过程，即可完成所有宏单元的布局。
该相关技术虽然可以实现自动化布局宏单元的目的，但在整个区域进行宏单元摆放位置抽取，仍然存在布局结果质量差的问题。
图4是本申请实施例提供的一种集成电路布局方法流程图，该方法应用于布局装置100。如图4所示，该方法通过布局预测模型对集成电路中各电路单元的摆放位置进行预测，从而实现集成电路的布局设计。包括如下的步骤S401-步骤S403。
在步骤S401中，获取集成电路的网表数据。
本实施例中，集成电路的网表数据参见前述介绍，此处不再介绍；集成电路可以是用于集成芯片设计的一个电路组件，也可以是一个完整的集成芯片的电路。其中，一个电路组件或者一个集成芯片可以包括多个电路器件，例如晶体管、电阻器、电容器等器件。集成电路具体可以是实现任意一种功能用途的电路，例如，可以是用于机 器学习计算、视频处理、加密或其他计算密集型功能的应用专用集成电路。
在步骤S402中，根据集成电路的网表数据训练布局预测模型。
在一种可选的方案中，布局预测模型可以通过强化学习算法训练获得，该布局预测模型可以如前述强化学习部分中介绍的预测模型，该布局预测模型的具体训练过程将在下述介绍中结合图5进行详细描述。
在步骤S403中，使用训练好的布局预测模型确定集成电路的布局。
本实施例中，在布局预测模型训练结束之后，采用布局预测模型对集成电路中的第一电路单元的摆放位置进行预测，从而实现集成电路的布局设计，其中，第一电路单元可以是集成电路的宏单元。具体地，本步骤的具体过程将在下述介绍中结合图13进行详细描述。
图5是本申请实施例提供的一种采用强化学习算法训练布局预测模型的方法流程图，该方法应用于布局装置100。该方法基于集成电路的网表数据中的电路单元(包括宏单元和标准单元)、单元连接关系和布局区域参数进行模型训练，在训练过程中，将第一电路单元的摆放位置视为智能体的动作、当前布局中的合法摆放位置视为智能体的动作集合、集成电路的布局视为环境的状态、以及布局的评估指标视为智能体的奖励和回报。下面以第一电路单元为宏单元为例，详细介绍本申请实施例的模型训练过程。
如图5所示，该方法包括如下的步骤S501～步骤S507。
在步骤S501中，获取集成电路的当前布局。
本实施例中，当前布局指的是在集成电路的布局区域中摆放了一个宏单元之后的布局结果，当前布局中可以包括第一区域和第二区域，其中，第一区域可以是当前布局中未布局宏单元的区域，第二区域可以是当前布局中布局了宏单元的区域。可以理解的，若当前布局是集成电路的首次布局时，也就表明当前布局是一个空白布局，即当前布局中仅仅包括前述的第一区域；若当前布局非该集成电路的首次布局时，当前布局中包括了前述的第一区域和第二区域。
在步骤S502中，在集成电路的当前布局中，获得多个合法摆放位置作为候选，合法摆放位置用于摆放待布局的宏单元。
本实施例中，本步骤可以是布局装置100基于预先设定的第一条件，对第一区域中的每一个布局位置进行逐个判断，从而获得满足第一条件的用于摆放待布局宏单元的合法摆放位置。具体地，获得的合法摆放位置的形状大小和待布局宏单元的形状大 小相匹配。在布局过程中，宏单元是一个固定的形态，即宏单元的形状大小不可以进行调整，宏单元也不可以进行旋转和镜像变形等操作。宏单元的形态可以是一个矩形区域，也可以是一个其他类型的多边形区域，在本申请的后续介绍中，均将宏单元视为一个矩形区域来描述。
在一个示例中，第一条件可以是按照宏单元的摆放规则或摆放要求设置的。可以理解，最终获得的合法摆放位置的数量可以是一个，也可以是多个。在一个示例中，当只获得一个合法摆放位置时，可直接将该合法摆放位置作为摆放宏单元的位置。
可选地，第一条件可以包括如下条件1-条件5中的至少一项。
条件1：合法摆放位置位于第一区域的角位置或者第一区域的边缘位置。其中，角位置可以包括基于当前布局中已布局的宏单元的顶点构成的角位置和第一区域的顶点构成的角位置。当合法摆放位置位于一个边缘位置时，合法摆放位置的一条边与该边缘位置重合。当合法摆放位置位于一个角位置时，合法摆放位置的一个顶点与该角位置的交点重合，且合法摆放位置的至少一条边与构成该角位置的一条交线重合。可以理解，一个角位置包括一个交点和至少两条交线。
可以理解，一个边缘位置可以对应一个用于摆放宏单元的合法摆放位置，也可以对应多个用于摆放宏单元的合法摆放位置，具体个数可以根据宏单元的长度和边缘位置的长度确定。
在一个示例中，当宏单元的长度与边缘位置的长度相等时，该边缘位置最多对应一个用于摆放该宏单元的合法摆放位置；如图6a所示，当前布局为一个如前述图1所示的方形区域，在当前布局中，当宏单元A的长度与Top边的长度相等时，Top边最多对应一个用于摆放宏单元A的合法摆放位置。
在一个示例中，当宏单元的长度小于边缘位置的长度时，该边缘位置可以对应多个用于该宏单元的合法摆放位置；如图6b所示，当宏单元A的长度小于Top边的长度时，Top边可以对应多个用于摆放宏单元A的合法摆放位置(图6b中只是示例性的给出了三个位置)。
可以理解，当角位置为第一区域的顶点构成的角位置时，该角位置最多对应一个用于摆放宏单元的合法摆放位置；当角位置为第一区域的已布局宏单元的顶点构成的角位置时，该角位置可以对应多个用于摆放宏单元的合法摆放位置。具体地，在当前布局是空白布局时，第一区域的角位置只包括第一区域的顶点构成的角位置；相应的，当前布局非空白布局时，第一区域的角位置还可以包括前述基于当前布局中已布局的 宏单元的顶点构成的角位置和第一区域的顶点构成的角位置。
在一个示例中，如图6c所示，空白布局可以是一个如前述图1所示的方形区域，在空白布局为当前布局时，当前布局的第一区域可以是如图6c所示的灰色区域，该第一区域除了包括四个边缘位置之外，还包括由其自身的四个顶点构成的角位置(五角标识)，每个角位置上仅可以存在一个用于摆放待布局宏单元的合法摆放位置。以用于摆放宏单元A为例，四个角位置上的合法摆放位置(虚线框A)如图6d所示。
在一个示例中，当在图6d中选择一个合法摆放位置摆放宏单元A之后，图6c所示的空白布局更新为如图6e所示的非空白布局。与图6c相比，图6e所示的当前布局中的第一区域的边缘位置的数量和角位置的数量发生了变化；其中，边缘位置包括如图6e所示的第一区域(灰色区域)的边缘位置，角位置在图6c所示的基础上，增加了宏单元A的顶点构成的角位置，即图6e中标号为①-⑦的角位置。可以理解，图6e中宏单元A的左下顶点和空白布局的最下顶点重合，因此这两个顶点只构成了一个角位置。其中，已摆放宏单元B为例，对于角位置②③④⑥，这个四个角位置上分别只可以存在一个合法摆放位置，具体示例参照图6d；对于角位置①⑤，这两个角位置上分别可以存在两个合法摆放位置，且位于角位置中交点的两侧，具体示例参照图f；对于角位置⑦，该角位置上可以存在四个合法摆放位置，且位于该角位置的交线形成的四个方向(左上、左下、右上和右下)，具体示例参照图6g。
条件2：合法摆放位置摆放宏单元后，宏单元与当前布局中已布局的宏单元不重叠。此条件适用于当前布局非空白布局的示例中。参照图7a和图7b进行示例性说明。在图7a中，宏单元A为已布局的宏单元，且摆放宏单元B的布局位置(虚线框B)位于单元A的一个顶点构成的角位置上(图7a中的五角标记)，当宏单元B摆放在该位置时，宏单元B不会和宏单元A产生重叠，因此，该布局位置(虚线框B)是一个合法摆放位置；对于图7b来说，宏单元A和B为已布局单元，且摆放宏单元C的布局位置(虚线框C)位于单元A的一个顶点构成的角位置上(图7a中的五角标记)，当宏单元C摆放在该布局位置(虚线框C)时，宏单元C会和宏单元B产生重叠，因此，该布局位置(虚线框C)不是合法摆放位置。
条件3：合法摆放位置摆放宏单元后，第一区域中不产生悬空区域。此条件同样适用于当前布局为非空白布局的示例中。参照图8，布局位置(虚线框B)位于图8所示角位置上，在布局位置(虚线框B)摆放宏单元B之后，在单元B的下方、单元A的右侧会产生悬空区域，因此，该布局位置(虚线框B)不是一个合法的摆放位置。
条件4：合法摆放位置摆放宏单元后，第一区域中不产生封闭区域。此条件同样适用于当前布局为非空白布局的示例中。参照图9，布局位置(虚线框C)位于图8所示角位置上，在布局位置(虚线框C)摆放宏单元C之后，在宏单元C的下方和宏单元A的右侧会产生封闭区域，因此，该布局位置(虚线框C)不是一个合法的摆放位置。
条件5：合法摆放位置位于第一区域中，与待布局的宏单元属于同一分组的已布局的宏单元构成的角位置，其中，同一分组中的宏单元的功能存在相关性。此条件同样适用于当前布局为非空白布局的示例中。可以理解，宏单元的功能存在相关性是指两个电路单元中一个宏单元实现自身功能时，需要另一个宏单元的数据或信息。在一个示例中，同一分组中的两个宏单元可以实现相同的功能。
在一个示例中，分组可以是在集成电路设计时，按照宏单元的功能关系和/或彼此的连接关系对宏单元划分的类别。在一个示例中，连接关系可以包括直接连接和间接连接，当两个宏单元需要直接连接时，可以将这两个宏单元划分为一个分组；其中，直接连接是指两个宏单元的连接点直接相连，不通过其他宏单元的连接点或其他公共节点连接；间接连接则是两个宏单元需要通过其他电路单元连接。可以理解的，网表数据中的宏单元可以被划分为多个分组，每个分组包括一个或多个宏单元。参照图10，在图10所示的当前布局中已经布局摆放了宏单元A和宏单元B，在摆放宏单元C的时候，假设获得的合法摆放位置可以包括图10中示出的三个五角标识的位置(①～③)，当判断出宏单元B和宏单元C属于同一分组时，由于③所标记的角位置是宏单元B的顶点构成的，所以将③所标记的角位置作为一个合法摆放位置。
在一个示例中，设计集成电路的网表数据时，可以将宏单元进行分组划分，因此，为提高集成电路的布局质量，在选取布局宏单元的合法摆放位置时，选取属于同一分组的宏单元的顶点构成的角位置。
在一个示例中，对于条件2，可以通过两个宏单元在当前布局中的中心点的距离判断两个宏单元是否重叠。具体地，可以计算如图7b中所示的宏单元B和宏单元C的中心点在宏单元长和宽两个方向上的距离D L和D W，当D L小于两个宏单元长度之和的一半、或者D W小于两个宏单元长度之和的一半时，可以判断出宏单元B和宏单元C发生了重叠，同时，可以判断出宏单元C所在位置不是合法摆放位置。其中，D L和D W可以通过两个宏单元中心点的坐标计算获得。
在一个示例中，对于条件3，可以通过判断宏单元的一条边是否与高度线完全重 合，来判断是否产生了悬空区域。具体地，当宏单元的一条边与高度线完全重合时，该宏单元不产生悬空区域，否则，产生悬空区域。高度线可以由两个端点的坐标确定，具体可以根据空白布局中的四条边、四条边的部分线段、或四条边的部分线段经过坐标变换获得的线段确定；其中，在空白布局中，高度线包括空白布局的四条边；在非空白布局中，高度线包括空白布局的四条边的部分线段和四条边的部分线段经过坐标变换获得的线段。
如图11a所示，在空白布局中Bottom边上包括一条高度线(该高度线根据Bottom边的两个端点的坐标确定，粗线条表示高度线)，当在Bottom边上摆放了宏单元A之后，当判断宏单元A下边的两个端点落在Bottom边上时，即宏单元A的下边与Bottom边上的高度线重合，此时，Bottom边上包括三条高度线，每一条高度线都可以由两个端点的坐标确定。继续参阅图11a，当用XY坐标系表示当前布局中的点坐标时，宏单元A下边的两个端点分别为左侧高度线和右侧高度线的一个端点，中间高度线的两个端点根据宏单元A的两个端点的坐标和宏单元A的高度来确定，也即重合部分的高度线上移至宏单元A的高度处。参阅图11b，摆放宏单元B的布局位置(虚线框B)位于在宏单元A的左上方顶点构成的角位置，当在该布局位置(虚线框B)摆放宏单元B时，从图11b可以看出，宏单元B的上边与中间高度线未完全重合，则表明布局位置(虚线框B)不是合法摆放位置。
在一个示例中，对于条件4，可以通过根据两个宏单元的实心方向或者实心区域确定两个宏单元是否构成了封闭区域。具体地，当两个宏单元存在至少一个相同的实心方向，或者两个宏单元的实心区域有公共区域时，两个宏单元不产生封闭区域，否则，两个宏单元产生封闭区域。宏单元的实心方向是指宏单元与高度线重合的边的方向，可以包括上、下、左和右；例如，当宏单元A的下侧边与高度线重和时，宏单元A的实心方向为下；可以理解，一个宏单元可以存在一个或多个实心方向，最多有四个实心方向。宏单元的实心区域是指宏单元与高度线重合的边至第一区域的边之间的区域；例如，当宏单元A的下侧边与第一区域的Bottom边的高度线重合时，宏单元A的实心区域即为宏单元A的下侧边至第一区域的Bottom边之间的区域；可以理解，一个宏单元可以存在一个或多个实心区域，最多有四个实心区域；特别地，宏单元也可以不存在实心区域，即宏单元的一个边与第一区域的任意一个边重合。在一个示例中，第一区域的边可以包括如图1所示的Top边、Bottom边、Left边和Right边。
如图12a所示，，已布局宏单元A的实心方向为下(区域a为宏单元A实心区域)， 待布局宏单元C摆放在虚线框C所示的布局位置时，宏单元C的实心方向为右(宏单元C不存在实心区域)，，两个宏单元的实心方向不同，则可判断出宏单元A和宏单元C会构成封闭区域，虚线框C所示的布局位置不是宏单元C的合法摆放位置。如图12b所示，待布局宏单元C摆放在虚线框C所示的布局位置时，宏单元C的实心区域c与已布局宏单元A不重合，且宏单元A的实心区域a与宏单元C也不重合，则可以判断出两个宏单元产生了封闭区域，虚线框C所示的布局位置不是宏单元C的合法摆放位置；相反地，如图12c所示，宏单元A的实心区域a与宏单元C不重合，但宏单元C的实心区域c(宏单元C的下侧边至Bottom边之间的区域)与宏单元A重合，则可以判断宏单元A和宏单元C不产生封闭区域，虚线框C所示的布局位置是宏单元C的合法摆放位置。
在一个示例中，对于条件5，可以通过宏单元的编号确定已布局宏单元与待布局宏单元是否属于同一分组，当属于同一分组时，将已布局宏单元的顶点构成的角位置作为合法摆放位置。示例性的，可以对网表数据中的各个分组中包括的各个宏单元进行编号，当已布局的宏单元的编号和待布局宏单元的编号在一个分组中时，即可认为待布局宏单元和已布局宏单元属于同一分组。
在步骤S503中，将当前布局和多个合法摆放位置输入布局预测模型中，获得布局预测模型的输出。
本实施例中，本步骤具体可以将多个合法摆放位置分别做不同的标记，然后，将当前布局和多个合法摆放位置对应的标记输入到布局预测模型中，获得布局预测模型输出的多个合法摆放位置的概率分布，其中，概率分布包括各个合法摆放位置对应的摆放概率。下面结合图13对上述步骤S503进行说明。
参照图13，先将图12中左图的6个合法摆放位置(虚线框所示)对应的合法摆放位置分别标记不同的编号，如图13中右图所示的编号1～6，然后将当前布局和6个合法摆放位置对应的编号输入到布局预测模型中，获得布局预测模型输出的各个合法摆放位置对应的摆放概率，即前述的概率分布。
可选的，布局预测模型可以包括如前所述的策略网络和价值网络，其中，策略网络和价值网络具体可以是任意一种类型的神经网络，例如卷积神经网络，本申请实施例不对神经网络的类型做具体限定，只要可以实现本申请的预测合法摆放位置的概率分布的功能即可。
可选地，评估指标可以包括前述的一个或多个指标，例如，线长(wire length)、拥 塞度(congestion)、时序(timing)、最大时延(WNS)和总时延(TNS)中一个或多个，还可以包括本申请没有公开的关于集成电路布局的其他评估指标，本申请实施例不做具体限定。
在步骤S504中，基于布局预测模型的输出，获得待布局宏单元的位置。
本实施例中，智能体基于布局预测模型输出的各个合法摆放位置对应的概率分布，对各个合法摆放位置进行采样一个合法摆放位置，作为待布局宏单元的位置，即获得智能体当前的动作。其中，概率分布包括每个合法摆放位置对应的摆放概率，即一个合法摆放位置对应一个概率值。
在一个示例中，可以使用python语言中的命令random.choices实现位置采样，将命令random.choices中的参数population设置为合法摆放位置的编号的列表，将参数weights设置为每个合法摆放位置的概率，执行该命令即可获得采到的合法摆放位置的编号，从而获得待布局宏单元的位置。
在一个示例中，假设合法摆放位置1～6的概率分别为0.11、0.1、0.13、0.16、0.3、0.2，在合法摆放位置1～6中采样时，每个合法摆放位置被抽到的可能性不同，合法摆放位置5的概率最大，则合法摆放位置5被抽到的可能性最大。参阅图14，假设采样得到合法摆放位置5，则将合法摆放位置5作为待摆放宏单元的位置，将待摆放的宏单元摆放在该位置上。可以理解的，在基于前述假设的概率对6个合法摆放位置进行采样时，还可能抽到除合法摆放位置5之外的其他合法摆放位置。
还可以理解，本申请实施例不限于通过概率采样的方式确定宏单元的摆放位置，还可以采用多种决策方式从合法摆放位置中获得宏单元的摆放位置。例如，可以将概率分布中概率最大的合法摆放位置作为待布局宏单元的摆放位置。即在一个示例中，在布局预测模型获得前述图14假设的6个合法摆放位置对应的概率之后，判断出合法摆放位置5的摆放概率最大，即可以选择合法摆放位置5作为待布局宏单元的摆放位置。
可选地，在步骤S505中，判断宏单元布局是否结束，当布局结束时，执行步骤S606，当布局未结束时，执行步骤S501。
本实施例中，本步骤可以通过比较已布局宏单元的数量和网表数据中的宏单元数量，来判断集成电路的宏单元布局是否结束。具体地，当已布局宏单元的数量小于网表数据中的宏单元数量时，说明宏单元布局未结束，还有剩余宏单元未布局，则返回步骤S501布局下一个宏单元；当已布局宏单元的数量等于网表数据中的宏单元数量时， 表明网表数据中的宏单元已经全部被布局摆放，宏单元布局结束，执行步骤S506。
可选地，在步骤S506中，计算当前布局的评估指标。
本实施例中，在将网表数据中的宏单元全部布局摆放之后，按照设定的评估指标对当前布局进行指标评估。
在一个示例中，在将网表数据中的宏单元全部布局摆放之后，先按照网表数据在当前布局中进行标准单元排布和绕线排布，然后计算当前布局的评估指标。
可选地，在步骤S507中，根据评估指标更新布局预测模型的参数。
本实施例中，将获得的评估指标值，作为智能体在多次动作后的回报，根据该回报调整布局预测模型中各个节点的参数，然后将更新参数后的布局预测模型用于下一次训练，重复这个过程，直至训练结束。
在一个示例中，可以在摆放了一个宏单元之后即智能体做出一次动作之后，计算当前布局的评估指标，作为智能体该次动作的奖励，然后累计智能体多次动作后的奖励，获得智能体在多次动作后的回报。
在一个示例中，布局装置100可以对布局预测模型进行多次训练，并在每次训练结束后计算评估指标，并根据该次训练获得的集成电路的布局结果及其评估指标，更新布局预测模型的参数，当完成设定的训练次数时，在多次训练获得的布局结果中，根据每次训练的评估指标选择一个布局质量最好的布局结果输出，从而获得结束集成电路的布局。在一个示例中，布局装置100可以基于任何一种训练终止标准来确定是否终止训练布局预测模型。可选地，可以通过判断布局预测模型各个节点的参数值是否收敛，来终止布局预测模型的训练过程。
图15是本申请实施例提供的一种采用布局预测模型进行集成电路的电路单元布局的方法流程图，该方法应用于布局装置100。如图15所示，该方法包括如下的步骤S1501～步骤S1504。
在S1501中，获取集成电路的当前布局。
在S1502中，在集成电路的当前布局中，获得多个合法摆放位置作为候选，合法摆放位置用于摆放待布局的宏单元。
在S1503中，布局预测模型基于当前布局和多个合法摆放位置输出预测结果。
在S1504中，基于布局预测模型输出的预测结果，获得待布局宏单元的位置。
本实施例中，步骤S1501-步骤S1504的具体介绍参见前述步骤S501-S504中的描述，此处不再赘述。重复执行上述步骤S1501-步骤S1504，对网表数据中的各个宏单 元进行布局摆放，即可完成集成电路的宏单元布局。
此外，在集成电路的标准单元排布时，同样可以采用前述方法实施例中的方法步骤，区别在于第一条件的不同，其中，第一条件可以根据实际需要进行设置，本申请不限定第一条件的具体内容。
本申请上述的方法实施例，采用第一条件在布局区域中获得待布局的电路单元(例如宏单元)的合法摆放位置，利用强化学习训练的布局预测模型获得各个合法摆放位置对应的摆放概率分布，从而在合法摆放位置中采样一个位置作为当前宏单元的摆放位置，可以提高集成电路中宏单元的布局质量，从而提高集成电路整体的布局质量。
基于上述图15所示的方法实施例，本申请还提供一种布局装置100，该布局装置100用于实现上述方法实施例中的各个步骤。该布局装置100的功能可以由软件系统实现，也可以由硬件设备实现，还可以由软件系统和硬件设备结合来实现。
当布局装置100为软件装置时，该布局装置100可以在逻辑上分成多个模块，每个模块可以具有不同的功能。参见图16，布局装置100可以包括：获取模块101、第一确定模块102、预测模块103和第二确定模块104。可以理解，本申请实施例仅对布局装置100的结构和功能模块进行示例性划分，并不对其具体划分做任何限定，因此，在其他可能的实施例中，还可以在逻辑上将布局装置100划分为其他数量的模块。
其中，布局装置100各个功能模块具体执行的步骤参见发明内容和前述方法实施例中的描述，此处不再赘述。
本申请实施例还提供另一种集成电路的电路单元布局装置，该装置100包括：一个或多个处理器以及传输接口；其中，该一个或多个处理器被配置为调用存储在存储器中的计算机指令，使得该装置执行本申请方法实施例中的步骤及可选步骤。
当布局装置100为硬件设备时，布局装置100可以是一个计算设备。图17是本申请实施例提供的计算设备的结构示意图。该计算设备200包括：至少一个中央处理器(Central Processing Unit，CPU)，存储器，存储器的类型例如可以包括静态随机存取存储器(Static Random-Access Memory，SRAM)和只读存储器(Read-Only Memory，ROM)，微控制器(Micro controller Unit，MCU)、无线局域网(Wireless Local Area Network，WLAN)子系统、总线、传输接口等。虽然图17中未示出，该计算设备200还可以包括应用处理器(Application Processor，AP)，NPU等其他专用处理器，以及电源管理子系统、时钟管理子系统和功耗管理子系统等其他子系统。
计算设备200的上述各个部分通过连接器相耦合，示例性的，连接器包括各类接 口、传输线或总线等，这些接口通常是电性通信接口，但是也可能是机械接口或其它形式的接口，本实施例对此不做限定。
可选的，CPU可以是一个单核(single-CPU)处理器或多核(multi-CPU)处理器；可选的，CPU可以是多个处理器构成的处理器组，多个处理器之间通过一个或多个总线彼此耦合。在一种可选的情况中，CPU通过调用片上述存储器或者片外存储器中存储的程序指令实现如前述方法实施例中的集成电路的电路单元布局方法。在一种可选的情况中，CPU和MCU共同实现如前述方法实施例中的任一种集成电路的电路单元布局方法，例如CPU完成电路单元布局方法中的部分步骤，而MCU完成电路单元布局方法中的其他步骤。在一种可选的情况中，AP或者其他专用处理器通过调用片上述存储器或者片外存储器中存储的程序指令实现如前述方法实施例中的任一种电路单元布局方法。
该传输接口可以为处理器芯片的接收和发送数据的接口，该传输接口通常包括多种接口，在一种可选的情况下，该传输接口可以包括内部整合电路(Inter-Integrated Circuit，I2C)接口、串行外设接口(Serial Peripheral Interface，SPI)、通用异步收发机(Universal asynchronous receiver-transmitter，UART)接口、通用输入输出(General-purpose input/output，GPIO)接口等。应当理解，这些接口可以是通过复用相同的物理接口来实现不同的功能。
在一种可选的情况中，传输接口还可以包括高清晰度多媒体接口(High Definition Multimedia Interface，HDMI)、V-By-One接口、嵌入式显示端口(Embedded Display Port，eDP)、移动产业处理器接口(Mobile Industry Processor Interface，MIPI)或Display Port(DP)等。
在一种可选的情况中，上述各部分集成在同一个芯片上；在另一种可选的情况中，存储器可以是独立存在的芯片。
WLAN子系统例如可以包括射频电路和基带。
在本申请实施例中涉及的芯片是以集成电路工艺制造在同一个半导体衬底上的系统，也叫半导体芯片，其可以是利用集成电路工艺制作在衬底(通常是例如硅一类的半导体材料)上形成的集成电路的集合，其外层通常被半导体封装材料封装。所述集成电路可以包括各类功能器件，每一类功能器件包括逻辑门电路、金属氧化物半导体(Metal-Oxide-Semiconductor，MOS)晶体管、双极晶体管或二极管等晶体管，也可包括电容、电阻或电感等其他部件。每个功能器件可以独立工作或者在必要的驱动软 件的作用下工作，可以实现通信、运算、或存储等各类功能。
可以理解的是，本申请实施例中的处理器可以是中央处理单元(central processing unit，CPU)，还可以是其他通用处理器、数字信号处理器(digital signal processor，DSP)、专用集成电路(application specific integrated circuit，ASIC)、现场可编程门阵列(field programmable gate array，FPGA)或者其他可编程逻辑器件、晶体管逻辑器件，硬件部件或者其任意组合。通用处理器可以是微处理器，也可以是任何常规的处理器。
本申请的实施例中的方法步骤可以通过硬件的方式来实现，也可以由处理器执行软件指令的方式来实现。软件指令可以由相应的软件模块组成，软件模块可以被存放于随机存取存储器(random access memory，RAM)、闪存、只读存储器(read-only memory，ROM)、可编程只读存储器(programmable rom，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM，EEPROM)、寄存器、硬盘、移动硬盘、CD-ROM或者本领域熟知的任何其它形式的存储介质中。一种示例性的存储介质耦合至处理器，从而使处理器能够从该存储介质读取信息，且可向该存储介质写入信息。当然，存储介质也可以是处理器的组成部分。处理器和存储介质可以位于ASIC中。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者通过所述计算机可读存储介质进行传输。所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘(solid state disk，SSD))等。
可以理解的是，在本申请的实施例中涉及的各种数字编号仅为描述方便进行的区分，并不用来限制本申请的实施例的范围。

Claims (19)

  1. 一种集成电路的电路单元布局方法，其特征在于，所述方法包括：
    获取集成电路的当前布局；所述当前布局中包括：未布局电路单元的第一区域；
    在所述第一区域中确定用于摆放第一电路单元的多个合法摆放位置；
    布局预测模型基于所述当前布局和所述多个合法摆放位置输出预测结果；
    根据所述预测结果，确定所述第一区域中摆放所述第一电路单元的位置。
  2. 根据权利要求1所述的方法，其特征在于，所述合法摆放位置包括：所述合法摆放位置位于所述第一区域的角位置和/或所述第一区域的边缘位置。
  3. 根据权利要求2所述的方法，其特征在于，所述角位置包括基于所述当前布局中已布局的电路单元的顶点构成的角位置和/或所述第一区域的顶点构成的角位置。
  4. 根据权利要求1-3任一项所述的方法，其特征在于，所述合法摆放位置还包括满足如下中的至少一项的位置：
    所述合法摆放位置摆放所述第一电路单元后，所述第一电路单元与所述当前布局中已布局的电路单元不重叠；
    所述合法摆放位置摆放所述第一电路单元后，所述第一区域不产生悬空区域；
    所述合法摆放位置摆放所述第一电路单元后，所述第一区域不产生封闭区域；或
    所述合法摆放位置位于所述第一区域中，与所述第一电路单元属于同一分组的已布局的电路单元的顶点构成的角位置；其中，同一分组中的多个电路单元的功能具有相关性。
  5. 根据权利要求1-4任一项所述的方法，其特征在于，所述布局预测模型的输出为所述多个合法摆放位置中各个合法摆放位置的概率，所述根据所述预测结果，确定所述第一区域中摆放所述第一电路单元的位置包括：根据所述多个合法摆放位置中各个合法摆放位置的概率，确定所述第一区域中摆放所述第一电路单元的位置。
  6. 根据权利要求5所述的方法，其特征在于，所述根据所述多个合法摆放位置中各个合法摆放位置的概率，确定所述第一区域中摆放所述第一电路单元的位置包括：将所述多个合法摆放位置中概率最大的合法摆放位置确定为摆放所述第一电路单元的位置。
  7. 根据权利要求5所述的方法，其特征在于，所述根据所述多个合法摆放位置中各个合法摆放位置的概率，确定所述第一区域中摆放所述第一电路单元的位置包括：
    根据所述多个合法摆放位置中各个合法摆放位置的概率，对所述多个合法摆放位置进行抽取，获得摆放所述第一电路单元的合法摆放位置。
  8. 根据权利要求1-7任一项所述的方法，其特征在于，所述第一电路单元包括宏单元。
  9. 一种集成电路的电路单元布局装置，其特征在于，所述装置包括：
    获取模块，用于获取集成电路的当前布局；所述当前布局中包括：未布局电路单元的第一区域；
    第一确定模块，用于在所述第一区域中确定用于摆放第一电路单元的多个合法摆放位置；
    预测模块，用于布局预测模型基于所述当前布局和所述多个合法摆放位置输出预测结果；
    第二确定模块，用于根据所述预测结果，确定所述第一区域中摆放所述第一电路单元的位置。
  10. 根据权利要求9所述的装置，其特征在于，所述合法摆放位置包括：所述合法摆放位置位于所述第一区域的角位置和/或所述第一区域的边缘位置。
  11. 根据权利要求10所述的装置，其特征在于，所述角位置包括基于所述当前布局中已布局的电路单元的顶点构成的角位置和/或所述第一区域的顶点构成的角位置。
  12. 根据权利要求9-11任一项所述的装置，其特征在于，所述合法摆放位置还包括满足如下中的至少一项的位置：
    所述合法摆放位置摆放所述第一电路单元后，所述第一电路单元与所述当前布局中已布局的电路单元不重叠；
    所述合法摆放位置摆放所述第一电路单元后，所述第一区域不产生悬空区域；
    所述合法摆放位置摆放所述第一电路单元后，所述第一区域不产生封闭区域；或
    所述合法摆放位置位于所述第一区域中，与所述第一电路单元属于同一分组的已布局的电路单元的顶点构成的角位置；其中，同一分组中的多个电路单元的功能具有相关性。
  13. 根据权利要求9-12任一项所述的装置，其特征在于，所述布局预测模型的输出为所述多个合法摆放位置中各个合法摆放位置的概率，所述第二确定模块具体用于：
    根据所述多个合法摆放位置中各个合法摆放位置的概率，确定所述第一区域中摆放所述第一电路单元的位置。
  14. 根据权利要求13所述的装置，其特征在于，所述第二确定模块具体用于：
    将所述多个合法摆放位置中概率最大的合法摆放位置确定为摆放所述第一电路单元的位置。
  15. 根据权利要求13所述的装置，其特征在于，所述第二确定模块具体用于：
    根据所述多个合法摆放位置中各个合法摆放位置的概率，对所述多个合法摆放位置进行抽取，获得摆放所述第一电路单元的合法摆放位置。
  16. 根据权利要求8-15任一项所述的装置，其特征在于，所述第一电路单元包括宏单元。
  17. 一种集成电路布局装置，其特征在于，所述装置包括：处理器和传输接口，所述处理器被配置为调用存储在存储器中的程序指令，以使得所述集成电路布局装置实现权利要求1-8任一项所述的方法。
  18. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质存储有计算机程序代码，当所述计算机程序代码被计算机或处理器执行时，所述计算机或所述处理器实现权利要求1-8任一项所述的方法。
  19. 一种包含指令的计算机程序产品，其特征在于，当所述指令被计算机或处理器执行时，使得所述计算机或所述处理器实现权利要求1-8任一项所述的方法。
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