WO2022237486A1 - 接口复用的芯片和芯片的调试系统 - Google Patents

接口复用的芯片和芯片的调试系统 Download PDF

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Publication number
WO2022237486A1
WO2022237486A1 PCT/CN2022/088107 CN2022088107W WO2022237486A1 WO 2022237486 A1 WO2022237486 A1 WO 2022237486A1 CN 2022088107 W CN2022088107 W CN 2022088107W WO 2022237486 A1 WO2022237486 A1 WO 2022237486A1
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Prior art keywords
interface
reset signal
receiving unit
chip
instruction receiving
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PCT/CN2022/088107
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English (en)
French (fr)
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张志仓
孙永琦
仲雨
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上海磐启微电子有限公司
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Publication of WO2022237486A1 publication Critical patent/WO2022237486A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0042—Universal serial bus [USB]

Definitions

  • the present application relates to the field of chip design, for example, to a chip with multiplexing interfaces and a debugging system for the chip.
  • Debugging is an essential step to ensure the correct operation of the program in the chip.
  • the debugger can download the program through the debugging interface, and test and modify the program in the chip.
  • Common debugging interfaces include Joint Test Action Group (JTAG) interface, C2 interface, etc.
  • JTAG Joint Test Action Group
  • C2 interface C2 interface
  • the chip can reserve dedicated pins for programming and debugging.
  • the JTAG interface needs four pins for debugging
  • the C2 interface needs two pins for debugging.
  • the number of debugging pins The design will cause a waste of pin resources.
  • many mass-produced circuit boards do not retain the debug interface.
  • the debugging interface can be multiplexed with the functional interface.
  • the external debugger cannot control the multiplexer to select the debug interface. It will cause the problem that the debugger cannot be debugged because the debugger cannot connect to the debug interface.
  • a method is to determine whether the signal multiplexing unit selects the function interface signal or the debugging mode through the level signal of the multiplexing control pin and whether the multiplexing control register receives the trigger command of the debugging mode.
  • the interface signal is used to choose to use the function interface or the debugging interface, wherein the trigger command of the debugging mode is sent by the user through buttons, toggle switches or menu selections.
  • this method requires an additional multiplexed control pin.
  • serial interface receives an emulation debugging switching command in a special command format
  • the serial communication signal is recognized as an emulation debugging signal.
  • the serial interface can be a serial Serial Peripheral Interface (SPI) or Universal Asynchronous Receiver/Transmitter (UART) serial interface.
  • SPI serial Peripheral Interface
  • UART Universal Asynchronous Receiver/Transmitter
  • the debugging interface in this method can only be reused with the interface of a specific function module, which has certain limitations in application.
  • the debugging interface and the functional interface can be flexibly multiplexed without additional setting of multiplexing control pins.
  • the embodiment of the present application provides an interface multiplexing chip, the chip includes a controller, a reset signal generating unit, an instruction receiving unit, an interface multiplexing unit, a debugging module, a function module and a general interface, and the general interface is set as Connected to a debugger, the instruction receiving unit is connected to the general interface to receive instructions sent by the debugger; the reset signal generating unit is set to generate valid first reset signals and second reset signals, and the The release time of the first reset signal is earlier than the release time of the second reset signal, and the release means that the signal changes from valid to invalid; the instruction receiving unit is configured to detect the first reset signal and the second Reset signal, and after the release of the first reset signal and before the release of the second reset signal, detect whether the instruction sent by the debugger is received; the control terminal of the interface multiplexing unit is connected with the instruction receiving unit and The controllers are respectively connected to the control terminals of the interface multiplexing unit, and in response to determining that the instruction unit has received the instruction, the instruction
  • the embodiment of the present application also provides a chip debugging system, the debugging system includes the above-mentioned interface multiplexed chip, and a debugger.
  • FIG. 1 is a schematic structural diagram of a first interface multiplexing chip according to an embodiment of the present application
  • FIG. 2 is a schematic diagram of a reset signal according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of data transmission between a debugger and an instruction receiving unit according to an embodiment of the present application
  • FIG. 4 is a schematic structural diagram of a chip debugging system according to an embodiment of the present application.
  • FIG. 4A is a schematic structural diagram of another chip debugging system according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of another chip debugging system according to an embodiment of the present application.
  • FIG. 5A is a schematic structural diagram of another chip debugging system according to an embodiment of the present application.
  • the JTAG interface adopts a four-wire serial communication protocol.
  • the four signal lines of the JTAG interface include the test mode selection (Test Mode Selection, TMS) signal, the test clock (Testing Clock, TCK) input signal, the test data input (Test Data Input, TDI) signal and the test data output (Test Data Output , TDO) signal.
  • TMS Test Mode Selection
  • TCK Test Clock
  • TDO Test Data Output
  • TAP Test Access Port
  • the state machine of the TAP controller changes the state through TCK and TMS to realize the input of data and instructions. Data is stored in the data register, and instructions are stored in the instruction register.
  • the C2 interface uses a two-wire serial communication protocol.
  • the communication device of the C2 interface includes an interface host (also called a debugger) and an interface slave (also called a device to be debugged).
  • the C2 interface protocol includes two lines, namely a data (Data) line, denoted as C2D and a clock (Clock) line, denoted as C2CK.
  • Data data
  • C2D clock
  • C2CK clock
  • the operation of the C2 interface is similar to JTAG.
  • Three JTAG data signals ie, TDI, TDO, and TMS
  • the signal direction of C2D is strictly controlled by the command protocol.
  • the debugger implements in-circuit programming and debugging functions through a set of data registers in the C2 interface.
  • the address register defines which data register the debugger can access (similar to JTAG's instruction register).
  • the embodiment of the present application provides an interface multiplexing chip, the chip includes a controller, a reset signal generating unit, an instruction receiving unit, an interface multiplexing unit, a debugging module, a function module and a general interface, and the general interface is set as Connected to a debugger, the instruction receiving unit is connected to the general interface to receive instructions sent by the debugger; the reset signal generating unit is set to generate valid first reset signals and second reset signals, and the The release time of the first reset signal is earlier than the release time of the second reset signal, and the release means that the signal changes from valid to invalid; the instruction receiving unit is configured to receive the first reset signal and the second reset signal, and after receiving the first reset signal and before receiving the second reset signal, detect whether an instruction sent by the debugger is received; the control terminal of the interface multiplexing unit is respectively connected to the The instruction receiving unit is connected to the controller, and under the control of the instruction receiving unit or the controller, the interface multiplexing unit gates the general interface and the debugging module or the functional module;
  • FIG. 1 is a schematic structural diagram of a first interface multiplexing chip according to an embodiment of the present application.
  • the chip 10 includes a controller 101, a reset signal generating unit 102, an instruction receiving unit 103, an interface multiplexing unit 104, a debugging module 105, a function module 106 and a general interface 107, and the general interface 107 is configured to be connected to the debugger 20 , the instruction receiving unit 103 is connected to the general interface 107 to receive instructions sent by the debugger 20 .
  • the common interface 107 is an interface multiplexed by the debugging module 105 and the function module 106 .
  • the functional module 106 may be a module for realizing various functions, for example, the functional module 106 may be a Universal Serial Bus (Universal Serial Bus, USB) module or a Pulse Width Modulation (Pulse Width Modulation, PWM) module or any other module.
  • the USB module is set to connect and communicate with a host computer such as a computer.
  • the USB module has two signal lines, USB_DP for transmitting positive signals of USB data and signal line USB_DM for transmitting negative signals of USB data, as an example.
  • the PWM module is set to output a square wave with a fixed period and adjustable width.
  • the PWM module has two signal lines, PWM0 and PWM1, as an example for illustration.
  • the interface of the debugging module 105 includes but not limited to the JTAG interface and/or the C2 interface.
  • the debugger 20 is a debugging device other than the chip 10, that is, the debugger 20 and the chip 10 are two independent devices. If the chip needs to be programmed and debugged, the debugger 20 can be connected to the general purpose device of the chip 10. interface 107. The debugger 20 can send instructions to the instruction receiving unit 103 through the general interface 107 .
  • the controller 101 can be various processors or processor cores, such as a central processing unit (central processing unit, CPU), etc., which can execute corresponding operations by executing instructions, and output various appropriate signals and the like.
  • a central processing unit central processing unit, CPU
  • CPU central processing unit
  • the reset signal generation unit 102 is configured to generate a valid first reset signal and a second reset signal, and the release time of the first reset signal is earlier than the release time of the second reset signal, the release means Signal transitions from active to inactive.
  • the instruction receiving unit 103 is configured to detect the first reset signal and the second reset signal, and detect whether the debugger is received after the first reset signal is released and before the second reset signal is released. 20 instructions issued. In other words, the instruction receiving unit 103 detects whether an instruction issued by the debugger 20 is received in the time window defined between the release time of the first reset signal and the release time of the second reset signal.
  • the release time of the first reset signal refers to the time when the first reset signal changes from valid to invalid
  • the release time of the second reset signal refers to the time when the second reset signal changes from valid to invalid.
  • FIG. 2 is a schematic diagram of a reset signal.
  • the reset signal generation unit 102 When the chip 10 is powered on, the voltage of the power port VDD gradually rises to the operating voltage, and the reset signal generation unit 102 generates an effective first reset signal ( That is, the reset signal 1) in FIG. 2 and the second reset signal (ie, the reset signal 2 in FIG. 2 ), and release the first reset signal and the second reset signal successively.
  • the time interval between the release times of the first reset signal and the second reset signal is t.
  • the value of t can be preset as required, and it is necessary to ensure that the instruction receiving unit 103 can successfully receive the instruction within the time interval t.
  • the debugger 20 may send an instruction to the instruction receiving unit 103 to control the general interface 107 and the debugging module 105 to be switched on, that is, a path is formed between the general interface 107 and the debugging module 105 .
  • the timing of generating and releasing the first reset signal and the second reset signal may be other timings besides after the chip 10 is powered on.
  • the chip 10 detects that the debugger 20 is connected to the general interface 107, it can also control the reset signal generating unit 102 to generate valid first reset signals and second reset signals, and then release the first reset signals and the second reset signals.
  • the reset signal generating unit 102 can also control the reset signal generating unit 102 to generate valid first reset signals and second reset signals, and then release the first reset signals and the second reset signals.
  • two reset signals, and the release time of the first reset signal is earlier than the release time of the second reset signal.
  • the instruction receiving unit 103 is further configured to detect whether the first reset signal is valid, and the instruction receiving unit 103 is reset when the valid first reset signal is detected. That is, the first reset signal is used to reset the instruction receiving unit 103 .
  • the valid second reset signal is used to reset at least one of other circuit units in the chip 10 except the instruction receiving unit 103 . That is, the second reset signal is used to reset other circuit units in the chip.
  • first reset signal and/or the second reset signal when the first reset signal and/or the second reset signal is a low level signal, it means that the first reset signal and/or the second reset signal are valid.
  • first reset signal/second reset signal when the first reset signal/second reset signal is a low-level signal, it means that the first reset signal/second reset signal is valid, and when it changes from a low-level signal to a high-level signal, Indicates that the first reset signal/second reset signal is released.
  • the relationship between the high/low level and whether the first reset signal/the second reset signal is valid includes but not limited to the limitation in FIG. 2 .
  • the instruction receiving unit 103 is reset when detecting that the first reset signal is valid, and other circuit units of the chip 10 are reset when detecting that the second reset signal is valid. For example, the instruction receiving unit 103 no longer works after detecting that the second reset signal is released, that is, no longer detects whether the instruction is received.
  • the control terminal 1041 of the interface multiplexing unit 104 is respectively connected with the instruction receiving unit 103 and the controller 101, and under the control of the instruction receiving unit 103 or the controller 101, the interface multiplexing unit 104 gates the general interface 107 with the debugging module 105 or the function module 106 .
  • Gating refers to selecting one of the debugging module 105 and the function module 106 to communicate with the common interface 107 .
  • the instruction receiving unit 103 controls the interface multiplexing unit 104 to gate the general interface 107 and the debugging module 105; the instruction receiving unit When 103 does not receive the instruction, the controller 101 controls the interface multiplexing unit 104 to enable the general interface 107 and the function module 106 .
  • the interface multiplexing unit 104 may include a multiplexer.
  • the interface multiplexing unit 104 controls which module in the general interface 107 and the debugging module 105, the function module 106 is selected, and when one of the modules is selected, the general interface 107 is used as the input and output interface of the selected module
  • the chip 10 can control the interface multiplexing unit through the controller 101 according to the software or other control signals stored in its internal memory (flash). 104 and which module is gated.
  • control signal source of the control terminal 1041 of the interface multiplexing unit 104 may include two groups: the first group of control signal source is the instruction issued by the debugger 20 through the instruction receiving unit 103, and the second group of control signal source is the chip 10 signal from controller 101.
  • the instruction receiving unit 103 and the controller 101 may be connected to the interface multiplexing unit 104 through an arbitration module (not shown in the figure), and the arbitration module is configured to process the above two groups of control signals to It is determined which group of control signals is selected to control the interface multiplexing unit 104 .
  • the priority of the instruction receiving unit 103 is higher than that of the controller 101 . That is, the priority of the first group of control signals is higher than that of the second group of control signals. That is, if the first group of control signals and the second group of control signals exist at the same time, the first group of control signals is preferentially selected to control the interface multiplexing unit 104 .
  • the instruction issued by the debugger 20 for controlling the interface multiplexing unit 104 to gate the general interface 107 and the debugging module 105 has a preset information structure, and only when the instruction receiving unit 103 When an instruction satisfying this information structure is received, it means that the instruction receiving unit 103 has received the instruction.
  • the information structure of the instruction includes: start command+instruction content. After receiving the start command, the command receiving unit 103 starts to receive the content of the command and analyze it. If the result of the parsing is correct, it means that the command receiving unit 103 has received the command.
  • the instruction receiving unit 103 is further configured to return a response signal to the debugger 20 after detecting that the instruction is received; if the instruction receiving unit 103 receives a wrong instruction content, it does not return a response signal. That is, the instruction receiving unit 103 informs the debugger 20 that the general interface 107 is controlled to be enabled with the debugging module 105 through the response signal, and the debugger 20 can debug the chip 10 through the debugging module 105 .
  • FIG. 3 is a schematic diagram of data transmission between a debugger and an instruction receiving unit.
  • the instructions transmitted in the connection path between the two include "initial command + instruction content + response signal".
  • the signal lines of the instruction receiving unit 103 may include a data line and a clock line, and the two lines may be connected to any signal line of the general interface 107, that is, the general interface 107 includes at least two signal lines.
  • the instruction receiving unit 103 uses at least two signal lines in the general interface 107 to receive instructions during the period when the first reset signal is released and the second reset signal is not released. During this period, the common interface 107 will not be occupied by any functional module until the second reset signal is released. After the second reset signal is released, the instruction receiving unit 103 no longer receives instructions, nor occupies the general interface 107, which can be used by other functional modules.
  • the initial command (taking the low level of four clock cycles as an example) and the instruction content (taking 0Xa5 as an example) are output to the instruction receiving unit 103 by the debugger 20; Output to debugger 20 after receiving start command and instruction content.
  • the signal transfer between the two is sent through the data line and the clock line.
  • the clock line is an input signal
  • the data line is an input signal during the debugger 20 sending the initial command and the instruction content
  • the instruction receiving unit 103 returns a response
  • the signal period is the output signal.
  • the instructions of this application are sent through the data line and the clock line during the reset period, without additional multiplexed control pins, and the data line and the clock line can use any available interface of the chip, which can save pin resources.
  • the interface multiplexing unit 104 gates the common interface 107 and the debugging module 105 by default. That is, after the chip 10 is powered on, the interface multiplexing unit 104 gates the common interface 107 and the debugging module 105 .
  • the chip 10 of FIG. 1 receives the instruction sent by the debugger 20 through the instruction receiving unit 103 during the reset period (that is, the period when the first reset signal and the second reset signal are released). If the instruction receiving unit 103 does not receive the instruction during the reset period, the The controller 101 controls the interface multiplexing unit 104 to select the interface of the debugging module 105 or the interface of the functional module 106; The debugger 20 does not send the command or the format of the command sent is incorrect, or the content of the command does not match, all belong to the situation that the command receiving unit 103 has not received the command, and will not trigger the command receiving unit 103 to control the interface multiplexing unit 104 to select the debugging module 105. interface.
  • This application does not impose any restrictions on the functional module 106 and the interface of the functional module 106, because no matter which interface of the functional module is selected by the controller 101 to control the interface multiplexing unit 104, it can always send instructions through the debugger 20 during the reset period.
  • the interface multiplexing unit 104 reselects the interface of the debugging module 105 until it is reset again. That is, when the present application reuses the debugging interface and the functional interface, the debugging module can perform interface multiplexing with any functional module, breaking the limitation of interface multiplexing in related technologies.
  • the embodiment of the present application also provides a chip debugging system.
  • the debugging system includes a chip 10 and a debugger 20 with interfaces multiplexed as described in FIGS. 1 to 3 .
  • the present application will be described in detail through two example implementations below.
  • FIG. 4 is a schematic structural diagram of a chip debugging system
  • FIG. 4A is a structural schematic diagram of a chip debugging system
  • the functional module 106 includes a USB module 1061 and a PWM module 1062
  • the interface of the debugging module 105 is a C2 interface (the debugging module 105 may also be called a C2 debugging module)
  • the general interface 107 includes pins P40 and P41.
  • USB module 1061 is connected with interface multiplexing unit 104 through signal lines 408 and 409
  • PWM module 1062 is connected with interface multiplexing unit 104 through signal lines 406 and 407
  • C2 debugging module 105 is connected with interface multiplexing unit 104 through signal lines 404 and 405 connection
  • the interface multiplexing unit 104 gates one of the USB module 1061 , the PWM module 1062 and the C2 debugging module 105 with the general interface 107 .
  • the signal line 401 is used for transmitting the first reset signal output by the reset signal generating unit 102
  • the signal line 402 is used for transmitting the second reset signal output by the reset signal generating unit 102 .
  • the signal line 403 is used to transmit the control signal of the instruction receiving unit 103 to the interface multiplexing unit 104; the signal line 404 is the data line C2D of the C2 debugging module 105; the signal line 405 is the clock line C2CK of the C2 debugging module 105; the signal line 406 is The signal line PWM0 of the PWM module 1062 ; the signal line 407 is the signal line PWM1 of the PWM module 1062 ; the signal line 408 is the signal line USB_DP of the USB module 1061 ; the signal line 409 is the signal line USB_DM of the USB module 1061 .
  • the signal line 410 is the clock line of the command receiving unit 103, that is, the command receiving unit 103 receives the clock signal sent by the debugger 20 through the signal line 410;
  • the signal line 411 is the data line of the command receiving unit 103, that is, the command receiving unit 103 receives the data signal sent by the debugger 20 through the signal line 411 .
  • the interface multiplexing unit 104 selects the signal line of the C2 debugging module 105 by default.
  • the debugger first downloads the software program 1 executed by the USB module 1061 to the chip 10 and runs the program 1 . Then download the software program 2 executed by the PWM module 1062 into the chip 10 and run the program 2 .
  • Program 1 controls the interface multiplexing unit 104 through the controller 101 (not shown in FIG. 4 ) to gate the interfaces of the pins P40 and P41 and the USB module 1061 (ie, the signal lines 408 and 409 ). That is, the interface multiplexing unit 104 selects the interface of the USB module 1061 to communicate with the pins P40 and P41, and starts the work of the USB module.
  • Program 2 controls the interface multiplexing unit 104 through the controller 101 to gate the interface between the pins P40 and P41 and the PWM module 1062 (ie signal lines 406 and 407 ), and start the PWM module to work.
  • Usage 1 Multiplexing the pins P40 and P41 as the interface of the USB module 1061 .
  • the use process includes the following actions: (1) the debugger is connected to the pins P40 and P41 of the chip 10; (2) the chip 10 is powered on and reset; when downloading for the first time, there is no software program in the chip 10, and the interface multiplexing unit 104 After the reset is released, the interface of the debugging module 105 is selected by default, so no instruction needs to be sent during the power-on reset process. (3) After the second reset signal is released, the debugger 20 downloads the program 1 to the chip 10 through the pins P40 and P41.
  • the debugger 20 is disconnected from the pins P40 and P41; (5) the chip 10 runs the program 1, and the interface multiplexing unit 104 is controlled by the controller 101 to select the interface of the USB module 1061, and starts the USB module 1061 jobs.
  • the second usage mode the pins P40 and P41 are multiplexed as the interface of the C2 debugging module 105 .
  • P40 and P41 are occupied by the USB module 1061 , and after the debugger 20 is connected to the pins P40 and P41 , it cannot be directly connected to the C2 debugging module 105 .
  • the debugger 20 If the time is relatively long, the debugger 20 will have enough time to occupy the pins P40 and P41 to start debugging. If the time is short, the debugger 20 cannot start the debugging work. Therefore, the following steps need to be performed to keep the debugger 20 occupying the pins P40 and P41: (1) Connect the debugger 20 to the chip pins P40 and P41; (2) Power on the chip 10 to reset. During power-on reset (that is, after the first reset signal is released and before the second reset signal is released), the debugger 20 sends commands (such as 0xa5) until the debugger receives a response signal (such as 0x55).
  • commands such as 0xa5
  • the control interface multiplexing unit 104 selects the interface of the debugging module. (3) After the power-on reset is completed, since the command receiving unit 103 controls the interface multiplexing unit 104 with a higher priority than the controller 101, the pins P40 and P41 are still occupied by the interface of the debugging module.
  • the third usage mode the pins P40 and P41 are multiplexed as the interface of the PWM module 1062 .
  • the debugger 20 has been connected to the debugging module 105 through P40 and P41.
  • the use process includes the following actions: (1) The debugger 20 downloads the program 2 to the chip 10 through the pins P40 and P41. (2) After the download is complete, the debugger 20 is disconnected from the pins P40 and P41; (3) The chip 10 runs the program 2, and the control interface multiplexing unit 104 selects the interface of the PWM module 1062, and starts the PWM module 1062 to work.
  • Fig. 5 is a schematic structural diagram of another chip debugging system
  • Fig. 5A is a structural schematic diagram of another chip debugging system according to an embodiment of the present application, JTAG debugging module and SPI module (That is, the interface of the module is a serial peripheral interface (Serial Peripheral Interface, SPI)).
  • SPI Serial Peripheral Interface
  • the interface of described debugging module 105 is that C2 interface is JTAG interface (debugging module 105 also can be referred to as JTAG debugging module), described function module 106 comprises SPI module, and common interface 107 comprises multiplexing pin P50, P51 , P52 and P53, the debugger 20 can be connected to at least two of the pins P50, P51, P52 and P53 (Fig. 5 is illustrated by connecting to P50 and P51 as an example).
  • SPI is a high-speed full-duplex, synchronous communication bus.
  • the signal line 501 is used to transmit the first reset signal output by the reset signal generating unit 102; the signal line 502 is used to transmit the second reset signal output by the reset signal generating unit 102; the signal line 503 is used to transmit the instruction receiving unit 103 to the interface
  • the control signal of the multiplexing unit 104 is the TMS signal line of JTAG debugging module 105;
  • Signal line 505 is the clock line TCK of JTAG debugging module 105;
  • Signal line 506 is the input signal line TDI of JTAG debugging module 105;
  • Signal line 507 is the output of JTAG debugging module 105 Signal line TDO.
  • Signal line 508 is the slave device enabling signal line SSN of SPI module 106;
  • Signal line 509 is the clock signal line SCK of SPI module 106;
  • Output slave input (Master Output Slave Input, MOSI);
  • Signal line 511 is the master device data input of SPI module 106, the signal line master input slave output (Master Input Slave Output, MISO) of slave device data output;
  • Signal line 512 is instruction The clock line of the receiving unit 103, the instruction receiving unit 103 receives the clock signal sent by the debugger 20 through the signal line 512;
  • the signal line 513 is the data line of the instruction receiving unit, and the instruction receiving unit 103 receives the data sent by the debugger 20 through the signal line 513 Signal.
  • the program in the chip 10 has multiplexed the pins P50 , P51 , P52 and P53 as the interface of the SPI module 106 . Now it is necessary to download a new section of program into the chip 10 and perform debugging. The new program will not control the interface multiplexing unit 104 . Proceed as follows:
  • the debugger 20 Connects the debugger 20 to the pins P50 and P51; (2) Power on the chip 10 to reset.
  • the debugger 20 is connected to the instruction receiving unit 103 through P50 and P51, and the debugger 20 sends the instruction 0xa5 until the debugger 20 receives the response signal 0x55.
  • the control interface multiplexing unit 104 selects the interface of the JTAG debugging module 105 .
  • the command receiving unit 103 controls the interface multiplexing unit 104 with a higher priority than the controller 101, the pins P50, P51, P52, and P53 are still occupied by the interface of the JTAG debugging module 105.
  • the debugger 20 is connected to the interface of the JTAG debugging module 105 by pins P50, P51, P52 and P53, and new programs are downloaded to the chip 10; (4) after the download of the new program is completed, the debugger 20 Send a debug command to the JTAG debug module 105 to execute the debug work.
  • Multiple appearing in the embodiments of the present application means two or more.
  • connection in the embodiment of the present application refers to various connection methods such as direct connection or indirect connection to realize communication between devices, which is not limited in the embodiment of the present application. Arrows of signal lines in various figures may indicate the flow of signals.
  • the interface multiplexing chip proposed by this application receives the instructions sent by the debugger through the instruction receiving unit during the reset period (also specifically, the time interval between the release of the first reset signal and the release of the second reset signal). If the instruction receiving unit does not receive the instruction, the controller controls the interface multiplexing unit to select the interface of the debugging module or the interface of the function module; if the instruction receiving unit receives the instruction during reset, the instruction receiving unit controls the interface multiplexing unit to select the interface of the debugging module .
  • the debugger does not send the command or the format of the command sent is incorrect, or the content of the command does not match, etc., all belong to the situation that the command receiving unit does not receive the command, and will not trigger the command receiving unit to control the interface multiplexing unit to select the interface of the debugging module.
  • This application does not impose any restrictions on the functional modules and the interfaces of the functional modules, because no matter which interface of the functional module is selected by the controller to control the interface multiplexing unit, the interface multiplexing unit can be restarted by sending instructions from the debugger during the reset period. Select the interface of the debug module until reset again.
  • the debugging module can perform interface multiplexing with any functional module, breaking the limitation of interface multiplexing in related technologies.
  • the above commands are received through a general interface during reset, without additional multiplexed control pins, and the general interface can be any available interface on the chip, saving pin resources.

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Abstract

一种接口复用的芯片和芯片的调试系统，芯片包括控制器、复位信号产生单元、指令接收单元、接口复用单元、调试模块、功能模块和通用接口，通用接口设置为与调试器连接，指令接收单元与通用接口连接；复位信号产生单元设置为生成有效的第一复位信号和有效的第二复位信号，第一复位信号的释放时间早于第二复位信号的释放时间；指令接收单元设置为在第一复位信号释放之后且第二复位信号释放之前检测是否收到调试器发出的指令；指令接收单元在接收到指令时控制接口复用单元将通用接口与调试模块选通；指令接收单元未收到指令时，控制器控制接口复用单元将通用接口与功能模块选通。

Description

接口复用的芯片和芯片的调试系统
本申请要求在2021年7月7日提交中国专利局、申请号为202110529581.8的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及芯片设计领域，例如涉及一种接口复用的芯片和芯片的调试系统。
背景技术
调试是保证芯片内程序正确运行必不可少的步骤，调试器可通过调试接口下载程序，并对芯片内程序进行测试、修改。常用的调试接口有联合测试工作组(Joint Test Action Group，JTAG)接口，C2接口等。通常，芯片可以留有专门的引脚用于编程和调试，例如JTAG接口需要四个引脚调试，C2接口需要两个引脚调试，对于引脚总数较少的芯片来说，调试引脚的设计会造成引脚资源的浪费。另外，很多量产的电路板未保留调试接口，在调试芯片程序时，需要通过重新引线将调试接口接出来。为了节省芯片的引脚资源并在电路板上保留调试接口，可以将调试接口与功能接口复用。在将调试接口与功能接口复用时，可以通过多路选择器选择使用调试接口或者功能接口，然而在多路选择器选择功能接口后，外部调试器无法控制多路选择器来选择调试接口，会造成由于调试器无法连接调试接口而无法调试的问题。
为解决该问题，在相关技术中，一种方法是通过复用控制引脚的电平信号和复用控制寄存器是否收到调试模式的触发指令，来决定信号复用单元选择功能接口信号还是调试接口信号，以选择使用功能接口或者调试接口，其中，调试模式的触发指令由用户通过按键、拨动开关或菜单选择等方式发出。然而，该方法需要额外的复用控制引脚。
另一种方法是将串行接口与调试接口复用，在串行接口接收到特殊指令格式的仿真调试切换指令时，将串行通信信号识别成仿真调试信号，其中，串行接口可以是串行外设接口(Serial Peripheral Interface，SPI)或异步收发传输器(Universal Asynchronous Receiver/Transmitter，UART)串行接口。然而该方法中的调试接口只能与特定的功能模块的接口进行复用，在应用上具有一定的局限性。
综上，相关技术中将调试接口与功能接口复用时，存在以下问题：(1)需要额外的复用控制引脚；(2)只能与特定的功能模块进行复用，应用上比较局限。
发明内容
本申请无需额外设置复用控制引脚，便可将调试接口与功能接口灵活复用。
本申请实施例提供了一种接口复用的芯片，所述芯片包括控制器、复位信号产生单元、指令接收单元、接口复用单元、调试模块、功能模块和通用接口，所述通用接口设置为与调试器连接，所述指令接收单元与所述通用接口连接，以接收所述调试器发送的指令；所述复位信号产生单元设置为生成有效的第一复位信号和第二复位信号，并且所述第一复位信号的释放时间早于所述第二复位信号的释放时间，所述释放指信号从有效转为无效；所述指令接收单元设置为检测所述第一复位信号和所述第二复位信号，并在所述第一复位信号释放之后且所述第二复位信号释放之前检测是否收到所述调试器发出的指令；所述接口复用单元的控制端与所述指令接收单元和所述控制器分别与所述接口复用单元的控制端连接，响应于确定所述指令单元接收到所述指令，所述指令接收单元控制所述接口复用单元将所述通用接口与所述调试模块选通；响应于确定所述指令接收单元未接收到所述指令，所述控制器设置为控制所述接口复用单元将所述通用接口与所述功能模块选通。
本申请实施例还提供一种芯片的调试系统，所述调试系统包括上述接口复用的芯片，以及调试器。
附图说明
图1为本申请实施例的第一种接口复用的芯片的结构示意图；
图2为本申请实施例的一种复位信号的示意图；
图3为本申请实施例的一种调试器与指令接收单元之间的数据传输示意图；
图4为本申请实施例的一种芯片的调试系统的结构示意图；
图4A为本申请实施例的另一种芯片的调试系统的结构示意图；
图5为本申请实施例的另一种芯片的调试系统的结构示意图；
图5A为本申请实施例的另一种芯片的调试系统的结构示意图。
具体实施方式
本领域技术人员应当理解，JTAG接口采用四线串行通信协议。JTAG接口的四根信号线包含测试模式选择(Test Mode Selection，TMS)信号，测试时钟(Testing Clock，TCK)输入信号，测试数据输入(Test Data Input，TDI)信号以及测试数据输出(Test Data Output，TDO)信号。含有JTAG接口的芯片内部有一个测试访问口(Test Access Port，TAP)控制器。TAP控制器的状态机通过TCK和TMS进行状态的改变，实现数据和指令的输入。数据保存到数据寄存器中，指令保存到指令寄存器中。
C2接口采用两线串行通信协议。C2接口的通信设备包括接口主机(也称调试器)和接口从机(也称待调试设备)。C2接口协议中包括两条线，分别是数据(Data)线，记作C2D和时钟(Clock)线，记作C2CK。C2接口的操作类似于JTAG，将三个JTAG数据信号(即TDI、TDO和TMS)映射到一个双向的C2的数据线(C2D)上，C2D的信号方向由指令协议严格控制。调试器通过C2接口中的一组数据寄存器实现在线编程和调试功能。地址寄存器定义了调试器可 访问哪个数据寄存器(类似于JTAG的指令寄存器)。
相关技术中将调试接口(如上述的JTAG接口和C2接口)与功能接口复用时，存在以下情况：(1)需要额外的复用控制引脚；(2)只能与特定的功能模块进行复用，应用上比较局限。
本申请实施例提供了一种接口复用的芯片，所述芯片包括控制器、复位信号产生单元、指令接收单元、接口复用单元、调试模块、功能模块和通用接口，所述通用接口设置为与调试器连接，所述指令接收单元与所述通用接口连接，以接收所述调试器发送的指令；所述复位信号产生单元设置为生成有效的第一复位信号和第二复位信号，并且所述第一复位信号的释放时间早于所述第二复位信号的释放时间，所述释放指的是信号从有效转为无效；所述指令接收单元设置为接收所述第一复位信号和所述第二复位信号，并在接收到所述第一复位信号之后且接收到所述第二复位信号之前检测是否收到所述调试器发出的指令；所述接口复用单元的控制端分别与所述指令接收单元和所述控制器连接，在所述指令接收单元或所述控制器的控制下，所述接口复用单元将所述通用接口与所述调试模块或所述功能模块选通；其中，所述指令接收单元在接收到所述指令时，所述指令接收单元控制所述接口复用单元将所述通用接口与所述调试模块选通；所述指令接收单元未收到所述指令时，所述控制器控制所述接口复用单元将所述通用接口与所述功能模块选通。由此，能够设计芯片时可将任意功能模块接口与调试模块接口复用，且不用添加控制引脚，节约引脚资源。
请参见图1，图1为本申请实施例的第一种接口复用芯片的结构示意图。例如，芯片10包括控制器101、复位信号产生单元102、指令接收单元103、接口复用单元104、调试模块105、功能模块106和通用接口107，所述通用接口107设置为与调试器20连接，所述指令接收单元103与所述通用接口107连接，以接收所述调试器20发送的指令。
其中，通用接口107为调试模块105和功能模块106复用的接口。
功能模块106可以为实现多种功能的模块，例如，功能模块106可以为通用串行总线(Universal Serial Bus,USB)模块或者脉冲宽度调制(Pulse Width Modulation,PWM)模块或者其他任意模块。其中，USB模块设置为与电脑等主机进行连接通讯，本方案中以USB模块具备用于传输USB数据正信号的信号线USB_DP和用于传输USB数据负信号的信号线USB_DM两根信号线为例进行说明。PWM模块设置为输出周期固定，宽度可调的方波，本方案中以PWM模块有PWM0和PWM1两根信号线为例进行说明。
调试模块105的接口包括但不限于JTAG接口和/或C2接口。
调试器20为芯片10之外的调试设备，也即，调试器20与芯片10是相独立的两个器件，若需要对芯片进行编程和调试，则可以将调试器20连接到芯片10的通用接口107上。调试器20可以通过通用接口107向指令接收单元103发送指令。
控制器101可以是多种处理器或者处理器核，如中央处理器(central processing unit，CPU)等，其可以通过运行指令执行相应的操作，输出多种适 当的信号等。
所述复位信号产生单元102设置为生成有效的第一复位信号和第二复位信号，并且所述第一复位信号的释放时间早于所述第二复位信号的释放时间，所述释放指的是信号从有效转为无效。所述指令接收单元103设置为检测所述第一复位信号和所述第二复位信号，并在所述第一复位信号释放之后且所述第二复位信号释放之前检测是否收到所述调试器20发出的指令。换言之，所述指令接收单元103在第一复位信号的释放时间和第二复位信号的释放时间之间定义的时间窗口中，检测是否接收到由调试器20发出的指令。其中，第一复位信号的释放时间是指第一复位信号由有效转为无效的时间，所述第二复位信号的释放时间是指第二复位信号由有效转为无效的时间。
例如，请参见图2，图2为一种复位信号的示意图，在所述芯片10上电时，电源端口VDD的电压逐渐上升至工作电压，复位信号产生单元102生成有效的第一复位信号(即图2中的复位信号1)和第二复位信号(即图2中的复位信号2)，并先后释放第一复位信号和第二复位信号。
第一复位信号和第二复位信号的释放时间之间的时间间隔为t。t的值可以根据需要预先设定，需保证在时间间隔t内，指令接收单元103能够成功接收到指令。在时间间隔t内，调试器20可以向指令接收单元103发送指令，以控制通用接口107与调试模块105选通，即通用接口107与调试模块105之间形成通路。
例如，所述第一复位信号和第二复位信号的生成及释放时机除了在所述芯片10上电之后，也可以为其他时机。例如，在所述芯片10检测到调试器20与通用接口107连接之后，也可以控制所述复位信号产生单元102生成有效的第一复位信号和第二复位信号，然后释放第一复位信号和第二复位信号，并且所述第一复位信号的释放时间早于所述第二复位信号的释放时间。
例如，所述指令接收单元103还设置为检测第一复位信号是否有效，所述指令接收单元103在检测到有效的第一复位信号时复位。也即，第一复位信号用于对指令接收单元103进行复位。
例如，有效的所述第二复位信号用于复位所述芯片10中除所述指令接收单元103之外的其他电路单元中的至少一个。也即，第二复位信号用于复位芯片中其他的电路单元。
例如，所述第一复位信号和/或第二复位信号为低电平信号时表示所述第一复位信号和/或第二复位信号有效。请继续参见图2，当第一复位信号/第二复位信号为低电平信号时，表示第一复位信号/第二复位信号有效，当其由低电平信号转为高电平信号时，表示第一复位信号/第二复位信号释放。需要说明的是，高/低电平与第一复位信号/第二复位信号是否有效之间的关系包括但不限于图2的限定。
例如，指令接收单元103在检测到第一复位信号有效时复位，芯片10的其他电路单元在检测到第二复位信号有效时复位。例如，指令接收单元103在检测到第二复位信号释放之后不再工作，也即，不再检测是否收到指令。
所述接口复用单元104的控制端1041分别与所述指令接收单元103和所述控制器101连接，在所述指令接收单元103或所述控制器101的控制下，所述接口复用单元104将所述通用接口107与所述调试模块105或所述功能模块106选通。选通是指选择调试模块105和功能模块106中的一个与通用接口107连通。其中，所述指令接收单元103在接收到所述指令时，所述指令接收单元103控制所述接口复用单元104将所述通用接口107与所述调试模块105选通；所述指令接收单元103未收到所述指令时，所述控制器101控制所述接口复用单元104将所述通用接口107与所述功能模块106选通。作为一个非限制性的例子，所述接口复用单元104可以包括多路选择器。
其中，接口复用单元104控制通用接口107和调试模块105、功能模块106中的哪一模块选通，当其中一个模块被选通时，通用接口107用作被选通的模块的输入输出接口在指令接收单元103在时间间隔t内未收到调试器20发送的指令时，芯片10可根据其内存(flash)中存储的软件或者其他控制信号，通过控制器101控制所述接口复用单元104与哪一模块选通。也即，接口复用单元104的控制端1041的控制信号来源可以包括两组：第一组控制信号来源为调试器20通过指令接收单元103下达的指令，第二组控制信号来源为芯片10的控制器101发出的信号。
例如，所述指令接收单元103以及所述控制器101可以通过仲裁模块与接口复用单元104连接(未在图中示出)，所述仲裁模块设置为对上述两组控制信号进行处理，以判定选择哪一组控制信号控制所述接口复用单元104。
例如，在控制所述接口复用单元104时，所述指令接收单元103的优先级高于所述控制器101的优先级。也即，上述第一组控制信号的优先级高于第二组控制信号的优先级。也即，若同时存在第一组控制信号和第二组控制信号时，优先选择第一组控制信号控制所述接口复用单元104。
在一个实施例中，所述调试器20发出的用于控制接口复用单元104将所述通用接口107与所述调试模块105选通的指令具有预设的信息结构，只有在指令接收单元103接收到满足这一信息结构的指令时，表示指令接收单元103接收到所述指令。例如，所述指令的信息结构包括：起始命令+指令内容。指令接收单元103在收到起始命令之后，开始接收指令内容并对其进行解析，若解析结果正确，则表示指令接收单元103接收到所述指令。
例如，所述指令接收单元103还设置为在检测收到所述指令之后向所述调试器20返回应答信号；指令接收单元103接收到错误的指令内容，则不返回应答信号。也即，指令接收单元103通过应答信号告知调试器20已控制通用接口107与所述调试模块105选通，调试器20可以通过调试模块105对所述芯片10进行调试。
例如，请参见图3，图3为一种调试器与指令接收单元的数据传输示意图，二者之间的连接通路中传输的指令包括“起始命令+指令内容+应答信号”。所述指令接收单元103的信号线可以包括数据线和时钟线，该两根线可以与所述通用接口107的任一根信号线连接，也即所述通用接口107至少包括两根信号线。
指令接收单元103在第一复位信号释放、第二复位信号未释放期间使用通用接口107中的至少两根信号线接收指令。在此期间，通用接口107不会被任何功能模块占用，直到第二复位信号释放。第二复位信号释放以后，指令接收单元103不再接收指令，也不再占用通用接口107，其可以供其他功能模块使用。
起始命令(以四个时钟周期的低电平为例)和指令内容(以0Xa5为例)由调试器20输出到指令接收单元103；应答信号(以0X55为例)由指令接收单元103在接收到起始命令和指令内容后输出到调试器20。二者之间的信号传递通过数据线和时钟线发送，对于芯片10，时钟线是输入信号，数据线在调试器20发送起始命令和指令内容期间是输入信号，在指令接收单元103返回应答信号期间是输出信号。
由此，本申请的指令在复位期间通过数据线和时钟线发送，无需额外的复用控制引脚，数据线和时钟线可使用芯片任意可用的接口，可节约引脚资源。
在一个实施例中，接口复用单元104默认将所述通用接口107与所述调试模块105选通。也即，所述芯片10上电后，所述接口复用单元104将所述通用接口107与所述调试模块105选通。
图1的芯片10通过指令接收单元103在复位期间(也即第一复位信号与第二复位信号释放的期间)接收调试器20发送的指令，若复位期间指令接收单元103未接收到指令，由控制器101控制接口复用单元104选择调试模块105的接口或功能模块106的接口；若复位期间指令接收单元103接收到指令，则接口复用单元104只能选择调试模块105的接口。调试器20不发送指令或者发送的指令格式不正确，或者指令内容不匹配都属于指令接收单元103未接收到指令的情况，不会触发指令接收单元103控制接口复用单元104选择调试模块105的接口。本申请对功能模块106以及功能模块106的接口不做任何限制，因为无论控制器101控制接口复用单元104选择哪个功能模块的接口后，总能通过复位期间调试器20发送指令的方式，让接口复用单元104重新选择调试模块105的接口，直到再次复位。也即，本申请将调试接口与功能接口复用时，调试模块可以与任何功能模块进行接口复用，打破相关技术中接口复用的限制。
本申请实施例还提供一种芯片的调试系统，所述调试系统包括如图1至图3所述接口复用的芯片10和调试器20。下面通过两个示例实施方式对本申请作详细说明。
请参见图1，图4和图4A，图4为一种芯片的调试系统的结构示意图，图4A为一种芯片的调试系统的结构示意图，所述功能模块106包括USB模块1061和PWM模块1062，所述调试模块105的接口为C2接口(调试模块105也可称为C2调试模块)，所述通用接口107包括引脚P40和P41。USB模块1061通过信号线408和409与接口复用单元104连接，PWM模块1062通过信号线406和407与接口复用单元104连接，C2调试模块105通过信号线404和405与接口复用单元104连接，接口复用单元104将USB模块1061、PWM模块1062和C2调试模块105中的一个与通用接口107选通。其中，信号线401用于传输复位信号产生单元102输出的第一复位信号；信号线402用于传输复位信号产 生单元102输出的第二复位信号。信号线403用于传输指令接收单元103对接口复用单元104的控制信号；信号线404为C2调试模块105的数据线C2D；信号线405为C2调试模块105的时钟线C2CK；信号线406为PWM模块1062的信号线PWM0；信号线407为PWM模块1062的信号线PWM1；信号线408为USB模块1061的信号线USB_DP；信号线409为USB模块1061的信号线USB_DM。信号线410为指令接收单元103的时钟线，也即指令接收单元103通过信号线410接收所述调试器20发送的时钟信号；信号线411为指令接收单元103的数据线，也即指令接收单元103通过信号线411接收所述调试器20发送的数据信号。本实施例中，接口复用单元104默认选择C2调试模块105的信号线。
本实施例中，调试器先将USB模块1061执行的软件程序1下载到芯片10中，并运行程序1。然后将PWM模块1062执行的软件程序2下载到芯片10中，并运行程序2。程序1通过控制器101(图4中未示出)控制接口复用单元104将引脚P40和P41与USB模块1061的接口(即信号线408和409)选通。也即，接口复用单元104选择USB模块1061的接口与引脚P40和P41连通，并启动USB模块工作。程序2通过控制器101控制接口复用单元104将引脚P40和P41与PWM模块1062的接口(即信号线406和407)选通，并启动PWM模块工作。
图4和图4A实施例的使用方式如下：
使用方式一：将引脚P40和P41复用成USB模块1061的接口。使用过程包括如下动作：(1)将调试器连接到芯片10的引脚P40和P41；(2)将芯片10上电复位；首次下载时，芯片10中没有软件程序，且接口复用单元104在复位释放后默认选择调试模块105的接口，因此在此上电复位过程中不需要发送指令。(3)第二复位信号释放后，调试器20通过引脚P40和P41将程序1下载至芯片10中。(4)下载完成后，将调试器20与引脚P40，P41断开；(5)芯片10运行程序1，由控制器101控制接口复用单元104选择USB模块1061的接口，并启动USB模块1061工作。
使用方式二：将引脚P40和P41复用成C2调试模块105的接口。程序1运行起来后，P40和P41被USB模块1061占用，调试器20连接到引脚P40和P41上之后，无法直接连接到C2调试模块105。即使再次上电复位，程序1重新运行，在程序1控制接口复用单元104选择USB模块1061的接口之前，会有短暂的时间内引脚P40和P41与调试模块105接口连接。如果该时间比较长，调试器20会有充足的时间占用引脚P40和P41，开始调试工作。如果该时间很短，调试器20无法开始调试工作。因此，需要执行下述步骤，保持调试器20对引脚P40和P41的占用：(1)将调试器20连接到芯片引脚P40和P41；(2)将芯片10上电复位。在上电复位期间(也即第一复位信号释放之后且第二复位信号释放之前)，调试器20发送指令(如0xa5)，直到调试器接收到应答信号(如0x55)。指令接收单元103接收到0xa5后，控制接口复用单元104选择调试模块的接口。(3)上电复位完成后，由于指令接收单元103对接口复用单元104 控制的优先级大于控制器101控制的优先级，引脚P40,和P41仍然被调试模块的接口占用。
使用方式三：将引脚P40和P41复用成PWM模块1062的接口。经过使用方式二后，调试器20已通过P40和P41与调试模块105连接。使用过程包括如下动作：(1)调试器20通过引脚P40和P41将程序2下载至芯片10中。(2)下载完成后，将调试器20与引脚P40和P41断开；(3)芯片10运行程序2，控制接口复用单元104选择PWM模块1062的接口，并启动PWM模块1062工作。
请参见图1，图5和图5A，图5为另一种芯片的调试系统的结构示意图，图5A为本申请实施例的另一种芯片的调试系统的结构示意图，JTAG调试模块和SPI模块(即该模块的接口为串行外设接口(Serial Peripheral Interface，SPI))。指令接收单元，所述调试模块105的接口为C2接口为JTAG接口(调试模块105也可称为JTAG调试模块)，所述功能模块106包括SPI模块，通用接口107包括复用引脚P50,P51,P52和P53，可以将调试器20连接到引脚P50,P51,P52和P53中的至少两个引脚(图5以连接到P50和P51为例说明)。其中，SPI是一种高速全双工、同步通信总线。
其中，信号线501用于传输复位信号产生单元102输出的第一复位信号；信号线502用于传输复位信号产生单元102输出的第二复位信号；信号线503用于传输指令接收单元103对接口复用单元104的控制信号。信号线504为JTAG调试模块105的TMS信号线；信号线505为JTAG调试模块105的时钟线TCK；信号线506为JTAG调试模块105的输入信号线TDI；信号线507为JTAG调试模块105的输出信号线TDO。信号线508为SPI模块106的从设备使能信号线SSN；信号线509为SPI模块106的时钟信号线SCK；信号线510为SPI模块106的主设备数据输出、从设备数据输入的信号线主输出从输入(Master Output Slave Input，MOSI)；信号线511为SPI模块106的主设备数据输入、从设备数据输出的信号线主输入从输出(Master Input Slave Output，MISO)；信号线512为指令接收单元103的时钟线，指令接收单元103通过信号线512接收调试器20发送的时钟信号；信号线513为指令接收单元的数据线，指令接收单元103通过信号线513接收调试器20发送的数据信号。
例如，芯片10中的程序已将引脚P50,P51,P52和P53复用成SPI模块106的接口。现需要将新的一段程序下载到芯片10中，并执行调试工作，新程序不会控制接口复用单元104。步骤如下：
(1)将调试器20连接到引脚P50和P51；(2)将芯片10上电复位。在上电复位期间，调试器20通过P50和P51连接到指令接收单元103，调试器20发送指令0xa5，直到调试器20接收到应答信号0x55。指令接收单元103接收到0xa5后，控制接口复用单元104选择JTAG调试模块105的接口。上电复位完成后，由于指令接收单元103对接口复用单元104控制的优先级大于控制器101控制的优先级，引脚P50,P51,P52,P53仍然被JTAG调试模块105的接口占用。(3)复位释放后，调试器20通过引脚P50,P51,P52和P53连接到JTAG调试模块105的接口，将新的程序下载至芯片10中；(4)新程序下载完成后，调 试器20向JTAG调试模块105发送调试指令，执行调试工作。
应理解，本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，表示前后关联对象是一种“或”的关系。
本申请实施例中出现的“多个”是指两个或两个以上。
本申请实施例中出现的第一、第二等描述，仅作示意与区分描述对象之用，没有次序之分，也不表示本申请实施例中对设备个数的特别限定，不能构成对本申请实施例的任何限制。
本申请实施例中出现的“连接”是指直接连接或者间接连接等多种连接方式，以实现设备间的通信，本申请实施例对此不做任何限定。多个附图中信号线的箭头可以表示信号的流向。
本申请提出的接口复用的芯片通过指令接收单元在复位期间(也具体而言，在第一复位信号释放和第二复位信号释放之间的时间间隔)接收调试器发送的指令，若复位期间指令接收单元未接收到指令，控制器控制接口复用单元选择调试模块的接口或功能模块的接口；若复位期间指令接收单元接收到指令，则指令接收单元控制接口复用单元选择调试模块的接口。其中，调试器不发送指令或者发送的指令格式不正确，或者指令内容不匹配等都属于指令接收单元未接收到指令的情况，不会触发指令接收单元控制接口复用单元选择调试模块的接口。本申请对功能模块以及功能模块的接口不做任何限制，因为无论控制器控制接口复用单元选择哪个功能模块的接口后，都能通过复位期间调试器发送指令的方式，使得接口复用单元重新选择调试模块的接口，直到再次复位。也即，本申请将调试接口与功能接口复用时，调试模块可以与任何功能模块进行接口复用，打破相关技术中接口复用的限制。另外，上述指令在复位期间通过通用接口接收，无需额外的复用控制引脚，该通用接口可以是芯片任意可用的接口，节约引脚资源。

Claims (10)

  1. 一种接口复用的芯片，所述芯片包括控制器、复位信号产生单元、指令接收单元、接口复用单元、调试模块、功能模块和通用接口，所述通用接口设置为与调试器连接，所述指令接收单元与所述通用接口连接，以接收所述调试器发送的指令；
    所述复位信号产生单元设置为生成有效的第一复位信号和有效的第二复位信号，并且所述第一复位信号的释放时间早于所述第二复位信号的释放时间，所述释放指信号从有效转为无效；
    所述指令接收单元设置为检测所述第一复位信号和所述第二复位信号，并在所述第一复位信号释放之后且所述第二复位信号释放之前检测是否收到所述调试器发出的指令；
    所述指令接收单元和所述控制器分别与所述接口复用单元的控制端连接，响应于确定所述指令单元接收到所述指令，所述指令接收单元设置为控制所述接口复用单元将所述通用接口与所述调试模块选通；响应于确定所述指令接收单元未接收到所述指令，所述控制器设置为控制所述接口复用单元将所述通用接口与所述功能模块选通。
  2. 根据权利要求1所述的芯片，其中，所述指令接收单元控制所述接口复用单元的优先级高于所述控制器控制所述接口复用单元的优先级。
  3. 根据权利要求1所述的芯片，其中，所述指令接收单元还设置为检测是否收到所述有效的第一复位信号，响应于检测收到所述有效的第一复位信号，所述指令接收单元复位。
  4. 根据权利要求3所述的芯片，其中，所述有效的第二复位信号用于复位所述芯片中除所述指令接收单元之外的其他电路单元中的至少一个。
  5. 根据权利要求1所述的芯片，其中，所述第一复位信号和第二复位信号分别为低电平信号时，表示所述第一复位信号和第二复位信号分别有效。
  6. 根据权利要求1至5任一所述的芯片，其中，所述复位信号产生单元设置为在所述芯片上电之后生成所述有效的第一复位信号和所述有效的第二复位信号。
  7. 根据权利要求1至5任一所述的芯片，其中，所述芯片上电后，所述接口复用单元设置为将所述通用接口与所述调试模块选通。
  8. 根据权利要求1所述的芯片，其中，所述指令接收单元还设置为在检测收到所述指令之后向所述调试器返回应答信号。
  9. 根据权利要求1所述的芯片，其中，所述调试模块接口包括以下至少之一：联合测试工作组JTAG接口和C2接口。
  10. 一种芯片的调试系统，包括如权利要求1至9任一项所述接口复用的芯片，以及调试器。
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CN116860096B (zh) * 2023-09-05 2023-11-21 厦门优迅高速芯片有限公司 Mcu芯片的rstn复位引脚功能复用控制方法及电路
CN118631767A (zh) * 2024-08-13 2024-09-10 井芯微电子技术(天津)有限公司 顺序可调整的多协议交换芯片及其复位控制方法

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