WO2022226997A1 - 存储单元的访问方法、修复方法、裸片和存储芯片 - Google Patents

存储单元的访问方法、修复方法、裸片和存储芯片 Download PDF

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Publication number
WO2022226997A1
WO2022226997A1 PCT/CN2021/091480 CN2021091480W WO2022226997A1 WO 2022226997 A1 WO2022226997 A1 WO 2022226997A1 CN 2021091480 W CN2021091480 W CN 2021091480W WO 2022226997 A1 WO2022226997 A1 WO 2022226997A1
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WIPO (PCT)
Prior art keywords
unit
redundant
storage
address
failed
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PCT/CN2021/091480
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English (en)
French (fr)
Inventor
沈国明
刘荣斌
伍青青
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华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN202180087793.3A priority Critical patent/CN116724355A/zh
Priority to PCT/CN2021/091480 priority patent/WO2022226997A1/zh
Priority to EP21938471.6A priority patent/EP4307306A4/en
Publication of WO2022226997A1 publication Critical patent/WO2022226997A1/zh
Priority to US18/495,883 priority patent/US20240055070A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G11C29/4401—Indication or identification of errors, e.g. for repair for self repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/72—Masking faults in memories by using spares or by reconfiguring with optimized replacement algorithms
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/787—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using a fuse hierarchy
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1202—Word line control
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/781—Masking faults in memories by using spares or by reconfiguring using programmable devices combined in a redundant decoder
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/816—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout

Definitions

  • the present application relates to the field of storage technologies, and in particular, to a method for accessing a storage unit, a method for repairing, a bare chip, and a storage chip.
  • the row selection signal selected by the row decoder after performing the row decoding operation on the original row address is the redundant row row select signal.
  • the data to be written is stored in the redundant row or the data stored in the redundant row is read.
  • the redundant row address is carried in the response message returned to the user. In this process, the user is not aware of the replacement operation of redundant rows.
  • the present application provides an access method, a repair method, a bare chip and a memory chip for a storage unit, which can reduce the volume of a product on the basis of realizing failure replacement.
  • a method for accessing a storage unit which is applied to a repairing device, and the method includes:
  • the access address includes the original address of at least one storage unit in the storage device
  • the global repair information includes the original address of the at least one failed unit existing in the storage device and the address used to replace the failed unit.
  • the original address in the access address that points to the first failed unit is replaced with the first redundant unit corresponding to the first failed unit redundant address of the unit;
  • the replaced access request is sent to the storage device.
  • the repair device when the repair device receives an access request including an access address, the repair device identifies whether there is a failed unit in the storage unit pointed to by the access address according to the global repair information, and in the storage unit identified by the access address When there is a first failure unit, replace the original address pointing to the first failure unit in the access address with the redundant address of the redundant unit corresponding to the first failure unit, and send the replaced access request to the storage device, which can realize the utilization of Redundant units repair failed units.
  • the storage device is a storage die
  • the repair device is a logic die
  • the storage device is a storage die
  • the repair device is located on a logic die including a controller
  • the repair device is connected to the storage die through the controller.
  • the storage device is a storage chip
  • the repair device is a main chip
  • the storage device is a storage chip
  • the repair device is located on a main chip including a controller
  • the repair device is connected to the storage chip through the controller.
  • the memory die may include row decoders. Row decoders are used to interface with the logic die.
  • a memory die includes at least one memory cell and at least one redundancy cell.
  • the failed unit is a failed storage unit, and the redundant unit is used to replace the failed unit to execute the access request.
  • a memory die may contain at least one data storage area and at least one redundancy area.
  • Each storage unit in the storage die is located in each data storage area, and each redundant unit is located in each redundant area.
  • one data storage area may correspond to one redundant area, and based on this, the redundant unit in the redundant area may only be used to replace the failed unit in the data storage area corresponding to the corresponding redundant area.
  • multiple data storage areas may correspond to one redundant area, and based on this, redundant units in the redundant area may be used to replace failed units in multiple data storage areas, that is, multiple data storage areas
  • the storage units in a redundant area can share redundant units in a redundant area.
  • a memory die may include multiple blocks, and each block may include multiple sectors.
  • each block may be provided with a data storage area and a redundancy area.
  • each block may be provided with a data storage area, and multiple blocks may be provided with a redundant area.
  • each sector may be provided with a data storage area and a redundancy area.
  • each sector may be provided with a data storage area, and multiple blocks may be provided with a redundant area.
  • each storage unit may be a row located in a data storage area
  • each redundant unit may be a row located in a redundant area
  • the original address of the storage unit belongs to the original address section, and the redundant address of the redundant unit belongs to the redundant address area; any original address points to any data storage area of the storage die A storage unit, any of the redundant addresses points to a redundant unit in any redundant area in the storage die.
  • the method before the receiving the access request including the access address, the method further includes:
  • the second failure unit is the same as or different from the first failure unit.
  • the repairing device includes a one-time programmable memory efuse
  • the method further includes:
  • the third failure unit is the same as or different from the first failure unit.
  • the method further includes:
  • the access response containing the original address of the first failed unit is sent to the bus.
  • the storage device is a storage die
  • the repair device is located on a logic die including a controller, and the repair device is connected to the storage die through the controller;
  • the memory die includes at least two data storage areas, and the global repair information includes the original addresses of all failed cells in the at least two data storage areas and a replacement for each of the at least two data storage areas.
  • the redundant address of the redundant unit of the failed unit includes the redundant address of the redundant unit of the failed unit.
  • any storage unit is a data row
  • any redundant unit is a redundant row
  • the first redundant unit and the first failed unit are located in the same sector of the storage device; or, the first redundant unit and the first failed unit different sectors in the same block in the storage device; or, the first redundant unit and the first failure unit are located in different blocks in the storage device.
  • a method for accessing a storage unit is provided, applied to a storage device, where the storage device includes at least one storage unit, and the method includes:
  • an access request including an access address sent by a repair device, wherein the access address includes a redundant address of a redundant unit in the storage device; wherein the redundant unit is used to replace the at least one storage unit in the the failed unit;
  • An access response is sent to the repair device.
  • the storage device is a storage die
  • the repair device is a logic die
  • the storage device is a storage die, the repair device is located on a logic die including a controller, and the repair device is connected to the storage die through the controller; or,
  • the storage device is a memory chip, and the repair device is a main chip; or,
  • the storage device is a storage chip, the repair device is located on a main chip including a controller, and the repair device is connected to the storage chip through the controller.
  • the method before receiving the access request including the access address sent by the repairing apparatus, the method further includes:
  • the original address of the failed unit is sent to the repair device, so that the repair device allocates the redundant unit for replacing the failed unit,
  • the corresponding relationship between the original address of the failed unit and the redundant address of the redundant unit is added to the global repair information.
  • a method for repairing a storage unit is provided, applied to a storage device, and the method includes:
  • the original address of the failed unit is sent to the repair device, so that the repair device is a redundant unit allocated to replace the failed unit.
  • sending the original address of the failed unit to the repair device includes:
  • the original address of the defective unit is sent to the repair device.
  • a method for repairing a storage unit which is applied to a repairing device, and the method includes:
  • the original address of the failed unit and the redundant address of the redundant unit are added to the global repair information.
  • the repairing device includes efuse;
  • the receiving, sent by the storage device, the original address of the failed unit existing in the storage unit in the storage device includes: receiving all the data sent by the storage device. the original address of at least one failed unit existing before encapsulation in the storage device;
  • the allocating a redundant unit for replacing the failed unit includes: allocating a redundant unit for replacing each of the failed units existing before encapsulation;
  • the adding the original address of the failed unit and the redundant address of the redundant unit to the global repair information includes: adding the original address of each failed unit existing before encapsulation and the redundancy corresponding to each failed unit The correspondence of redundant addresses of units is stored in the efuse; after each power-on of the repair device, the original address of at least one failed unit existing in the storage device read from the efuse The corresponding relationship with the redundant addresses of the redundant units corresponding to each failed unit is added to the global repair information.
  • a repair device comprising:
  • the transceiver module is configured to receive an access request including an access address; the access address includes an original address of at least one storage unit in the storage device.
  • the processing module is configured to identify whether there is a failed unit in the storage unit pointed to by the access address according to the global repair information; wherein, the global repair information includes the original address and usage of at least one failed unit existing in the storage die. the redundant address of the redundant unit to replace each of the failed units in the at least one failed unit; when it is recognized that there is a first failed unit in the storage unit pointed to by the access address, point the access address to the redundant unit The original address of the first failed unit is replaced with the redundant address of the first redundant unit corresponding to the first failed unit.
  • the transceiver module is further configured to send the replaced access request to the storage device.
  • the transceiver module is further configured to receive, before the receiving the access request including the access address, the original address of the second failure unit existing in the storage device sent by the storage device;
  • the processing module is used for assigning a second redundant unit for replacing the second failed unit; and for adding the corresponding relationship between the original address of the second failed unit and the redundant address of the second redundant unit to the global repair information; wherein, the second failure unit and the first failure unit may be the same or different.
  • the repair device includes a one-time programmable memory efuse; the transceiver module is further configured to receive the storage device sent by the storage device before receiving the access request including the access address.
  • the corresponding relationship between the original addresses of the three failed units and the redundant addresses of the third redundant unit is stored in the efuse; and is used for, after each power-on of the repair device, read from the efuse
  • the corresponding relationship between the original address of the third failed unit and the redundant address of the third redundant unit existing in the storage device is added to the global repair information.
  • the transceiver module is further configured to receive an access response including the redundant address of the first redundant unit sent by the storage device; the processing module is further configured to obtain the the original address of the first failed unit corresponding to the first redundant unit; adding the original address of the first failed unit to the access response; the transceiver module is further configured to include the first failed unit The original address of the access response is sent to the bus
  • a storage device comprising:
  • a transceiver module configured to receive an access request including an access address sent by a repair device, wherein the access address includes a redundant address of a redundant unit in the storage device; wherein the redundant unit is used to replace the a failed unit in at least one storage unit;
  • the processing module is configured to access the redundant address; the transceiver module is further configured to send an access response to the repair device.
  • the processing module is further configured to detect whether there is a failed unit in the storage unit in the storage device before receiving the access request including the access address sent by the repairing device; the transceiver module is further configured to , when there is a failed unit in the storage unit in the storage device, send the original address of the failed unit to the repair device, so that the repair device allocates the redundant unit for replacing the failed unit , and the corresponding relationship between the original address of the failed unit and the redundant address of the redundant unit is added to the global repair information.
  • a storage device comprising:
  • the processing module is used for detecting whether there is a failed unit in the storage device.
  • the transceiver module is configured to send the original address of the failed unit to the repairing device when there is a failed unit in the storage unit in the storage device.
  • the processing module is specifically used to detect whether there is a failed unit in the storage unit in the storage device before the storage device is packaged; the transceiver module is specifically used for the storage unit in the storage device. When there is a failed unit in the storage unit, the original address of the failed unit is sent to the repairing device.
  • a repair device comprising:
  • the transceiver module is configured to receive the original address of the failed unit existing in at least one storage unit of the storage device sent by the storage device.
  • a processing module configured to allocate a redundant unit for replacing the failed unit; and configured to add the original address of the failed unit and the redundant address of the redundant unit to the global repair information.
  • the repairing device includes a one-time programmable memory efuse
  • the transceiver module is specifically configured to receive the original address of at least one failed unit existing in the storage device before encapsulation sent by the storage device; the processing module is specifically configured to allocate an redundant unit; and be specifically used for storing the correspondence relationship between the original address of each failed unit before encapsulation and the redundant address of the redundant unit corresponding to each failed unit in the efuse; in the repair device After each power-on, the corresponding relationship between the original address of at least one failed unit existing in the storage device read from the efuse and the redundant address of the redundant unit corresponding to each failed unit is added to the corresponding relationship. global repair information.
  • a repair device comprising: an interface, a processor and a memory;
  • the interface is used to connect a storage device and a bus; the memory is used to store instructions; the processor is used to execute the instructions to implement any one of the first aspect and the fourth aspect or any possible implementation manner. method.
  • the storage device is a storage die
  • the repair device is a logic die
  • the storage device is a storage die, the repair device is located on a logic die including a controller, and the repair device is connected to the storage die through the controller; or,
  • the storage device is a memory chip, and the repair device is a main chip; or,
  • the storage device is a storage chip, the repair device is located on a main chip including a controller, and the repair device is connected to the storage chip through the controller.
  • the memory further includes: a one-time programmable memory efuse.
  • the processor may include: a DRAM controller.
  • a storage device comprising: an interface, a processor and a memory;
  • the interface is used to connect the repair device and the bus;
  • the memory is used to store instructions and data;
  • the processor is used to execute the instructions to implement any one of the second aspect or the third aspect or any possible implementation manner method in .
  • the processor may include: a row address decoder.
  • each storage unit includes at least one data row
  • each redundant unit includes at least one redundant row
  • a memory chip including:
  • the logic die includes a repair device and a controller, the repair device communicates with the storage die through the controller;
  • the logic die is used to perform the method in any one of the first aspect or the fourth aspect or any possible implementation;
  • the memory die is used to perform the method of any of the second or third aspects or any possible implementation.
  • a twelfth aspect provides a memory chip, comprising:
  • the logic die is used for executing the method in any possible implementation manner of the first aspect, and the storage die is used for executing the method in any possible implementation manner in the second aspect; or,
  • the logic die is used for executing the method in any possible implementation of the fourth aspect, and the memory die is used for executing the method in any possible implementation in the third aspect.
  • an apparatus in yet another aspect, includes a processing module and a transceiver module, and the processing unit executes an instruction to control the apparatus to execute the method in the first aspect or any possible design of the first aspect.
  • the apparatus may further include a storage module.
  • the device may be a memory chip.
  • the processing module may be a processor, and the transceiver module may be a transceiver; if a storage module is further included, the storage module may be a memory.
  • the processing module may be a processor, and the transceiver module may be an input/output interface, a pin or a circuit, etc.; if a memory module is also included, the memory module may be an in-chip memory module.
  • the storage module (eg, register, cache, etc.) of the chip can also be a storage module outside the chip (eg, read-only memory, random access memory, etc.).
  • the processor mentioned in any of the above may be a general-purpose central processing unit (Central Processing Unit, referred to as CPU), a microprocessor, a specific application integrated circuit (application-specific integrated circuit, referred to as ASIC), or an or A plurality of integrated circuits for controlling program execution of the spatial multiplexing method of the above aspects.
  • CPU Central Processing Unit
  • ASIC application-specific integrated circuit
  • a computer-readable storage medium having stored therein instructions executable by one or more processors on a processing circuit. When run on a computer, the computer is caused to perform the method of the first aspect above or any possible implementation thereof.
  • a computer program product comprising instructions which, when run on a computer, cause the computer to perform the method of the first aspect above or any possible implementation thereof.
  • FIG. 1 is a schematic structural diagram of a memory chip in an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a layered structure of a die in a memory chip according to an embodiment of the present application
  • FIG. 3 is a schematic diagram of a logical structure of a memory chip in an embodiment of the present application.
  • FIG. 4 is a schematic diagram 1 of an interaction flow of a method for accessing a storage unit provided by an embodiment of the present application
  • FIG. 5 is a schematic diagram of an interaction flow of a method for repairing a storage unit according to an embodiment of the present application
  • FIG. 6 is a schematic diagram of a system architecture and a processing process when the method for accessing a storage unit provided by an embodiment of the present application is applied to a DRAM;
  • FIG. 7 is a schematic structural diagram 1 of a repairing device provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram 1 of a storage device provided by an embodiment of the present application.
  • FIG. 9 is a second structural schematic diagram of a repairing device provided by an embodiment of the present application.
  • FIG. 10 is a second schematic structural diagram of a storage device provided by an embodiment of the present application.
  • the embodiments of the present application provide a storage unit access method, a repair method, and related technical solutions.
  • a chip with a memory function may be referred to as a memory chip.
  • the memory chip can be dynamic random access memory (DRAM), static random access memory (SRAM), non-volatile memory (Non-Volatile Memory, NVM), etc. .
  • DRAM dynamic random access memory
  • SRAM static random access memory
  • NVM non-volatile memory
  • the memory chip may be composed of one or more dies.
  • the manufacturer of the storage chip needs to perform quality inspection on the bare chips that make up the chip, and after the inspection, package the multiple bare chips that make up the chip to obtain the storage chip.
  • FIG. 1 is a schematic structural diagram of a memory chip in an embodiment of the present application.
  • the memory chip 10 may include one logic die 100 and at least one storage die 200 .
  • one or more storage particles can be deployed on each storage die.
  • the storage granules deployed on each storage die may be divided into one or more blocks (banks), and each bank may be divided into one or more sectors (sectors). Each sector can be divided into multiple rows (row).
  • Each memory die may also be deployed with an address decoder, such as a row address decoder, which may also be referred to as a row decoder.
  • the memory chip may further include an outer packaging layer.
  • FIG. 2 is a schematic diagram of a layered structure of a die in a memory chip according to an embodiment of the present application.
  • the logic die and the storage die in the memory chip may be arranged in layers in a 3D stacking manner, wherein the logic die is located on the bottom layer, and the storage die is located above the logic die , the projection of the storage die on the plane where the logical die is located can occupy the same area as the logical die.
  • the multiple storage die is also hierarchically set, and each storage die is placed on the logical die. The area occupied by the projection of the plane on which the slices lie can be the same.
  • one memory chip may include one logic die and an integer multiple of four memory die.
  • the logic die may also be referred to as a base film, or a base die.
  • FIG. 3 is a schematic diagram of a logical structure of a memory chip in an embodiment of the present application.
  • the logic die 100 may include: a repair apparatus 1001 and a controller 1002 .
  • the logic die may also include an external interface to communicate with the system bus, and an internal interface to communicate with the various memory dies.
  • the memory chip may also communicate with the system bus through the main chip, wherein the main chip may be provided with a repair device and a controller, and the controller may communicate with the system bus through the main chip.
  • the logic die accesses the memory cells in each memory die on the memory chip, and the repair device and the controller in the main chip can perform a method similar to the repair device and controller in the structure shown in FIG.
  • the controller and the repair device may not be provided in the logic die of the memory chip in the MCU.
  • the chip scale is getting larger and the operating frequency is getting higher and higher, for example, DRAM is a large-capacity and high-density semiconductor memory.
  • DRAM is a large-capacity and high-density semiconductor memory.
  • redundant rows may be deployed in the storage die of the memory chip to replace the failed data rows.
  • the repair technology based on redundant rows may be referred to as a row redundancy (Row Redundancy) technology .
  • the storage die may include: at least one storage unit and at least one redundant unit.
  • a storage die may be divided into rows on the grains deployed on itself, each row comprising one or more smallest cells.
  • the storage die can divide multiple rows divided on its own grain into at least one data storage area and at least one redundant area, and configure the original address segment for each data storage area, and configure redundant addresses for each redundant area segment, wherein each original address segment and each redundant address segment do not overlap each other.
  • each data storage area may include at least one storage unit, each storage unit may include one data row or multiple data rows, and the original address of each storage unit belongs to the data storage area to which the storage unit belongs.
  • Original address segment; each redundant area may include at least one redundant unit, each redundant unit may include 1 redundant row or multiple redundant rows, and the redundant address of the redundant unit of each redundant area It belongs to the redundant address segment corresponding to the redundant area to which the redundant unit belongs.
  • the number of rows contained in each redundant cell may be the same as the number of rows contained in each memory cell.
  • the failed memory cell can be called a failed cell, and the memory chip uses the redundant cell located in the redundant area to replace the failed cell to complete the data access operation to improve the chip yield.
  • M data storage areas and N redundancy areas may be deployed on the storage die.
  • M and N are positive integers, and in one example, M ⁇ N.
  • the correspondence between the M data storage areas and the N redundant areas can be flexibly configured.
  • one data storage area may correspond to one redundant area, and based on this, the redundant unit in the redundant area may only be used to replace the failed unit in the data storage area corresponding to the corresponding redundant area.
  • multiple data storage areas may correspond to one redundant area, and based on this, redundant units in the redundant area may be used to replace failed units in multiple data storage areas, that is, multiple data storage areas The storage units in a redundant area can share redundant units in a redundant area.
  • a memory die may include multiple banks, and each block may include multiple sectors.
  • each bank can have a data storage area and a redundancy area.
  • each bank can set up a data storage area, and multiple banks can set up a redundant area.
  • each sector can have a data storage area and a redundancy area.
  • each sector can set up a data storage area, and multiple sectors can set up a redundant area.
  • each storage unit may include at least one data row, and the number of redundant rows included in each redundant unit may be the same as the number of data rows included in each storage unit.
  • each sector set a data storage area and a redundant area as an example, the ratio of the number of rows located in the data storage area to the number of redundant rows located in the redundant area in each sector can be agreed Scale, for example 2K:16.
  • each storage die contains multiple banks, wherein each sector in a part of the bank may deploy a redundant area, and each sector in another part of the bank may not deploy a redundant area.
  • a bank may contain multiple sectors, wherein some sectors may deploy redundant areas, and other sectors may not deploy redundant areas. The embodiments of the present application are not limited thereto.
  • FIG. 4 is a schematic diagram 1 of an interaction flow of a method for accessing a storage unit according to an embodiment of the present application.
  • the execution body of the embodiment of the present application may include: a repair device and a storage device.
  • the storage device may be a storage die including at least one storage unit and at least one redundant unit.
  • the repair device may be located on a logic die containing a controller, and the repair device may communicate with the storage die through the controller.
  • the repair apparatus receives an access request including an access address from a bus; the access address includes an original address of at least one storage unit in the storage apparatus.
  • the repairing device may receive an access request from an IO bus through an external interface.
  • the access request can be a read command or a write command.
  • the read instruction may contain the memory address of the memory cell requested to be read.
  • the write instruction may include a request for data to be written, and a target address of the data, that is, a storage address of a storage unit where the data is to be stored.
  • the access request may also be a refresh request.
  • the access request may be any data processing request including a storage address of data.
  • the storage device may configure an original address segment for all storage units in the storage device, and configure all redundant storage units in the storage device with an original address segment.
  • the unit configures redundant address segments.
  • the storage die includes at least one data storage area and at least one redundant area, each data storage area includes at least one storage unit, and the original address of each storage unit belongs to the original address segment; each redundant area At least one redundant unit is included, and the redundant address of each redundant unit belongs to the redundant address segment.
  • the memory chip only presents the original address segment to the outside world, that is, the address included in the access request is the original address of the storage unit.
  • the access address may be a logical block address (Logical Block Address, LBA), also referred to as a logical block address.
  • LBA Logical Block Address
  • the original address area is LBA001 to LBA399
  • the redundant address area may be LBA400 to LBA420.
  • the repair device identifies whether there is a failed unit in the storage unit pointed to by the access address according to the global repair information; wherein the global repair information includes the original address of at least one failed unit existing in the storage device and the replacement A redundant address of a redundant unit of each of the at least one failed unit.
  • the repair apparatus may identify whether the access address includes the original address of the failed unit according to the global repair information.
  • the global repair information may be stored on the repair device, and the repair device may continuously update the global repair information during the operation of the chip.
  • the repair device can learn the information of the failed unit detected by the storage device during the process of reading and writing data, refreshing data, detecting and maintaining, etc., and assigns redundant units to it, and adds newly detected units to the global repair information.
  • the global repair information may include original addresses of all detected failed cells in the storage device and redundant addresses of redundant cells used to replace each failed cell.
  • the repairing device can also detect the original address of the failed unit by the storage device in the testing phase and the redundant unit allocated by the repairing device for each failed unit.
  • the corresponding relationship information of the redundant addresses is stored in the efuse.
  • the repairable device can read the repair information recorded in the test phase from the efuse as the initial global repair information.
  • the repair device when recognizing that there is a first failed unit in the storage unit pointed to by the access address, the repair device replaces the original address pointing to the first failed unit in the access address with the redundant address of the first redundant unit corresponding to the first failed unit .
  • the access address contains an original address pointing to the first failed unit
  • the first failure unit is any failure unit.
  • the access address includes the first original address
  • the logic die queries the global information table to determine that the first storage unit pointed to by the first original address has failed, and the failed first storage unit is the first failed unit, and further The global information table is queried to obtain the first redundant address corresponding to the first original address, wherein the first redundant unit pointed to by the first redundant address is used to replace the first failed unit pointed to by the first original address.
  • the access address may include the address range LBA001 to LBA010, assuming that LBA002 and LBA004 are the original addresses of the failed units recorded in the global repair information, if the original address is the redundant address of the redundant unit corresponding to the storage unit of LBA002 is LBA500, the redundant address of the redundant unit corresponding to the storage unit whose original address is LBA004 is LBA501, then the replaceable access addresses can be LBA001, LBA500, LBA003, LBA501, LBA005 to LBA010.
  • the repairing device sends the replaced access request to the storage device.
  • the replaced access request includes the first redundant address corresponding to the first redundant unit.
  • the storage device is a storage die
  • the repair device located on the logical die can send the replaced access request to the storage die through the controller on the logical die.
  • the storage device completes the access process based on the redundant unit pointed to by the redundant address.
  • the storage device can access redundant addresses.
  • the access request when the access request is a write command, the access request further includes data to be written, the storage device can write the data to be written into the redundant unit pointed to by the redundant address, and then the storage device can generate an access response. , which contains the redundant addresses of the redundant cells that store the data to be written.
  • the storage device when the access request is a read command, the storage device may read data stored in the redundant unit pointed to by the redundant address, including data read from the redundant unit pointed to by the redundant address.
  • the storage device sends an access response to the repair device, where the access response includes the redundant address of the first redundant unit.
  • the access response when the access request is a write command, the access response includes the redundant address of the redundant unit storing the data to be written. In yet another example, when the access request is a read command, the access response includes data read from the redundant unit pointed to by the redundant address.
  • the storage device is a storage die
  • a repair device located on the logical die may receive an access response sent by the storage device through a controller on the logical die.
  • the repairing device obtains, according to the global repair information, the original address of the first failed unit corresponding to the redundant address of the first redundant unit, and replaces the redundant address pointing to the first redundant unit in the access response is the original address of the first failed unit.
  • the access response may contain an address range consisting of LBA001, LBA500, LBA003, LBA501, LBA005 to LBA010, assuming that LBA500 and LBA501 are the redundant addresses of the redundant units recorded in the global repair information, if the redundant addresses are The original address of the storage unit corresponding to the storage unit of LBA500 is LBA002, and the original address of the failed unit corresponding to the redundant unit whose redundant address is LBA501 is LBA004, so the replaceable access addresses can be LBA001 to LBA010.
  • the global repair information may support using the original address of the failed unit to query the redundant address of the corresponding redundant unit, and may also support using the redundant address of the redundant unit to reversely query the original address of the corresponding failed unit.
  • the repair apparatus may store the global repair information as redundant address mapping information and original address reverse mapping information, respectively, and the repair apparatus may query the original address of the storage unit according to the redundant address mapping information when receiving an access request. The address corresponds to the redundant address of the redundant unit. When receiving the access response, the repairing apparatus may also query the original address of the corresponding storage unit according to the redundant address of the redundant unit.
  • the repair device sends the replaced access response to the bus.
  • the restoration device and the storage device cooperate to realize the process of completing data access based on the redundant unit.
  • the restoration device realizes the redundancy replacement and restoration according to the global restoration information, and the control function of the redundancy replacement restoration can be implemented on the logic die with more advanced technology, and the storage die does not need to be provided with support A circuit for switching row selection signals, wherein the circuit for switching row selection signals is used to directly transfer the row selection signal of the failed row pointing to the normal data storage area to the row in the redundant area for replacing the redundant row of the failed row circuit for marking signals.
  • the circuit structure on the memory die is greatly simplified.
  • the technical solutions provided by the embodiments of the present application can reduce the area of the tiled area occupied by the storage die by simplifying unnecessary circuits in the storage die without reducing the storage capacity.
  • the area of the tiled area occupied by the final memory chip product can be greatly reduced, that is, with a smaller die.
  • the area realizes the redundant replacement function, saves the storage die area, and makes the product more miniaturized.
  • each redundant unit may be one row in the sector.
  • the minimum replacement unit can realize more fine-grained planning and utilization of redundant resources, and flexibly and comprehensively repair the failed unit in each sector. For example, when there are 3 failed rows in a sector, and the interval between the 3 failed rows exceeds 8 rows, if the minimum replacement unit is 8, the 16 redundant row resources can actually only repair 2 failed rows. Then the sector cannot be repaired.
  • the minimum replacement unit is one row, 16 redundant row resources can repair the three failed rows, so that the sector can be repaired and used.
  • Embodiments of the present application further provide technical solutions related to a method for repairing a group of storage units.
  • the method for repairing provided by the embodiments of the present application may be executed before executing the method for accessing storage units in the foregoing embodiments.
  • the repairing apparatus may acquire or update the global repairing information through the repairing method for the storage unit provided in the embodiment of the present application.
  • the repair apparatus may update the global repair information in the following manner.
  • the embodiment of the present application may further include:
  • the storage device detects whether there is a failed unit in the storage units in the storage device.
  • the storage device may be a storage die.
  • the memory die may detect a failed unit when executing instructions such as a read data command, a data write command, and a refresh command. This embodiment of the present application does not limit this.
  • the failure unit detected by the storage device may be the second failure unit, where the second failure unit may be the first failure unit in the foregoing embodiment or another failure unit.
  • the storage device sends the detected original address of the failed unit to the repairing device.
  • the storage device is a storage die, and when the repair device is located on a logic die including the controller, the storage device may send the original data of the failed unit to the repair device through the controller. As an example, the storage device may send the original address of the failed unit to the repair device when there is a failed unit.
  • the original address of the detected failed unit may be recorded as the original address of the second failed unit.
  • the repairing apparatus allocates a redundant unit for replacing the detected failed unit.
  • the redundant unit used to replace the second failed unit may be the second redundant unit.
  • the storage device may include at least one data storage area and at least one redundant area.
  • each data storage area includes at least one storage unit
  • each redundant area includes at least one redundant unit
  • the storage device can allocate original address segments to the storage units belonging to the respective data storage areas, and, for the storage units belonging to the respective redundant areas
  • the redundant units of the area are allocated redundant address segments.
  • the addresses of any redundant address segment and any original address segment do not overlap.
  • the storage device may include M data storage areas and N redundancy areas, where M and N are positive integers. As an example, M may be greater than or equal to N.
  • redundant units may be allocated based on the principle of proximity.
  • the storage device may be provided with X functional areas, wherein each functional area may include 1 data storage area, and the number of redundant areas in at least one of the X functional areas is not zero.
  • each functional area may include 1 data storage area, and the number of redundant areas in at least one of the X functional areas is not zero.
  • the repairing device allocates redundant units, it can preferentially allocate redundant units belonging to the same functional area to the failed units. If the redundant units belonging to the same functional area have been allocated, redundant units in other functional areas can be selected.
  • the functional area may be a sector or a block.
  • the storage device may further set a high-level functional area and a low-level functional area, wherein each high-level functional area includes at least one low-level functional area, each low-level functional area includes at least one data storage area, and all of the low-level functional areas include at least one low-level functional area.
  • the number of redundant areas of at least one lower-level functional area is not zero.
  • high-level functional areas can be blocks and low-level functional areas can be sectors. Each block may include at least one sector.
  • the storage device may include block 0 and block 1, block 0 includes sector 0 (denoted as S01) and sector 1 (denoted as S02), and block 1 includes sector 0 (denoted as S11).
  • the storage device may set a redundant area on at least one of the four sectors S01, S02, S11 and S12.
  • the storage device may include a first storage unit located at S01 and a first redundant unit located at S01, and in yet another example, the storage device may include a first storage unit located at S01 and a first redundant unit located at S02. In yet another example, the storage device may include a first storage unit located at S01 and a first redundant unit located at S11.
  • the repair device can preferentially select the redundant unit in the redundant area corresponding to the same low-level functional area as the first redundant unit; if the redundant units in the redundant area corresponding to the same low-level functional area have been allocated, the same In the high-level functional area, select the redundant unit in the redundant area of the nearest low-level functional area; if the redundant units in the redundant area corresponding to the nearest low-level functional area have been allocated, the same high-level functional area can be used. Redundant units in the redundant areas of other low-level functional areas in the area; if the redundant units in the redundant areas of the same high-level functional area have been allocated, you can select the redundant units in the redundant areas of other high-level functional areas. redundant unit.
  • the redundant unit in is the first redundant unit corresponding to the first failed unit.
  • the redundant units in the redundant area belonging to the same sector have been allocated, select the redundant unit in the redundant area in the nearest sector that belongs to the same bank as the first data storage area as the first data storage area.
  • the first redundant unit corresponding to the failed unit is selected as the corresponding first failed unit.
  • the redundant cells in the redundant areas in all banks on the storage die select the redundant cells in the redundant area in the storage die closest to the storage die as the redundant cells in the redundant area.
  • the first redundant unit corresponding to the first failed unit may be located in the same sector, or, alternatively, the first failed unit and the first redundant unit may be located in different sectors of the same bank , or, the first failed unit and the first redundant unit may be located in different banks of the same memory die.
  • the embodiment of the present application can actually realize cross-sector/cross-block sharing of global redundant resources, effectively improving the utilization rate of redundant resources , thereby improving the chip yield.
  • the failure unit of each sector and each block can be repaired. For example, when the number of rows of failed units in a sector exceeds the number of rows of redundant units configured in the sector, a comprehensive repair can be performed by scheduling idle redundant units in other sectors to avoid appearing in the entire storage system. When there are spare redundant units on the chip, it is still impossible to repair the situation that a large number of failed units in a certain sector are concentrated.
  • the repair apparatus adds the original address of the detected failure unit and the allocated redundant address of the redundant unit to the global repair information.
  • the global repair information may include one or more groups of corresponding relationships between the failed units and the redundant units.
  • steps S201 to S204 may also be executed after step S101.
  • this repair method when the storage device detects a failed unit, it can notify the repair device to allocate the corresponding redundant unit, so that the global update can be dynamically updated during the process of executing read and write instructions, refresh instructions, etc. that can trigger the detection of the failed unit. Repair information.
  • the access method of the storage unit is executed, the read and write operations can be performed on the redundant unit, and the use of the failed unit can be avoided, so that the access speed of the storage chip can be improved.
  • FIG. 5 is a schematic diagram of an interaction flowchart of a method for repairing a storage unit provided by an embodiment of the present application.
  • the repairing apparatus may also obtain the global repairing information in the following manner.
  • a one-time programmable memory may also be deployed in the repair device or the logic die where the repair device is located.
  • the corresponding information of the replacement unit that is, the repair information recorded in the test phase, is stored in efuse.
  • the repair device can read the repair information written in the test phase from the efuse as the initial global repair information, and continuously update the global repair information in combination with the method in FIG. 4 .
  • the steps in this embodiment of the present application may further include:
  • the repair device sends a failure detection indication to the storage device.
  • the failure detection indication may be a test command obtained from the IO bus, for example, may be a write command, a read command or a refresh command, wherein the carrying access address is the original address corresponding to all rows on the storage die.
  • the repair device may send various messages to the storage device through the controller.
  • the storage device detects whether there is a failed unit in the storage unit.
  • the failure unit detected by the presence device before packaging may be the third failure unit, and the third failure unit may be the first failure unit in the foregoing embodiment, or may be another failure unit.
  • the storage device sends the detected original address of the failed unit to the repairing device.
  • the repair apparatus allocates a redundant unit for replacing the failed unit.
  • the redundant unit used to replace the third failed unit may be denoted as the third redundant unit.
  • steps S302-S304 is similar to that of S201-S203, and reference may be made to the relevant descriptions in S201-S203.
  • the repairing device writes the original addresses of all the failed units and the redundant addresses of the corresponding redundant units into the efuse.
  • the original addresses of all the failed units and the redundant addresses of the corresponding redundant units recorded in the test phase may be referred to as test repair information.
  • the repairing apparatus writes the original addresses of all the failed cells detected before encapsulation and the redundant addresses of the redundant cells corresponding to each failed cell into the efuse at one time.
  • the repair device when powered on, the repair device reads the original addresses of all failed units and the redundant addresses of the corresponding redundant units stored in the efuse, and uses them as initial global repair information.
  • the repair device can directly obtain this part of the repair information every time it is powered on, which avoids repeated detection after each power-on, thereby reducing the need for repeated detection and repair work.
  • the energy consumption of the bare chip improves the access efficiency of the memory chip.
  • the above two repair methods can respectively perform the repair work of the memory cell when the memory chip is in the working state and when the memory chip is in the test stage, and the memory chip can support the execution of the above two repair methods at the same time.
  • FIG. 6 is a schematic diagram of a system architecture and a processing flow when the method for accessing a memory cell provided by an embodiment of the present application is applied to a DRAM.
  • the memory chip in this embodiment of the present application may include: a logic die 610 and a DRAM die (DRAM die) 620 .
  • the logic die may include: a DRAM controller (DRAM controller) 601, a redundant row address mapping (Redundent Row Address Mapping) module 603, a global repair information (Repair info) management module 604, an original address reverse mapping (Original Row Address Reverse Mapping) module 605.
  • the modules 603 to 605 may constitute the repair device 602 .
  • the DRAM die 620 may include a row decoder (Row Decoder) 606 and a memory array arranged as blocks and sectors (the right portion of the row decoder in FIG. 6).
  • the row decoder is also called a row address decoder or a row address decoding module.
  • redundant storage resources used for failure repair can be evenly distributed in each Sector or Bank on the DRAM Die , for example, every 2K rows can be equipped with 16 redundant rows (as shown by the gray block in Figure 6); on the other hand, the control of replacing and repairing failed rows with redundant rows is implemented on the logic die, and on the DRAM die It is no longer necessary to set up replacement repair related logic.
  • the storage unit is one data row and the redundant unit is one redundant row, wherein each row can be recorded as 1WLs).
  • the steps in this embodiment of the present application may include two parts: steps in the chip testing process and steps in the normal use phase of the chip.
  • the steps in the chip testing stage may include:
  • Step 1 If a DRAM bare chip finds a failed cell in the normal data storage area, it is determined which redundant row to use for replacement according to the allocation strategy. For example, according to the principle of proximity, the failed cell located in the same sector or the same bank can be preferentially selected. the failed unit. All the repair information of the memory chip is burned and written on the logic die, and it needs to be recorded in the global repair information management module by programming efuse. In the normal use scenario, when the chip is powered on, the global repair information management module reads the repair information recorded in the test phase from the efuse and transfers it to the redundant row address mapping module and the original row address reverse mapping module.
  • the global repair information management module on the logic die is mainly composed of efuse resources, and is used to record the global redundant row repair information of the chip.
  • the failure repair information can record the target failure row that needs to be replaced according to the redundant behavior unit, and also need to consider mechanisms such as fault tolerance and supplementary records.
  • the global repair information management module can also be called the efuse module.
  • Step 2 in the normal use scenario, when the user initiates read and write access to the chip, the read and write commands will first enter the redundant row address mapping module for processing, and the redundant row address mapping module identifies the invalid row in the original access address. address, and replace the original invalid row address with the redundant row address according to the determined replacement strategy.
  • a content addressable memory (Content Addressable Memory, CAM) is used in the redundant row address mapping module to form a failed row address mapping table with redundant row addresses.
  • the CAM search is performed for the row address in each access instruction, and the invalid row address in the match will be replaced with the corresponding CAM address (ie, redundant row address).
  • the replacement strategy may be the principle of proximity, the principle of balance, etc. For example, the redundant unit in the redundant area in the sector with the lowest usage rate in the same bank is preferentially selected.
  • Step 3 the access command after the invalid row address is replaced by the redundant row address will normally enter the controller for processing.
  • the controller sends corresponding commands to the DRAM die according to the DRAM timing.
  • Step 4 The row address decoding module on the DRAM bare chip decodes the received row address into a row selection signal, among which redundant rows are also addressed uniformly, and the addressing of redundant rows can be within the address range of normal data rows. outside). For the instruction that has been replaced with the redundant row address, it is directly decoded as the row select signal of the redundant row. At this time, all access operations are actually operations on the smallest unit in the redundant row.
  • each storage unit may include at least one row and at least one column of the smallest unit.
  • the storage unit includes 1 row and column address.
  • Step 5 After the controller completes the operation on the DRAM bare chip, it will return corresponding read and write responses and read data. For read and write operations of redundant rows, the controller will normally return the corresponding redundant row address information to the original address reverse mapping module.
  • Step 6 the original address reverse mapping module will check out the redundant row address, and look up an original row address reverse mapping table, after converting the redundant row address in the read and write response to the original row address, the read and write response and The read data is returned to the user side. The user is not aware of the redundant replacement operation of the invalid address.
  • the original row address reverse mapping table in the foregoing embodiment may be a global information table.
  • the original address reverse mapping module may use the SRAM to form an original row address reverse mapping table with redundant row addresses.
  • the address of each failed cell is recorded in the SRAM.
  • the redundant row address is used to find the corresponding original address in the SRAM, and reverse replacement is performed .
  • the global repair information management module, the redundant row address mapping module, and the original row address reverse mapping module cooperate with other modules to support the global redundancy replacement and repair of the entire chip, and support the fine-grained single row Replacement fixes.
  • the embodiment of the present application also provides a repairing device.
  • FIG. 7 is a first structural schematic diagram of a repairing device provided by an embodiment of the present application.
  • the repairing apparatus in this embodiment of the present application may include: a transceiver module 801 and a processing module 802 , wherein the transceiver module is configured to communicate with a bus and a storage device.
  • the repair apparatus may further include a storage module 803 .
  • the transceiver module is configured to receive an access request including an access address; the access address includes an original address of at least one storage unit in the storage device.
  • a processing module configured to identify whether there is a failed unit in the storage unit pointed to by the access address according to the global repair information; wherein, the global repair information includes the original address of at least one failed unit existing in the storage device and an A redundant address of a redundant unit that replaces each of the failed units in the at least one failed unit; when it is recognized that there is a first failed unit in the storage unit pointed to by the access address, pointing the access address to the The original address of the first failed unit is replaced with the redundant address of the first redundant unit corresponding to the first failed unit.
  • the transceiver module is further configured to send the replaced access request to the storage device.
  • the transceiver module is further configured to receive, before the receiving the access request including the access address, the original address of the second failure unit existing in the storage device sent by the storage device;
  • the processing module is used for assigning a second redundant unit for replacing the second failed unit; and for adding the corresponding relationship between the original address of the second failed unit and the redundant address of the second redundant unit to the global repair information, wherein the second failure unit and the first failure unit are the same or different.
  • the repair device includes a one-time programmable memory efuse; the transceiver module is further configured to receive the storage device sent by the storage device before receiving the access request including the access address. the original address of the third failed unit existing before encapsulation in the device; the processing module is further configured to allocate a third redundant unit used to replace the third failed unit existing before encapsulation; The corresponding relationship between the original address of the third failed unit and the redundant address of the third redundant unit existing before encapsulation is stored in the efuse; The corresponding relationship between the original address of the third failed unit and the redundant address of the third redundant unit in the storage device read in efuse is added to the global repair information; wherein, the third failed unit and the third A failed unit is the same or different.
  • the transceiver module is further configured to receive an access response including the redundant address of the first redundant unit sent by the storage device; the processing module is further configured to obtain the the original address of the first failed unit corresponding to the first redundant unit; adding the original address of the first failed unit to the access response; the transceiver module is further configured to include the first failed unit The original address of the access response is sent to the bus.
  • the transceiver module is configured to receive the original address of the failed unit existing in at least one storage unit of the storage device sent by the storage device.
  • a processing module configured to allocate a redundant unit for replacing the failed unit; and configured to add the original address of the failed unit and the redundant address of the redundant unit to the global repair information.
  • the repairing device includes a one-time programmable memory efuse
  • the transceiver module is specifically configured to receive the original address of at least one failed unit existing before encapsulation in the storage device sent by the storage device; redundant unit; and be specifically used for storing the correspondence relationship between the original address of each failed unit before encapsulation and the redundant address of the redundant unit corresponding to each failed unit in the efuse; in the repair device After each power-on, the corresponding relationship between the original address of at least one failed unit existing in the storage device read from the efuse and the redundant address of the redundant unit corresponding to each failed unit is added to the corresponding relationship. global repair information.
  • Embodiments of the present application further provide a storage device.
  • FIG. 8 is a first schematic structural diagram of a storage device according to an embodiment of the present application.
  • the storage device in this embodiment of the present application may include: a transceiver module 901 and a processing module 902 , wherein the transceiver module is configured to communicate with the bus and the storage device.
  • the storage device may further include a storage module 903 .
  • a transceiver module configured to receive an access request including an access address sent by a repair device, wherein the access address includes a redundant address of a redundant unit in the storage device; wherein the redundant unit is used to replace the a failure unit in at least one storage unit; a processing module for accessing the redundant address; a transceiver module for sending an access response to the repairing device.
  • the processing module is further configured to detect whether there is a failed unit in the storage unit in the storage device before receiving the access request including the access address sent by the repairing device; the transceiver module is further configured to , when there is a failed unit in the storage unit in the storage device, send the original address of the failed unit to the repair device, so that the repair device allocates the redundant unit for replacing the failed unit , and the corresponding relationship between the original address of the failed unit and the redundant address of the redundant unit is added to the global repair information.
  • the processing module is used for detecting whether there is a failed unit in the storage device.
  • the transceiver module is configured to send the original address of the failed unit to the repair device when there is a failed unit in the storage unit in the storage device.
  • the processing module is specifically used to detect whether there is a failed unit in the storage unit in the storage device before the storage device is packaged; the transceiver module is specifically used for the storage unit in the storage device. When there is a failed unit in the storage unit, the original address of the failed unit is sent to the repairing device.
  • FIG. 9 is a first schematic structural diagram of a repairing apparatus provided by an embodiment of the present application; as shown in FIG. 9 , the repairing apparatus in this embodiment of the present application may include: an interface 1110, a processor 1120, and a memory 1120; wherein, the interface is used for A storage device is connected; the memory is used to store the instructions; the processor is used to execute the instructions to implement the methods in the foregoing embodiments.
  • the repair apparatus may also include a bus 1160 for internal interconnection.
  • the storage device is a storage die, and the repair device is a logic die; or, the storage device is a storage die, and the repair device is located on a logic die including a controller , and the repair device is connected to the storage die through the controller; or, the storage device is a memory chip, and the repair device is a main chip; or, the storage device is a memory chip, and the repair device A device is located on a host chip that includes a controller, and the repair device is connected to the memory chip through the controller.
  • the memory further includes: a one-time programmable memory efuse.
  • the memory die may be a DRAM die and the controller may be a DRAM controller.
  • FIG. 10 is a schematic structural diagram 1 of a storage device provided by an embodiment of the present application; as shown in FIG. 10 , the storage device in the embodiment of the present application may include: an interface 1210, a processor 1220, and a memory 1230; wherein, the interface is used for The repairing device is connected; the memory is used to store the instructions; the processor is used to execute the instructions to implement the method in the foregoing embodiment.
  • the storage device may also include a bus 1260 for internal interconnection.
  • the storage device is a storage die, and the repair device is a logic die; or, the storage device is a storage die, and the repair device is located on a logic die including a controller , and the repairing device is connected to the storage die through the controller.
  • the embodiment of the present application further provides a repairing device, and the repairing device can be used to execute the method performed by any repairing device in the foregoing embodiments.
  • the repair device may be a logic die in a memory chip.
  • the repair device may be located on a logic die in a memory chip, on which a controller may also be deployed.
  • the repairing device can communicate with the bus, and can also communicate with the memory die in the memory chip through the controller.
  • An embodiment of the present application further provides a storage device, and the storage device can be used to execute the method executed by any of the storage devices in the foregoing embodiments.
  • the memory device may be a memory die in a memory chip.
  • the memory device may be located on a memory die in a memory chip.
  • Embodiments of the present application further provide a logic die, where the logic die can be used to execute the method performed by any of the repair apparatuses in the foregoing embodiments.
  • the logic die may include a repair device and a controller.
  • the repairing device may also be located in the controller, which is not limited in this application.
  • Embodiments of the present application further provide a storage die, and the memory die can be used to execute the method executed by any of the storage devices in the foregoing embodiments.
  • Embodiments of the present application further provide a memory chip, where the memory chip may include a logic die and a memory die, wherein the logic die includes a repair device and a controller, and the memory die may be used to execute any one of the memory chips in the foregoing embodiments.
  • the repairing device may be used to execute the method performed by any repairing device in the foregoing embodiments.
  • the embodiment of the present application further provides a main chip, the main chip can communicate with the bus and the memory chip, and the main chip can be used to execute the method performed by any repairing apparatus in the foregoing embodiments.
  • the main chip may include a repair device and a controller.
  • the repairing device may also be located in the controller, which is not limited in this application.
  • the embodiment of the present application further provides a memory chip, the memory chip can communicate with the main chip, and the memory chip can be used to execute the method executed by any of the storage devices in the foregoing embodiments.
  • Embodiments of the present application further provide a controller, where the controller is located on a logic die, and the controller can be configured to forward an access instruction sent by a restoration device to a storage die, and forward an access response and restoration information sent by the storage die to the restoration device Wait.
  • the controller is configured to receive an access command sent by the repair device, where the access command includes a redundant address pointing to a redundant unit in the storage die, wherein the redundant unit is used to replace the memory unit in the storage die. Failing units, the controller can forward the access instructions to the memory die.
  • the controller may also receive an access response sent by the memory die, where the access response includes an access result obtained when the access request is performed based on the redundant address of the redundant unit, and the controller may include the redundant address of the redundant unit.
  • the access response is forwarded to the repair device.
  • the controller may be a DRAM controller.
  • the above-mentioned embodiments it may be implemented in whole or in part by software, hardware, firmware or any combination thereof.
  • software it can be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions.
  • the computer program instructions when loaded and executed on a computer, result in whole or in part of the processes or functions described herein.
  • the computer may be a general purpose computer, special purpose computer, computer network, or other programmable device.
  • the computer instructions may be stored in or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions may be downloaded from a website site, computer, server or data center Transmission to another website site, computer, server, or data center by wire (eg, coaxial cable, optical fiber, digital subscriber line) or wireless (eg, infrared, wireless, microwave, etc.).
  • the computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that includes an integration of one or more available media.
  • the usable media may be magnetic media (eg, floppy disks, hard disks, magnetic tapes), optical media (eg, DVD), or semiconductor media (eg, Solid State Disk), and the like.

Abstract

一种存储单元的访问方法、修复方法、裸片和存储芯片。方法包括：接收包含访问地址的访问请求；访问地址包括存储装置中的至少一个存储单元的原始地址（S101）；根据全局修复信息识别访问地址指向的存储单元中是否存在失效单元；其中，全局修复信息包含所有失效单元的原始地址与用于替代各个失效单元的冗余单元的冗余地址（S102）；在识别到存在第一失效单元时，将访问地址中指向第一失效单元的原始地址替换为第一失效单元对应的第一冗余单元的冗余地址（S103）；将替换后的访问请求发送至存储装置（S104）。

Description

存储单元的访问方法、修复方法、裸片和存储芯片 技术领域
本申请涉及存储技术领域，尤其涉及一种存储单元访问方法、修复方法、裸片和存储芯片。
背景技术
随着半导体技术的飞速发展，具有存储功能的存储芯片的规模越来越大。
为了确保芯片良率，在芯片测试过程中，如果在正常的数据存储区发现有失效行，则需要通过烧写一次性可编程存储器(efuse)，将失效行的行选信号切断，同时接通用于替换的冗余行的行选信号。在执行烧写操作之后，当接收到用户对指向失效行的原始行地址进行读写访问的请求时，行译码器对原始行地址执行行译码操作之后选中的行选信号为冗余行的行选信号。之后，将待写入数据存储在冗余行或者读取存储在冗余行中的数据。在对冗余行进行读写操作之后，在返回给用户的响应消息中携带原始行地址。在这一过程中，用户对冗余行的替换操作不感知。
目前，为了通过烧写efuse切换行选信号，存储裸片上需要部署逻辑复杂的行选信号切换电路，这使得产品存在体积较大的问题。
发明内容
本申请提供了一种存储单元的访问方法、修复方法、裸片和存储芯片，能够在实现失效替换的基础上减小产品的体积。
第一方面，提供一种存储单元的访问方法，应用于修复装置，所述方法包括：
接收包含访问地址的访问请求；所述访问地址包括存储装置中的至少一个存储单元的原始地址；
根据全局修复信息，识别所述访问地址指向的至少一个存储单元中是否存在失效单元；其中，所述全局修复信息包含所述存储装置中存在的至少一个失效单元的原始地址与用于替代所述至少一个失效单元中每个失效单元的冗余单元的冗余地址；
在识别到所述访问地址指向的至少一个存储单元中存在第一失效单元，将所述访问地址中指向所述第一失效单元的原始地址替换为所述第一失效单元对应的第一冗余单元的冗余地址；
将替换后的访问请求发送至所述存储装置。
在本申请实施例中，通过修复装置在接收包含访问地址的访问请求时，修复装置根据全局修复信息，识别访问地址指向的存储单元中是否存在失效单元，在识别到访问地址指向的存储单元中存在第一失效单元时，将访问地址中指向第一失效单元的原始地址替换为第一失效单元对应的冗余单元的冗余地址，并将替换后的访问请求发送至存储装置，可以实现利用冗余单元修复失效单元。采用本申请实施例提供的技术方案，由于不需要为存储装置中的存储单元配置支持逻辑复杂的切换行选信号的电路，能够简化存储装置中的非必要的电路，进而可以减少存储装置占用的平铺区域的面积，从而能够使得最终的产品占用的平铺区域的面积大幅缩小，产品更加小型化。
在一种可能的实现方式中，所述存储装置为存储裸片，所述修复装置为逻辑裸片。
在一种可能的实现方式中，所述存储装置为存储裸片，所述修复装置位于包含控制器的逻辑裸片上，且所述修复装置通过所述控制器与所述存储裸片相连。
在一种可能的实现方式中，所述存储装置为存储芯片，所述修复装置为主芯片。
在一种可能的实现方式中，所述存储装置为存储芯片，所述修复装置位于包含控制器的主芯片上，且所述修复装置通过所述控制器与所述存储芯片相连。
作为一种示例，存储裸片可以包括行译码器。行译码器用于与逻辑裸片相连。
作为一种示例，存储裸片包含至少一个存储单元和至少一个冗余单元。失效单元为发生故障失效的存储单元，冗余单元用于替代失效单元执行访问请求。
作为一种示例，存储裸片可以包含至少一个数据存储区和至少一个冗余区。存储裸片中的各个存储单元位于各个数据存储区，各个冗余单元位于各个冗余区。在一示例中，一个数据存储区可以对应一个冗余区，基于此，冗余区中的冗余单元可以仅用于替代所属冗余区对应的数据存储区中的失效单元。在又一示例中，多个数据存储区可以对应一个冗余区，基于此，冗余区中的冗余单元可以用于替代多个数据存储区中的失效单元，也即多个数据存储区中的存储单元可以共享一个冗余区中的冗余单元。
在实际应用中，存储裸片可以包括多个块，每个块可以包括多个扇区。
作为一种示例，每个块可以设置一个数据存储区和一个冗余区。作为一种示例，每个块可以设置一个数据存储区，多个块可以设置一个冗余区。
作为一种示例，每个扇区可以设置一个数据存储区和一个冗余区。作为一种示例，每个扇区可以设置一个数据存储区，多个块可以设置一个冗余区。
作为一种示例，每个存储单元可以为位于数据存储区中的行，每个冗余单元可以为位于冗余区中的行。
在本申请实施例中，存储单元的原始地址属于原始地址区段，冗余单元的冗余地址属于冗余地址区域；任一所述原始地址指向所述存储裸片的任一数据存储区中存储单元，任一所述冗余地址指向所述存储裸片中的任一冗余区中的冗余单元。
在一种可能的实现方式中，在所述接收包含访问地址的访问请求之前，所述方法还包括：
接收所述存储装置发送的所述存储装置中存在的第二失效单元的原始地址；
分配用于替代所述第二失效单元的第二冗余单元；
将所述第二失效单元的原始地址和所述第二冗余单元的冗余地址的对应关系添加到所述全局修复信息；
其中，所述第二失效单元与所述第一失效单元相同或不同。
在一种可能的实现方式中，所述修复装置包括一次性可编程存储器efuse；
在所述接收包含访问地址的访问请求之前，所述方法还包括：
接收所述存储装置发送的所述存储装置中在封装前存在的第三失效单元的原始地址；
分配用于替代在封装前存在的第三失效单元的第三冗余单元；
将所述在封装前存在的第三失效单元的原始地址和第三失效单元对应的冗余单元的冗余地址的对应关系存储在所述efuse中；
在所述修复装置每次上电后，将从所述efuse中读取到的所述存储装置中存在的至少一个失效单元的原始地址和各个失效单元对应的冗余单元的冗余地址的对应关系，添加到所述全局修复信息；
其中，所述第三失效单元与所述第一失效单元相同或不同。
在一种可能的实现方式中，所述方法还包括：
接收所述存储装置发送的包含所述第一冗余单元的冗余地址的访问响应；
根据全局修复信息，将所述第一冗余单元的冗余地址替换为所述第一失效单元的原始地址；
将包含所述第一失效单元的原始地址的所述访问响应发送至总线。
在一种可能的实现方式中，所述存储装置为存储裸片，所述修复装置位于包含控制器的逻辑裸片上，且所述修复装置通过所述控制器与所述存储裸片相连；
所述存储裸片包括至少两个数据存储区，所述全局修复信息包括所述至少两个数据存储区中的所有失效单元的原始地址与用于替换所述至少两个数据存储区中的各个失效单元的冗余单元的冗余地址。
在一种可能的实现方式中，任一存储单元为一个数据行，任一冗余单元为一个冗余行。
在一种可能的实现方式中，所述第一冗余单元与所述第一失效单元位于所述存储装置中的同一扇区；或者，所述第一冗余单元与所述第一失效单元位于所述存储装置中同一块中的不同扇区；或者，所述第一冗余单元与所述第一失效单元位于所述存储装置中的不同块。
第二方面，提供了一种存储单元的访问方法，应用于存储装置，所述存储装置包括至少一个存储单元，所述方法包括：
接收修复装置发送的包含访问地址的访问请求，其中，所述访问地址包括所述存储装置中的冗余单元的冗余地址；其中，所述冗余单元用于替代所述至少一个存储单元中的失效单元；
访问所述冗余地址；
向所述修复装置发送访问响应。
在一种可能的实现方式中，所述存储装置为存储裸片，所述修复装置为逻辑裸片；或者，
所述存储装置为存储裸片，所述修复装置位于包含控制器的逻辑裸片上，且所述修复装置通过所述控制器与所述存储裸片相连；或者，
所述存储装置为存储芯片，所述修复装置为主芯片；或者，
所述存储装置为存储芯片，所述修复装置位于包含控制器的主芯片上，且所述修复装置通过所述控制器与所述存储芯片相连。
在一种可能的实现方式中，在所述接收修复装置发送的包含访问地址的访问请求之前，所述方法还包括：
在所述存储装置中的存储单元中存在失效单元时，向所述修复装置发送所述失效单元的原始地址,以使所述修复装置分配用于替代所述失效单元的所述冗余单元，并将所述失效单元的原始地址和所述冗余单元的冗余地址之间的对应关系加入全局修复 信息。
第三方面，提供了一种存储单元的修复方法，应用于存储装置，所述方法包括：
在所述存储装置中的存储单元中存在失效单元时，向修复装置发送所述失效单元的原始地址，以使所述修复装置为分配用于替代所述失效单元的冗余单元。
在一种可能的实现方式中，所述在所述存储装置中的存储单元中存在失效单元时，向修复装置发送所述失效单元的原始地址，包括：
在所述存储装置封装前，检测所述存储装置中的存储单元中是否存在失效单元；
在所述存储装置中的存储单元中存在失效单元时，向所述修复装置发送所述失效单元的原始地址。
第四方面，提供了一种存储单元的修复方法，应用于修复装置，所述方法包括：
接收存储装置发送的所述存储装置中的存储单元中存在的失效单元的原始地址；
分配用于替换所述失效单元的冗余单元；
将所述失效单元的原始地址与所述冗余单元的冗余地址添加到全局修复信息。
在一种可能的实现方式中，所述修复装置包括efuse；所述接收存储装置发送的所述存储装置中的存储单元中存在的失效单元的原始址，包括：接收所述存储装置发送的所述存储装置中在封装前存在的至少一个失效单元的原始地址；
所述分配用于替换所述失效单元的冗余单元，包括：分配用于替代在封装前存在的各个失效单元的冗余单元；
所述将所述失效单元的原始地址与所述冗余单元的冗余地址添加到全局修复信息，包括：将所述在封装前存在的各个失效单元的原始地址和各个失效单元对应的冗余单元的冗余地址的对应关系存储在所述efuse中；在所述修复装置每次上电后，将从所述efuse中读取到的所述存储装置中存在的至少一个失效单元的原始地址和各个失效单元对应的冗余单元的冗余地址的对应关系，添加到所述全局修复信息。
第五方面，提供了一种修复装置，包括：
收发模块，用于接收包含访问地址的访问请求；所述访问地址包括存储装置中的至少一个存储单元的原始地址。
处理模块，用于根据全局修复信息，识别所述访问地址指向的存储单元中是否存在失效单元；其中，所述全局修复信息包含所述存储裸片中存在的至少一个失效单元的原始地址与用于替代所述至少一个失效单元中的每个失效单元的冗余单元的冗余地址；在识别到所述访问地址指向的存储单元中存在第一失效单元时，将所述访问地址中指向所述第一失效单元的原始地址替换为所述第一失效单元对应的第一冗余单元的冗余地址。
所述收发模块还用于将替换后的访问请求发送至所述存储装置。
在一种可能的实现方式中，所述收发模块还用于在所述接收包含访问地址的访问请求之前，接收所述存储装置发送的所述存储装置中存在的第二失效单元的原始地址；所述处理模块用于，分配用于替代第二失效单元的第二冗余单元；以及，用于将所述第二失效单元的原始地址和第二冗余单元的冗余地址的对应关系添加到所述全局修复信息；其中，第二失效单元与第一失效单元可以相同也可以不同。
在一种可能的实现方式中，所述修复装置包括一次性可编程存储器efuse；所述收 发模块还用于在所述接收包含访问地址的访问请求之前，接收所述存储装置发送的所述存储装置中在封装前存在的第三失效单元的原始地址；所述处理模块还用于分配用于替代第三失效单元的第三冗余单元；以及用于，将所述在封装前存在的第三失效单元的原始地址和第三冗余单元的冗余地址的对应关系存储在所述efuse中；以及用于，在所述修复装置每次上电后，将从所述efuse中读取到的所述存储装置中存在的第三失效单元的原始地址和第三冗余单元的冗余地址的对应关系，添加到所述全局修复信息。
在一种可能的实现方式中，收发模块还用于接收所述存储装置发送的包含所述第一冗余单元的冗余地址的访问响应；处理模块还用于根据全局修复信息，获取所述第一冗余单元对应的所述第一失效单元的原始地址；将所述第一失效单元的原始地址添加到所述访问响应中；所述收发模块还用于将包含所述第一失效单元的原始地址的所述访问响应发送至总线
第六方面，提供了一种存储装置，包括：
收发模块，用于接收修复装置发送的包含访问地址的访问请求，其中，所述访问地址包括所述存储装置中的冗余单元的冗余地址；其中，所述冗余单元用于替代所述至少一个存储单元中的失效单元；
处理模块，用于访问所述冗余地址；收发模块，还用于向所述修复装置发送访问响应。
在一种可能的实现方式中，处理模块还用于在所述接收修复装置发送的包含访问地址的访问请求之前，检测所述存储装置中的存储单元中是否存在失效单元；收发模块还用于，在所述存储装置中的存储单元中存在失效单元时，向所述修复装置发送所述失效单元的原始地址，以使所述修复装置分配用于替代所述失效单元的所述冗余单元，并将所述失效单元的原始地址和所述冗余单元的冗余地址之间的对应关系加入全局修复信息。
第七方面，提供了一种存储装置，包括：
处理模块，用于检测存储装置中是否存在失效单元。收发模块，用于在所述存储装置中的存储单元中存在失效单元时，向修复装置发送所述失效单元的原始地址。
在一种可能的实现方式中，处理模块具体用于在所述存储装置封装前，检测所述存储装置中的存储单元中是否存在失效单元；收发模块，具体用于在所述存储装置中的存储单元中存在失效单元时，向所述修复装置发送所述失效单元的原始地址。
第八方面，提供了一种修复装置，包括：
收发模块，用于接收存储装置发送的存储装置的至少一个存储单元中存在的失效单元的原始地址。
处理模块，用于分配用于替换所述失效单元的冗余单元；以及用于，将所述失效单元的原始地址与所述冗余单元的冗余地址添加到全局修复信息。
在一种可能的实现方式中，所述修复装置包括一次性可编程存储器efuse；
收发模块，具体用于接收所述存储装置发送的所述存储装置中在封装前存在的至少一个失效单元的原始地址；处理模块，具体用于分配用于替代在封装前存在的各个失效单元的冗余单元；以及具体用于将所述在封装前存在的各个失效单元的原始地址 和各个失效单元对应的冗余单元的冗余地址的对应关系存储在所述efuse中；在所述修复装置每次上电后，将从所述efuse中读取到的所述存储装置中存在的至少一个失效单元的原始地址和各个失效单元对应的冗余单元的冗余地址的对应关系，添加到所述全局修复信息。
第九方面，提供了一种修复装置，包括：接口，处理器和存储器；
其中，所述接口用于连接存储装置和总线；所述存储器，用于存储指令；所述处理器，用于执行指令以实现第一方面和第四方面任一方面或者任意可能实现方式中的方法。
在一种可能的实现方式中，所述存储装置为存储裸片，所述修复装置为逻辑裸片；或者，
所述存储装置为存储裸片，所述修复装置位于包含控制器的逻辑裸片上，且所述修复装置通过所述控制器与所述存储裸片相连；或者，
所述存储装置为存储芯片，所述修复装置为主芯片；或者，
所述存储装置为存储芯片，所述修复装置位于包含控制器的主芯片上，且所述修复装置通过所述控制器与所述存储芯片相连。
在一种可能的实现方式中，所述存储器还包括：一次性可编程存储器efuse。
作为一种示例，处理器可以包括：DRAM控制器。
第十方面，提供了一种存储装置，包括：接口，处理器和存储器；
其中，所述接口用于连接修复装置和总线；所述存储器，用于存储指令和数据；所述处理器用于执行指令以实现第二方面或者第三方面中任一方面或者任意可能的实现方式中的方法。
作为一种示例，处理器可以包括：行地址译码器。
在一种可能的实现方式中，每个存储单元包括至少一个数据行，每个冗余单元包括至少一个冗余行。
第十一方面，提供了一种存储芯片，包括：
逻辑裸片和至少一个存储裸片；其中，逻辑裸片包括修复装置和控制器，所述修复装置通过所述控制器与所述存储裸片通信；
所述逻辑裸片用于执行第一方面或者第四方面中任一方面或者任意可能的实现方式中的方法；
所述存储裸片用于执行第二方面或者第三方面中任一方面或者任意可能的实现方式中的方法。
第十二方面，提供了一种存储芯片，包括：
逻辑裸片和至少一个存储裸片；其中，
所述逻辑裸片用于执行第一方面中任意可能的实现方式中的方法，所述存储裸片用于执行第二方面中任意可能的实现方式中的方法；或者，
所述逻辑裸片用于执行第四方面中任意可能的实现方式中的方法，所述存储裸片用于执行第三方面中任意可能的实现方式中的方法。
又一方面，提供一种装置，该装置包括处理模块和收发模块，处理单元执行指令以控制该装置执行第一方面或第一方面任意一种可能的设计中的方法。
在一种可能的实现方式中，该装置还可以包括存储模块。
在一种可能的实现方式中，该装置可以是存储芯片。
作为一种示例，处理模块可以是处理器，收发模块可以是收发器；若还包括存储模块，存储模块可以是存储器。
作为另一种示例，当该装置是存储芯片时，处理模块可以是处理器，收发模块可以是输入/输出接口、管脚或电路等；若还包括存储模块，该存储模块可以是该芯片内的存储模块(例如，寄存器、缓存等)，也可以是该芯片外部的存储模块(例如，只读存储器、随机存取存储器等)。
其中，上述任一处提到的处理器，可以是一个通用中央处理器(Central Processing Unit，简称CPU)，微处理器，特定应用集成电路(application-specific integrated circuit，简称ASIC)，或一个或多个用于控制上述各方面空间复用方法的程序执行的集成电路。
又一方面，提供了一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，所述指令可以由处理电路上的一个或多个处理器执行。当其在计算机上运行时，使得计算机执行上述第一方面或其任意可能的实现方式中的方法。
又一方面，提供了一种包含指令的计算机程序产品，其在计算机上运行时，使得计算机执行上述第一方面或其任意可能的实现方式中的方法。
附图说明
为了更清楚地说明本申请或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例中存储芯片一种结构示意图；
图2为本申请实施例中存储芯片中的裸片的分层结构示意图；
图3为本申请实施例中存储芯片的逻辑结构的一种示意图；
图4为本申请实施例提供的存储单元的访问方法的交互流程示意图一；
图5为本申请实施例提供的存储单元的修复方法的一种交互流程示意图；
图6为本申请实施例提供的存储单元的访问方法应用于DRAM时的系统架构及处理过程的示意图；
图7为本申请实施例提供的修复装置的结构示意图一；
图8为本申请实施例提供的存储装置的结构示意图一；
图9为本申请实施例提供的修复装置的结构示意图二；
图10为本申请实施例提供的存储装置的结构示意图二。
具体实施方式
本申请的实施方式部分使用的术语仅用于对本申请的具体实施例进行解释，而非旨在限定本申请。
实施例一
本申请实施例提供存储单元访问方法、修复方法及相关技术方案。
本申请实施例提供的各个方法可应用于具有存储功能的芯片中。在本申请实施例中，具有存储功能的芯片可以称为为存储芯片。举例来说，存储芯片可以为动态随机存取存储器(dynamic random access memory，DRAM)、静态随机存取存储器(Static Random-Access Memory，SRAM)、非易失存储器(Non-Volatile Memory，NVM)等。
在本申请实施例中，存储芯片可以由一个或多个裸片(die)组成。在存储芯片出厂前，存储芯片的生产厂商需要对组成芯片的裸片进行质量检测，在检测后，对组成该芯片的多个裸片进行封装，得到存储芯片。
图1为本申请实施例中存储芯片一种结构示意图。
如图1所示，存储芯片10可以包括一个逻辑裸片(logic die)100和至少一个存储裸片(store die)200。其中，每个存储裸片上可以部署有一个或多个存储颗粒。作为一种示例，每个存储裸片上部署的存储颗粒可以被划分为一个或多个块(bank)，每个bank可以划分为一个或多个扇区(sector)。每个sector可以划分为多个行(row)。每个存储裸片上还可以部署有地址译码器，如行地址译码器，也可以称为行译码器。作为一种示例，在封装以后，存储芯片还可以包括外封装层。
图2为本申请实施例中存储芯片中的裸片的分层结构示意图。
如图2所示，在本申请实施例中，存储芯片中的逻辑裸片和存储裸片可采用3D堆叠方式分层设置，其中，逻辑裸片位于底层，存储裸片位于逻辑裸片之上，存储裸片在逻辑裸片所在平面的投影与逻辑裸片可以占用相同的面积，当有多个存储裸片时，多个存储裸片也采用分层设置，每个存储裸片在逻辑裸片所在平面的投影占用的面积可以相同。在一示例中，一个存储芯片可以包括一个逻辑裸片和4的整数倍个存储裸片。在本申请实施例中，逻辑裸片也可以称为底膜，或者，基层裸片(base die)。
图3为本申请实施例中存储芯片的逻辑结构的一种示意图。
在本申请实施例中，如图3所示，作为一种示例，逻辑裸片100可以包括：修复装置1001和控制器1002。在一示例中，逻辑裸片还可以包括与系统总线进行通信的对外接口，以及与各个存储裸片进行通信的对内接口。
需要说明的是，在本申请其他实施例中，作为一种示例，存储芯片也可以通过主芯片与系统总线通信，其中，主芯片可以设置修复装置和控制器，控制器可以通过存储芯片中的逻辑裸片访问存储芯片上的各个存储裸片中的存储单元，且主芯片中的修复装置和控制器可以执行与图3所示结构中的修复装置和控制器类似的方法，这种设置方式中存储芯片的逻辑裸片中可以不设置控制器和修复装置。
下面对本申请提供的技术方案进行示例性说明。
在本申请实施例中，随着半导体技术的不断发展，芯片规模越来越大，工作频率越来越高，例如DRAM就是一种大容量高密度的半导体存储器。但是，芯片在生产过程和工作状态时都存在局部失效概率，导致芯片良率下降。
为此，可以在存储芯片的存储裸片中部署冗余行，用于替换失效的数据行，在本申请实施例中，基于冗余行的修复技术可以称为行冗余(Row Redundancy)技术。
在本申请实施例中，存储裸片可以包括：至少一个存储单元和至少一个冗余单元。
举例来说，存储裸片可以在自身部署的颗粒上划分多个行，每行包括一个或多个最小单元。存储裸片可以将自身颗粒上划分出的多个行划分为至少一个数据存储区和至少一个冗余区，并为各个数据存储区配置原始地址区段，以及为各个冗余区配置冗余地址区段，其中，各个原始地址区段与各个冗余地址区段均互不重叠。
作为一种示例，每个数据存储区可以包括至少一个存储单元，每个存储单元可以包括1个数据行或者多个数据行，每个存储单元的原始地址属于存储单元所属的数据存储区对应的原始地址区段；每个冗余区可以包括至少一个冗余单元，每个冗余单元可以包括1个冗余行或者多个冗余行，每个冗余区的冗余单元的冗余地址属于冗余单元所属冗余区对应的冗余地址区段。在一示例中，每个冗余单元中包含的行的数量可以与每个存储单元中包含的行的数量相同。
当数据存储区中的存储单元发生故障失效时，发生故障的存储单元可以称为失效单元，存储芯片采用位于冗余区的冗余单元替代失效单元来完成数据存取操作，以提高芯片良率。
在本申请实施例，存储裸片上可以部署M个数据存储区和N个冗余区。其中，M和N为正整数，在一示例中，M≥N。M个数据存储区和N个冗余区的对应关系可以灵活配置。
在一示例中，一个数据存储区可以对应一个冗余区，基于此，冗余区中的冗余单元可以仅用于替代所属冗余区对应的数据存储区中的失效单元。在又一示例中，多个数据存储区可以对应一个冗余区，基于此，冗余区中的冗余单元可以用于替代多个数据存储区中的失效单元，也即多个数据存储区中的存储单元可以共享一个冗余区中的冗余单元。
在实际应用中，存储裸片可以包括多个块(bank)，每个块可以包括多个扇区(sector)。作为一种示例，每个bank可以设置一个数据存储区和一个冗余区。作为一种示例，每个bank可以设置一个数据存储区，多个bank可以设置一个冗余区。作为一种示例，每个sector可以设置一个数据存储区和一个冗余区。作为一种示例，每个sector可以设置一个数据存储区，多个sector可以设置一个冗余区。作为一种示例，每个存储单元可以包含至少一个数据行，每个冗余单元中包含的冗余行的数量可以与每个存储单元中包含的数据行的数量相同。
作为一种示例，以每个sector设置一个数据存储区和一个冗余区为例，每个Sector中位于数据存储区中的行的数量与位于冗余区的冗余行的数量的比例可以约定比例，例如为2K：16。作为另一种示例，每个存储裸片包含多个bank，其中，一部分bank中的每个sector可以部署冗余区，另一部分bank中的每个sector可以不部署冗余区。作为再一种示例，一个bank可以包含多个sector，其中，一部分sector可以部署冗余区，另一部分sector可以不部署冗余区。本申请实施例并不以此为限。
基于上面的系统架构，下面对本申请实施例提供的基于冗余单元的数据访问方法进行说明。
图4为本申请实施例提供的存储单元的访问方法的交互流程示意图一。
如图4所示，本申请实施例的执行主体可以包括：修复装置和存储装置。
其中，作为一种示例，存储装置可以为包括至少一个存储单元和至少一个冗余单元的存储裸片。修复装置可以位于包含控制器的逻辑裸片上，修复装置可以通过控制器与存储裸片通信。
S101，修复装置从总线接收包含访问地址的访问请求；所述访问地址包括存储装置中的至少一个存储单元的原始地址。
在本申请实施例中，修复装置可以通过外部接口从IO总线上接收访问请求。访问请求可以为读指令或写指令等。作为一种示例，读指令可以包含请求读取的存储单元的存储地址。作为另一种示例，写指令可以包含请求待写入的数据，以及，该数据的目标地址，即待存入数据的存储单元的存储地址。在本申请实施例中，访问请求还可以为刷新请求。作为一种可选的实施方式，在本申请实施例中，访问请求可以为包含数据的存储地址的任一数据处理请求。
在本申请实施例中，在向存储装置中的至少一个存储单元中写入数据之前，存储装置可以为存储装置中的所有存储单元配置原始地址区段，以及，为存储装置中的所有冗余单元配置冗余地址区段。作为一种示例，存储裸片包括至少一个数据存储区和至少一个冗余区，每个数据存储区包括至少一个存储单元，每个存储单元的原始地址属于原始地址区段；每个冗余区包括至少一个冗余单元，每个冗余单元的冗余地址属于冗余地址区段。存储芯片对外只呈现原始地址区段，即访问请求中包含的地址为存储单元的原始地址。
在本申请实施例中，需要说明的是，以存储芯片为DRAM芯片为例，访问地址可以为逻辑块地址(Logical Block Address，LBA)，也称为逻辑块地址。作为一种示例，原始地址区段为LBA001至LBA399，冗余地址区域可以为LBA400至LBA420。
S102，修复装置根据全局修复信息，识别所述访问地址指向的存储单元中是否存在失效单元；其中，所述全局修复信息包含所述存储装置中存在的至少一个失效单元的原始地址与用于替换所述至少一个失效单元中每个失效单元的冗余单元的冗余地址。
作为一种示例，修复装置可以根据全局修复信息，识别所述访问地址是否包含失效单元的原始地址。
在本申请实施例中，全局修复信息可以存储于修复装置上，修复装置可以在芯片工作的过程中不断更新全局修复信息。例如，修复装置可以在进行读写数据、刷新数据、检测维护等处理过程中，获悉存储装置检测到的失效单元的信息，并未其分配冗余单元，并在全局修复信息中添加新检测到的失效单元和对应的冗余单元的对应关系。作为一种示例，全局修复信息可以包含存储装置中已检测到的所有失效单元的原始地址与用于替换各个失效单元的冗余单元的冗余地址。
在本申请实施例中，修复装置上若部署有efuse，则在测试阶段，修复装置还可以将测试阶段由存储装置检测到失效单元的原始地址以及修复装置为各个失效单元分配的冗余单元的冗余地址的对应关系信息存储至efuse，之后，在存储芯片每次上电工作时，可以修复装置可以从efuse中读取测试阶段记录的修复信息作为初始的全局修复信息。
在本申请其他实施例中，将对修复装置获取和更新全局修复信息的实施方式进行 详细说明。
S103，在识别到访问地址指向的存储单元中存在第一失效单元时，修复装置将访问地址中指向第一失效单元的原始地址替换为第一失效单元对应的第一冗余单元的冗余地址。
作为一种示例，在识别到访问地址中包含指向第一失效单元的原始地址时，确定访问地址指向的存储单元中存在第一失效单元，将访问地址中指向第一失效单元的原始地址替换为第一失效单元对应的第一冗余单元的冗余地址。第一失效单元为任一失效单元。
在一示例中，访问地址中包含第一原始地址，逻辑裸片查询全局信息表确定第一原始地址指向的第一存储单元已经失效，已经失效的第一存储单元即为第一失效单元，进一步查询全局信息表，获得第一原始地址对应的第一冗余地址，其中，第一冗余地址指向的第一冗余单元用于替代第一原始地址指向的第一失效单元。
作为一种示例，访问地址可以包含地址区间LBA001至LBA010，假设LBA002和LBA004为全局修复信息中记录的失效单元的原始地址，若原始地址为LBA002的存储单元对应的冗余单元的冗余地址为LBA500，原始地址为LBA004的存储单元对应的冗余单元的冗余地址为LBA501，则可以替换后的访问地址可以为LBA001，LBA500，LBA003，LBA501，LBA005至LBA010。
S104，修复装置将替换后的访问请求发送至存储装置。
其中，在一示例中，所述替换后的访问请求包含第一冗余单元对应的第一冗余地址。
作为一种示例，存储装置为存储裸片，位于逻辑裸片上的修复装置可以通过逻辑裸片上的控制器将替换后的访问请求发送至存储裸片。
S105，存储装置基于冗余地址指向的冗余单元完成访问处理。
其中，存储装置可以访问冗余地址。在一示例中，当访问请求为写指令，访问请求还包括待写入的数据，存储装置可以将待写入的数据写入冗余地址指向的冗余单元，之后，存储装置可以生成访问响应，其中包含存储待写入的数据的冗余单元的冗余地址。在又一示例中，当访问请求为读指令，存储装置可以读取冗余地址指向的冗余单元中存储的数据，其中包括从冗余地址指向的冗余单元中读取到的数据。
S106，存储装置向修复装置发送访问响应，所述访问响应包含所述第一冗余单元的冗余地址。
其中，在一示例中，在访问请求为写指令时，访问响应中包含存储待写入的数据的冗余单元的冗余地址。在又一示例中，在访问请求为读指令时，访问响应中包含从冗余地址指向的冗余单元中读取到的数据。
作为一种示例，存储装置为存储裸片，位于逻辑裸片上的修复装置可以通过逻辑裸片上的控制器接收存储装置发送的访问响应。
S107，修复装置根据全局修复信息，获取所述第一冗余单元的冗余地址对应的第一失效单元的原始地址，将所述访问响应中指向所述第一冗余单元的冗余地址替换为所述第一失效单元的原始地址。
作为一种示例，访问响应可以包含由LBA001，LBA500，LBA003，LBA501， LBA005至LBA010组成的地址区间，假设LBA500和LBA501为全局修复信息中记录的冗余单元的冗余地址，若冗余地址为LBA500的存储单元对应的存储单元的原始地址为LBA002，冗余地址为LBA501的冗余单元对应的失效单元的原始地址为LBA004，则可以替换后的访问地址可以为LBA001至LBA010。
作为一种示例，全局修复信息可以支持利用失效单元的原始地址查询对应的冗余单元的冗余地址，也可以支持利用冗余单元的冗余地址反向查询对应的失效单元的原始地址。作为另一种示例，修复装置可以将全局修复信息分别存储为冗余地址映射信息和原始地址反向映射信息，修复装置可以在接收到访问请求时，根据冗余地址映射信息查询存储单元的原始地址对应的冗余单元的冗余地址，修复装置还可以在接收到访问响应时，根据冗余单元的冗余地址查询对应的存储单元的原始地址。
S108，修复装置将替换后的所述访问响应发送至总线。
在本申请实施例中，修复装置和存储装置相配合，实现了基于冗余单元完成数据访问的过程。
采用本申请实施例提供的方法，通过修复装置根据全局修复信息实现冗余替换修复，可以将冗余替换修复的控制功能设置在工艺更先进的逻辑裸片上实现，存储裸片中不需要设置支持切换行选信号的电路，其中，切换行选信号的电路用于将指向正常的数据存储区的失效行的行选信号直接转接至冗余区中用于替换失效行的冗余行的行标信号的电路。基于此，存储裸片上的电路结构得到了极大的简化。进一步地，本申请实施例提供的技术方案，能够在不降低存储容量的前提下，通过简化存储裸片中非必要的电路，减少存储裸片占用的平铺区域的面积，当存储裸片和逻辑裸片采用分层设置方式时，由于每个存储裸片占用的平铺区域都得以减少，因而能够使得最终的存储芯片产品占用的平铺区域的面积大幅缩小，即以较小的裸片面积实现冗余替换功能，节省存储裸片面积，使得产品更加小型化。
此外，在本申请实施例中，每个冗余单元可以为sector中的1行。相比于采用切换行选信号的电路时，由于电路逻辑的复杂度不能太高，只能采用多行组合作为最小替换单元，在本申请实施例的方法中，冗余替换功能以1行为最小替换单元，能够实现更细粒度的冗余资源的规划和利用，灵活且全面地修复各个扇区中的失效单元。例如，当一个sector中存在3个失效行，且这3个失效行之间的间隔超过8行时，若最小替换单元为8时，16个冗余行资源实际只能修复2个失效行，则该sector无法被修复，当采用本申请实施例提供的方法时，最小替换单元为1行时，16个冗余行资源可以修复这3个失效行，使得该扇区得以修复使用。
实施例二
本申请实施例还提供一组存储单元的修复方法相关的技术方案，本申请实施例提供的修复方法可在执行上述实施例中的存储单元的访问方法之前执行。修复装置可以通过本申请实施例提供的存储单元的修复方法获取或者更新全局修复信息。
在本申请实施例中，修复装置可以通过以下方式更新全局修复信息。如图4所示，本申请实施例还可以包括：
S201，存储装置检测存储装置中的存储单元中是否存在失效单元。
其中，作为一种示例，存储装置可以为存储裸片。存储裸片可以是在执行读数据指令、写数据指令、刷新指令等指令时检测到失效单元的。本申请实施例对此不做限制。
作为一种示例，存储装置检测到的失效单元可以为第二失效单元，其中，第二失效单元可以是前述实施例中的第一失效单元也可以是其他的失效单元。
S202，存储装置向修复装置发送检测到的失效单元的原始地址。
作为一种示例，存储装置为存储裸片，修复装置位于包含控制器的逻辑裸片时，存储装置可以通过控制器向修复装置发送失效单元的原始。作为一种示例，存储装置可以在存在失效单元时，向修复装置发送所述失效单元的原始地址。
作为一种示例，检测到失效单元的原始地址可以记为第二失效单元的原始地址。
S203，修复装置分配用于替代检测到的失效单元的冗余单元。
在本申请实施例中，修复装置分配失效单元对应的冗余单元的分配方法有多种实施方式，能够实现复杂灵活的冗余替换功能。作为一种示例，用于替代第二失效单元的冗余单元可以为第二冗余单元。
在本申请实施例中，存储装置可以包括至少一个数据存储区和至少一个冗余区。其中，每个数据存储区包含至少一个存储单元，每个冗余区包含至少一个冗余单元，存储装置可以为属于各个数据存储区的存储单元分配原始地址区段，以及，为属于各个冗余区的冗余单元分配冗余地址区段。其中，任一冗余地址区段与任一原始地址区段的地址不重叠。作为一种示例，存储装置可以包含M个数据存储区和N个冗余区，其中，M和N为正整数。作为一种示例，M可以大于或者等于N。
在一种可选的分配方式中，可以基于就近原则分配冗余单元。
作为一种示例，存储装置可以设置X个功能区，其中，每个功能区可以包括1个数据存储区，X个功能区中的至少一个功能区中的冗余区的数量不为零。示例性地，修复装置分配冗余单元时，可以优先为失效单元分配属于同一功能区的冗余单元，若属于同一功能区的冗余单元已分配完，则可以选择其他功能区的冗余单元。在一示例中，功能区可以为一个扇区或者一个块。
作为另一种示例，存储装置还可以设置高层功能区和低层功能区，其中，每个高层功能区包括至少一个低层功能区，每个低层功能区包括至少一个数据存储区，所有低层功能区中至少一个低层功能区的冗余区的数量不为零。例如，高层功能区可以为块，低层功能区可以为扇区。每个块可以包括至少一个扇区。
举例来说，在分配冗余单元的实际过程中，存储装置可以包括块0和块1，块0包括扇区0(记为S01)和扇区1(记为S02)，块1包括扇区0(记为S11)。存储装置可以在S01、S02、S11、S12四个扇区中至少一个扇区上设置冗余区。在一示例中，存储装置可以包括位于S01的第一存储单元和位于S01的第一冗余单元，在又一示例中，存储装置可以包括位于S01的第一存储单元和位于S02的第一冗余单元，在再一示例中，存储装置可以包括位于S01的第一存储单元和位于S11的第一冗余单元。
修复装置可以优先选择同一低层功能区对应的冗余区中的冗余单元作为第一冗余单元；如果同一低层功能区对应的冗余区中的冗余单元已被分配完，则可以在同一高层功能区中，选择最邻近的低层功能区中的冗余区中的冗余单元；如果最邻近的低 层功能区对应的冗余区中的冗余单元已被分配完，则可以同一高层功能区中的其他低层功能区的冗余区中的冗余单元；如果同一高层功能区中冗余区中的冗余单元已被分配完，则可以选择其他高层功能区中的冗余区中的冗余单元。
以每个sector设置一个数据存储区和1个冗余区为例，首先，如果第一失效单元为第一数据存储区的存储单元，优先选择与第一数据存储区属于相同sector的冗余区中的冗余单元作为第一失效单元对应的第一冗余单元。其次，如果属于相同sector的冗余区中的冗余单元已分配完，则选择与第一数据存储区属于相同bank的最邻近的sector中的冗余区中的冗余单元作为所述第一失效单元对应的第一冗余单元。再次，如果位于同一bank的冗余区的冗余单元已分配完，则选择与第一数据存储区所述bank最邻近的bank中的冗余区中的冗余单元作为第一失效单元对应的第一冗余单元。最后，若所述存储裸片上的所有bank中的冗余区中的冗余单元已全部被分配，选择与所述存储裸片最邻近的存储裸片中的冗余区中的冗余单元作为第一失效单元对应的第一冗余单元。也就是说，在一种可能的分配方式中，第一失效单元与第一冗余单元可以位于同一sector，或者，或者，第一失效单元与第一冗余单元可以位于同一bank的不同sector中，或者，第一失效单元与第一冗余单元可以位于同一存储裸片的不同bank中。
采用上述分配方式，存储装置上全部的冗余资源都在修复装置上进行控制集中，本申请实施例实际上能够实现全局冗余资源的跨扇区/跨块共享，有效提高冗余资源利用率，从而提高芯片良率。对于各个扇区或者各个块非均匀失效场景下能够对各个扇区和各个块的失效单元进行修复。例如，在一个扇区的失效单元的行数超过该扇区中配置的冗余单元的行数时，可以通过调度其他扇区中空闲的冗余单元进行全面的修复，避免出现在整个存储裸片上有空闲冗余单元时仍无法修复某一扇区中集中出现大量失效单元的情况。
S204，修复装置将检测到失效单元的原始地址和分配的冗余单元的冗余地址添加到全局修复信息。
其中，全局修复信息可以包含一组或多组失效单元和冗余单元的对应关系。
需要说明的是，步骤S201至S204也可以在步骤S101之后执行。
采用这种修复方式，存储装置在检测到失效单元时，可以通知修复装置分配对应的冗余单元，由此可以在执行读写指令、刷新指令等能够触发失效单元检测的过程中，动态更新全局修复信息。在执行存储单元的访问方法时，就可以对冗余单元进行读写操作，避免使用失效单元，从而能够提高存储芯片的存取速度。
图5为本申请实施例提供的存储单元的修复方法的一种交互流程图示意。
在本申请实施例中，修复装置还可以采用以下方式获取全局修复信息。
在本申请实施例中，修复装置或者修复装置所在的逻辑裸片中还可以部署有一次性可编程存储器(efuse)，在芯片出厂前的测试阶段，可以将检测到的失效单元以及分配好的替换单元的对应信息，即测试阶段记录的修复信息存入efuse之中。在存储芯片出厂后，每次上电工作时，修复装置可以从efuse中读取测试阶段写入的修复信息作为初始的全局修复信息，并结合图4中的方法不断更新全局修复信息。
如图5所示，本申请实施例的步骤还可以包括：
S301，修复装置向存储装置发送失效检测指示。
其中，该失效检测指示可以是从IO总线上获取的测试指令，例如，可以是写指令或者读指令或者刷新指令，其中，携带访问地址为存储裸片上的所有行对应的原始地址。作为一种示例，当存储装置为存储裸片，修复装置位于包括控制器的逻辑裸片上时，修复装置可通过控制器向存储装置发送各种消息。
S302，存储装置检测存储单元中是否存在失效单元。
其中，作为一种示例，存在装置在封装前检测到的失效单元可以为第三失效单元，第三失效单元可以为前述实施例中的第一失效单元，也可以是其他的失效单元。
S303，存储装置向修复装置发送检测到的失效单元的原始地址。
S304，修复装置分配用于替代失效单元的冗余单元。
作为一种示例，用于替代第三失效单元的冗余单元可以记为第三冗余单元。
其中，步骤S302-S304与S201-S203的实施过程相似，可参看S201-S203中的相关说明。
S305，修复装置将所有失效单元的原始地址与对应的冗余单元的冗余地址写入efuse。
其中，在测试阶段记录的所有失效单元的原始地址和对应的冗余单元的冗余地址可以称为测试修复信息。作为一种示例，修复装置将在封装前检测到的所有失效单元的原始地址和每个失效单元对应的冗余单元的冗余地址一次性写入efuse。
S306，在上电时，修复装置读取efuse中存储的所有失效单元的原始地址与对应的冗余单元的冗余地址，将其作为初始的全局修复信息。
采用这种方式时，在测试阶段已经检测出的失效单元和分配的冗余单元的对应关系被写入efuse中，基于efuse只能写入一次且下电后存储于efuse的数据不会丢失这一特性，在存储芯片出厂之后，修复装置每次上电都可以直接获取到这部分修复信息，避免了在每次上电后进行重复检测，从而能够减少执行重复的检测工作和修复工作时存储裸片的能耗，提高存储芯片的存取效率。
在本申请实施例中，上述两种修复方法可以分别在存储芯片处于工作状态时和在存储芯片处于测试阶段时进行存储单元的修复工作，存储芯片可以同时支持执行上述两种修复方法。
需要说明的是，当一个逻辑裸片与多个存储裸片相连时，可以将每个存储裸片中在测试阶段检测出的失效单元和分配的冗余单元的对应关系一次性写入efuse中。
下面采用具体的例子对本申请实施例提供的方法进行详细说明。
图6为本申请实施例提供的存储单元的访问方法应用于DRAM时的系统架构及处理流程的示意图。
如图6所示，本申请实施例中的存储芯片可以包括：逻辑裸片610和DRAM裸片(DRAM die)620。
其中，逻辑裸片可以包括：DRAM控制器(DRAM controller)601、冗余行地址映射(Redundent Row Address Mapping)模块603、全局修复信息(Repair info)管理 模块604、原始地址反向映射(Original Row Address Reverse Mapping)模块605。其中，模块603至605可以组成修复装置602。DRAM裸片620可以包括：行译码器(Row Decoder)606和部署为块和扇区的存储阵列(图6中行译码器右侧部分)。行译码器也称为行地址译码器或者行地址译码模块。
需要说明的是，在本申请实施例提供一种全局化细粒度的DRAM行冗余修复方案中，一方面，用于失效修复的冗余存储资源可以均匀分布在DRAM Die上的各个Sector或Bank，例如，每2K行可以配16个冗余行(如图6中灰色块所示)；另一方面，利用冗余行对失效行进行替换修复的控制在逻辑裸片上实现，在DRAM裸片不再需要设置替换修复相关的逻辑。
以存储单元为1个数据行，冗余单元为1个冗余行为例进行示例性说明，其中，每个行可以记为1WLs)。
如图6所示，本申请实施例的步骤可以包括：芯片测试过程中的步骤和芯片正常使用阶段的步骤两部分。其中，在芯片测试阶段的步骤可以包括：
步骤1，DRAM裸片如果在正常的数据存储区发现有失效单元，则按分配策略确定使用哪个冗余行进行替换，例如就近原则，可以优先选择位于相同sector的失效单元或者优先选择位于相同bank的失效单元。存储芯片所有的修复信息集中烧写在逻辑裸片上，需要通过烧写efuse记录在全局修复信息管理模块中。在正常使用的场景中，当芯片上电时，全局修复信息管理模块从efuse中读出测试阶段记录的修复信息并转写入冗余行地址映射模块和原始行地址反向映射模块。
在本申请实施例中，逻辑裸片上的全局修复信息管理模块主要由efuse资源组成，用于记录芯片全局的冗余行修复信息。失效修复信息可以按冗余行为单位，记录需要替换的目标失效行，同时还需要考虑容错及补记录等机制。全局修复信息管理模块也可以称为efuse模块。
步骤2，在正常使用的场景中，当用户对芯片发起读写访问时，读写指令首先会进入冗余行地址映射模块处理，冗余行地址映射模块在原始访问地址中识别出失效的行地址，并按确定的替换策略将原始的失效行地址替换为冗余行地址。
在本申请实施例中，冗余行地址映射模块中使用内容寻址存储器(Content Addressable Memory，CAM)以冗余行地址组成失效行地址映射表。每次访问指令中的行地址都进行CAM查找，匹配中的失效行地址将使用对应的CAM地址(即冗余行地址)替换。CAM除了在上电时通过efuse加载冗余修复信息，也可以在使用过程中根据需要添加。作为一种示例，替换策略可以为就近原则，均衡原则等，例如，优先选择同一bank中使用率最低的sector中的冗余区的冗余单元。
步骤3，失效行地址被冗余行地址替换后的访问指令将正常进入控制器处理。控制器按DRAM时序发送相应指令给DRAM裸片。
步骤4，DRAM裸片上的行地址译码模块将接收的行地址，译码为行选信号，其中冗余行也有会统一编址，冗余行的编址可以在正常数据行的地址范围之外)。对于已经替换为冗余行地址的指令，则直接译码为冗余行的行选信号。此时，所有访问操作实际上是对冗余行中的最小单元的操作，例如，每个存储单元可以包括至少一行和至少一列的最小单元，以存储单元包括1行和为例，列地址。
步骤5，控制器对DRAM裸片的操作完成后，将返回相应的读写响应及读数据。对于冗余行的读写操作，控制器将正常返回相应的冗余行地址信息给原始地址反向映射模块。
步骤6，原始地址反向映射模块会检查出冗余行地址，并查找一个原始行地址反向映射表，将读写响应中的冗余行地址转换为原始行地址之后，将读写响应及读数据返回给用户侧。用户对失效地址的冗余替换操作并不感知。
作为一种示例，前述实施例中的原始行地址反向映射表可以为全局信息表。
在本申请实施例中，原始地址反向映射模块可以使用SRAM以冗余行地址组成原始行地址反向映射表。SRAM中记录每个失效单元的地址。当识别到控制器返回的读写响应中的行地址为冗余行地址时(在正常数据存储地址范围之上)，以冗余行地址在SRAM中查找对应的原始地址，并进行反向替换。
在本申请实施例中，全局修复信息管理模块、冗余行地址映射模块和原始行地址反向映射模块与其他模块配合，可以支持整芯片全局化的冗余替换修复，并支持单行的细粒度替换修复。
实施例三
本申请实施例还提供一种修复装置。
图7为本申请实施例提供的修复装置的结构示意图一。如图7所示，本申请实施例中的修复装置可以包括：收发模块801、处理模块802；其中，收发模块用于与总线和存储装置通信。在一种可选的实施方式中，修复装置还可以包括存储模块803。
在修复装置的第一种可选的实施方式中：
收发模块，用于接收包含访问地址的访问请求；所述访问地址包括存储装置中的至少一个存储单元的原始地址。处理模块，用于根据全局修复信息，识别所述访问地址指向的存储单元中是否存在失效单元；其中，所述全局修复信息包含所述存储装置中存在的至少一个失效单元的原始地址与用于替代所述至少一个失效单元中的每个失效单元的冗余单元的冗余地址；在识别到所述访问地址指向的存储单元中存在第一失效单元时，将所述访问地址中指向所述第一失效单元的原始地址替换为所述第一失效单元对应的第一冗余单元的冗余地址。所述收发模块还用于将替换后的访问请求发送至所述存储装置。
在一种可能的实现方式中，所述收发模块还用于在所述接收包含访问地址的访问请求之前，接收所述存储装置发送的所述存储装置中存在的第二失效单元的原始地址；所述处理模块用于，分配用于替代第二失效单元的第二冗余单元；以及，用于将所述第二失效单元的原始地址和第二冗余单元的冗余地址的对应关系添加到所述全局修复信息，其中，第二失效单元和第一失效单元相同或不同。
在一种可能的实现方式中，所述修复装置包括一次性可编程存储器efuse；所述收发模块还用于在所述接收包含访问地址的访问请求之前，接收所述存储装置发送的所述存储装置中在封装前存在的第三失效单元的原始地址；所述处理模块还用于分配用于替代在封装前存在的第三失效单元的第三冗余单元；以及用于，将所述在封装前存在的第三失效单元的原始地址和第三冗余单元的冗余地址的对应关系存储在所述 efuse中；以及用于，在所述修复装置每次上电后，将从所述efuse中读取到的所述存储装置中存在的第三失效单元的原始地址和第三冗余单元的冗余地址的对应关系，添加到所述全局修复信息；其中，第三失效单元和第一失效单元相同或不同。
在一种可能的实现方式中，收发模块还用于接收所述存储装置发送的包含所述第一冗余单元的冗余地址的访问响应；处理模块还用于根据全局修复信息，获取所述第一冗余单元对应的所述第一失效单元的原始地址；将所述第一失效单元的原始地址添加到所述访问响应中；所述收发模块还用于将包含所述第一失效单元的原始地址的所述访问响应发送至总线。
在修复装置的第二种可选的实施方式中：
收发模块，用于接收存储装置发送的存储装置的至少一个存储单元中存在的失效单元的原始地址。处理模块，用于分配用于替换所述失效单元的冗余单元；以及用于，将所述失效单元的原始地址与所述冗余单元的冗余地址添加到全局修复信息。
在一种可能的实现方式中，所述修复装置包括一次性可编程存储器efuse；
收发模块，具体用于接收所述存储装置发送的所述存储装置中在封装前存在的至少一个失效单元的原始地址；处理模块，具体用于分配用于替代在封装前存在的各个失效单元的冗余单元；以及具体用于将所述在封装前存在的各个失效单元的原始地址和各个失效单元对应的冗余单元的冗余地址的对应关系存储在所述efuse中；在所述修复装置每次上电后，将从所述efuse中读取到的所述存储装置中存在的至少一个失效单元的原始地址和各个失效单元对应的冗余单元的冗余地址的对应关系，添加到所述全局修复信息。
本申请实施例的其他技术方案细节和技术效果可参看本申请其他实施例中的描述。
本申请实施例还提供一种存储装置。
图8为本申请实施例提供的存储装置的结构示意图一。如图8所示，本申请实施例中的存储装置可以包括：收发模块901、处理模块902；其中，收发模块用于与总线和存储装置通信。在一种可选的实施方式中，存储装置还可以包括存储模块903。
在存储装置的第一种可选的实施方式中：
收发模块，用于接收修复装置发送的包含访问地址的访问请求，其中，所述访问地址包括所述存储装置中的冗余单元的冗余地址；其中，所述冗余单元用于替代所述至少一个存储单元中的失效单元；处理模块，用于访问所述冗余地址；收发模块，还用于向所述修复装置发送访问响应。
在一种可能的实现方式中，处理模块还用于在所述接收修复装置发送的包含访问地址的访问请求之前，检测所述存储装置中的存储单元中是否存在失效单元；收发模块还用于，在所述存储装置中的存储单元中存在失效单元时，向所述修复装置发送所述失效单元的原始地址，以使所述修复装置分配用于替代所述失效单元的所述冗余单元，并将所述失效单元的原始地址和所述冗余单元的冗余地址之间的对应关系加入全局修复信息。
在存储装置的第二种实施方式中：
处理模块，用于检测存储装置中是否存在失效单元。收发模块，用于在所述存储 装置中的存储单元中存在失效单元时，向修复装置发送所述失效单元的原始地址。
在一种可能的实现方式中，处理模块具体用于在所述存储装置封装前，检测所述存储装置中的存储单元中是否存在失效单元；收发模块，具体用于在所述存储装置中的存储单元中存在失效单元时，向所述修复装置发送所述失效单元的原始地址。
本申请实施例的其他技术方案细节和技术效果可参看本申请其他实施例中的描述。
图9为本申请实施例提供的修复装置的结构示意图一；如图9所示，本申请实施例中的修复装置可以包括：接口1110、处理器1120、存储器1120；其中，所述接口用于连接存储装置；所述存储器，用于存储指令；所述处理器，用于执行指令以实现前述实施例中的方法。修复装置还可以包括用于内部互连的总线1160。
在一种可能的实现方式中，所述存储装置为存储裸片，所述修复装置为逻辑裸片；或者，所述存储装置为存储裸片，所述修复装置位于包含控制器的逻辑裸片上，且所述修复装置通过所述控制器与所述存储裸片相连；或者，所述存储装置为存储芯片，所述修复装置为主芯片；或者，所述存储装置为存储芯片，所述修复装置位于包含控制器的主芯片上，且所述修复装置通过所述控制器与所述存储芯片相连。
在一种可能的实现方式中，所述存储器还包括：一次性可编程存储器efuse。
作为一种示例，存储裸片可以为DRAM裸片，控制器可以为DRAM控制器。
图10为本申请实施例提供的存储装置的结构示意图一；如图10所示，本申请实施例中的存储装置可以包括：接口1210、处理器1220、存储器1230；其中，所述接口用于连接修复装置；所述存储器，用于存储指令；所述处理器，用于执行指令以实现前述实施例中的方法。存储装置还可以包括用于内部互连的总线1260。
在一种可能的实现方式中，所述存储装置为存储裸片，所述修复装置为逻辑裸片；或者，所述存储装置为存储裸片，所述修复装置位于包含控制器的逻辑裸片上，且所述修复装置通过所述控制器与所述存储裸片相连。
本申请实施例还提供一种修复装置，该修复装置可以用于执行前述实施例中任一修复装置执行的方法。在一示例中，该修复装置可以是存储芯片中的逻辑裸片。在又一示例中，该修复装置可以位于存储芯片中的逻辑裸片上，该逻辑裸片上还可以部署有控制器。该修复装置可以与总线通信，也可以通过控制器与存储芯片中的存储裸片通信。
本申请实施例还提供一种存储装置，该存储装置可以用于执行前述实施例中任一存储装置执行的方法。在一示例中，该存储装置可以是存储芯片中的存储裸片。在又一示例中，该存储装置可以位于存储芯片中的存储裸片上。
本申请实施例还提供一种逻辑裸片，该逻辑裸片可用于执行前述实施例中任一修复装置执行的方法。在一示例中，逻辑裸片可以包括修复装置和控制器。在一示例中，修复装置也可以位于控制器中，本申请对此不做限制。
本申请实施例还提供一种存储裸片，该存储裸片可以用于执行前述实施例中任一存储装置执行的方法。
本申请实施例还提供一种存储芯片，该存储芯片可以包括逻辑裸片和存储裸片，其中，逻辑裸片包括修复装置和控制器，存储裸片可以用于执行前述实施例中任一存 储装置执行的方法，修复装置可以用于执行前述实施例中任一修复装置执行的方法。
本申请实施例还提供一种主芯片，该主芯片可以与总线和存储芯片通信，该主芯片可以用于执行前述实施例中任一修复装置执行的方法。在一示例中，主芯片可以包括修复装置和控制器。在一示例中，修复装置也可以位于控制器中，本申请对此不做限制。
本申请实施例还提供一种存储芯片，该存储芯片可以与主芯片通信，该存储芯片可以用于执行前述实施例中任一存储装置执行的方法。
本申请实施例还提供一种控制器，控制器位于逻辑裸片上，控制器可用于转发修复装置发送至存储裸片的访问指令，以及，转发存储裸片向修复装置发送的访问响应和修复信息等。在一示例中，控制器用于接收修复装置发送的访问指令，访问指令中包含指向存储裸片中的冗余单元的冗余地址，其中，冗余单元用于替代存储裸片的存储单元中的失效单元，控制器可以将访问指令转发给存储裸片。在一示例中，控制器还可以接收存储裸片发送的访问响应，访问响应包含基于冗余单元的冗余地址执行访问请求时得到的访问结果，控制器可以将包含冗余单元的冗余地址的访问响应转发给修复装置。作为一种示例，控制器可以为DRAM控制器。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线)或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘Solid State Disk)等。

Claims (20)

  1. 一种存储单元的访问方法，其特征在于，应用于修复装置，所述方法包括：
    接收包含访问地址的访问请求；所述访问地址包括存储装置中的至少一个存储单元的原始地址；
    根据全局修复信息，识别所述访问地址指向的存储单元中是否存在失效单元；其中，所述全局修复信息包含所述存储装置中的至少一个失效单元的原始地址与用于替代所述至少一个失效单元中每个失效单元的冗余单元的冗余地址；
    在识别到所述访问地址指向的存储单元中存在第一失效单元时，将所述访问地址中指向所述第一失效单元的原始地址替换为所述第一失效单元对应的第一冗余单元的冗余地址；
    将替换后的访问请求发送至所述存储装置。
  2. 根据权利要求1所述的方法，其特征在于，在所述接收包含访问地址的访问请求之前，所述方法还包括：
    接收所述存储装置发送的所述存储装置中存在的第二失效单元的原始地址；
    分配用于替代第二失效单元的第二冗余单元；
    将所述第二失效单元的原始地址和所述第二冗余单元的冗余地址的对应关系添加到所述全局修复信息；
    其中，所述第二失效单元与所述第一失效单元相同或不同。
  3. 根据权利要求1或2所述的方法，其特征在于，所述修复装置包括一次性可编程存储器efuse；
    在所述接收包含访问地址的访问请求之前，所述方法还包括：
    接收所述存储装置发送的所述存储装置中在封装前存在的第三失效单元的原始地址；
    分配用于替代所述第三失效单元的第三冗余单元；
    将所述第三失效单元的原始地址和所述第三冗余单元的冗余地址的对应关系存储在所述efuse中；
    在所述修复装置每次上电后，将从所述efuse中读取到的所述存储装置中存在的第三失效单元的原始地址和第三冗余单元的冗余地址的对应关系，添加到所述全局修复信息；
    其中，所述第三失效单元与所述第一失效单元相同或不同。
  4. 根据权利要求1-3任一所述的方法，其特征在于，所述方法还包括：
    接收所述存储装置发送的包含所述第一冗余单元的冗余地址的访问响应；
    根据全局修复信息，将所述第一冗余单元的冗余地址替换为所述第一失效单元的原始地址；
    将包含所述第一失效单元的原始地址的所述访问响应发送至总线。
  5. 根据权利要求1-4任一所述的方法，其特征在于，所述存储装置为存储裸片，所述修复装置为逻辑裸片；或者，
    所述存储装置为存储裸片，所述修复装置位于包含控制器的逻辑裸片上，且所述 修复装置通过所述控制器与所述存储裸片相连；或者，
    所述存储装置为存储芯片，所述修复装置为主芯片；或者，
    所述存储装置为存储芯片，所述修复装置位于包含控制器的主芯片上，且所述修复装置通过所述控制器与所述存储芯片相连。
  6. 根据权利要求1-5任一所述的方法，其特征在于，所述存储装置为存储裸片，所述修复装置位于包含控制器的逻辑裸片上，且所述修复装置通过所述控制器与所述存储裸片相连；
    所述存储裸片包括至少两个数据存储区，所述全局修复信息包括所述至少两个数据存储区中的所有失效单元的原始地址与用于替换所述至少两个数据存储区中的各个失效单元的冗余单元的冗余地址；
    任一存储单元为一个数据行，任一冗余单元为一个冗余行。
  7. 根据权利要求2或6所述的方法，其特征在于，所述第一冗余单元与所述第一失效单元位于所述存储装置中的同一扇区；或者，所述第一冗余单元与所述第一失效单元位于所述存储装置中同一块中的不同扇区；或者，所述第一冗余单元与所述第一失效单元位于所述存储装置中的不同块。
  8. 一种存储单元的访问方法，其特征在于，应用于存储装置，所述存储装置包括至少一个存储单元，所述方法包括：
    接收修复装置发送的包含访问地址的访问请求，其中，所述访问地址包括所述存储装置中的冗余单元的冗余地址；其中，所述冗余单元用于替代所述至少一个存储单元中的失效单元；
    访问所述冗余地址；
    向所述修复装置发送访问响应。
  9. 根据权利要求8所述的方法，其特征在于，在所述接收修复装置发送的包含访问地址的访问请求之前，所述方法还包括：
    在所述存储装置中的存储单元中存在失效单元时，向所述修复装置发送所述失效单元的原始地址,以使述修复装置分配用于替代所述失效单元的所述冗余单元，并将所述失效单元的原始地址和所述冗余单元的冗余地址之间的对应关系加入全局修复信息。
  10. 根据权利要求8或9所述的方法，其特征在于，所述存储装置为存储裸片，所述修复装置为逻辑裸片；或者，
    所述存储装置为存储裸片，所述修复装置位于包含控制器的逻辑裸片上，且所述修复装置通过所述控制器与所述存储裸片相连；或者，
    所述存储装置为存储芯片，所述修复装置为主芯片；或者，
    所述存储装置为存储芯片，所述修复装置位于包含控制器的主芯片上，且所述修复装置通过所述控制器与所述存储芯片相连。
  11. 一种存储单元的修复方法，其特征在于，应用于存储装置，所述方法包括：
    在所述存储装置中的存储单元中存在失效单元时，向修复装置发送所述失效单元的原始地址。
  12. 根据权利要求8或9所述的方法，其特征在于，所述在所述存储装置中的存储 单元中存在失效单元时，向修复装置发送所述失效单元的原始地址，包括：
    在所述存储装置封装前，检测所述存储装置中的存储单元中是否存在失效单元；
    在所述存储装置中的存储单元中存在失效单元时，向所述修复装置发送所述失效单元的原始地址。
  13. 一种存储单元的修复方法，其特征在于，应用于修复装置，所述方法包括：
    接收存储装置发送的所述存储装置中的存储单元中存在的失效单元的原始地址；
    分配用于替换所述失效单元的冗余单元；
    将所述失效单元的原始地址与所述冗余单元的冗余地址添加到全局修复信息。
  14. 根据权利要求13所述的方法，其特征在于，所述修复装置包括一次性可编程存储器efuse；
    所述接收存储装置发送的所述存储装置中的存储单元中存在的失效单元的原始址，包括：接收所述存储装置发送的所述存储装置中在封装前存在的至少一个失效单元的原始地址；
    所述分配用于替换所述失效单元的冗余单元，包括：分配用于替代在封装前存在的各个失效单元的冗余单元；
    所述将所述失效单元的原始地址与所述冗余单元的冗余地址添加到全局修复信息，包括：将所述在封装前存在的各个失效单元的原始地址和各个失效单元对应的冗余单元的冗余地址的对应关系存储在所述efuse中；在所述修复装置每次上电后，将从所述efuse中读取到的所述存储装置中存在的至少一个失效单元的原始地址和各个失效单元对应的冗余单元的冗余地址的对应关系，添加到所述全局修复信息。
  15. 一种修复装置，其特征在于，包括：接口，处理器和存储器；
    其中，所述接口用于连接存储装置；
    所述存储器，用于存储指令；
    所述处理器，用于执行指令以实现权利要求1-7,13-14任一所述的方法。
  16. 根据权利要求15所述修复装置，其特征在于，所述存储装置为存储裸片，所述修复装置为逻辑裸片；或者，
    所述存储装置为存储裸片，所述修复装置位于包含控制器的逻辑裸片上，且所述修复装置通过所述控制器与所述存储裸片相连。
  17. 根据权利要求15所述修复装置，其特征在于，所述存储器还包括：一次性可编程存储器efuse。
  18. 一种存储装置，其特征在于，包括：接口，处理器和存储器；
    其中，所述接口用于连接修复装置；
    所述存储器，用于存储指令和数据；
    所述处理器，用于执行指令以实现权利要求8-12任一所述的方法。
  19. 根据权利要求18所述存储装置，其特征在于，所述存储装置为存储裸片，所述修复装置为逻辑裸片；或者，
    所述存储装置为存储裸片，所述修复装置位于包含控制器的逻辑裸片上，且所述修复装置通过所述控制器与所述存储裸片相连。
  20. 一种存储芯片，其特征在于，包括：逻辑裸片和至少一个存储裸片；其中，所 述逻辑裸片包括修复装置和控制器，所述修复装置通过所述控制器与所述存储裸片通信；所述修复装置用于执行权利要求1-7，13-14任一所述的方法，所述存储裸片为存储装置，所述存储装置用于执行权利要求8-12任一所述的方法。
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