WO2022226750A1 - 神经元脉冲信号的转换电路及其装置 - Google Patents

神经元脉冲信号的转换电路及其装置 Download PDF

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WO2022226750A1
WO2022226750A1 PCT/CN2021/090075 CN2021090075W WO2022226750A1 WO 2022226750 A1 WO2022226750 A1 WO 2022226750A1 CN 2021090075 W CN2021090075 W CN 2021090075W WO 2022226750 A1 WO2022226750 A1 WO 2022226750A1
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pulse signal
digital
signal
neuron
threshold
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PCT/CN2021/090075
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French (fr)
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邢楚枫
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邢楚枫
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Priority to PCT/CN2021/090075 priority Critical patent/WO2022226750A1/zh
Priority to CN202180097621.4A priority patent/CN117751526A/zh
Publication of WO2022226750A1 publication Critical patent/WO2022226750A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters

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  • the present application relates to the field of biomedical engineering, in particular to a neuron pulse signal conversion circuit and its device suitable for an invasive brain-computer interface system.
  • brain-computer interface technology As an important branch of neuroscience and biomedical engineering, brain-computer interface technology has developed rapidly in recent years. Collecting the electrical signals of the human brain through various external computing and processing equipment, neuroscientists can analyze and study the working modes of individual neurons and clusters from microscopic to macroscopic scales, deepening the understanding of the way the brain works, and the field of biomedical engineering The researchers of the company can also use various forms of brain-computer interface systems to develop corresponding medical aids to help patients with damaged nervous systems to restore function to a certain extent.
  • An invasive brain-computer interface that collects the firing signals of individual neurons at the microscopic scale can directly obtain the temporal and spatial information of neuronal firing, and the resulting signals have high spatial and temporal resolution.
  • invasive brain-computer interfaces require opening the skull and placing electrodes and signal acquisition devices under the dura.
  • the space under the dura is limited, and to avoid thermal damage to the tissue, the power of the implanted device is limited to below 0.8 milliwatts per square millimeter.
  • a neuron pulse signal conversion circuit including: a preprocessing module, an input end of the preprocessing module is adapted to receive the neuron pulse signal, and the preprocessing module is configured to generating an analog signal by amplifying and band-pass filtering the received neuron pulse signal, and outputting the analog signal at the output of the preprocessing module; and
  • a threshold detection module the input end of the threshold detection module is connected to the output end of the preprocessing module, the threshold detection module is configured to receive the analog signal output by the preprocessing module, and use a threshold detection method The analog signal is converted into a target digital pulse signal corresponding to the neuron pulse signal.
  • the threshold detection module includes a threshold detection unit and a threshold control unit connected in sequence, and the threshold detection unit is configured to convert the analog signal into a target digital pulse corresponding to the neuron pulse signal. signal, the threshold control unit is configured to adjust the detection threshold of the threshold detection unit according to the target digital pulse signal.
  • the preprocessing module includes a variable gain amplifier configured to adjust the neuron pulse signal according to a magnification of the variable gain amplifier.
  • the threshold detection module includes a threshold detection unit and a gain and threshold control unit connected in sequence, and the threshold detection unit is configured to convert the analog signal into a target corresponding to the neuron pulse signal.
  • the gain and threshold value control unit is configured to adjust the amplification factor of the variable gain amplifier and/or the detection threshold value of the threshold value detection unit according to the target digital pulse signal.
  • the threshold detection unit includes a comparator, and the comparator is configured to compare the analog signal output by the preprocessing module with the threshold of the comparator, and output a high voltage according to the comparison result.
  • the gain and threshold control unit includes a pulse signal processing subunit, and the pulse signal processing subunit is configured to process a plurality of consecutive first digital pulse signals of the single neuron pulse. Converted into the target digital pulse signal corresponding to the single neuron pulse.
  • the comparator comprises a dynamic latch comparator.
  • the output terminal of the comparator is connected to an inverter, and the inverter is configured to shape the target digital pulse signal output by the comparator.
  • the threshold detection unit includes an analog-to-digital conversion circuit and a digital comparator connected in series, an output end of the analog-to-digital conversion circuit is connected to the digital comparator, and the analog-to-digital conversion circuit is configured to
  • the analog signal output by the preprocessing module is converted into a digital signal
  • the digital comparator is configured to compare the digital signal with the threshold of the digital comparator, and output the target with a high level according to the comparison result A digital pulse signal or the target digital pulse signal of a low level.
  • the circuit further includes a subsequent digital signal processing module, and the subsequent digital signal processing module is configured to, after processing the target digital pulse signal, generate an electrical stimulation signal to act on the microelectrode.
  • the circuit further includes a subsequent digital signal processing module, and the subsequent digital signal processing module is configured to process the target digital pulse signal and send it to an external device through a wireless or wired connection device.
  • the preprocessing module includes a low noise amplifier configured to amplify the neuron pulse signal.
  • the preprocessing module includes a bandpass filter configured to bandpass filter the neuron spike signal.
  • Exemplary embodiments of the present application also provide a device for collecting and processing neuron pulse signals, including: microelectrodes configured to collect the neuron pulse signals; and converting the neuron pulse signals in any of the foregoing embodiments circuit, the input terminal of the preprocessing module is connected to the microelectrode to receive the collected neuron pulse signal.
  • Each exemplary embodiment of the present application proposes a conversion circuit for neuron pulse signals that processes multi-channel neuron pulse signals in real time based on a threshold detection method.
  • This circuit greatly increases the number of electrode channels that can be simultaneously acquired and processed by the invasive brain-computer interface system under the existing technical conditions, and based on this, a large-scale invasive brain-computer with bidirectional real-time interaction at the level of a single neuron can be realized interface system.
  • FIG. 1 is a schematic structural diagram of an analog-to-digital conversion circuit for neuron pulse signals according to an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a circuit for analog-to-digital conversion of neuron pulse signals according to an embodiment of the present application
  • FIG. 3 is a schematic diagram of a circuit structure in a preprocessing module according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a circuit structure in a threshold detection module according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a pulse signal processing circuit according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of pulse waveform and timing according to an embodiment of the present application.
  • FIG. 7 is an apparatus for collecting and processing neuron pulse signals according to an embodiment of the present application.
  • invasive brain-computer interfaces require opening the skull and placing electrodes and signal acquisition devices under the dura.
  • the power of the implanted device is limited to below 0.8 mW per square millimeter. This places high demands on the hardware resources and power of the device.
  • Existing solutions need to amplify, filter, and convert analog-to-digital signals of neuron pulses collected by microelectrodes.
  • Pulse detection and waveform alignment based on methods such as threshold or energy are sequentially performed on the digital signal generated after processing, and then feature extraction algorithms such as principal component analysis or wavelet transform are used to reduce the dimension of the pulse signal, and then use such as cluster analysis or support Methods such as vector machines classify impulse signals to distinguish nerve impulses from different neurons.
  • each exemplary embodiment of the present application provides an analog-to-digital conversion circuit for neuron pulse signals that processes multi-channel neuron pulse signals in real time based on a threshold detection method, which greatly improves the invasiveness of The number of electrode channels that can be simultaneously acquired and processed in the brain-computer interface system, and based on this, a large-scale invasive brain-computer interface system can be realized with bidirectional real-time interaction at the level of a single neuron.
  • the threshold detection method described in the embodiments of the present application refers to comparing the neuron pulse signal with a set threshold, and outputting a corresponding digital pulse signal according to the comparison result.
  • An analog-to-digital conversion circuit for neuron impulse signals includes: a preprocessing module configured to amplify and filter neuron impulse signals from microelectrodes; and a preprocessing module configured to convert neuron impulse analog signals It is a threshold detection circuit module for digital pulse signal.
  • the preprocessing module uses a low-noise amplifier to amplify the weak electrical signal collected by the front-end electrode and filters out the lower-frequency local field potential signal through a band-pass filter, so as to avoid the local field potential signal with a relatively large amplitude from reaching the subsequent threshold In the detection module, it affects the output result.
  • the amplifier is optimized for power consumption, die area and noise performance.
  • the output end of the amplifier can be selectively connected to the band-pass filtering and variable gain amplifying module, so as to further filter out the low-frequency local field potential signal and dynamically adjust the magnification of the input signal.
  • the threshold detection module uses hardware circuit to realize the threshold detection method to process the analog signal output by the band-pass filtering and variable gain amplification module, and output the digital pulse signal representing the neuron firing time.
  • the output terminal of the threshold detection circuit module is selectively connected to the gain and threshold control module.
  • the gain and threshold control module can dynamically adjust the gain of the variable gain amplifier and the threshold of the threshold detection module.
  • the subsequent digital signal processing module can perform local calculation on the digital pulse signal to generate electrical stimulation signals acting on other microelectrodes, or send it to an external computing device through wired and wireless connections after processing.
  • the LNA is capacitively coupled to the micro-electrode at the front end, and has a band-pass filtering function.
  • variable gain amplifying module uses a configurable capacitor array to adjust the gain and has a band-pass filtering function.
  • the threshold detection module uses a dynamic latch comparator to compare the input signal with the set threshold, and output a digitized pulse signal.
  • the output of the dynamic latch comparator is connected to an inverter to shape the digital pulse signal.
  • the gain and threshold control module sets the constant threshold of the dynamic latch comparator and adjusts the amplification of the variable gain amplifier.
  • the threshold detection circuit directly processes it and outputs a digital pulse signal.
  • the amplification factor of the variable gain amplifier and the detection threshold of the determination pulse signal are set by the subsequent gain and threshold control unit.
  • the neuron pulse signal is adjusted by setting a variable gain amplifier, and adjusting and controlling the amplification of the variable gain amplifier through the gain and threshold control unit, and/or adjusting the threshold detection unit through the gain and threshold control unit. Threshold, so as to screen the analog signal of neuron signal.
  • the analog-to-digital conversion circuit can be implemented to occupy a smaller chip area and generate lower power consumption than conventional analog-to-digital conversion circuits without running energy-intensive pulse classification algorithms on the analog signal.
  • it is convenient to process more electrode channel signals on a chip with a unit area, prolong the working time of the invasive brain-computer interface device, and improve the communication efficiency of the entire system.
  • FIG. 1 is a schematic structural diagram of a conversion circuit of a neuron pulse signal according to an embodiment of the present application.
  • the conversion circuit of the neuron pulse signal in this embodiment includes: a preprocessing module, an input end of the preprocessing module is adapted to receive the neuron pulse signal, and the preprocessing module is configured to The received neuron pulse signal is amplified and band-pass filtered to generate an analog signal, and the analog signal is output at the output of the preprocessing module; and a threshold detection module, the input of which is connected to the threshold detection module to the output end of the preprocessing module, the threshold detection module is configured to receive the analog signal output by the preprocessing module, and use a threshold detection method to convert the analog signal into a pulse with the neuron pulse The target digital pulse signal corresponding to the signal.
  • FIG. 2 is a schematic structural diagram of a conversion circuit of a neuron pulse signal according to an embodiment of the present application.
  • the preprocessing module includes a variable gain amplifier, and the variable gain amplifier is configured to adjust the neuron pulse signal according to the magnification of the variable gain amplifier .
  • the threshold detection module includes a threshold detection unit and a gain and threshold control unit connected in sequence, and the threshold detection unit is configured to convert the analog signal into a target corresponding to the neuron pulse signal.
  • the gain and threshold control unit is configured to adjust the amplification factor of the variable gain amplifier according to the size of the target digital pulse signal.
  • the threshold detection unit includes a comparator, and the comparator is configured to compare the analog signal output by the preprocessing module with the threshold of the comparator, and output a high voltage according to the comparison result.
  • the comparator when the analog signal is greater than or equal to the threshold of the comparator, the comparator outputs a high-level first digital pulse signal, and when the analog signal is less than the threshold of the comparator, the comparator outputs a low A first digital pulse signal of a low level; it can also be that when the analog signal is greater than or equal to the threshold of the comparator, the comparator outputs a first digital pulse signal of a low level, and when the analog signal is smaller than the comparator When the threshold value is , the comparator outputs a high-level first digital pulse signal.
  • the gain and threshold control unit includes a pulse signal processing subunit, and the pulse signal processing subunit is configured to convert a plurality of consecutive first digital pulse signals of the single neuron pulse into the single pulse signal. the target digital pulse signal corresponding to the neuron pulse;
  • the gain and threshold value control unit is further configured to adjust the size of the threshold value of the comparator according to the size of the target digital pulse signal.
  • the threshold of the comparator is set properly, the output result is a sequence of 1 and 0 (high and low level), 1 means there is a neuron pulse at the moment, and 0 means no. If the threshold of the comparator is set too large, the output digital signal is only 0. Adjusting the magnification or the threshold of the comparator needs to be based on the subsequent algorithm. For example, count the number of 1s that appear in a period of time. If there are no 1s or the number of 1s is small, it means that the overall analog signal at this time is smaller than the comparator. Threshold, either increase the magnification, or reduce the threshold of the comparator, so that the pulse peak value in the analog signal can be greater than the threshold of the comparator, so that the comparator will output the result 1 at this moment.
  • the comparator comprises a dynamic latch comparator.
  • the output terminal of the comparator is connected to an inverter, and the inverter is configured to shape the target digital pulse signal output by the comparator.
  • the subsequent gain and threshold control module will adjust the amplification of the variable gain amplifier or/and the reference voltage at the other end of the comparator according to a specific algorithm to obtain a suitable threshold or/ and magnification.
  • the threshold detection unit includes an analog-to-digital conversion circuit and a digital comparator connected in series, an output end of the analog-to-digital conversion circuit is connected to the digital comparator, and the analog-to-digital conversion circuit is configured to
  • the analog signal output by the preprocessing module is converted into a digital signal
  • the digital comparator is configured to compare the digital signal with the threshold of the digital comparator, and output the target with a high level according to the comparison result A digital pulse signal or the target digital pulse signal of a low level.
  • Dynamic latching comparators and analog-to-digital converters are two different approaches to implementing threshold detection. After the analog signal passes through the dynamic latch comparator and the inverter, it will be directly converted into the target digital pulse signal; if the dynamic latch comparator is not used, the traditional method, such as sampling the analog signal and converting it into a 10-bit digital signal, Then, the 10-bit digital signal is compared with the preset digital threshold through the digital comparator, that is, if the input value at time t is greater than the digital threshold of the digital comparator, output 1, and output 0 if it is less than to obtain the target digital pulse signal.
  • the circuit further includes a subsequent digital signal processing module, and the subsequent digital signal processing module is configured to, after processing the target digital pulse signal, generate an electrical stimulation signal to act on the microelectrode.
  • the subsequent digital signal processing module is further configured to process the target digital pulse signal and send it to an external device through a wireless or wired connection device.
  • the processing here can be based on the target digital pulse signal, running a specific algorithm to achieve a specific function, such as processing the target digital signal with a machine learning method, controlling the robot arm, and then the sensor on the robot arm will return Some signals represent information such as position, touch, etc.
  • the returned signals can generate stimulation signals through operations, and stimulate the human brain through microelectrodes, so that the human brain can receive feedback from the robotic arm.
  • the embodiments of the present application do not specifically limit the application of the target digital pulse signal.
  • the preprocessing module includes a low noise amplifier configured to amplify the neuron pulse signal.
  • the preprocessing module includes a bandpass filter configured to bandpass filter the neuron spike signal.
  • the digital signal processing module is further configured to process the target digital pulse signal and send it to an external device through an analog front end or a wired connection device.
  • FIG. 3 is a schematic diagram of a circuit structure in a preprocessing module according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a circuit structure in a threshold detection module according to an embodiment of the present application.
  • the embodiment of the present application uses a specific example to describe a processing process of an optional neuron pulse signal conversion circuit.
  • the low-noise amplifier is connected to the front-end neuron pulse signal acquisition electrode by capacitive coupling to filter out the DC offset with a typical value of about 1V caused by the electrode-tissue interface.
  • the coupling capacitor is Cin and the capacitance Value 18.8pF.
  • the capacitor Cf is connected in parallel with two diode-connected PMOS transistors to form negative feedback to obtain a lower high-pass cut-off frequency.
  • the high-pass cut-off frequency is Among them, R f is the feedback resistance, C f is the feedback capacitance, and the value of the capacitance Cf is 108fF.
  • Diode-connected PMOS transistors are used instead of polysilicon resistors to provide large resistors for ease of integration.
  • the low-pass cutoff frequency of the amplifier is Where g m is the input differential pair transconductance, and C l is the load capacitance.
  • the midband gain of this amplifier is Under the given conditions, this midband gain is about 44.5dB.
  • the band-pass filtering and variable-gain amplifying unit is composed of a variable-gain amplifier and a band-pass filter connected in series, both of which are connected to the previous stage circuit by capacitive coupling.
  • the feedback capacitor of the variable gain amplifier is connected in reverse with the operational transconductance amplifier after being connected in parallel with the capacitor array and the resistor to form negative feedback.
  • the feedback resistor here also consists of two diode-connected PMOS transistors to provide a large resistor for ease of integration.
  • the capacitor array consists of capacitors with different capacitance values and switches connected in series with the capacitors. The capacitances of different branches are connected in parallel, and the capacitance values of the conduction branches are added to form the total input or feedback capacitance value.
  • the feedback loop and the input capacitance value can be changed sequentially. Since the mid-band gain of the amplifier is determined by the ratio of the input capacitance to the feedback capacitance, the mid-band gain of the variable gain amplifier can also be varied sequentially.
  • the maximum gain value that the variable gain amplifier can provide is 29dB
  • the input capacitance value is 1.54pF
  • the feedback capacitance value is 48fF
  • the minimum gain value that can be provided is 1.2dB.
  • the band-pass filter is composed of high-pass and low-pass filters in series, and band-pass filters the output signal of the variable gain amplifier to reduce the influence of the local field potential signal on the neuron pulse signal.
  • the low-frequency cutoff frequency of the first-stage RC high-pass filter is The required large resistance is provided in series by two diode-connected PMOS transistors.
  • the capacitance C h value is 15.5fF, resulting in a low frequency cutoff frequency of 305Hz.
  • the operational transconductance amplifier is connected in reverse phase, and the output terminal is connected to the load capacitor. The two form a low-pass filter.
  • the high-frequency cut-off frequency is determined by the ratio of the transconductance of Gm to the load capacitor. is 37kHz.
  • the threshold detection unit is formed by a dynamic latch comparator and an inverter in series. One end of the comparator is connected to the neuron pulse signal after amplification and filtering, and the other end is connected to a reference voltage for comparison.
  • the DC operating point of the aforementioned operational transconductance amplifier is set at half of the power supply voltage, that is, 1/2 times Vdd, and the power supply voltage Vdd is 1.2V, the DC operating point is 0.6V.
  • the typical value of the neuron pulse signal collected by the invasive electrode is 50 microvolts to 1 millivolt.
  • the reference voltage V at the other end of the comparator is used here.
  • the inverter is connected to the output end of the comparator to shape the digital pulse signal after the analog-to-digital conversion.
  • the gain and threshold control unit is composed of a pulse signal processing subunit and a gain control subunit, which together realize further processing of the digitized pulse signal and gain adjustment of the variable gain amplifier.
  • the pulse signal processing subunit is configured to convert a plurality of consecutive first digital pulse signals of the single neuron pulse into the target digital pulse signal, and the gain control subunit is configured to adjust the variable The amplification of the gain amplifier, and/or the reference value of the comparator is adjusted.
  • the subsequent gain and threshold control module will adjust the amplification of the variable gain amplifier or/and the reference voltage at the other end of the comparator according to a specific algorithm to obtain a suitable threshold or/ and magnification.
  • FIG. 5 is a schematic structural diagram of a pulse signal processing circuit in a threshold detection module according to an embodiment of the present application.
  • a digital pulse signal obtained after being amplified and filtered by an analog front end and converted by a comparator is converted in the pulse signal processing part. is a specific timestamp representing the release of the pulse signal.
  • the aforementioned T0-T9 switching signals are given by a specific gain setting program. In this example, first set the gain of the variable gain amplifier to the minimum value, and then count the number of digital pulses measured per unit time. If the value is 0, increase the gain of the variable gain amplifier by one level. Repeat the above steps until the number of digital pulses detected per unit time is not 0.
  • the gain value at this time is stored in the register as the gain multiplier of this channel electrode. If the number of digital pulses measured per unit time is still 0 when the gain is adjusted to the maximum, shield the electrode of this channel. After that, the digital pulses obtained by the unshielded channel electrodes in normal operation will be transmitted to the subsequent digital processing modules for local calculation to generate electrical stimulation signals or processed by the baseband chip and sent to external devices through the RF front-end.
  • the magnification can be adjusted.
  • the specific algorithm includes, but is not limited to, the number of digital pulses per unit time as given in the specific embodiment. If it is 0, it means that the magnification is small, and the magnification of the variable gain amplifier is increased by one level, and then the cycle is repeated until The number of digital pulses per unit time is not 0.
  • FIG. 6 is a schematic diagram of a pulse waveform and timing sequence according to an embodiment of the present application.
  • Vin represents the input pulse signal input from the micro-electrode to the preprocessing module
  • Vd represents the pulse signal output by the inverter
  • Vpulse represents the pulse signal processed by the pulse signal processing circuit.
  • Vd in FIG. 6 can be understood as the waveform of the aforementioned first digital pulse signal, which is 0 and 1, 0 represents no pulse, and 1 represents pulse.
  • FIG. 7 is an apparatus for collecting and processing neuron pulse signals according to an embodiment of the present application.
  • the device includes: a microelectrode configured to collect the neuron pulse signal; and the neuron pulse signal conversion circuit according to any of the above embodiments, the input end of the preprocessing module is connected to the microelectrode to receive the collected neuron pulse signals.
  • the conversion circuit of the acquisition and processing apparatus may have the same or similar functions as the conversion circuit of the neuron pulse signal in any of the foregoing embodiments, and details are not described herein again.

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Abstract

一种神经元脉冲信号的转换电路及采集处理装置，该转换电路包括预处理模块，预处理模块的输入端适于接收所述神经元脉冲信号，预处理模块配置为通过对所接收的神经元脉冲信号进行放大和带通滤波来生成模拟信号，并在预处理模块的输出端输出所述模拟信号；以及阈值检测模块，阈值检测模块的输入端连接至所述预处理模块的所述输出端，阈值检测模块配置为接收预处理模块输出的所述模拟信号，并使用阈值检测法将所述模拟信号转换为与神经元脉冲信号对应的目标数字脉冲信号。

Description

神经元脉冲信号的转换电路及其装置 技术领域
本申请涉及生物医学工程领域，尤其涉及一种适用于侵入式脑机接口系统的神经元脉冲信号的转换电路及其装置。
背景技术
作为神经科学与生物医学工程领域的重要分支，脑机接口技术近年来发展迅速。通过各种外部计算处理设备采集人脑的电信号，神经科学家可以从微观到宏观的不同尺度来分析和研究神经元个体和集群的工作模式，加深对于大脑运作方式的理解，而生物医学工程领域的研究人员也可以利用各种形式的脑机接口系统，开发出相应的医疗辅助设备，帮助神经系统受损的病人在一定程度上恢复功能。
在微观尺度上采集单个神经元放电信号的侵入式脑机接口，可以直接获得神经元放电的时间和空间信息，所得的信号具有较高的时空分辨率。
传统技术中，侵入式脑机接口需要打开颅骨，将电极和信号采集装置放置于硬脑膜之下。硬脑膜之下的空间有限，并且为了避免对组织的热损伤，植入器件的功率被限制在0.8毫瓦每平方毫米之下。
发明内容
本申请各示例性实施例提供了一种神经元脉冲信号的转换电路，包括：预处理模块，所述预处理模块的输入端适于接收所述神经元脉冲信号，所述预处理模块配置为通过对所接收的所述神经元脉冲信号进行放大和带通滤波来生成模拟信号，并在所述预处理模块的输出端输出所述模拟信号；以及
阈值检测模块，所述阈值检测模块的输入端连接至所述预处理模 块的所述输出端，所述阈值检测模块配置为接收所述预处理模块输出的所述模拟信号，并使用阈值检测法将所述模拟信号转换为与所述神经元脉冲信号对应的目标数字脉冲信号。
在一实施例中，所述阈值检测模块包括依次连接的阈值检测单元和阈值控制单元，所述阈值检测单元配置为，将所述模拟信号转换为与所述神经元脉冲信号对应的目标数字脉冲信号，所述阈值控制单元配置为，根据所述目标数字脉冲信号调整所述阈值检测单元的检测阈值。
在一实施例中，所述预处理模块包括可变增益放大器，所述可变增益放大器配置为，根据所述可变增益放大器的放大倍率来调整所述神经元脉冲信号。
在一实施例中，所述阈值检测模块包括依次连接的阈值检测单元和增益及阈值控制单元，所述阈值检测单元配置为，将所述模拟信号转换为与所述神经元脉冲信号对应的目标数字脉冲信号，所述增益及阈值控制单元配置为，根据所述目标数字脉冲信号调整所述可变增益放大器的放大倍率和/或所述阈值检测单元的检测阈值。
在一实施例中，所述阈值检测单元包括比较器，所述比较器配置为，将所述预处理模块输出的所述模拟信号与所述比较器的阈值进行比较，根据比较结果输出高电平的第一数字脉冲信号或低电平的第一数字脉冲信号。
在一实施例中，所述增益及阈值控制单元包括脉冲信号处理子单元，所述脉冲信号处理子单元配置为，将所述单次神经元脉冲的多个连续的所述第一数字脉冲信号转化为所述单次神经元脉冲对应的所述目标数字脉冲信号。
在一实施例中，所述比较器包括动态锁存比较器。
在一实施例中，所述比较器的输出端连接至反相器，所述反相器配置为，对所述比较器输出的所述目标数字脉冲信号进行整形。
在一实施例中，所述阈值检测单元包括串联的模数转换电路和数字比较器，所述模数转换电路的输出端连接所述数字比较器，所述模数转换电路配置为，将所述预处理模块输出的所述模拟信号转化为数字信号，所述数字比较器配置为，将所述数字信号与所述数字比较器的阈值进行比较，根据比较结果输出高电平的所述目标数字脉冲信号或低电平的所述目标数字脉冲信号。
在一实施例中，所述电路还包括后续数字信号处理模块，所述后续数字信号处理模块配置为，对所述目标数字脉冲信号处理后，生成电刺激信号作用于所述微电极。
在一实施例中，所述电路还包括后续数字信号处理模块，所述后续数字信号处理模块配置为，将所述目标数字脉冲信号处理后通过无线或有线连接装置发送至外部设备。
在一实施例中，所述预处理模块包括低噪声放大器，所述低噪声放大器配置为对所述神经元脉冲信号进行放大。
在一实施例中，所述预处理模块包括带通滤波器，所述带通滤波器配置为对所述神经元脉冲信号进行带通滤波。
本申请各示例性实施例还提供了一种神经元脉冲信号的采集处理装置，包括：微电极，配置为采集所述神经元脉冲信号；以及上述任一实施例中的神经元脉冲信号的转换电路，所述预处理模块的输入端连接至所述微电极以接收所采集的所述神经元脉冲信号。
本申请各示例性实施例提出了一种基于阈值检测法对多通道神经元脉冲信号进行实时处理的神经元脉冲信号的转换电路。该电路大幅提高了侵入式脑机接口系统在现有技术条件下可同时采集与处理的电极通道数量，并可以此为基础实现在单个神经元的层面上双向实 时交互的大规模侵入式脑机接口系统。
附图说明
此处所说明的附图用来提供对本申请的进一步理解，构成本申请的一部分，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在附图中：
图1是根据本申请一实施例的一种神经元脉冲信号的模数转换电路的结构示意图；
图2是根据本申请一实施例的神经元脉冲信号的模数转换的电路的结构示意图；
图3是根据本申请一实施例的预处理模块内的电路结构示意图；
图4是根据本申请一实施例的阈值检测模块内的电路结构示意图；
图5是根据本申请一实施例的脉冲信号处理电路结构示意图；
图6是根据本申请一实施例的脉冲波形和时序示意图；以及
图7是根据本申请一实施例的神经元脉冲信号的采集处理装置。
具体实施方式
下文中将参考附图并结合实施例来详细说明本申请。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
需要说明的是，本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而并非对对象的限定，也不旨在用于描述特定的顺序或先后次序。
除非另有明确定义，本申请中当一元件被称为“连接”另一个元件，它可以直接电连接于另一个元件，也可以存在居中的元件。
传统技术中，侵入式脑机接口需要打开颅骨，将电极和信号采集 装置放置于硬脑膜之下。然而，由于硬脑膜之下的空间有限，并且为了避免对组织的热损伤，所以植入器件的功率被限制在0.8毫瓦每平方毫米之下。这对装置的硬件资源和功率提出了很高的要求。现有的解决方案需要对微电极采集到的神经元脉冲信号进行放大、滤波以及模数转换的处理。对经过处理后产生的数字信号依次进行基于阈值或能量等方法的脉冲检测以及波形对齐，然后使用主成分分析或小波变换等特征提取算法对脉冲信号进行降维，再运用如聚类分析或支持向量机等方法对脉冲信号进行分类，以区分来自于不同神经元的神经脉冲信号。
发明人发现，这个过程会占用大量的芯片面积并消耗很高的功率，从而缩短了侵入式脑机接口设备的工作时间，限制了脑机接口可实时处理的电极数量。
为了克服现有技术的不足，本申请各示例性实施例提供一种基于阈值检测法对多通道神经元脉冲信号进行实时处理的神经元脉冲信号的模数转换电路，该电路大幅提高了侵入式脑机接口系统的可同时采集与处理的电极通道的数量，并可以此为基础实现在单个神经元的层面上的双向实时交互的大规模侵入式脑机接口系统。
本申请实施例中所述的阈值检测法是指将神经元脉冲信号与设定阈值进行比较，根据比较结果输出相应数字脉冲信号。
本申请一实施例提供的神经元脉冲信号的模数转换电路，包括：配置为对来自微电极的神经元脉冲信号进行放大和滤波的预处理模块；以及配置为将对神经元脉冲模拟信号转换为数字脉冲信号的阈值检测电路模块。
预处理模块使用低噪声放大器对前端电极采集到的微弱电信号进行放大并通过带通滤波器滤除较低频率的局部场电位信号，从而避免幅度相对较大的局部场电位信号在之后的阈值检测模块中，对输出结果产生影响。该放大器的功耗、芯片使用面积和噪声性能经过优化。放大器的输出端可选择地连接至带通滤波及可变增益放大模块，以进一步滤除低频的局部场电位信号并可动态调整输入信号的放大倍率。
阈值检测模块使用硬件电路实现阈值检测法，以处理带通滤波及可变增益放大模块输出的模拟信号，并输出代表神经元发放时间的数字脉冲信号。阈值检测电路模块的输出端可选择地连接至增益及阈值控制模块。
增益及阈值控制模块可动态调整前述可变增益放大器的增益以及阈值检测模块的阈值。
后续数字信号处理模块可对数字脉冲信号进行本地计算后，生成作用于其他微电极的电刺激信号，或经过处理后通过有线以及无线连接发送至外部计算设备。
在一实施例中，低噪声放大器与前端的微电极采用电容耦合，并具有带通滤波功能。
在一实施例中，可变增益放大模块使用可配置电容阵列调整增益，并具有带通滤波功能。
在一实施例中，阈值检测模块使用动态锁存比较器比较输入信号和设定阈值，输出数字化脉冲信号。
在一实施例中，动态锁存比较器的输出端连接至反相器，对数字脉冲信号整形。
在一实施例中，增益及阈值控制模块设定动态锁存比较器的恒定阈值并调整可变增益放大器的放大倍率。
本申请实施例提出的神经元脉冲信号的转换电路，由电极采集到的信号经过低噪声放大和滤波后，由阈值检测电路直接对其进行处理并输出数字脉冲信号。可变增益放大器的放大倍率以及判定脉冲信号的检测阈值由后续的增益及阈值控制单元设定。通过设置可变增益放大器，并通过增益及阈值控制单元来调整控制可变增益放大器的放大倍率来调整所述神经元脉冲信号，和/或，通过增益及阈值控制单元来调整阈值检测单元中的阈值，从而实现筛选神经元信号的模拟信号。这样，无需对模拟信号运行高能耗的脉冲分类算法，就能实现该模数转换电路相对于传统的模数转换电路而言占用更小的芯片面积并且 产生更低的能耗。由此，便于在单位面积的芯片上处理更多的电极通道信号，延长侵入式脑机接口设备的工作时间并提升整个系统的通信效率。
下面结合附图对本申请的实施例做详细说明。本申请中的各示例性实施例在以本申请技术方案为前提下进行实施，给出了详细的实施方式和具体的实施细节，但本申请的保护范围不限于下述的实施例。
图1是根据本申请一实施例的神经元脉冲信号的转换电路的结构示意图。如图1所示，本实施例的神经元脉冲信号的转换电路包括：预处理模块，所述预处理模块的输入端适于接收所述神经元脉冲信号，所述预处理模块配置为通过对所接收的所述神经元脉冲信号进行放大和带通滤波来生成模拟信号，并在所述预处理模块的输出端输出所述模拟信号；以及阈值检测模块，所述阈值检测模块的输入端连接至所述预处理模块的所述输出端，所述阈值检测模块配置为接收所述预处理模块输出的所述模拟信号，并使用阈值检测法将所述模拟信号转换为与所述神经元脉冲信号对应的目标数字脉冲信号。
图2是根据本申请一实施例的神经元脉冲信号的转换电路的结构示意图。如图2所示，在一实施例中，所述预处理模块包括可变增益放大器，所述可变增益放大器配置为，根据所述可变增益放大器的放大倍率来调整所述神经元脉冲信号。
在一实施例中，所述阈值检测模块包括依次连接的阈值检测单元和增益及阈值控制单元，所述阈值检测单元配置为，将所述模拟信号转换为与所述神经元脉冲信号对应的目标数字脉冲信号，所述增益及阈值控制单元配置为，根据所述目标数字脉冲信号的大小调整所述可变增益放大器的放大倍率。
在一实施例中，所述阈值检测单元包括比较器，所述比较器配置为，将所述预处理模块输出的所述模拟信号与所述比较器的阈值进行比较，根据比较结果输出高电平的第一数字脉冲信号或低电平的第一 数字脉冲信号。可以是，当所述模拟信号大于或等于比较器的阈值时，所述比较器输出高电平的第一数字脉冲信号，当所述模拟信号小于比较器的阈值时，所述比较器输出低电平的第一数字脉冲信号；也可以是，当所述模拟信号大于或等于比较器的阈值时，所述比较器输出低电平的第一数字脉冲信号，当所述模拟信号小于比较器的阈值时，所述比较器输出高电平的第一数字脉冲信号。
所述增益及阈值控制单元包括脉冲信号处理子单元，所述脉冲信号处理子单元配置为，将所述单次神经元脉冲的多个连续的所述第一数字脉冲信号转化为所述单次神经元脉冲对应的所述目标数字脉冲信号；
所述增益及阈值控制单元还配置为，根据所述目标数字脉冲信号的大小调整所述比较器的阈值的大小。
如果比较器的阈值设置得当，输出结果就是1和0(高低电平)的序列，1代表此刻有神经元脉冲，0代表无。如果比较器的阈值设置过大，则输出的数字信号只有0。调整放大倍率或者比较器的阈值需要根据后续的算法，例如，在一段时间内统计出现的1的个数，如果没有1或者1的个数较少，说明此时的模拟信号整体小于比较器的阈值，要么增大放大倍率，要么调小比较器的阈值，以使得模拟信号中的脉冲峰值能够大于比较器的阈值，这样比较器就会在该时刻输出结果1。
在一实施例中，所述比较器包括动态锁存比较器。
在一实施例中，所述比较器的输出端连接至反相器，所述反相器配置为，对所述比较器输出的所述目标数字脉冲信号进行整形。
根据比较器和反相器输出的信号，后续的增益及阈值控制模块会根据特定的算法，调整可变增益放大器的放大倍率或/和比较器另一端的参考电压，以获得合适的阈值或/和放大倍率。
在一实施例中，所述阈值检测单元包括串联的模数转换电路和数字比较器，所述模数转换电路的输出端连接所述数字比较器，所述模数转换电路配置为，将所述预处理模块输出的所述模拟信号转化为数字信号，所述数字比较器配置为，将所述数字信号与所述数字比较器的阈值进行比较，根据比较结果输出高电平的所述目标数字脉冲信号或低电平的所述目标数字脉冲信号。
动态锁存比较器和模数转换器是实现阈值检测的两种不同方案。模拟信号经过动态锁存比较器和反相器以后，会直接转变成目标数字脉冲信号；如果不使用动态锁存比较器，则按照传统方式，例如对模拟信号进行采样并转换为10bit数字信号，然后将10bit数字信号通过数字比较器与预设的数字阈值进行比较,即如果时刻t的输入值大于数字比较器的数字阈值，则输出1，小于则输出0，得到目标数字脉冲信号。
在一实施例中，所述电路还包括后续数字信号处理模块，所述后续数字信号处理模块配置为，对所述目标数字脉冲信号处理后，生成电刺激信号作用于所述微电极。
在一实施例中，所述后续数字信号处理模块还配置为，将所述目标数字脉冲信号处理后通过无线或有线连接装置发送至外部设备。
需要说明的是，此处的处理可以是根据目标数字脉冲信号，运行特定的算法来实现特定的功能，例如用机器学习的方法处理目标数字信号，控制机械臂，然后机械臂上的传感器会返回一些信号，代表位置，触觉等信息，返回的信号通过运算可以生成刺激信号，通过微电极刺激人脑，使人脑可以接收到到机械臂的反馈。本申请实施例对于目标数字脉冲信号的应用不做具体限定。
在一实施例中，所述预处理模块包括低噪声放大器，所述低噪声放大器配置为对所述神经元脉冲信号进行放大。
在一实施例中，所述预处理模块包括带通滤波器，所述带通滤波器配置为对所述神经元脉冲信号进行带通滤波。
在一实施例中，所述数字信号处理模块还配置为，将所述目标数字脉冲信号处理后通过模拟前端或有线连接装置发送至外部设备。
图3是根据本申请一实施例的预处理模块内的电路结构示意图。图4是根据本申请一实施例的阈值检测模块内的电路结构示意图。本申请实施例通过一具体示例来说明一种可选的神经元脉冲信号的转换电路的处理过程。如图3、4所示，低噪声放大器采用电容耦合方式与前端神经元脉冲信号采集电极连接，以滤除电极-组织界面引起的典型值为1V左右的直流偏移，耦合电容为Cin，电容值18.8pF。电容Cf与两个二极管连接PMOS晶体管并联后形成负反馈，以获得较低的高通截止频率，高通截止频率为
Figure PCTCN2021090075-appb-000001
其中R f为反馈电阻，C f为反馈电容，电容Cf值为108fF。使用二极管连接PMOS晶体管取代多晶硅电阻，以提供便于集成的大电阻。放大器的低通截止频率为
Figure PCTCN2021090075-appb-000002
其中g m为输入差分对跨导，C l为负载电容。该放大器的中带增益为
Figure PCTCN2021090075-appb-000003
在给定条件下，该中带增益约为44.5dB。
所述带通滤波及可变增益放大单元，由可变增益放大器及带通滤波器串联而成，两者均使用电容耦合方式与前一级电路连接。可变增益放大器的反馈电容由电容阵列以及电阻并联后与运算跨导放大器反相连接，形成负反馈。与前述低噪声放大器相同，此处反馈电阻也由两个二极管连接PMOS晶体管组成，以提供便于集成的大电阻。电容阵列由不同电容值的电容和与电容串联的开关组成。不同支路的电容并联，导通支路的电容值相加后形成总的输入或反馈电容值。在外部控制信号作用下，反馈环路和输入的电容值可以依次变化。由于该放大器的中带增益由输入电容和反馈电容的比值决定，该可变增益放 大器的中带增益也能够依次变化。该可变增益放大器可提供的最大增益值为29dB，此时输入电容值为1.54pF，反馈电容值为48fF，所能提供的最小增益值为1.2dB。
带通滤波器由高通和低通滤波器串联而成，对可变增益放大器输出信号进行带通滤波，以减少局部场电位信号对神经元脉冲信号的影响。第一级RC高通滤波器的低频截止频率为
Figure PCTCN2021090075-appb-000004
由两个二极管连接的PMOS晶体管串联提供所需的大电阻。电容C h值为15.5fF，所得的低频截止频率为305Hz。运算跨导放大器反相连接，输出端接负载电容，两者形成低通滤波器，高频截止频率由Gm的跨导和负载电容比值决定，负载电容C l值为18.8pF，高频截止频率为37kHz。
所述阈值检测单元由动态锁存比较器和反相器串联而成，比较器的一端连接经过放大和滤波之后的神经元脉冲信号，另一端连接比较用的参考电压。考虑到前述运算跨导放大器的直流工作点设置在电源电压的一半，即1/2倍Vdd，而电源电压Vdd为1.2V，所以直流工作点为0.6V。侵入式电极采集到的神经元脉冲信号的典型值为50微伏到1毫伏，为了能够对脉冲信号进行阈值检测，正确区分出神经元放电时间，此处将比较器另一端的参考电压V comp设置为733mV，即比放大器和滤波器直流工作点高133mV。比较器时钟信号CLK频率设置为50kHz。大于此频率的时钟信号不影响最终结果。反相器连接在比较器输出端，对模数转换后的数字脉冲信号进行整形。
增益及阈值控制单元由脉冲信号处理子单元和增益控制子单元两部分组成，共同实现对数字化脉冲信号的进一步处理和可变增益放大器的增益调节。脉冲信号处理子单元配置为，将所述单次神经元脉冲的多个连续的所述第一数字脉冲信号转化为所述目标数字脉冲信号，增益控制子单元配置为，根据调整所述可变增益放大器的放大倍率，和/或，调整所述比较器的参考值。
根据比较器和反相器输出的信号，后续的增益及阈值控制模块会根据特定的算法，调整可变增益放大器的放大倍率或/和比较器另一端的参考电压，以获得合适的阈值或/和放大倍率。
图5是根据本申请一实施例的阈值检测模块内的脉冲信号处理电路结构示意图，如图5所示，经模拟前端放大滤波和比较器转换后得到的数字脉冲信号，在脉冲信号处理部分转化为代表脉冲信号发放的具体时间戳。在初始化过程中，由特定的增益设置程序给出前述T0～T9开关信号。本实例中，首先将可变增益放大器的增益设置为最小值，然后统计单位时间内测量得到的数字脉冲个数，若该值为0，则将可变增益放大器的增益调大一档。重复上述步骤直至单位时间内检测到的数字脉冲个数不为0。将此时的增益值存入寄存器中，作为该通道电极的增益倍数。如果增益调整至最大时，单位时间内测量得到的数字脉冲个数仍为0，则屏蔽该通道电极。之后正常工作未屏蔽的通道电极所得的数字脉冲将传输到后续数字处理模块，用于本地计算生成电刺激信号或经基带芯片处理后通过射频前端发送至外部设备。
本申请实施例中涉及的根据阈值检测单元输出的目标脉冲数字信号以及特定的算法，可以调整放大倍率。特定算法包括但不限于具体实施例中给出的，统计单位时间内的数字脉冲个数，若为0则说明放大倍率较小，将可变增益放大器的放大倍率增大一档，然后循环直到单位时间内的数字脉冲个数不为0。
图6是根据本申请一实施例的脉冲波形和时序示意图。如图5所示，图6中的Vin、Vd和Vpulse与图3和图4中对应。Vin表示从微电极输入预处理模块的输入脉冲信号，Vd表示反相器输出的脉冲信号，Vpulse表示经过脉冲信号处理电路处理后的脉冲信号。
图6中的Vd可以理解为前述第一数字脉冲信号的波形，为0和1，0代表无脉冲，1代表有脉冲。
图7是根据本申请一实施例的神经元脉冲信号的采集处理装置。 所述装置包括：微电极，配置为采集所述神经元脉冲信号；以及根据上述任一实施例所述的神经元脉冲信号的转换电路，所述预处理模块的输入端连接至所述微电极以接收所采集的所述神经元脉冲信号。
可以理解的是，采集处理装置的转换电路可以具有与前述任一实施例中的神经元脉冲信号的转换电路的相同或相似的功能，这里不再赘述。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (14)

  1. 一种神经元脉冲信号的转换电路，包括：
    预处理模块，所述预处理模块的输入端适于接收所述神经元脉冲信号，所述预处理模块配置为通过对所接收的所述神经元脉冲信号进行放大和带通滤波来生成模拟信号，并在所述预处理模块的输出端输出所述模拟信号；以及
    阈值检测模块，所述阈值检测模块的输入端连接至所述预处理模块的所述输出端，所述阈值检测模块配置为接收所述预处理模块输出的所述模拟信号，并使用阈值检测法将所述模拟信号转换为与所述神经元脉冲信号对应的目标数字脉冲信号。
  2. 根据权利要求1所述的电路，其中，所述阈值检测模块包括依次连接的阈值检测单元和阈值控制单元，所述阈值检测单元配置为，将所述模拟信号转换为与所述神经元脉冲信号对应的目标数字脉冲信号，所述阈值控制单元配置为，根据所述目标数字脉冲信号调整所述阈值检测单元的检测阈值。
  3. 根据权利要求1所述的电路，其中，所述预处理模块包括可变增益放大器，所述可变增益放大器配置为，根据所述可变增益放大器的放大倍率来调整所述神经元脉冲信号。
  4. 根据权利要求3所述的电路，其中，所述阈值检测模块包括依次连接的阈值检测单元和增益及阈值控制单元，所述阈值检测单元配置为，将所述模拟信号转换为与所述神经元脉冲信号对应的目标数字脉冲信号，所述增益及阈值控制单元配置为，根据所述目标数字脉冲信号调整所述可变增益放大器的放大倍率和/或所述阈值检测单元的检测阈值。
  5. 根据权利要求1所述的电路，其中，所述阈值检测单元包括比较器，所述比较器配置为，将所述预处理模块输出的所述模拟信号 与所述比较器的阈值进行比较，根据比较结果输出高电平的第一数字脉冲信号或低电平的第一数字脉冲信号。
  6. 根据权利要求5所述的电路，其中，所述增益及阈值控制单元包括脉冲信号处理子单元，所述脉冲信号处理子单元配置为，将单次神经元脉冲的多个连续的所述第一数字脉冲信号转化为所述单次神经元脉冲对应的所述目标数字脉冲信号。
  7. 根据权利要求5所述的电路，其中，所述比较器包括动态锁存比较器。
  8. 根据权利要求5所述的电路，其中，所述比较器的输出端连接至反相器，所述反相器配置为，对所述比较器输出的所述目标数字脉冲信号进行整形。
  9. 根据权利要求1所述的电路，其中，所述阈值检测单元包括串联的模数转换电路和数字比较器，所述模数转换电路的输出端连接所述数字比较器，所述模数转换电路配置为，将所述预处理模块输出的所述模拟信号转化为数字信号，所述数字比较器配置为，将所述数字信号与所述数字比较器的阈值进行比较，根据比较结果输出高电平的所述目标数字脉冲信号或低电平的所述目标数字脉冲信号。
  10. 根据权利要求1所述的电路，其中，所述电路还包括后续数字信号处理模块，所述后续数字信号处理模块配置为，对所述目标数字脉冲信号处理后，生成电刺激信号作用于微电极。
  11. 根据权利要求1所述的电路，其中，所述电路还包括后续数字信号处理模块，所述后续数字信号处理模块配置为，将所述目标数字脉冲信号处理后通过无线或有线连接装置发送至外部设备。
  12. 根据权利要求1所述的电路，其中，所述预处理模块包括低噪声放大器，所述低噪声放大器配置为对所述神经元脉冲信号进行放 大。
  13. 根据权利要求1所述的电路，其中，所述预处理模块包括带通滤波器，所述带通滤波器配置为对所述神经元脉冲信号进行带通滤波。
  14. 一种神经元脉冲信号的采集处理装置，包括：
    微电极，配置为采集所述神经元脉冲信号；以及
    根据权利要求1至13中任一项所述的神经元脉冲信号的转换电路，所述预处理模块的输入端连接至所述微电极以接收所采集的所述神经元脉冲信号。
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