WO2022221784A1 - An architecture of elastic forwarding pipeline for programmable switch chips - Google Patents

Abstract

An elastic forwarding pipeline architecture that includes a plurality of pipeline stage processors (PSPs) serially connected and partitioned into a first set of PSPs, a second set of flexibly allocated PSPs, and a third set of PSPs. The elastic forwarding pipeline architecture includes a traffic manager (TM) and an input/output (I/O) selector. The I/O selector is coupled to the TM and to each PSP in the second set of flexibly allocated PSPs

Description

An Architecture of Elastic Forwarding Pipeline for Programmable Switch Chips

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to United States Provisional Patent Application Number 63/197,874, filed June 7, 2021 by Haoyu Song and titled “An Architecture of Elastic Forwarding Pipeline for Programmable Switch Chips,” which is incorporated by reference.

TECHNICAL FIELD

[0002] The present disclosure is generally related to the field of data communication fixed networks and, in particular, to an architecture of elastic forwarding pipeline for programmable switch chips.

BACKGROUND

[0003] Programmable network devices are used to support in-network computing, network automation, and various network innovations. Such programmable network devices may include, for example, an application-specific integrated circuit (ASIC), a network processor (NP), a Tofino chip, and so on.

[0004] The programmable network devices can include a Protocol-Independent Switch Architecture (PISA) and can be programmed using the Programming Protocol-independent Packet Processors (P4) language.

SUMMARY

[0005] The disclosed aspects/embodiments provide an elastic forwarding pipeline architecture for programmable switch chips. The elastic forwarding pipeline architecture permits pipeline stage processors (PSPs) to be allocated arbitrarily as opposed to the fixed allocation of PSPs in an elastic forwarding pipeline architecture with a static or hard pipeline. The elastic forwarding pipeline also permits unused PSPs to be put in low-power mode, which saves energy. The elastic forwarding pipeline supports in-service incremental updates, which involves inserting and/or removing one or more PSPs. By using the elastic forwarding pipeline, network resources are better utilized and energy costs are reduced.

[0006] A first aspect relates to an elastic forwarding pipeline architecture comprising: a plurality of pipeline stage processors (PSPs), the plurality of PSPs serially connected and partitioned into a first set of PSPs, a second set of flexibly allocated PSPs, and a third set of PSPs; a traffic manager (TM); and an input/output (I/O) selector coupled to the TM and to each PSP in the second set of flexibly allocated PSPs.

[0007] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the first set of PSPs and a first PSP of the second set of flexibly allocated PSPs are dedicated for an ingress pipeline.

[0008] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the third set of PSPs and a last PSP of the second set of flexibly allocated PSPs are dedicated for an egress pipeline.

[0009] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the ingress pipeline can be extended to include any number of unallocated PSPs between the first PSP and the last PSP of the second set of flexibly allocated PSPs.

[0010] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the egress pipeline can be extended to include any number of unallocated PSPs between the first PSP and the last PSP of the second set of flexibly allocated PSPs.

[0011] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the I/O selector is configured to bypass the unallocated PSPs between the first PSP and the last PSP of the second set of flexibly allocated PSPs.

[0012] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the unallocated PSPs between the first PSP and the last PSP of the second set of flexibly allocated PSPs are placed in low-power mode.

[0013] Optionally, in any of the preceding aspects, another implementation of the aspect provides that a number of PSPs in the first set of PSPs, the second set of flexibly allocated PSPs, and the third set of PSPs are predetermined by a chip manufacturer based on application statistics. [0014] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the ingress pipeline and the egress pipeline can be reconfigured while the programmable switch chips are installed on a programmable network device using stage migration and I/O selector reconfiguration.

[0015] A second aspect relates to a method of processing a packet in elastic forwarding pipeline architecture, comprising: receiving requirements of an application for a pipeline stage processor (PSP) pipeline; expanding and/or contracting at least one of an ingress pipeline or an egress pipeline of the PSP pipeline using a set of flexibly allocated PSPs to satisfy the requirements; mapping the requirements to the PSP pipeline; and processing the packet associated with the application through the PSP pipeline. [0016] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the ingress pipeline comprises at least one PSP from the set of flexibly allocated PSPs.

[0017] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the egress pipeline comprises at least one PSP from the set of flexibly allocated PSPs.

[0018] Optionally, in any of the preceding aspects, another implementation of the aspect further comprises placing any unallocated PSPs in the set of flexibly allocated PSPs to a low power mode.

[0019] Optionally, in any of the preceding aspects, another implementation of the aspect further comprises bypassing the unallocated PSPs in the set of flexibly allocated PSPs.

[0020] Optionally, in any of the preceding aspects, another implementation of the aspect further comprises receiving a new ingress PSP stage processing requirement for the application; allocating a left-most unallocated PSP from the set of flexibly allocated PSPs to the ingress pipeline; copying each ingress PSP stage, that is downstream from an intended location of the new ingress PSP stage, to a right-adjacent PSP; and inserting the new ingress PSP stage in the intended location of the ingress pipeline.

[0021] Optionally, in any of the preceding aspects, another implementation of the aspect further comprises receiving a new egress PSP stage processing requirement for the application; allocating a right-most unallocated PSP from the set of flexibly allocated PSPs to the egress pipeline; copying each egress PSP stage, that is upstream from an intended location of the new egress PSP stage, to a left-adjacent PSP; and inserting the new egress PSP stage in the intended location of the egress pipeline.

[0022] Optionally, in any of the preceding aspects, another implementation of the aspect further comprises receiving instructions to remove an ingress PSP stage for the application; copying each ingress PSP stage, that is downstream from the ingress PSP stage, to a left- adjacent PSP; unallocating a right-most PSP from the ingress pipeline; and placing the unallocated PSP to a low power mode.

[0023] Optionally, in any of the preceding aspects, another implementation of the aspect further comprises receiving instructions to remove an egress PSP stage for the application; copying each egress PSP stage, that is upstream from the egress PSP stage, to a right-adjacent PSP; unallocating a left-most PSP from the egress pipeline; and placing the unallocated PSP to a low power mode. [0024] A third aspect relates to a programmable network device, comprising: an elastic forwarding pipeline architecture, comprising: a plurality of pipeline stage processors (PSPs), the plurality of PSPs serially connected and partitioned into a first set of PSPs, a second set of flexibly allocated PSPs, and a third set of PSPs; a traffic manager (TM); and an input/output (I/O) selector coupled to the TM and to each PSP in the second set of flexibly allocated PSPs. [0025] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the first set of PSPs and a first PSP of the second set of flexibly allocated PSPs are dedicated for an ingress pipeline, and wherein the third set of PSPs and a last PSP of the second set of flexibly allocated PSPs are dedicated for an egress pipeline.

[0026] For the purpose of clarity, any one of the foregoing embodiments may be combined with any one or more of the other foregoing embodiments to create a new embodiment within the scope of the present disclosure.

[0027] These and other features will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0028] For a more complete understanding of this disclosure, reference is now made to the following brief description, taken in connection with the accompanying drawings and detailed description, wherein like reference numerals represent like parts.

[0029] FIG. 1 is an example of a Protocol-Independent Switch Architecture (PISA).

[0030] FIG. 2 illustrates an elastic forwarding pipeline for programmable switch chips according to an embodiment of the disclosure.

[0031] FIG. 3 illustrates the packet processing path of the elastic forwarding pipeline according to an embodiment of the disclosure.

[0032] FIG. 4 illustrates the packet processing path of the elastic forwarding pipeline according to an embodiment of the disclosure.

[0033] FIG. 5 illustrates the packet processing path of the elastic forwarding pipeline according to an embodiment of the disclosure.

[0034] FIG. 6 illustrates a process for inserting a new function into the logical ingress pipeline according to an embodiment of the disclosure.

[0035] FIG. 7 is a flowchart illustrating a process for processing a packet using an elastic forwarding pipeline architecture according to an embodiment of the disclosure. [0036] FIG. 8 is a schematic diagram of a network device according to an embodiment of the disclosure.

DETAILED DESCRIPTION

[0037] It should be understood at the outset that although an illustrative implementation of one or more embodiments are provided below, the disclosed systems and/or methods may be implemented using any number of techniques, whether currently known or in existence. The disclosure should in no way be limited to the illustrative implementations, drawings, and techniques illustrated below, including the exemplary designs and implementations illustrated and described herein, but may be modified within the scope of the appended claims along with their full scope of equivalents.

[0038] Current programmable chips built for the Protocol-Independent Switch Architecture (PISA) have a static/hard pipeline stage resource allocation for the ingress and egress, which is inflexible and inefficient. For example, if the resource on one side (i.e., either the ingress or egress) is not enough for a particular application, the mapping of the resources for the application fails, even when the other side has unused resources. Additionally, because all stages are chained together, even when some of the stages are unused, unnecessary power is consumed and the unused stages increase latency due to the data having to pass through all the unused stages. Further, in-service incremental updates such as, but not limited to, needing to move the logic stages are difficult to implement.

[0039] For instance, FIG. 1 is an example of a PISA 100. As shown, the PISA 100 includes a traffic manager (TM) 102 disposed between an ingress pipeline 104 and an egress pipeline 106. The ingress pipeline 104 and the egress pipeline 106 of FIG. 1 each include a front-end parser 108, a plurality of pipeline stage processors (PSPs) 110, and a queue/buffer 112. Although only two PSPs 110 are depicted in FIG. 1, the plurality of PSPs 110 may include additional PSPs 110. The front-end parser 108 is configured to receive, parse, and craft packets (a.k.a., data packets, network packets, etc.). The front-end parser 108 is configured to forward the packets to the PSP 110 in the first stage (e.g., the PSP 110 immediately adjacent to the front-end parser 108).

[0040] The PSP 110 in the first stage may or may not process the packets received from the front-end parser 108. In order to process the packets, each PSP 110 may include a memory 114, an arithmetic logic unit (ALU) 116, or other processing components. The ALU 116 carries out arithmetic and logic operations on the operands in computer instructions. The PSPs 110 may include other components in practical applications. [0041] The first PSP 110 forwards the packets to the PSP 110 in the second stage. The PSP 110 in the second stage may or may not process the packets received from the PSP 110 in the first stage. This process continues in succession until all of the PSPs 110 in subsequent stages have either processed the packets or forwarded the packets to the next PSP 110 without performing any processing. The last PSP 110 in sequential order forwards the packets to the queue/buffer 112. The queue/buffer 112 temporarily stores the packets until the packets are transmitted.

[0042] The TM 102 receives the packets from the queue/buffer 112 of the ingress pipeline 104 and forwards the packets to the front-end parser 108 of the egress pipeline 106. The TM 102 is configured to queue, replicate, and schedule the transmission of the packets. In some cases, the queue/buffer 112 is incorporated into, and forms part of, the TM 102.

[0043] Unfortunately, programmable network devices incorporating the PISA 100 of FIG. 1 use a static or “hard” allocation of the resources. That is, the PSPs 110 are organized in a series of sequential stages (e.g., first stage, second stage, etc.) within the ingress pipeline 104 and the egress pipeline 106. Because of the static configuration of the PSPs 110, reprogramming a programmable network device using the PISA 100 may fail. Take, for example, a PISA (e.g., PISA 100) having five PSPs 110 available in the ingress pipeline 104 and another five PSPs 110 available in the egress pipeline 106. When the P4 language used to reprogram the programmable network device calls for an ingress pipeline to have six PSPs in the ingress pipeline 104 and to have three PSPs 110 in the egress pipeline 106, the mapping fails because the ingress pipeline 104 only has five available PSPs 110. This failure occurs even though the egress pipeline 106 had two unused PSPs 110 in the design. Thus, the conventional allocation of PSPs 110 is inflexible and inefficient.

[0044] In addition, in the PISA 100 of FIG. 1, all of the PSPs 110 are chained together, even when the PSPs 110 of some of the stages are unused (e.g., do not perform any processing and simply forward the packet). This configuration consumes more power and introduces latency. Further, any in-service incremental update for the PISA 100 of FIG. 1 necessitates moving one or more of the PSPs 110, which is difficult and time consuming.

[0045] To address the above technical problems, disclosed herein is an elastic forwarding pipeline for programmable switch chips. The elastic forwarding pipeline permits any number of PSPs in a set of PSPs to be allocated to an ingress pipeline and/or an egress pipeline as needed as opposed to the fixed allocation of PSPs in the current static or hard pipeline. The elastic forwarding pipeline also permits unused PSPs to be bypassed and put in low-power mode, which reduces latency and saves energy. The elastic forwarding pipeline supports in-service incremental updates, which involves inserting and/or removing one or more PSPs, or functions associated with one or more PSPs. By using the elastic forwarding pipeline, network resources are better utilized and energy costs are reduced.

[0046] FIG. 2 illustrates an elastic forwarding pipeline 200 for a programmable network device according to an embodiment of the disclosure. As shown, the elastic forwarding pipeline 200 includes a plurality of PSPs 202 chained together. The PSPs 202 are similar to the PSPs 110 of FIG. 1. That is, the PSPs 202 are configured to process packets. The plurality of PSPs 202 may include n number of PSPs, where n is any positive integer. For example, the plurality of PSPs may include 10 PSPs, 16 PSPs, 24 PSPs, 32 PSPs, or any other number of PSPs. For illustrative purposes only, the below description assumes that the elastic forwarding pipeline 200 includes 32 PSPs (i.e., n = 32). In accordance with the disclosed embodiments, the plurality of PSPs is partitioned into 3 sections labeled as r, s, and I as shown in FIG. 2 (i.e., r+s+t = n). Each of the 3 sections may include any number of PSPs in practical applications. For example, r may include 6 PSPs, s may include 20 PSPs, and t may include 6 PSPs. Although r and I have the same number of PSPs in the given example, r and I may contain a different number of PSPs. [0047] In accordance with the disclosed embodiments, each of the PSPs 202 in section s have an extra side interface to one side of the TM/PSP input and/or output (EO) selector 204 (as shown by the double-sided arrows). The other side of the TM/PSP EO selector 204 interfaces with a TM 206 (as shown by the arrows). The TM 206 is configured to perform similar functions as that of the TM 102 in FIG. 1 (e.g., queue, replicate, and schedule the transmission of packets). The TM/PSP EO selector 204 is configured to receive an input from an upstream PSP and to provide an output to a downstream PSP (i.e., as depicted in FIG. 2, the TM/PSP I/O selector 204 receives an input from an ingress pipeline PSP to the left (i.e., upstream) of an egress pipeline PSP that receives an output from the TM/PSP I/O selector 204).

[0048] In accordance with the disclosed embodiments, at a minimum, the first (r+1) PSPs are dedicated for the ingress pipeline (i.e., the set of PSPs in r plus the initial PSP in s ), the last (I /) PSPs are dedicated for the egress pipeline (i.e., the set of PSPs in t plus the final PSP in s ), and the middle ( s-2 ) PSPs are flexibly allocated to either the ingress or the egress pipeline (or remain unassigned). Thus, the shortest ingress pipeline supported by the disclosed embodiments is r+1. When the actual logic ingress pipeline is shorter than r+1, unused PSPs are still kept in the ingress pipeline for packet pass-through. The longest ingress pipeline supported by the disclosed embodiments r+s-1 (i.e., the set of PSPs in r plus all the PSPs in s except the final PSP in s). [0049] The shortest egress pipeline supported by the disclosed embodiments is t+1. When the actual logic egress pipeline is shorterthan t+1, unused PSPs are still kept in the egress pipeline for packet pass-through. The longest egress pipeline supported by the disclosed embodiments is t+s-1 (i.e., the set of PSPs in t plus all the PSPs in s except the initial PSP in s ). At most, s-2 PSPs can be excluded from the logic pipeline (i.e., the ingress pipeline and the egress pipeline) and put into low power mode.

[0050] In an embodiment, the parameters r, s, and I (i.e., how many PSPs to assign to each partition) are decided by chip makers based on application statistics and the tradeoff between flexibility and cost.

[0051] As an example, FIG. 3 illustrates the packet processing path of the elastic forwarding pipeline 200 when the shortest ingress pipeline(r+7) and the shortest egress pipeline (t+1) are used. In the example, each of the PSPs in the ingress pipeline either process the packet or forward the packet without processing. At PSP 202i, the packet is received by the TM/PSP I/O selector 204 and routed to the TM 206. The TM 206 then routes the packet back to the TM/PSP I/O selector 204, which transmits the packet to PSP 202o of the egress pipeline. Each of the PSPs in the egress pipeline either process the packet or forward the packet without processing. In this example, the remaining s-2 PSPs are not utilized and are placed into low power mode to conserve energy.

[0052] As another example, FIG. 4 illustrates the packet processing path of the elastic forwarding pipeline 200 when the longest ingress pipeline (r+s-1) and the shortest egress pipeline (t+1) is used. As described above, each of the PSPs in the egress pipeline either process the packet or forward the packet without processing. At PSP 202i, the packet is received by the TM/PSP I/O selector 204 and routed to the TM 206. The TM 206 then routes the packet back to the TM/PSP I/O selector 204, which transmits the packet to PSP 202o of the egress pipeline. Each of the PSPs in the egress pipeline either process the packet or forward the packet without processing. In this example, all the PSPs in s are utilized.

[0053] As another example, FIG. 5 illustrates the packet processing path of the elastic forwarding pipeline 200 when the ingress pipeline includes a certain number of PSPs from s (e.g., r +4) and the egress pipeline (t+2) is used. In the example, each of the PSPs in the ingress pipeline either process the packet or forward the packet without processing. At PSP 202i, the packet is received by the TM/PSP I/O selector 204 and routed to the TM 206. The TM 206 then routes the packet back to the TM/PSP EO selector 204, which transmits the packet to PSP 202o of the egress pipeline. Each of the PSPs in the egress pipeline either process the packet or forward the packet without processing. In this example, the remaining PSPs in s (e.g., s- 6) are not utilized and are placed into low power mode to conserve energy.

[0054] FIG. 6 illustrates a process for inserting a new function X 602 into the logical ingress pipeline in accordance with an embodiment of the present disclosure. In the depicted embodiment, the logical ingress pipeline currently comprises PSP 604, PSP 606, and PSP 608. The PSP 604 and PSP 604 may be a part of r as described in FIG. 2. PSP 608 may be the initial PSP in s. PSP 610 is also part of s and is currently set to idle (i.e., not used and placed into low power mode to conserve energy).

[0055] In the initial configuration (depicted on the left in FIG. 6), PSP 604 is configured to perform function A on a packet. PSP 606 is configured to perform function B on the packet or on the output data of the PSP 604. PSP 608 is configured to perform function C on the packet or on the output data of the PSP 606. The output data of the PSP 608 is received by the TM/PSP I/O selector 204 and routed to the TM 206 as described in FIG. 2.

[0056] As shown in FIG. 6, a new function X 602 is to be inserted in between function A and function B. To insert the new function X 602, each ingress PSP downstream (i.e., to the right) of the new function X 602 is shifted to the immediately-adjacent downstream PSP. This process is referred to as stage migration. That is, each of the PSPs following the new function X 602 moves to the right in FIG. 6. For example, function B is moved from PSP 606 to PSP 608 and function C is moved from PSP 608 to PSP 610, which was previously idle. An I/O selector reconfiguration is performed that changes the output of PSP 608 to connect to PSP 610, and connects the TM/PSP I/O selector 204 to the output of PSP 610, thus making PSP 610 part of the logical ingress pipeline. PSP 606, which is now vacant due to the shift of function B to PSP 608, is then configured to perform new function X 602. The packet is then processed through the new logical pipeline comprising PSP 604, PSP 606, PSP 608, and PSP 610. Although FIG. 6 describes the logical ingress pipeline, a similar process can also be applied to a logical egress pipeline. Additionally, a similar process may be performed to remove a function from the logical ingress pipeline or egress pipeline (e.g., a function is removed from a PSP, functions downstream of the removed function are shifted to immediately-adjacent upstream PSPs, and the now unused PSP at the end of the egress pipeline is placed in low power mode to conserve energy). As described above, the disclosed embodiments can support in-situ incremental updates by stage migration and selector reconfiguration. In an embodiment, active ingress stages are left aligned, and active egress stages are right aligned to maximize the unused PSPs.

[0057] FIG. 7 is a method 700 of processing a packet using an elastic forwarding pipeline architecture (e.g., elastic forwarding pipeline 200 in FIG. 2) according to an embodiment of the disclosure. The method 700 may be implemented by a programmable network device in order to add, or remove, functions from either an ingress pipeline or an egress pipeline of the elastic forwarding pipeline.

[0058] In block 702, the programmable network device receives the packet. In an embodiment, the packet includes various headers or other instructions indicating how the packet should be processed or handled by the elastic forwarding pipeline architecture. In an embodiment, the instructions indicating how the packet should be processed or handled are received from an application (e.g., a mobile application). In an embodiment, the instructions indicating how the packet should be processed or handled are provided by both the packet and the application.

[0059] In block 704, the programmable network device, if needed, modifies a number of PSPs of an ingress pipeline and/or egress pipeline to process the packet according to the instructions. For instance, the programmable network device can expand (add more PSP stages) or contact (remove PSP stages) the ingress pipeline and/or egress pipeline to process the packet according to the instructions. For example, when the instructions for processing the packet call for more PSP stages than are currently allocated to the ingress pipeline, the programmable network device expands the ingress pipeline by adding one or more of the initial unallocated PSP from the expandable set of PSPs (i.e., set s in FIG. 2) to satisfy the instructions. Similarly, when the application requires more PSP stages than are currently allocated to the egress pipeline, the programmable network device expands the egress pipeline using the final unallocated PSP or PSPs from the expandable set of PSPs (i.e., set s in FIG. 2) to satisfy the instructions. The programmable network device can similarly remove one or more PSPs from the ingress or egress pipelines. As stated above, both the ingress pipeline and the egress pipeline, at a minimum, includes at least one PSP from the set of flexibly allocated PSPs. [0060] In block 706, the programmable network device maps the application requirements (e.g., the processing functions for each PSP) to the PSP pipeline. In an embodiment, the programmable network device may reprogram one or more PSPs previously not tasked with processing the packet and/or that was placed in a low power idle state in order to add a new stage to perform a task associated with processing the packet of the application.

[0061] In block 708, the programmable network device processes the packet using the ingress pipeline and the egress pipeline as expanded or contracted. As stated above, the programmable network device bypasses the unallocated PSPs in the set of flexibly allocated PSPs during packet processing via the TM/PSP I/O selector 204. [0062] As an optional step, as indicated by the dashed arrow, the programmable network device, in block 710, sets any unused PSPs to idle/low power mode to conserve energy. That is, any of the plurality of PSPs not forming the ingress pipeline or the egress pipeline may be placed in the low power idle state to conserve energy.

[0063] As another optional step, in block 712, the programmable network device may modify the PSP pipeline based on new instructions or requirements. For example, in an embodiment, the programmable network device receives a new ingress PSP stage processing requirement for the application; allocates a left-most unallocated PSP from the set of flexibly allocated PSPs to the ingress pipeline; copies each ingress PSP stage, that is downstream from an intended location of the new ingress PSP stage, to a right-adjacent PSP; and inserts the new ingress PSP stage in the intended location of the ingress pipeline. Similarly, the programmable network device can receive a new egress PSP stage processing requirement for the application; allocate a right-most unallocated PSP from the set of flexibly allocated PSPs to the egress pipeline; copy each egress PSP stage, that is upstream from an intended location of the new egress PSP stage, to a left-adjacent PSP; and insert the new egress PSP stage in the intended location of the egress pipeline. The programmable network device can also receive instructions to remove an ingress PSP stage for the application; copy each ingress PSP stage, that is downstream from the ingress PSP stage, to a left-adjacent PSP; unallocate a right-most PSP from the ingress pipeline; and place the unallocated PSP to a low power mode. Similarly, the programmable network device can receive instructions to remove an egress PSP stage for the application; copy each egress PSP stage, that is upstream from the egress PSP stage, to a right- adjacent PSP; unallocate a left-most PSP from the egress pipeline; and place the unallocated PSP to a low power mode. After the PSP pipeline is modified, the programmable network device process the packet through the updated pipeline.

[0064] FIG. 8 is a schematic diagram of a network device 800 (e. g. , a programmable network device). The network apparatus 800 is suitable for implementing the disclosed embodiments as described herein. The network device 800 comprises ingress ports/ingress means 810 and receiver units (Rx)/receiving means 820 for receiving data; a processor, logic unit, or central processing unit (CPU)/processing means 830 to process the data; transmitter units (Tx)/transmitting means 840 and egress ports/egress means 850 for transmitting the data; and a memory/memory means 860 for storing the data. The network device 800 may also comprise optical-to-electrical (OE) components and electrical-to-optical (EO) components coupled to the ingress ports/ingress means 810, the receiver units/receiving means 820, the transmitter units/transmitting means 840, and the egress ports/egress means 850 for egress or ingress of optical or electrical signals.

[0065] The processor/processing means 830 is implemented by hardware and software. The processor/processing means 830 may be implemented as one or more CPU chips, cores (e.g., as a multi-core processor), field-programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), and digital signal processors (DSPs). The processor/processing means 830 is in communication with the ingress ports/ingress means 810, receiver units/receiving means 820, transmitter units/transmitting means 840, egress ports/egress means 850, and memory/memory means 860. The processor/processing means 830 comprises an elastic forwarding pipeline architecture module 870. The elastic forwarding pipeline architecture module 870 is able to implement the methods disclosed herein. The inclusion of the elastic forwarding pipeline architecture module 870 therefore provides a substantial improvement to the functionality of the network device 800 and effects a transformation of the network device 800 to a different state. Alternatively, the elastic forwarding pipeline architecture module 870 is implemented as instructions stored in the memory/memory means 860 and executed by the processor/processing means 830.

[0066] The network device 800 may also include input and/or output (I/O) devices/I/O means 880 for communicating data to and from a user. The I/O devices I/O means 880 may include output devices such as a display for displaying video data, speakers for outputting audio data, etc. The I/O devices I/O means 880 may also include input devices, such as a keyboard, mouse, trackball, etc., and/or corresponding interfaces for interacting with such output devices. [0067] The memory/memory means 860 comprises one or more disks, tape drives, and solid- state drives and may be used as an over-flow data storage device, to store programs when such programs are selected for execution, and to store instructions and data that are read during program execution. The memory/memory means 860 may be volatile and/or non-volatile and may be read-only memory (ROM), random access memory (RAM), ternary content-addressable memory (TCAM), and/or static random-access memory (SRAM).

[0068] Accordingly, unlike current programmable chips that have static/hard pipeline stage resource allocation for ingress and egress pipelines, the disclosed embodiments offer flexibility elastic forwarding pipeline. The disclosed embodiments provide better flexibility, resource efficiency, and power efficiency. In addition, the disclosed embodiments support in-service incremental update. The disclosed embodiments offer a key innovation front on high performance/programmable networking chips for the next generation network devices such as router/switch/smart network interface controller (NIC). [0069] While several embodiments have been provided in the present disclosure, it may be understood that the disclosed systems and methods might be embodied in many other specific forms without departing from the spirit or scope of the present disclosure. The present examples are to be considered as illustrative and not restrictive, and the intention is not to be limited to the details given herein. For example, the various elements or components may be combined or integrated in another system or certain features may be omitted, or not implemented.

[0070] In addition, techniques, systems, subsystems, and methods described and illustrated in the various embodiments as discrete or separate may be combined or integrated with other systems, components, techniques, or methods without departing from the scope of the present disclosure. Other examples of changes, substitutions, and alterations are ascertainable by one skilled in the art and may be made without departing from the spirit and scope disclosed herein.

Claims

CLAIMS What is claimed is:

1. An elastic forwarding pipeline for a programmable network device, the elastic forwarding pipeline comprising: a plurality of pipeline stage processors (PSPs), the plurality of PSPs serially connected and partitioned into a first set of PSPs, a second set of flexibly allocated PSPs, and a third set of PSPs; a traffic manager (TM); and an input/output (I/O) selector coupled to the TM and to each PSP in the second set of flexibly allocated PSPs.

2. The elastic forwarding pipeline according to claim 1, wherein the first set of PSPs and a first PSP of the second set of flexibly allocated PSPs form an ingress pipeline.

3. The elastic forwarding pipeline for programmable switch chips according to any of claims 1-2, wherein the third set of PSPs and a last PSP of the second set of flexibly allocated PSPs form an egress pipeline.

4. The elastic forwarding pipeline for programmable switch chips according to any of claims 2-3, wherein the ingress pipeline can be extended to include any number of unallocated PSPs between the first PSP and the last PSP of the second set of flexibly allocated PSPs.

5. The elastic forwarding pipeline for programmable switch chips according to any of claims 2-3, wherein the egress pipeline can be extended to include any number of unallocated PSPs between the first PSP and the last PSP of the second set of flexibly allocated PSPs.

6. The elastic forwarding pipeline for programmable switch chips according to any of claims 1-5, wherein the I/O selector is configured to bypass unallocated PSPs between the first PSP and the last PSP of the second set of flexibly allocated PSPs.

7. The elastic forwarding pipeline for programmable switch chips according to any of claims 1-6, wherein unallocated PSPs between the first PSP and the last PSP of the second set of flexibly allocated PSPs are placed in low-power mode.

8. The elastic forwarding pipeline for programmable switch chips according to any of claims 1-7, wherein a number of PSPs included in the first set of PSPs, the second set of flexibly allocated PSPs, and the third set of PSPs are predetermined by a chip manufacturer based on application statistics.

9. The elastic forwarding pipeline for programmable switch chips according to any of claims 1-8, wherein the ingress pipeline and the egress pipeline can be reconfigured while the programmable switch chips are installed on a programmable network device using stage migration and I/O selector reconfiguration.

10. A method of processing a packet in an elastic forwarding pipeline of a programmable network device, comprising: receiving, by the programmable network device, requirements of an application for a pipeline stage processor (PSP) pipeline of the programmable network device; modifying, by the programmable network device, a number of PSPs of an ingress pipeline or an egress pipeline of the PSP pipeline using a set of flexibly allocated PSPs to satisfy the requirements; mapping, by the programmable network device, the requirements to the PSP pipeline; and processing, by the programmable network device, the packet associated with the application through the PSP pipeline.

11. The method of claim 10, wherein the ingress pipeline comprises at least one PSP from the set of flexibly allocated PSPs.

12. The method according to any of claims 10-11, wherein the egress pipeline comprises at least one PSP from the set of flexibly allocated PSPs.

13. The method according to any of claims 10-12, further comprising placing any unallocated PSPs in the set of flexibly allocated PSPs to a low power mode.

14. The method according to any of claims 10-13, wherein processing the packet associated with the application through the PSP pipeline comprises bypassing the unallocated PSPs in the set of flexibly allocated PSPs.

15. The method according to any of claims 10-14, further comprising: receiving a new ingress PSP stage processing requirement for the application; allocating a left-most unallocated PSP from the set of flexibly allocated PSPs to the ingress pipeline; copying each ingress PSP stage, that is downstream from an intended location of the new ingress PSP stage, to a right-adjacent PSP; and inserting the new ingress PSP stage in the intended location of the ingress pipeline.

16. The method according to any of claims 10-15, further comprising: receiving a new egress PSP stage processing requirement for the application; allocating a right-most unallocated PSP from the set of flexibly allocated PSPs to the egress pipeline; copying each egress PSP stage, that is upstream from an intended location of the new egress PSP stage, to a left-adjacent PSP; and inserting the new egress PSP stage in the intended location of the egress pipeline.

17. The method according to any of claims 10-16, further comprising: receiving instructions to remove an ingress PSP stage for the application; copying each ingress PSP stage, that is downstream from the ingress PSP stage, to a left-adjacent PSP; unallocating a right-most PSP from the ingress pipeline; and placing the unallocated PSP to a low power mode.

18. The method according to any of claims 10-17, further comprising: receiving instructions to remove an egress PSP stage for the application; copying each egress PSP stage, that is upstream from the egress PSP stage, to a right- adjacent PSP; unallocating a left-most PSP from the egress pipeline; and placing the unallocated PSP to a low power mode.

19. A programmable network device, comprising: an elastic forwarding pipeline architecture, comprising: a plurality of pipeline stage processors (PSPs), the plurality of PSPs serially connected and partitioned into a first set of PSPs, a second set of flexibly allocated PSPs, and a third set of PSPs; a traffic manager (TM); and an input/output (I/O) selector coupled to the TM and to each PSP in the second set of flexibly allocated PSPs.

20. The programmable network device of claim 19, wherein the first set of PSPs and a first PSP of the second set of flexibly allocated PSPs are dedicated for an ingress pipeline, and wherein the third set of PSPs and a last PSP of the second set of flexibly allocated PSPs are dedicated for an egress pipeline.