WO2022221044A1 - Expansion de longueur de préfixe dans des processeurs de paquets - Google Patents

Expansion de longueur de préfixe dans des processeurs de paquets Download PDF

Info

Publication number
WO2022221044A1
WO2022221044A1 PCT/US2022/022233 US2022022233W WO2022221044A1 WO 2022221044 A1 WO2022221044 A1 WO 2022221044A1 US 2022022233 W US2022022233 W US 2022022233W WO 2022221044 A1 WO2022221044 A1 WO 2022221044A1
Authority
WO
WIPO (PCT)
Prior art keywords
prefix
action
prefix length
length
expanded
Prior art date
Application number
PCT/US2022/022233
Other languages
English (en)
Inventor
Steven BALLS
Matthew Ian Ronald Williams
Abhishek Pandey
Daniel Thomas O'BRIEN
Original Assignee
Microsoft Technology Licensing, Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GBGB2105368.1A external-priority patent/GB202105368D0/en
Application filed by Microsoft Technology Licensing, Llc filed Critical Microsoft Technology Licensing, Llc
Priority to EP22718376.1A priority Critical patent/EP4324174A1/fr
Publication of WO2022221044A1 publication Critical patent/WO2022221044A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/54—Organization of routing tables
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/74—Address processing for routing
    • H04L45/745—Address table lookup; Address filtering
    • H04L45/748—Address table lookup; Address filtering using longest matching prefix
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/74—Address processing for routing
    • H04L45/745—Address table lookup; Address filtering
    • H04L45/7452—Multiple parallel or consecutive lookup operations

Definitions

  • Packet processors are designed to perform actions on large numbers of packets efficiently based on control information in each packet and action information stored in the packet processor.
  • Packet processors can include memory storing tables containing action entries that associate an address or range of destination addresses for incoming packets, with an action to be performed by the packet processor.
  • a lookup operation can be performed by the packet processor to match an address of the packet with the action entries stored in memory to find an associated action to perform on the packet.
  • Possible actions performed on packets include forwarding, dropping the packet, encrypting/decrypting the packet and others.
  • the action entries in the memory of a packet processor can be associated with a single address or a subnetwork designated by a subnetwork address, herein referred to as a prefix.
  • the existence of action entries in the table containing prefixes means there can be overlapping action entries. This leads to possible scenarios where an incoming packet can match to multiple table action entries and the packet processor has a process for selecting one action to perform.
  • Methods exist to configure a packet processor to select an appropriate table action entry for a packet in these overlap scenarios.
  • One such method is longest prefix matching, where the action entry associated with the longest prefix out of the matching entries is chosen. Longest prefix matching can be particularly advantageous for packet forwarding as it selects the most specific entry out of a plurality of possible matching entries.
  • a method to be performed by a packet processor in a communications network comprises retrieving from a memory of the packet processor, a first prefix length associated with a first lookup stage and a second prefix length associated with a second lookup stage.
  • the second prefix length is shorter than the first prefix length.
  • the packet processor can receive instructions from a control plane of the communications network to program an action entry for a destination subnet into the packet processor, the action entry having an action entry prefix denoting the subnet.
  • the length of the action entry prefix is compared to the first prefix length associated with first lookup stage and the second prefix length associated with the second lookup stage.
  • the second prefix length is selected as an expanded prefix length.
  • the first prefix length is selected as the expanded prefix length.
  • a plurality of expanded action entries is then generated with the selected expanded prefix length and stored in a match-action table of the lookup stage associated with the prefix length selected as the expanded prefix length.
  • FIG. l is a block diagram illustrating the operation of a packet processing system featuring control plane components and a packet processor with two lookup stages;
  • FIG. 2 is a schematic diagram of a packet processor showing action entries stored in lookup stages of a packet processor according to an example;
  • FIG. 3 is a schematic diagram of a packet processor showing expanded action entries in a lookup stage generated for a new action entry programmed to the packet processor according to an example;
  • FIG. 4 is a diagram of a packet processor illustrating a method of matching a packet address to a stored expanded action entry at a first lookup stage according to an example
  • FIG. 5 is a diagram of a packet processor illustrating a method of matching a packet address to a stored action entry at a second lookup stage according to an example
  • FIG. 6 is a diagram of a packet processor illustrating a method of updating a set of expanded action entries at a first lookup stage with a new entry
  • FIG. 7 is a flow chart illustrating a method performed by a packet processor according to an example.
  • a packet processor can attempt to match an address or other control information in a packet header to stored action entries in one or more match- action tables.
  • the one or more action tables can be stored in a memory of the packet processor. Access to these memory resources is required when performing a lookup for a packet.
  • a packet processor can store thousands of entries meaning the resource usage for lookup operations is not trivial.
  • a packet processor configured to perform a lookup operation over all the stored action entries whenever a packet arrives for processing would require only one matching operation to successfully match the packet address. However, this approach would consume a large amount of memory resources for each lookup operation.
  • DIR-24-8-BASIC splits the action entries into two tables.
  • the first table stores action entries for subnetworks with prefixes of 24- bits or shorter, and a second table that contains the entries for the remaining bits of the prefixes to provide finer grain action entries for more specific subnetworks.
  • This configuration was designed for internet routing where /24 subnetworks and shorter are most common. Starting the search from the /24 size and larger prefixes means the DIR-24- 8-BASIC is not a true longest prefix match configuration which can be a disadvantage in smaller networks.
  • the inventors have recognized that, in certain applications it is beneficial to perform lookups on different prefixes depending on the nature of the network that the packet processor is operating in and modify these prefix values to adapt to changes in network performance metrics.
  • the technology is tunable and enables better use of resources as a result of this tunability.
  • Embodiments described below outline a packet processing system with lookup stages that perform lookups of action entries of one prefix length. These prefixes can then be modified according to the performance needs of the network. The embodiments also perform a true longest prefix match and so can reduce the number of processing operations required compared to alternative implementations with initial lookups being performed at a more specific prefix length.
  • a lookup stage is a hardware and/or software element storing a table of action entries with a single prefix length. Each stored action entry describing an action to be performed by the packet processor on the packet. The lookup stage performs a lookup operation to match an incoming packet address to a stored action entry prefix from the table of action entries.
  • a lookup stage when a lookup stage has matched the packet address to an action entry the packet processor performs the action, described by the action entry, on the packet.
  • the packet processor performs the action, described by the action entry, on the packet.
  • FIG. 1 is a block diagram illustrating a packet processing system 100.
  • the packet processing system comprises a packet processor 112, and a control component 102 of a control plane or optionally a cloud control component 118 of the control plane. Either control component 102 provides instructions to the packet processor 112 through a connection 104.
  • the connection 104 is a wired or wireless connection.
  • the packet processor 112 is connected to a network and receives data packets at connection 106 and, in this embodiment, forwards them at a connection 114 to a destination 116.
  • the packet processor 112 contains a first lookup stage 108 showing 732 and a second lookup stage 110 with a label /24.
  • the look up stages each contain a match-action table that match an address of packets arriving at connection 106 to an action to be performed on the packets by the packet processor 112.
  • the /32 of the first lookup stage indicates that the match-action table used in the first lookup stage only matches packet addresses to entries with a 32-bit prefix.
  • the /24 of the second lookup stage indicates the second lookup stage only matches packet addresses with action entries with a 24-bit prefix.
  • the control component 102 or optionally cloud control component 118 provides the action entries to be stored in the match-action tables of the first lookup stage 108 and second lookup stage 110.
  • the control component 102 may provide an action entry with a prefix of a length that does not match the prefix length of entries stored in any of the lookup stages of packet processor 112. In this case the prefix lengths of the entries are expanded for storing in the nearest highest lookup stage.
  • the action that is performed is shown as a forwarding action of the packet to destination 116 through connection 114.
  • This is one of many possible actions applied to a packet by the packet processor 112.
  • there are two lookup stages a first and a second lookup stage with match-action table entries comprising 32-bit and 24-bit prefixes respectively.
  • more lookup stages are used, and/or different prefix lengths are used.
  • the second look up stage is associated with a shorter prefix length such as /12, so a greater proportion of the action entries are expanded and stored in the first lookup stage.
  • FIG. 2 is a block diagram illustrating a first lookup stage 204 and a second lookup stage 212.
  • Each lookup stage performs a lookup operation of an address of packets arriving at 202 against entries of an associated prefix length.
  • the first lookup stage 204 matches incoming packets to entries with prefixes of 32-bits during a lookup operation.
  • prefixes 32-bits during a lookup operation.
  • /32 is chosen as the prefix associated with the first lookup stage as, in IPv4 networks this is the longest and therefore most specific prefix length for an entry.
  • the packet processor 200 performs a true longest prefix match.
  • the first lookup stage performs a lookup operation 206 by comparing the address of packets entering at 202 to a prefix of a stored action entry in match action table 208.
  • match action table 208 there are currently no entries and any attempt to match 206 at the first lookup stage 204 leads to a miss in the lookup operation.
  • the packet information is propagated to the second lookup stage 212 through connection 210.
  • a second lookup operation 214 is performed on the packet arriving at connection 210.
  • the second lookup stage 212 stores only action entries with a prefix of 24-bits which is less specific than the prefixes of the first lookup stage 204.
  • the second lookup stage 212 will perform a lookup operation to match the address of the packet arriving at connection 210 to the prefix shown in table 216.
  • the packet processor 200 carries out the action described in the action entry of the table 216.
  • the action described in the action entry in table 216 is a forwarding action to forward via a connection X.
  • Many different actions may be performed by the packet processor 200 such as drop, encrypt, decrypt, inspect etc.
  • FIG. 3 is a block diagram illustrating a method of programming a new action entry 318 into a packet processor 300.
  • New entry 318 is received from a control component of a control plane or optionally a cloud control component and contains a prefix denoting a subnetwork.
  • a prefix length for the new entry 318 is 30 bits long as shown by the /30 notation.
  • the packet processor 300 contains a first lookup stage 304 that performs lookup operations on packets arriving at connection 302 to action entries 308 with a prefix length of 32-bits only.
  • the packet processor also contains a second lookup stage 312 that performs lookup operations on packets arriving at connection 310 to stored action entries with a prefix length of 24-bits only.
  • the new entry 318 with a prefix length of 30-bits therefore cannot be used in a lookup operation by either the first or the second lookup stage.
  • the packet processor modifies the prefix of the new action entry 318.
  • First an appropriate prefix length is selected from either the first lookup stage 304 or the second lookup stage 312. Selecting a shorter prefix length for entries is undesirable as it extends the addresses covered by the action entry beyond the designated range. Therefore, a longer prefix is chosen, in the example of FIG. 3 the larger prefix length is the 32-bit prefix length of the entries stored at the first lookup table 304. In embodiments the next longest prefix from the prefixes associated with the lookup stages to the new action entry 318 is selected. [0027] Modifying the new action entry to a longer prefix length comprises producing expanded action entries 308.
  • a plurality of expanded action entries are generated 308.
  • each /32 prefix at the first lookup stage 304 designates a smaller range of addresses than a /30 address range as in the new action entry 318.
  • the packet processor calculates a difference, d, between the longer prefix length and the length of the new entry prefix 318.
  • the difference, d shows how many extra bits are to be appended in the new action entry prefixes 308 to reach the longer prefix length.
  • Each of the 2 d expanded action entries 308 is then appended with a distinct sequence of bits of d length.
  • the values of the d bits generated provide the possible combinations of binary values of d bits.
  • the expanded action entries represent all of the addresses that were designated in the new action entry 318.
  • each of the four expanded action entries 308 is appended with a 2-bit value in a unique combination resulting in prefixes that comprise the new action entry 318 appended with the values 0, 1, 2, 3 and 4.
  • the expanded action entries 308 are stored in the selected lookup stage and associated with the same action as the new action entry 318.
  • the action information is to forward matched packets via port X. This is not a limiting example of an action as there are many possibilities of actions that are associable with a prefix such as dropping the packet, encryption etc.
  • FIG. 4 illustrates a packet processor 400, configured with a plurality of expanded action entries 412.
  • the packet processor is processing an incoming packet 402.
  • the incoming packet 402 contains an address value.
  • the incoming packet arrives at the packet processor at connection 404 and enters a first lookup stage 406.
  • the first lookup stage uses a plurality of action entries stored in table 412 to perform a lookup operation 408 on the incoming packet 402.
  • a successful lookup operation results in a matching action entry 410 of the plurality of stored action entries 412 and the associated action is performed on packet 402 by the packet processor 408.
  • the stored action entries 412 can result from the process described in FIG. 3.
  • the first lookup stage uses 32-bits and the second lookup stage uses 24 bits, in other embodiments different prefix lengths are used.
  • prefix lengths are chosen based on a network protocol used such as IPv4 or IPv6 or a private network protocol that is not compatible with other packet processing technologies.
  • the adaptability of the prefix lengths used provides improved useability of the packet processor for network operators.
  • extra lookup stages can be included after the second lookup stage to reduce the memory utilization per lookup operation.
  • the prefixes of the action entries in the table 412 of the first lookup stage 406 are 32-bits in length.
  • the lookup operation 408 results in a successful match 410 as the address of the packet 402 corresponds to a prefix of an action entry in the plurality of action entries 412 stored at the first lookup stage 406.
  • the action designated by the matched action entry 410 is then performed on the packet 402 by the packet processor 400.
  • the packet 402 has an address that matches the prefix of an action entry at the first lookup stage 406, and therefore an action is performed on packet 402.
  • the action performed on the packet 402, by the packet processor 400 is a forwarding action via X, but there are many other possible examples of actions.
  • FIG. 5 illustrates a packet processor equivalent to that of FIG. 4.
  • a packet 502 entering the packet processor 500 at a connection 504 has a different address.
  • the address of the packet undergoes a lookup operation at a first lookup stage 506 in the same way as previously described.
  • the address of packet 502 does not correspond to any of the action entry prefixes 512 stored at the first lookup stage and therefore the lookup operation 510 of the first lookup stage 506 results in a miss 508.
  • the packet 502 or in other embodiments only the address of packet 502, is transferred to a second lookup stage 516 through connection 514.
  • the second lookup stage 516 performs a lookup operation on the action entries that are stored at the second lookup stage 516.
  • the lengths of the prefixes of the action entries 520 stored at the second lookup stage 516 are shorter than those stored at the first lookup stage 506 to perform a longest prefix match operation.
  • the action entries 520 have prefix lengths of 24-bits, which is shorter than the prefix lengths associated with the action entries of the first lookup stage 512.
  • the lookup operation 518 is successful as an action entry 522, with a prefix that corresponds to the address of the packet 502, is stored at the second lookup stage 520.
  • the action that is associated with the action entry 522 is then performed on the packet 502 by the packet processor 500.
  • the action performed on the packet 502, by the packet processor 500 is a forwarding action via X.
  • FIG. 6 illustrates programming a new action entry 618 into a packet processor 600 where the new action entry 618 has a same prefix length as that associated with a lookup stage.
  • the packet processor 600 is equivalent to the packet processor of FIG. 3 containing a first lookup stage 604 associated with action entries of one prefix length, and a second lookup stage 612 associated with action entries of a shorter prefix length.
  • the first lookup stage stores action entries 608 with a prefix length of 32-bits for use in a lookup operation 606.
  • the second lookup stage 612 stores action entries 616 of a prefix length 24-bits for performing lookup operations 614.
  • FIG. 6 illustrates programming a new action entry 618 into a packet processor 600 where the new action entry 618 has a same prefix length as that associated with a lookup stage.
  • the packet processor 600 is equivalent to the packet processor of FIG. 3 containing a first lookup stage 604 associated with action entries of one prefix length, and a second lookup stage 612
  • a new entry 618 is to be programmed with a prefix length equal to that of the action entries of the first lookup stage 604.
  • the prefix length of the new action entry 618 is equal to the action entry prefix lengths used by any of the lookup stages, it is stored directly at the lookup stage without expansion.
  • the new action entry 618 with a /32 prefix is being programmed. This is equal in prefix length to the /32 entries associated with the first lookup stage 604. Therefore, the new action entry is stored directly into the table 608 without the expansion described in previous examples. The new action entry 618 has overwritten a previously stored action entry in the table 608 and there is now a new associated action with that prefix.
  • FIG. 7 is a flowchart that illustrates an example method performed by a packet processor such as that of FIG. 1.
  • the packet processor retrieves first and second prefix lengths.
  • the first and second prefix lengths are then associated with a first and second lookup stage respectively of the packet processor.
  • the first prefix length is the longest prefix length to provide a longest prefix match operation.
  • the prefix lengths are stored on a memory of the packet processor or retrieved from a control component of the network or from a control component in the cloud.
  • lookup stages there are two lookup stages; in alternative embodiments more lookup stages are used each with a different prefix length associated with them.
  • the prefix lengths associated with the lookup stages are modified by the packet processor in response to measured performance metrics. The modification is triggered by the packet processor or other control plane components in communication with the packet processor.
  • a non-exhaustive list of example performance metrics which are used is: amount of available memory, average number of look up operations, packet latency, and max throughput.
  • Other examples of metrics which are used are: predicted performance metrics, programmatic knowledge of expected changes to programmed routes.
  • the modification of the prefix lengths associated with the lookup stages comprises decreasing the prefix length of the second lookup stage to reduce the average number of lookup operations performed.
  • modification may be applied to increase the second prefix length to reduce the amount of memory used in each lookup operation.
  • the prefix lengths can also be chosen based on a protocol used in a connected communications network, examples include IPv4 and IPv6 and the skilled person will be aware that alternative protocols can be implemented.
  • the packet processor receives instructions to program a new action entry with a prefix denoting a subnetwork into the packet processor.
  • the instructions and new entry are received from a control plane, or from a local operator.
  • the control plane comprises a connected control component on the network such as a server or other computing device.
  • the control plane may be comprised of one or more cloud-based control components.
  • the action entry prefix is expanded, as described in FIG. 3.
  • a comparison is made to determine whether the second prefix length, associated with the second lookup stage, is longer than the length of the action entry prefix. When it is longer the packet processor moves onto block 708, if not then the packet processor moves on to block 710.
  • the action entry prefix is expanded to generate a plurality of expanded action entries with an expanded prefix length equal to the second prefix length.
  • the expanded entries are then stored at the second lookup stage.
  • the action entry prefix is expanded to generate a plurality of expanded action entries with an expanded prefix length equal to the first prefix length.
  • the expanded entries are then stored at the first lookup stage.
  • the lookup stages in this embodiment have been considered for the new action entry and it has been found that the action entry is longer than the prefix lengths of the first and the second lookup stages. In this event the action entry has been programmed in error. In various embodiments an error message is returned to the control plane component that provided the instructions to program the action entry. [0050] Alternatively, or in addition, the functionality described herein is performed, at least in part, by one or more hardware logic components.
  • illustrative types of hardware logic components include Field-programmable Gate Arrays (FPGAs), Application-specific Integrated Circuits (ASICs), Application-specific Standard Products (ASSPs), System-on-a-chip systems (SOCs), Complex Programmable Logic Devices (CPLDs).
  • FPGAs Field-programmable Gate Arrays
  • ASICs Application-specific Integrated Circuits
  • ASSPs Application-specific Standard Products
  • SOCs System-on-a-chip systems
  • CPLDs Complex Programmable Logic Devices
  • a method performed by a packet processor in a communications network comprising: retrieving from a memory of the packet processor, a first prefix length to associate with a first lookup stage and a second prefix length to associate with a second lookup stage, wherein the second prefix length is shorter than the first prefix length; receiving instructions from a control plane of the communications network, to program an action entry for a destination subnet into the packet processor, the action entry having an action entry prefix; comparing a length of the action entry prefix to the first prefix length associated with the first lookup stage and the second prefix length associated with the second lookup stage; in response to determining that the length of the action entry prefix is shorter than the second prefix length, selecting the second prefix length as an expanded prefix length; in response to determining that the length of the action entry prefix is longer than the second prefix length and shorter than the first prefix length, selecting the first prefix length as the expanded prefix length; generating a plurality of expanded action entries each with the selected expanded prefix
  • Clause B The method of clause A further comprising: in response to determining that the entry prefix length is equal to one of the first and the second prefix length: storing the action entry for the subnet directly into the match-action table of the lookup stage that uses the prefix length equal to the entry prefix length;
  • Clause C The method of clause A or B further comprising: receiving a packet at the packet processor; attempting to match an address of the packet with the action entries stored in the first lookup stage; and in response to a successful match, performing an action on the packet.
  • Clause D The method of clause C further comprising: attempting to match the destination address of the packet with the action entries stored in the second lookup stage; and in response to a successful match at the second lookup stage, performing an action on the packet.
  • Clause E The method of any of the previous clauses, further comprising a third lookup stage, wherein the third lookup stage is associated with a third prefix length shorter than the second prefix length.
  • Clause F The method of any of the preceding clauses wherein generating a plurality of expanded action entries further comprises: calculating a difference in length, d, between the expanded entry prefix length and the entry prefix length; and wherein the plurality of expanded action entries comprises 2d expanded action entries.
  • Clause G The method of clause F, wherein each of the expanded action entries comprises an expanded entry prefix, wherein the expanded entry prefix comprises an action entry prefix appended with d binary bits, and wherein the values of the d binary bits are different for each of the expanded action entries.
  • Clause H The method of any of the preceding clauses wherein the value of the first prefix length is one of 32 and 127 bits.
  • a packet processor in a communications network comprising: at least one processor in data communication with a control plane of the network; and a hardware storage device in data communication with the processor, the hardware storage device having instructions thereon that cause the processor to: retrieve a first prefix length to associate with a first lookup stage and a second prefix length to associate with a second lookup stage, wherein the second prefix length is shorter than the first prefix length; receive instructions from the control plane of the communications network, to program an action entry for a destination subnet into the packet processor, the action entry having an action entry prefix; compare the length of the action entry prefix to the first prefix length associated with the first lookup stage and the second prefix length associated with the second lookup stage; in response to determining that the length of the action entry prefix is shorter than the second prefix length, select the second prefix length as an expanded prefix length; in response to determining that the length of the action entry prefix is longer than the second prefix length and shorter than the first prefix length, select the first pre
  • Clause L The packet processor of claim K further comprising: in response to determining that the length of the action entry prefix is equal to one of the first and the second prefix length: store the action entry for the subnet directly into the match-action table of the lookup stage that uses the prefix length equal to the length of the action entry prefix;
  • Clause M The packet processor of clause K or L further comprising: receive a packet at the packet processor; perform a lookup at the first lookup stage to match an address of the packet with each of the action entries stored in the first lookup stage; and in response to a successful match at the first lookup stage, perform an action on the packet.
  • Clause N The packet processor of clause M further comprising: perform a lookup at the second lookup stage to match an address of the packet with each of the action entries stored in the second lookup stage; and in response to a successful match at the second lookup stage, perform an action on the packet.
  • Clause R The packet processor of any of the preceding clauses wherein the values of the first and second prefix length can be modified by a control plane of the communications network using at least one of latency and packet loss performance metrics.
  • a communications network comprising: a control plane communicatively coupled to a packet processor; and the packet processor comprising: at least one processor in data communication with the control plane of the communications network; and a hardware storage device in data communication with the processor, the hardware storage device having instructions thereon that cause the processor to: retrieve a first prefix length to associate with a first lookup stage and a second prefix length to associate with a second lookup stage, wherein the second prefix length is shorter than the first prefix length; receive instructions from the control plane of the communications network, to program an action entry for a destination subnet into the packet processor, the action entry having an action entry prefix; compare the length of the action entry prefix to the first prefix length associated with the first lookup stage and the second prefix length associated with the second lookup stage; in response to determining that the length of the action entry prefix is shorter than the second prefix length, select the second prefix length as an expanded prefix length; in response to determining that the length of the action entry prefix is longer than the
  • the methods described herein are performed, in some examples, by software in machine readable form on a tangible storage medium e.g. in the form of a computer program comprising computer program code means adapted to perform all the operations of one or more of the methods described herein when the program is run on a computer and where the computer program may be embodied on a computer readable medium.
  • the software is suitable for execution on a parallel processor or a serial processor such that the method operations may be carried out in any suitable order, or simultaneously.
  • Computer-readable media includes, for example, computer storage media such as memory and communications media.
  • Computer storage media such as memory, includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or the like.
  • Computer storage media includes, but is not limited to, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM), electronic erasable programmable read only memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital versatile disks (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that is used to store information for access by a computing device.
  • communication media embody computer readable instructions, data structures, program modules, or the like in a modulated data signal, such as a carrier wave, or other transport mechanism.
  • computer storage media does not include communication media. Therefore, a computer storage medium should not be interpreted to be a propagating signal per se.
  • a remote computer is able to store an example of the process described as software.
  • a local or terminal computer is able to access the remote computer and download a part or all of the software to run the program.
  • the local computer may download pieces of the software as needed or execute some software instructions at the local terminal and some at the remote computer (or computer network).
  • a dedicated circuit such as a digital signal processor (DSP), programmable logic array, or the like.
  • DSP digital signal processor

Abstract

Un procédé réalisé par un processeur de paquets consiste à récupérer une première longueur de préfixe pour un premier étage de consultation et une seconde longueur de préfixe plus courte pour un second étage de consultation. Le processeur de paquets peut recevoir des instructions pour programmer une entrée d'action. La longueur du préfixe d'entrée d'action est comparée au premier préfixe et à la seconde longueur de préfixe. S'il est déterminé que la longueur du préfixe d'entrée d'action est plus courte que la seconde longueur de préfixe, la seconde longueur de préfixe est sélectionnée en tant que longueur de préfixe expansée. S'il est déterminé que la longueur du préfixe d'entrée d'action est plus longue que la seconde longueur de préfixe et plus courte que la première longueur de préfixe, alors la première longueur de préfixe est sélectionnée en tant que longueur de préfixe expansée. Des entrées d'action expansées sont générées avec des préfixes expansés de la longueur de préfixe expansée et stockées au niveau de l'étage de consultation associé à la longueur de préfixe expansée.
PCT/US2022/022233 2021-04-15 2022-03-29 Expansion de longueur de préfixe dans des processeurs de paquets WO2022221044A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP22718376.1A EP4324174A1 (fr) 2021-04-15 2022-03-29 Expansion de longueur de préfixe dans des processeurs de paquets

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GBGB2105368.1A GB202105368D0 (en) 2021-04-15 2021-04-15 Prefix length expansion in packet processors
GB2105368.1 2021-04-15
US17/343,655 2021-06-09
US17/343,655 US11916789B2 (en) 2021-04-15 2021-06-09 Prefix length expansion in packet processors

Publications (1)

Publication Number Publication Date
WO2022221044A1 true WO2022221044A1 (fr) 2022-10-20

Family

ID=81384647

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2022/022233 WO2022221044A1 (fr) 2021-04-15 2022-03-29 Expansion de longueur de préfixe dans des processeurs de paquets

Country Status (2)

Country Link
EP (1) EP4324174A1 (fr)
WO (1) WO2022221044A1 (fr)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6011795A (en) * 1997-03-20 2000-01-04 Washington University Method and apparatus for fast hierarchical address lookup using controlled expansion of prefixes
WO2019173410A1 (fr) * 2018-03-06 2019-09-12 Barefoot Networks, Inc. Appariement de préfixe le plus long en chaîne dans un commutateur programmable

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6011795A (en) * 1997-03-20 2000-01-04 Washington University Method and apparatus for fast hierarchical address lookup using controlled expansion of prefixes
WO2019173410A1 (fr) * 2018-03-06 2019-09-12 Barefoot Networks, Inc. Appariement de préfixe le plus long en chaîne dans un commutateur programmable

Also Published As

Publication number Publication date
EP4324174A1 (fr) 2024-02-21

Similar Documents

Publication Publication Date Title
EP3035613B1 (fr) Routage ccn utilisant des tables de hachage assisté par un matériel informatique
US7650429B2 (en) Preventing aliasing of compressed keys across multiple hash tables
WO2014000670A1 (fr) Protocole internet et consultation ethernet via un arbre haché unifié
EP3280104B1 (fr) Recherche de routage ip
CN107547407B (zh) 报文传输方法、装置和实现装置
WO2015090179A1 (fr) Équilibrage de niveau trie pour la consultation d'adresses réseau
US9135833B2 (en) Process for selecting compressed key bits for collision resolution in hash lookup table
CN106789859B (zh) 报文匹配方法及装置
WO2006063217A1 (fr) Memoire adressable par le contenu masquable
US20230041395A1 (en) Method and Device for Processing Routing Table Entries
US11916789B2 (en) Prefix length expansion in packet processors
CN112187636A (zh) Ecmp路由的存储方法及装置
EP4324174A1 (fr) Expansion de longueur de préfixe dans des processeurs de paquets
CN113824814B (zh) 一种转发表的地址匹配方法、装置、网络设备及介质
US11063870B2 (en) Selective route download traffic sampling
EP3319279B1 (fr) Recherche de routage de préfixe ip
CN113949662B (zh) 一种报文转发方法、装置、网络设备及存储介质
EP2947839B1 (fr) Procédé et appareil d'envoi d'une requête pour un contenu
US11606296B2 (en) Longest-prefix matching dynamic allocation in communications network
CN116633686B (zh) 一种安全网关自适应访问控制的方法、装置及电子设备
CN107547406B (zh) 分布式evpn网关组网中建立fib表的方法和装置
CN116471094A (zh) 基于ram和tcam实现ipsg的方法、装置、电子设备及存储介质
EP4278583A1 (fr) Affectation dynamique de correspondance de préfixe le plus long dans un réseau de communication
CN115665066A (zh) 一种扩展mac地址表容量的方法、设备及介质
CN114866471A (zh) 路由查找方法、装置及设备

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22718376

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2022718376

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2022718376

Country of ref document: EP

Effective date: 20231115