WO2022219727A1 - 情報処理システム、情報処理装置、サーバ装置、プログラム、リコンフィグラブルデバイス、又は方法 - Google Patents

情報処理システム、情報処理装置、サーバ装置、プログラム、リコンフィグラブルデバイス、又は方法 Download PDF

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Publication number
WO2022219727A1
WO2022219727A1 PCT/JP2021/015354 JP2021015354W WO2022219727A1 WO 2022219727 A1 WO2022219727 A1 WO 2022219727A1 JP 2021015354 W JP2021015354 W JP 2021015354W WO 2022219727 A1 WO2022219727 A1 WO 2022219727A1
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Prior art keywords
information
resource
fpga
user
shell
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PCT/JP2021/015354
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English (en)
French (fr)
Japanese (ja)
Inventor
エリック駿 福田
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Chiptip Technology
Chiptip Technology KK
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Chiptip Technology
Chiptip Technology KK
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Priority to JP2023514231A priority Critical patent/JP7611613B2/ja
Priority to CN202180099351.0A priority patent/CN117529706A/zh
Priority to EP21936929.5A priority patent/EP4325359A4/en
Priority to PCT/JP2021/015354 priority patent/WO2022219727A1/ja
Priority to US18/555,242 priority patent/US20240193121A1/en
Publication of WO2022219727A1 publication Critical patent/WO2022219727A1/ja
Anticipated expiration legal-status Critical
Priority to JP2024220990A priority patent/JP2025041718A/ja
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
    • G06F15/7875—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS for multiple contexts
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4411—Configuring for operating with peripheral devices; Loading of device drivers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45558—Hypervisor-specific management and integration aspects

Definitions

  • the technology disclosed in this application relates to an information processing system, information processing device, server device, reconfigurable device, program, or method.
  • various embodiments of the present invention provide an information processing system, an information processing device, a server device, a program, a reconfigurable device, or a method in order to solve the above problems.
  • One embodiment of the present application includes: an acquisition unit that acquires information indicating a first resource from a user; an identifying unit that identifies a first reconfigurable device corresponding to the information indicating the first resource; an instruction unit that instructs the first reconfigurable device to write a first partition shell corresponding to the information indicating the first resource;
  • Another embodiment of the present application includes: the system, obtaining information indicative of the first resource from the user; identifying a first reconfigurable device corresponding to the information indicating the first resource; instructing the first reconfigurable device to write a first partition shell corresponding to the information indicating the first resource; how to run.
  • Another embodiment of the present application includes: the system, means for obtaining information indicative of the first resource from the user; means for identifying a first reconfigurable device corresponding to the information indicating the first resource; means for instructing the first reconfigurable device to write a first partition shell corresponding to the information indicating the first resource; A program to operate as
  • reconfigurable devices can be used more appropriately.
  • FIG. 1 is a block diagram of an example showing the relationship between a system according to one embodiment and a reconfigurable device.
  • FIG. 2 is an example block diagram illustrating the relationship between a system and a reconfigurable device according to one embodiment.
  • FIG. 3 is a block diagram illustrating the functionality of the system according to one embodiment.
  • FIG. 4 is a diagram illustrating an example processing flow of a system according to an embodiment.
  • FIG. 5 is a diagram illustrating an example data format for a system according to one embodiment.
  • FIG. 6 is a diagram illustrating an example data format for a system according to one embodiment.
  • FIG. 7 is a diagram illustrating an example data format for a system according to one embodiment.
  • FIG. 8 is a diagram illustrating an example processing flow of a system according to an embodiment.
  • FIG. 1 is a block diagram of an example showing the relationship between a system according to one embodiment and a reconfigurable device.
  • FIG. 2 is an example block diagram illustrating the relationship between a system and
  • FIG. 9 is a diagram illustrating an example data format for a system according to one embodiment.
  • FIG. 10 is a block diagram illustrating the functionality of the system according to one embodiment.
  • FIG. 11 is a block diagram illustrating the functionality of the system according to one embodiment.
  • FIG. 12 is a diagram illustrating part of the processing of an example system according to one embodiment.
  • FIG. 13 is a diagram illustrating part of the processing of an example system according to one embodiment.
  • FIG. 14 is a diagram illustrating part of the processing of an example system according to one embodiment.
  • FIG. 15 is a diagram illustrating part of the processing of an example system according to one embodiment.
  • FIG. 16 is a diagram illustrating part of the processing of an example system according to one embodiment.
  • FIG. 17 is a diagram illustrating part of the processing of an example system according to one embodiment.
  • FIG. 18 is a diagram illustrating part of the processing of an example system according to one embodiment.
  • FIG. 19 is a diagram illustrating part of the processing of an example system according to one embodiment.
  • FIG. 20 is a diagram illustrating part of the processing of an example system according to one embodiment.
  • FIG. 21 is a diagram illustrating part of the processing of an example system according to an embodiment.
  • FIG. 22 is a block diagram illustrating the functionality of the system according to one embodiment.
  • FIG. 23 is a diagram illustrating an example processing flow of a system according to an embodiment.
  • FIG. 24 is a block diagram showing an example configuration of a system according to an embodiment.
  • rewritable circuits relate to rewritable circuits.
  • an example of the present technology may be used with an information processing device including a circuit that is not rewritable.
  • a rewritable circuit is also called a programmable logic device, etc., but in this document, it is called a reconfigurable device (Reconfigurable Logic Device) including these.
  • non-rewritable circuits are sometimes referred to as instruction decoding schemes, von Neumann devices, and the like, but in this document, they are collectively referred to as Program Variable Devices.
  • Reconfigurable devices are, for example, PAL (Programmable Array Logic), PLA (Programmable Logic Array), GAL (Generic Array Logic), CPLD (Complex Programmable Logic Device), FPGA (Field Programmable Gate Array), CGRA (Coarse-Grained Reconfigurable Array), etc.
  • FPGAs are mainly used as reconfigurable devices, but it goes without saying that they can be applied to other reconfigurable devices instead of such FPGAs.
  • partial reconfiguration that is, a function that allows independent writing of multiple regions (for example, PR regions) in one programmable logic device, requires processing for each region, which will be described later. It may be possible.
  • writing independently of each other means that while processing is being performed in one area in one programmable logic device, writing is possible in another area in the one programmable logic device that is different from the one area. May contain functions.
  • the term "information processing device” is used as a generic term for reconfigurable devices and programmable devices.
  • first through fourth systems are inventions independent of each other, in the following explanations of the second through fourth systems, the same terms as those of the first system may be explained due to circumstances unique to each system. The description is omitted except in some cases.
  • Example of First System The system of this example relates to a system that provides a user with hardware resources in which a hypervisor shell and a partition shell including a communication function are written before an application is written by the user. Such a system has the advantage of being able to appropriately provide the hardware resources of the reconfigurable device to the user.
  • the system of this example may consist of one or more information processing devices.
  • Such one or more information processors may comprise one or more FPGAs and/or one or more programmable devices.
  • system of this example may be connected to one or more FPGAs.
  • FPGAs field-programmable gate arrays
  • Figure 1 shows an example in which the system of this example is connected to one or more FPGAs.
  • the system (001) of this example is connected to FPGA1 (0021) to FPGA4 (0024).
  • Such connection may be made by Ethernet or by a bus such as PCIExpress.
  • the system of this example may be connected only to one or more FPGAs as a computing function to execute the user's application.
  • the hardware resource that performs functions other than the computational function of executing the user's application may be connected to the programmable device.
  • system of this example may be connected to one or more FPGAs and may also be connected to one or more programmable devices.
  • the system of this example has the advantage of being able to manage distributed processing, including programmable devices, in addition to managing FPGAs.
  • One or more FPGAs may be installed in the same facility as the system of this example, or may be installed in a different facility. Also, the specific location of installation of one or more FPGAs may be of any kind. For example, one or more FPGAs may be installed inside a building (indoor) or outside the building (outdoor). IoT devices such as sensors may operate inside and/or outside buildings, and these may be implemented by FPGAs.
  • a network may be wired, wireless, or a mixture thereof.
  • FIG. 2 shows a situation in which the system of this example is connected to FPGAs and programmable devices via a network (000).
  • This figure shows a configuration example in which a plurality of FPGAs and programmable devices are included in the FPGA group (002).
  • CPU1 and CPU2 are described to indicate the programmable device, and for the sake of convenience these are also shown as part of the FPGA group.
  • the FPGA group (003) includes an information processing device including a plurality of FPGAs and functions of an FPGA writer.
  • Such an FPGA writer may be capable of both writing bitstreams to the FPGA group (003) and bitstream writing to the FPGA group (002).
  • the network within these FPGA groups (002) and (003) may be a bus, Ethernet, or the like.
  • the system of this example, the one or more FPGAs described above, and/or the one or more programmable devices described above may be information processing devices on the cloud.
  • the system of this example may include a database section containing FPGA information, and a management section for managing the information in the database section.
  • FIG. 3 illustrates an example of such functionality.
  • the management unit has a function of managing processing.
  • processing may include, for example, the function of providing information, the function of receiving information, the function of transmitting information, and/or the function of receiving information.
  • Information to be provided, accepted, transmitted, and received may be the same or different.
  • the management unit may have a function of providing information to users.
  • the system of this example has the advantage of providing information to the user and enabling the user to make meaningful decisions.
  • the management unit may have a function of receiving information input by the user.
  • the system of this example has the advantage of being able to use the information received from the user.
  • the management unit may have a function of transmitting information to the FPGA.
  • the system of this example has the advantage of being able to influence the FPGA with information sent to the FPGA.
  • the management unit may have a function of receiving information from the FPGA.
  • the system of this example has the advantage of being able to manage the status of the FPGA based on the information received from the FPGA. Details of these will be described later.
  • the database section has a function of storing information about the FPGA.
  • the database may store one or more resource information, described below.
  • the database unit may store other information. Since the system of this example has a database unit, there is an advantage that the information of the FPGA managed by the system of this example can be used.
  • the preparation phase may be a phase that occurs when a new FPGA is connected to the system. Such cases include, for example, the case of adding an FPGA or changing a conventional FPGA. Changing a conventional FPGA may include changing the configuration within the conventional FPGA.
  • the operational phase may be a phase for which the preparatory phase has ended.
  • step one the system of this example and the FPGA may be connected so as to enable signal communication.
  • Such connections may be wired or wireless and may allow communication of signals.
  • Such connections include, but are not limited to, when a new FPGA is added, when the physical configuration of the FPGA is changed due to repairs, etc.
  • connection may include connecting FPGAs via a network, and connecting FPGAs and information processing devices including other CPUs via a network.
  • step 2 The example system may support the process of writing a hypervisor shell to an attached FPGA.
  • a well-known technique may be used as the technique itself for writing to the FPGA.
  • the writing of the hypervisor shell can be done automatically by the system of this example, or it can be done manually.
  • the hypervisor shell can be written in any programming language.
  • the hypervisor shell if written, may be converted to a bitstream and written to the FPGA using known techniques.
  • the writing means may be, for example, technology through JTAG or USB.
  • the hypervisor shell that is written may correspond to the type and function of the target FPGA.
  • the hypervisor shell need only provide communication functions with the management unit to the FPGA by being written into the FPGA, and does not need to have all the functions of the hypervisor shell described later. Writing the hypervisor shell in this step allows the example system to communicate with the FPGA on which the hypervisor shell is written.
  • the example system may assist in registering information about physically connected FPGAs in a database.
  • the system of this example has the advantage of being able to use the information of the FPGA via the information held by the database.
  • the database may or may not use a database management system as long as it can store the information described later. If there is a data model on which the database is based, it may be of various types such as hierarchical, network, relational, and object data models, and the type is not limited. Hardware resources that implement such databases may be dedicated devices, general-purpose devices, or various information processing devices such as clouds and servers.
  • the system of this example When using a database, the system of this example only needs to be able to access the database.
  • the system of this example may have a database, or the system of this example may not have a database. In the latter case, it is sufficient if the system of this example can be directly or indirectly connected to the database via a network or the like.
  • the database may store information that actually identifies one FPGA and information about the functions that the FPGA has (sometimes referred to as "resource information" in this document) in association with each other.
  • Resource information includes, for example, information such as the type of reconfigurable device, attributes related to arithmetic devices, attributes related to storage devices, and/or attributes related to communication devices.
  • Attributes associated with a computing device may include the type of computing device, the number of computing devices such as the number of cells, the capabilities of the computing device such as the number of clock frequencies, and/or the power used by the computing device.
  • Arithmetic devices may include, for example, logic elements (LEs), logic cells (LCs), and/or LUTs (Look Up Tables).
  • the attributes related to the storage device may include the type of storage device, the capacity of the storage device, the read/write speed of the storage device, and/or the power used by the storage device.
  • the storage device may be, for example, an on-chip storage device within the reconfigurable device, or may be another storage device installed outside the reconfigurable device.
  • the communication device related attributes may include internal communication device related attributes and/or external communication device related attributes.
  • the attribute related to the internal communication device may be communication information related to the inside of the FPGA. Attributes associated with the external communication device may include network bandwidth and/or band speed of communication with the outside, and the like.
  • one FPGA may include one or more PR regions.
  • a PR region is a section whose circuit configuration can be changed independently.
  • the FPGA may be able to perform one or more independent operations with partial reconfiguration or one or more independent operations without partial reconfiguration. may be possible. Since they are independent, for example, when one FPGA includes PR region A and PR region B, PR region A and PR region B may operate independently with respect to circuit rewriting and circuit execution. Therefore, it may be possible to rewrite PR region B while PR region A is running.
  • one resource information in this document may be one unit that can be used by the user as a hardware resource. Therefore, if the FPGA is not managed in PR region units, one resource information may be one FPGA, but the FPGA is managed in PR region units and is a hardware resource that can be used for each PR region. If there is, one resource information can be one PR region in one FPGA.
  • the database described above may store the resource information described above in association with each of one or more PR regions contained within one FPGA.
  • one FPGA may be divided into two PR regions, PR regions A and B, or four PR regions, PR regions A to D.
  • resource information for each PR region is also different. Therefore, resource information may be stored in association with a specific PR region in a certain division method.
  • Fig. 5 is an example of logically arranging the information held by the database in which information on FPGA resources is registered.
  • FPGAID indicates an ID assigned to the FPGA actually connected to the system of this example. Since the resource information may have divisions as described above, the resource information may be stored in association with each FPGA ID.
  • FIG. 6 is another example of logically arranging the information held by the database in which the FPGA resource information is registered.
  • This figure shows an example in which a plurality of PR regions are set for one FPGA. For example, two PR regions are set for FPGAID 001, and two PR 3 PR regions are set for . Resource information is set for each PR region. This is because each PR region may have the same resources or different resources. Especially in the latter case, there is an advantage that resource information corresponding to each PR region can be set.
  • FIG. 7 is another example of logically arranging the information held by the database in which the FPGA resource information is registered.
  • This figure shows a case where there are a plurality of PR region division methods for one FPGA.
  • PR region division method 1 divides the PR region into two
  • division method 2 divides the PR region into four. It is set as a method of separation.
  • each PR region may have the same resources or different resources, so resource information for each PR region is associated with information specifying each PR region. may be stored.
  • the database may store information specifying the type of FPGA in association with information specifying each actual FPGA.
  • the type of FPGA is because the user needs the type of target FPGA when programming VHDL, which is a hardware description language (HDL), Verilog, or a high-level synthesis language such as C, or when generating a bitstream. .
  • VHDL hardware description language
  • Verilog Verilog
  • C high-level synthesis language
  • the database may also store information indicating whether or not each PR region is in use, in association with the corresponding PR region. There is an advantage that it is possible to manage whether or not the corresponding PR region is being used by the user by using the information indicating whether or not it is in use.
  • the database may associate and store information indicating the PR region being used and information indicating the user using the PR region. In this case, there is an advantage that users can be managed when the PR region is used.
  • the database may store information related to the user associated with the information indicating the user.
  • Information related to the user includes information that identifies the user in the real world, such as the user's address and email address, the user's ID, the password corresponding to the ID, and/or information related to the service that the user uses, etc.
  • the service information may include information about courses of service that the user has paid for and/or information about options that the user may subscribe to, and/or the like.
  • the database may be associated with each FPGA and store information related to licenses related to each FPGA.
  • the database may store information indicating whether or not each FPGA has the required license.
  • the database may also store information associated with each FPGA indicating the type of license required for each FPGA. By storing such license information, there is an advantage that it is possible to verify whether or not a license is required when using each FPGA and the type of license.
  • the license may be a license for each type of FPGA, calculation function, storage function, and/or communication function. This is because the license may differ depending on the type of FPGA, calculation function, storage function, and/or communication function.
  • licenses may also be storable for different licenses, such as low-end, high-end, special-purpose, and so on.
  • the license may be a license for one FPGA or a package license for multiple FPGAs, depending on the nature of the license.
  • the database may have information related to licenses possessed by such users in association with the above-described information indicating users.
  • it may include information specifying the presence and/or type of license possessed by the user. In this case, there is an advantage that information indicating what kind of FPGA the user has a license to use can be generated or verified.
  • the database may also store physical information about the FPGA in association with the information indicating the FPGA.
  • Physical information about the FPGA may include, for example, geographic information where the FPGA is located.
  • the physical information about the FPGA is, for example, the latitude and longitude where the FPGA is installed, the name of the facility where the FPGA is installed, the name of the facility manager who manages the FPGA, and/or the name of the facility where the FPGA is managed. management level information of the facility where the facility is located, and so on. Such information can be useful as reference information for consideration of security and incident response capabilities regarding the place where the FPGA is installed and management.
  • the database may consist of a single database or multiple databases for all connectable FPGAs.
  • the latter may be managed separately, for example, into a database for FPGAs to which partition shells have been written and a database for FPGAs to which partition shells have not been written. In the latter case, there is an advantage that quick access is possible when the amount of written FPGA is small.
  • Such resource information about FPGA may be manually registered in the database by a person, or may be recorded and registered in the database as information corresponding to FPGA.
  • a flavor may be a template of virtual hardware. Flavor is a term used in OpenStack, which is middleware for virtualization, but it may be similar functions in other virtualization middleware. Flavors may be displayed on a display device provided by the example system.
  • a flavor may include one or more resource information for one or more FPGAs.
  • a piece of resource information may include associated device name, PR shell, PR region, and/or device information.
  • a PR shell is a shell that manages a PR region, and may refer to the same thing as a partition shell in this document. Displaying the flavors has the advantage that the user can use the resource information to select resource information suitable for the circuit to be written.
  • the resource information includes information such as the type of reconfigurable device, attributes related to arithmetic devices, attributes related to storage devices, and/or attributes related to communication devices. There is an advantage that you can select the one that is suitable for
  • Fig. 9 is an example of flavors.
  • the device name is FPGA1
  • the PR shell is 1 (displayed as PRS1)
  • the PR region is displayed as PR1.
  • a shell capable of managing two PR regions corresponds as a PR shell
  • the two PR regions are displayed as PR1 and PR2, respectively.
  • the flavor may include information indicating a plurality of PR region setting methods for one physical device.
  • FPGA4 may be divided into two PR regions or four PR regions. In the former, the names PR1 and PR2 are assigned to the two PR regions, and PRS2 corresponds to the shell that manages them.
  • names PR1 to PR4 are assigned to four PR regions, and PRS4 corresponds to a shell that manages them.
  • the example system may be capable of managing any number of PR regions.
  • the system of the present example can manage and include within flavors combinations of the number of PR regions that can be split.
  • the database may store one or more division methods associated with one FPGA device so that such a display can be presented.
  • the flavor may include the type of FPGA associated with the information indicating one FPGA as one element of the resource information as described above.
  • the user has the advantage of being able to select desired resource information, including the type of FPGA.
  • a flavor may also include a PR region as one element of resource information as described above.
  • application bitstreams written into FPGAs may be generated depending on the type of FPGA and/or the PR region.
  • a program written in a hardware description language or high-level synthesis language for rewriting an FPGA has the advantage of being able to use information about the FPGA type and/or PR region when it is compiled and a bitstream is generated. .
  • the program for rewriting the FPGA may require the type of FPGA and/or the PR region at the time of compilation, and may require a considerable amount of time such as several hours for compilation. If the type of FPGA and/or the PR region related to the compiled program for the FPGA used in this example is different from the type of FPGA and/or the PR region related to the hardware resources related to the resource information provided by the system of this example, newly It has the advantage of avoiding the issue of requiring compilation.
  • the resource information presented by the flavor may or may not have a one-to-one relationship with the resource information in the real world.
  • the former indicates that the resource information presented by the flavor actually exists.
  • the flavor can also present two pieces of the same information.
  • the latter may have a one-to-many relationship between the resource information presented by the flavor and the resource information in the real world.
  • the flavor means presenting one such resource information ⁇ . In this case, since the resource information is the same, there is an advantage that the display area can be effectively used.
  • the flavor may display both of the above.
  • the resource information presented by the flavor may display one of the relationships between the resource information in the real world and the resource information in the real world, and may separately present a different element as the other.
  • the different elements include the number of hardware resources related to the actual resource information, the installation location where the hardware resources related to the actual resource information are installed, and the number of hardware resources related to the actual resource information. It may be the distance from the system to the place where the ware resource is installed, and so on. Here, the distance may be a physical distance, which will be described later, or a distance related to information communication.
  • the flavor may include and present all resource information provided by the database, regardless of whether the device is usable by the user or not.
  • the user can understand what kind of hardware resources the database has. For example, there is an advantage that the user can understand whether there are more than a predetermined number of hardware resources including certain resource information or less than a predetermined number.
  • the flavor may include and present one or more pieces of resource information for which a user is writable, regardless of the specific user. That is, flavors may present resource information other than resource information that is in use. In this case, since resource information already in use is not displayed, there is an advantage that resource information can be easily selected. In this case, additionally, the resource information currently used by the user who selects the resource information may be displayed. In this case, there is an advantage that new resource information can be selected while referring to the resource information currently used by the user who selects the resource information.
  • the flavor may include and present one or more pieces of resource information available to a specific user who selects the flavor.
  • the user may have available resource information determined in advance based on the presence/absence and type of license possessed by the user, the membership course and rules of the system of this example, and one or more resources available to the user. Information only may be presented. Also in this case, the resource information currently used by the user who selects the resource information may be displayed. In this case, there is an advantage that new resource information can be selected while referring to the resource information currently used by the user who selects the resource information.
  • a flavor may be one or more resources available to a specific user who selects the flavor, and one or more resource information available to the specific user if certain conditions are met. Multiple resource information may be included and presented.
  • the specific conditions include, for example, acquiring a new license, changing the membership course of the system of this example, and/or acquiring options for membership of the system of this example. may contain. These particular conditions may also be presented in association with resource information available if each condition is met. In this case, there is an advantage that the user can understand what conditions must be satisfied to select the corresponding resource information.
  • the flavor may include and present physical information about the FPGA.
  • the user has the advantage of being able to make a selection considering the physical information of the FPGA.
  • Physical information about the FPGA may include, for example, geographical information where the FPGA is installed. Also, the physical information about the FPGA is, for example, the latitude and longitude where the FPGA is installed, the name of the facility where the FPGA is installed, the name of the facility manager who manages the FPGA, and/or the name of the facility where the FPGA is managed. management level information of the facility where the facility is located, and so on. If such information is displayed in association with physical information corresponding to resource information, it may be advantageous as reference information for consideration of security and incident response capabilities regarding the place where FPGA is installed and management. .
  • physical information about FPGAs may include information indicating the distance between FPGAs.
  • the distance between FPGAs may be a physical distance or a distance related to information communication.
  • the former may be the Euclidean distance
  • its measurement method may be a straight line distance between FPGAs or a distance along a communication network between FPGAs.
  • the distance related to information communication which is the latter, may be obtained by using the number of hops during communication between FPGAs or the amount of network bandwidth. In this case, there is an advantage that the distance can be specified based on the communication status.
  • the distance between the above-mentioned FPGAs may be the distance between the two FPGAs if there are two FPGAs, and the distance between the two FPGAs for three or more FPGAs.
  • It may be the total distance or the maximum distance when information is transmitted between three or more FPGAs.
  • the distance between the FPGAs described above may be such that information indicating the distance between the selected plurality of FPGAs is calculated and displayed for the selected plurality of resource information. In this case the selection may be provisional.
  • the distance between devices may be displayed using a two-dimensional or three-dimensional graph.
  • a graph may be displayed such that each node of the graph is positioned at a position corresponding to the distance between devices calculated above.
  • the flavor may correspond to the type and/or number of PR regions that can be provided by a partition shell prepared in advance for the FPGA, for PR regions that can be provided by the user for one FPGA.
  • the flavor is the resource information in the case of PR region 2 and / or PR and resource information in the case of region 4.
  • the flavor is provided when the partition shell is written for the PR region that has not been written even for the FPGA to which the partition shell has been written. It may contain multiple possible patterns. For example, in one FPGA in which a partition shell (first partition shell) for providing two PR regions is written, if one PR region (first PR region) has already been written, the partition shells are hierarchically If not provided, the flavor may be provided with the first PR region already written (even if a partition shell different from the first partition shell that can provide the number and type of multiple PR regions for such FPGA can be provided). If the first PR region and the first partition shell were not deleted, only one remaining PR region (second PR region) could be provided. However, when a partition shell (second partition shell) is written in such a second PR region, one or more resource information may be provided to the extent that such second partition shell can provide.
  • the flavors are expressed in tabular form, but they may be displayed to the user in this manner, and the flavors may be displayed to the user in various manners without being limited to this manner.
  • step 2 the user selects one or more pieces of resource information from the flavors presented by the system of the present example, and the system of the present example displays the selected resource information corresponding to the resource information selected by the user. Or acquire information that specifies a plurality of pieces of resource information.
  • the flavor of the system of this example presents resource information corresponding to resource information in the physical hardware resource on a one-to-one basis, corresponding to the resource information selected by the user, the user may acquire information identifying a hardware resource that corresponds one-to-one with the resource information selected by .
  • the system of this example can A hardware resource identification process may be performed to identify one of the hardware resources.
  • the hardware resource identification process may be executed from various viewpoints.
  • the hardware resource identification process may use information about the user and/or information about the hardware resource used by the user.
  • information related to the user information related to the user's membership and/or information related to the user's membership period may be used.
  • the system of this example may use the length of the user's membership period to identify hardware resources. For example, the system of this example may perform a process of allocating one of the hardware resources for long-term use when the length of the remaining membership period of the user is equal to or longer than a predetermined period. In this case, there is an advantage that the administrator of the system of this example can efficiently perform maintenance of hardware resources. Also, for example, the system of this example may identify hardware resources using the length of the remaining membership period of the user and the hardware replacement schedule.
  • the system may not allocate anything shorter than a predetermined period until the hardware resource is replaced.
  • the system of this example targets the hardware resource that is longer than the first predetermined period until the next replacement time of the hardware resource.
  • the hardware resources may be determined. In this case, there is an advantage that the maintenance of hardware resources can be efficiently performed when the user's membership period is not extended.
  • Information related to the membership period may include the remaining period during which hardware resources can be used, and/or the total or continuous period from when the user joined the membership of the system of this example.
  • the information related to the user's membership may include information related to the member's course or status.
  • the example system may process allocating one of a given hardware resource if the user's membership course is a given and/or membership status is a given.
  • Such predetermined hardware resources may have higher hardware resource stability and robustness than other hardware resources. In this case, there is an advantage that higher quality hardware resources can be used when the user is a specific member or a predetermined course.
  • information relating to the member's course or rank may be selected by the user when using the system of this example. For example, it may be obtained through a contract to the effect of using a certain amount of resource information.
  • information related to hardware resources used by the user may include one or more hardware resources being used by the user at the time of the above selection.
  • 1) the FPGA that contains one or more hardware resources that the user is currently using, and the 2) hardware resources within the same local area network or bus as one or more hardware resources currently being utilized by the user; and/or 3) one or more hardware resources currently being utilized by the user. May include hardware resources and short distances.
  • the identity of the local area network or bus may be of any hierarchy as long as it can reduce the processing for communicating over the network.
  • 2) above may be a virtual local network.
  • the physical distance is not necessarily shorter than the predetermined distance and the distance related to information communication is not necessarily shorter than the predetermined distance, there is an advantage of high security.
  • the distance may be the physical distance described above or the distance related to information communication.
  • the hardware resources that are currently being used by the user and one or more hardware resources that are short in distance are selected. It has the advantage of helping to provide hardware resources for more efficient communication.
  • step 3 the example system verifies the availability of one or more hardware resources corresponding to the one or more resource information selected by the user. That is, the system of this example attempts to write the partition shell corresponding to the resource information to the FPGA device, which is the hardware resource corresponding to the resource information.
  • a bit stream may be written for such writing, and the method of transmitting information may be writing using TAG or writing using USB, and there is no limitation to the mode. Also, a known technique may be used as the writing technique itself to the FPGA.
  • the system of this example displays that the resource information selected by the user cannot be selected, such as failure to write the partition shell. , may be displayed to prompt the user to select new resource information.
  • the partition shell may be the same as the partition shell described later, or it may be different.
  • the partition shell only needs to have a function to assist the user in using the hardware resources in the FPGA in which the partition shell is written, and does not need to have all the functions that the partition shell has, which will be described later.
  • step 4 When the system of this example succeeds in writing the partition shell, it registers information about the successfully written resource information in the database.
  • the system of this example may feed back to the user information about resource information that has been successfully written.
  • resource information may be displayed on a display device, emailed to the user, or stored in a user-accessible predetermined location.
  • Information about such resource information may include information specifying the hardware resource in which the partition shell was actually written, and the information specifying the hardware resource may be information specifying a specific reconfigurable device. may contain.
  • information on such resource information includes information specifying the type of FPGA, attributes related to arithmetic devices, attributes related to storage devices, attributes related to communication devices, PR regions, and/or locations on the network. may contain.
  • the information specifying the location on the network may be, for example, an IP address for an FPGA, and an IP address or port number for a PR region within the FPGA.
  • the user may be able to access the written PR region using this information.
  • the user writes a program, which is an application that the user intends to use in the FPGA and has been converted into a bitstream by compilation, to the corresponding FPGA using such information.
  • the system of this example may assist in writing such user-provided bitstreams to corresponding FPGAs using the above information.
  • it may be written via USB (JTAG), it may be written via Ethernet, or it may be written via PCIe.
  • the system of this example first selects the resource information by the user, and if it cannot be selected by trying to write the PR shell
  • system of this example may perform processing for managing the user's member registration at the stage before step 1 of the operation stage.
  • the system of this example may have functions for managing user registration, correction of user membership information, and the like.
  • User registration may be a process in which the system of this example acquires the above-described information related to the user.
  • the example system presents user-selectable course and/or service options to the user, and the user selects a course and/or service option from among the presented course and/or service options.
  • the system of this example may acquire oriented information about the reconfigurable device used by the user and store it in association with information identifying the user.
  • the oriented information about the reconfigurable device is, for example, the type, the attribute about the computing device, the attribute about the storage device, and/or the attribute about the communication device, etc. about the reconfigurable device that the user plans to use. may contain information about This is because if there is a specific type of reconfigurable device that the user normally uses, it is assumed that the user is familiar with that type of reconfigurable device. This is because there is a high possibility that they are reconfigurable devices of the same type, and using such information may improve convenience. Similarly, if attributes related to computing devices, attributes related to storage devices, and/or attributes related to communication devices are in line with user preferences, user convenience may be improved. It's for.
  • the above steps may be directly input by the user to the system of this example.
  • the system of the present example includes a user terminal utilized by the user, the above steps may interact with the user in the system of the present example, and the system of the present example directly displays to the user, The example system may obtain user input directly.
  • step 1 information including the flavor may be transmitted from the system of this example to the user terminal, and the information including the flavor may be displayed on the user terminal.
  • step 2 the resource information selected in the user terminal may be sent from the user terminal to the example system, and such resource information may be received in the example system.
  • step 3 the system of the present example may check the availability of hardware resources corresponding to such resource information.
  • Step 4 above may be registered in the database by the system of this example.
  • the reconfigurable device in which the partition shell in step 3 is written is part of the system of this example. It may be external to the system of this example. Also, the database registered in step 4 may be a part of the system of this example or may be external to the system of this example.
  • the second system may relate to a reconfigurable device.
  • the second system may be a reconfigurable device itself that implements the functions described below as functions written into the FPGA, bits that implement the functions described below when written into the reconfigurable device. It may be a stream, or a program written in an HDL description language that is converted into such a bitstream by compilation.
  • an FPGA will be mainly used in the following description, but a reconfigurable device can also be used instead of the FPGA.
  • Functionality written into the system's functional FPGA may include functionality handled by the hypervisor shell (hypervisor shell functionality) and/or functionality handled by the partition shell (partition shell functionality). That is, the FPGA after such functionality is written may comprise a hypervisor shell portion including hypervisor shell functionality and/or a partition shell portion including partition shell functionality, as described below.
  • FIG. 10 illustrates such functions and example functions that these functions may provide.
  • One hypervisor shell may be associated with one FPGA. Such a hypervisor shell may be written within such an FPGA. Also, one partition shell may be associated with one FPGA. So, for example, a single FPGA may have a single partition shell even though there may be multiple PR regions, and such partition shell may be written within such a single FPGA.
  • the hypervisor shell may be determined according to information such as the type of FPGA to be written, attributes related to arithmetic devices, attributes related to storage devices, and/or attributes related to communication devices.
  • the partition shell includes the type of FPGA to be written, attributes related to arithmetic units, attributes related to storage units, attributes related to communication units, the number of PR regions, attributes related to arithmetic units in PR regions, and storage units in PR regions. and/or attributes of the communication device in the PR region.
  • the database related to the system of this example stores hypervisor shells associated with information such as FPGA types, attributes related to arithmetic devices, attributes related to storage devices, and/or attributes related to communication devices. You can In this case, as will be described later, the system of this example acquires the type and/or function of the FPGA, and has the advantage of being able to identify and use the corresponding hypervisor shell according to the type and/or function of the FPGA. . Furthermore, the database related to the system of this example is associated with information such as the type of FPGA, attributes related to arithmetic devices, attributes related to storage devices, attributes related to communication devices, and/or the number of PR regions. A partition shell may be stored.
  • the system of this example obtains the type of FPGA, the number of functions and/or PR regions, and depending on the type of FPGA, the number of functions and/or PR regions, the corresponding partition shell
  • the hypervisor shell and partition shell may have different functions.
  • the hypervisor shell and the partition shell may contain the same functions.
  • the timing of writing to the FPGA may be the same within a predetermined range for the hypervisor shell and the partition shell, or may be different.
  • the former may include, for example, a case where the partition shell is written immediately after the hypervisor shell is written, and so on.
  • different times may mean that the hypervisor shell is written during FPGA registration and the partition shell is written at the stage when the user writes the application data (or just before the user writes the application data).
  • the partition shell may be written once, then the partition shell is deleted, and the partition shell is written again.
  • the hypervisor shell portion may include functions for communicating with the management portion, communicating with external devices, providing communication functions to the partition shell, write-related functions, and/or initialization. If the hypervisor shell has some or all of these functions, there is an advantage that the convenience of the corresponding functions of the reconfigurable device, which can be written to execute programs, is improved.
  • Communication with the management department may include the function of responding to requests from the management department. For example, when a management department requests an inquiry about the status of a specific PR region, the status of the specific PR region may be answered.
  • the PR region status may include, for example, information such as "unwritten” or "written", or information such as "in use” or “not in use”.
  • the FPGA has the function of a hypervisor shell and can communicate with the management unit, the management unit has the advantage of being able to obtain information about the status of the FPGA from an FPGA that differs from a normal CPU.
  • Communication with an external device may include the function of transmitting information to and/or receiving information from an external device.
  • the external device may be, for example, a storage medium.
  • the hypervisor shell part may provide an interface to external devices.
  • the external device may provide an interface for communication with an external storage device by a partition shell, which will be described later.
  • the provision of communication functions to the partition shell may include support when the PR region in the FPGA communicates.
  • a PR region within an FPGA communicates with another PR region within the same FPGA as its own PR region, and/or when communicating with another device within an FPGA different from its own PR region, information may be sent.
  • the communication function of the partition shell may then set and/or change the destination of such information as needed.
  • the hypervisor shell may include a table of communication destination relationships (also referred to herein as a "communication destination table”) for providing communication functions to the partition shell.
  • This communication destination table contains destinations within the application used by the user (also referred to as "user destinations” in this document), PR regions that are processing entities within the FPGA, and/or calculation entities outside the FPGA.
  • node destinations (sometimes referred to in this document as "node destinations"), and . If the hypervisor shell has such a relationship between the user destination and the node destination, the user destination used by the user in the application is set to the node destination provided by the system according to the present document, and information is transmitted. There is an advantage that the user can build an application without worrying about the fact that the calculation subject of the FPGA is different.
  • the hypervisor shell part may have write-related functions.
  • Write-related functions may include partition shell write functions.
  • the hypervisor shell may have a function of writing the partition shell obtained from the management unit into the FPGA to which the hypervisor shell belongs or a function of supporting the writing.
  • the writing support function may be used by obtaining a code having a writing function from the management unit. If the hypervisor shell has write-related functions, there is an advantage that the administrator or user does not need to manually write the partition shell, and the burden is reduced.
  • the write-related functions of the hypervisor shell may have functions related to user authority.
  • a user's authority function may include a function of checking the authority of the PR region to which the user writes.
  • the PR region that the user writes to may include the user's program and thus the compiled bitstream, or information indicating where such bitstream is written, that is written to a PR region that the user is not authorized to.
  • the hypervisor shell unit to be written may have a function to check whether the user has write authority for the PR region to be written before performing the process of writing the received bitstream.
  • Such a function has the advantage of preventing the writing of bitstreams that constitute an application related to such a user to a PR region for which the user does not have write permission, intentionally or by mistake.
  • writing-related functions of the hypervisor shell part include functions related to user authority, for example, the following processing may be performed.
  • the hypervisor shell receives, via the network, information including the first bitstream that implements the first application associated with the first user at the time of writing (step 1).
  • the hypervisor shell portion in response to receiving information containing such first bitstream, identifies from the information containing such first bitstream a first PR region to which such first bitstream is written. and information specifying the first application (step 2).
  • the hypervisor shell unit transmits information including information specifying the first application and information specifying the first PR region to be written to the management unit (step 3).
  • the management unit uses the information identifying the first application and the information identifying the first PR region in response to receiving the information including the information identifying the first application and the information identifying the first PR region. Then, it is determined whether or not the first application has the authority to write to the first PR region (step 4).
  • the management unit determines that the authority exists, the management unit transmits permission to execute writing to the hypervisor shell unit. not convey permission to perform writes (step 5). In the latter, disallowance to perform writes may be conveyed.
  • information specifying the first application instead of the information specifying the first application, information specifying the user who gave the instruction to write the first application may be used.
  • the information identifying the first application is used to identify the first user who executes the first application and/or the instruction to write the first application, and the first user assigned to the first user.
  • Hardware resource information may be used to determine whether such first user has write permission in the first PR region. The above is just an example, and if information identifying the first user is included in the information including the first bitstream acquired by the hypervisor shell unit, such information is used and transmitted to the management unit, It may be determined whether such first user has write privileges in the first PR region.
  • the hypervisor shell writes a bitstream. Transmitting information including the bitstream to the config memory in the FPGA, obtaining information identifying the PR region to be written from the information including the bitstream, and information including the bitstream in the config memory may be written into the PR region corresponding to information identifying such PR region.
  • the hypervisor shell initialization function may include a memory function and/or communication function initialization function related to the FPGA to which the hypervisor shell belongs.
  • the initialization function may include the function of returning to an unused state. Initialization has the advantage of preventing malfunction.
  • Initializing the storage function may include, for example, returning the information in the storage function to an initial state. In this case, there is an advantage that a state in which meaningless information is stored can be avoided.
  • the initialization of the communication function includes, for example, processing such as deleting the FIFO queue in the communication function and resetting the information in the middle of the bus handshake sequence to return to the initial state. good. In this case, there is an advantage that an intermediate stage of communication can be eliminated.
  • the hypervisor shell executes the initialization, so even if the initialization function is not included in the execution mechanism of the user's application, the distributed processing of the system of this example can prevent the application from malfunctioning. It has the advantage of being able to reduce
  • the initialization may be performed at various timings. For example, in response to the partition shell being written as described above, storage and/or communication functions utilized by such partition shell may be initialized. Writing the partition shell has the advantage that it can be initialized before the application is used because the user is scheduled to write the application later. However, initialization may require time, which may delay the writing of the user's application. Also, in response to the writing of a user's application being executed, storage and/or communication functions utilized by such application may be initialized. Writing an application has the advantage that it can be initialized before the application is used because the user is planning to use the application later. However, initialization may require time, and in this case, the user's use of the application may be delayed.
  • the storage function and/or communication function related to the PR region related to the user may be initialized.
  • the storage function and/or communication function related to the PR region related to the user may be initialized. For example, in response to termination of a user's membership course or option, storage and/or communication functions associated with the PR region for such user may be initialized.
  • the Administration Department will monitor the course and options of each user's membership and/or the termination time of the PR region used by such user, and in response to the arrival of these termination times, the Administration Department will Information identifying the PR region to be used may be used to communicate with the hypervisor shell of the FPGA to which the PR region belongs to initialize storage and/or communication functions associated with the PR region.
  • the hypervisor shell part may initialize storage and/or communication functions for the corresponding PR region in response to such communication from the management part.
  • the partition shell part has a function to support functions in the PR region. For example, it may manage clock frequency functions, storage functions, and/or communication functions used by functions within the PR region. If the partition shell has some or all of these functions, it has the advantage of increasing the convenience of the corresponding functions in the PR regions supported by the partition shell.
  • the partition shell part may manage the clock frequency functions used by the functions within the PR region.
  • the partition shell part may be responsible for supplying clock frequency signals to the PR regions.
  • the partition shell part may have the function of generating one or more clock frequency signals to supply the PR region.
  • the partition shell may be capable of generating different clock frequency signals.
  • the clock frequencies generated by the partition shell may be those available to the circuitry within the PR region.
  • the user has the advantage of being able to use the clock frequency signal in the circuit within the PR region without having to prepare it himself.
  • the partition shell when the partition shell generates a plurality of different clock frequency signals, it is possible to select a clock frequency signal suitable for the circuit written in the PR region, and the width of the selection of the clock frequency signal that can be used by the circuit is It has the advantage of spreading. For example, if the circuit into which the reconfigurable device is written is simple, a higher clock frequency signal is set, and if the circuit is more complicated, a lower clock frequency signal is set. has the advantage of being able to choose
  • the partition shell section may supply one or more clock frequency signals to one PR region.
  • the partition shell may supply different clock frequency signals to the same or different circuits written within one PR region.
  • the clock frequency signal corresponding to each circuit There are benefits available.
  • the clock frequency signal used by the circuit may be determined in advance by the user who determines the circuit to be written.
  • the system of this example supports an environment in which the user can specify the clock frequencies available to the circuit in an environment where the user programs the circuit in a hardware description language or a high-level synthesis language. You can Also, when it is desired to supply different clock frequency signals to a plurality of identical or different circuits within one PR region, the system of this example provides an environment in which the user programs circuits using a hardware description language or a high-level synthesis language. may support an environment in which the available clock frequencies can be specified for each of the same or different circuits.
  • the support of an environment in which a clock frequency signal can be specified is, for example, for one or more circuits that are the same or different, a process of displaying one or more clock frequency signals available for each circuit, a clock frequency selected by a user It may include storing the signal in association with the circuit of interest and/or writing the connection relationship between such associated circuit and the clock frequency signal at the time of writing in the PR region.
  • the partition shell part may have a function to manage the correspondence between the storage functions used by the arithmetic functions in the PR region and the storage functions used by the FPGA to which the PR region belongs. Management of such correspondence has the advantage of reducing the risk of interfering with memory-related processing of other PR regions. For example, when the memory used by the arithmetic function in the PR region has an address of 000 to 999, and the address corresponds to 20000 to 20999 of the storage functions used by the FPGA to which the PR region belongs. , the partition shell may have a table showing such a correspondence relationship, and the partition shell uses this table to identify the PR region to which the PR region belongs corresponding to the specific address of the memory used by the arithmetic function in the PR region. It may help to use the memory corresponding to the memory function that the FPGA uses.
  • the storage function used by the FPGA may be a storage device installed within the FPGA or an external storage device accessible by the FPGA.
  • the partition shell part has a function to manage the correspondence relationship between the information specifying the communication channel used by the communication function in the PR region and the information specifying the communication channel with the outside of the FPGA to which the PR region belongs. may have Management of such correspondence has the advantage of reducing the risk of interfering with communication-related processing of other PR regions. For example, for communication based on a communication channel used by a certain PR region, the communication information may be passed to the hypervisor shell with information indicating that it is based on the PR region.
  • the partition shell part may be hierarchically provided within the PR region.
  • partition shells for example, providing another partition shell within the PR region managed by the partition shell.
  • first 1/2 PR region the remaining 1/2 PR region
  • second 1/2 PR region the partition shell section (first partition shell section) in which two PR regions have already been set has already been written, and the first 1/2 PR region is in use. Therefore, a partition shell part ( By writing the second partition shell part) and allowing the user to use the first 1/4 PR region, there is an advantage that efficient use is possible.
  • the partition shell part may eventually communicate with the hierarchically provided lower layer partition shell part as described above.
  • the partition shell part may support circuits in the PR region managed by the lower partition shell via communication functions and/or storage functions managed by the lower partition shell.
  • the third system is an example of a system that supports distributed processing using FPGAs.
  • the system of this example may have a JOB manager function, a resource manager function, and a TASK manager function.
  • the JOB manager and resource manager functions may be implemented on programmable devices.
  • the TASK manager functionality may be implemented as functionality on the reconfigurable device.
  • an FPGA will be mainly used in the following description, but a reconfigurable device can also be used instead of the FPGA.
  • the hypervisor shell and/or the partition shell may or may not be written in the FPGA. As in the latter, even if the hypervisor shell and/or partition shell are not written, distributed processing may still be performed by writing the bitstream as follows.
  • JOB manager has the function of managing JOBs.
  • a JOB may be a JOB defined in advance by a programmer as a single unit, or a unit defined by a programmer further subdivided by a separate JOB management technology for distributed processing, or a JOB defined by a programmer. It may be a collection of a plurality of groups.
  • JOB When JOB is executed on an FPGA, it can be a program converted by a programmer into a bitstream.
  • JOB When JOB is executed on a program variable device, it may be in a form that can be executed on hardware, such as a compiled version of a program programmed by a programmer or a version converted into machine language.
  • a JOB may be managed using information that can identify the job, such as a JOB ID that can uniquely identify the JOB. Therefore, the JOB manager may have a database that associates and stores information specifying JOBs and JOBs that are actually executed.
  • the JOB Manager may perform data flow analysis on JOBs and determine the order of JOBs to be processed according to the data flow. This order may be an order determined by data flow analysis using information on the input data and output data of each JOB.
  • the JOB manager may manage TASKs, which are granular processing below JOB.
  • management by the JOB manager includes a process of decomposing one JOB into one or more TASKs, a process of acquiring information about the processing status of TASKs executed in hardware resources, and one or more of the decomposed TASKs.
  • Information about the TASK processing status includes, for example, initialization for TASK, start of TASK execution, timer management for TASK execution, processing for processing abnormalities in TASK, processing for ending TASK, and the like. OK.
  • Termination processing may include, for example, the ability to receive TASK termination reports from TASK.
  • the instruction regarding execution may include an instruction corresponding to the processing status described above.
  • the resource manager has the function of managing hardware resources for one or more TASKs that make up a JOB.
  • a resource manager may comprise a database of the aforementioned resource information associated with hardware resources and manage the hardware resources.
  • the resource manager may associate information (such as an ID) that identifies one or more TASKs that make up one JOB with the hardware resources in which the TASKs are written, and store them in the database.
  • information such as an ID
  • Such an ID may be attached to each bitstream.
  • such an ID may be, for example, simply explained in a program language, with one ID assigned to something like one function. Therefore, various input information (arguments) may be given when executing a function, and one function whose output results may change depending on such arguments may be associated with one ID.
  • the input information resource manager uses such a database to determine whether the information specifying the TASK has been written to the hardware resource, and if it has been written, it uses the written circuit, and if it has not been written, If so, it may be executed after newly written. Such association has the advantage of reducing unnecessary writing.
  • One TASK may be assigned to one FPGA as described above, or one TASK may be assigned to one PR region in one FPGA.
  • the management function of the resource manager may include the function of providing hardware resources for TASK.
  • the resource manager may select hardware resources corresponding to TASK and notify the JOB manager.
  • the resource manager may acquire information on TASK from the JOB manager when selecting hardware resources.
  • the information related to TASK may include the resource information described above. It may include information such as related attributes.
  • the resource manager may select, from within a database of resource information, hardware resources that correspond to information pertaining to TASK, ie, those that have hardware resources capable of executing TASK.
  • the selection may be any hardware resource capable of executing TASK.
  • functional information such as attributes related to computing devices, attributes related to storage devices, and/or attributes related to communication devices are functions of information related to TASK Anything that includes
  • the Resource Manager may communicate to the JOB Manager information identifying the actual hardware resources corresponding to the selected resource information.
  • the physical ID of the reconfigurable device being written to, the network location such as an IP address identifying such device, and/or the IP address or port number identifying the PR region being written to. location on the FPGA or network, etc., may be conveyed to the JOB Manager. Also, in the database, the fact that such a TASK has been assigned may be stored in association with information specifying the assigned hardware resource.
  • the resource manager may sequentially process the following three steps in selecting those having hardware resources that can execute TASK. If the following steps are performed, there is an advantage that more time can be saved.
  • Step 1 If the TASK to which the hardware resource is to be assigned has already been written in the hardware resource, the hardware resource of such operator is assigned. If the operator has already been written, there is an advantage that the time for newly writing can be shortened. The presence or absence of such writing is determined using the ID associated with TASK, as described above. Also, the user may decide whether to use the already written data or write a new one through the ID. As another aspect, when a certain TASK is being executed using other input information, a configuration may be made to allocate such hardware resources, or selection to allocate other hardware resources may be made. may be configured to In the latter case, you may proceed to step 2 below.
  • Such choices may be determined based on a prediction process that predicts the time it will take to write the bitstream corresponding to the new TASK compared to the expected completion times of other running TASKs.
  • the latter process may be performed only when information such as priority TASK is attached to the TASK. This is to prevent a delay due to the execution of other TASKs, even if the TASK has already been written, in the case of a TASK that should be preferentially processed.
  • Step 2 If the TASK to which the hardware resource is to be allocated is not already written in the hardware resource, and if a PR region to which such ASK can be written can be selected in the database, for such PR region, the bit about the TASK Write a stream. Comparing to the next three steps has the advantage of saving compilation time which may require several hours with the partition shell writing and such newly selected PR region information.
  • the hardware resource identification process described above may be used as the PR region selection criteria.
  • Step 3 If the TASK to which the hardware resource is to be allocated has not been written in the hardware resource, and a PR region to which the TASK can be written cannot be selected in the database, a PR region to which the TASK can be written can be secured.
  • TASK may be written without using the PR region in an FPGA in which the hypervisor shell has been written and the partition shell has not been written.
  • the partition shell and / Or you may write the bitstream corresponding to TASK to the FPGA using a USB cable or JTAG without writing the hypervisor shell.
  • the USB cable is connected in advance, and the program may automatically write the bitstream corresponding to TASK via JTAG, or a person may connect the USB cable and write the TASK using JTAG. A corresponding bitstream may be written.
  • the TASK manager has a function of managing TASKs.
  • the TASK Manager uses direction from the JOB Manager to manage TASKs that run in the same FPGA in which the TASK Manager was written. Alternatively, the TASK manager may communicate the processing status of the TASK to the JOB manager.
  • the TASK manager may have a table showing the relationship between the information indicating the JOB to be executed in the FPGA written by the TASK manager and the current execution status of such JOB.
  • execution status may include statuses such as running, not running, and/or suspended.
  • Instructions from the JOB manager may include instructions to initialize, start, suspend, or cancel associated with information identifying the JOB.
  • Initialization includes initialization of storage information and/or communication information used by JOB. Such initialization instructions may be processed when a new operator is written into the FPGA and/or when a new JOB is executed. When an operator is newly written, memory information and/or communication information may be initialized as one step of the writing process. There are guaranteed benefits. Also, in the case of a new JOB within the same operator, it has the advantage of nullifying the effects of processing of previously executed JOBs.
  • Start may indicate the start of TASK.
  • the TASK manager may acquire the start instruction from the JOB manager in association with parameters used by the operator (input information for executing TASK).
  • the TASK manager may send the TASK start instruction together with the input information for executing the TASK to the PR region that executes the TASK related to the start instruction, and cause the TASK to start.
  • Suspension may be a temporary suspension of TASK execution. If the command to start is received again, the execution of TASK may be restarted.
  • the TASK manager may transmit TASK error processing and TSK completion reports to the JOB manager as the TASK processing status.
  • information about the actual FPGA is stored in the resource manager database.
  • information about the actual FPGA is stored in the resource manager database.
  • information such as the type of FPGA, attributes related to arithmetic devices, attributes related to storage devices, and/or attributes related to communication devices are stored in association with information specifying connected physical FPGAs.
  • the resource manager can identify hardware resources capable of executing the inquired JOB. Such information may be entered into the database manually or automatically.
  • the JOB manager may have a table of information related to each JOB.
  • the JOB Manager performs data flow analysis of JOBs and decides which JOBs to execute.
  • the JOB manager may use information about each JOB to perform data flow analysis.
  • the information related to the JOB may be information necessary for data flow analysis, such as JOB input data and JOB output data.
  • a known technique may be used for the data flow analysis itself.
  • the JOB may also be compiled to be executable on the FPGA and in bitstream form.
  • step 2 The JOB manager queries the resource manager about hardware resources that can execute the JOB to be executed.
  • resource information necessary for each JOB may be held in advance by the JOB manager.
  • Such resource information may be registered in advance by a programmer as necessary resource information when executing each JOB. If the JOB is compiled as described above and is in the form of a bitstream, the resource information includes information about the assumed FPGA and/or information about the PR region, etc., and hardware resource selection is performed. can be used for
  • step 3 A Resource Manager determines hardware resources for a JOB to execute and communicates such hardware resources to the JOB Manager. In this case, the above three steps may be processed.
  • step 4 A JOB manager communicates bitstreams associated with the JOB and/or input information during execution of the JOB to corresponding hardware resources for each JOB.
  • the partition shell and/or JOB operator may be written in the corresponding hardware resource in a bitstream or the like manner. In this case, it may be written using an FPGA writer and/or partition shell or the like.
  • step 5 A TASK manager in the hardware resource corresponding to each JOB manages the TASKs included in the JOB and advances the execution of the TASKs.
  • the JOB manager 01 sends the bitstream information to be used by the FPGAs 03A and 03B to the FPGA writer 02.
  • FPGA writer 02 sends the bitstream to FPGAs 03A and 03B and writes them respectively.
  • the JOB manager 01 transmits a task start instruction to each TASK manager in the FPGAs 03A and 03B where the tasks are executed. , start execution.
  • bitstream is sent from the JOB manager.
  • the stream may be stored and used in a storage, database, or storage system associated with the information processing device on which the FPGA writer is running.
  • the system of this example includes a server 01 having a JOB manager implemented in a programmable device, and a programmable device implemented with an FPGA writer connected via a network.
  • a server 02 including an FPGA connected to such a programmable device via PCIe, and a server 03 including the FPGA may be included.
  • Such a configuration is an example, and the number of FPGAs in the server is not limited to two, and may be one or more. , and the network may have various configurations.
  • FIG. 16 shows a state in which a bitstream scheduled to be written to the FPGA is sent from the JOB manager to the FPGA writer within the server 02 .
  • bitstreams used for each FPGA may be the same or different. For example, in this example, as described later, it is assumed that the sum of 1 to 1000 is calculated separately from 1 to 250, 251 to 500, 501 to 750, and 751 to 1000, but these divided A bitstream for an FPGA that processes each subcalculation and returns the result is different from a bitstream for an FPGA that processes each of these separate subcalculations plus the sum of them. good. Also in the former, if the types of FPGAs to be written in and the functions in the FPGAs are different, the bitstream may be adapted accordingly.
  • FIG. 17 shows how the FPGA writer writes bitstreams to each FPGA.
  • bitstreams can be written to each FPGA via an interconnect such as PCIe, USB, JTAG, Ethernet, Infiniband, or the like.
  • these writes may be in the same server where the FPGA being written to is in the same server as the FPGA writer, or in a different server than the FPGA writer.
  • FIG. 18 shows a state in which a task start instruction is transmitted from the JOB manager to the task manager in each FPGA.
  • input information used for the task may also be communicated.
  • input information from 1 to 250, 251 to 500, 501 to 750, 751 to 1000, etc. may be communicated.
  • the processing circuits to which the bitstreams are written within each FPGA execute the tasks. For example, in this example, portions 1 to 250, 251 to 500, 501 to 750, 751 to 1000, may be calculated.
  • FIG. 20 shows the state of transmitting the results calculated in each FPGA to the task processing circuit in one FPGA and calculating the sum of them.
  • each result calculated by FPGA04A-04C may be communicated to FPGA04D.
  • the location of FPGA 04D on the network may be determined in advance based on data flow analysis by the JOB manager.
  • the position on the network may be included in the bitstream and written to each FPGA, or may be transmitted to each FPGA as input information to the task indicating the transmission destination of the processing result together with the start instruction of each task. good too.
  • FIG. 21 shows a state in which each task manager in the FPGA notifies the JOB manager that execution of each task has ended.
  • a system includes: A distributed processing management system comprising a JOB manager and a resource manager, The JOB manager obtains a plurality of JOBs, including one or more JOBs to be executed on an FPGA; The resource manager selects a resource corresponding to the JOB, a system in which the JOB manager allocates the JOBs to the resources; When the JOB is a bitstream JOB executed by writing a bitstream on the FPGA, the resource manager transfers the corresponding bitstream corresponding to the PR region to which the bitstream JOB is allocated to the bitstream. selecting from multiple bitstreams for the JOB; It may be a distributed processing system.
  • the resource manager If the bitstream capable of executing the JOB is written in the FPGA, conveying information corresponding to the written position to the JOB manager; If the JOB-executable bitstream has not been written into the FPGA but there is a writable PR region, communicating information including information indicating the writable PR region to the JOB manager; When the bitstream capable of executing the JOB is not written in the FPGA and there is no writable PR region, information including information indicating the writable region is transmitted to the JOB manager. , It may be a distributed processing system.
  • the fourth system is a technology related to a development tool for developing a bitstream written by the user in the first system described above. After the user develops a program to be executed on FPGA, when the user writes the program on FPGA, the program written in hardware description language or high-level synthesis language (referred to as "HDL program or HLS program" in this document) ) must be compiled and bitstreamed so that it can be written on the FPGA. This bitstream must correspond to resource information such as FPGA type and PR region. Bitstreams that do not correspond to resource information such as FPGA type and PR region are FPGA cannot be written.
  • HDL program or HLS program high-level synthesis language
  • the compilation time may take several hours or more. Therefore, in the first system, after the user reserves the hardware corresponding to the specific resource information, if the bitstream corresponding to the reserved hardware is not generated, it takes time to generate the bitstream. is required, and the reserved hardware is unused during that time. This is an inefficient use of hardware resources, and if the user is on a time-based billing system, costs will be incurred even though they are not in use. Therefore, the fourth system is designed to address this problem and improve the efficiency of using hardware resources. As described above, an FPGA will be mainly used in the following description, but a reconfigurable device can also be used instead of the FPGA.
  • the fourth system may be associated with the fourth system on the premise of the first system described above.
  • the fourth system may be a system in an environment in which the first system is not implemented.
  • the fourth system may be directly or indirectly connected to a hardware information providing device described later, a compiling device described later, and a network or the like.
  • the fourth system may be the system used by the user.
  • the fourth system may be a terminal device used by the user, an information processing device accessed by the terminal used by the user, or a program executed on these devices.
  • a system as an example of the functional example fourth system may include a user interface unit, a hardware information providing device communication unit, and/or a compiler communication unit, as shown in FIG.
  • the user interface unit may obtain information from the user. For example, an instruction may be obtained from the user to update the information regarding the flavor.
  • the user interface unit may provide information to the user.
  • the update of the information on the flavor is not limited to instructions from the user, and may be updated according to predetermined conditions.
  • the predetermined condition may include, for example, every predetermined periodic period.
  • the hardware information providing device communication section may have a function capable of communicating with a system capable of providing hardware information, which is different from the fourth system.
  • a device capable of providing hardware information (also referred to as a "hardware information providing device" in this document) may be the first system described above, or may not be the first system described above.
  • the hardware information providing device only needs to have a function capable of providing information specifying the FPGA or the PR region within the FPGA in which the HDL program or HLS program is written.
  • the communication unit of the hardware information providing device sends information specifying the FPGA or the PR region in the FPGA in which the HDL program or HLS program is written to the hardware information providing device (in this document, (sometimes referred to as "hardware specific information").
  • the hardware identification information may be resource information identified as long as the bitstream in which the HDL program or HLS program is compiled can be written.
  • the hardware information may be resource information, such as resource information including information specifying a PR region, that allows different hardware to write the same bitstream. This is because resource information that does not include a PR region cannot write the same bitstream if the PR region is different.
  • the predetermined condition may include the case where information to update the flavor is obtained from the user.
  • the predetermined condition may include a case where a predetermined temporal condition is satisfied.
  • the predetermined temporal condition may be every predetermined regular time.
  • the predetermined time condition may be a predetermined date and time.
  • the hardware information providing device communication unit may have a function of acquiring hardware specific information from the hardware information providing device.
  • the hardware information providing device communication unit may acquire the hardware identification information in response to the above request, or may acquire it without making the above request. In the latter, for example, the hardware information providing device transmits hardware specific information to the fourth system based on a predetermined condition, and the hardware information providing device Specific information may be obtained.
  • the hardware specific information acquired by the hardware information providing device communication unit may be hardware specific information about all hardware that the hardware information providing device can provide, or the hardware information providing device can provide it. It may be hardware specific information about a part of the hardware. Such part may be selected based on information on hardware available to the user in the hardware provided by the hardware information providing device. For example, such piece of hardware specific information may be selected from hardware available to a given member if the user utilizing the compiled HDL or HLS program is a member. Such selection may be selected based on predetermined criteria. Such a predetermined criterion may be, for example, such that the administrator of the first system selects from among the hardware available to such users the hardware that the users wish to use.
  • the compiler communication unit has a function of communicating with a compiler outside the fourth system.
  • the compiler communication unit may have a function of transmitting compilation instructions to the compiler.
  • the compiler communication unit may transmit information used for compilation in association with compilation instructions to the compiler. Such information may include, for example, the HDL or HLS program being compiled, and/or hardware specific information to which the compiled bitstream is written.
  • Compilation results may include design intermediate files.
  • the design intermediate file may include information on placement and routing of parts other than the target PR region. For example, if the PR region 1 of the first FPGA is included as the hardware specific information, the corresponding design intermediate file may include wiring information with portions within the first FPGA other than the PR region 1 of the first FPGA. . In addition, if the hardware specific information includes multiple PR regions, the corresponding design intermediate file is not included in the FPGA (including each PR region) other than each PR region corresponding to each of these multiple PR regions. Wiring information with the part may be included.
  • Compilation results may also include information in the form of bitstreams. Compiler results may include information in the form of multiple partial bitstreams.
  • the system of this example which is the fourth system, acquires from the user an instruction to update the hardware specific information (step 1).
  • the system of this example instructs the hardware information providing device to update the hardware specific information (step 2).
  • step 3 the system of this example acquires hardware specific information from the hardware information providing device and updates it.
  • the system of this example acquires hardware specific information from a hardware information providing device. Note that step 3 may be performed without steps 1 and/or 2, in which case steps 1 and 2 may or may not be present.
  • the system of this example receives from the user information related to the HDL program to be compiled (including information specifying the HDL program or HLS program and/or the HDL program or HLS program; the same shall apply hereinafter) and , communicates the hardware specific information to the compiling device (step 4).
  • the hardware identification information may be all hardware identification information possessed by the system of this example, or may be a part thereof.
  • the more hardware specific information to be compiled the more writable targets.
  • the total compile time is shortened although the number of writable targets is reduced.
  • the compiling device compiles using information related to the HDL program to be compiled and the hardware specific information (step 5).
  • the compiling device may compile for all hardware specifying information, or may compile using a predetermined range of hardware specifying information.
  • the more hardware specific information to be compiled the more writable targets.
  • the range is limited to a predetermined range, the number of writable targets is reduced, but there is an advantage in that the total compile time is shortened.
  • the compiling device sends the compiling result to the system of this example, and the system of this example obtains the compiling result from the compiling device (step 6).
  • the system of this example selects one or more pieces of resource information in the flavor and requests the first system to reserve corresponding hardware resources. may request. If the first system succeeds in securing the corresponding hardware resource, it may register the information in the database and transmit information on the secured hardware resource to the system of this example.
  • the reserved hardware resource information may include, for example, information identifying the available PR regions in which partition shells are written. Information identifying such available PR regions includes the network address for the PR region, such as an IP address or MAC address, the ID of such PR region, and/or information identifying the FPGA containing such PR region. OK.
  • An example system of the fourth system includes: a user interface unit that provides information to and/or obtains information from a user; a hardware specific information providing device communication unit having a function capable of communicating with the first system or the hardware specific information providing device; a compiler communication unit having a function capable of communicating with a compiler capable of converting an HDL program or HLS program into a bitstream that can be written to an FPGA; may be provided.
  • the system according to the first aspect comprises: an acquisition unit that acquires information indicating a first resource from a user; an identifying unit that identifies a first reconfigurable device corresponding to the information indicating the first resource; an instruction unit that instructs the first reconfigurable device to write a first partition shell corresponding to the information indicating the first resource; It is a system with
  • the acquisition unit acquires information indicating a second resource that is not the same as information indicating the first resource
  • the instruction unit instructs the first reconfigurable device to write a second partition shell corresponding to the information indicating the second resource and different from the first partition shell.
  • the system according to the third aspect in the first aspect or the second aspect, " further comprising a presentation unit that presents one or more pieces of resource information to the user;
  • the information indicating the first resource is part of the presented one or more pieces of reconfigurable device resource information.
  • the presentation unit presents a plurality of setting methods for setting the PR region for the first reconfigurable device.
  • a system according to a fifth aspect is characterized in that, in any one of the first to fourth aspects, "the one or more resource information is information related to computing functions, information related to storage functions, and/or communication functions including information relating to
  • the system according to the sixth aspect is, in any one of the first to fifth aspects, "
  • the acquisition unit acquires information indicating a third resource that is not the same as the information indicating the first resource and the information indicating the second resource,
  • the identifying unit identifies a third reconfigurable device corresponding to the information indicating the third resource and different from the first reconfigurable device,
  • the instruction unit instructs the third reconfigurable device to write a third partition shell corresponding to the information indicating the third resource.”
  • the system according to the seventh aspect is, in any one of the first to sixth aspects, "
  • the system comprises a database that associates and stores at least information indicating the first resource and information indicating the first reconfigurable device corresponding to the information indicating the first resource.
  • the system according to the eighth aspect is, in any one of the first to seventh aspects, " A hypervisor shell having functions that the first partition shell does not have is already written in the first reconfigurable device.”
  • the system according to the ninth aspect is, in any one of the first to eighth aspects, "
  • the system comprises an inquiry unit for inquiring the status of the first PR region corresponding to the hypervisor shell,
  • the hypervisor shell is capable of replying to an inquiry about the status of the first PR region from the inquiry unit.
  • the system according to the tenth aspect is, in any one of the first to ninth aspects, "
  • the hypervisor shell has a function of confirming authority for the PR region to which the user writes.
  • the hypervisor shell has a memory function and/or a communication function initialization function related to the first reconfigurable device. "has a function of verifying authority for the PR region to which the user may write, which may contain”.
  • the method according to the twelfth aspect comprises: the system, obtaining information indicative of the first resource from the user; identifying a first reconfigurable device corresponding to the information indicating the first resource; instructing the first reconfigurable device to write a first partition shell corresponding to the information indicating the first resource; How to perform
  • a method according to a thirteenth aspect is the above-described twelfth aspect, wherein "the system stores information specifying a first reconfigurable device corresponding to the information indicating the first resource".
  • a computer program comprises: the system, means for obtaining information indicative of the first resource from the user; means for identifying a first reconfigurable device corresponding to the information indicating the first resource; means for instructing the first reconfigurable device to write a first partition shell corresponding to the information indicating the first resource; It is a program for operating as
  • a computer program according to a fifteenth aspect is the computer program according to the fourteenth aspect, wherein "the system stores information specifying a first reconfigurable device corresponding to the information indicating the first resource”.
  • the program variable device 10 may comprise an arithmetic device 12, a storage device 13, a communication IF 16, and a bus 11 connecting them.
  • Programmable device 10 may also include an input device 14, a display device 15, and a bus 11 that also connects these devices.
  • the programmable device 10 may be directly or indirectly connected to another information processing apparatus via a network 19 .
  • the programmable device 10 may be an information processing device such as a server, cloud, or the like. It may be a dedicated device or a general-purpose device. Also, the programmable device 10 itself may be a reconfigurable device in which a circuit is written. In this case, there is the advantage that the programs of the various embodiments described above can be executed more quickly.
  • a presentation may include a display.
  • the system of this example may be displayed by a display device included in the system of this example, or may be displayed on a display device in another information processing device to which the system of this example is directly or indirectly connected.
  • processes and procedures described in this document may be implemented not only by those explicitly described in the embodiments, but also by software, hardware, or a combination thereof.
  • the processes and procedures described in this document may be implemented as computer programs and executed by various computers. These computer programs may also be stored in a storage medium. Also, these programs may be stored in a non-transitory or temporary storage medium.

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