WO2022218536A1 - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Semiconductor device and method for manufacturing semiconductor device Download PDF

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Publication number
WO2022218536A1
WO2022218536A1 PCT/EP2021/059844 EP2021059844W WO2022218536A1 WO 2022218536 A1 WO2022218536 A1 WO 2022218536A1 EP 2021059844 W EP2021059844 W EP 2021059844W WO 2022218536 A1 WO2022218536 A1 WO 2022218536A1
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Prior art keywords
fets
substrate
semiconductor device
region
fet
Prior art date
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PCT/EP2021/059844
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French (fr)
Inventor
Krishna Kumar BHUWALKA
Original Assignee
Huawei Technologies Co., Ltd.
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Publication date
Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Priority to CN202180097120.6A priority Critical patent/CN117378048A/en
Priority to EP21719892.8A priority patent/EP4324028A1/en
Priority to PCT/EP2021/059844 priority patent/WO2022218536A1/en
Publication of WO2022218536A1 publication Critical patent/WO2022218536A1/en

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    • H—ELECTRICITY
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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Definitions

  • the disclosure relates generally to the field of semiconductor devices; more specifically, the disclosure relates to a semiconductor device and a method for (namely, a method of) manufacturing the semiconductor device.
  • a semiconductor device is an electronic device whose functioning is based on electronic properties of a semiconductor material, such as Silicon (Si), Germanium (Ge), Galium Arsende and the like.
  • the semiconductor device is manufactured either as an individual device or as an integrated circuit (IC) device.
  • a well known semiconductor device is named as a metal oxide semiconductor field-effect transistor (MOSFET) that includes a drain terminal, a source terminal and a gate terminal.
  • MOSFET metal oxide semiconductor field-effect transistor
  • FinFET fin field-effect transistor
  • Such a FinFET device includes two or more gate terminals which lie on two, or three sides of a channel made by a source terminal and a drain terminal of the FinFET device, hence, the FinFET device manifests somewhat better electrical conduction properties in comparison to the known MOSFET device.
  • a gate all around FET (GAAFET) device is proposed as a replacement for the FinFET device or the FinFET -based complementary metal oxide semiconductor (CMOS) logic devices (e.g. as used in contemporary microprocessors, memory cells, etc.).
  • a conventional GAAFET device is a multigate device having a channel made by a source terminal(s) and a drain terminal(s).
  • the conventional GAAFET device is similar in concept to the FinFET device except that multiple gates surround the channel on all sides, which results in partly improved performance of the conventional GAAFET device over the FinFET device.
  • the conventional GAAFET device includes one or more conventional N/P-type devices with multiple stacks of nanosheets (NS) arranged on top of one another.
  • a conventional N-type device is referred to as a semiconductor device, in which majority charge carriers are electrons.
  • a conventional P-type device is referred to as a semiconductor device, in which majority charge carriers are holes.
  • the one or more conventional N/P-type devices that are manufactured on a single wafer i.e., a substrate or a chip
  • Various methods have been proposed to design the multiple stacks of nanosheets (NS) on the single wafer (i.e., the substrate).
  • a conventional method for designing the multiple stacks of nanosheets (or multiple active stacks) on the single wafer (i.e., the substrate) in a conventional GAAFET device is based on making a physical isolation between the multiple stacks of nanosheets.
  • the physical isolation between the multiple stacks of nanosheets is made by deposition and subsequent etching of a low-k dielectric material.
  • the low-k dielectric material is deposited at first on the single wafer (i.e., the substrate) to block electrical conduction in lower channels of the conventional GAAFET device.
  • the conventional method includes a source and a drain which are epitaxially grown on the low-k dielectric material that results in a loss of channel stress and hence, in a reduced performance of the conventional GAAFET device.
  • the conventional method has another limitation of a poor quality of the source and the drain that are epitaxially formed on the low-k dielectric material.
  • Another conventional method is based on designing the multiple stacks of nanosheets (or multiple active stacks) on the single wafer (or the substrate) by etching out active regions and then regrowing silicon (Si) or silicon-germanium (SiGe) stacks.
  • Si silicon
  • SiGe silicon-germanium
  • the disclosure seeks to provide an improved semiconductor device that includes a substrate with one or more field-effect transistors (FETs) formed on the substrate.
  • the disclosure further seeks to provide an improved method for (namely, method of) manufacturing the semiconductor device that includes the substrate with the one or more field-effect transistors (FETs) formed on the substrate.
  • the disclosure provides a solution to the existing problem of the conventional GAAFET device that has inadequacy in its basic properties with respect to performance and stress in the channel of the source and the drain.
  • An objective of the disclosure is to provide a solution that overcomes at least partially the problems encountered in the prior art and provides a semiconductor device that includes a substrate with one or more field-effect transistors (FETs) formed on the substrate and further an improved method for (namely, method of) manufacturing the semiconductor device that includes the substrate with the one or more field-effect transistors (FETs) formed on the substrate.
  • FETs field-effect transistors
  • the disclosure provides a semiconductor device that includes a substrate having one or more field-effect transistors (FETs) formed thereon, wherein a given FET of the one or more FETs includes multiple nano-layers formed into alternate gates and channels in a vertical stack.
  • FETs field-effect transistors
  • a source region and a drain region of the given FET flank the vertical stack such that the channels are configured to provide a conduction path between the source region and the drain region depending on a voltage signal applied to the gates.
  • the semiconductor device further includes that one or more of the source region and the drain region of the given FET is epitaxially formed on a doped layer that is epitaxially formed on the substrate, such that a crystallographic orientation of the substrate is communicated via the doped layer to the one or more of the source region and the drain region.
  • the doped layer is configured to blank-off one or more of the gates and their one or more associated channels in the vertical stack from contributing to conduction between the source region and drain region when the given FET is in operation.
  • the disclosed semiconductor device includes stacks of multiple nano layers (or nanosheets) that are formed on the substrate (or the same substrate) with a flexibility in the number of stacks of nano layers.
  • the disclosed semiconductor device manifests N/P ratio control with an option to have different stack number for N-FETs or P-FETs (e.g. 3:2, 3:1, etc.).
  • the disclosed semiconductor device manifests an electrical isolation between stacks of multiple nano layers in contrast to a physical isolation that is made between stacks of multiple nano layers used in a conventional semiconductor device which further results in a loss of channel stress and hence, into a reduced performance of the conventional semiconductor device.
  • the disclosed semiconductor device maintains a channel stress (or a stress between the source region and the drain region) that further maintains the performance (or a performance-power trade off design).
  • the doped layer is of a same doping polarity type as that of a region of the substrate on which the one or more FETs are formed.
  • the doped layer of the same doping polarity type as that of the region of the substrate on which the one or more FETs are formed in order to keep a monocrystalline structure of the substrate that further results into an improved epitaxial quality of the source region and the drain region.
  • the doped layer is formed epitaxially from one or more of: SiGe, GeSn, Ge and GaAs.
  • the doped layer epitaxially from one of SiGe, GeSn, Ge and GaAs is advantageous to form the doped layer epitaxially from one of SiGe, GeSn, Ge and GaAs to further improve the epitaxial quality of the source region and the drain region.
  • the substrate includes both at least one n-type region and at least one p-type region, wherein a portion of the one or more FETs are fabricated as p-type FETs onto the at least one n-type region, and another portion of the one or more FETs are fabricated as n-type FETs onto the at least one p-type region.
  • the disclosed semiconductor device includes both the n-type region and the p-type region on the same substrate therefore, wherein the disclosed semiconductor device further includes the p-type FETs and the n-type FETs and manifests a flexibility in the stack number of multiple nano layers.
  • each conducting layer of the multiple layers in the vertical stack has a thickness in a direction that is orthogonal to a plane of the substrate that is in a range of 1 nm to 20 nm.
  • each conducting layer of the multiple layers has a thickness in the range of lnm to 20 nm in order to have a dense packaging and a reduced size of the disclosed semiconductor device.
  • the one or more FETs are fabricated as gate-all-around (GAA) structures.
  • the one or more FETs are formed to be a FinFET elongate structure arrangement, wherein an elongate axis of the one or more FETs is parallel to a plane of the substrate, and is orthogonal to a conduction direction from the source region to the drain region.
  • the one or more FETs as the FinFET elongate structure arrangement to incorporate simplicity in the disclosed semiconductor device.
  • the doped layer is configured to isolate from the one or more FETs one or more layers of the vertical stack that are closest to the substrate.
  • the doped layer electrically isolates in the one or more FETs one or more layers of the vertical stack that are closest to the substrate in order to maintain the channel stress (or the stress between the source region and the drain region) that further maintains the performance (or the performance-power trade off design) of the disclosed semiconductor device.
  • the one or more FETs are Silicon-based devices.
  • the one or more FETs as the silicon based devices to enable a reduced power consumption and a reduced size of the disclosed semiconductor device.
  • the disclosure provides a method for (namely, method of) manufacturing a semicondictor device having one or more field-effect transistors (FETs) formed thereon.
  • the method includes forming one or more stacks of multiple nano-layers into a plurality of alternate gates and channels in vertical stacks.
  • the method further includes forming a source region and a drain region to flank the plurality of alternate gates and channels in the given vertical stack, wherein at least one of the source region and the drain region are epitaxially fabricated onto a doped layer that is epitaxially formed onto the substrate, such that a crystallographic orientation of the substrate is communicated via the doped layer to the at least one of the source region and the drain region.
  • the doped layer is configured to blank-off at least one of the gates and its associated channel in the given vertical stack from contributing to conduction between the source region and drain regions via the channels when the given FET is in operation.
  • the disclosed method proposes the semiconductor device with stacks of multiple nano layers (or nanosheets) that are formed on the substrate (or the same substrate) with electrical islolation among the multiple nano layers.
  • the disclosed method achieves all the advantages and effects of the disclosed semiconductor device.
  • FIG. 1A is an illustration of a side view of a semiconductor device with one stack of nanosheets formed on a substrate, in accordance with an embodiment of the disclosure
  • FIG. IB is an illustration of a side view of a semiconductor device with two stacks of nanosheets formed on the substrate, in accordance with an embodiment of the disclosure
  • FIG. 1C is an illustration of a side view of a semiconductor device with three stacks of nanosheets formed on the substrate, in accordance with an embodiment of the disclosure
  • FIG. 2 is an illustration of a side view of a semiconductor device with multiple choice of stack number on a N-FET and a P-FET, of the one or more FETs that can be formed on the substrate, in accordance with an embodiment of the disclosure;
  • FIG. 3 is a flowchart of a method for manufacturing a semiconductor device having one or more field-effect transistors (FETs) formed on the substrate, in accordance with an embodiment of the disclosure.
  • FETs field-effect transistors
  • FIGs. 4A-4H collectively is a representation of a method for manufacturing a semiconductor device with a multiple choice of stack number on two N-FETs, in accordance with an embodiment of the disclosure.
  • an underlined number is employed to represent an item over which the underlined number is positioned or an item to which the underlined number is adjacent.
  • a non-underlined number relates to an item identified by a line linking the non- underlined number to the item.
  • the non-underlined number is used to identify a general item at which the arrow is pointing.
  • FIG. 1 A there is shown a side view illustration of a semiconductor device with one stack of nanosheets formed on a substrate, in accordance with an embodiment of the disclosure.
  • FIG. 1 A there is shown a side view of a semiconductor device 100A that includes a substrate 102 and a field effect transistor (FET) 104 formed on the substrate 102.
  • FET field effect transistor
  • the FET 104 includes a first gate 106 A, a second gate 106B, a third gate 106C, a first channel 108 A, a second channel 108B, a third channel 108C, and a top gate 110.
  • the FET 104 further includes a plurality of side pockets 109.
  • the plurality of side pockets 109 is associated with the first gate 106 A, the second gate 106B, and the third gate 106C.
  • Each of the first gate 106 A, the second gate 106B, the third gate 106C, the first channel 108 A, the second channel 108B, the third channel 108C, and the top gate 110 of the FET 104 are arranged in a vertical stack 112.
  • the gates 106A, 106B, 106C are isolated from the channels 108A, 108B, 108C by a thin layer of oxide or high-k, for example in a range of circa 0.1 nm to 2 nm thick; this thin layer of oxide or high-k is not shown on FIG. 1A.
  • the FET 104 further incudes a source region 114, a drain region 116, a doped layer 118 and a contact (CNT) 120.
  • Each of the FET 104, the vertical stack 112, the source region 114 and the drain region 116 is represented by a dashed-line rectangular box; the box is used for illustration purpose only and does not form a part of circuitry of the field effect transistor (FET) 104.
  • the substrate 102 may also be referred as a single wafer or a chip.
  • the substrate 102 is made up of a semiconductor material such as, silicon (Si) or germanium (Ge) and the like.
  • a p-type dopant is added in the semiconductor material of the substrate 102. Therefore, the substrate 102 may also be referred as a p-type semiconductor.
  • a p-type semiconductor is one in which majority charge carriers are holes. Examples of the p-type dopants are, but not limited to, Boron (B), Indium (In), and the like.
  • the substrate 102 may also have an isolation property.
  • the substrate 102 may have n-type doping hence, may be referred as a n-type semiconductor.
  • a n-type semiconductor is one in which majority charge carriers are electrons. Examples of the n-type semiconductor are, but not limited to, Phosphorus (P), Arsenic (As), Antimony (Sb), and the like.
  • the FET 104 is a transistor which uses an electric field to control a flow of current.
  • the FET 104 is configured to control the flow of current by applying a voltage signal to the first gate 106A, the second gate 106B, and the third gate 106C that results into conductivity beween the source region 114 and the drain region 116.
  • the substrate 102 is the p-type semiconductor, therefore, the FET 104 that is formed on the substrate 102 is an n-type FET (or N-FET).
  • the FET 104 will be a p-type FET (or P-FET).
  • a semiconductor device with the n-type FET (or N-FET) and the p-type FET (or P-FET) is described in detail, for example, in FIG. 2.
  • the semiconductor device 100A includes the substrate 102 having one or more field-effect transistors (FETs) formed thereon, wherein a given FET 104 of the one or more FETs includes multiple nano-layers formed into alternate gates and channels in the vertical stack 112.
  • the first gate 106 A, the second gate 106B, the third gate 106C, the first channel 108 A, the second channel 108B, and the third channel 108C of the FET 104 together form the alternate gates and the channels, respectively, in the vertical stack 112.
  • the first gate 106A, the second gate 106B, the third gate 106C, the first channel 108 A, the second channel 108B, and the third channel 108C of the FET 104 are arranged alternatively with respect to each other.
  • the first channel 108A is arranged over the first gate 106A and the second gate 106B is arranged over the first channel 108A but below the second channel 108B.
  • the third gate 106C is arranged over the second channel 108B but below the third channel 108C.
  • the top gate 110 is arranged over the third channel 108C in the vertical stack 112.
  • the first gate 106A alongwith the first channel 108A represents one stack of nanosheet.
  • the first gate 106A alongwith the first channel 108A, the second gate 106B alongwith the second channel 108B and the third gate 106C alongwith the third channel 108C may also be referred as the multiple nano-layers or multiple stacks (e.g.
  • the plurality of side pockets 109 associated with the first gate 106A, the second gate 106B, and the third gate 106C is made up of dielectric materials (e.g. an oxide or nitride or high-k) and used for insulation purposes.
  • the source region 114 and the drain region 116 of the given FET 104 flank the vertical stack 112 such that the channels are configured to provide a conduction path between the source region 114 and the drain region 116 depending on a voltage signal applied to the gates.
  • the source region 114 (also represented as S) and the drain region 116 (also represented as D) of the FET 104 form the sides (e.g. a left side and a right side) of the vertical stack 112 in such a way that the first channel 108A, the second channel 108B and the third channel 108C provide the conduction path between the source region 114 (i.e., S) and the drain region 116 (i.e., D).
  • the source region 114 (i.e., S) and the drain region 116 (i.e., D) are formed by n-type doping into the Silicon (Si) or Germanium (Ge) or Silion-Germanium (SiGe) semiconductor material. Therefore, the source region 114 (i.e., S) and the drain region 116 (i.e., D) may also be referred as n-type semiconductor.
  • the source region 114 (i.e., S) and the drain region 116 (i.e., D) may be one or more in the FET 104.
  • One or more of the source region 114 and the drain region 116 of the given FET 104 is epitaxially formed on the doped layer 118 that is epitaxially formed on the substrate 102, such that a crystallographic orientation of the substrate 102 is communicated via the doped layer 118 to the one or more of the source region 114 and the drain region 116.
  • the one or more of the source region 114 (i.e., S) and the drain region 116 (i.e., D) of the FET 104 is epitaxially (or in an ordered manner) formed on the doped layer 118 to maintain a monocrystalline structure of the substrate 102.
  • the doped layer 118 is a p-type layer that is epitaxially formed on the substrate 102 to communicate the crystallographic orientation of the substrate 102 to the at least one of the source region 114 (i.e., S) and the drain region 116 (i.e., D). In this way, the one or more of the source region 114 and the drain region 116 have the same crystallographic orientation as the substrate 102. This means that planar indices of one or more lattice planes of the substrate 102 and the one or more of the source region 114 and the drain region 116 are the same.
  • the doped layer 118 may also be referred as a p-type epitaxial (or p-type epi) layer.
  • the doped layer 118 is configured to blank-off one or more of the gates and their one or more associated channels in the vertical stack 112 from contributing to conduction between the source region 114 and drain region 116 when the given FET 104 is in operation.
  • the doped layer 118 (or p-type epi) blocks the first gate 106A and the second gate 106B and their associated channels such as the first channel 108A and the second channel 108B as well, from full or parital conduction.
  • the doped layer 118 electrically isolates the first gate 106A and the associated first channel 108A and the second gate 106B and the associated second channel 108B in contrast to a conventional physical isolation which result in loss of channel stress and hence, loss of performance of a conventional semiconductor device. Due to electrical isolation of the first gate 106A and the second gate 106B and their associated channels such as the first channel 108A and the second channel 108B, a channel stress (or a stress between the source region 114 and the drain region 116) is maintained and hence, the performance (or a performance-power trade off design) of the semiconductor device 100A is maintained.
  • the doped layer 118 is of a same doping polarity type as that of a region of the substrate 102 on which the one or more FETs are formed.
  • the doped layer 118 is of the same doping polarity type (e.g. p-type) as that of the region of the substrate 102 is doped to keep the monocrystalline structure of the substrate 102 and to communicate the crystallographic orientation of the substrate 102 to the source region 114 (i.e., S) and the drain region 116 (i.e., D).
  • the doped layer 118 is formed epitaxially from one or more of: SiGe, GeSn, Ge and GaAs.
  • the doped layer 118 is formed epitaxially over the substrate 102 from one of the Silicon-Germanium (SiGe), Germanium- Stannum (GeSn), Germanium (Ge) and Gallium- Arsenide (GaAs).
  • the substrate 102 includes both at least one n-type region and at least one p-type region, wherein a portion of the one or more FETs are fabricated as p- type FETs onto the at least one n-type region, and another portion of the one or more FETs are fabricated as n-type FETs onto the at least one p-type region.
  • the substrate 102 may include both one or more n-type regions and one or more p-type regions as well. In the one or more n-type regions of the substrate 102, the portion of the one or more FETs are fabricated as the p-type FETs.
  • the portion of the one or more FETs are fabricated as the n-type FETs.
  • the substrate 102 includes the at least one p-type region and the FET 104 that is fabricated on the substrate 102 is of the n-type (or N-FET).
  • each conducting layer of the multiple layers in the vertical stack 112 has a thickness in a direction that is orthogonal to a plane of the substrate 102 that is in a range of 1 nm to 20 nm.
  • Each conducting layer of the multiple nano layers or multiple stacks of nanosheets (NS) in the vertical stack 112 of the FET 104 has the thickness in the direction that is orthogonal to the plane of the substrate 102.
  • the thickness of each conducting layer may be 1 nanometer (nm), 3 nm, sub-3 nm, 5 nm, 7 nm, 9 nm, 11 nm, 13 nm, 15 nm, 17 nm, 19 nm or 20 nm.
  • the one or more FETs are fabricated as gate-all-around (GAA) structures.
  • the FET 104 is formed on the substrate 102 in such a way that the first gate 106 A, the second gate 106B and the third gate 106C surround the first channel 108 A, the second channel 108B and the third channel 108C, respectively.
  • the one or more FETs are formed on the substrate 102, hence, the one or more FETs manifest the gate-all-around (GAA) structures.
  • the one or more FETs are formed to be a FinFET elongate structure arrangement, wherein an elongate axis of the one or more FETs is parallel to a plane of the substrate 102, and is orthogonal to a conduction direction from the source region 114 to the drain region 116.
  • the one or more FETs manifest the FinFET elongate structure arrangement with the elongate axis.
  • the elongate axis of the one or more FETs is parallel to the plane of the substrate 102 and is orthogonal (or perpendicular) to the conduction direction from the source region 114 (i.e., S) to the drain region 116 (i.e., D).
  • the doped layer 118 is configured to isolate from the one or more FETs one or more layers of the vertical stack 112 that are closest to the substrate 102.
  • the doped layer 118 is configured to electrically isolate the one or more layers or nanosheets (NS) of the vertical stack 112 that are close to the substrate 102 from the one or more FETs.
  • the doped layer 118 electrically isolates the first gate 106A alongwith the first channel 108 A and the second gate 106B along with the second channel 108B in order to maintain the channel stress (or the stress between the source region 114 and the drain region 116) that further maintains the performance (or the performance-power trade off design) of the semiconductor device 100A.
  • the semiconductor device 100A manifests one stack of nanosheets that is the third gate 106C and the third channel 108C to provide the electrical conduction between the source region 114 (i.e., S) and the drain region 116 (i.e., D).
  • the one or more FETs are Silicon-based devices.
  • the one or more FETs are made up of Silicon (Si) semiconductor material.
  • the semiconductor device 100A includes the FET 104 of the one or more FETs formed on the substrate 102.
  • the FET 104 includes the multiple nano layers or multiple (e.g. 3) stacks of nanaosheets (NS) formed into the alternate gates and the channels.
  • the FET 104 includes the first gate 106 A, the second gate 106B, the third gate 106C and the first channel 108 A, the second channel 108B and the third channel 108C which are alternatively arranged in the vertical stack 112.
  • the FET 104 further includes the doped layer 118 on which the source region 114 (i.e., S) and the drain region 116 (i.e., D) are epitaxially formed.
  • the doped layer 118 is formed of the same polarity type as that of the region of the substrate 102 on which the one or more FETs are formed to keep the monocrystalline nature of the substrate 102 and to communicate the crystallographic orientation of the substrate 102 to the source region 114 (i.e., S) and the drain region 116 (i.e., D). Therefore, the semiconductor device 100A provides an improved epitaxial quality of the source region 114 (i.e., S) and the drain region 116 (i.e., D).
  • the doped layer 118 electrically isolates the first gate 106A and the second gate 106B and their associated channels such as the first channel 108A and the second channel 108B as well, in order to maintain the channel stress (or the stress between the source region 114 and the drain region 116) that further maintains the performance (or the performance-power trade off design) of the semiconductor device 100A.
  • the electrical conduction between the source region 114 (i.e., S) and the drain region 116 (i.e., D) takes place only through one stack that is the third gate 106C and the third channel 108C. Therefore, the semiconductor device 100A may also be referred as a N-FET 1 -stack nanosheet (NS) GAA device.
  • FIG. IB there is shown a side view illustration of a semiconductor device with two stack of nanosheets formed on the substrate, in accordance with an embodiment of the disclosure.
  • FIG. IB is described in conjunction with elements from FIG. 1A.
  • FIG. IB there is shown a side view of a semiconductor device 100B.
  • the semiconductor device 100B is similar to the semiconductor device 100A except that the doped layer 118 blanks-off the first gate 106A and the first channel 108A instead of the first gate 106A, the second gate 106B, the first channel 108A and the second channel 108B, as obtained in the semiconductor device 100A.
  • the semiconductor device 100B manifests two stacks of nanosheets (NS), namely the second gate 106B alongwith the second channel 108B and the third gate 106C alongwith the third channel 108C to provide the electrical conduction between the source region 114 (i.e., S) and the drain region 116 (i.e., D). Therefore, the semiconductor device 100B may also be referred as a N-FET 2-stack NS GAA device.
  • FIG. 1C there is shown a side view illustration of a semiconductor device with two stacks of nanosheets formed on the substrate, in accordance with an embodiment of the disclosure.
  • FIG. 1C is described in conjunction with elements from FIGs. 1A and IB.
  • FIG. 1C there is shown a side view of a semiconductor device lOOC.
  • the semiconductor device lOOC is similar to the semiconductor device 100A except that the semiconductor device lOOC manifests three stacks of nanosheets (NS), namely the first gate 106A alongwith the first channel 108A, the second gate 106B alongwith the second channel 108B and the third gate 106C alongwith the third channel 108C to provide the electrical conduction between the source region 114 (i.e., S) and the drain region 116 (i.e., D). Therefore, the semiconductor device lOOC may also be referred as a N-FET 3-stack NS GAA device. In the semiconductor device lOOC, the doped layer 118 is completely removed.
  • NS nanosheets
  • the semiconductor devices 100A, 100B and lOOC collectively represents a flexibility in the number of stacks of nanosheets that can be formed on the substrate 102. This in turn provides a flexibility in the performance-power trade off design of the semiconductor devices 100A, 100B and lOOC.
  • the number of stacks of nanosheets that can be formed on the substrate 102 can further be increased depending on requirements.
  • the semiconductor devices 100A, 100B and lOOC manifest N/P ratio control with an option to have different stack numbers for N-FET or P-FET (e.g. 3:2, 3:1, etc.).
  • a semiconductor device can be manufactured in such a way that the semiconductor device may have 3 stacks of nanosheets formed on a N-FET along with 2 stacks of nanosheets on a P-FET, of the one or more FETs that can be formed on the substrate 102.
  • An example of such semiconductor device is described in detail, for example, with reference to FIG. 2.
  • FIG. 2 there is shown a side view illustration of a semiconductor device with a multiple choice of stack numbers on a N-FET and a P-FET, of the one or more FETs that can be formed on a substrate, in accordance with an embodiment of the disclosure.
  • FIG. 2 is described in conjunction with elements from FIGs. 1 A, IB, and 1C.
  • FIG. 2 there is shown a side view of a semiconductor device 200 that includes a semiconductor device 200A and another semiconductor device 200B.
  • Each of the semiconductor devices 200, 200A, and 200B is represented by a dashed rectangular box, which is used for illustration purpose only and do not form a part of circuitry.
  • the semiconductor device 200A corresponds to the semiconductor device lOOC (of FIG. 1C).
  • the semiconductor device 200A is named as a N-FET 3-stack NS GAA device.
  • the semiconductor device 200 A includes 3 stacks of nanosheets of the FET 104 formed on the substrate 102.
  • the semiconductor device 200B includes a substrate 202, a FET 204, a first gate 206A, a second gate 206B, a third gate 206C, a first channel 208A, a second channel 208B, a third channel 208C, a plurality of side pockets 209, a top gate 210, a vertical stack 212, a source region 214, a drain region 216, a doped layer 218 and a contact 220.
  • the substrate 202 corresponds to the substrate 102 (of FIG. 1A) except that the substrate 202 is doped with a n-type impurity, hereinafter referred as the n-type semiconductor.
  • the FET 204 corresponds to the FET 104 except that the FET 204 is a P-FET.
  • Each of the first gate 206A, the second gate 206B, the third gate 206C, the first channel 208A, the second channel 208B, the third channel 208C, the plurality of side pockets 209, the top gate 210, the vertical stack 212 and the contact 220 of the semiconductor device 200B corresponds to the first gate 106 A, the second gate 106B, the third gate 106C, the first channel 108 A, the second channel 108B, the third channel 108C, the plurality of side pockets 109, the top gate 110, the vertical stack 112 and the contact 120 of the semiconductor device 100B (of FIG. IB), respectively.
  • the source region 214 (also represented as S) and the drain region 216 (also represented as D) corresponds to the source region 114 and the drain region 116 (of FIG. IB), respectively, except that the source region 214 (i.e., S) and the drain region 216 (i.e., D) are formed by p-type doping into the Silicon-Germanium (SiGe) semiconductor material. Therefore, the source region 214 (i.e., S) and the drain region 216 (i.e., D) may also be referred as p-type semiconductor.
  • the source region 214 (i.e., S) and the drain region 216 (i.e., D) may be one or more that are epitaxially grown on the doped layer 218 in the FET 204.
  • the doped layer 218 corresponds to the doped layer 118 except that the doped layer 218 is a n-type layer that is epitaxially formed on the substrate 202 to communicate the crystallographic orientation of the substrate 202 to at least one of the source region 214 (i.e., S) and the drain region 216 (i.e., D).
  • the doped layer 218 may also be referred as a n-type epitaxial (or n-type epi) layer.
  • the doped layer 218 blank-off the first gate 206 A and the first channel 208A.
  • the semiconductor device 200B manifests two stacks of nanosheets (NS) that is the second gate 206B alongwith the second channel 208B and the third gate 206C alongwith the third channel 208C to provide the electrical conduction between the source region 214 (i.e., S) and the drain region 216 (i.e., D). Therefore, the semiconductor device 200B corresponds to the semiconductor device 100B (of FIG. IB) except that the semiconductor device 200B includes 2 stacks of nanosheets of the FET 204 (i.e., P-FET) formed on the substrate 202 (i.e., n-type substrate).
  • the semiconductor device 200B may also be referred as a P-FET 2-stack NS GAA device.
  • Embodiment of the disclosure are in contradistinction to a conventional semiconductor device that requires that same number of stacks of nanosheets to be formed on one or more conventional FETs (i.e., N-FET or P-FET).
  • a conventional semiconductor device may require that 3 stacks of nanosheets are formed on a conventional FET (e.g. N-FET) and another 3 stacks of nanosheets are formed on another conventional FET (e.g. P-FET). Therefore, the conventional semiconductor device lacks in flexibility in the number of stacks of nanosheets (e.g. 3:3) that may be formed on the conventional FETs.
  • the semiconductor device 200 represents a flexibility in the number of stacks of nanosheets (e.g.
  • FIG. 3 is a flowchart of a method for (namely, method of) manufacturing a semiconductor device having one or more field-effect transistors (FETs) formed on a substrate, in accordance with an embodiment of the disclosure.
  • FIG. 3 is described in conjunction with elements from FIGs. 1A, IB, 1C, and 2.
  • a method 300 for manufacturing a semiconductor device having one or more field-effect transistors (FETs) formed on a substrate is executed to form the semiconductor device 100A.
  • the method 300 includes steps 302 and 304.
  • the disclosure provides the method 300 for manufacturing a semicondictor device having one or more field-effect transistors (FETs) formed thereon, wherein the method 300 includes:
  • the method 300 is used for manufacturing the semiconductor device such as the semiconductor devices 100A, 100B, and lOOC with one FET (i.e., the FET 104) or the semiconductor device 200 with two FETs (i.e., the FET 104 and the FET 204).
  • the method 300 includes forming one or more stacks of multiple nano-layers into a plurality of alternate gates and channels in vertical stacks.
  • the FET 104 of the semiconductor device 100A includes the one or more stacks of multiple nano-layers (or nanosheets) in a form of the plurality of alternate gates and channels in vertical stacks.
  • the first gate 106 A, the second gate 106B and the third gate 106C and their associated channels such as the first channel 108A, the second channel 108B and the third channel 108C, respectively, are arranged alternatively in the vertical stack 112 of the FET 104 of the semiconductor device 100A.
  • the method 300 further includes for a given vertical stack (e.g. the vertical stack 112) forming a given FET (e.g. the FET 104), forming a source region (e.g. the source region 114) and a drain region (e.g. the drain region 116) to flank the plurality of alternate gates and channels in the given vertical stack (i.e., the vertical stack 112), wherein at least one of the source region (i.e., the source region 114) and the drain region (i.e., the drain region 116) are epitaxially formed (namely, fabricated) onto a doped layer (e.g. the doped layer 118) that is epitaxially formed onto the substrate (e.g.
  • the FET 104 of the semiconductor device 100A further includes the source region 114 (i.e., S) and the drain region 116 (i.e., D) to form sides of the plurality of alternate gates and channels in the vertical stack 112.
  • the source region 114 and the drain region 116 are epitaxially formed on the doped layer 118.
  • the doped layer 118 e.g. a p-type epitaxial layer
  • the doped layer (i.e., the doped layer 118) is configured to blank-off at least one of the gates and its associated channel in the given vertical stack (i.e., the vertical stack 112) from contributing to conduction between the source region (i.e., the source region 114) and drain regions (i.e., the drain region 116) via the channels when the given FET (i.e., the FET 104) is in operation.
  • the method 300 further includes arranging for the doped layer (i.e., the doped layer 118) to be of a same doping polarity type as that of a region of the substrate (i.e., the substrate 102) on which the given FET (i.e., the FET 104) is formed.
  • the doped layer 118 is of the same doping polarity type (e.g. p-type) as that of the region of the substrate 102 is doped to keep the monocrystalline structure of the substrate 102 and to communicate the crystallographic orientation of the substrate 102 to the source region 114 (i.e., S) and the drain region 116 (i.e., D).
  • the method 300 further includes forming the doped layer (i.e., the doped layer 118) epitaxially from at least one of: Si, SiGe, GeSn, Ge and GaAs.
  • the doped layer 118 is formed epitaxially over the substrate 102 from one of the Silicon (Si), Silicon-Germanium (SiGe), Germanium- Stannum (GeSn), Germanium (Ge) and Gallium- Arsenide (GaAs).
  • the method 300 further includes forming (namely, fabricating) the substrate (i.e., the substrate 102) to include at least one n-type region and at least one p-type region, wherein a portion of the one or more FETs are formed as p-type FETs onto the at least one n-type region, and another portion of the one or more FETs are formed as n-type FETs onto the at least one p-type region.
  • the substrate 102 may include both one or more n-type regions and one or more p-type regions as well. In the one or more n-type regions of the substrate 102, the portion of the one or more FETs are fabricated as the p-type FETs. Similarly, in the one or more p-type regions of the substrate 102, the portion of the one or more FETs are fabricated as the n-type FETs.
  • the method 300 further includes arranging for each conducting layer of the multiple layers in the given vertical stack (i.e., the vertical stack 112) to have a thickness in a direction that is orthogonal to a plane of the substrate (i.e., the substrate 102) that is in a range of 1 nm to 20 nm.
  • Each conducting layer of the multiple nano layers or multiple stacks of nanosheets (NS) in the vertical stack 112 of the FET 104 has the thickness in the direction that is orthogonal to the plane of the substrate 102.
  • each conducting layer may be 1 nanometer (nm), 3 nm, sub-3 nm, 5 nm, 7 nm, 9 nm, 11 nm, 13 nm, 15 nm, 17 nm, 19 nm or 20 nm.
  • the method 300 further includes forming the one or more FETs as gate-all-around (GAA) structures.
  • the FET 104 is formed on the substrate 102 in such a way that the first gate 106 A, the second gate 106B and the third gate 106C surround the first channel 108A, the second channel 108B and the third channel 108C, respectively.
  • the one or more FETs are formed on the substrate 102 hence, the one or more FETs manifest the gate-all-around (GAA) structures.
  • the method 300 further includes forming the one more more FETs to be a FinFET elongate structure arrangement, wherein an elongate axis of the one or more FETs is parallel to a plane of the substrate (i.e., the substrate 102), and is orthogonal to a conduction direction from the source region (i.e., the source region 114) to the drain region (i.e., the drain region 116).
  • the one or more FETs manifest the FinFET elongate structure arrangement with the elongate axis.
  • the elongate axis of the one or more FETs is parallel to the plane of the substrate 102 and is orthogonal (or perpendicular) to the conduction direction from the source region 114 (i.e., S) to the drain region 116 (i.e., D).
  • the method 300 further includes configuring the doped layer (i.e., the doped layer 118) to isolate from the one or more FETs one or more layers of the given vertical stack (i.e., the vertical stack 112) that are closest to the substrate (i.e., the substrate 102).
  • the doped layer 118 is configured to electrically isolate the one or more layers or nanosheets (NS) of the vertical stack 112 that are close to the substrate 102 from the one or more FETs.
  • the doped layer 118 electrically isolates the first gate 106 A alongwith the first channel 108 A and the second gate 106B alongwith the second channel 108B in order to maintain the channel stress (or the stress between the source region 114 and the drain region 116) of the semiconductor device 100A.
  • the method 300 further includes forming the one or more FETs to be Silicon-based devices.
  • the one or more FETs are made up of Silicon (Si) semiconductor material.
  • the method 300 achieves all the advantages and effects of the semiconductor device
  • FIGs. 4A-4H collectively represent a method for (namely, method of) manufacturing a semiconductor device with multiple choice of stack number on two N-FETs, in accordance with an embodiment of the disclosure.
  • FIGs. 4A-4H are described in conjunction with elements from FIGs. 1A, IB, 1C, 2, and 3.
  • a method 400 for (namely, method of) manufacturing a semiconductor device with multiple choice of stack number on two N-FETs includes steps 402 to 416.
  • the method 400 collectively describes the steps of manufacturing a GAA device 400A with 3 stacks of nanosheets formed on a N-FET such as the FET 104 (of FIG. 1 A) and another GAA device 400B with 2 stacks of nanosheets formed on another N-FET that is same as the FET 104.
  • Each step of the method 400 is represented by a dashed rectangular box in each of the FIGs. 4A-4H, that is used for illustration purpose only.
  • each of the GAA devices 400A and 400B is represented by a dashed rectangular box, which is used for illustration purpose only and do not form a part of circuitry.
  • the FET 104 (i.e., N-FET) is formed on the substrate 102 (i.e., doped with p-type impurity in Silicon substrate).
  • the FET 104 includes a first self aligned contact (SAC) layer 418A, a second SAC layer 418B and a third SAC layer 418C.
  • the FET 104 further includes the first channel 108A, the second channel 108B, the third channel 108C and a dummy layer 420.
  • the first SAC layer 418A, the second SAC layer 418B and the third SAC layer 418C collectively, may be described as a protective dielectric layer formed over a gate (e.g. the first gate 106A, the second gate 106B or the third gate 106C of the FET 104, not shown here) in order to prevent contact-to-gate short.
  • a gate e.g. the first gate 106A, the second gate 106B or the third gate 106C of the FET 104, not shown here
  • each of the first SAC layer 418A, the second SAC layer 418B and the third SAC layer 418C is made up of an oxide, or a nitride or a high-k dielectric material.
  • the first SAC layer 418A, the second SAC layer 418B, the third SAC layer 418C, the first channel 108A, the second channel 108B, the third channel 108C are arranged alternatively in the vertical stack 112 with the dummy layer 420 at the top.
  • the dummy layer 420 may be defined as a protective layer or an isolation layer. Similar processing is carried out in the 2-stack GAA device 400B till inner spacer formation.
  • the doped layer 118 is epitaxially formed on the substrate 102.
  • the doped layer 118 is epitaxially formed on the substrate 102.
  • the doped layer 118 is configured to balnk-off at least one of the first SAC layer 418A, the second SAC layer 418B and the third SAC layer 418C and their associated channels such as the first channel 108A, the second channel 108B and the third channel 108C, in the vertical stack 112 from contributing to electrical conduction when the FET 104 is in operation.
  • the doped layer 118 is doped with an impurity of opposite polarity type as that of the channels such as the first channel 108A, the second channel 108B and the third channel 108C.
  • the doped layer 118 will be doped with a p-type impurity or vice-versa.
  • the 3-stack GAA device 400A may also be referred as a n-type 3 -stack GAA device 400A.
  • the 2-stack GAA device 400B may also be referred as a n-type 2-stack GAA device 400B.
  • a hard mask 422 (also represented as HM) is deposited over the FET 104.
  • the hard mask 422 i.e., HM
  • a lower stack number device such as the 2-stack GAA device 400B from any unwanted processing (e.g. etching).
  • no hard mask is used in a higher stack number device (or devices) such as the 3 -stack GAA device 400A.
  • step 408 selective etching of the doped layer 118 is performed in the 3-stack GAA device 400A (or the higher stack number device).
  • the hard mask 422 is removed from the 2-stack GAA device 400B (or the lower stack number device).
  • the doped layer 118 in each of the 3-stack GAA device 400A and the 2-stack GAA device 400B is exposed for etching.
  • the result is the doped layer 118 is completely removed in the 3-stack GAA device 400A and partially removed in the 2-stack GAA device 400B.
  • the doped layer 118 i.e., partially left
  • the doped layer 118 is used to blank-off the first SAC layer 418A and the first channel 108A from contributing to electrical conduction when the FET 104 is in operation.
  • the source region 114 i.e., S
  • the drain region 116 i.e., D
  • appropriate doping type are epitaxially grown in each of the 3-stack GAA device 400A and the 2-stack GAA device 400B.
  • an excess region 424 is also formed in the 2-stack GAA device
  • planarization e.g. top planarization
  • planarization of the 2-stack GAA device 400B is performed in order to remove the excess region 424 and to obtain suitable dimensions of the epitaxially grown source region 114 (i.e., S) and the drain region 116 (i.e., D).
  • the method 400 provides an easy process for forming (manufacturing) a semiconductor device (i.e., the 3 -stack GAA device 400A and the 2-stack GAA device 400B) with the flexibility in the stack number on one or more FETs. Additionally, the method 400 does not require development of any new epitaxial flow for manufacturing a GAA device with different stack numbers.

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Abstract

A semiconductor device includes a substrate having one or more field-effect transistors (FETs), where a given FET of the one or more FETs includes multiple nano-layers formed into alternate gates and channels in a vertical stack. A source region and a drain region of the given FET flank the vertical stack. At least one of the source region and the drain region of the given FET is epitaxially formed on a doped layer that is epitaxially formed on the substrate. The doped layer is configured to blank-off one or more of the gates and their one or more associated channels in the vertical stack from contributing to conduction between the source region and drain region when the given FET is in operation. The disclosed semiconductor device includes stacks of multiple nano layers with electrical isolation, which results into an improved channel stress and performance-power trade-off design.

Description

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING
SEMICONDUCTOR DEVICE
TECHNICAL FIELD
The disclosure relates generally to the field of semiconductor devices; more specifically, the disclosure relates to a semiconductor device and a method for (namely, a method of) manufacturing the semiconductor device.
BACKGROUND
Generally, a semiconductor device is an electronic device whose functioning is based on electronic properties of a semiconductor material, such as Silicon (Si), Germanium (Ge), Galium Arsende and the like. The semiconductor device is manufactured either as an individual device or as an integrated circuit (IC) device. A well known semiconductor device is named as a metal oxide semiconductor field-effect transistor (MOSFET) that includes a drain terminal, a source terminal and a gate terminal. Another well known semiconductor device with a partially improved performance, is named as a fin field-effect transistor (FinFET) which is a multigate device. Such a FinFET device includes two or more gate terminals which lie on two, or three sides of a channel made by a source terminal and a drain terminal of the FinFET device, hence, the FinFET device manifests somewhat better electrical conduction properties in comparison to the known MOSFET device.
Currently, a gate all around FET (GAAFET) device is proposed as a replacement for the FinFET device or the FinFET -based complementary metal oxide semiconductor (CMOS) logic devices (e.g. as used in contemporary microprocessors, memory cells, etc.). A conventional GAAFET device is a multigate device having a channel made by a source terminal(s) and a drain terminal(s). The conventional GAAFET device is similar in concept to the FinFET device except that multiple gates surround the channel on all sides, which results in partly improved performance of the conventional GAAFET device over the FinFET device. The conventional GAAFET device includes one or more conventional N/P-type devices with multiple stacks of nanosheets (NS) arranged on top of one another. A conventional N-type device is referred to as a semiconductor device, in which majority charge carriers are electrons. Similarly, a conventional P-type device is referred to as a semiconductor device, in which majority charge carriers are holes. The one or more conventional N/P-type devices that are manufactured on a single wafer (i.e., a substrate or a chip) have a same number of stacks of nanosheets. Various methods have been proposed to design the multiple stacks of nanosheets (NS) on the single wafer (i.e., the substrate). A conventional method for designing the multiple stacks of nanosheets (or multiple active stacks) on the single wafer (i.e., the substrate) in a conventional GAAFET device is based on making a physical isolation between the multiple stacks of nanosheets. The physical isolation between the multiple stacks of nanosheets is made by deposition and subsequent etching of a low-k dielectric material. The low-k dielectric material is deposited at first on the single wafer (i.e., the substrate) to block electrical conduction in lower channels of the conventional GAAFET device. Thereafter, the conventional method includes a source and a drain which are epitaxially grown on the low-k dielectric material that results in a loss of channel stress and hence, in a reduced performance of the conventional GAAFET device. The conventional method has another limitation of a poor quality of the source and the drain that are epitaxially formed on the low-k dielectric material. Another conventional method is based on designing the multiple stacks of nanosheets (or multiple active stacks) on the single wafer (or the substrate) by etching out active regions and then regrowing silicon (Si) or silicon-germanium (SiGe) stacks. However, the other conventional method is cost-intensive. Thus, there exists a technical problem of the conventional GAAFET device that has inadequacy in its basic properties with respect to performance and stress in the channel of the source and the drain.
Therefore, in light of the foregoing discussion, there exists a need to overcome the aforementioned drawbacks associated with the conventional methods for (namely, methods of) manufacturing the conventional GAAFET device with the multiple stacks of nanosheets on the same wafer (i.e., the substrate).
SUMMARY
The disclosure seeks to provide an improved semiconductor device that includes a substrate with one or more field-effect transistors (FETs) formed on the substrate. The disclosure further seeks to provide an improved method for (namely, method of) manufacturing the semiconductor device that includes the substrate with the one or more field-effect transistors (FETs) formed on the substrate. The disclosure provides a solution to the existing problem of the conventional GAAFET device that has inadequacy in its basic properties with respect to performance and stress in the channel of the source and the drain. An objective of the disclosure is to provide a solution that overcomes at least partially the problems encountered in the prior art and provides a semiconductor device that includes a substrate with one or more field-effect transistors (FETs) formed on the substrate and further an improved method for (namely, method of) manufacturing the semiconductor device that includes the substrate with the one or more field-effect transistors (FETs) formed on the substrate.
One or more objectives of the disclosure is achieved by the solutions provided in the enclosed independent claims. Advantageous implementations of the disclosure are further defined in the dependent claims.
In one aspect, the disclosure provides a semiconductor device that includes a substrate having one or more field-effect transistors (FETs) formed thereon, wherein a given FET of the one or more FETs includes multiple nano-layers formed into alternate gates and channels in a vertical stack. A source region and a drain region of the given FET flank the vertical stack such that the channels are configured to provide a conduction path between the source region and the drain region depending on a voltage signal applied to the gates. The semiconductor device further includes that one or more of the source region and the drain region of the given FET is epitaxially formed on a doped layer that is epitaxially formed on the substrate, such that a crystallographic orientation of the substrate is communicated via the doped layer to the one or more of the source region and the drain region. The doped layer is configured to blank-off one or more of the gates and their one or more associated channels in the vertical stack from contributing to conduction between the source region and drain region when the given FET is in operation.
The disclosed semiconductor device includes stacks of multiple nano layers (or nanosheets) that are formed on the substrate (or the same substrate) with a flexibility in the number of stacks of nano layers. The disclosed semiconductor device manifests N/P ratio control with an option to have different stack number for N-FETs or P-FETs (e.g. 3:2, 3:1, etc.). Additionally, the disclosed semiconductor device manifests an electrical isolation between stacks of multiple nano layers in contrast to a physical isolation that is made between stacks of multiple nano layers used in a conventional semiconductor device which further results in a loss of channel stress and hence, into a reduced performance of the conventional semiconductor device. Moreover, the disclosed semiconductor device maintains a channel stress (or a stress between the source region and the drain region) that further maintains the performance (or a performance-power trade off design).
In an implementation form, the doped layer is of a same doping polarity type as that of a region of the substrate on which the one or more FETs are formed.
It is advantageous to have the doped layer of the same doping polarity type as that of the region of the substrate on which the one or more FETs are formed in order to keep a monocrystalline structure of the substrate that further results into an improved epitaxial quality of the source region and the drain region.
In a further implementation form, the doped layer is formed epitaxially from one or more of: SiGe, GeSn, Ge and GaAs.
It is advantageous to form the doped layer epitaxially from one of SiGe, GeSn, Ge and GaAs to further improve the epitaxial quality of the source region and the drain region.
In a further implementation form, the substrate includes both at least one n-type region and at least one p-type region, wherein a portion of the one or more FETs are fabricated as p-type FETs onto the at least one n-type region, and another portion of the one or more FETs are fabricated as n-type FETs onto the at least one p-type region.
The disclosed semiconductor device includes both the n-type region and the p-type region on the same substrate therefore, wherein the disclosed semiconductor device further includes the p-type FETs and the n-type FETs and manifests a flexibility in the stack number of multiple nano layers.
In a further implementation form, each conducting layer of the multiple layers in the vertical stack has a thickness in a direction that is orthogonal to a plane of the substrate that is in a range of 1 nm to 20 nm.
It is advantageous to have each conducting layer of the multiple layers has a thickness in the range of lnm to 20 nm in order to have a dense packaging and a reduced size of the disclosed semiconductor device. In a further implementation form, the one or more FETs are fabricated as gate-all-around (GAA) structures.
By virtue of having the one or more FETs as GAA structures, an improved electrical conduction between the source region and the drain region is provided.
In a further implementation form, the one or more FETs are formed to be a FinFET elongate structure arrangement, wherein an elongate axis of the one or more FETs is parallel to a plane of the substrate, and is orthogonal to a conduction direction from the source region to the drain region.
It is advantageous to form the one or more FETs as the FinFET elongate structure arrangement to incorporate simplicity in the disclosed semiconductor device.
In a further implementation form, the doped layer is configured to isolate from the one or more FETs one or more layers of the vertical stack that are closest to the substrate.
The doped layer electrically isolates in the one or more FETs one or more layers of the vertical stack that are closest to the substrate in order to maintain the channel stress (or the stress between the source region and the drain region) that further maintains the performance (or the performance-power trade off design) of the disclosed semiconductor device.
In a further implementation form, the one or more FETs are Silicon-based devices.
It is advantageous to have the one or more FETs as the silicon based devices to enable a reduced power consumption and a reduced size of the disclosed semiconductor device.
In another aspect, the disclosure provides a method for (namely, method of) manufacturing a semicondictor device having one or more field-effect transistors (FETs) formed thereon. The method includes forming one or more stacks of multiple nano-layers into a plurality of alternate gates and channels in vertical stacks. For a given vertical stack forming a given FET, the method further includes forming a source region and a drain region to flank the plurality of alternate gates and channels in the given vertical stack, wherein at least one of the source region and the drain region are epitaxially fabricated onto a doped layer that is epitaxially formed onto the substrate, such that a crystallographic orientation of the substrate is communicated via the doped layer to the at least one of the source region and the drain region. The doped layer is configured to blank-off at least one of the gates and its associated channel in the given vertical stack from contributing to conduction between the source region and drain regions via the channels when the given FET is in operation.
The disclosed method proposes the semiconductor device with stacks of multiple nano layers (or nanosheets) that are formed on the substrate (or the same substrate) with electrical islolation among the multiple nano layers. The disclosed method achieves all the advantages and effects of the disclosed semiconductor device.
It is to be appreciated that all the aforementioned implementation forms can be combined in various ways.
It has to be noted that all devices, elements, circuitry, units and means described in the present application could be implemented in the software or hardware elements or any kind of combination thereof. All steps which are performed by the various entities described in the present application as well as the functionalities described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective software or hardware elements, or any kind of combination thereof. It will be appreciated that features of the disclosure are susceptible to being combined in various combinations without departing from the scope of the disclosure as defined by the appended claims.
Additional aspects, advantages, features and objects of the disclosure would be made apparent from the drawings and the detailed description of the illustrative implementations construed in conjunction with the appended claims that follow.
BRIEF DESCRIPTION OF THE DRAWINGS
The summary above, as well as the following detailed description of illustrative embodiments, is better understood when read in conjunction with the appended drawings. For the purpose of illustrating the disclosure, exemplary constructions of the disclosure are shown in the drawings. However, the disclosure is not limited to specific methods and instrumentalities disclosed herein. Moreover, those in the art will understand that the drawings are not to scale. Wherever possible, like elements have been indicated by identical numbers.
Embodiments of the disclosure will now be described, by way of example only, with reference to the following diagrams wherein:
FIG. 1A is an illustration of a side view of a semiconductor device with one stack of nanosheets formed on a substrate, in accordance with an embodiment of the disclosure;
FIG. IB is an illustration of a side view of a semiconductor device with two stacks of nanosheets formed on the substrate, in accordance with an embodiment of the disclosure;
FIG. 1C is an illustration of a side view of a semiconductor device with three stacks of nanosheets formed on the substrate, in accordance with an embodiment of the disclosure;
FIG. 2 is an illustration of a side view of a semiconductor device with multiple choice of stack number on a N-FET and a P-FET, of the one or more FETs that can be formed on the substrate, in accordance with an embodiment of the disclosure;
FIG. 3 is a flowchart of a method for manufacturing a semiconductor device having one or more field-effect transistors (FETs) formed on the substrate, in accordance with an embodiment of the disclosure; and
FIGs. 4A-4H collectively is a representation of a method for manufacturing a semiconductor device with a multiple choice of stack number on two N-FETs, in accordance with an embodiment of the disclosure.
In the accompanying drawings, an underlined number is employed to represent an item over which the underlined number is positioned or an item to which the underlined number is adjacent. A non-underlined number relates to an item identified by a line linking the non- underlined number to the item. When a number is non-underlined and accompanied by an associated arrow, the non-underlined number is used to identify a general item at which the arrow is pointing.
DETAILED DESCRIPTION OF EMBODIMENTS
The following detailed description illustrates embodiments of the disclosure and ways in which they can be implemented. Although some modes of carrying out the disclosure have been disclosed, those skilled in the art would recognize that other embodiments for carrying out or practicing the disclosure are also possible. In FIG. 1 A, there is shown a side view illustration of a semiconductor device with one stack of nanosheets formed on a substrate, in accordance with an embodiment of the disclosure. With reference to FIG. 1 A, there is shown a side view of a semiconductor device 100A that includes a substrate 102 and a field effect transistor (FET) 104 formed on the substrate 102. The FET 104 includes a first gate 106 A, a second gate 106B, a third gate 106C, a first channel 108 A, a second channel 108B, a third channel 108C, and a top gate 110. The FET 104 further includes a plurality of side pockets 109. The plurality of side pockets 109 is associated with the first gate 106 A, the second gate 106B, and the third gate 106C. Each of the first gate 106 A, the second gate 106B, the third gate 106C, the first channel 108 A, the second channel 108B, the third channel 108C, and the top gate 110 of the FET 104 are arranged in a vertical stack 112. The gates 106A, 106B, 106C are isolated from the channels 108A, 108B, 108C by a thin layer of oxide or high-k, for example in a range of circa 0.1 nm to 2 nm thick; this thin layer of oxide or high-k is not shown on FIG. 1A. The FET 104 further incudes a source region 114, a drain region 116, a doped layer 118 and a contact (CNT) 120. Each of the FET 104, the vertical stack 112, the source region 114 and the drain region 116 is represented by a dashed-line rectangular box; the box is used for illustration purpose only and does not form a part of circuitry of the field effect transistor (FET) 104.
The substrate 102 may also be referred as a single wafer or a chip. The substrate 102 is made up of a semiconductor material such as, silicon (Si) or germanium (Ge) and the like. In the semiconductor material of the substrate 102, a p-type dopant is added. Therefore, the substrate 102 may also be referred as a p-type semiconductor. Generally, a p-type semiconductor is one in which majority charge carriers are holes. Examples of the p-type dopants are, but not limited to, Boron (B), Indium (In), and the like. The substrate 102 may also have an isolation property. In another embodiment, the substrate 102 may have n-type doping hence, may be referred as a n-type semiconductor. Generally, a n-type semiconductor is one in which majority charge carriers are electrons. Examples of the n-type semiconductor are, but not limited to, Phosphorus (P), Arsenic (As), Antimony (Sb), and the like.
The FET 104 is a transistor which uses an electric field to control a flow of current. The FET 104 is configured to control the flow of current by applying a voltage signal to the first gate 106A, the second gate 106B, and the third gate 106C that results into conductivity beween the source region 114 and the drain region 116. In the semiconductor device 100A, the substrate 102 is the p-type semiconductor, therefore, the FET 104 that is formed on the substrate 102 is an n-type FET (or N-FET). In another case, when the substrate 102 is of the n-type semiconductor, the FET 104 will be a p-type FET (or P-FET). A semiconductor device with the n-type FET (or N-FET) and the p-type FET (or P-FET) is described in detail, for example, in FIG. 2.
The semiconductor device 100A includes the substrate 102 having one or more field-effect transistors (FETs) formed thereon, wherein a given FET 104 of the one or more FETs includes multiple nano-layers formed into alternate gates and channels in the vertical stack 112. The first gate 106 A, the second gate 106B, the third gate 106C, the first channel 108 A, the second channel 108B, and the third channel 108C of the FET 104 together form the alternate gates and the channels, respectively, in the vertical stack 112. Alternatively stated, the first gate 106A, the second gate 106B, the third gate 106C, the first channel 108 A, the second channel 108B, and the third channel 108C of the FET 104 are arranged alternatively with respect to each other. For example, the first channel 108A is arranged over the first gate 106A and the second gate 106B is arranged over the first channel 108A but below the second channel 108B. Similarly, the third gate 106C is arranged over the second channel 108B but below the third channel 108C. At last, the top gate 110 is arranged over the third channel 108C in the vertical stack 112. The first gate 106A alongwith the first channel 108A represents one stack of nanosheet. Similarly, the first gate 106A alongwith the first channel 108A, the second gate 106B alongwith the second channel 108B and the third gate 106C alongwith the third channel 108C, may also be referred as the multiple nano-layers or multiple stacks (e.g. 3 stacks) of nanosheets (NS) of the FET 104. The given FET may also be referred as the FET 104. Additionally, the plurality of side pockets 109 associated with the first gate 106A, the second gate 106B, and the third gate 106C is made up of dielectric materials (e.g. an oxide or nitride or high-k) and used for insulation purposes.
The source region 114 and the drain region 116 of the given FET 104 flank the vertical stack 112 such that the channels are configured to provide a conduction path between the source region 114 and the drain region 116 depending on a voltage signal applied to the gates. The source region 114 (also represented as S) and the drain region 116 (also represented as D) of the FET 104 form the sides (e.g. a left side and a right side) of the vertical stack 112 in such a way that the first channel 108A, the second channel 108B and the third channel 108C provide the conduction path between the source region 114 (i.e., S) and the drain region 116 (i.e., D). The source region 114 (i.e., S) and the drain region 116 (i.e., D) are formed by n-type doping into the Silicon (Si) or Germanium (Ge) or Silion-Germanium (SiGe) semiconductor material. Therefore, the source region 114 (i.e., S) and the drain region 116 (i.e., D) may also be referred as n-type semiconductor. The source region 114 (i.e., S) and the drain region 116 (i.e., D) may be one or more in the FET 104.
One or more of the source region 114 and the drain region 116 of the given FET 104 is epitaxially formed on the doped layer 118 that is epitaxially formed on the substrate 102, such that a crystallographic orientation of the substrate 102 is communicated via the doped layer 118 to the one or more of the source region 114 and the drain region 116. The one or more of the source region 114 (i.e., S) and the drain region 116 (i.e., D) of the FET 104 is epitaxially (or in an ordered manner) formed on the doped layer 118 to maintain a monocrystalline structure of the substrate 102. In the semiconductor device 100A, the doped layer 118 is a p-type layer that is epitaxially formed on the substrate 102 to communicate the crystallographic orientation of the substrate 102 to the at least one of the source region 114 (i.e., S) and the drain region 116 (i.e., D). In this way, the one or more of the source region 114 and the drain region 116 have the same crystallographic orientation as the substrate 102. This means that planar indices of one or more lattice planes of the substrate 102 and the one or more of the source region 114 and the drain region 116 are the same. The doped layer 118 may also be referred as a p-type epitaxial (or p-type epi) layer.
The doped layer 118 is configured to blank-off one or more of the gates and their one or more associated channels in the vertical stack 112 from contributing to conduction between the source region 114 and drain region 116 when the given FET 104 is in operation. When the FET 104 is in operation, the doped layer 118 (or p-type epi) blocks the first gate 106A and the second gate 106B and their associated channels such as the first channel 108A and the second channel 108B as well, from full or parital conduction. In other words, the doped layer 118 electrically isolates the first gate 106A and the associated first channel 108A and the second gate 106B and the associated second channel 108B in contrast to a conventional physical isolation which result in loss of channel stress and hence, loss of performance of a conventional semiconductor device. Due to electrical isolation of the first gate 106A and the second gate 106B and their associated channels such as the first channel 108A and the second channel 108B, a channel stress (or a stress between the source region 114 and the drain region 116) is maintained and hence, the performance (or a performance-power trade off design) of the semiconductor device 100A is maintained.
In accordance with an embodiment, the doped layer 118 is of a same doping polarity type as that of a region of the substrate 102 on which the one or more FETs are formed. The doped layer 118 is of the same doping polarity type (e.g. p-type) as that of the region of the substrate 102 is doped to keep the monocrystalline structure of the substrate 102 and to communicate the crystallographic orientation of the substrate 102 to the source region 114 (i.e., S) and the drain region 116 (i.e., D).
In accordance with an embodiment, the doped layer 118 is formed epitaxially from one or more of: SiGe, GeSn, Ge and GaAs. The doped layer 118 is formed epitaxially over the substrate 102 from one of the Silicon-Germanium (SiGe), Germanium- Stannum (GeSn), Germanium (Ge) and Gallium- Arsenide (GaAs).
In accordance with an embodiment, the substrate 102 includes both at least one n-type region and at least one p-type region, wherein a portion of the one or more FETs are fabricated as p- type FETs onto the at least one n-type region, and another portion of the one or more FETs are fabricated as n-type FETs onto the at least one p-type region. In an implementation, the substrate 102 may include both one or more n-type regions and one or more p-type regions as well. In the one or more n-type regions of the substrate 102, the portion of the one or more FETs are fabricated as the p-type FETs. Similarly, in the one or more p-type regions of the substrate 102, the portion of the one or more FETs are fabricated as the n-type FETs. In the semiconductor device 100A, the substrate 102 includes the at least one p-type region and the FET 104 that is fabricated on the substrate 102 is of the n-type (or N-FET).
In accordance with an embodiment, each conducting layer of the multiple layers in the vertical stack 112 has a thickness in a direction that is orthogonal to a plane of the substrate 102 that is in a range of 1 nm to 20 nm. Each conducting layer of the multiple nano layers or multiple stacks of nanosheets (NS) in the vertical stack 112 of the FET 104 has the thickness in the direction that is orthogonal to the plane of the substrate 102. The thickness of each conducting layer may be 1 nanometer (nm), 3 nm, sub-3 nm, 5 nm, 7 nm, 9 nm, 11 nm, 13 nm, 15 nm, 17 nm, 19 nm or 20 nm.
In accordance with an embodiment, the one or more FETs are fabricated as gate-all-around (GAA) structures. The FET 104 is formed on the substrate 102 in such a way that the first gate 106 A, the second gate 106B and the third gate 106C surround the first channel 108 A, the second channel 108B and the third channel 108C, respectively. Similarly, the one or more FETs are formed on the substrate 102, hence, the one or more FETs manifest the gate-all-around (GAA) structures. In accordance with an embodiment, the one or more FETs are formed to be a FinFET elongate structure arrangement, wherein an elongate axis of the one or more FETs is parallel to a plane of the substrate 102, and is orthogonal to a conduction direction from the source region 114 to the drain region 116. The one or more FETs manifest the FinFET elongate structure arrangement with the elongate axis. The elongate axis of the one or more FETs is parallel to the plane of the substrate 102 and is orthogonal (or perpendicular) to the conduction direction from the source region 114 (i.e., S) to the drain region 116 (i.e., D).
In accordance with an embodiment, the doped layer 118 is configured to isolate from the one or more FETs one or more layers of the vertical stack 112 that are closest to the substrate 102. The doped layer 118 is configured to electrically isolate the one or more layers or nanosheets (NS) of the vertical stack 112 that are close to the substrate 102 from the one or more FETs. In the semiconductor device 100A, the doped layer 118 electrically isolates the first gate 106A alongwith the first channel 108 A and the second gate 106B along with the second channel 108B in order to maintain the channel stress (or the stress between the source region 114 and the drain region 116) that further maintains the performance (or the performance-power trade off design) of the semiconductor device 100A. In this way, the semiconductor device 100A manifests one stack of nanosheets that is the third gate 106C and the third channel 108C to provide the electrical conduction between the source region 114 (i.e., S) and the drain region 116 (i.e., D).
In accordance with an embodiment, the one or more FETs are Silicon-based devices. In the semiconductor device 100A, the one or more FETs are made up of Silicon (Si) semiconductor material.
Thus, the semiconductor device 100A includes the FET 104 of the one or more FETs formed on the substrate 102. The FET 104 includes the multiple nano layers or multiple (e.g. 3) stacks of nanaosheets (NS) formed into the alternate gates and the channels. For example, the FET 104 includes the first gate 106 A, the second gate 106B, the third gate 106C and the first channel 108 A, the second channel 108B and the third channel 108C which are alternatively arranged in the vertical stack 112. Additionally, the first gate 106A, the second gate 106B and the third gate 106C surround the first channel 108A, the second channel 108B and the third channel 108C hence, the semiconductor device 100A may also be referred as a GAA device. The FET 104 further includes the doped layer 118 on which the source region 114 (i.e., S) and the drain region 116 (i.e., D) are epitaxially formed. The doped layer 118 is formed of the same polarity type as that of the region of the substrate 102 on which the one or more FETs are formed to keep the monocrystalline nature of the substrate 102 and to communicate the crystallographic orientation of the substrate 102 to the source region 114 (i.e., S) and the drain region 116 (i.e., D). Therefore, the semiconductor device 100A provides an improved epitaxial quality of the source region 114 (i.e., S) and the drain region 116 (i.e., D). Moreover, the doped layer 118 electrically isolates the first gate 106A and the second gate 106B and their associated channels such as the first channel 108A and the second channel 108B as well, in order to maintain the channel stress (or the stress between the source region 114 and the drain region 116) that further maintains the performance (or the performance-power trade off design) of the semiconductor device 100A. The electrical conduction between the source region 114 (i.e., S) and the drain region 116 (i.e., D) takes place only through one stack that is the third gate 106C and the third channel 108C. Therefore, the semiconductor device 100A may also be referred as a N-FET 1 -stack nanosheet (NS) GAA device.
In FIG. IB, there is shown a side view illustration of a semiconductor device with two stack of nanosheets formed on the substrate, in accordance with an embodiment of the disclosure. FIG. IB is described in conjunction with elements from FIG. 1A. With reference to FIG. IB, there is shown a side view of a semiconductor device 100B.
The semiconductor device 100B is similar to the semiconductor device 100A except that the doped layer 118 blanks-off the first gate 106A and the first channel 108A instead of the first gate 106A, the second gate 106B, the first channel 108A and the second channel 108B, as obtained in the semiconductor device 100A. Thus, the semiconductor device 100B manifests two stacks of nanosheets (NS), namely the second gate 106B alongwith the second channel 108B and the third gate 106C alongwith the third channel 108C to provide the electrical conduction between the source region 114 (i.e., S) and the drain region 116 (i.e., D). Therefore, the semiconductor device 100B may also be referred as a N-FET 2-stack NS GAA device.
In FIG. 1C, there is shown a side view illustration of a semiconductor device with two stacks of nanosheets formed on the substrate, in accordance with an embodiment of the disclosure. FIG. 1C is described in conjunction with elements from FIGs. 1A and IB. With reference to FIG. 1C, there is shown a side view of a semiconductor device lOOC.
The semiconductor device lOOC is similar to the semiconductor device 100A except that the semiconductor device lOOC manifests three stacks of nanosheets (NS), namely the first gate 106A alongwith the first channel 108A, the second gate 106B alongwith the second channel 108B and the third gate 106C alongwith the third channel 108C to provide the electrical conduction between the source region 114 (i.e., S) and the drain region 116 (i.e., D). Therefore, the semiconductor device lOOC may also be referred as a N-FET 3-stack NS GAA device. In the semiconductor device lOOC, the doped layer 118 is completely removed.
Thus, the semiconductor devices 100A, 100B and lOOC collectively represents a flexibility in the number of stacks of nanosheets that can be formed on the substrate 102. This in turn provides a flexibility in the performance-power trade off design of the semiconductor devices 100A, 100B and lOOC. Optionally, the number of stacks of nanosheets that can be formed on the substrate 102 can further be increased depending on requirements. Moreover, the semiconductor devices 100A, 100B and lOOC manifest N/P ratio control with an option to have different stack numbers for N-FET or P-FET (e.g. 3:2, 3:1, etc.). Alternatively stated, a semiconductor device can be manufactured in such a way that the semiconductor device may have 3 stacks of nanosheets formed on a N-FET along with 2 stacks of nanosheets on a P-FET, of the one or more FETs that can be formed on the substrate 102. An example of such semiconductor device is described in detail, for example, with reference to FIG. 2.
In FIG. 2, there is shown a side view illustration of a semiconductor device with a multiple choice of stack numbers on a N-FET and a P-FET, of the one or more FETs that can be formed on a substrate, in accordance with an embodiment of the disclosure. FIG. 2 is described in conjunction with elements from FIGs. 1 A, IB, and 1C. With reference to FIG. 2, there is shown a side view of a semiconductor device 200 that includes a semiconductor device 200A and another semiconductor device 200B. Each of the semiconductor devices 200, 200A, and 200B is represented by a dashed rectangular box, which is used for illustration purpose only and do not form a part of circuitry.
The semiconductor device 200A corresponds to the semiconductor device lOOC (of FIG. 1C). The semiconductor device 200A is named as a N-FET 3-stack NS GAA device. The semiconductor device 200 A includes 3 stacks of nanosheets of the FET 104 formed on the substrate 102.
The semiconductor device 200B includes a substrate 202, a FET 204, a first gate 206A, a second gate 206B, a third gate 206C, a first channel 208A, a second channel 208B, a third channel 208C, a plurality of side pockets 209, a top gate 210, a vertical stack 212, a source region 214, a drain region 216, a doped layer 218 and a contact 220. The substrate 202 corresponds to the substrate 102 (of FIG. 1A) except that the substrate 202 is doped with a n-type impurity, hereinafter referred as the n-type semiconductor. Similarly, the FET 204 corresponds to the FET 104 except that the FET 204 is a P-FET. Each of the first gate 206A, the second gate 206B, the third gate 206C, the first channel 208A, the second channel 208B, the third channel 208C, the plurality of side pockets 209, the top gate 210, the vertical stack 212 and the contact 220 of the semiconductor device 200B corresponds to the first gate 106 A, the second gate 106B, the third gate 106C, the first channel 108 A, the second channel 108B, the third channel 108C, the plurality of side pockets 109, the top gate 110, the vertical stack 112 and the contact 120 of the semiconductor device 100B (of FIG. IB), respectively.
The source region 214 (also represented as S) and the drain region 216 (also represented as D) corresponds to the source region 114 and the drain region 116 (of FIG. IB), respectively, except that the source region 214 (i.e., S) and the drain region 216 (i.e., D) are formed by p-type doping into the Silicon-Germanium (SiGe) semiconductor material. Therefore, the source region 214 (i.e., S) and the drain region 216 (i.e., D) may also be referred as p-type semiconductor. The source region 214 (i.e., S) and the drain region 216 (i.e., D) may be one or more that are epitaxially grown on the doped layer 218 in the FET 204.
Simlarly, the doped layer 218 corresponds to the doped layer 118 except that the doped layer 218 is a n-type layer that is epitaxially formed on the substrate 202 to communicate the crystallographic orientation of the substrate 202 to at least one of the source region 214 (i.e., S) and the drain region 216 (i.e., D). The doped layer 218 may also be referred as a n-type epitaxial (or n-type epi) layer. The doped layer 218 blank-off the first gate 206 A and the first channel 208A. Thus, the semiconductor device 200B manifests two stacks of nanosheets (NS) that is the second gate 206B alongwith the second channel 208B and the third gate 206C alongwith the third channel 208C to provide the electrical conduction between the source region 214 (i.e., S) and the drain region 216 (i.e., D). Therefore, the semiconductor device 200B corresponds to the semiconductor device 100B (of FIG. IB) except that the semiconductor device 200B includes 2 stacks of nanosheets of the FET 204 (i.e., P-FET) formed on the substrate 202 (i.e., n-type substrate). The semiconductor device 200B may also be referred as a P-FET 2-stack NS GAA device.
Embodiment of the disclosure are in contradistinction to a conventional semiconductor device that requires that same number of stacks of nanosheets to be formed on one or more conventional FETs (i.e., N-FET or P-FET). For example, a conventional semiconductor device may require that 3 stacks of nanosheets are formed on a conventional FET (e.g. N-FET) and another 3 stacks of nanosheets are formed on another conventional FET (e.g. P-FET). Therefore, the conventional semiconductor device lacks in flexibility in the number of stacks of nanosheets (e.g. 3:3) that may be formed on the conventional FETs. However, the semiconductor device 200 represents a flexibility in the number of stacks of nanosheets (e.g. 3:2) that may be formed on the FET 104 (i.e., N-FET) and the FET 204 (i.e., P-FET), respectively. For example, the FET 104 (i.e., N-FET) of the semiconductor device 200A includes 3 stacks of nanosheets and the FET 204 (i.e., P-FET) of the semiconductor device 200B includes 2 stacks of nanosheets. FIG. 3 is a flowchart of a method for (namely, method of) manufacturing a semiconductor device having one or more field-effect transistors (FETs) formed on a substrate, in accordance with an embodiment of the disclosure. FIG. 3 is described in conjunction with elements from FIGs. 1A, IB, 1C, and 2. With reference to FIG. 3, there is shown a method 300 for manufacturing a semiconductor device having one or more field-effect transistors (FETs) formed on a substrate. The method 300 is executed to form the semiconductor device 100A. The method 300 includes steps 302 and 304.
The disclosure provides the method 300 for manufacturing a semicondictor device having one or more field-effect transistors (FETs) formed thereon, wherein the method 300 includes:
(i) forming one or more stacks of multiple nano-layers into a plurality of alternate gates and channels in vertical stacks;
(ii) for a given vertical stack forming a given FET, forming a source region and a drain region to flank the plurality of alternate gates and channels in the given vertical stack, wherein at least one of the source region and the drain region are epitaxially fabricated onto a doped layer that is epitaxially formed onto the substrate, such that a crystallographic orientation of the substrate is communicated via the doped layer to the at least one of the source region and the drain region; wherein the doped layer is configured to blank-off at least one of the gates and its associated channel in the given vertical stack from contributing to conduction between the source region and drain regions via the channels when the given FET is in operation. The method 300 for manufacturing a semicondictor device having one or more field-effect transistors (FETs) formed thereon. The method 300 is used for manufacturing the semiconductor device such as the semiconductor devices 100A, 100B, and lOOC with one FET (i.e., the FET 104) or the semiconductor device 200 with two FETs (i.e., the FET 104 and the FET 204).
At the step 302, the method 300 includes forming one or more stacks of multiple nano-layers into a plurality of alternate gates and channels in vertical stacks. For example, the FET 104 of the semiconductor device 100A includes the one or more stacks of multiple nano-layers (or nanosheets) in a form of the plurality of alternate gates and channels in vertical stacks. Alternatively stated, the first gate 106 A, the second gate 106B and the third gate 106C and their associated channels such as the first channel 108A, the second channel 108B and the third channel 108C, respectively, are arranged alternatively in the vertical stack 112 of the FET 104 of the semiconductor device 100A.
At the step 304, the method 300 further includes for a given vertical stack (e.g. the vertical stack 112) forming a given FET (e.g. the FET 104), forming a source region (e.g. the source region 114) and a drain region (e.g. the drain region 116) to flank the plurality of alternate gates and channels in the given vertical stack (i.e., the vertical stack 112), wherein at least one of the source region (i.e., the source region 114) and the drain region (i.e., the drain region 116) are epitaxially formed (namely, fabricated) onto a doped layer (e.g. the doped layer 118) that is epitaxially formed onto the substrate (e.g. the substrate 102), such that a crystallographic orientation of the substrate (i.e., the substrate 102) is communicated via the doped layer (e.g. doped layer 118) to the at least one of the source region (i.e., the source region 114) and the drain region (i.e., the drain region 116). The FET 104 of the semiconductor device 100A further includes the source region 114 (i.e., S) and the drain region 116 (i.e., D) to form sides of the plurality of alternate gates and channels in the vertical stack 112. The source region 114 and the drain region 116 are epitaxially formed on the doped layer 118. The doped layer 118 (e.g. a p-type epitaxial layer) is also epitaxially grown on the substrate 102 to keep the monocrystalline structure of the substrate 102.
The doped layer (i.e., the doped layer 118) is configured to blank-off at least one of the gates and its associated channel in the given vertical stack (i.e., the vertical stack 112) from contributing to conduction between the source region (i.e., the source region 114) and drain regions (i.e., the drain region 116) via the channels when the given FET (i.e., the FET 104) is in operation.
In accordance with an embodiment, the method 300 further includes arranging for the doped layer (i.e., the doped layer 118) to be of a same doping polarity type as that of a region of the substrate (i.e., the substrate 102) on which the given FET (i.e., the FET 104) is formed. The doped layer 118 is of the same doping polarity type (e.g. p-type) as that of the region of the substrate 102 is doped to keep the monocrystalline structure of the substrate 102 and to communicate the crystallographic orientation of the substrate 102 to the source region 114 (i.e., S) and the drain region 116 (i.e., D).
In accordance with an embodiment, the method 300 further includes forming the doped layer (i.e., the doped layer 118) epitaxially from at least one of: Si, SiGe, GeSn, Ge and GaAs. The doped layer 118 is formed epitaxially over the substrate 102 from one of the Silicon (Si), Silicon-Germanium (SiGe), Germanium- Stannum (GeSn), Germanium (Ge) and Gallium- Arsenide (GaAs).
In accordance with an embodiment, the method 300 further includes forming (namely, fabricating) the substrate (i.e., the substrate 102) to include at least one n-type region and at least one p-type region, wherein a portion of the one or more FETs are formed as p-type FETs onto the at least one n-type region, and another portion of the one or more FETs are formed as n-type FETs onto the at least one p-type region. In an implementation, the substrate 102 may include both one or more n-type regions and one or more p-type regions as well. In the one or more n-type regions of the substrate 102, the portion of the one or more FETs are fabricated as the p-type FETs. Similarly, in the one or more p-type regions of the substrate 102, the portion of the one or more FETs are fabricated as the n-type FETs.
In accordance with an embodiment, the method 300 further includes arranging for each conducting layer of the multiple layers in the given vertical stack (i.e., the vertical stack 112) to have a thickness in a direction that is orthogonal to a plane of the substrate (i.e., the substrate 102) that is in a range of 1 nm to 20 nm. Each conducting layer of the multiple nano layers or multiple stacks of nanosheets (NS) in the vertical stack 112 of the FET 104 has the thickness in the direction that is orthogonal to the plane of the substrate 102. The thickness of each conducting layer may be 1 nanometer (nm), 3 nm, sub-3 nm, 5 nm, 7 nm, 9 nm, 11 nm, 13 nm, 15 nm, 17 nm, 19 nm or 20 nm. In accordance with an embodiment, the method 300 further includes forming the one or more FETs as gate-all-around (GAA) structures. The FET 104 is formed on the substrate 102 in such a way that the first gate 106 A, the second gate 106B and the third gate 106C surround the first channel 108A, the second channel 108B and the third channel 108C, respectively. Similarly, the one or more FETs are formed on the substrate 102 hence, the one or more FETs manifest the gate-all-around (GAA) structures.
In accordance with an embodiment, the method 300 further includes forming the one more more FETs to be a FinFET elongate structure arrangement, wherein an elongate axis of the one or more FETs is parallel to a plane of the substrate (i.e., the substrate 102), and is orthogonal to a conduction direction from the source region (i.e., the source region 114) to the drain region (i.e., the drain region 116). The one or more FETs manifest the FinFET elongate structure arrangement with the elongate axis. The elongate axis of the one or more FETs is parallel to the plane of the substrate 102 and is orthogonal (or perpendicular) to the conduction direction from the source region 114 (i.e., S) to the drain region 116 (i.e., D).
In accordance with an embodiment, the method 300 further includes configuring the doped layer (i.e., the doped layer 118) to isolate from the one or more FETs one or more layers of the given vertical stack (i.e., the vertical stack 112) that are closest to the substrate (i.e., the substrate 102). The doped layer 118 is configured to electrically isolate the one or more layers or nanosheets (NS) of the vertical stack 112 that are close to the substrate 102 from the one or more FETs. In the semiconductor device 100A, the doped layer 118 electrically isolates the first gate 106 A alongwith the first channel 108 A and the second gate 106B alongwith the second channel 108B in order to maintain the channel stress (or the stress between the source region 114 and the drain region 116) of the semiconductor device 100A.
In accordance with an embodiment, the method 300 further includes forming the one or more FETs to be Silicon-based devices. In the semiconductor device 100A, the one or more FETs are made up of Silicon (Si) semiconductor material.
Thus, the method 300 achieves all the advantages and effects of the semiconductor device
100A.
The steps 302 and 304 are only illustrative and other alternatives can also be provided where one or more steps are added, one or more steps are removed, or one or more steps are provided in a different sequence without departing from the scope of the claims herein. FIGs. 4A-4H collectively represent a method for (namely, method of) manufacturing a semiconductor device with multiple choice of stack number on two N-FETs, in accordance with an embodiment of the disclosure. FIGs. 4A-4H are described in conjunction with elements from FIGs. 1A, IB, 1C, 2, and 3. With reference to FIGs. 4A-4H, there is shown a method 400 for (namely, method of) manufacturing a semiconductor device with multiple choice of stack number on two N-FETs. The method 400 includes steps 402 to 416.
The method 400 collectively describes the steps of manufacturing a GAA device 400A with 3 stacks of nanosheets formed on a N-FET such as the FET 104 (of FIG. 1 A) and another GAA device 400B with 2 stacks of nanosheets formed on another N-FET that is same as the FET 104. Each step of the method 400 is represented by a dashed rectangular box in each of the FIGs. 4A-4H, that is used for illustration purpose only. Additionally, each of the GAA devices 400A and 400B is represented by a dashed rectangular box, which is used for illustration purpose only and do not form a part of circuitry.
With referene to FIG. 4A, at the step 402, in the 3-stack GAA device 400A, the FET 104 (i.e., N-FET) is formed on the substrate 102 (i.e., doped with p-type impurity in Silicon substrate). The FET 104 includes a first self aligned contact (SAC) layer 418A, a second SAC layer 418B and a third SAC layer 418C. The FET 104 further includes the first channel 108A, the second channel 108B, the third channel 108C and a dummy layer 420. The first SAC layer 418A, the second SAC layer 418B and the third SAC layer 418C collectively, may be described as a protective dielectric layer formed over a gate (e.g. the first gate 106A, the second gate 106B or the third gate 106C of the FET 104, not shown here) in order to prevent contact-to-gate short. Moreover, each of the first SAC layer 418A, the second SAC layer 418B and the third SAC layer 418C is made up of an oxide, or a nitride or a high-k dielectric material. The first SAC layer 418A, the second SAC layer 418B, the third SAC layer 418C, the first channel 108A, the second channel 108B, the third channel 108C are arranged alternatively in the vertical stack 112 with the dummy layer 420 at the top. The dummy layer 420 may be defined as a protective layer or an isolation layer. Similar processing is carried out in the 2-stack GAA device 400B till inner spacer formation.
With referene to FIG. 4B, at the step 404, in the 3 -stack GAA device 400A, the doped layer 118 is epitaxially formed on the substrate 102. Similarly, in the 2-stack GAA device 400B, the doped layer 118 is epitaxially formed on the substrate 102. The doped layer 118 is configured to balnk-off at least one of the first SAC layer 418A, the second SAC layer 418B and the third SAC layer 418C and their associated channels such as the first channel 108A, the second channel 108B and the third channel 108C, in the vertical stack 112 from contributing to electrical conduction when the FET 104 is in operation. The doped layer 118 is doped with an impurity of opposite polarity type as that of the channels such as the first channel 108A, the second channel 108B and the third channel 108C. For example, in a case, if the first channel 108A, the second channel 108B and the third channel 108C are formed (fabricated) as n-type channels (or N channels) then, in such a case, the doped layer 118 will be doped with a p-type impurity or vice-versa. In case of the n-type channels, the 3-stack GAA device 400A may also be referred as a n-type 3 -stack GAA device 400A. Similarly, the 2-stack GAA device 400B may also be referred as a n-type 2-stack GAA device 400B.
With referene to FIG. 4C, at the step 406, in the 2-stack GAA device 400B, a hard mask 422 (also represented as HM) is deposited over the FET 104. The hard mask 422 (i.e., HM) is used to protect a lower stack number device (or devices) such as the 2-stack GAA device 400B from any unwanted processing (e.g. etching). In a higher stack number device (or devices) such as the 3 -stack GAA device 400A, no hard mask is used.
With referene to FIG. 4D, at the step 408, selective etching of the doped layer 118 is performed in the 3-stack GAA device 400A (or the higher stack number device).
With reference to FIG. 4E, at the step 410, the hard mask 422 is removed from the 2-stack GAA device 400B (or the lower stack number device).
With reference to FIG. 4F, at the step 412, the doped layer 118 in each of the 3-stack GAA device 400A and the 2-stack GAA device 400B is exposed for etching. The result is the doped layer 118 is completely removed in the 3-stack GAA device 400A and partially removed in the 2-stack GAA device 400B. In the 2-stack GAA device 400B, the doped layer 118 (i.e., partially left) is used to blank-off the first SAC layer 418A and the first channel 108A from contributing to electrical conduction when the FET 104 is in operation.
With reference to FIG. 4G, at the step 414, the source region 114 (i.e., S) and the drain region 116 (i.e., D) with appropriate doping type are epitaxially grown in each of the 3-stack GAA device 400A and the 2-stack GAA device 400B. Alongwith the source region 114 (i.e., S) and the drain region 116 (i.e., D), an excess region 424 is also formed in the 2-stack GAA device
400B. With reference to FIG. 4H, at the step 416, planarization (e.g. top planarization) of the 2-stack GAA device 400B is performed in order to remove the excess region 424 and to obtain suitable dimensions of the epitaxially grown source region 114 (i.e., S) and the drain region 116 (i.e., D). In this way, the method 400 provides an easy process for forming (manufacturing) a semiconductor device (i.e., the 3 -stack GAA device 400A and the 2-stack GAA device 400B) with the flexibility in the stack number on one or more FETs. Additionally, the method 400 does not require development of any new epitaxial flow for manufacturing a GAA device with different stack numbers. Modifications to embodiments of the disclosure described in the foregoing are possible without departing from the scope of the disclosure as defined by the accompanying claims. Expressions such as "including", "comprising", "incorporating", "have", "is" used to describe and claim the disclosure are intended to be construed in a non-exclusive manner, namely allowing for items, components or elements not explicitly described also to be present. Reference to the singular is also to be construed to relate to the plural. The word "exemplary" is used herein to mean "serving as an example, instance or illustration". Any embodiment described as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or to exclude the incorporation of features from other embodiments. The word "optionally" is used herein to mean "is provided in some embodiments and not provided in other embodiments". It is appreciated that certain features of the disclosure, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the invention, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable combination or as suitable in any other described embodiment of the disclosure.

Claims

1. A semiconductor device (100A, 100B, lOOC) including a substrate (102) having one or more field-effect transistors, FETs, formed thereon, wherein a given FET (104) of the one or more FETs includes multiple nano-layers formed into alternate gates and channels in a vertical stack (112); wherein a source region (114) and a drain region (116) of the given FET (104) flank the vertical stack (112) such that the channels are configured to provide a conduction path between the source region (114) and the drain region (116) depending on a voltage signal applied to the gates; wherein at least one of the source region (114) and the drain region (116) of the given FET (104) is epitaxially formed on a doped layer (118) that is epitaxially formed on the substrate (102), such that a crystallographic orientation of the substrate (102) is communicated via the doped layer (118) to the at least one of the source region (114) and the drain region (116); and wherein the doped layer (118) is configured to blank-off one or more of the gates and their one or more associated channels in the vertical stack (112) from contributing to conduction between the source region (114) and drain region (116) when the given FET (104) is in operation.
2. The semiconductor device (100A, 100B, lOOC) of claim 1, wherein the doped layer (118) is of a same doping polarity type as that of a region of the substrate (102) on which the one or more FETs are formed.
3. The semiconductor device (100A, 100B, lOOC) of claim 1, wherein the doped layer (118) is formed epitaxially from at least one of: SiGe, GeSn, Ge and GaAs.
4. The semiconductor device (100A, 100B, lOOC) of claim 2 or 3, wherein the substrate (102) includes both at least one n-type region and at least one p-type region, wherein a portion of the one or more FETs are fabricated as p-type FETs onto the at least one n-type region, and another portion of the one or more FETs are fabricated as n-type FETs onto the at least one p- type region.
5. The semiconductor device (100 A, 100B, lOOC) of claim 1, wherein each conducting layer of the multiple layers in the vertical stack (112) has a thickness in a direction that is orthogonal to a plane of the substrate (102) that is in a range of 1 nm to 20 nm.
6. The semiconductor device (100A, 100B, lOOC) of claim 1, wherein the one or more FETs are fabricated as gate-all-around, GAA, structures.
7. The semiconductor device (100A, 100B, lOOC) of claim 1, wherein the one or more FETs are formed to be a FinFET elongate structure arrangement, wherein an elongate axis of the one or more FETs is parallel to a plane of the substrate (102), and is orthogonal to a conduction direction from the source region (114) to the drain region (116).
8. The semiconductor device (100A, 100B, lOOC) of claim 1, wherein the doped layer (118) is configured to isolate from the one or more FETs one or more layers of the vertical stack (112) that are closest to the substrate (102).
9. The semiconductor device (100A, 100B, lOOC) of claim 1, wherein the one or more FETs are Silicon-based devices.
10. A method (300) for manufacturing a semicondictor device (100A, 100B, lOOC) having one or more field-effect transistors, FETs, formed thereon, wherein the method (300) includes:
(i) forming one or more stacks of multiple nano-layers into a plurality of alternate gates and channels in vertical stacks;
(ii) for a given vertical stack (112) forming a given FET (104), forming a source region (114) and a drain region (116) to flank the plurality of alternate gates and channels in the given vertical stack (112), wherein at least one of the source region (114) and the drain region (116) are epitaxially fabricated onto a doped layer (118) that is epitaxially formed onto the substrate (102), such that a crystallographic orientation of the substrate (102) is communicated via the doped layer (118) to the at least one of the source region (114) and the drain region (116); wherein the doped layer (118) is configured to blank-off at least one of the gates and its associated channel in the given vertical stack (112) from contributing to conduction between the source region (114) and drain regions (116) via the channels when the given FET (104) is in operation.
11. The method (300) of claim 10, wherein the method (300) includes arranging for the doped layer (118) to be of a same doping polarity type as that of a region of the substrate (102) on which the given FET (104) is formed.
12. The method (300) of claim 11, wherein the method (300) includes forming the doped layer (118) epitaxially from at least one of: SiGe, GeSn, Ge and GaAs.
13. The method (300) of claim 11 or 12, wherein the method (300) includes fabricating the substrate (102) to include a n-type region and a p-type region, wherein a portion of the one or more FETs are formed as p-type FETs onto the at least one n-type region, and another portion of the one or more FETs are formed as n-FETs onto the at least one p-type region. 14. The method (300) of claim 10, wherein the method (300) includes arranging for each conducting layer of the multiple layers in the given vertical stack (112) to have a thickness in a direction that is orthogonal to a plane of the substrate (102) that is in a range of 1 nm to 20 nm.
15. The method (300) of claim 10, wherein the method (300) includes forming the one or more FETs as gate-all-around, GAA, structures. 16. The method (300) of claim 10, wherein the method (300) includes forming the one more more FETs to be a FinFET elongate structure arrangement, wherein an elongate axis of the one or more FETs is parallel to a plane of the substrate (102), and is orthogonal to a conduction direction from the source region (114) to the drain region (116).
17. The method (300) of claim 10, wherein the method (300) includes configuring the doped layer (118) to isolate from the one or more FETs one or more layers of the given vertical stack
(112) that are closest to the substrate (102).
18. The method (300) of claim 10, wherein the method (300) includes forming the one or more FETs to be Silicon-based devices.
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