WO2022218337A1 - 一种弱内存序架构下的代码检查方法及相应设备 - Google Patents

一种弱内存序架构下的代码检查方法及相应设备 Download PDF

Info

Publication number
WO2022218337A1
WO2022218337A1 PCT/CN2022/086590 CN2022086590W WO2022218337A1 WO 2022218337 A1 WO2022218337 A1 WO 2022218337A1 CN 2022086590 W CN2022086590 W CN 2022086590W WO 2022218337 A1 WO2022218337 A1 WO 2022218337A1
Authority
WO
WIPO (PCT)
Prior art keywords
loop
busy
code
execution flow
source code
Prior art date
Application number
PCT/CN2022/086590
Other languages
English (en)
French (fr)
Inventor
文羽中
奥伯豪泽尔•乔纳斯
贝伦斯•迪亚戈
付明
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP22787559.8A priority Critical patent/EP4318211A1/en
Publication of WO2022218337A1 publication Critical patent/WO2022218337A1/zh
Priority to US18/484,641 priority patent/US20240045787A1/en

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/3604—Software analysis for verifying properties of programs
    • G06F11/3612—Software analysis for verifying properties of programs by runtime analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3628—Software debugging of optimised code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/443—Optimisation
    • G06F8/4441—Reducing the execution time required by the program code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/45—Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
    • G06F8/458—Synchronisation, e.g. post-wait, barriers, locks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/524—Deadlock detection or avoidance

Definitions

  • the present application relates to the field of computer technology, and in particular to a code inspection method and corresponding device under a weak memory sequence architecture.
  • the processor calls the thread to operate the memory, if it is in a strong memory order architecture (such as the x86 architecture), the actual execution code sequence is the same as the code writing sequence, and the memory access sequence will not be rearranged.
  • weak memory order architectures such as advanced RISC machine, ARM
  • the fifth-generation instruction architecture based on reduced instruction set (reduced instruction set computing five, RISC-V), no pipeline interlock microprocessor processor architecture (Microprocessor without Interlocked Pipeline Stages, MIPS), instruction set architecture (performance optimization with enhanced RISC, POWER) based on reduced instruction set architecture (performance optimization with enhanced RISC, POWER)
  • the processor usually rearranges the memory access order according to the execution situation , the rearrangement may cause the processor to actually execute the code in a different order from the order in which the code was written.
  • the code sequence actually executed by the processor to the memory may be inconsistent with the code writing order. After transplanting the code that executes correctly in the strong memory order architecture to the weak memory order architecture, there will be a high probability of problems, resulting in non-conformity. expected behavior.
  • model checking technology is used to check the rearrangement execution flow of accessing memory under the weak memory ordering architecture, so as to find out whether the same code has behavior differences between the weak memory ordering architecture and the strong memory ordering architecture.
  • the current model checking technology cannot predict the number of executions of busy-waiting loops in the rearranged code, when encountering codes with busy-waiting loops, an infinite number of execution streams will be generated, and the infinite number of execution streams will be found. Whether there is a problem with rearranging the code is obviously an impossible task.
  • the embodiment of the present application provides a code checking method under a weak memory order architecture, which is used to solve the correctness check of the busy-wait loop code under the weak memory order architecture.
  • Embodiments of the present application also provide corresponding devices, computer-readable storage media, computer program products, and the like.
  • a first aspect of the present application provides a code inspection method under a weak memory sequence architecture, including: obtaining a first source code and a test code, the first source code includes a blocking flag, and the test code is used to indicate that the first source code can run correctly The conditions to be met, the first source code corresponds to multiple threads, the multiple threads have at least one piece of shared memory, and the blocking flag is used to indicate the location of the busy-wait loop in the first source code; according to the conditions indicated by the test code and the first source code
  • the code generates multiple execution streams under the weak memory order architecture for multiple threads operating the same shared memory, wherein each execution stream is the result of the processor running multiple threads to read and/or write the same shared memory.
  • the code execution process there is a busy-wait loop in the target execution stream that contains blocking flags in multiple execution streams; if the multi-thread execution of the busy-wait loop in the target execution stream is called, the read operation performed by the target thread in the busy-wait loop If less than one unreferenced write operation is referenced, it is determined that the busy-wait loop in the target execution flow is an infinite loop, and the infinite loop indicates that there is an error in the first source code, and the target thread is any one of the multiple threads.
  • the code inspection method is applied to a computer device, and the computer device may be a server, a terminal device or a virtual machine (virtual machine, VM).
  • the weak memory order architecture is relative to the strong memory order architecture. Both the weak memory order architecture and the strong memory order architecture are instruction set architectures.
  • the strong memory order architecture can include the x86 architecture, and the weak memory order architecture can include advanced reduced instruction sets ( advanced RISC machine, ARM) architecture.
  • advanced RISC machine, ARM advanced reduced instruction sets
  • the code sequence actually executed by the processor when the calling thread operates the memory will be consistent with the code writing sequence.
  • the weak memory order architecture the code sequence actually executed by the processor when the calling thread operates the memory may be inconsistent with the code writing sequence.
  • the first source code is usually a multi-threaded synchronization algorithm with busy-wait semantics, such as spin locks, lock-free lists, and the like.
  • the blocking mark in the first source code may be added manually, or may be added by a computer device by preprocessing the initially acquired source code without blocking mark.
  • the test code is used to define the correctness of the first source code, and the test code can indicate what conditions the first source code needs to meet to be correct. For example, the test code can give the conditions that must be met to exit the loop.
  • the fact that the first source code corresponds to multiple threads means that the first source code can be called by multiple threads to perform operations on the memory.
  • a busy-waiting loop refers to that when one thread operates the shared memory, other threads occupy the processor in a waiting state, and the busy-waiting loop will not exit until the loop condition in the busy-waiting loop reaches a corresponding value.
  • a busy-wait loop is a code block, and the code in the code block represents the process of the busy-wait loop.
  • a thread operating a shared memory may include a thread performing a read operation and/or a write operation on the shared memory.
  • Read operation and/or write operation means that only a read operation, only a write operation, or both a read operation and a write operation may be performed. Perform a write operation.
  • both read and write operations must be performed. For example, thread 1 performs read operations and thread 2 performs write operations.
  • the execution flow is the actual execution flow of the code in which multiple threads perform read operations and/or write operations on the same piece of shared memory.
  • Different execution flows can be determined according to the sequence of operations performed by multiple threads on the same piece of memory.
  • Each thread operates the same piece of shared memory.
  • According to the execution order of the three threads there can be 6 execution streams.
  • There is a busy-wait loop in the target execution flow and the busy-wait loop contains a blocking flag.
  • the target execution flow is not limited to one, and each execution flow in multiple execution flows can be the target execution flow, as long as the execution flow containing the blocking flag is included. Can be understood as the target execution flow.
  • the target execution flow containing the blocking flag will be checked. Because there is a busy-wait loop in the target execution flow, the process of executing the target execution flow may execute the code of the busy-wait loop for many times.
  • the process of looping involves read operations. Usually, a newly generated read operation corresponds to a new write operation, because a newly generated read operation corresponds to a write operation that has been referenced by other read operations, which is just a meaningless cycle. , so, when a newly generated read operation does not refer to a new write operation, that is, an unreferenced write operation, it means that the busy-wait loop of the target execution stream cannot be exited, which is an infinite loop, then Indicates that the first source code has errors and cannot be executed normally.
  • the first aspect provides The solution can complete the correctness check of the first source code within a limited time.
  • obtaining the first source code includes: obtaining a second source code; identifying a code block representing a busy-wait loop from the second source code, and performing a code block indicating a busy-wait loop in the second source code. Add a blocking marker to the code block of the loop to obtain the first source code.
  • the second source code that does not contain the blocking mark can be identified, and the blocking mark can be added, so that the source code can be checked for correctness in the subsequent code checking process.
  • the method further includes: converting the symbol representing the loop condition in the code block representing the busy-wait loop from the first form to the second form; the above steps: in the code block representing the busy-wait loop adding a blocking marker to the code block of , comprising: adding the blocking marker at a position associated with the symbol of the loop condition of the second form.
  • the loop condition represents the condition for the end of the loop, for example: while (lock) represents a loop condition, where while represents the symbol of the loop condition, and the symbol of the loop condition is changed from the first form
  • Converting to the second form may be converting the while of the first form to the if of the second form.
  • Blocking markers can be blocking primitives, such as: modelchecker_block. In the present application, the blocking mark may be added after the loop condition.
  • the present application does not limit the specific position where the blocking mark is added, as long as the position is associated with the symbol of the loop condition of the second form.
  • This possible implementation is convenient to quickly check out the busy-wait loop, thereby improving the speed of code correctness checking.
  • identifying a code block representing a busy-wait loop from the second source code includes: identifying a loop condition from the second source code, where the loop condition includes a constant True or not always true; if the loop condition is not always true, the code block associated with the loop condition is determined to be the code block of the busy-waiting loop according to the value corresponding to the loop condition; if the loop condition is always true, then according to the loop condition The associated loop body determines that the code block associated with the loop condition is the code block of the busy-wait loop.
  • the loop condition usually includes always being true or not being always true. If it is not always true, the loop condition is usually a read operation of an atomic variable or an atomic read-swap (compare and swap) operation, and the loop condition is determined by whether the value read by the read operation of the atomic variable satisfies the exit loop. . If it is always true, you need to define the exit condition through the loop body (loop-body), so as to determine the loop condition in the code. This possible implementation is beneficial to quickly determine the loop condition, so as to quickly identify the code block of the busy-wait loop in the source code.
  • the method further includes: filtering out redundant execution flows in the multiple execution flows, and at least two write operations in at least two loops of the redundant execution flows correspond to the same one write operation.
  • the above step: filtering out redundant execution streams in multiple execution streams includes: checking the first read operation in the current loop of the first execution stream, first executing The stream is any one of the multiple execution streams, and this loop is a busy-wait loop being executed in the first execution stream; if the current thread performing the first read operation is executing the busy-wait loop in the first execution stream , then check the write operation corresponding to the first read operation; if the write operation referenced by the current thread performing the first read operation has been referenced by the current thread when performing the second read operation in the previous loop, then determine the first read operation.
  • An execution flow is a redundant execution flow; the first execution flow is filtered out.
  • the process of determining the redundant execution flow may be performed by checking whether the read operation has a corresponding unreferenced write operation. If the two write operations performed by the threads in the loop are referred to, it means that the first execution flow to be executed is a redundant execution flow, and the first execution flow needs to be filtered out. This solution of filtering redundant execution flows can speed up and narrow down the scope of checking execution flows.
  • the above steps if a busy-wait loop in a multi-threaded execution target execution flow is invoked, the read operation performed by the target thread in a busy-wait loop refers to less than one unsupported loop.
  • the busy-wait loop in the target execution flow is an infinite loop, including: setting a status flag for each read operation in the status set when calling the multi-threaded execution of the busy-wait loop in the target execution flow ;
  • a status flag is deleted from the state set; until no more write operations are generated in the busy-wait loop, if the state set still contains a state flag, then determine the busy state in the target execution flow.
  • the loop is an infinite loop.
  • each newly generated read operation will have a newly generated write operation by means of a status mark. If there are remaining status marks in the status set, it indicates a newly generated read operation. If there is no corresponding new write operation, it means that the busy-waiting loop cannot be exited, and the busy-waiting loop is an infinite loop. This implementation is helpful for quickly determining whether the busy-waiting loop can be terminated. If it cannot be terminated, it means that there is an error in the first source code.
  • a second aspect of the present application provides a code inspection device under a weak memory sequence architecture, including:
  • the obtaining unit is used to obtain the first source code and the test code.
  • the first source code includes a blocking mark, and the test code is used to indicate the conditions that the first source code must meet to run correctly.
  • the first source code corresponds to multiple threads, and the multiple Each thread has at least one piece of shared memory, and the blocking flag is used to indicate the location of the busy-wait loop in the first source code.
  • the first processing unit is configured to generate, according to the conditions indicated by the test code obtained by the obtaining unit and the first source code, multiple execution streams under the weak memory sequence architecture for multithreading operating the same shared memory, wherein each The execution flow is the code execution flow in which the processor runs multiple threads to read and/or write the same shared memory, and there is a busy-wait loop in the target execution flow that contains the blocking flag in the multiple execution flows.
  • the second processing unit is used for, if multi-threading is invoked to execute the busy-wait loop in the target execution flow generated by the first processing unit, the read operation performed by the target thread in a busy-wait loop refers to less than one unreferenced
  • the busy-wait loop in the target execution flow is an infinite loop, the infinite loop indicates that there is an error in the first source code, and the target thread is any one of the multi-threads.
  • the obtaining unit is configured to obtain the second source code; identify the code block representing the busy-wait loop from the second source code, and identify the code block representing the busy-wait loop in the code block representing the busy-wait loop Add blocking flags to get the first source code.
  • the first processing unit is further configured to convert the symbol representing the loop condition in the code block representing the busy-wait loop from the first form to the second form; adding the blocking flag in the The position associated with the symbol of the loop condition of the second form.
  • the first processing unit is configured to identify the loop condition from the second source code, and the loop condition includes always being true or not being always true; if the loop condition is not always being true , then the code block associated with the loop condition is determined to be the code block of the busy-wait loop according to the value corresponding to the loop condition; if the loop condition is always true, then the code block associated with the loop condition is determined according to the loop body associated with the loop condition as A block of code for a busy-wait loop.
  • the first processing unit is further configured to filter out redundant execution flows in the multiple execution flows, and at least two write operations in at least two loops of the redundant execution flows Corresponds to the same write operation.
  • the first processing unit is configured to check the first read operation in the current loop of the first execution flow, where the first execution flow is any one of the multiple execution flows. flow, this loop is a busy-wait loop being executed in the first execution flow; if the current thread executing the first read operation is executing the busy-wait loop in the first execution flow, check the write corresponding to the first read operation Operation; if the write operation referenced by the current thread performing the first read operation has been referenced by the current thread when the second read operation is performed in the previous loop, then it is determined that the first execution flow is a redundant execution flow; filter out The first execution flow.
  • the second processing unit is configured to set a status flag for each read operation in the status set when invoking the busy-wait loop in the multi-threaded execution target execution flow; If a write operation occurs in the waiting loop, a status flag is deleted from the state set; until no write operation occurs in the busy-waiting loop, if the state set also contains a status flag, the busy-waiting loop in the target execution flow is determined as Infinite loop.
  • a third aspect of the present application provides a computer device, the computer device includes a processor, a memory, and a computer-readable storage medium storing a computer program; the processor is coupled to the computer-readable storage medium, and a computer running on the processor executes instructions, When the computer-executed instructions are executed by the processor, the processor executes the method as described above in the first aspect or any one of the possible implementations of the first aspect.
  • the computer device may further include an input/output (I/O) interface, and the computer-readable storage medium storing the computer program may be a memory.
  • I/O input/output
  • a fourth aspect of the present application provides a computer-readable storage medium that stores one or more computer-executable instructions.
  • the processor executes the first aspect or any one of the possible operations of the first aspect. method of implementation.
  • a fifth aspect of the present application provides a computer program product that stores one or more computer-executable instructions.
  • the processor executes the first aspect or any possible implementation manner of the first aspect. Methods.
  • a sixth aspect of the present application provides a chip system, the chip system includes at least one processor, and the at least one processor is used to support the memory management device to implement the first aspect or any of the possible implementation manners of the first aspect. function.
  • the chip system may further include a memory, which is used for saving necessary program instructions and data of the memory management device.
  • the chip system may be composed of chips, or may include chips and other discrete devices.
  • the target execution flow can be checked through the blocking mark, even if the first source code generates an infinite number of execution flows, it is not necessary to check all of them. Therefore, the execution flow can be completed within a limited time. First source code correctness check.
  • Fig. 1A is a code block example diagram
  • FIG. 1B is an example diagram of another code block
  • FIG. 2 is a schematic structural diagram of a computer system provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of an embodiment of a code inspection method under a weak memory sequence architecture provided by an embodiment of the present application
  • FIG. 4 is a schematic diagram of another embodiment of a code inspection method under a weak memory sequence architecture provided by an embodiment of the present application
  • 5A is a schematic diagram of an example of a spinlock code provided by an embodiment of the present application.
  • 5B is a schematic diagram of an example of a spinlock variant code provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of performing flow filtering provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of another embodiment of performing flow filtering provided by an embodiment of the present application.
  • FIG. 8A is an exemplary schematic diagram provided by an embodiment of the present application.
  • FIG. 8B is an exemplary schematic diagram provided by an embodiment of the present application.
  • FIG. 9 is an embodiment of an execution flow check provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of an embodiment of a code inspection apparatus under a weak memory sequence architecture provided by an embodiment of the present application
  • FIG. 11 is a schematic structural diagram of a computer device provided by an embodiment of the present application.
  • the embodiment of the present application provides a code checking method under a weak memory order architecture, which is used to solve the correctness check of the busy-wait loop code under the weak memory order architecture.
  • Embodiments of the present application also provide corresponding devices, computer-readable storage media, computer program products, and the like. Each of them will be described in detail below.
  • the weak memory ordering architecture is relative to the strong memory ordering architecture.
  • Both the weak memory ordering architecture and the strong memory ordering architecture are instruction set architectures.
  • the strong memory ordering architecture may include the x86 architecture, and the weak memory ordering architecture may Including advanced RISC machine (ARM) architecture, fifth-generation instruction architecture based on reduced instruction set (reduced instruction set computing five, RISC-V), no pipeline interlock microprocessor architecture (Microprocessor without Interlocked Pipeline) Stages, MIPS) or instruction set architecture based on reduced instruction set architecture (performance optimization with enhanced RISC, POWER).
  • ARM advanced RISC machine
  • RISC-V reduced instruction set
  • MIPS microprocessor without Interlocked Pipeline
  • instruction set architecture based on reduced instruction set architecture (performance optimization with enhanced RISC, POWER).
  • the strong memory order architecture the code sequence actually executed by the processor when the calling thread operates the memory will be consistent with the code writing sequence.
  • the weak memory order architecture the code sequence actually executed by the processor when the calling thread operates the memory may be inconsistent
  • the code block shown in FIG. 1A is the code writing sequence
  • the code block shown in FIG. 1B is the actual execution sequence of the code.
  • the sequence shown in FIG. 1A will be executed, and the codes on both sides of the vertical line 100 represent codes in two different threads respectively.
  • the thread on the right side of the vertical bar 100 will definitely be assigned the value of 0 after the await_while loop exits, and l is not equal to 1. Therefore, the await_while of the thread to the left of the vertical line 100 must be able to exit smoothly.
  • the solution provided by this application is a solution for checking the source code to be run under the weak memory sequence architecture.
  • the code checking method under the weak memory order architecture provided by the embodiments of the present application is applied to a computer system, and the computing system may be a server, a terminal device, a virtual machine (virtual machine, VM) or a container (container).
  • the computing system may be a server, a terminal device, a virtual machine (virtual machine, VM) or a container (container).
  • the server can be any form of physical machine.
  • Terminal equipment also known as user equipment (UE) is a device with wireless transceiver functions that can be deployed on land, including indoor or outdoor, handheld or vehicle-mounted; it can also be deployed on water (such as ships). etc.); can also be deployed in the air (eg on airplanes, balloons, satellites, etc.).
  • the terminal equipment can be a personal computer (PC), a mobile phone (mobile phone), a tablet computer (pad), a computer with wireless transceiver function, a virtual reality (VR) terminal, and an augmented reality (AR) terminal.
  • PC personal computer
  • mobile phone mobile phone
  • tablet computer tablet computer
  • AR augmented reality
  • wireless terminals in industrial control wireless terminals in self-driving, wireless terminals in remote medical, wireless terminals in smart grid, transportation security wireless terminal in safety), wireless terminal in smart city (smart city), wireless terminal in smart home (smart home), wireless terminal in internet of things (IoT), etc.
  • Virtual machines can be in the cloud or on-premises.
  • the architecture of the computer system provided by the embodiments of the present application can be understood by referring to FIG. 2 .
  • FIG. 2 is a schematic structural diagram of a computer system provided by an embodiment of the present application.
  • the architecture of the computer system 10 may include an application layer 101 , a kernel layer 102 and a hardware layer 103 .
  • the application layer 101 includes an operation interface, through which the program detection staff can start the source code inspection process.
  • the kernel layer 102 includes an acquisition module for acquiring source codes and test codes, the kernel layer 102 further includes a model checking module, and may also include a preprocessing module.
  • This preprocessing module is used to add blocking markers to source code that has not been added with blocking markers.
  • the model checking module is used to check the correctness of source code containing blocking flags when multithreaded execution accesses the same shared memory.
  • the hardware layer 103 includes a communication interface 1031, a processor 1032, a memory 1033, a bus 1034, and the like.
  • the communication interface 1031 , the processor 1032 and the memory 1033 are connected through the bus 1034 .
  • the processor 1032 may include any type of general-purpose computing circuit or special-purpose logic circuit, such as: a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). It can also be one or more processors, such as a central processing unit (CPU), coupled to one or more semiconductor substrates.
  • the memory may include a plurality of shared memories, such as shared memory 1 to shared memory n as shown in FIG. 2 , and each shared memory is a storage area in the memory. Each shared memory has a memory address, and different shared memories have different memory addresses.
  • the processor may run multiple threads to execute the execution flow generated according to the source code and the test code, operate the same piece of shared memory, and check whether the busy-waiting loop in the execution flow containing the blocking flag is an infinite loop, thereby Determine if there are errors in this source code. Because the target execution flow can be checked through the blocking flag, even if the source code generates an infinite number of execution flows, it is not necessary to check all of them, so the correctness check of the source code can be completed in a limited time.
  • the solutions provided by this application include: 1.
  • the source code is directly checked by the model checking module without going through the preprocessing module; 2.
  • the source code is preprocessed by the preprocessing module and then Scenario for code checking performed by the model checking module.
  • the computer equipment is used as the execution subject to be introduced respectively.
  • the source code is directly checked by the model checking module without going through the preprocessing module.
  • an embodiment of a code inspection method under a weak memory sequence architecture includes:
  • the first source code contains a blocking mark
  • the test code is used to indicate the conditions that the first source code can run correctly
  • the first source code corresponds to multiple threads, and the multiple threads have at least one piece of shared memory
  • the blocking mark is used to indicate the first source code. The location of a busy-wait loop in the source code.
  • the first source code is usually a multi-threaded synchronization algorithm with busy-wait semantics, such as code for spin lock, code for lock-free list, and the like.
  • the blocking flags in the first source code may be added manually.
  • the test code is used to define the correctness of the first source code, and the test code can indicate what conditions the first source code needs to meet to be correct. For example, the test code can give the conditions that must be met to exit the loop.
  • the fact that the first source code corresponds to multiple threads means that the first source code can be called by multiple threads to perform operations on the shared memory.
  • a busy-waiting loop refers to that when one thread operates the shared memory, other threads occupy the processor in a waiting state, and the busy-waiting loop will not exit until the loop condition in the busy-waiting loop reaches a corresponding value.
  • a busy-wait loop is a code block, and the code in the code block represents the process of the busy-wait loop.
  • each execution flow is a code execution flow in which the processor runs multiple threads to read and/or write the same shared memory, and there is a busy-wait loop in the target execution flow containing the blocking flag in the multiple execution flows.
  • the thread operating on the shared memory may include the thread performing a read operation and/or a write operation on the shared memory, and "read operation and/or write operation" means that only a read operation, only a write operation, or both a read operation can be performed. The operation in turn performs a write operation.
  • read operation and/or write operation means that only a read operation, only a write operation, or both a read operation can be performed. The operation in turn performs a write operation.
  • both read and write operations must be performed. For example, thread 1 performs read operations and thread 2 performs write operations.
  • the execution flow is the actual execution flow of the code in which multiple threads perform read operations and/or write operations on the same piece of shared memory.
  • the target execution flow is not limited to one, and each execution flow in multiple execution flows can be the target execution flow, as long as the execution flow containing the blocking flag is included. Can be understood as the target execution flow.
  • the read operation performed by the target thread in a busy-waiting loop does not refer to an unreferenced write operation, then determine the target execution flow.
  • the busy-wait loop is an infinite loop.
  • An infinite loop indicates that there is an error in the first source code, and the target thread is any one of the multiple threads.
  • the target execution stream containing the blocking flag is checked. Because there is a busy-wait loop in the target execution stream, the process of executing the target execution stream may execute the code of the busy-wait loop for many times.
  • the process of busy-waiting cycle involves read operations. Usually, a newly generated read operation corresponds to a new write operation, because a newly generated read operation corresponds to a write operation that has been referenced by other read operations. Therefore, when a newly generated read operation does not refer to a new write operation, that is, an unreferenced write operation, it means that the busy-wait loop of the target execution stream cannot be exited, which is an infinite loop. Then, it means that there is an error in the first source code and cannot be executed normally.
  • the target execution flow can be checked through the blocking mark, even if the first source code generates an infinite number of execution flows, it is not necessary to check all of them. Therefore, the execution flow can be completed within a limited time. First source code correctness check.
  • the source code is preprocessed by the preprocessing module, and then the model checking module performs code checking.
  • FIG. 4 another embodiment of a code inspection method under a weak memory sequence architecture provided by an embodiment of the present application includes:
  • the computer device obtains the second source code and the test code.
  • the second source code is the source code with no blocking flags added.
  • the preprocessing process may also convert the symbols representing the loop condition in the code block representing the busy-wait loop from the first form to the second form; adding a blocking marker at a position associated with the symbol of the loop condition in the second form.
  • the loop condition indicates the condition of the end of the loop, such as: while (lock) indicates a loop condition, where while indicates the symbol of the loop condition, and the symbol of the loop condition is converted from the first form to the second form.
  • the while of the first form is converted into the if of the second form.
  • Blocking markers can be blocking primitives, such as: modelchecker_block. In the present application, the blocking mark may be added after the loop condition.
  • the present application does not limit the specific position where the blocking mark is added, as long as the position is associated with the symbol of the loop condition of the second form. This scheme facilitates fast detection of busy-wait loops, thereby increasing the speed of code correctness checking.
  • each execution flow is a code execution flow in which the processor runs multiple threads to read and/or write the same shared memory, and there is a busy-wait loop in the target execution flow containing the blocking flag in the multiple execution flows.
  • the read operation performed by the target thread in a busy-wait loop does not refer to an unreferenced write operation, then determine the target execution flow.
  • the busy-wait loop is an infinite loop.
  • An infinite loop indicates that there is an error in the first source code, and the target thread is any one of the multiple threads.
  • Steps 303 and 304 can be understood by referring to the aforementioned steps 202 and 203, and will not be repeated here.
  • the solution provided by this embodiment of the present application can preprocess the source code that does not contain blocking marks, and add blocking marks, so that the target execution flow can be checked through the blocking marks, even if the first source code will generate an infinite number of executions The flow does not need to be all checked, so the correctness check of the first source code can be completed within a limited time.
  • identifying the code block representing the busy-wait loop from the second source code including: identifying the loop condition from the second source code, the loop condition includes being always true or not always being true; If the loop condition is not always true, the code block associated with the loop condition is determined to be the code block of the busy-waiting loop according to the value corresponding to the loop condition; if the loop condition is always true, the loop is determined according to the loop body associated with the loop condition The code block associated with the condition is the code block of the busy-wait loop.
  • the loop condition is usually a read operation of an atomic variable or an atomic read-swap (compare and swap) operation, and whether the value read through the read operation of the atomic variable satisfies Exit the loop to determine the loop condition. If it is always true, you need to define the exit condition through the loop body (loop-body), so as to determine the loop condition in the code. This possible implementation is beneficial to quickly determine the loop condition, so as to quickly identify the code block of the busy-wait loop in the source code.
  • FIG. 5A is a schematic diagram of an example of the spin lock code shown in FIG. 5A .
  • the example diagram includes 12 lines of code, and each line of code is marked with 1 to 12 respectively.
  • the third line while(lock) is the loop condition.
  • FIG. 5B is a schematic diagram of an example of the spinlock variant code shown in FIG. 5B .
  • the example diagram includes 13 lines of code, and each line of code is marked with 1 to 13 respectively.
  • the loop condition can be converted by the method described in the above step 302, and a loop mark is added, for example, the loop in the third row in FIG. 5A can be changed.
  • the condition while(lock) is converted to if(!Locked)_MODELCHECKER_block(); the loop condition while(true) of line 3 in Figure 5B is converted to if(!Locked)_MODELCHECKER_block().
  • the processor checks the execution flow containing if(!Locked)_MODELCHECKER_block(), it will mark the execution flow as a potential infinite loop execution flow, so as to perform the corresponding check process to confirm whether the execution flow is an infinite loop Execute flow.
  • filtering may also be performed on multiple execution streams to filter out redundant execution streams.
  • the scope of the flow inspection thereby reducing the time to inspect the source code.
  • the filtering algorithm used in the process of filtering the execution flow may be referred to as an await progress condition (APC) algorithm.
  • APC await progress condition
  • the process of filtering the infinite number of execution flows generated by the loop into finite execution flows can be understood with reference to FIG. 6 .
  • the computer device After the computer device receives the source code and the test code, it will perform model checking.
  • the model checking process will perform graph traversal and loop traversal.
  • Executing graph traversal will traverse each branch in the source code and execute loop
  • the traversal will traverse the loop of each branch, and the loop traversal process will generate an infinite number of execution flows.
  • the APC filtering algorithm will be used to filter the infinite number of execution flows, and filter out the redundant execution flows. to a finite execution flow, wherein at least two write operations in at least two loops of the redundant execution flow correspond to the same write operation.
  • the filtering process includes:
  • the execution flow checked in step 401 may be any execution flow, which may be referred to as the first execution flow in this application. It could be a read operation in this loop that examines the first execution stream.
  • the read operation may be any read operation in this cycle, which may be called the first read operation.
  • the first execution flow is any one of the multiple execution flows, and this loop is a busy-waiting loop being executed in the first execution flow.
  • Step 402 refers to determining whether the checked operation is a read operation or a write operation. If it is a read operation, then step 403 is performed. If not, it means that it is not a read operation, but a write operation, and then step 407 is performed.
  • step 404 determines whether the read operation is in the busy-wait loop; if so, execute step 404; if not, execute step 407.
  • the write operation corresponding to the first read operation is checked.
  • step 405. Determine whether the write operation corresponding to the read operation is found, if so, execute step 407, if not, execute step 406.
  • step 402 If it is determined in step 402 that the checked operation is a write operation, or if the write operation corresponding to the read operation cannot be found in step 405, the model search traversal is continued.
  • the APC algorithm described above ensures that each read operation for a busy-wait condition in the model checking process gets the value from the new write operation, not the old value. This removes meaningless read traversals and ensures that every time a busy-wait loop condition reads a new value.
  • the process of determining the redundant execution flow may be performed by checking whether the read operation has a corresponding unreferenced write operation. It is referred to by the two write operations performed by the thread of , indicating that the executed first execution flow is a redundant execution flow, and the first execution flow needs to be filtered out. This solution of filtering redundant execution flows can speed up and narrow down the scope of checking execution flows.
  • whether to use the execution flow generated by the APC filtering algorithm can be understood by referring to the comparison between the schematic diagram without APC filtering shown in FIG. 8A and the schematic diagram with APC filtering shown in FIG. 8B .
  • rf in FIG. 8A represents a reference relationship between a read operation and a write operation. The reference relationship in FIG.
  • the read operation R(1)1 refers to W(1,0)
  • the read operation R(1)2 refers to W(1,2)
  • the read operation R(1)3 refers to W( l,2)
  • the read operation R(1)4 references W(l,3), where W(l,2) is referenced by two read operations R(1)2 and R(1)3, where, R(1)3 is W(1,2) quoted in R(1)2. Therefore, the execution flow including R(1)3 is used for execution flow. If it is the APC provided according to the embodiment of the present application
  • the filtering algorithm is used for filtering, and the schematic diagram shown in FIG. 8B can be obtained. It can be seen from the comparison between FIG. 8A and FIG. 8B that filtering redundant execution flows through APC can narrow the scope of checking execution flows and improve the efficiency of source code correctness checking.
  • the above-mentioned step 203 or step 304 provided in this embodiment of the present application may include: when invoking the busy-wait loop in the multi-threaded execution target execution flow, setting a status flag for each read operation in the status set; If a write operation occurs in the loop, a status flag is deleted from the state set; until no more write operations are generated in the busy-wait loop, if the state set also contains a status flag, it is determined that the busy-wait loop in the target execution flow is dead cycle.
  • the process of checking the target execution flow can be understood with reference to FIG. 9 .
  • the process of checking the target execution flow may include:
  • the operation instruction refers to the operation instruction of the thread calling the target execution flow on the shared memory.
  • step 502. If the operation instruction is a write operation, record the write address, record the write operation into the write operation set, and continue to perform step 506.
  • This step adds a write operation to the set of write operations.
  • the state set is used to store state tokens, each of which represents a new read operation.
  • step 504. Check whether a corresponding write operation can be determined for a read operation from the set of write operations. If yes, go to step 505, if not, go to step 506.
  • step 506 If the corresponding write operation is determined for the read operation, remove the state flag corresponding to the read operation from the state set, and remove the corresponding write operation from the write operation set, and then perform step 506.
  • step 506. Check whether there is a next operation instruction, if yes, repeat step 501, if not, go to step 507.
  • step 507. Check whether the state flag still exists in the state set, if so, go to step 508.
  • whether each newly generated read operation will have a newly generated write operation can be determined by means of a status mark. If there are remaining status marks in the status set, it means that the newly generated read operation does not correspond to The newly generated write operation indicates that the busy-waiting loop cannot be exited, and the busy-waiting loop is an infinite loop. This implementation is helpful for quickly determining whether the busy-waiting loop can be terminated. If it cannot be terminated, it means that there is an error in the first source code.
  • an embodiment of the code checking apparatus 60 under the weak memory sequence architecture provided by the embodiment of the present application includes:
  • the obtaining unit 601 is used to obtain a first source code and a test code, the first source code contains a blocking mark, the test code is used to indicate the conditions that the first source code can run correctly, and the first source code corresponds to multiple threads, The multiple threads have at least one piece of shared memory, and the blocking flag is used to indicate the location of the busy-wait loop in the first source code.
  • the obtaining unit 601 may execute step 201 or step 301 of the foregoing method embodiment part.
  • the first processing unit 602 is configured to, according to the conditions indicated by the test code obtained by the obtaining unit 601 and the first source code, generate multiple execution streams under the weak memory sequence architecture for multithreading operating the same shared memory, wherein, Each execution flow is a code execution flow in which the processor runs multiple threads to read and/or write the same shared memory, and there is a busy-wait loop in the target execution flow that contains blocking flags in the multiple execution flows.
  • the first processing unit 602 may execute step 202 or 303 of the foregoing method embodiment part.
  • the second processing unit 603 is configured to, if multithreading is invoked to execute the busy-wait loop in the target execution stream generated by the first processing unit 602, the read operation performed by the target thread in a busy-wait loop refers to less than one unreferenced read operation. If the write operation has passed, it is determined that the busy-waiting loop in the target execution flow is an infinite loop, and the infinite loop indicates that there is an error in the first source code, and the target thread is any one of the multiple threads.
  • the second processing unit 603 may execute step 203 or 304 of the foregoing method embodiment part.
  • the target execution flow can be checked through the blocking mark, even if the first source code generates an infinite number of execution flows, it is not necessary to check all of them. Therefore, the execution flow can be completed within a limited time. First source code correctness check.
  • the obtaining unit 601 is used to obtain the second source code; identify the code block representing the busy waiting cycle from the second source code, and add a blocking mark in the code block representing the busy waiting cycle to obtain the first code block. source code.
  • the obtaining unit 601 may execute step 302 of the foregoing method embodiment part.
  • the first processing unit 602 is further configured to convert the symbol representing the loop condition in the code block representing the busy-wait loop from the first form to the second form; adding a blocking mark to the loop condition of the second form. The location of the symbol association.
  • the first processing unit 602 is used to identify the loop condition from the second source code, and the loop condition includes whether it is always true or not always true; if the loop condition is not always true, according to the corresponding loop condition The value determines that the code block associated with the loop condition is the code block of the busy-wait loop; if the loop condition is always true, the code block associated with the loop condition is determined to be the code block of the busy-wait loop according to the loop body associated with the loop condition.
  • the first processing unit 602 is further configured to filter out redundant execution flows in the multiple execution flows, and at least two write operations in at least two cycles of the redundant execution flows correspond to the same write operation.
  • the first processing unit 602 is used to check the first read operation in the current loop of the first execution flow, the first execution flow is any one of the multiple execution flows, and this loop is the first execution flow.
  • a busy-wait loop being executed in the execution stream; if the current thread executing the first read operation is executing a busy-wait loop in the first execution stream, check the write operation corresponding to the first read operation; if the first read operation is executed
  • the write operation referenced by the current thread has been referenced when the current thread performs the second read operation in the previous loop, then it is determined that the first execution flow is a redundant execution flow; the first execution flow is filtered out.
  • the second processing unit 603 is configured to set a status flag for each read operation in the state set when invoking the busy-wait loop in the multi-threaded execution target execution flow; when a write operation is generated in the busy-wait loop, Then delete a state marker from the state set; until no more write operations are generated in the busy-wait loop, if the state set still contains the state marker, it is determined that the busy-wait loop in the target execution flow is an infinite loop.
  • the acquisition unit 601 may correspond to the (source code + test code) acquisition module in the above-mentioned FIG. 2
  • the first processing unit 602 and the second processing unit 603 may correspond to the model checking module in the above-mentioned FIG. 2
  • the acquisition unit 601 may also correspond to the preprocessing module in FIG. 2 above.
  • the apparatus 60 described above can be understood by referring to the corresponding content of the foregoing method embodiments, and details are not repeated here.
  • Computer device 70 includes: processor 701 , communication interface 702 , physical memory 703 , and bus 704 .
  • the processor 701 , the communication interface 702 and the physical memory 703 are connected to each other through a bus 704 .
  • the processor 701 is configured to control and manage the actions of the computer device 70.
  • the processor 701 is configured to execute the steps in the method embodiments of FIG. 2 to FIG. 8B.
  • Communication interface 702 is used to support computer device 70 to communicate.
  • the physical memory 703 is used to store program codes and data of the computer device 70 and provide memory space for the process group.
  • the processor 701 may be a central processing unit, a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array, or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It may implement or execute the various exemplary logical blocks, modules and circuits described in connection with this disclosure.
  • the processor 701 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a digital signal processor and a microprocessor, and the like.
  • the bus 704 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus or the like. The bus can be divided into address bus, data bus, control bus and so on. For ease of presentation, only one thick line is used in FIG. 11, but it does not mean that there is only one bus or one type of bus.
  • PCI Peripheral Component Interconnect
  • EISA Extended Industry Standard Architecture
  • a computer-readable storage medium is also provided, where computer-executable instructions are stored in the computer-readable storage medium.
  • the processor of the device executes the computer-executable instructions
  • the device executes the above-mentioned FIG. 2 to Steps performed by the processor in Figure 8B.
  • a computer program product includes computer-executable instructions, and the computer-executable instructions are stored in a computer-readable storage medium; when a processor of a device executes the computer-executable instructions , the device performs the steps performed by the processor in the above-mentioned FIGS. 2 to 8B .
  • a chip system is further provided, the chip system includes a processor, and the processor is used for the apparatus for supporting memory management to implement the steps performed by the processor in the above-mentioned FIG. 2 to FIG. 8B .
  • the chip system may further include a memory, the memory, and the necessary program instructions and data of the device for saving data writing.
  • the chip system may be composed of chips, or may include chips and other discrete devices.
  • Units described as separate components may or may not be physically separated, and components shown as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit in each embodiment of the embodiments of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the functions, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer-readable storage medium.
  • the technical solutions of the embodiments of the present application can be embodied in the form of software products in essence, or the parts that make contributions to the prior art or the parts of the technical solutions, and the computer software products are stored in a storage medium , including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in the embodiments of the present application.
  • the aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other media that can store program codes .

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Multi Processors (AREA)
  • Debugging And Monitoring (AREA)
  • Hardware Redundancy (AREA)

Abstract

本申请公开了一种弱内存序架构下的代码检查方法，包括：获取第一源代码和测试代码，第一源代码中包含阻塞标记，第一源代码对应多个线程，多个线程具有至少一块共享内存；根据测试代码所指示的条件和第一源代码，为操作同一块共享内存的多线程生成在弱内存序架构下的多条执行流，多条执行流中包含阻塞标记的目标执行流中存在忙等循环；若调用多线程执行目标执行流中的忙等循环时，一次忙等循环中的目标线程所执行的读操作引用不到一个未被引用过的写操作，则确定出目标执行流中的忙等循环为死循环。本申请提供的方案，因为可以通过阻塞标记来检查目标执行流，所以，可以在有限的时间内完成对第一源代码的正确性检查。

Description

一种弱内存序架构下的代码检查方法及相应设备
本申请要求于2021年4月14日提交中国专利局、申请号为202110401685.0、发明名称为“一种弱内存序架构下的代码检查方法及相应设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机技术领域，具体涉及一种弱内存序架构下的代码检查方法及相应设备。
背景技术
处理器在调用线程操作内存时，若是在强内存序架构(如：x86架构)下，实际执行的代码顺序与代码编写顺序一致，不会出现对内存的访问顺序进行重排的情况。而在弱内存序架构(如：高级精简指令集(advanced RISC machine，ARM)、基于精简指令集的第五代指令架构(reduced instruction set computing five，RISC-V)、无流水线互锁的微处理器架构(Microprocessor without Interlocked Pipeline Stages，MIPS)、基于精简指令集架构的指令集体系构架(performance optimization with enhanced RISC,POWER))下，处理器通常会根据执行的情况对内存的访问顺序进行重排，重排可能会导致处理器实际执行的代码顺序与代码的编写顺序不一致。
由于弱内存序架构下，处理器对内存实际执行的代码顺序与代码的编写顺序可能存在不一致，将强内存序架构下执行无误的代码移植到弱内存序架构后会大概率出现问题，产生非预期行为。
目前会通过模型检查技术来检查弱内存序架构下的访问内存的重排执行流，从而找出同样的代码在弱内存序架构和强内存序架构下是否存在行为差异。但由于目前的模型检查技术无法预知重排代码中忙等循环的执行次数，在碰到有忙等循环的代码时，就会生成无穷多的执行流，而在无穷多的执行流中找出重排代码是否存在问题，显然是无法完成的任务。
发明内容
本申请实施例提供一种弱内存序架构下的代码检查方法，用于解决在弱内存序架构下实现忙等循环代码的正确性检查。本申请实施例还提供了相应设备、计算机可读存储介质及计算机程序产品等。
本申请第一方面提供一种弱内存序架构下的代码检查方法，包括：获取第一源代码和测试代码，第一源代码中包含阻塞标记，测试代码用于指示第一源代码能正确运行需符合的条件，第一源代码对应多个线程，多个线程具有至少一块共享内存，阻塞标记用于指示第一源代码中忙等循环的位置；根据测试代码所指示的条件和第一源代码，为操作同一块共享内存的多线程生成在弱内存序架构下的多条执行流，其中，每条执行流为处理器运行多线程对同一块共享内存进行读操作和/或写操作的代码执行流程，多条执行流中包含阻塞标记的目标执行流中存在忙等循环；若调用多线程执行目标执行流中的忙等循环时，一次忙等循环中的目标线程所执行的读操作引用不到一个未被引用过的写操作，则确定出目标执行流中的忙等循环为死循环，死循环指示第一源代码存在错误，目标线程为多线程中的 任意一个。
本申请中，该代码检查方法应用于计算机设备，该计算机设备可以是服务器、终端设备或虚拟机(virtual machine，VM)。弱内存序架构是相对于强内存序架构来说的，弱内存序架构和强内存序架构都是指令集架构，强内存序架构可以包括x86架构，弱内存序架构可以包括高级精简指令集(advanced RISC machine，ARM)架构。在强内存序架构下，处理器在调用线程操作内存时实际所执行的代码顺序会与代码的编写顺序保持一致。而在弱内存序架构下，处理器在调用线程操作内存时实际所执行的代码顺序可能会与代码的编写顺序保持不一致。
本申请中，第一源代码通常是带有忙等语义的多线程同步算法，如：自旋锁、无锁列表等。该第一源代码中的阻塞标记可以是人工添加的，也可以是计算机设备通过对最初获取的无阻塞标记的源代码进行预处理时添加的。测试代码用于定义第一源代码的正确性，该测试代码中可以给出第一源代码需要满足什么样的条件才是正确的。如：测试代码中可以给出循环退出需满足的条件。
本申请中，第一源代码对应多个线程指的是第一源代码可以被多个线程调用来执行对内存的操作。共享内存可以有多块，每块共享内存都有一个内存地址，不同共享内存的内存地址不同，多线程操作同一块共享内存时就会存在忙等循环的情况。忙等循环指的是一个线程操作共享内存时，其他线程占用处理器处于等待状态，直到忙等循环中的循环条件达到相应值时才会退出该忙等循环。在本申请中，忙等循环是一个代码块，该代码块中的代码表示了忙等循环的过程。
本申请中，线程操作共享内存可以包括线程对共享内存执行读操作和/或写操作，“读操作和/或写操作”表示可以只执行读操作，只执行写操作，或者既执行读操作又执行写操作。通常在多线程操作共享内存时，既要执行读操作也要执行写操作，如：线程1执行读操作，线程2执行写操作。
本申请中，执行流是多线程对同一块共享内存执行读操作和/或写操作的代码的实际执行流程，可以根据多线程对同一块内存的操作顺序来确定不同的执行流，如：有三个线程操作同一块共享内存，按照三个线程的执行顺序，可以有6个执行流。目标执行流中存在忙等循环，该忙等循环中包含阻塞标记，目标执行流不限于一条，多条执行流中的都每条执行流都可以是目标执行流，只要包含阻塞标记的执行流都可以理解为是目标执行流。
本申请中，会针对包含阻塞标记的目标执行流进行检查，因为目标执行流中存在忙等循环，所以，执行目标执行流的过程可能会执行多次忙等循环的代码，在每次忙等循环的过程都会涉及到读操作，通常一个新产生的读操作会对应一个新的写操作，因为一个新产生的读操作对应一个已经被别的读操作引用过的写操作只是一次无意义的循环，所以，当一个新产生的读操作引用不到一个新的写操作，也就是一个未被引用过的写操作时，就表示该目标执行流的忙等循环无法退出，是个死循环，那么则表示该第一源代码存在错误，不能正常执行。由以上内容可知，该第一方面中，因为可以通过阻塞标记来检查目标执行流，即使该第一源代码会产生无穷多个执行流，也无需全部都做检查，所以，该第一方面提供的方案可以在有限的时间内完成对第一源代码的正确性检查。
在第一方面的一种可能的实现方式中，上述步骤：获取第一源代码，包括：获取第二源代码；从第二源代码中识别出表示忙等循环的代码块，并在表示忙等循环的代码块中添加阻塞标记，以得到第一源代码。
该种可能的实现方式中，可以对不包含阻塞标记的第二源代码进行识别，并且添加阻塞标记，从而便于后续的代码检查过程可以实现对源代码的正确性检查。
在第一方面的一种可能的实现方式中，该方法还包括：将表示忙等循环的代码块中表示循环条件的符号由第一形式转换为第二形式；上述步骤：在表示忙等循环的代码块中添加阻塞标记，包括：将阻塞标记添加在与第二形式的循环条件的符号关联的位置。
该种可能的实现方式中，循环条件(loop-condition)表示循环结束的条件，如：while(lock)表示一个循环条件，其中，while表示循环条件的符号，将循环条件的符号由第一形式转换为第二形式可以是将第一形式的while转换为第二形式的if，当然，本申请不限于第一形式和第二形式的内容，只要第一形式的符号能表示循环条件，第二形式的符号能被检查出表示循环即可。阻塞标记可以是阻塞原语，如：modelchecker_block。本申请中，可以将阻塞标记会添加到循环条件之后，当然，本申请不限定阻塞标记所添加的具体位置，只要与第二形式的循环条件的符号相关联的位置即可。该种可能的实现方式便于快速检查出忙等循环，从而提高代码正确性检查的速度。
在第一方面的一种可能的实现方式中，上述步骤：从第二源代码中识别出表示忙等循环的代码块，包括：从第二源代码中识别出循环条件，循环条件包括恒为真或不是恒为真；若循环条件不是恒为真，则根据循环条件所对应的值确定循环条件所关联的代码块为忙等循环的代码块；若循环条件恒为真，则根据循环条件所关联的循环体确定循环条件所关联的代码块为忙等循环的代码块。
该种可能的实现方式中，循环条件通常包括恒为真或不是恒为真。若不是恒为真，则循环条件通常为对某个原子变量的读操作或者原子读-交换(compare and swap)操作，通过该原子量变量的读操作读到的值是否满足退出循环来确定循环条件。若是恒为真，则需要通过循环体(loop–body)来定义退出的条件，从而确定代码中的循环条件。该种可能的实现方式，有利于快速确定循环条件，从而快速识别出源代码中的忙等循环的代码块。
在第一方面的一种可能的实现方式中，该方法还包括：过滤掉多条执行流中的冗余执行流，冗余执行流的至少两次循环中的至少两个写操作对应同一个写操作。
该种可能的实现方式中，在确定出多条执行流后，可以过滤掉其中的冗余执行流，这样可以缩小对执行流检查的范围，从而缩短检查源代码的时间。
在第一方面的一种可能的实现方式中，上述步骤：过滤掉多条执行流中的冗余执行流，包括：检查第一执行流的本次循环中的第一读操作，第一执行流为多条执行流中的任意一条执行流，本次循环为第一执行流中正在执行的一次忙等循环；若执行第一读操作的当前线程正在执行第一执行流中的忙等循环，则检查第一读操作所对应的写操作；若执行第一读操作的当前线程所引用的写操作，已被当前线程在之前的循环中执行第二读操作时引用过，则确定出第一执行流为冗余执行流；过滤掉第一执行流。
该种可能的实现方式中，确定冗余执行流的过程可以是通过检查读操作是否有对应的 未被引用的写操作的方式来进行的，若一个写操作两次被不属于同一次忙等循环中的线程所执行的两个写操作所引用到，则表示所执行的第一执行流是冗余执行流，则需要过滤掉该第一执行流。该种过滤冗余执行流的方案，可以加速缩小对执行流检查的范围。
在第一方面的一种可能的实现方式中，上述步骤：若调用多线程执行目标执行流中的忙等循环时，一次忙等循环中的目标线程所执行的读操作引用不到一个未被引用过的写操作，则确定出目标执行流中的忙等循环为死循环，包括：调用多线程执行目标执行流中的忙等循环时，在状态集合中为每个读操作设置一个状态标记；当忙等循环中产生一个写操作，则从状态集合中删除一个状态标记；直到忙等循环中不再产生写操作，若状态集合中还包含状态标记，则确定出目标执行流中的忙等循环为死循环。
该种可能的实现方式中，可以通过状态标记的方式来确定是否每个新产生的读操作都会有一个新产生的写操作，若状态集合中的状态标记有剩余，则表示新产生的读操作没有对应的新产生的写操作了，则表示该忙等循环无法退出，该忙等循环为死循环。该种实现方式有利于快速确定出忙等循环是否可终止，若不可终止，则表示该第一源代码存在错误。
本申请第二方面提供一种弱内存序架构下的代码检查装置，包括：
获取单元，用于获取第一源代码和测试代码，第一源代码中包含阻塞标记，测试代码用于指示第一源代码能正确运行需符合的条件，第一源代码对应多个线程，多个线程具有至少一块共享内存，阻塞标记用于指示第一源代码中忙等循环的位置。
第一处理单元，用于根据获取单元获取的测试代码所指示的条件和第一源代码，为操作同一块共享内存的多线程生成在弱内存序架构下的多条执行流，其中，每条执行流为处理器运行多线程对同一块共享内存进行读操作和/或写操作的代码执行流程，多条执行流中包含阻塞标记的目标执行流中存在忙等循环。
第二处理单元，用于若调用多线程执行第一处理单元生成的目标执行流中的忙等循环时，一次忙等循环中的目标线程所执行的读操作引用不到一个未被引用过的写操作，则确定出目标执行流中的忙等循环为死循环，死循环指示第一源代码存在错误，目标线程为多线程中的任意一个。
在第二方面的一种可能的实现方式中，获取单元，用于获取第二源代码；从第二源代码中识别出表示忙等循环的代码块，并在表示忙等循环的代码块中添加阻塞标记，以得到第一源代码。
在第二方面的一种可能的实现方式中，第一处理单元，还用于将表示忙等循环的代码块中表示循环条件的符号由第一形式转换为第二形式；将阻塞标记添加在与第二形式的循环条件的符号关联的位置。
在第二方面的一种可能的实现方式中，第一处理单元，用于从第二源代码中识别出循环条件，循环条件包括恒为真或不是恒为真；若循环条件不是恒为真，则根据循环条件所对应的值确定循环条件所关联的代码块为忙等循环的代码块；若循环条件恒为真，则根据循环条件所关联的循环体确定循环条件所关联的代码块为忙等循环的代码块。
在第二方面的一种可能的实现方式中，第一处理单元，还用于过滤掉多条执行流中的冗余执行流，冗余执行流的至少两次循环中的至少两个写操作对应同一个写操作。
在第二方面的一种可能的实现方式中，第一处理单元，用于检查第一执行流的本次循环中的第一读操作，第一执行流为多条执行流中的任意一条执行流，本次循环为第一执行流中正在执行的一次忙等循环；若执行第一读操作的当前线程正在执行第一执行流中的忙等循环，则检查第一读操作所对应的写操作；若执行第一读操作的当前线程所引用的写操作，已被当前线程在之前的循环中执行第二读操作时引用过，则确定出第一执行流为冗余执行流；过滤掉第一执行流。
在第二方面的一种可能的实现方式中，第二处理单元，用于调用多线程执行目标执行流中的忙等循环时，在状态集合中为每个读操作设置一个状态标记；当忙等循环中产生一个写操作，则从状态集合中删除一个状态标记；直到忙等循环中不再产生写操作，若状态集合中还包含状态标记，则确定出目标执行流中的忙等循环为死循环。
本申请第三方面提供一种计算机设备，该计算机设备包括处理器、内存和存储有计算机程序的计算机可读存储介质；处理器与计算机可读存储介质耦合，处理器上运行的计算机执行指令，当计算机执行指令被处理器执行时，处理器执行如上述第一方面或第一方面任意一种可能的实现方式的方法。可选地，该计算机设备还可以包括输入/输出(input/output，I/O)接口，该存储有计算机程序的计算机可读存储介质可以是存储器。
本申请第四方面提供一种存储一个或多个计算机执行指令的计算机可读存储介质，当计算机执行指令被处理器执行时，处理器执行如上述第一方面或第一方面任意一种可能的实现方式的方法。
本申请第五方面提供一种存储一个或多个计算机执行指令的计算机程序产品，当计算机执行指令被处理器执行时，处理器执行如上述第一方面或第一方面任意一种可能的实现方式的方法。
本申请第六方面提供了一种芯片系统，该芯片系统包括至少一个处理器，至少一个处理器用于支持内存管理的装置实现上述第一方面或第一方面任意一种可能的实现方式中所涉及的功能。在一种可能的设计中，芯片系统还可以包括存储器，存储器，用于保存内存管理的装置必要的程序指令和数据。该芯片系统，可以由芯片构成，也可以包含芯片和其他分立器件。
其中，第二方面至第六方面或者其中任一种可能实现方式所带来的技术效果可参见第一方面或第一方面不同可能实现方式所带来的技术效果，此处不再赘述。
本申请实施例提供的方案，因为可以通过阻塞标记来检查目标执行流，即使该第一源代码会产生无穷多个执行流，也无需全部都做检查，所以，可以在有限的时间内完成对第一源代码的正确性检查。
附图说明
图1A是一代码块示例图；
图1B为另一代码块示例图；
图2是本申请实施例提供的计算机系统的一架构示意图；
图3是本申请实施例提供的一种弱内存序架构下的代码检查方法的一实施例示意图；
图4是本申请实施例提供的一种弱内存序架构下的代码检查方法的另一实施例示意图；
图5A是本申请实施例提供的一自旋锁代码的一示例示意图；
图5B是本申请实施例提供的一自旋锁变体代码的一示例示意图；
图6是本申请实施例提供的执行流过滤的一示意图；
图7是本申请实施例提供的执行流过滤的另一实施例示意图；
图8A是本申请实施例提供的一示例示意图；
图8B是本申请实施例提供的一示例示意图；
图9是本申请实施例提供的执行流检查一实施例；
图10是本申请实施例提供的一种弱内存序架构下的代码检查装置的一实施例示意图；
图11是本申请实施例提供的计算机设备的一结构示意图。
具体实施方式
下面结合附图，对本申请的实施例进行描述，显然，所描述的实施例仅仅是本申请一部分的实施例，而不是全部的实施例。本领域普通技术人员可知，随着技术发展和新场景的出现，本申请实施例提供的技术方案对于类似的技术问题，同样适用。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这里图示或描述的内容以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
本申请实施例提供一种弱内存序架构下的代码检查方法，用于解决在弱内存序架构下实现忙等循环代码的正确性检查。本申请实施例还提供了相应设备、计算机可读存储介质及计算机程序产品等。以下分别进行详细说明。
本申请实施例中，弱内存序架构是相对于强内存序架构来说的，弱内存序架构和强内存序架构都是指令集架构，强内存序架构可以包括x86架构，弱内存序架构可以包括高级精简指令集(advanced RISC machine，ARM)架构、基于精简指令集的第五代指令架构(reduced instruction set computing five，RISC-V)、无流水线互锁的微处理器架构(Microprocessor without Interlocked Pipeline Stages，MIPS)或基于精简指令集架构的指令集体系构架(performance optimization with enhanced RISC,POWER)。在强内存序架构下，处理器在调用线程操作内存时实际所执行的代码顺序会与代码的编写顺序保持一致。而在弱内存序架构下，处理器在调用线程操作内存时实际所执行的代码顺序可能会与代码的编写顺序不一致。
在实际应用中，通常会有将强内存序架构下的代码迁移到弱内存序架构下运行的情况，如：将业务从x86架构迁移到ARM架构时，在x86的强内存序架构下运行没有问题的代码，在ARM的弱内存序架构下可能会存在挂死或死锁的问题。
如图1A所示的代码块为代码编写顺序，如图1B所示的代码块为代码的实际执行顺序。在强内存序架构下，则会执行图1A所示的顺序，竖线100两侧的代码分别代表两个不同线程 中的代码。在实际编写顺序上，竖线100左侧的代码中，由于x在l之后被赋值为1，因此竖线100右侧的线程在await_while循环退出后，l一定会被赋值为0，l不等于1，所以，竖线100左侧的线程的await_while一定可以顺利退出。该图1A所示的代码迁移到弱内存序架构后，代码会产生重排，会执行图1B所示的流程，x是可能比l先赋值。那么竖线100右侧的线程执行完l＝0后，有可能轮到竖线100左侧的线程执行l＝1，因为l＝1,会导致await_while循环继续执行下去，最终导致竖线100左侧的await_while无法退出，程序挂死。
因此，为了避免代码运行中出现程序挂死或死锁的问题，在源代码要在弱内存序架构下实际运行前，需要在弱内存序架构下进行检查，若检查到问题，则说明这个源代码存在问题，需要修改。本申请所提供的方案即是对要在弱内存序架构下运行的源代码的检查方案。
本申请实施例提供的弱内存序架构下的代码检查方法应用于计算机系统，该计算系统可以为服务器、终端设备、虚拟机(virtual machine，VM)或容器(container)。
服务器可以是任意形态的物理机。
终端设备(也可以称为用户设备(user equipment，UE))是一种具有无线收发功能的设备，可以部署在陆地上，包括室内或室外、手持或车载；也可以部署在水面上(如轮船等)；还可以部署在空中(例如飞机、气球和卫星上等)。终端设备可以个人电脑(personal computer，PC)、手机(mobile phone)、平板电脑(pad)、带无线收发功能的电脑、虚拟现实(virtual reality，VR)终端、增强现实(augmented reality，AR)终端、工业控制(industrial control)中的无线终端、无人驾驶(self driving)中的无线终端、远程医疗(remote medical)中的无线终端、智能电网(smart grid)中的无线终端、运输安全(transportation safety)中的无线终端、智慧城市(smart city)中的无线终端、智慧家庭(smart home)中的无线终端、以物联网(internet of things，IoT)中的无线终端等。
虚拟机可以位于云端也可以位于本地。
本申请实施例提供的计算机系统的架构可以参阅图2进行理解。
图2是本申请实施例提供的计算机系统的一架构示意图。
如图2所示，该计算机系统10的架构可以包括应用层101、内核层102和硬件层103。
应用层101包括操作界面，程序检测的工作人员可以通过该操作界面启动源代码的检查过程。
内核层102包括获取模块，该获取模块用于获取源代码和测试代码，该内核层102还包括模型检查模块，还可以包括预处理模块。
该预处理模块用于对未添加阻塞标记的源代码添加阻塞标记。
该模型检查模块用于检查多线程执行包含阻塞标记的源代码访问同一共享内存时，该源代码的正确性。
硬件层103包括通信接口1031、处理器1032、内存1033和总线1034等。通信接口1031、处理器1032和内存1033通过总线1034连接。其中，处理器1032可以包括任何类型的通用计算电路或专用逻辑电路，例如：现场可编程门阵列(field-programmable gate array，FPGA) 或专用集成电路(application specific integrated circuit，ASIC)。也可以是耦合到一个或多个半导体基板的一个或多个处理器，例如中央处理器(central processing unit，CPU)。内存可以包括多个共享内存，如图2中示意出的共享内存1至共享内存n，每个共享内存是内存中的一块存储区域。每个共享内存具有一个内存地址，不同的共享内存的内存地址不同。
本申请实施例中，处理器可以运行多个线程执行根据源代码和测试代码产生的执行流，操作同一块共享内存，并检查包含阻塞标记的执行流中的忙等循环是否是死循环，从而确定该源代码中是否存在错误。因为可以通过阻塞标记来检查目标执行流，即使该源代码会产生无穷多个执行流，也无需全部都做检查，所以，可以在有限的时间内完成对源代码的正确性检查。
由上述图2部分的内容可知，本申请所提供的方案包括：一、源代码不经过预处理模块直接由模型检查模块执行代码检查的方案；二、源代码经过预处理模块进行预处理后再由模型检查模块执行代码检查的方案。下面以计算机设备作为执行主体分别进行介绍。
一、源代码不经过预处理模块直接由模型检查模块执行代码检查的方案。
如图3所示，本申请实施例提供的一种弱内存序架构下的代码检查方法的一实施例包括：
201.获取第一源代码和测试代码。
第一源代码中包含阻塞标记，测试代码用于指示第一源代码能正确运行需符合的条件，第一源代码对应多个线程，多个线程具有至少一块共享内存，阻塞标记用于指示第一源代码中忙等循环的位置。
本申请实施例中，第一源代码通常是带有忙等语义的多线程同步算法，如：自旋锁的代码、无锁列表的代码等。该第一源代码中的阻塞标记可以是人工添加。测试代码用于定义第一源代码的正确性，该测试代码中可以给出第一源代码需要满足什么样的条件才是正确的。如：测试代码中可以给出循环退出需满足的条件。
本申请实施例中，第一源代码对应多个线程指的是第一源代码可以被多个线程调用来执行对共享内存的操作。内存中的共享内存可以有多块，每块共享内存都有一个内存地址，不同共享内存的内存地址不同，多线程操作同一块共享内存时就会存在忙等循环的情况。忙等循环指的是一个线程操作共享内存时，其他线程占用处理器处于等待状态，直到忙等循环中的循环条件达到相应值时才会退出该忙等循环。在本申请中，忙等循环是一个代码块，该代码块中的代码表示了忙等循环的过程。
202.根据测试代码所指示的条件和第一源代码，为操作同一块共享内存的多线程生成在弱内存序架构下的多条执行流。
其中，每条执行流为处理器运行多线程对同一块共享内存进行读操作和/或写操作的代码执行流程，多条执行流中包含阻塞标记的目标执行流中存在忙等循环。
本申请实施例中，线程操作共享内存可以包括线程对共享内存执行读操作和/或写操作，“读操作和/或写操作”表示可以只执行读操作，只执行写操作，或者既执行读操作又执行写操作。通常在多线程操作共享内存时，既要执行读操作也要执行写操作，如：线程1执行读操作，线程2执行写操作。
本申请实施例中，执行流是多线程对同一块共享内存执行读操作和/或写操作的代码的实际执行流程，可以根据多线程对同一块内存的操作顺序来确定不同的执行流，如：有三个线程操作同一块共享内存，按照三个线程的执行顺序，可以有6个执行流。目标执行流中存在忙等循环，该忙等循环中包含阻塞标记，目标执行流不限于一条，多条执行流中的都每条执行流都可以是目标执行流，只要包含阻塞标记的执行流都可以理解为是目标执行流。
203.若调用多线程执行目标执行流中的忙等循环时，一次忙等循环中的目标线程所执行的读操作引用不到一个未被引用过的写操作，则确定出目标执行流中的忙等循环为死循环。
死循环指示第一源代码存在错误，目标线程为多线程中的任意一个。
本申请实施例中，会针对包含阻塞标记的目标执行流进行检查，因为目标执行流中存在忙等循环，所以，执行目标执行流的过程可能会执行多次忙等循环的代码，在每次忙等循环的过程都会涉及到读操作，通常一个新产生的读操作会对应一个新的写操作，因为一个新产生的读操作对应一个已经被别的读操作引用过的写操作只是一次无意义的循环，所以，当一个新产生的读操作引用不到一个新的写操作，也就是一个未被引用过的写操作时，就表示该目标执行流的忙等循环无法退出，是个死循环，那么则表示该第一源代码存在错误，不能正常执行。
本申请实施例提供的方案，因为可以通过阻塞标记来检查目标执行流，即使该第一源代码会产生无穷多个执行流，也无需全部都做检查，所以，可以在有限的时间内完成对第一源代码的正确性检查。
二、源代码经过预处理模块进行预处理后再由模型检查模块执行代码检查的方案。
如图4所示，本申请实施例提供的一种弱内存序架构下的代码检查方法的另一实施例包括：
301.计算机设备获取第二源代码和测试代码。
该第二源代码是没有添加阻塞标记的源代码。
302.从第二源代码中识别出表示忙等循环的代码块，并在表示忙等循环的代码块中添加阻塞标记，以得到第一源代码。
该预处理过程还可以将表示忙等循环的代码块中表示循环条件的符号由第一形式转换为第二形式；将阻塞标记添加在与第二形式的循环条件的符号关联的位置。
循环条件(loop-condition)表示循环结束的条件，如：while(lock)表示一个循环条件，其中，while表示循环条件的符号，将循环条件的符号由第一形式转换为第二形式可以是将第一形式的while转换为第二形式的if，当然，本申请不限于第一形式和第二形式的内容，只要第一形式的符号能表示循环条件，第二形式的符号能被检查出表示循环即可。阻塞标记可以是阻塞原语，如：modelchecker_block。本申请中，可以将阻塞标记会添加到循环条件之后，当然，本申请不限定阻塞标记所添加的具体位置，只要与第二形式的循环条件的符号相关联的位置即可。该方案便于快速检查出忙等循环，从而提高代码正确性检查的速度。
303.根据测试代码所指示的条件和第一源代码，为操作同一块共享内存的多线程生成 在弱内存序架构下的多条执行流。
其中，每条执行流为处理器运行多线程对同一块共享内存进行读操作和/或写操作的代码执行流程，多条执行流中包含阻塞标记的目标执行流中存在忙等循环。
304.若调用多线程执行目标执行流中的忙等循环时，一次忙等循环中的目标线程所执行的读操作引用不到一个未被引用过的写操作，则确定出目标执行流中的忙等循环为死循环。
死循环指示第一源代码存在错误，目标线程为多线程中的任意一个。
步骤303和步骤304可以参阅前述步骤202和203进行理解，此处不再重复赘述。
本申请实施例提供的方案，可以对不包阻塞标记的源代码进行预处理，添加上阻塞标记，这样就可以通过阻塞标记来检查目标执行流，即使该第一源代码会产生无穷多个执行流，也无需全部都做检查，所以，可以在有限的时间内完成对第一源代码的正确性检查。
可选地，上述步骤302中，从第二源代码中识别出表示忙等循环的代码块，包括：从第二源代码中识别出循环条件，循环条件包括恒为真或不是恒为真；若循环条件不是恒为真，则根据循环条件所对应的值确定循环条件所关联的代码块为忙等循环的代码块；若循环条件恒为真，则根据循环条件所关联的循环体确定循环条件所关联的代码块为忙等循环的代码块。
本申请实施例中，若不是恒为真，则循环条件通常为对某个原子变量的读操作或者原子读-交换(compare and swap)操作，通过该原子量变量的读操作读到的值是否满足退出循环来确定循环条件。若是恒为真，则需要通过循环体(loop–body)来定义退出的条件，从而确定代码中的循环条件。该种可能的实现方式，有利于快速确定循环条件，从而快速识别出源代码中的忙等循环的代码块。
本申请实施例中，循环条件不是恒为真的情况可以参阅图5A进行理解，如图5A所示的自旋锁代码的一示例示意图。如图5A所示，该示例图中包括12行代码，在每行代码前分别用1至12做了标记。其中，第3行while(lock)是循环条件，通过在循环中反复检查lock的值，来决定调用spinlock_lock函数的线程是继续第3行到第6行这个循环，还是退出循环执行第6行之后的代码。
本申请实施例中，循环条件恒为真的情况可以参阅图5B进行理解，如图5B所示的自旋锁变体代码的一示例示意图。如图5B所示，该示例图中包括13行代码，在每行代码前分别用1至13做了标记。其中，第3行while(true)表示循环条件恒为真，第3行至第6行的{if(lock＝＝0)break；}表示循环体，循环体中会反复检查lock的值，来决定调用spinlock_lock函数的线程是继续第3行到第7行这个循环，还是退出循环执行第7行之后的代码。
按照上述恒为真或不是恒为真识别出忙等循环后，可以将上述步骤302所介绍的方式，将循环条件做转换，并添加上循环标记，如：将图5A中第3行的循环条件while(lock)转换为if(！Locked)_MODELCHECKER_block()；将图5B中第3行的循环条件while(true)转换为if(！Locked)_MODELCHECKER_block()。当处理器检查到包含if(！Locked)_MODELCHECKER_block()的执行流时，就会将该执行流标记为潜在的死循环执行流，从而执行相应的检查过程，来确认该执行流是否为死循环执行流。
在上述图3对应的实施例的步骤202之后，或者在图4对应的实施例的步骤303之后，还可以对多条执行流执行过滤，过滤掉其中的冗余执行流，这样可以缩小对执行流检查的范围，从而缩短检查源代码的时间。
该过滤执行流的过程所使用的过滤算法可以称为等待进度条件(await progress condition，APC)算法。本申请实施例中，将循环生成的无穷多的执行流过滤为有限执行流的过程可以参阅图6进行理解。如图6所示，计算机设备接收到源代码和测试代码后，会进行模型检查，该模型检查过程会执行图遍历和循环遍历，执行图遍历会遍历该源代码中的每个分支，执行循环遍历会针对每个分支的循环进行遍历，循环遍历过程会产生无穷多的执行流，本申请中会采用APC过滤算法对无穷多的执行流进行过滤，过滤掉其中的冗余执行流，从而的到有限的执行流，其中，冗余执行流的至少两次循环中的至少两个写操作对应同一个写操作。
关于上述APC过滤多条执行流中的冗余执行流的具体过程可以参阅图7进行理解。
如图7所示，该过滤过程包括：
401.检查执行流。
该步骤401检查的执行流可以是任意一个执行流，本申请中可以将其称为第一执行流。可以是检查第一执行流的本次循环中的读操作。该读操作可以是本次循环中的任意一个读操作，可以将其称为第一读操作。
第一执行流为多条执行流中的任意一条执行流，本次循环为第一执行流中正在执行的一次忙等循环。
402.确定是否为读操作。
该步骤402指的是确定所检查的操作是读操作还是写操作，若是读操作，则执行步骤403，若否，则表示不是读操作，是写操作，则执行步骤407。
403.若是读操作，则确定该读操作是否在忙等循环内，若是，则执行步骤404，若否，则执行步骤407。
404.检查该读操作所对应的写操作。
也就是：若执行第一读操作的当前线程正在执行第一执行流中的忙等循环，则检查第一读操作所对应的写操作。
405.确定是否找到该读操作所对应的写操作，若是，则执行步骤407，若否，则执行步骤406。
406.若执行该读操作的当前线程所引用的写操作，已被当前线程在之前的循环中执行读操作时引用过，则确定出该执行流为冗余执行流；过滤掉该执行流。并生成下一个执行流，重复上述过程。
407.继续执行模型查找遍历。
若步骤402确定所检查的操作为写操作，或者步骤405找不到该读操作对应的写操作，则继续执行模型查找遍历。
也就是说：若执行第一读操作的当前线程所引用的写操作，已被当前线程在之前的循环中执行第二读操作时引用过，则确定出第一执行流为冗余执行流；过滤掉第一执行流。
上述APC算法在模型检查的流程中确保忙等条件的每一次读操作都是从新的写操作中得到值，而不是旧值。这样能删除掉无意义的读遍历，确保每一次在忙等循环条件里读到的都是新值。
本申请实施例中，确定冗余执行流的过程可以是通过检查读操作是否有对应的未被引用的写操作的方式来进行的，若一个写操作两次被不属于同一次忙等循环中的线程所执行的两个写操作所引用到，则表示所执行的第一执行流是冗余执行流，则需要过滤掉该第一执行流。该种过滤冗余执行流的方案，可以加速缩小对执行流检查的范围。
在具体应用中，关于是否使用APC过滤算法所产生的执行流可以参阅图8A所示的未使用APC过滤的示意图和图8B所示的使用了APC过滤的示意图的对比进行理解。
如图8A所示，针对一个await_while(l＜3)的循环条件，在l＝3时该循环才退出，因此，在该循环条件下可以产生如图8A中所示的多条执行流，图8A中，W(l,0)表示l＝0时的初始写操作。W(l,1)表示l＝1时的写操作，W(l,2)表示l＝2时的写操作，W(l,3)表示l＝3时的写操作。图8A中的rf表示读操作与写操作之间的引用关系。图8A中的引用关系包括读操作R(1)1引用了W(l,0)，读操作R(1)2引用了W(l,2)，读操作R(1)3引用了W(l,2)，读操作R(1)4引用了W(l,3)，其中，W(l,2)被两个读操作R(1)2和R(1)3引用了，其中，R(1)3是在R(1)2引用的W(l,2)，所以，包含了R(1)3的这条执行流为用于执行流，若是按照本申请实施例提供的APC过滤算法进行过滤，则可以得到如图8B所示的示意图。从图8A和图8B的对比可以看出，通过APC过滤冗余执行流，可以缩小对执行流检查的范围，提高源代码正确性检查的效率。
可选地，本申请实施例提供的上述步骤203或者步骤304可以包括：调用多线程执行目标执行流中的忙等循环时，在状态集合中为每个读操作设置一个状态标记；当忙等循环中产生一个写操作，则从状态集合中删除一个状态标记；直到忙等循环中不再产生写操作，若状态集合中还包含状态标记，则确定出目标执行流中的忙等循环为死循环。
本申请实施例中，该检查目标执行流的过程可以参阅图9进行理解，如图9所示，该检查目标执行流的过程可以包括：
501.检查操作指令，若该操作指令为写操作，则执行步骤502，若该操作指令为读操作，则执行步骤503。
该操作指令指的是线程调用该目标执行流对共享内存的操作指令。
502.若操作指令为写操作，则记录写地址，将写操作记录进写操作集合，并继续执行步骤506。
该步骤会在写操作集合中增加一个写操作。
503.若操作指令为读操作，则记录读地址，在状态集合中为读操作设置一个状态标记。
状态集合用于存放状态标记，每个状态标记代表一个新的读操作。
504.检查是否可以从写操作集合中为读操作确定对应的写操作。若是，则执行步骤505，若否，则执行步骤506。
505.若为读操作确定了对应的写操作，则从状态集合中移除该读操作对应的状态标记，并从写操作集合中移除对应的写操作，然后执行步骤506。
506.检查是否有下一条操作指令，若有，则重复执行步骤501，若无，则执行步骤507。
507.检查状态集合中是否还存在状态标记，若是，则执行步骤508。
508.若状态集合中还存在状态标记，则报告存在死循环。
本申请实施例中，可以通过状态标记的方式来确定是否每个新产生的读操作都会有一个新产生的写操作，若状态集合中的状态标记有剩余，则表示新产生的读操作没有对应的新产生的写操作了，则表示该忙等循环无法退出，该忙等循环为死循环。该种实现方式有利于快速确定出忙等循环是否可终止，若不可终止，则表示该第一源代码存在错误。
以上描述了在弱内存序架构下的代码检查方法，下面结合附图介绍本申请实施例提供的一种弱内存序架构下的代码检查装置60。
如图10所示，本申请实施例提供的弱内存序架构下的代码检查装置60的一实施例包括：
获取单元601，用于获取第一源代码和测试代码，第一源代码中包含阻塞标记，测试代码用于指示第一源代码能正确运行需符合的条件，第一源代码对应多个线程，多个线程具有至少一块共享内存，阻塞标记用于指示第一源代码中忙等循环的位置。该获取单元601可以执行上述方法实施例部分的步骤201或步骤301。
第一处理单元602，用于根据获取单元601获取的测试代码所指示的条件和第一源代码，为操作同一块共享内存的多线程生成在弱内存序架构下的多条执行流，其中，每条执行流为处理器运行多线程对同一块共享内存进行读操作和/或写操作的代码执行流程，多条执行流中包含阻塞标记的目标执行流中存在忙等循环。该第一处理单元602可以执行上述方法实施例部分的步骤202或303。
第二处理单元603，用于若调用多线程执行第一处理单元602生成的目标执行流中的忙等循环时，一次忙等循环中的目标线程所执行的读操作引用不到一个未被引用过的写操作，则确定出目标执行流中的忙等循环为死循环，死循环指示第一源代码存在错误，目标线程为多线程中的任意一个。该第二处理单元603可以执行上述方法实施例部分的步骤203或304。
本申请实施例提供的方案，因为可以通过阻塞标记来检查目标执行流，即使该第一源代码会产生无穷多个执行流，也无需全部都做检查，所以，可以在有限的时间内完成对第一源代码的正确性检查。
可选地，获取单元601，用于获取第二源代码；从第二源代码中识别出表示忙等循环的代码块，并在表示忙等循环的代码块中添加阻塞标记，以得到第一源代码。该获取单元601可以执行上述方法实施例部分的步骤302。
可选地，第一处理单元602，还用于将表示忙等循环的代码块中表示循环条件的符号由第一形式转换为第二形式；将阻塞标记添加在与第二形式的循环条件的符号关联的位置。
可选地，第一处理单元602，用于从第二源代码中识别出循环条件，循环条件包括恒为真或不是恒为真；若循环条件不是恒为真，则根据循环条件所对应的值确定循环条件所关联的代码块为忙等循环的代码块；若循环条件恒为真，则根据循环条件所关联的循环体确定循环条件所关联的代码块为忙等循环的代码块。
可选地，第一处理单元602，还用于过滤掉多条执行流中的冗余执行流，冗余执行流的至少两次循环中的至少两个写操作对应同一个写操作。
可选地，第一处理单元602，用于检查第一执行流的本次循环中的第一读操作，第一执行流为多条执行流中的任意一条执行流，本次循环为第一执行流中正在执行的一次忙等循环；若执行第一读操作的当前线程正在执行第一执行流中的忙等循环，则检查第一读操作所对应的写操作；若执行第一读操作的当前线程所引用的写操作，已被当前线程在之前的循环中执行第二读操作时引用过，则确定出第一执行流为冗余执行流；过滤掉第一执行流。
可选地，第二处理单元603，用于调用多线程执行目标执行流中的忙等循环时，在状态集合中为每个读操作设置一个状态标记；当忙等循环中产生一个写操作，则从状态集合中删除一个状态标记；直到忙等循环中不再产生写操作，若状态集合中还包含状态标记，则确定出目标执行流中的忙等循环为死循环。
本申请实施例中，获取单元601可以对应上述图2中的(源代码+测试代码)获取模块，第一处理单元602和第二处理单元603可以对应上述图2中的模型检查模块，获取单元601还可以对应上述图2中的预处理模块。
以上所描述的装置60可以参阅前面方法实施例的相应内容进行理解，此处不在重复赘述。
图11所示，为本申请的实施例提供的计算机设备70的一种可能的逻辑结构示意图。计算机设备70包括：处理器701、通信接口702、物理内存703以及总线704。处理器701、通信接口702以及物理内存703通过总线704相互连接。在本申请的实施例中，处理器701用于对计算机设备70的动作进行控制管理，例如，处理器701用于执行图2至图8B的方法实施例中的步骤。通信接口702用于支持计算机设备70进行通信。物理内存703，用于存储计算机设备70的程序代码和数据，并为进程组提供内存空间。
其中，处理器701可以是中央处理器单元，通用处理器，数字信号处理器，专用集成电路，现场可编程门阵列或者其他可编程逻辑器件、晶体管逻辑器件、硬件部件或者其任意组合。其可以实现或执行结合本申请公开内容所描述的各种示例性的逻辑方框，模块和电路。处理器701也可以是实现计算功能的组合，例如包含一个或多个微处理器组合，数字信号处理器和微处理器的组合等等。总线704可以是外设部件互连标准(Peripheral Component Interconnect，PCI)总线或扩展工业标准结构(Extended Industry Standard Architecture，EISA)总线等。总线可以分为地址总线、数据总线、控制总线等。为便于表示，图11中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
在本申请的另一实施例中，还提供一种计算机可读存储介质，计算机可读存储介质中存储有计算机执行指令，当设备的处理器执行该计算机执行指令时，设备执行上述图2至图8B中处理器所执行的步骤。
在本申请的另一实施例中，还提供一种计算机程序产品，该计算机程序产品包括计算机执行指令，该计算机执行指令存储在计算机可读存储介质中；当设备的处理器执行该计算机执行指令时，设备执行上述图2至图8B中处理器所执行的步骤。
在本申请的另一实施例中，还提供一种芯片系统，该芯片系统包括处理器，该处理器用于支持内存管理的装置实现上述图2至图8B中处理器所执行的步骤。在一种可能的设计中，芯片系统还可以包括存储器，存储器，用于保存数据写入的装置必要的程序指令和数据。 该芯片系统，可以由芯片构成，也可以包含芯片和其他分立器件。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请实施例的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请实施例所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请实施例各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请实施例的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请实施例各个实施例方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上，仅为本申请实施例的具体实施方式，但本申请实施例的保护范围并不局限于此。

Claims (16)

  1. 一种弱内存序架构下的代码检查方法，其特征在于，包括：
    获取第一源代码和测试代码，所述第一源代码中包含阻塞标记，所述测试代码用于指示所述第一源代码能正确运行需符合的条件，所述第一源代码对应多个线程，所述多个线程具有至少一块共享内存，所述阻塞标记用于指示所述第一源代码中忙等循环的位置；
    根据所述测试代码所指示的条件和所述第一源代码，为操作同一块共享内存的所述多线程生成在弱内存序架构下的多条执行流，其中，每条执行流为处理器运行所述多线程对所述同一块共享内存进行读操作和/或写操作的代码执行流程，所述多条执行流中包含阻塞标记的目标执行流中存在忙等循环；
    若调用所述多线程执行所述目标执行流中的忙等循环时，一次忙等循环中的目标线程所执行的读操作引用不到一个未被引用过的写操作，则确定出所述目标执行流中的忙等循环为死循环，所述死循环指示所述第一源代码存在错误，所述目标线程为所述多线程中的任意一个。
  2. 根据权利要求1所述的方法，其特征在于，所述获取第一源代码，包括：
    获取第二源代码；
    从所述第二源代码中识别出表示忙等循环的代码块，并在所述表示忙等循环的代码块中添加所述阻塞标记，以得到所述第一源代码。
  3. 根据权利要求2所述的方法，其特征在于，所述方法还包括：
    将所述表示忙等循环的代码块中表示循环条件的符号由第一形式转换为第二形式；
    所述在所述表示忙等循环的代码块中添加所述阻塞标记，包括：
    将所述阻塞标记添加在与所述第二形式的循环条件的符号关联的位置。
  4. 根据权利要求2或3所述的方法，其特征在于，所述从所述第二源代码中识别出表示忙等循环的代码块，包括：
    从所述第二源代码中识别出循环条件，所述循环条件包括恒为真或不是恒为真；
    若所述循环条件不是恒为真，则根据所述循环条件所对应的值确定所述循环条件所关联的代码块为忙等循环的代码块；
    若所述循环条件恒为真，则根据所述循环条件所关联的循环体确定所述循环条件所关联的代码块为忙等循环的代码块。
  5. 根据权利要求1-4任一项所述的方法，其特征在于，所述方法还包括：
    过滤掉所述多条执行流中的冗余执行流，所述冗余执行流的至少两次循环中的至少两个写操作对应同一个写操作。
  6. 根据权利要求5所述的方法，其特征在于，所述过滤掉所述多条执行流中的冗余执行流，包括：
    检查第一执行流的本次循环中的第一读操作，所述第一执行流为所述多条执行流中的任意一条执行流，所述本次循环为所述第一执行流中正在执行的一次忙等循环；
    若执行所述第一读操作的当前线程正在执行所述第一执行流中的忙等循环，则检查所述第一读操作所对应的写操作；
    若执行所述第一读操作的所述当前线程所引用的写操作，已被所述当前线程在之前的循环中执行第二读操作时引用过，则确定出所述第一执行流为所述冗余执行流；
    过滤掉所述第一执行流。
  7. 根据权利要求1-6任一项所述的方法，其特征在于，所述若调用所述多线程执行所述目标执行流中的忙等循环时，一次忙等循环中的目标线程所执行的读操作引用不到一个未被引用过的写操作，则确定出所述目标执行流中的忙等循环为死循环，包括：
    调用所述多线程执行所述目标执行流中的忙等循环时，在状态集合中为每个读操作设置一个状态标记；
    当所述忙等循环中产生一个写操作，则从所述状态集合中删除一个状态标记；
    直到所述忙等循环中不再产生写操作，若所述状态集合中还包含状态标记，则确定出所述目标执行流中的忙等循环为死循环。
  8. 一种计算机设备，其特征在于，包括：处理器、内存和存储有计算机程序的计算机可读存储介质；所述处理器与所述计算机可读存储介质耦合，所述计算机程序被所述处理器执行时实现如下步骤：
    获取第一源代码和测试代码，所述第一源代码中包含阻塞标记，所述测试代码用于指示所述第一源代码能正确运行需符合的条件，所述第一源代码对应多个线程，所述多个线程具有至少一块共享内存，所述阻塞标记用于指示所述第一源代码中忙等循环的位置；
    根据所述测试代码所指示的条件和所述第一源代码，为操作同一块共享内存的所述多线程生成在弱内存序架构下的多条执行流，其中，每条执行流为处理器运行所述多线程对所述同一块共享内存进行读操作和/或写操作的代码执行流程，所述多条执行流中包含阻塞标记的目标执行流中存在忙等循环；
    若调用所述多线程执行所述目标执行流中的忙等循环时，一次忙等循环中的目标线程所执行的读操作引用不到一个未被引用过的写操作，则确定出所述目标执行流中的忙等循环为死循环，所述死循环指示所述第一源代码存在错误，所述目标线程为所述多线程中的任意一个。
  9. 根据权利要求8所述的计算机设备，其特征在于，所述处理器用于：
    获取第二源代码；
    从所述第二源代码中识别出表示忙等循环的代码块，并在所述表示忙等循环的代码块中添加所述阻塞标记，以得到所述第一源代码。
  10. 根据权利要求9所述的计算机设备，其特征在于，所述处理器还用于：
    将所述表示忙等循环的代码块中表示循环条件的符号由第一形式转换为第二形式；
    将所述阻塞标记添加在与所述第二形式的循环条件的符号关联的位置。
  11. 根据权利要求9或10所述的计算机设备，其特征在于，所述处理器用于：
    从所述第二源代码中识别出循环条件，所述循环条件包括恒为真或不是恒为真；
    若所述循环条件不是恒为真，则根据所述循环条件所对应的值确定所述循环条件所关联的代码块为忙等循环的代码块；
    若所述循环条件恒为真，则根据所述循环条件所关联的循环体确定所述循环条件所关 联的代码块为忙等循环的代码块。
  12. 根据权利要求8-11任一项所述的计算机设备，其特征在于，所述处理器还用于：
    过滤掉所述多条执行流中的冗余执行流，所述冗余执行流的至少两次循环中的至少两个写操作对应同一个写操作。
  13. 根据权利要求12所述的计算机设备，其特征在于，所述处理器用于：
    检查第一执行流的本次循环中的第一读操作，所述第一执行流为所述多条执行流中的任意一条执行流，所述本次循环为所述第一执行流中正在执行的一次忙等循环；
    若执行所述第一读操作的当前线程正在执行所述第一执行流中的忙等循环，则检查所述第一读操作所对应的写操作；
    若执行所述第一读操作的所述当前线程所引用的写操作，已被所述当前线程在之前的循环中执行第二读操作时引用过，则确定出所述第一执行流为所述冗余执行流；
    过滤掉所述第一执行流。
  14. 根据权利要求8-13任一项所述的计算机设备，其特征在于，所述处理器用于：
    调用所述多线程执行所述目标执行流中的忙等循环时，在状态集合中为每个读操作设置一个状态标记；
    当所述忙等循环中产生一个写操作，则从所述状态集合中删除一个状态标记；
    直到所述忙等循环中不再产生写操作，若所述状态集合中还包含状态标记，则确定出所述目标执行流中的忙等循环为死循环。
  15. 一种计算机可读存储介质，其上存储有计算机程序，其特征在于，所述计算机程序被处理器执行时实现如权利要求1-7任一项所述的方法。
  16. 一种芯片系统，其特征在于，包括处理器，所述处理器被调用用于执行如权利要求1-7任一项所述的方法。
PCT/CN2022/086590 2021-04-14 2022-04-13 一种弱内存序架构下的代码检查方法及相应设备 WO2022218337A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP22787559.8A EP4318211A1 (en) 2021-04-14 2022-04-13 Method for inspecting code under weak memory order architecture, and corresponding device
US18/484,641 US20240045787A1 (en) 2021-04-14 2023-10-11 Code inspection method under weak memory ordering architecture and corresponding device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110401685.0A CN115202662B (zh) 2021-04-14 2021-04-14 一种弱内存序架构下的代码检查方法及相应设备
CN202110401685.0 2021-04-14

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/484,641 Continuation US20240045787A1 (en) 2021-04-14 2023-10-11 Code inspection method under weak memory ordering architecture and corresponding device

Publications (1)

Publication Number Publication Date
WO2022218337A1 true WO2022218337A1 (zh) 2022-10-20

Family

ID=83574205

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/086590 WO2022218337A1 (zh) 2021-04-14 2022-04-13 一种弱内存序架构下的代码检查方法及相应设备

Country Status (4)

Country Link
US (1) US20240045787A1 (zh)
EP (1) EP4318211A1 (zh)
CN (1) CN115202662B (zh)
WO (1) WO2022218337A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117667103A (zh) * 2023-10-19 2024-03-08 北京邮电大学 基于c11弱内存模型的c语言程序验证方法及装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115202662B (zh) * 2021-04-14 2024-06-18 华为技术有限公司 一种弱内存序架构下的代码检查方法及相应设备

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101833440A (zh) * 2010-04-30 2010-09-15 西安交通大学 编译器支持下的推测多线程内存数据同步执行方法及装置
CN104572451A (zh) * 2014-12-25 2015-04-29 北京京东尚科信息技术有限公司 一种代码效率检查方法及系统
US20190196810A1 (en) * 2016-12-22 2019-06-27 The United States Of America As Represented By The Secretary Of The Navy Systems and methods for automated renumbering, reformatting, and re-referencing of branching statements or go-to instruction line referencing within modified code using a dual-pass approach that includes operations using predicted new line numbers, error detection/correction, and alignment correction processing
CN109960643A (zh) * 2017-12-22 2019-07-02 网宿科技股份有限公司 一种代码测试方法和装置
CN111045832A (zh) * 2019-11-13 2020-04-21 烽火通信科技股份有限公司 一种软件死循环或阻塞监控的方法及系统

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8930926B2 (en) * 2008-02-08 2015-01-06 Reservoir Labs, Inc. System, methods and apparatus for program optimization for multi-threaded processor architectures
US8612959B2 (en) * 2011-10-03 2013-12-17 International Business Machines Corporation Linking code for an enhanced application binary interface (ABI) with decode time instruction optimization
CN108509772B (zh) * 2018-02-12 2022-01-07 北京梆梆安全科技有限公司 基于执行顺序和单点逻辑的源代码加固方法及装置
CN114518884A (zh) * 2020-11-19 2022-05-20 华为技术有限公司 修复弱内存序问题的方法及装置
CN115202662B (zh) * 2021-04-14 2024-06-18 华为技术有限公司 一种弱内存序架构下的代码检查方法及相应设备
CN116841564B (zh) * 2023-08-29 2023-11-14 腾讯科技（深圳）有限公司 一种数据处理方法、装置、设备以及计算机可读存储介质

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101833440A (zh) * 2010-04-30 2010-09-15 西安交通大学 编译器支持下的推测多线程内存数据同步执行方法及装置
CN104572451A (zh) * 2014-12-25 2015-04-29 北京京东尚科信息技术有限公司 一种代码效率检查方法及系统
US20190196810A1 (en) * 2016-12-22 2019-06-27 The United States Of America As Represented By The Secretary Of The Navy Systems and methods for automated renumbering, reformatting, and re-referencing of branching statements or go-to instruction line referencing within modified code using a dual-pass approach that includes operations using predicted new line numbers, error detection/correction, and alignment correction processing
CN109960643A (zh) * 2017-12-22 2019-07-02 网宿科技股份有限公司 一种代码测试方法和装置
CN111045832A (zh) * 2019-11-13 2020-04-21 烽火通信科技股份有限公司 一种软件死循环或阻塞监控的方法及系统

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117667103A (zh) * 2023-10-19 2024-03-08 北京邮电大学 基于c11弱内存模型的c语言程序验证方法及装置

Also Published As

Publication number Publication date
CN115202662B (zh) 2024-06-18
US20240045787A1 (en) 2024-02-08
EP4318211A1 (en) 2024-02-07
CN115202662A (zh) 2022-10-18

Similar Documents

Publication Publication Date Title
WO2022218337A1 (zh) 一种弱内存序架构下的代码检查方法及相应设备
CN102648449B (zh) 一种用于处理干扰事件的方法和图形处理单元
JP5035277B2 (ja) 共有メモリに対するアトミックな更新を可能にするロックメカニズム
US9459876B2 (en) System, method, and computer program product for managing divergences and synchronization points during thread block execution by using a double sided queue for token storage
US20160004478A1 (en) Wait-free algorithm for inter-core, inter-process, or inter-task communication
CN111208933B (zh) 数据访问的方法、装置、设备和存储介质
JP2014235747A (ja) データ処理システム
CN105074656B (zh) 管理并发谓词表达式的方法和装置
TWI764997B (zh) 圖形處理單元及處理圖形應用程式的方法
US20160147516A1 (en) Execution of complex recursive algorithms
US20130304996A1 (en) Method and system for run time detection of shared memory data access hazards
CN109117201A (zh) 一种程序退出的方法及相关设备
WO2015171862A1 (en) Detecting data dependencies of instructions associated with threads in a simultaneous multithreading scheme
US10599638B2 (en) System and method for identifying maximal independent sets in parallel
CN109885489B (zh) 驱动程序中数据竞争检测方法及装置
US20120059997A1 (en) Apparatus and method for detecting data race
CN116257338A (zh) Blender渲染在神威超算中的并行优化方法及系统
CN115905040A (zh) 计数器的处理方法、图形处理器、设备及存储介质
US10956240B2 (en) Sharing data by a virtual machine
CN111078449B (zh) 信息处理方法、信息处理装置及终端设备
US20070043746A1 (en) System and method for asynchronous linked data structure traversal
US20190042332A1 (en) Hardware locking primitive system for hardware and methods for generating same
CN111522600B (zh) 一种在dsp上的异构计算框架构建方法及系统
US11875057B2 (en) Shared structure for a logic analyzer and programmable state machine
US11687435B2 (en) Programmable state machine for a hardware performance monitor

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22787559

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2022787559

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2022787559

Country of ref document: EP

Effective date: 20231024

NENP Non-entry into the national phase

Ref country code: DE