WO2022217673A1 - 基于忆阻器的朴素贝叶斯分类器设计方法、系统及分类器 - Google Patents

基于忆阻器的朴素贝叶斯分类器设计方法、系统及分类器 Download PDF

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WO2022217673A1
WO2022217673A1 PCT/CN2021/092106 CN2021092106W WO2022217673A1 WO 2022217673 A1 WO2022217673 A1 WO 2022217673A1 CN 2021092106 W CN2021092106 W CN 2021092106W WO 2022217673 A1 WO2022217673 A1 WO 2022217673A1
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memristor
conductance
naive bayes
bayes classifier
pixel
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PCT/CN2021/092106
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French (fr)
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孙华军
周佐湃
李莉
缪向水
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华中科技大学
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V10/00—Arrangements for image or video recognition or understanding
    • G06V10/70—Arrangements for image or video recognition or understanding using pattern recognition or machine learning
    • G06V10/84—Arrangements for image or video recognition or understanding using pattern recognition or machine learning using probabilistic graphical models from image or video features, e.g. Markov models or Bayesian networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V10/00—Arrangements for image or video recognition or understanding
    • G06V10/70—Arrangements for image or video recognition or understanding using pattern recognition or machine learning
    • G06V10/764—Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F18/00—Pattern recognition
    • G06F18/20—Analysing
    • G06F18/21—Design or setup of recognition systems or techniques; Extraction of features in feature space; Blind source separation
    • G06F18/214—Generating training patterns; Bootstrap methods, e.g. bagging or boosting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F18/00—Pattern recognition
    • G06F18/20—Analysing
    • G06F18/24—Classification techniques
    • G06F18/241—Classification techniques relating to the classification model, e.g. parametric or non-parametric approaches
    • G06F18/2415—Classification techniques relating to the classification model, e.g. parametric or non-parametric approaches based on parametric or probabilistic models, e.g. based on likelihood ratio or false acceptance rate versus a false rejection rate
    • G06F18/24155—Bayesian classification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G06N3/082—Learning methods modifying the architecture, e.g. adding, deleting or silencing nodes or connections
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V10/00—Arrangements for image or video recognition or understanding
    • G06V10/94—Hardware or software architectures specially adapted for image or video understanding
    • G06V10/955—Hardware or software architectures specially adapted for image or video understanding using specific electronic processors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the invention belongs to the field of information technology, and more particularly, relates to a design method, system and classifier of a memristor-based naive Bayes classifier.
  • the in-memory computing architecture based on new memory can realize the integration of storage and computing, which is expected to break through the traditional computer architecture and greatly improve the performance of existing computers.
  • the memristor has the characteristics of non-volatility, fast read and write speed, easy integration, and low power consumption, making it a hot spot for the next generation of memory.
  • the neural network learning algorithm has complex derivation calculations, and its calculation process is difficult to implement on memristors, requiring additional computing resources.
  • the non-ideal characteristics of memristor such as device inconsistency, device error, limited number of conductance states, nonlinearity and asymmetry of conductance distribution, have a great impact on the performance of neural network systems, and also restrict its application process. .
  • Naive Bayes classifier is a probabilistic classifier based on Bayes' theorem. Compared with other neural network algorithms, the Naive Bayes classifier has a simple structure, stable performance, and is more friendly to hardware.
  • the naive Bayes classifier mainly uses the training data to learn the joint probability distribution, and then obtains the posterior probability distribution. Learning the joint probability distribution requires logarithmic computation, which also restricts the implementation of naive Bayesian classifiers on memristors.
  • the multiplication process in the naive Bayesian algorithm is usually realized through the crossbar array of the memristor based on Ohm's law, and the final result is obtained by accumulation, but only the properties can be realized. There are no more than three recognition tasks, which greatly limits its universality.
  • the present invention provides a memristor-based Naive Bayesian classifier design method, system and classifier, the purpose of which is to overcome the conductance change of memristor in neural network applications. Asymmetry and nonlinear constraints, to avoid accuracy degradation caused by non-ideal resistive behavior, and improve the universality of Naive Bayes classifiers.
  • the conductance of the memristor is:
  • the classification statistics calculation probability corresponding to the memristor and the conductance of the memristor satisfy:
  • G is the conductance of the memristor
  • N 1 is the number of pulses applied to the memristor
  • P is the conditional probability value corresponding to the memristor
  • ln P is the statistical calculation probability of the classification
  • a is the first fitting parameter
  • b is the second fitting parameter.
  • step S3 it also includes: acquiring the pixel value of each pixel in the picture to be classified, and when the pixel value of the i-th pixel is 0, applying a pulse to the 2i-1th column of memristors , otherwise, apply a pulse to the memristors in the 2i-th column; compare the currents at the output terminals of the memristors in each row in the naive Bayes classifier, and the type of the row corresponding to the minimum current is the type of the picture to be classified.
  • the S1 includes: acquiring the number M of sample types in the training sample, and dividing the training sample into pixels, so as to divide each training sample into N pixels; dividing the memristive
  • the number of rows of the memristor array is designed to be M, and the number of columns of the memristor array is designed to be 2N.
  • the S2 further includes: performing equal scaling on h j,2i-1 and h j,2i , In order to reduce each h j,2i-1 and h j,2i to the range of the number of samples corresponding to the conductance range of the memristor; in the S3, according to the reduced result of h j,2i-1 and h j,2i
  • the conductances of the memristor Rj,2i-1 and the memristor Rj,2i are modulated, respectively.
  • the step after S3 further includes: according to the type j' of the newly added training sample and the pixel value of each pixel i in the newly added training sample, in the modulated A pulse is applied to the memristor at row j', column 2i-1 or at row j', column 2i in the Naive Bayes classifier for conductance modulation.
  • the step after S3 further includes: performing a pruning process on the memristor columns corresponding to each pixel in the modulated Naive Bayes classifier. optimization.
  • the method further includes: initializing the conductance of each memristor in the memristor array to the maximum conductance value of the memristor.
  • a memristor-based naive Bayes classifier design system comprising: a building block for building a naive Bayes classifier comprising M rows ⁇ 2N columns of memristor arrays M is the number of types output by the Naive Bayes classifier, N is the number of pixels in the picture, and the pixel value of each pixel is 0 or 1; the selection and calculation module is used to extract the training samples from the training samples.
  • the modulated Naive Bayes classifier is used to identify the type of the picture to be classified.
  • a memristor-based naive Bayes classifier is provided, the naive Bayes classifier is designed by the above-mentioned memristor-based naive Bayes classifier design method get.
  • the attribute information of each attribute is scaled, so that one pulse corresponds to the information of multiple samples, so as to realize the training according to all the training samples.
  • the samples are used to train the classifier to ensure the classification accuracy of the classifier after training;
  • the attributes of the training samples are screened to realize the optimization of the naive Bayesian classifier, which is further improved to a memristor-based selection Bayesian classifier, which can better tolerate Nonideal properties of memristors.
  • FIG. 1 is a flowchart of a memristor-based Naive Bayes classifier design method provided by an embodiment of the present invention
  • FIG. 2 is a schematic diagram of a circuit structure of a memristor-based naive Bayes classifier according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a fitting curve of a change in conductance of a memristor reset process with the number of applied pulses according to an embodiment of the present invention
  • FIG. 4 is a block diagram of a design system for a memristor-based naive Bayes classifier according to an embodiment of the present invention.
  • FIG. 1 is a flowchart of a method for designing a memristor-based naive Bayes classifier according to an embodiment of the present invention. Referring to FIG. 1 , in conjunction with FIGS. 2 to 3 , the design method of the memristor-based naive Bayes classifier in this embodiment will be described in detail. Referring to FIG. 1, the method includes operations S1-operation S3.
  • Operation S1 construct a naive Bayes classifier including M rows ⁇ 2N columns of memristor arrays, where M is the number of types output by the naive Bayes classifier, N is the number of pixels in the image, and each pixel The pixel value of 0 or 1.
  • the number M of sample types in the training sample is obtained, and the sample pictures in the training sample are divided into pixels, so that each training sample is divided into N pixels.
  • the sample images in the training samples are binarized into black and white images, so that each pixel has two attribute values of 0 and 1, and two columns of memristors are designed for each pixel.
  • the number of rows of the memristor array is designed to be M rows, and the number of columns of the memristor array is designed to be 2N to form an M ⁇ 2N memristor array, as shown in FIG. 2 .
  • the sample types in the training sample include ten types: 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9. That is, the number M of sample types is 10, and thus 10 rows of memristors need to be designed. Each row of memristors corresponds to one sample type. For example, in the circuit structure shown in FIG. 2, each row from top to bottom corresponds to sample types 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9 in sequence.
  • the MNIST data set is selected as a training sample, and the MNIST data picture is binarized into a black and white image, each picture contains 28 ⁇ 28 pixels, and each pixel represents an attribute, with a total of 784 attributes.
  • Each pixel has two pixel values (ie, attribute values) of 0 and 1.
  • a pixel value of 0 indicates that the pixel is white
  • a pixel value of 1 indicates that the pixel is black.
  • Two memristors are used to represent an attribute, representing the two cases where the pixel value is 0 and 1 respectively, so 1568 memristors need to be designed in each row.
  • the constructed Naive Bayes classifier contains a memristor array of 10 rows ⁇ 1568 columns, each two columns represent an attribute, and each row represents a class. It can be understood that, in this embodiment, the rows and columns of the memristor array can be interchanged, and after the interchange, the columns correspond to the classification types, and the rows correspond to the corresponding attribute values.
  • Operation S2 select the jth training sample corresponding to the jth type from the training samples, and calculate the number hj,2i-1 of the pixel value of 0 in the ith pixel in the jth training sample and the pixel value of 1.
  • the sample pictures are divided into 10 types based on the numbers in each sample picture of the training sample.
  • the number of occurrences of pixel value 0 and the number of occurrences of pixel value 1 in each pixel point in the training samples corresponding to each type are calculated.
  • the Naive Bayes classifier by analyzing the Naive Bayes algorithm, it can be known that when the number of all categories of the sample is the same, the Naive Bayes classifier only needs to find the pair of the conditional probability P of each attribute in the category. Number form ln P.
  • the conditional probability P is proportional to the number of occurrences of the input feature n.
  • its conductance value G is inversely proportional to the logarithm of the number of pulses N 1 applied to the memristor, which satisfies the following relationship:
  • the relationship between the conductance value G and the number of pulses N 1 conforms to the trend defined by the above-mentioned relational expression, that is, it can be fitted to the above-mentioned relational expression to a certain extent, but the two are not completely consistent.
  • the pulse electrical characteristic curve of the memristor selected in this embodiment should conform to the above relationship as much as possible. Further, the number of input data attribute values n and the number of pulses N 1 applied to the memristor are linearly mapped, and the following relationship is satisfied:
  • the statistical calculation probability of classification corresponding to the memristor is inversely proportional to the conductance of the memristor, which satisfies the following relationship:
  • G is the conductance of the memristor
  • N1 is the number of pulses applied to the memristor
  • P is the conditional probability value corresponding to the memristor
  • ln P is the statistical calculation probability of classification
  • a is the first fitting parameter
  • b is the second fitting parameter.
  • the mapping of the probability value to the memristor conductance value is implemented in the embodiment of the present invention. Since the naive Bayes classifier mainly classifies the input data into the class with the largest posterior probability, and does not require detailed probability values, the naive Bayes classifier can be completely implemented on the memristor through the above mapping process.
  • h j,2i-1 pulses are applied to the memristor R j,2i-1 in the jth row and the 2i-1 column to modulate the conductance of the memristor R j,2i-1 .
  • the memristor R j,2i in row j, column 2i is applied with h j,2i pulses to modulate the conductance of the memristor R j,2i , and the modulated Naive Bayes classifier is used to identify the type.
  • the fitting curve of the change of conductance with the number of applied pulses during the reset process of the memristor is shown in Figure 3.
  • the position where the pulse should be applied can be determined according to the category and attribute value of the training sample, and the corresponding row and column Applying pulses to adjust the conductance value enables the training of a Naive Bayes classifier.
  • each memristor in the memristor array is initialized to the maximum conductance value of the memristor, and then each memristor is trained after initialization.
  • the crossbar array every two columns represent an attribute, and each row represents a category.
  • each sample image is trained one by one. For each sample image, the row corresponding to the category of the sample image is selected, and a pulse is applied to the memristor in the column corresponding to the attribute value of each attribute of the sample image to conduct conductance. modulation to train on this sample picture.
  • the second modulation scheme is to train each sample image in parallel, count the number of occurrences of each attribute value in each attribute in each sample image, obtain the number of pulses that should be applied to each memristor, and select the corresponding memristor. Conduct conductance modulation by applying pulses corresponding to the number of pulses to complete the training of all sample pictures.
  • the first pixel of the number 1 is black, and the column with the characteristic value of 1 in the first pixel is selected, and the magnitude of the amplitude is applied. is the pulse voltage of VP .
  • V P /2 conductance is applied to all rows that are not number 1, so that in the selected first column, except for the pulse voltage of the second row is V P , and all other unselected rows are the voltage of V P /2.
  • V P /2 By controlling V P /2 to be less than the device's threshold voltage V d , while V P is greater than the threshold voltage V d , it is possible to avoid selecting all rows at the same time during training, and to precisely control the setting of each memristor conductance value. And the corresponding pulse voltage can be applied to all columns at the same time, so as to realize the row-by-row operation during the training process, so that the training of a picture or a class of pictures can be completed in one operation during the training process, which significantly reduces the training process. time complexity.
  • the corresponding first row of memristors corresponds to pixel value 1
  • the corresponding second row of memristors corresponds to pixel value 0.
  • operation S3 Apply h j,2i-1 pulses to memristor R j ,2i at row j, column 2i to modulate the conductance of memristor R j,2i, and at row j, column 2i-1 memristor R j,2i
  • the conductance of the memristor R j ,2i-1 is modulated by applying h j,2i pulses to the resistor R j,2i-1.
  • the corresponding first column of memristors can also be corresponding to pixel value 0, and the corresponding second column of memristors can also be corresponding to pixel value 1.
  • operation S3 in the jth row 2i-1 h j,2i-1 pulses are applied to the memristor R j ,2i-1 of the column to modulate the conductance of the memristor R j,2i-1, the memristor R j in the jth row and the 2i column ,2i is applied with h j,2i pulses to modulate the conductance of the memristor R j,2i .
  • operation S2 when the number of training samples exceeds the range of the number of samples corresponding to the conductance range of the memristor, all the conductances of the memristor can be set to the initial state, and then operation S2 further includes: pairing h j, 2i- 1 and h j,2i are proportionally scaled to reduce each h j,2i-1 and h j,2i to the range of sample numbers corresponding to the conductance range of the memristor.
  • h j,2i-1 ′ pulses are applied to the memristor R j,2i-1 at row j, column 2i-1 to modulate the conductance of R j,2i-1 , at row j
  • the conductance of R j,2i is modulated by applying h j,2i ′ pulses to the memristor R j,2i in column 2i, where h j,2i-1 ′ and h j,2i ′ are respectively h j,2i -1 and h j,2i scaled results.
  • the new samples when training samples are newly added to the training samples, the new samples can be directly trained on the basis of the original array, and it is only necessary to control the number of samples of each category to be the same.
  • the training process of the newly added training samples is the same as the training process of the original training samples, and will not be repeated here.
  • the method when there is redundancy in the number of columns of the memristor array, after operation S3, the method further includes: optimizing the memristor columns corresponding to each pixel in the modulated Naive Bayes classifier through pruning processing . Because the characteristics of the memristor are unstable, the conductance value of the memristor will not reach the preset conductance value, resulting in certain errors. Therefore, when the number of training sample attributes is large enough, the attributes can be filtered through the validation set. Specifically, after the training is completed, delete the corresponding attribute, and then test the accuracy of the naive Bayes classifier through the validation set. If the accuracy decreases, delete the attribute; otherwise, continue to filter the next attribute until It ends when removing any attributes does not reduce the accuracy of the Naive Bayes classifier, and finally the attribute set is the optimal subset after pruning.
  • all memristors can be reset to the initial state, and then the naive Bayes classifier can be reset by using the training samples in other training sets. Train it to implement other classification functions.
  • the step further includes: acquiring the pixel value of each pixel point in the picture to be classified, and when the pixel value of the i-th pixel point is 0, applying a pulse to the memristor in the 2i-1th column, Otherwise, apply a pulse to the memristor in the 2i column; compare the currents at the output terminals of the memristors in each row in the Naive Bayes classifier, and the type of the row corresponding to the minimum current is the type of the image to be classified.
  • a row represents the classification result of the Naive Bayes classifier.
  • FIG. 4 is a block diagram of a design system for a memristor-based naive Bayes classifier according to an embodiment of the present invention.
  • the memristor-based Naive Bayesian classifier design system 400 includes a building module 410 , a selection and calculation module 420 , and a modulation module 430 .
  • the building module 410 performs operation S1 for building a naive Bayesian classifier including M rows ⁇ 2N columns of memristor arrays, where M is the number of types output by the naive Bayesian classifier, and N is the number of pixels in the picture.
  • M is the number of types output by the naive Bayesian classifier
  • N is the number of pixels in the picture.
  • the number of pixels, the pixel value of each pixel is 0 or 1.
  • the modulation module 430 performs operation S3 for applying h j, 2i-1 pulses on the memristor R j , 2i-1 in the j-th row and the 2i-1 column to apply h j, 2i-1 pulses to the memristor R j, 2i-1
  • the conductance of the memristor R j,2i is modulated by applying h j,2i pulses to the memristor R j,2i in the jth row and the 2i column, and the modulated Naive Bayesian classification
  • the classifier is used to identify the type of image to be classified.
  • the memristor-based naive Bayesian classifier design system 400 is used to implement the memristor-based naive Bayesian classifier design method in the embodiments shown in FIG. 1 to FIG. 3 .
  • the design method of the memristor-based naive Bayesian classifier in the embodiments shown in the aforementioned FIG. 1 to FIG. 3 which will not be repeated here.
  • An embodiment of the present invention also provides a memristor-based naive Bayes classifier, which is obtained from the design method of the memristor-based naive Bayes classifier in the embodiments shown in the foregoing FIG. 1 to FIG. 3 .
  • the structure is shown in Figure 2 for example.
  • the design method of the memristor-based naive Bayesian classifier in the embodiments shown in the aforementioned FIG. 1 to FIG. 3 please refer to the design method of the memristor-based naive Bayesian classifier in the embodiments shown in the aforementioned FIG. 1 to FIG. 3 , which will not be repeated here.

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Abstract

一种基于忆阻器的朴素贝叶斯分类器设计方法、系统及分类器，属于信息技术领域，方法包括：构建包含M行×2N列忆阻器阵列的朴素贝叶斯分类器，M为分类类型数量，N为图片中像素点的个数（S1）；计算第j训练样本中第i个像素点中像素值为0的个数h j,2i-1和像素值为1的个数h j,2i，j＝1，2，……，M（S2）；在第j行第2i-1列的忆阻器R j,2i-1上施加h j,2i-1个脉冲以对R j,2i-1的电导进行调制，在第j行第2i列的忆阻器R j,2i上施加h j,2i个脉冲以对R j,2i的电导进行调制，调制后的朴素贝叶斯分类器用于识别待分类图片的类型（S3）。有效克服忆阻器在神经网络应用中电导变化的非对称性和非线性制约，避免非理想阻变行为导致的精度下降，提高朴素贝叶斯分类器的普适性。

Description

基于忆阻器的朴素贝叶斯分类器设计方法、系统及分类器 【技术领域】
本发明属于信息技术领域，更具体地，涉及一种基于忆阻器的朴素贝叶斯分类器设计方法、系统及分类器。
【背景技术】
人工智能的发展和数据大爆炸对计算机性能提出了更高的要求。基于新型存储器的存内计算架构能够实现存储和计算的融合，有望突破传统计算机体系架构，极大提高现有计算机的性能。忆阻器作为最有希望的存算一体器件，其非易失性、读写速度快、易集成、低功耗等特点使其成为下一代存储器的热点，其独特的存内计算架构能够很好地模拟人脑存储和计算一体的机制。神经网络为机器学习中非常重要的学习算法，利用忆阻器实现神经网络时，通常对器件的一致性和对称性有很高要求。此外，神经网络学习算法具有复杂求导计算，其计算过程难以在忆阻器上实现，需要额外的计算资源。实际应用时，忆阻器存在的器件不一致性、器件错误、电导状态数有限、电导分布非线性和非对称性等非理想特性对神经网络系统性能有很大的影响，也制约了其应用进程。
朴素贝叶斯分类器是一种以贝叶斯定理为基础的概率分类器。相比其他神经网络算法，朴素贝叶斯分类器结构简单、性能稳定，对硬件更为友好。朴素贝叶斯分类器主要利用训练数据学习联合概率分布，然后求得后验概率分布。学习联合概率分布需要对数计算，这也制约了朴素贝叶斯分类器在忆阻器上实现。现有基于忆阻器实现朴素贝叶斯算法的方法中，通常通过忆阻器的crossbar阵列，基于欧姆定律实现朴素贝叶斯算法中的乘法过程，并累加得到最后结果，但是只能实现属性不超过三个的识别任务， 极大限制了其普适性。
【发明内容】
针对现有技术的缺陷和改进需求，本发明提供了一种基于忆阻器的朴素贝叶斯分类器设计方法、系统及分类器，其目的在于克服忆阻器在神经网络应用中电导变化的非对称性和非线性制约，避免非理想阻变行为导致的精度下降，提高朴素贝叶斯分类器的普适性。
为实现上述目的，按照本发明的一个方面，提供了一种基于忆阻器的朴素贝叶斯分类器设计方法，包括：S1，构建包含M行×2N列忆阻器阵列的朴素贝叶斯分类器，M为所述朴素贝叶斯分类器输出的类型的数量，N为图片中像素点的个数，每一像素点的像素值为0或1；S2，从训练样本中选取第j个类型对应的第j训练样本，计算所述第j训练样本中第i个像素点中像素值为0的个数h j,2i-1和像素值为1的个数h j,2i，j＝1，2，……，M，i＝1，2，……，N；S3，在第j行第2i-1列的忆阻器R j,2i-1上施加h j,2i-1个脉冲以对所述忆阻器R j,2i-1的电导进行调制，在第j行第2i列的忆阻器R j,2i上施加h j,2i个脉冲以对所述忆阻器R j,2i的电导进行调制，调制后的朴素贝叶斯分类器用于识别待分类图片的类型。
更进一步地，调制过程中，所述忆阻器的电导为：
G＝a×ln(N 1)+b
所述忆阻器对应的分类统计计算概率与所述忆阻器的电导满足：
ln P∝-G
其中，G为所述忆阻器的电导，N 1为所述忆阻器上施加的脉冲的数量，P为所述忆阻器对应的条件概率值，ln P为所述分类统计计算概率，a为第一拟合参数，b为第二拟合参数。
更进一步地，所述S3之后还包括：获取所述待分类图片中各像素点的像素值，当第i个像素点的像素值为0时，在第2i-1列忆阻器上施加脉冲， 否则，在第2i列忆阻器上施加脉冲；比较所述朴素贝叶斯分类器中各行忆阻器输出端的电流，最小电流对应行的类型为所述待分类图片的类型。
更进一步地，所述S1包括：获取所述训练样本中样本类型的数量M，并对所述训练样本进行像素点划分，以将每一训练样本划分为N个像素点；将所述忆阻器阵列的行数设计为M，并将所述忆阻器阵列的列数设计为2N。
更进一步地，当所述训练样本的数量超出所述忆阻器的电导范围对应的样本数量范围时，所述S2还包括：对h j,2i-1和h j,2i进行等比例缩放，以将各h j,2i-1和h j,2i缩小至所述忆阻器的电导范围对应的样本数量范围；所述S3中根据h j,2i-1和h j,2i缩小后的结果分别对所述忆阻器R j,2i-1和所述忆阻器R j,2i的电导进行调制。
更进一步地，当所述训练样本中新增训练样本时，所述S3之后还包括：根据新增训练样本的类型j′、新增训练样本中各像素点i的像素值，在调制后的朴素贝叶斯分类器中第j′行第2i-1列或第j′行第2i列的忆阻器上施加脉冲以进行电导调制。
更进一步地，当所述忆阻器阵列的列数存在冗余时，所述S3之后还包括：通过剪枝处理对调制后朴素贝叶斯分类器中各像素点对应的忆阻器列进行优化。
更进一步地，所述S3中进行调制之前还包括：将所述忆阻器阵列中各忆阻器的电导初始化为所述忆阻器的最大电导值。
按照本发明的另一个方面，提供了一种基于忆阻器的朴素贝叶斯分类器设计系统，包括：构建模块，用于构建包含M行×2N列忆阻器阵列的朴素贝叶斯分类器，M为所述朴素贝叶斯分类器输出的类型的数量，N为图片中像素点的个数，每一像素点的像素值为0或1；选取及计算模块，用于从训练样本中选取第j个类型对应的第j训练样本，计算所述第j训练样本中第i个像素点中像素值为0的个数h j,2i-1和像素值为1的个数h j,2i，j＝1，2，……，M，i＝1，2，……，N；调制模块，用于在第j行第2i-1列的忆阻 器R j,2i-1上施加h j,2i-1个脉冲以对所述忆阻器R j,2i-1的电导进行调制，在第j行第2i列的忆阻器R j,2i上施加h j,2i个脉冲以对所述忆阻器R j,2i的电导进行调制，调制后的朴素贝叶斯分类器用于识别待分类图片的类型。
按照本发明的另一个方面，提供了一种基于忆阻器的朴素贝叶斯分类器，所述朴素贝叶斯分类器由如上所述的基于忆阻器的朴素贝叶斯分类器设计方法得到。
总体而言，通过本发明所构思的以上技术方案，能够取得以下有益效果：
(1)将忆阻器电导的非线性、非对称性与朴素贝叶斯算法相结合，发现了分类统计计算概率与忆阻器电导之间的反向关系，基于此发现，将朴素贝叶斯算法中的概率值计算过程映射到忆阻器电导随着脉冲数量渐变成对数函数的特性中，通过调节忆阻器中输入脉冲的数量来计算相应类别的输出概率值以实现分类，使得朴素贝叶斯分类器的训练和推断均可在忆阻器上实现，有效利用了忆阻器的非线性电导并同时避免了繁琐的计算过程以及消耗额外的计算资源，提高朴素贝叶斯分类器的普适性；该朴素贝叶斯分类器完全在忆阻器阵列上实现真正的学习，无需额外的计算资源；
(2)当训练样本的数量过多超出忆阻器的电导范围对应的样本数量范围时，通过对各属性的属性信息进行缩放处理，使得一个脉冲对应多个样本的信息，从而实现根据所有训练样本对分类器进行训练，保证训练后分类器的分类准确度；
(3)通过剪枝处理，对训练样本的属性进行筛选，以实现对朴素贝叶斯分类器的优化，将其进一步改进为基于忆阻器的选择贝叶斯分类器，可以更好地容忍忆阻器的非理想特性。
【附图说明】
图1为本发明实施例提供的基于忆阻器的朴素贝叶斯分类器设计方法 的流程图；
图2为本发明实施例提供的基于忆阻器的朴素贝叶斯分类器的电路结构示意图；
图3为本发明实施例提供的忆阻器reset过程电导随外加脉冲数量变化的拟合曲线示意图；
图4为本发明实施例提供的基于忆阻器的朴素贝叶斯分类器设计系统的框图。
【具体实施方式】
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。此外，下面所描述的本发明各个实施方式中所涉及到的技术特征只要彼此之间未构成冲突就可以相互组合。
在本发明中，本发明及附图中的术语“第一”、“第二”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
图1为本发明实施例提供的基于忆阻器的朴素贝叶斯分类器设计方法的流程图。参阅图1，结合图2-图3，对本实施例中基于忆阻器的朴素贝叶斯分类器设计方法进行详细说明。参阅图1，方法包括操作S1-操作S3。
操作S1，构建包含M行×2N列忆阻器阵列的朴素贝叶斯分类器，M为朴素贝叶斯分类器输出的类型的数量，N为图片中像素点的个数，每一像素点的像素值为0或1。
本发明实施例中，获取训练样本中样本类型的数量M，并对训练样本中的样本图片进行像素点划分，以将每一训练样本划分为N个像素点。训练样本中的样本图片二值化为黑白图像，由此，每一像素点具有0、1两个属性值，为每一像素点对应设计两列忆阻器。进一步地，将忆阻器阵列的 行数设计为M行，将忆阻器阵列的列数设计为2N，形成M×2N的忆阻器阵列，如图2所示。
以朴素贝叶斯分类器用于识别样本图片中的数字0～9为例，训练样本中样本类型包括0、1、2、3、4、5、6、7、8以及9这十种类型，即样本类型的数量M为10，由此需要设计10行忆阻器。每行忆阻器对应一种样本类型，例如图2中电路结构从上至下各行依次对应样本类型0、1、2、3、4、5、6、7、8和9。
进一步地，例如选用MNIST数据集作为训练样本，将MNIST数据图片二值化为黑白图像，每张图片中包含28×28个像素点，每一像素点表示一个属性，共784个属性。每个像素点具有0、1两种像素值(即属性值)，像素值0表示该像素点为白色，像素值1表示该像素点为黑色。采用两个忆阻器表示一个属性，分别表示该像素值为0和1这两种情况，因此每行需要设计1568个忆阻器。
基于此，构建的朴素贝叶斯分类器包含一10行×1568列的忆阻器阵列，每两列代表一个属性，每一行代表一个类别。可以理解的是，本实施例中，忆阻器阵列的行列可以互换，互换之后，列对应各分类类型，行对应各相应属性值。
操作S2，从训练样本中选取第j个类型对应的第j训练样本，计算第j训练样本中第i个像素点中像素值为0的个数h j,2i-1和像素值为1的个数h j,2i，j＝1，2，……，M，i＝1，2，……，N。
仍以图2中示出的用于识别图片中数字0～9的朴素贝叶斯分类器为例，基于训练样本的各样本图片中的数字将样本图片划分为10个类型。以第一类型样本图片的第一个像素点为例，假设第一类型中样本图片的数量为s个，第一个像素点为黑色的样本图片的数量为s 1，第一个像素点为白色的样本图片的数量为s 2，s 1+s 2＝s，则第一训练样本中第一个像素点中像素值0出现的次数h 1,1为s 2，第一训练样本中第一个像素点中像素值1出现的次 数h 1,2为s 1。以此类推，计算每一类型对应的训练样本中每一像素点中像素值0出现的次数和像素值1出现的次数。
进一步地，本发明实施例中，通过分析朴素贝叶斯算法可知，在样本的所有类别数量相同的情况下，朴素贝叶斯分类器只需求出每个属性在该类别的条件概率P的对数形式ln P。而条件概率P正比于输入特征的出现次数n。忆阻器reset过程中，其电导值G与忆阻器上施加的脉冲的数量N 1的对数成反比，满足以下关系式：
G＝a×ln(N 1)+b
需要说明的是，实际应用中，电导值G与脉冲数量N 1之间的关系符合上述关系式限定的趋势，即在一定程度上可拟合为上述关系式，二者并非完全一致。本实施例中选取的忆阻器的脉冲电学特性曲线应尽可能符合上述关系式。进一步地，将输入数据属性值的次数n与忆阻器上施加的脉冲数量N 1进行线性映射，满足以下关系式：
N 1＝a×n
由此，忆阻器对应的分类统计计算概率与忆阻器的电导成反比，满足以下关系式：
ln P∝ln n∝ln N 1∝-G
其中，G为忆阻器的电导，N 1为忆阻器上施加的脉冲的数量，P为忆阻器对应的条件概率值，ln P为分类统计计算概率，a为第一拟合参数，b为第二拟合参数。
基于此，本发明实施例中实现了概率值到忆阻器电导值的映射。由于朴素贝叶斯分类器主要将输入数据分类到后验概率最大的类，不需要详细的概率值，所以可以通过上述映射过程在忆阻器上完整的实现朴素贝叶斯分类器。
操作S3，在第j行第2i-1列的忆阻器R j,2i-1上施加h j,2i-1个脉冲以对忆阻 器R j,2i-1的电导进行调制，在第j行第2i列的忆阻器R j,2i上施加h j,2i个脉冲以对忆阻器R j,2i的电导进行调制，调制后的朴素贝叶斯分类器用于识别待分类图片的类型。
忆阻器reset过程电导随外加脉冲数量变化的拟合曲线如图3所示，本实施例中，可以根据训练样本的类别和属性值确定脉冲所应该施加的位置，在对应的行和列上施加脉冲调整电导值，实现朴素贝叶斯分类器的训练。
训练之前，将忆阻器阵列中各忆阻器的电导初始化为忆阻器的最大电导值，初始化之后再对各忆阻器进行训练。在crossbar阵列中，每两列代表一个属性，每一行则代表一个类别，本实施例中，操作S2和操作S3中至少存在以下两种忆阻器电导调制方案：
第一种调制方案，逐张训练各样本图片，每训练一张样本图片，选中该样本图片类别对应的行，在该样本图片各属性的属性值对应列的忆阻器上施加一个脉冲进行电导调制，以训练该样本图片。
第二种调制方案，并行训练各样本图片，统计出各类样本图片中各属性中每个属性值出现的次数，得到相应的各忆阻器上应施加的脉冲数量，选中相应的忆阻器施加其对应脉冲数量的脉冲进行电导调制，以完成所有样本图片的训练。
具体地，仍以图2中示出的电路结构为例，训练过程中，数字1的第一个像素点为黑，选中第一个像素点中特征值为1的那一列，施加幅值大小为V P的脉冲电压。同时，为了避免这一列中代表其他数字的行都被选中而受到影响，在所有的不是数字1的行施加V P/2电导，这样在选中的第一列中，除了第二行的脉冲电压为V P，其他所有未被选中的行则是V P/2的电压。通过控制V P/2小于器件的阈值电压V d，而V P大于阈值电压V d，这样就可以避免在训练过程中同时选中所有行，可以精准控制每一个忆阻器电导值的设置。并且可以同时在所有列加相应的脉冲电压，从而在训练过程中实现逐行操作，这样在训练过程中通过一次操作就能完成一张图片、或 一类图片的训练，显著降低了训练过程的时间复杂度。
以图2所示电路结构为例，对于任一像素点，其对应的第一列忆阻器对应像素值1，其对应的第二列忆阻器对应像素值0，此时操作S3中，在第j行第2i列的忆阻器R j,2i上施加h j,2i-1个脉冲以对忆阻器R j,2i的电导进行调制，在第j行第2i-1列的忆阻器R j,2i-1上施加h j,2i个脉冲以对忆阻器R j,2i-1的电导进行调制。可以理解的是，也可以将其对应的第一列忆阻器对应像素值0，其对应的第二列忆阻器对应像素值1，此时操作S3中，在第j行第2i-1列的忆阻器R j,2i-1上施加h j,2i-1个脉冲以对忆阻器R j,2i-1的电导进行调制，在第j行第2i列的忆阻器R j,2i上施加h j,2i个脉冲以对忆阻器R j,2i的电导进行调制。
本发明实施例中，当训练样本的数量超出忆阻器的电导范围对应的样本数量范围时，可以将忆阻器的电导全部set到初始状态，之后操作S2还包括：对h j,2i-1和h j,2i进行等比例缩放，以将各h j,2i-1和h j,2i缩小至忆阻器的电导范围对应的样本数量范围。此时，操作S3中根据h j,2i-1和h j,2i缩小后的结果分别对忆阻器R j,2i-1和忆阻器R j,2i的电导进行调制，j＝1，2，……，M，i＝1，2，……，N。具体地，在第j行第2i-1列的忆阻器R j,2i-1上施加h j,2i-1 ′个脉冲以对R j,2i-1的电导进行调制，在第j行第2i列的忆阻器R j,2i上施加h j,2i ′个脉冲以对R j,2i的电导进行调制，h j,2i-1 ′和h j,2i ′分别为h j,2i-1和h j,2i缩放后的结果。
本发明实施例中，当训练样本中新增训练样本时，可以直接在原有阵列的基础上继续训练新增的样本，只需要控制每一个类别的样本的数量相同即可，此时操作S3之后还包括：根据新增训练样本的类型j′、新增训练样本中各像素点i的像素值，在调制后的朴素贝叶斯分类器中第j′行第2i-1列或第j′行第2i列的忆阻器上施加脉冲以进行电导调制，j′＝1，2，……，M。新增训练样本的训练过程与原有训练样本的训练过程相同，此处不再赘述。
本发明实施例中，当忆阻器阵列的列数存在冗余时，操作S3之后还包括：通过剪枝处理对调制后朴素贝叶斯分类器中各像素点对应的忆阻器列进行优化。因为忆阻器特性不稳定会导致其电导值并没有达到预设的电导值，从而造成一定的误差。所以当训练样本属性数量足够多时，可以通过验证集对属性进行筛选。具体地，在训练完成后，通过删除相应的属性，再通过验证集对朴素贝叶斯分类器的准确度进行测试，若准确度下降，则删除该属性；否则，继续筛选下一个属性，直到删除任何属性都不会降低朴素贝叶斯分类器的准确度时结束，最终该属性集为剪枝后的最优子集。
相应的，也可以通过向空集中不断添加属性，并判断朴素贝叶斯分类器的准确度是否会下降，会下降则不添加该属性，否则添加该属性后继续遍历下一个属性，直到添加任何属性朴素贝叶斯分类器的准确度都会下降时停止。
本实施例中，当训练后的朴素贝叶斯分类器需要重新其他训练集时，可以将各忆阻器全部reset到初始状态，然后利用其他训练集中的训练样本对该朴素贝叶斯分类器进行训练，使其实现其他分类功能。
本发明实施例中，操作S3之后还包括：获取待分类图片中各像素点的像素值，当第i个像素点的像素值为0时，在第2i-1列忆阻器上施加脉冲，否则，在第2i列忆阻器上施加脉冲；比较朴素贝叶斯分类器中各行忆阻器输出端的电流，最小电流对应行的类型为待分类图片的类型。预测过程中则只需要将待分类图片输入到每一列上，然后同时选中所有行，即在每一行都施加电压0，由此便可并行计算出各个类别的概率值，此时输出电流最小的一行即代表朴素贝叶斯分类器的分类结果。
图4为本发明实施例提供的基于忆阻器的朴素贝叶斯分类器设计系统的框图。参阅图4，该基于忆阻器的朴素贝叶斯分类器设计系统400包括构建模块410、选取及计算模块420以及调制模块430。
构建模块410例如执行操作S1，用于构建包含M行×2N列忆阻器阵 列的朴素贝叶斯分类器，M为朴素贝叶斯分类器输出的类型的数量，N为图片中像素点的个数，每一像素点的像素值为0或1。
选取及计算模块420例如执行操作S2，用于从训练样本中选取第j个类型对应的第j训练样本，计算第j训练样本中第i个像素点中像素值为0的个数h j,2i-1和像素值为1的个数h j,2i，j＝1，2，……，M；i＝1，2，……，N。
调制模块430例如执行操作S3，用于在第j行第2i-1列的忆阻器R j,2i-1上施加h j,2i-1个脉冲以对忆阻器R j,2i-1的电导进行调制，在第j行第2i列的忆阻器R j,2i上施加h j,2i个脉冲以对忆阻器R j,2i的电导进行调制，调制后的朴素贝叶斯分类器用于识别待分类图片的类型。
基于忆阻器的朴素贝叶斯分类器设计系统400用于执行上述图1-图3所示实施例中的基于忆阻器的朴素贝叶斯分类器设计方法。本实施例未尽之细节，请参阅前述图1-图3所示实施例中的基于忆阻器的朴素贝叶斯分类器设计方法，此处不再赘述。
本发明实施例还提供了一种基于忆阻器的朴素贝叶斯分类器，由前述图1-图3所示实施例中的基于忆阻器的朴素贝叶斯分类器设计方法得到，其结构例如图2所示。本实施例未尽之细节，请参阅前述图1-图3所示实施例中的基于忆阻器的朴素贝叶斯分类器设计方法，此处不再赘述。
本领域的技术人员容易理解，以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种基于忆阻器的朴素贝叶斯分类器设计方法，其特征在于，包括：
    S1，构建包含M行×2N列忆阻器阵列的朴素贝叶斯分类器，M为所述朴素贝叶斯分类器输出的类型的数量，N为图片中像素点的个数，每一像素点的像素值为0或1；
    S2，从训练样本中选取第j个类型对应的第j训练样本，计算所述第j训练样本中第i个像素点中像素值为0的个数h j,2i-1和像素值为1的个数h j,2i，j＝1，2，……，M，i＝1，2，……，N；
    S3，在第j行第2i-1列的忆阻器R j,2i-1上施加h j,2i-1个脉冲以对所述忆阻器R j,2i-1的电导进行调制，在第j行第2i列的忆阻器R j,2i上施加h j,2i个脉冲以对所述忆阻器R j,2i的电导进行调制，调制后的朴素贝叶斯分类器用于识别待分类图片的类型。
  2. 如权利要求1所述的基于忆阻器的朴素贝叶斯分类器设计方法，其特征在于，调制过程中，所述忆阻器的电导为：
    G＝a×ln(N 1)+b
    所述忆阻器对应的分类统计计算概率与所述忆阻器的电导满足：
    lnP∝-G
    其中，G为所述忆阻器的电导，N 1为所述忆阻器上施加的脉冲的数量，P为所述忆阻器对应的条件概率值，lnP为所述分类统计计算概率，a为第一拟合参数，b为第二拟合参数。
  3. 如权利要求1所述的基于忆阻器的朴素贝叶斯分类器设计方法，其特征在于，所述S3之后还包括：
    获取所述待分类图片中各像素点的像素值，当第i个像素点的像素值为0时，在第2i-1列忆阻器上施加脉冲，否则，在第2i列忆阻器上施加脉冲；
    比较所述朴素贝叶斯分类器中各行忆阻器输出端的电流，最小电流对 应行的类型为所述待分类图片的类型。
  4. 如权利要求1所述的基于忆阻器的朴素贝叶斯分类器设计方法，其特征在于，所述S1包括：
    获取所述训练样本中样本类型的数量M，并对所述训练样本进行像素点划分，以将每一训练样本划分为N个像素点；
    将所述忆阻器阵列的行数设计为M，并将所述忆阻器阵列的列数设计为2N。
  5. 如权利要求1所述的基于忆阻器的朴素贝叶斯分类器设计方法，其特征在于，当所述训练样本的数量超出所述忆阻器的电导范围对应的样本数量范围时，所述S2还包括：对h j,2i-1和h j,2i进行等比例缩放，以将各h j,2i-1和h j,2i缩小至所述忆阻器的电导范围对应的样本数量范围；
    所述S3中根据h j,2i-1和h j,2i缩小后的结果分别对所述忆阻器R j,2i-1和所述忆阻器R j,2i的电导进行调制。
  6. 如权利要求1所述的基于忆阻器的朴素贝叶斯分类器设计方法，其特征在于，当所述训练样本中新增训练样本时，所述S3之后还包括：
    根据新增训练样本的类型j′、新增训练样本中各像素点i的像素值，在调制后的朴素贝叶斯分类器中第j′行第2i-1列或第j′行第2i列的忆阻器上施加脉冲以进行电导调制。
  7. 如权利要求1所述的基于忆阻器的朴素贝叶斯分类器设计方法，其特征在于，当所述忆阻器阵列的列数存在冗余时，所述S3之后还包括：通过剪枝处理对调制后朴素贝叶斯分类器中各像素点对应的忆阻器列进行优化。
  8. 如权利要求1-7任一项所述的基于忆阻器的朴素贝叶斯分类器设计方法，其特征在于，所述S3中进行调制之前还包括：将所述忆阻器阵列中各忆阻器的电导初始化为所述忆阻器的最大电导值。
  9. 一种基于忆阻器的朴素贝叶斯分类器设计系统，其特征在于，包括：
    构建模块，用于构建包含M行×2N列忆阻器阵列的朴素贝叶斯分类器，M为所述朴素贝叶斯分类器输出的类型的数量，N为图片中像素点的个数，每一像素点的像素值为0或1；
    选取及计算模块，用于从训练样本中选取第j个类型对应的第j训练样本，计算所述第j训练样本中第i个像素点中像素值为0的个数h j,2i-1和像素值为1的个数h j,2i，j＝1，2，……，M，i＝1，2，……，N；
    调制模块，用于在第j行第2i-1列的忆阻器R j,2i-1上施加h j,2i-1个脉冲以对所述忆阻器R j,2i-1的电导进行调制，在第j行第2i列的忆阻器R j,2i上施加h j,2i个脉冲以对所述忆阻器R j,2i的电导进行调制，调制后的朴素贝叶斯分类器用于识别待分类图片的类型。
  10. 一种基于忆阻器的朴素贝叶斯分类器，其特征在于，所述朴素贝叶斯分类器由如权利要求1-8任一项所述的基于忆阻器的朴素贝叶斯分类器设计方法得到。
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