WO2022214249A1

WO2022214249A1 - Method for producing a semiconductor component, and semiconductor component

Info

Publication number: WO2022214249A1
Application number: PCT/EP2022/055445
Authority: WO
Inventors: Martin Hetzl; Christian Lauer
Original assignee: Ams-Osram International Gmbh
Priority date: 2021-04-08
Filing date: 2022-03-03
Publication date: 2022-10-13
Also published as: DE102021108785A1

Abstract

The invention relates to a method for producing a semiconductor component (20), having the steps of forming (S110) a semiconductor layer stack (110) which has an Al_xGa_1-xAs-containing layer (111), an Al_zGa_1-zAs-containing layer (113), and an Al_1-y-kIn_yGa_kAs layer (112) arranged between the Al_xGa_1-xAs-containing layer (111) and the Al_zGa_1-zAs-containing layer (113), where 0≤x<1, 0≤z<1, 0.02<y<0.12, and 0≤k<0.05; and carrying out (S120) an oxidation process, whereby the Al_1-y-kIn_yGa_kAs layer (112) is at least partly oxidized, whereby an insulating region is produced.

Description

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND

SEMICONDUCTOR DEVICE

For certain semiconductor devices, an insulating layer within an epitaxially grown layer stack is desirable or necessary. Typically, such an insulating layer can be fabricated by growing a layer stack containing an AlGaAs layer with a high Al content. An oxidation step then takes place, in which the AlGaAs layer with a high Al content is oxidized from the side. The oxidized AlGaAs layer, for example an AlGaAsO layer, is insulating and as a result represents a buried insulating layer. The problem is that the volume changes as a result of the oxidation. As a result, stresses are generated in the layer stack, which in the worst case can lead to detachment of layers.

For this reason, improved methods are sought with which one can produce semiconductor devices with a buried insulating layer or a buried insulating layer region.

The object of the present invention is to provide an improved method for producing a semiconductor component and an improved semiconductor component.

According to embodiments, the object is solved by the subject matter of the independent patent claims. Advantageous further developments are defined in the dependent patent claims. A method for manufacturing a semiconductor device includes forming a semiconductor layer stack comprising an Al _x Gai- _x As-containing layer, an Al _z Gai- _z As-containing layer and a layer between the Al _x Gai- _x As-containing layer and the Al _z Gai _z As- containing layer arranged Ali _yk In _y Ga _k As layer, with 0<x<l, 0<z<l, 0.02<y<0.12, 0<k<0 .05 and performing an oxidation process whereby the Ali- _yk In _y Ga _k As layer is at least partially oxidized, thereby creating an insulating region. According to embodiments, the Ga content of the _Aliyk In _y Ga _k As layer can also be lower. For example, k may be less than or equal to 0.04 or 0.02.

According to further embodiments, a method for producing a semiconductor device comprises the formation of a semiconductor layer stack comprising an Al _x Gai- _x As-containing layer, a first Al _y Gai- _y As layer, an Al _z Gai- _z As-containing layer and a to the first Al _y Gai- _y As layer adjoining first in dium-containing compound semiconductor layer layer, where at the first Al _y Gai- _y As layer between the Al _x Gai- _x As-containing layer and the Al _z Gai- _z As-containing layer is arranged with 0<x<l, 0<y<l, y>x, y>z, and y>0.95, and performing an oxidation process, whereby the first Al _y Gai- _y As -Layer is at least partially oxidized, creating an insulating Be rich is generated. According to embodiments, the stoichiometric proportion of Al in the Al _y Gai- _y As layer can also be greater than 0.98.

For example, the semiconductor layer stack can also have a second indium-containing compound semiconductor layer which adjoins the first Al _y Gai- _y As layer and is arranged on a side of the first Al _y Gai- _y As layer which faces away from the first indium-containing compound semiconductor layer. According to embodiments, a material of the first and/or second indium-containing compound semiconductor layer can be Al _X' In _y' Gai _-X'-y' As, with 0<x'<0.7 and 0.02<y'<0.26.

A layer thickness of the first Al _y Gai- _y As layer can be less than 15 nm.

According to embodiments, a layer thickness of the indium-containing compound semiconductor layer can be less than 10 nm.

For example, a layer stack with a sequence of a plurality of Al _y Gai- _y As layers with indium-containing compound semiconductor layers arranged between the individual Al _y Gai- _y As layers can be formed. In this way, it is possible to increase the total layer thickness of the oxide layer without the stress in the layer stack becoming too great.

For example, a number of Al _y Gai- _y As layers can be less than 5.

According to embodiments, the semiconductor layer stack may be at least two Ali- _yk In _y Ga _k As layers or Al _y Gai- _y As layers and a semi-insulating semiconductor layer between the two Ali- _yk In _y Ga _k As layers or Al _y Gai- _y Have As layers. In this way, the insulating effect of the semiconductor layer stack can be further improved.

According to further embodiments, the semiconductor layer stack can have at least two Ali _yk In _y Ga _k As layers or Al _y _ Gai _y As layers and a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type and a third semiconductor layer of the first Conductivity type between the two Ali _yk In _y Ga _k As layers or Al _y Gai _y As layers are formed. On the- In this way, a pnp or npn structure can be formed between the insulating layers. As a result, the insulating effect of the semiconductor stacked layer can be further improved.

According to further embodiments, a method for producing a semiconductor device comprises the formation of a semiconductor layer stack comprising an Al _x Gai- _x As-containing layer, a first Al _y Gai- _y AsP layer, an Al _z Gai- _z As-containing layer and a first indium-containing compound semiconductor layer adjoining the first Al _y Gai- _y AsP layer, the first Al _y Gai- _y AsP layer between the Al _x Gai- _x As-containing layer and the Al _z Gai- _z As-containing layer is arranged, with 0<x<l, 0<y<l, y>x, y>z, and y>0.95, and performing an oxidation process, whereby the first Al _y Gai- _y AsP layer at least partially oxidized, creating an insulating region.

For example, the semiconductor layer stack can have a second indium-containing compound semiconductor layer which adjoins the first Al _y Gai- _y AsP layer and is arranged on a side of the first Al _y Gai- _y AsP layer which is remote from the first indium-containing compound semiconductor layer.

A material of the first and/or second indium-containing compound semiconductor layer can be Al _X' In _y' Gai _-X'-y As, with 0<x'<0.7 and 0.02<y'<0.26.

A layer thickness of the first Al _y Gai- _y AsP layer can be less than 10 nm. A layer thickness of the indium-containing compound semiconductor layer can be less than 10 nm.

For example, a layer stack with a sequence of several Al _y Gai- _y AsP layers with between the individual NEN Al _y Gai- _y AsP layers arranged indium-containing compound semiconductor layers are formed. In this way, it is possible to increase the overall layer thickness of the oxide layer without the layer stack being stressed too much.

A semiconductor component has a semiconductor layer stack which contains an Al _x Gai- _x As-containing layer, an Al _z Gai- _z As-containing layer and regions of a layer between the Al _x Gai- _x As-containing layer and the Al _z Gai- _z As-containing layer arranged _Aliyk In _y Ga _k OAs layer, with 0<x<l, 0<z<l, 0.02<y<0.12, k<0.05. The portions of the _Aliyk In _y Ga _k OAs layer constitute an insulating portion. The Ali _yk In _y Ga _k OAs layer results from oxidation of the Ali _yk In _y Ga _k As layer. The _Aliyk _Iny Ga _k OAs layer may have amorphous components with locally varying composition ratio.

A semiconductor component according to further embodiments has a semiconductor layer stack, which contains an Al _x Gai- _x As- layer, regions of a first Al _y Gai- _y OAs layer, an Al _z Gai- _z As-containing layer and one to the regions of first indium-containing compound semiconductor layer adjoining the first Al _y Gai- _y OAs layer, the regions of the first Al _y _ Gai- _y OAs layer between the Al _x Gai- _x As-containing layer and the Al _z Gai- _z As- containing layer are arranged, with 0<x<l, 0<y<l, y>x, y>z, and y>0.95. The areas of the first Al _y Gai- _y OAs layer represent an isolating area.

A semiconductor component has a semiconductor layer stack that contains an Al _x Gai- _x As-containing layer, regions of a first Al _y Gai- _y O layer, an Al _z Gai- _z As-containing layer and a layer that is attached to the regions of the first Al _y Gai- _y O-layer adjoining first compound semiconductor layer containing dium, wherein the areas of the first Al _y Gai- _y O-layer between the Al _x Gai- _x As- layer and the layer containing Al _z Gai- _z As are arranged, with 0<x<l, 0<y<l, y>x, y>z, and y>0.95. The areas of the first Al _y Gai- _y O layer represent an isolating area.

A semiconductor component has a semiconductor layer stack that contains an Al _x Gai- _x As-containing layer, regions of a first Al _y Gai- _y OAsP layer, an Al _z Gai- _z As-containing layer and a layer that is attached to the regions of the first Al _y Gai- _y OAsP layer has adjoining first te indium-containing compound semiconductor layer, the regions of the first Al _y Gai- _y OAsP layer being arranged between the Al _x Gai- _x As-containing layer and the Al _z Gai- _z As-containing layer are, with 0<x<l, 0<y<l, y>x, y>z, and y>0.95. The areas of the first Al _y Gai- _y OAsP layer represent an isolating area.

For example, the semiconductor component can be designed as a surface emitting semiconductor laser (VCSEL), the regions of the Ali _yk In _y Ga _k OAs layer, the first Al _y Gai _y OAs layer, the first Al _y Gai _y O layer or the first Al _y _ Gai- _y OAsP layer form an aperture for current conduction in the semiconductor laser.

According to further embodiments, the regions of the Ali- _yk In _y Ga _k OAs layer, the first Al _y Gai- _y OAs layer, the first Al _y Gai- _y O layer or the first Al _y Gai- _y OAsP Layer be appro net to electrically and / or optically isolate two component regions of the semiconductor component from each other. For example, semiconductor components insulated from one another can be arranged in the two component regions of the semiconductor component.

According to further embodiments, the semiconductor component can be designed as an edge-emitting semiconductor laser with a plurality of laser elements arranged one above the other Areas of the Ali- _yk In _y Ga _k OAs layer, the first Al _y Gai- _y OAs layer, the first Al _y Gai- _y O layer or the first Al _y _ Gai- _y OAsP layer have an aperture for current conduction form lasers in the semiconductor.

The accompanying drawings serve to understand exemplary embodiments from the invention. The drawings illustrate exemplary embodiments and, together with the description, serve to explain them. Further exemplary embodiments and numerous of the intended advantages result directly from the following detailed description. The elements and structures shown in the drawings are not necessarily drawn to scale with respect to one another. The same reference numbers refer to the same or corresponding elements and structures.

FIG. 1A shows a schematic cross-sectional view of a workpiece when carrying out a method according to embodiments.

FIG. 1B shows a cross-sectional view of another workpiece when a method according to embodiments is carried out.

2A shows a cross-sectional view of a workpiece after further method steps have been carried out.

2B shows a cross-sectional view of a workpiece according to further embodiments.

2C summarizes a method according to embodiments.

3A shows a workpiece when carrying out a method according to embodiments. 3B shows a cross-sectional view of a semiconductor device according to embodiments.

3C summarizes a method according to further embodiments.

3D summarizes a method according to further embodiments.

4A shows a cross-sectional view of a workpiece when performing a method according to embodiments.

4B shows a cross-sectional view of a portion of a semiconductor device according to embodiments.

5A shows a cross-sectional view of a portion of a semiconductor device according to embodiments.

5B shows a cross-sectional view of a portion of a semiconductor device according to embodiments.

5C illustrates another semiconductor device according to embodiments.

In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which specific example embodiments are shown by way of illustration. In this context, directional terminology such as "top", "bottom", "front", "back", "over", "on", "in front", "back", "front", "back", etc. is used the orientation of the figures just described. Since the components of the exemplary embodiments can be positioned in different orientations, the directional terminology is used for explanation only and is in no way limiting.

The description of the exemplary embodiments is not restrictive, since other exemplary embodiments exist and structural or logical changes can be made without departing from the scope defined by the claims. In particular, elements of exemplary embodiments described below can be combined with elements of other exemplary embodiments described, unless the context dictates otherwise.

The terms "wafer" or "semiconductor substrate" used in the following description may include any semiconductor-based structure that has a semiconductor surface. Wafer and structure are understood to include doped and undoped semiconductors, epitaxial semiconductor layers optionally supported by a base substrate, and other semiconductor structures. For example, a layer of a first semiconductor material may be grown on a growth substrate of a second semiconductor material, such as a GaAs substrate, a GaN substrate, or a Si substrate, or of an insulating material, such as a sapphire substrate.

Depending on the intended use, the semiconductor can be based on a direct or an indirect semiconductor material. Examples of semiconductor materials that are particularly suitable for generating electromagnetic radiation include, in particular, nitride semiconductor compounds that can be used, for example, to generate ultraviolet, blue or longer-wave light, such as GaN, InGaN, AlN, AlGaN, AlGaInN, AlGaInBN, phosphide semiconductor compounds , through the example wise green or longer-wave light can be generated, such as GaAsP, AlGaInP, GaP, AlGaP, and other semiconductor materials such as GaAs, AlGaAs, InGaAs, AlInGaAs, SiC, ZnSe, ZnO, Ga _2Ü3 , diamond, hexagonal BN and combinations of the materials mentioned. The stoichiometric ratio of the compound semiconductor materials can vary. Other examples of semiconductor materials may include silicon, silicon-germanium, and germanium. In the context of the present description, the term "semiconductor" also includes organic semiconductor materials.

The term "substrate" generally includes insulating, conductive, or semiconductor substrates.

The term "vertical" as used in this specification is intended to describe an orientation that is substantially perpendicular to the first surface of a substrate or semiconductor body. The vertical direction can correspond to a growth direction when layers are grown, for example.

The terms "lateral" and "horizontal" as used in this specification are intended to describe an orientation or alignment that is substantially parallel to a first surface of a substrate or semiconductor body. This can be the surface of a wafer or a chip (die), for example.

The horizontal direction can, for example, lie in a plane perpendicular to a growth direction when layers are grown.

The terms “have”, “contain”, “include”, “have” and the like are used here open-ended terms that indicate the presence of said elements or features, but do not exclude the presence of other elements or features. The indefinite articles and the definite articles include both the plural and the singular, unless the context clearly indicates otherwise.

In the context of this description, the term "electrically connected" means a low-impedance ^electrical connection between the connected elements. The electrically connected elements do not necessarily have to be connected directly to one another. Further elements can be arranged ^between electrically connected elements.

The term "electrically connected" also includes tunnel contacts between the connected elements.

1A shows a cross-sectional view of a workpiece 15 when performing a method according to embodiments. A method of fabricating a semiconductor device includes forming a semiconductor layer stack 110 that includes an Al _x Gai- _x As-containing layer 111, an Al _z Gai- _z As-containing layer 113, and a layer 113 between the Al _x Gai- _x As-containing layer and the Al _z Gai- _z As-containing layer arranged Ali- _yk In _y Ga _k As layer 112. For example, the _Aliyk In _y Ga _k As layer 112 can have a layer thickness of more than 8 nm. The layer thickness of the _Aliyk In _y Ga _k As layer 112 can be less than 15 nm. Since the Al content of the Ali _yk In _y Ga _k As layer 112 is greater than that of the Al _x Gai _x As-containing layer 111 and the Al _z Gai_ _z As-containing layer 113. For example, a stoichiometric shear Al content of the _Aliyk In _y Ga _k As layer 112 must be greater than 0.9. For example, the stoichiometric fraction of In in the _{AliykInyGakAs} _layer ₁₁₂ may be between 0.02 and 0.12. The Ga content of the Ali- _yk In _y Ga _k As layer 112 can be low. For example, the stoichiometric proportion of _Ga of the _{AliykInyGakAs} _layer 112 can be less than 0.02. For example, the _Aliyk In _y Ga _k As layer 112 can also be an AlInAs layer and contain no Ga. The Al _x Ga _x As-containing layer 111 can be part of a first resonator mirror 125, for example. For example, the workpiece 15 can be a workpiece for producing a vertically emitting semiconductor laser (VCSEL, “Vertical Cavity Surface Emitting Laser”).

The term _AlxGai -xAs-containing layer with 0< _x <1, which is used within the scope of the present application, designates a compound semiconductor layer that can contain GaAs and, for example, Al or other elements. Examples include AlGaAs, GaAs, InGaAs, and others.

The first cavity mirror 125 may include alternately stacked first layers of a first composition and second layers of a second composition. For example, when using dielectric layers, they can alternately have a high refractive index (n>1.7) and a low refractive index (n<1.7) and be designed as a Bragg reflector. According to further embodiments, the first resonator mirror 125 can also have semiconductor layers. In this case, semiconductor layers with a high refractive index (n>3.3) and semiconductor layers with a low refractive index (n<3.3) can be arranged alternately. For example, the layer thickness can be 1/4 or a multiple of 1/4, where 1 indicates the wavelength of the light to be reflected. The first resonator mirror 125 can have, for example, 2 to 50 different layers. A typical layer thickness of the individual layers can be about 30 to 90 nm, for example about 50 nm. The layer stack can also contain one or two or more layers that are thicker than about 180 nm, for example thicker than 200 nm. For example, the first resonator mirror 125 can have a total reflectivity of 99.8% or more for the laser radiation.

The Al _x Ga _x As-containing layer 111 and further layers of the first resonator mirror 125 can be doped, for example, with a first conductivity type, for example n-conducting. A first semiconductor layer 116 of a first conductivity type, for example n-type, can be arranged above the first resonator mirror 125 . Furthermore, the semiconductor layer stack 110 can have a second semiconductor layer 120 of a second conductivity type, for example p-conducting. An active zone 115 can be arranged between the first semiconductor layer 116 and the second semiconductor layer 120 .

The active zone can have, for example, a pn junction, a double heterostructure, a single quantum well structure (SQW, single quantum well) or a multiple quantum well structure (MQW, multi quantum well) for generating radiation.

The term "quantum well structure" has no meaning here with regard to the dimensionality of the quantization. It thus includes, among other things, quantum wells, quantum wires and quantum dots as well as any combination of these layers.

The Ali _yk in _y Ga _k As layer 112 may be arranged within the first semiconductor layer 116 or the second semiconductor layer 120, for example. The _Aliyk In _y Ga _k As layer 112 can also be arranged such that it is adjacent to the active region 115 .

The semiconductor layer stack 110 also has a second resonator mirror 130 . The second resonator mirror 130 can in turn be designed as a Bragg mirror and, for example have a lower reflectivity for the electromagnetic ^radiation generated than the first resonator mirror 125. Accordingly, the second resonator mirror 130 can act as a decoupling mirror. The Al _z Gai_ _z As-containing layer 113 can be part of the second resonator mirror 130, for example. Of course, the Al _x Gai- _x As-containing layer 111 and the Al _z Gai_ _z As-containing layer 113 can be arranged at any other location within the layer stack 110 . For example ^, they can be part of the first and/or the second semiconductor layer 116, 120. An optical resonator 105 is formed between the first resonator mirror 125 and the second resonator mirror 130 , the direction of which runs perpendicular to a first main surface of the semiconductor layer stack 110 .

1B shows a workpiece 15 according to further embodiments. For example, the workpiece shown in FIG. 1B may be a workpiece for forming a semiconductor device in which a first device region 140 and a second device region 145 are stacked and separated and insulated from each other by an insulating layer. The Al _x Ga _x As layer 111 can be arranged in the first component area 140 provided. The layer 113 containing Al _z ^Gai_ _z As can be arranged within the provided component region 145 . Between the Al _x Gai- _x As-containing layer 111 and the Al _z Gai- _z As-containing layer 113, the Ali- _yk In _y Ga _k As layer 112 is arranged as described above.

For further processing, the workpiece is subjected to a thermal oxidation process. For example, the thermal oxidation process can be carried out at temperatures in a range of 300°C or 450/500°C. For example, the thermal oxidation process can be carried out in water ^vapor or in an oxygen atmosphere. be led. The oxidation progresses in the lateral direction from the edge of the respective workpiece towards the center.

As a result, using the workpiece shown in Fig. 1A, for example, the surface emitting semiconductor laser shown in Fig. 2A can be manufactured. As can be seen, the outer portion of the former Ali- _yk In _y Ga _k As layer 112 is now oxidized and presents an Ali _-yk In _y Ga _k OAs layer 118. The central portion of the Ali _-yk In _y Ga _k As layer 112 remains unoxidized and thus conductive. The _oxidized portion of the _{Ali_ykInyGakAs} _layer ₁₁₂ , ie, the _{Ali_ykInyGakOAs} _layer ₁₁₈ , is insulating. In this way, an aperture 106 of the surface-emitting semiconductor laser 10 is provided, which leads to a corresponding deflection and concentration of an impressed current onto the middle region of the surface-emitting semiconductor laser. Fig. 2A also shows a first contact element 132 for making electrical contact with the first semiconductor layer 116 and a second contact element 135 for making electrical contact with the second semiconductor layer 120.

If the workpiece 15 shown in FIG. 1B is subjected to a thermal oxidation process, for example also in steam, the result is the semiconductor component shown in FIG. 2B. A first component region 140 and a second component region 145 are arranged one above the other and are insulated from one another by an insulating _{Ali_yk} _Iny Ga _k OAs layer 118 . For example, semiconductor components 143 can be arranged in the first and second component regions 140, 145, respectively. Examples of semiconductor components 143 include, for example, transistors, for example HEMTs (“High Electron Mobility Transistor”), diodes, for example light-emitting diodes or light-receiving diodes, capacitors sators and others. The semiconductor components 143 may be suitable for high voltage applications, for example. The semiconductor components 143 can be manufactured before or after the thermal oxidation process is performed.

By oxidizing an indium-containing Ali- _yk Iri _y Ga _k As layer 112 to an insulating material as has been described, the oxidized Ali- _yk In _y Ga _k OAs layer 118 has less strain than the conventional one AlGaOAs layer. If, for example, an AlGaAs layer that does not contain In is oxidized, a volume change, for example a volume reduction, of the oxidized layer can occur. Furthermore, it is possible that the oxidized AlGaAs layer no longer contains a periodic crystal structure. Together with the strain resulting from the reduction in volume, peeling off or delamination of the oxidized AlGaOAs layer can thus take place.

For example, the _Aliyk In _y Ga _k As layer 112 is compressively stressed prior to performing the oxidation process.

The set relative compressive stress can be 0.3 to 1%, for example. In this way, a tensile stress that occurs due to volume shrinkage as a result of oxidation is reduced. As a result, the mechanical stability of the oxidized layer and the adjacent layers is improved. As a result, for example, the film thickness of the Ali_ _yk In _y Ga _k OAs insulating layer 118 and also the Ali _y - _k In _y Ga _k As layer 112 can be increased. For example, a maximum total oxide thickness can be 20 nm. Furthermore, it is possible, please include, after the oxidation process has been carried out, to carry out high-temperature steps or other steps which can represent a mechanical stress for the semiconductor layer stack, such as the application of new materials, for example. This allows the manufacturing process to be optimized the. As a further result, the performance of the semiconductor devices is improved.

2C summarizes a method according to embodiments.

A method for manufacturing a semiconductor device includes forming (S110) a semiconductor layer stack that includes an Al _x Gai- _x As-containing layer, an Al _z Gai- _z As-containing layer, and a layer between the Al _x Gai- _x As- containing layer and the Al _z _ Gai _z As-containing layer arranged Ali _yk In _y Ga _k As layer has, with 0<x<l, 0<z<l, 0.02<y<0.12 , 0<k<0.02 and performing (S210) an oxidation process whereby the Ali- _yk In _y Ga _k As layer is at least partially oxidized, thereby creating an insulating region.

According to embodiments which have been described with reference to FIGS. 1A to 2C, an indium-containing compound semiconductor layer 112, which has, for example, the composition Ali- _yk in _y Ga _k As and has a compressive stress after application, instead of the usual AlGaAs -High Al content layer used.

According to embodiments described below, it is also possible to use the conventionally used AlGaAs layer to form an insulating region, with an indium-containing compound semiconductor layer 117 being provided as a spacer layer adjacent to this layer. The indium-containing compound semiconductor layer 117 can be compressively strained, for example. As shown in FIG. 3A, the semiconductor layer stack includes an Al _y Gai- _y As layer 114 sandwiched between the Al _x Gai- _x As containing layer 111 and the Al _z Gai- _z As containing layer 113 . The Al content of the Al _y Gai- _y As layer 114 is greater than the Al content of the AlGaAs- containing layers 111 and 113. For example, the stoch- iometric ratio of Al must be greater than 0.7. The indium-containing compound semiconductor layer 117 can have the composition Al _X' In _y' Gai _-X'-y As, for example, with 0<x'<0.7 and 0.02<y'<0.26.

For example, the AlGaAs layer 114 may be compressively stressed prior to oxidation. For this reason, it can be advantageous if the Al _y Gai- _y As layer 114 is less than 15 nm thick. For example, a layer thickness of the indium-containing compound semiconductor layer 117 can be less than 10 nm. For example, the indium-containing compound semiconductor layer 117 may be adjacent to one side of the Al _y Gai- _y As layer 114 . According to further embodiments, the indium-containing compound semiconductor layer 117 can also be arranged on both sides of the Al _y _ Gai- _y As layer 114 . The indium-containing compound semiconductor layer 117 can directly adjoin the Al _y Gai- _y As layer 114 . Additional layers of the workpiece 15 are as described with reference to Figure 1A.

Fig. 3B shows a cross-sectional view of a surface emitting semiconductor laser after performing the oxidation process. As a result, an AlGaOAs layer 122 is formed in the edge area. The non-oxidized Al _y Gai- _y As layer 114 remains in the middle region of the surface emitting semiconductor laser 10 and thus forms the aperture of the surface emitting semiconductor laser 10 . The other components are as described with reference to Figure 2A.

3C summarizes a method according to embodiments. A method for manufacturing a semiconductor component includes the formation (S210) of a semiconductor layer stack that includes an Al _x Gai- _x As-containing layer, a first Al _y Gai- _y As layer, an Al _z Gai- _z As-containing layer, and a first indium-containing compound semiconductor adjoining the first Al _y Gai- _y As layer conductor layer layer, wherein the first Al _y Gai- _y As layer is arranged between the Al _x Gai- _x As-containing layer and the Al _z Gai- _z As-containing layer, with 0<x<1, 0<y<l,y>x,y>z, and y>0.7, and performing (S220) an oxidation process whereby the first Al _y Gai- _y As layer is at least partially oxidized, thereby creating an insulating region .

According to further embodiments, instead of the Al _y Gai- _y As layer 114, a phosphorus-containing Al _y Gai- _y AsP layer 119 can also be arranged in the workpiece shown in FIG. 3A. For example, the Al _y ^Gai- _y AsP layer 119 can have the composition Al 0.98 Ga 0.02 As _IX P _X , where 0.1< _x <0.6. The ^layer thickness can be less than 10 nm. The stoichiometric proportion of P can be less than 0.6, for example. The stoichiometric proportion of P can be greater than 0.1. These ^proportions apply regardless of the stoichiometric proportion of Al and Ga.

For example, the phosphorus-containing Al _y Gai- _y AsP layer 119 may be under tension before oxidation. For example, a low phosphorus content of less than, for example, 5% in the stoichiometric ratio can lead to tensile stress in the AlGaAsP layers. In this way, the phosphorus-containing Al _y ^Gai- _y AsP layer 119 can compensate for the compressive stress of the adjoining indium-containing compound semiconductor layers 117 . As a result, the overall stress of the semiconductor ^layer stack is reduced or even compensated for before the oxidation process is carried out.

In this case, when an oxidation process is carried out, an AlGaAsPO layer 117 is formed as the oxidized layer. The Al _y Gai- _y AsP layer 119 remains in the central region of the surface-emitting semiconductor laser in FIG. 3B. For example, in the case of a wet thermal oxidation Processes, for example in water vapour, the oxygen predominantly on the semi-covalent bonds between aluminum, arsenic and phosphorus, whereby aluminum oxides are formed. Since the hydrogen is bound with arsenic or phosphorus, where with arsine (AsH ₃ ) and phosphine (PH ₃ ) or molecular hydrogen, atomic arsenic and phosphorus are formed. All of these by-products are very volatile at high temperatures.

They are expected to at least partially diffuse out of the structure. Phosphorus and phosphine have even higher volatility than arsenic and arsine. Therefore, the outgassing rate of phosphorus and phosphine should be much greater than that of arsenic and arsine. As a result, the resulting tensile stress in the stress-optimized oxidized layer resulting from oxidation of AlGaAsP will be similar to the standard oxidized layer resulting from oxidation of AlGaAs. However, there is a lower relative volume change. Because of the pressure-stressed adjacent indium-containing compound semiconductor layers, the overall stress in this semiconductor layer stack is reduced or even compensated for in comparison to the conventional layer stack. As a result, the film thickness of the oxide film can be increased significantly. As a result, a more voltage-resistant insulation layer can be provided, which can be used in power and high-voltage components, such as power transistors.

3D summarizes a method according to embodiments.

A method for manufacturing a semiconductor device includes the formation (S310) of a semiconductor layer stack comprising an Al _x Gai- _x As-containing layer, a first Al _y Gai- _y AsP layer, an Al _z Gai- _z As-containing layer and has a first indium-containing compound semiconductor layer adjoining the first Al _y Gai- _y AsP layer, the first Al _y Gai- _y AsP layer between See the Al _x Gai- _x As-containing layer and the Al _z Gai- _z As-containing layer arranged with 0<x<l, 0<y<l, y>x, y>z, and y>0 7, and performing (S320) an oxidation process whereby the first Al _y Gai- _y AsP layer is at least partially oxidized, thereby creating an insulating region.

The concept described with reference to FIGS. 3A and 3B can also be applied to the case where a semiconductor device 15 is to be provided in which two device regions 140, 145 are to be isolated from one another. However, unlike the case of the surface-emitting semiconductor laser, the insulating layer may be required to have a high dielectric strength. In this case, a layer stack 123 comprising a plurality of (In)AlGaAs layers 117 and 114 or phosphorus-containing AlGaAsP layers 119, as illustrated in Figure 4A, can be used.

The workpiece 15 illustrated in FIG. 4A has a first and second component region 140,145. The layer stack 123 is arranged between these areas and has alternately arranged (In)AlGaAs layers 117 and 114 or AlGaAsP layers 119 . An example of a layer thickness of the layer stack when using the Al _y Gai- _y As layers is 11460 nm. If the Al _y Gai- _y AsP layers 119 are used, there is no upper limit to the layer thickness. For example, the layer thickness of the layer stack when using AlGaAsP layers 119 can be more than 1 gm, for example 2 gm. In this case, for example, the layer thickness of the layer stack can be less than 5 μm.

After performing an oxidation process, the semiconductor device 20 shown in FIG. 4B can be obtained, for example, in which the first and second device regions 140, 145 are isolated from one another by the insulating layer stack 148 . The insulating layer stack 148 has alternately arranged InAlGaAs layers 117 and AlGaOAs layers 122 . The InAlGaAs layers are compressively strained and therefore compensate for the tensile stress in the AlGaOAs layers. Due to the increased layer thickness of the insulating layer stack 148, the first and second component regions 140, 145 are very well insulated from one another.

For example, the AlGaOAs layers 122 may have been produced by oxidizing AlGaAsP layers 119 . When using a layer stack that has AlGaAsP layers and indium-containing compound semiconductor layers 117 adjoining them, the tensile stress of the AlGaAsP layers can partially or completely compensate for the compressive stress of the indium-containing compound semiconductor layers. In this case, the layer thickness of the layer stack 148 can be as large as desired. For example, a layer thickness of the layer stack 148 can be greater than 60 nm.

According to embodiments described with reference to FIGS. 3A to 4B, the indium-containing compound semiconductor layer adjacent to the AlGaAs(P) layer to be oxidized may exhibit compressive stress, while the oxidized AlGaOAs layer is subject to tensile stress. The strain on the AlGaOAs layer can thus be compensated for by the adjacent compressively strained layer. As a result, the resulting layer stack has less strain than the AlGaOAs layer. As a further result, the mechanical stability of the oxidized layer and the adjacent layers is improved.

The dielectric strength of the insulating layer stack 148 shown in FIG. 4B can be determined by various measures. increased further. This is for example in Fig.

5A or 5B. As shown in FIG. 5A, the semiconductor device 20 has two insulating layers including portions of an Ali- _yk In _y Ga _k OAs layer 118 . The portions of Ali- _yk In _y Ga _k OAs layer 118 may be fabricated, for example, according to the method described with reference to FIGS. 1B and 2B. Due to oxidation, the Ali- _yk In _y Ga _k OAs layer 118 may contain amorphous regions with a varying composition ratio. A semi-insulating semiconductor layer 150 may be disposed between the insulating layers, which include regions of an _Aliyk In _y Ga _k OAs layer 118 .

For example, the semi-insulating semiconductor layer 150 can have any layer thickness depending on the requirements of the semiconductor component. The semi-insulating semiconductor layer 150 can contain, for example, a minimal or undoped semiconductor material with a wide band gap, for example GaAs or AlGaAs. In accordance with further specific embodiments, the semiconductor material of the semi-insulating semiconductor layer 150 can also contain lattice-matched GaAsP, AlAsP or very generally AlGaAsP to compensate for possible strains. Alternatively, the semi-insulating semiconductor layer can also be simultaneously doped with donors and acceptors in order to additionally impair mobility. For example, the respective concentration of the donors and acceptors can be set precisely as a function of the ionization energies and the temperature in order to set a high resistance. For example, the semi-insulating semiconductor layer can also be n-doped in order to compensate for carbon pollution.

In the case of the semiconductor component shown in FIG. 5B, additional insulation can be provided by a semiconductor layer stack, which represents an npn or pnp structure, are realized. The semiconductor component 20 shown in FIG. 5B in turn has a first and a second component region 140, 145. An Ali_ _yk In _y Ga _k OAs layer 118 is provided between the first and second device regions 140,145. the

Ali_ _yk In _y Ga _k OAs layer 118 may be fabricated using the process described with reference to Figures 1B and 2B. Furthermore, the component 20 comprises a first semiconductor layer 151 of a first conductivity type and a semiconductor layer 152 of a second conductivity type. The second semiconductor layer 152 is surrounded by the first semiconductor layer 151 on both sides. Depending on the doping of the first and the second semiconductor layer 151, 152, an npn or pnp structure is thus obtained. The insulating structure 149 may comprise one or two Ali_ _y _ _k In _y Ga _k OAs insulating layers 118, for example, the _{Ali_} y k In _y Ga _k OAs insulating layer 118 being on both sides or on one side of the pnp or npn Layer structure can be arranged.

FIG. 5C shows another semiconductor component according to embodiments, which is designed as an edge-emitting laser 30 . A plurality of laser elements 154 are stacked on top of one another over a substrate 100 . For example, the substrate 100 can have a layer 113 containing Al _z Ga _z As. Each of the laser elements 154 has a first semiconductor layer 116 of a first conductivity type, for example n-type, a second semiconductor layer 120 of a second conductivity type, for example p-type, and an active zone arranged between the first and second semiconductor layers 116, 120 115 on. For example, the second or the first semiconductor layer 120, 160 can have a layer 111 containing Al _x Ga _x As. An optical resonator 105 of each Laserele element 154 extends in a horizontal direction. the la serelemente 154 are arranged one above the other in the vertical direction and are electrically connected to one another by a tunnel contact 137 . A first contact element 132 for making electrical contact with the first semiconductor layer 116 is arranged, for example, adjacent to the substrate 100 on the side remote from the first semiconductor layer 116 . A second contact element 135 for making electrical contact with the second semiconductor layer 120 is arranged, for example, on the upper side of the semiconductor layer stack.

A tunnel contact 137 generally comprises a pn or pin junction, each with very highly doped layers, which is arranged in the blocking direction with respect to a voltage applied to the semiconductor component from the outside. A p ⁺⁺ -doped layer, an n ⁺⁺ -doped layer and optionally an intrinsic intermediate layer represent the tunnel contact 137. Through the tunnel contact 137, whose n-side is connected to the positive terminal, holes are made in the laser element 154 injected. In the region of the active zone 115, the injected holes recombine with the electrons provided by the negative connection, with the emission of photons.

Between the substrate 100 and the adjoining first semiconductor layer 116, an insulating layer region 118, 122 is arranged. This may be formed according to the methods described above with reference to Figures 1A, 2A, 3A, 4A. Furthermore, a white terer insulating layer region 118, 122 between the lowermost laser element 154 and the middle laser element 154 is arranged. This isolating area can also have been produced using the method described here. This further insulating layer region 118, 122 can be thinner than the lowermost insulating layer region 118, 122, for example. Furthermore, this further insulating layer area 118, 122 contain less Al. In this way, when a thermal oxidation process is performed, oxidation proceeds more slowly than in the lowermost insulating layer region. As a result, apertures 106 with a similar lateral extent are formed in each case. Due to the high Querleit capability in the highly doped tunnel contacts 137, the current profile defined by the second contact element 135 is widened. On the one hand, the oxide apertures 106 between the substrate and the bottom and middle laser element 154 lead to a lateral delimitation of the current path. As a result, the same or similar near field widths of the stacked laser elements 154 are achieved. Furthermore, it is avoided that the current reaches the mesa flanks. As a result, non-radiative surface recombination losses and inefficient pumping at the emitter edge are avoided. Furthermore, a more defined near-field profile is obtained.

Although specific embodiments have been illustrated and described herein, those skilled in the art will recognize that a variety of alternative and/or equivalent configurations may be substituted for the specific embodiments shown and described without departing from the scope of the invention. The application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, the invention is to be limited only by the claims and their equivalents. REFERENCE LIST

10 surface emitting semiconductor laser

15 workpiece

20 semiconductor device

30 edge emitting semiconductor laser

100 substrate

105 optical resonator

106 aperture

109 first major surface

110 semiconductor layer stack

111 Al _x Gai_ _x As-containing layer

112 Ali_ _yk In _y Ga _k As layer

113 Al _z Gai_ _z As-containing layer

114 Al _y Gai- _y As layer

115 active zone

116 first semiconductor layer

117 indium-containing compound semiconductor layer

118 Ali_ _yk In _y Ga _k OAs layer

119 Al _y Gai- _y AsP layer

120 second semiconductor layer

122 AlGaAsPO layer

123 layer stack

125 first resonator mirror

130 second resonator mirror

132 first contact element

135 second contact element

137 tunnel contact

140 first device region

143 semiconductor component

145 second device area

148 insulating layer stack

149 insulating structure

150 semi-insulating semiconductor layer Semiconductor layer of a first conductivity type Semiconductor layer of a second conductivity type Laser element

Claims

EXPECTATIONS

A method of manufacturing a semiconductor device (20) comprising:

Forming (S110) a semiconductor layer stack (110) containing an Al _x Gai- _x As-containing layer (111), an Al _z Gai- _z As- containing layer (113) and one between the Al _x Gai- _x As- containing Layer (111) and the Al _z Gai _z As-containing layer (113) arranged compressively strained Ali _yk In _y Ga _k As layer (112) has, with 0<x<l, 0<z<l, 0 .02<y<0.12, 0<k<0.05 and

performing (S120) an oxidation process whereby the compressively stressed Ali- _yk In _y Ga _k As layer (112) is at least partially oxidized, thereby creating an insulating region.

A method of manufacturing a semiconductor device (20) comprising:

Forming (S210) a semiconductor layer stack (110) comprising an Al _x Gai- _x As-containing layer (111), a first Al _y Gai- _y As layer (114), an Al _z Gai- _z As-containing layer ( 113), a first indium-containing compound semiconductor layer (117) adjoining the first Al _y Gai- _y As layer (114) and a second indium-containing compound semiconductor layer (117) adjoining the first Al _y Gai- _y As layer (114 ) Adjacent and on one of the first indium-containing compound semiconductor layer (117) facing away from the first Al _y Gai- _y As layer (114) is arranged, wherein the first Al _y Gai- _y As layer (114) between the Al _x Gai- _x As-containing layer (111) and the Al _z Gai- _z As-containing layer (113) is arranged, with 0<x<l, 0<y<l, y>x, y>z, and y>0.95, and

performing (S220) an oxidation process whereby the first Al _y Gai- _y As layer (114) is at least partially oxidized, thereby creating an insulating region. 3. The method according to claim 2, wherein a material of the first and/or second indium-containing compound semiconductor layer (117) is Al _X' In _y' _{Ga i X'-y'} As, with 0<x'<0.7 and

0.02<y'<0.26.

4. The method according to claim 2 or 3, wherein a layer thickness of the first Al _y Gai- _y As layer (114) is less than 15 nm.

5. The method according to any one of claims 2 to 4, wherein a layer thickness of the indium-containing compound semiconductor layer (117) is less than 10 nm.

6. The method according to any one of claims 2 to 5, wherein the layer stack (110) is a sequence of a plurality of Al _y Gai- _y As layers (114) with indium-containing compound semiconductor layers arranged between the individual Al _y Gai- _y As layers ( 117) contains.

7. The method of claim 6, wherein a number of Al _y _ Gai- _y As layers (114) is less than five.

8. The method of claim 1, wherein at least two Ali- _yk In _y Ga _k As layers (112) and a semi-insulating semiconductor layer (150) are formed between the two Ali- _yk In _y Ga _k As layers (112).

9. The method of claim 1, wherein at least two Ali- _yk In _y Ga _k As layers (112) and a first semiconductor layer

(151) of a first conductivity type, a second semiconductor ^¬ layer (152) of a second conductivity type and a third semiconductor layer (151) of the first conductivity type between the two Ali _yk In _y Ga _k As layers (112) are formed. 10. The method according to any one of claims 2 to 7, wherein at least two Al _y ^Gai- _y As layers (114) and a first semiconductor layer (151) of a first conductivity type, a second semiconductor layer (152) of a second conductivity type ^¬ and a third semiconductor layer (151) of the first conductivity type are formed between the two Al _y Gai- _y As layers (114).

A method of manufacturing a semiconductor device (20) comprising:

Forming (S310) a semiconductor layer stack (110) comprising an Al _x Gai- _x As-containing layer (111), a first Al _y Gai- _y AsP layer (119), an Al _z Gai- _z As-containing layer ( 113) and a first indium-containing compound semiconductor layer (117) adjoining the first Al _y Gai- _y AsP layer (119), where ^¬ at the first Al _y Gai- _y AsP layer (119) between the Al _x Gai- _x As-containing layer (111) and the Al _z Gai- _z As-containing layer (113) is arranged, with 0<x<l, 0<y<l, y>x, y>z, and y>0, 95, and

Carrying out (S320) an oxidation process, as a result of which the first Al _y ^Gai- _y AsP layer (119) is at least partially oxidized, as a result of which an insulating region is produced.

12. The method of claim 11, wherein the semiconductor layer ^stack (110) further comprises a second indium-containing compound semiconductor layer (117) which is adjacent to the first Al _y Gai- _y AsP layer (119) and on one of the first indi ^¬ umcontaining compound semiconductor layer (117) facing away from Be ^¬ te the first Al _y Gai- _y AsP layer (119) is arranged.

13. The method according to claim 11 or 12, wherein a material of the first and/or second indium-containing compound semiconductor layer (117) is Al _X' In _y' _{Ga i X'-y'} As, with 0<x'<0.7 and

0.02<y'<0.26. 14. The method according to any one of claims 11 to 13, wherein a layer thickness of the first Al _y Gai- _y AsP layer (119) is less than 10 nm.

15. The method according to any one of claims 11 to 14, wherein a layer thickness of the indium-containing compound semiconductor layer (117) is less than 10 nm.

16. The method according to any one of claims 11 to 15, wherein the layer stack (110) is a sequence of several Al _y Gai- _y AsP layers (119) each between the individual Al _y Gai- _y AsP layers (119) arranged indium-containing Compound semiconductor layers (117) contains.

17. Semiconductor component (10, 20, 30) with a semiconductor layer stack (110) containing an Al _x Gai- _x As-containing layer (111), an Al _z Gai- _z As- containing layer (113) and areas of a between the Al _x Gai- _x As-containing layer (111) and the Al _z Gai- _z As-containing layer (113) arranged Ali _yk In _y Ga _k OAs layer (118), with 0<x<l , 0<z<l, 0.02<y<0.12, k<0.05 and the areas of the Ali _yk In _y Ga _k OAs layer (118) represent an insulating area, the areas of the Ali- _yk In _y Ga _k OAs layer (118) or the first Al _y Gai- _y OAs layer (122) are suitable for isolating two component regions (140, 145) of the semiconductor component (20) from one another.

18. Semiconductor component (10, 20, 30) with a semiconductor layer stack (110) containing an Al _x Gai- _x As-containing layer (111), areas of a first Al _y Gai- _y OAs layer (122), an Al _z Gai- _z As-containing layer (113), one attached to the areas of the first Al _y Gai- _y OAs layer (122) adjoining first indium-containing compound semiconductor layer (117) and a second indium-containing compound semiconductor layer (117) which borders on the first Al _y Gai- _y As layer (114) and on a side of the first indium-containing compound semiconductor layer (117) facing away from the first Al _y _ Gai- _y As layer (114) is arranged, wherein the Be rich of the first Al _y Gai- _y OAs layer (122) between the Al _x Gai- _x As-containing layer (111) and the Al _z Gai _z As-containing layer (113) are arranged, with 0<x<l, 0<y<l, y>x, y>z, and y>0.95, and the areas of the first Al _y Gai- _y OAs layer (122) represent an insulating region.

19. Semiconductor component (10, 20, 30) with a semiconductor layer stack (110) containing an Al _x Gai- _x As-containing layer (111), areas of a first Al _y Gai- _y OAsP layer (122), an Al _z Gai- _z As-containing layer (113) and a region of the first Al _y Gai- _y OAsP layer (122) adjoining the first indium-containing compound semiconductor layer (117), the regions of the first Al _y Gai- _y OAsP -layer (122) is arranged between the Al _x Gai- _x As-containing layer (111) and the Al _z Gai- _z As-containing layer (113), with 0<x<l, 0<y<l, y >x, y>z, and y>0.95, and the regions of the first Al _y Gai- _y OAsP layer (122) represent an insulating region.

20. Semiconductor component (10) according to any one of claims 17 to 19, which as a surface-emitting semiconductor laser

(VCSEL) is formed, wherein the regions of the Ali- _yk In _y Ga _k OAs layer (118), the first Al _y Gai- _y OAs layer (122) or the first Al _y Gai- _y OAsP layer (122 ) forms an aperture (106) for current conduction in the semiconductor laser.

21. The semiconductor component (20) according to claim 18 or 19, where the regions of the Ali _yk In _y Ga _k OAs layer (118), the first Al _y Gai- _y OAs layer (122) or the first Al _y Gai - _y OAsP layer

(122) are suitable for isolating two component regions (140, 145) of the semiconductor component (20) from one another.

22. The semiconductor component (30) as claimed in one of claims 17 to 19, which is designed as an edge-emitting semiconductor laser with a plurality of laser elements (154) arranged one above the other, the regions of the Ali- _yk In _y Ga _k OAs layer

(118), the first Al _y Gai- _y OAs layer (122) or the first Al _y _ Gai- _y OAsP layer (122) forms an aperture (106) for current conduction in the semiconductor laser (30).