WO2022213719A1 - 链路状态测试方法及其装置、计算机可读存储介质 - Google Patents

链路状态测试方法及其装置、计算机可读存储介质 Download PDF

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WO2022213719A1
WO2022213719A1 PCT/CN2022/075681 CN2022075681W WO2022213719A1 WO 2022213719 A1 WO2022213719 A1 WO 2022213719A1 CN 2022075681 W CN2022075681 W CN 2022075681W WO 2022213719 A1 WO2022213719 A1 WO 2022213719A1
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Prior art keywords
serdes link
link
serdes
state
bit error
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PCT/CN2022/075681
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English (en)
French (fr)
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严丽琴
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中兴通讯股份有限公司
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Publication of WO2022213719A1 publication Critical patent/WO2022213719A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters

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  • the embodiments of the present application relate to, but are not limited to, the field of communications technologies, and in particular, relate to a link state testing method and device, and a computer-readable storage medium.
  • Embodiments of the present application provide a link state testing method and device thereof, and a computer-readable storage medium.
  • an embodiment of the present application provides a link status testing method, which is applied to a first device, where the first device is connected to a second device through a SerDes link group, and the SerDes link group It includes a first SerDes link and a second SerDes link, and the method includes: sending a test signal to the second device through the first SerDes link; obtaining data from the second SerDes link through the second SerDes link The feedback signal of the device, wherein the feedback signal is of the same origin as the test signal; the working state of the SerDes link group is determined according to the test signal and the feedback signal.
  • an embodiment of the present application further provides a method for testing a link state, which is applied to a second device, where the second device is connected to the first device through a SerDes link group, where the SerDes link group includes the first device.
  • SerDes link and a second SerDes link the method comprising: acquiring a test signal sent by the first device through the first SerDes link; sending a test signal to the first device through the second SerDes link a feedback signal, so that the first device determines the working state of the SerDes link group according to the test signal and the feedback signal, wherein the feedback signal and the test signal are of the same origin.
  • an embodiment of the present application further provides a first apparatus, including: a memory, a processor, and a computer program stored in the memory and running on the processor, where the processor implements the above when executing the computer program
  • a first apparatus including: a memory, a processor, and a computer program stored in the memory and running on the processor, where the processor implements the above when executing the computer program
  • the link state testing method of the first aspect is described.
  • an embodiment of the present application further provides a second device, including: a memory, a processor, and a computer program stored in the memory and running on the processor, the processor implements the above when executing the computer program
  • a second device including: a memory, a processor, and a computer program stored in the memory and running on the processor, the processor implements the above when executing the computer program
  • the link state testing method of the second aspect is described.
  • an embodiment of the present application further provides a computer-readable storage medium storing computer-executable instructions, where the computer-executable instructions are used to execute the link state testing method described in the first aspect or the second aspect. .
  • FIG. 1 is a schematic diagram of a test platform for performing a link state test method provided by an embodiment of the present application
  • FIG. 2 is a schematic diagram of a test platform for performing a link state test method provided by another embodiment of the present application.
  • FIG. 3 is a flowchart of a link state testing method provided by an embodiment of the present application.
  • FIG. 4 is a flowchart of determining the working state of a SerDes link group in a link state testing method provided by an embodiment of the present application;
  • FIG. 5 is a flowchart of determining the working state of a SerDes link group in a link state testing method provided by another embodiment of the present application;
  • FIG. 6 is a flowchart of determining the working state of a SerDes link group in a link state testing method provided by another embodiment of the present application.
  • FIG. 7 is a flowchart of a link state testing method provided by another embodiment of the present application when it is determined that a SerDes link group is in an abnormal working state;
  • FIG. 9 is a flow chart of enabling the first device to determine the working state of a SerDes link group in a link state testing method provided by an embodiment of the present application;
  • FIG. 10 is a flowchart of a method for testing a link state provided by an embodiment of the present application after acquiring a test signal;
  • FIG. 11 is a schematic diagram of a first device provided by an embodiment of the present application.
  • FIG. 12 is a schematic diagram of a second apparatus provided by an embodiment of the present application.
  • the present application provides a link state testing method and device, and a computer-readable storage medium.
  • the second device is sent to the second device through the first SerDes link.
  • Send a test signal and obtain a feedback signal from the second device that is homologous to the test signal through the second SerDes link, so that the working state of the SerDes link group can be determined according to the test signal and the feedback signal, that is, based on only two
  • the relevant communication detection signals between the hardware devices determine the working status of the SerDes link group, so as to find out the corresponding hidden problems of the SerDes link group, so as to facilitate the detection of the SerDes link group and the corresponding hardware equipment according to the known hidden problems.
  • FIG. 1 is a schematic diagram of a test platform for executing a link state test method provided by an embodiment of the present application.
  • the test platform includes, but is not limited to, a first device and a second device, wherein the first device is connected to the second device through a serializer-deserializer (SerDes) link group, and the SerDes
  • the link group includes but is not limited to a first SerDes link and a second SerDes link, wherein the first SerDes link is available for the first device to send downlink signals from the first device to the second device, and the second SerDes link
  • the first device can receive the upstream signal from the second device to the first device, and the upstream signal and the downstream signal are of the same origin.
  • the second device may be provided with several ports, each port being adapted to a corresponding SerDes link, in this case, the first device may communicate with each of the second devices.
  • the port is connected through its corresponding SerDes link. If the connection status of a port is displayed as not connected, the first device cannot connect to the port, indicating that the port cannot be adapted to the SerDes link for corresponding testing. Check for possible faults on the port accordingly.
  • the ports of the first device and the corresponding ports of the second device can be matched to facilitate link establishment, so as to realize the connection between the first device and the second device through the SerDes link group.
  • the first device can be, but is not limited to, various types of line cards.
  • the line card When the line card is connected to the second device, it can provide the second device with corresponding working conditions such as power supply, clock drive, etc.
  • the link test chip is integrated in the line card, and the link test chip is connected to the second device through the SerDes link, and is used to detect the state of the SerDes link.
  • the type of the link test chip does not matter in this embodiment. Limited, various types of Ethernet switching chips can be used, for example, a Broadcom (BROADCOM, BCM) chip produced by Broadcom, or a link test chip can be selected according to the SerDes link in the actual application.
  • BROADCOM Broadcom
  • BCM Broadcom
  • the second device may include, but is not limited to, various types of hardware devices with communication capabilities that can be integrated and adapted to electronic equipment or systems, such as controllers, computers, controller systems, and computers System, etc.
  • the second device can be a daughter card (Daughter Board) attached to a computer adapter card.
  • the daughter card does not need to match the contact design with the slot on the computer motherboard, but transmits the relevant information through the contact point with the mother card.
  • the types of signals can include, but are not limited to, a Moving Picture Experts Group (MPEG) sub-card, a capture sub-card and a TV tuner sub-card, etc., and, according to the actual situation, the sub-card can be selected as a CPU-carrying sub-card.
  • the daughter card may be a daughter card that does not carry a CPU, which is not limited in this embodiment.
  • the second device is provided with a signal conditioning chip, and the signal conditioning chip can further perform signal equalization and enhancement on the uplink signal in the second SerDes link, so that the first device can obtain a more stable and reliable uplink signal.
  • the specific type of the signal conditioning chip can be set according to the actual situation of the uplink signal, for example, a retimer (Retimer) chip is set to improve the transmission energy of the uplink signal, so as to reconstruct and expand the clock of the uplink signal, or, A driver (Redriver) chip is provided to improve the communication quality of the uplink signal, etc., which is not limited in this embodiment.
  • the test platform may further include, but is not limited to, a third device (not shown), the SerDes link group may also include, but is not limited to, a third SerDes link and a fourth SerDes link, a second SerDes link
  • the device is connected to the third device through a third SerDes link and a fourth SerDes link, wherein the third SerDes link can be used by the second device to send downlink signals from the second device to the third device, and the fourth SerDes link can be used.
  • the third device can match the second device as the load of the second device, in this case , the third device may be set to only transmit relevant communication signals to assist in the state test of the SerDes link group, without involving the specific determination of the state of the SerDes link group.
  • the third device may include, but is not limited to, various types of optical module fixtures and sets thereof, or simulated optical module fixtures and sets thereof obtained by simulating optical module fixtures.
  • the module fixture complies with different communication protocols. Therefore, in order to match the communication protocol applicable to the second device, a matching optical module fixture may be set accordingly, which is not limited in this embodiment.
  • the optical module fixture and the second device can be matched in a way of correspondingly matching each port, that is, it is only necessary to ensure that there are corresponding ports so that the The optical module fixture is matched with the second device. Therefore, in addition to selecting a single optical module fixture to match with the second device, multiple optical module fixtures can also be selected to match the second device.
  • the second device has 20 The ports are to be matched. In one case, if an optical module clamp also has at least 20 corresponding ports for matching, the third device can only set the optical module clamp.
  • the third device can be equipped with two optical modules as shown above at the same time, and the effect of matching with the second device can also be achieved as a whole.
  • the third device when the link state test is performed, the third device can be matched with the corresponding port of the second device to realize the test, and the SerDes parameter of the third device can be configured to match the corresponding port of the second device. Matching, if the parameter configuration fails, it can be determined that the corresponding port of the third device or the second device has a fault problem, which can be confirmed by replacing the corresponding port of the third device or the second device. It is understandable that this method is adopted.
  • the second device and the third device can be more easily adapted to test, so as to meet the test requirements, wherein the SerDes parameter is a hardware parameter well known to those skilled in the art, and for different third devices, the SerDes parameter can be performed correspondingly.
  • the settings, such as port rate, serial data parameters, serial clock parameters, and two-wire serial parameters, are not limited in this embodiment.
  • the port rate of the second device when the port rate of the second device is initially configured, in order to match it with the third device, it can be set to the maximum port rate. If it can be matched, it means that the port rate is smaller than the maximum port rate. It can also be matched with the third device. Since the port rate is adjustable, it is easier to match the second device with the third device in this way. To match the port rate of each device, it is not necessary to set the port rate to the maximum initially.
  • FIG. 2 is a schematic diagram of a test platform for executing a link state test method provided by another embodiment of the present application.
  • the test platform includes, but is not limited to, a first device and a second device, wherein the first device is connected to the second device through a serializer-deserializer (SerDes) link group, and the SerDes
  • the link group includes, but is limited to, a first SerDes link and a second SerDes link, wherein the first SerDes link can be used by the second device to obtain downlink signals from the first device to the second device, and the second SerDes link can be used for obtaining downlink signals from the first device to the second device.
  • the corresponding link state test can be implemented through the combination of the uplink signal and the downlink signal.
  • the ports of the first device and the corresponding ports of the second device can be matched to facilitate link establishment, so as to realize the connection between the first device and the second device through the SerDes link group.
  • the second device is provided with a programmable logic chip
  • the programmable logic chip has a test capability
  • the working state of the first SerDes link can be obtained through the programmable logic chip, so as to accurately understand the first SerDes chain.
  • the specific type of the programmable logic chip can be set according to the actual situation of the uplink signal, for example, it can be set as a Field Programmable Gate Array (FPGA) chip, or , set as a programmable logic chip with similar functions, etc., which is not limited in this embodiment.
  • FPGA Field Programmable Gate Array
  • the test platform may further include, but is not limited to, a third device
  • the SerDes link group may also include, but is not limited to, a third SerDes link and a fourth SerDes link
  • the second device passes through the third SerDes link.
  • link and a fourth SerDes link are connected to the third device, wherein the third SerDes link is available for the second device to transmit downlink signals from the second device to the third device, and the fourth SerDes link is available for the second device to obtain
  • the uplink signal from the third device to the second device, and the uplink signal and the downlink signal can be set to be the same source, in this case, the corresponding link state test can be implemented by the combination of the uplink signal and the downlink signal.
  • test platform and application scenarios described in the embodiments of the present application are for the purpose of illustrating the technical solutions of the embodiments of the present application more clearly, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application.
  • Those skilled in the art will know that , with the evolution of the test platform and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.
  • test platform shown in FIG. 1 or FIG. 2 does not constitute a limitation to the embodiments of the present application, and may include more or less components than the one shown, or combine some components , or a different component arrangement.
  • the first device or the second device can respectively call the stored link state test program to execute the link state test method.
  • FIG. 3 is a flowchart of a link state testing method provided by an embodiment of the present application, and the link state testing method can be applied to the first device in the test platform of the embodiment shown in FIG. 1,
  • the testing method includes but is not limited to step S100, step S200 and step S300.
  • Step S100 sending a test signal to the second device through the first SerDes link.
  • the test signal can be set to any form, as long as it can be sent in the first SerDes link and sent to the second device, for example, the test signal can be set to digital codes, character strings and graphics.
  • the digital code can be set to be random or fixed, the length and size of the character string can be set to vary, and the range of the graphic scene can also be set accordingly, which are not limited in this embodiment.
  • the first device and the second device before sending the test signal to the second device through the first SerDes link, the first device and the second device may be initialized, and the historical signal data of the first device and the second device may be cleared through the initialization operation to prevent The historical signal data of the first device and the second device have an interference influence on the link state test, so as to avoid causing a large error in the link state test, so as to improve the accuracy of the link state test.
  • the test signal can be sent in the form of a digital code, such as a pseudo-random binary sequence code (Pseudo-Random Binary Sequence, PRBS), and the PRBS is sent as a test signal, which can test the first SerDes as a high-speed serial channel.
  • PRBS pseudo-random binary sequence code
  • PRBS pseudo-random Binary Sequence
  • Step S200 obtaining a feedback signal from the second device through the second SerDes link, wherein the feedback signal and the test signal are of the same origin.
  • Step S300 determining the working state of the SerDes link group according to the test signal and the feedback signal.
  • the feedback signal is used as a homologous signal with the test signal, so the basic signal functions and properties of the feedback signal and the test signal are corresponding, and the corresponding difference between the two is brought by the difference.
  • the incoming status updates are all caused during link transmission. Specifically, since the test signal is sent through the first SerDes link, and the feedback signal is sent through the second SerDes link, there is no difference between the feedback signal and the test signal. The difference and the status update brought by the difference are based on the first SerDes link and the second SerDes link.
  • the working status of the SerDes link group can be directly determined through the test signal and the feedback signal , so as to find out the corresponding hidden problems of the SerDes link group, so as to improve the performance of the SerDes link group and the corresponding hardware equipment according to the known hidden problems, instead of waiting for the SerDes link group to have a problem before starting from the corresponding problem.
  • the business logic layer starts to gradually find the cause of the problem, thereby reducing the burden of the staff to find the problem. It is understandable that, compared with the traditional technology, the method of this embodiment can reduce the work of finding the SerDes link group problem. It increases the search efficiency for the SerDes link group problem, and helps to improve the use performance of the second device corresponding to the SerDes link group.
  • the homologous source of the feedback signal and the test signal means that the source of the test signal and the feedback signal is the same, that is, the feedback signal is essentially formed after the test signal is transmitted through the link.
  • the feedback signal can be the test signal in sequence. It is obtained after going through the first SerDes link, the second device and the second SerDes link. Therefore, the basic signal function and properties of the feedback signal and the test signal are corresponding, and the corresponding difference between the two is determined by the The status update brought about by the difference is caused by link transmission. Therefore, the working status of the SerDes link group can be determined based on the two signals.
  • the link status testing method can also be applied to the first device in the test platform of the embodiment shown in FIG. 2 , in this case, the test signal will be further transmitted to the third device through the second device. And perform feedback, that is, the feedback signal can be the test signal after the first SerDes link, the second device, the third SerDes link, the third device, the fourth SerDes link, the second device and the second SerDes link in sequence.
  • the working state of the SerDes link group composed of the first SerDes link, the second SerDes link, the third SerDes link and the fourth SerDes link can be determined through the test signal and the feedback signal, so as to find The potential problems existing in the SerDes link group are eliminated, and the use performance of the second device corresponding to the entire SerDes link group is further improved.
  • step S300 includes but is not limited to:
  • Step S310 determining the bit error parameter corresponding to the SerDes link group according to the test signal and the feedback signal;
  • Step S320 Determine the working state of the SerDes link group according to the bit error parameter.
  • the bit error parameter is used to represent the accuracy of data transmission within the SerDes link group in a certain period of time, and the bit error parameter is determined through the test signal and the feedback signal, that is, the data of the SerDes link group can be determined. Transmission status, and then determine its working status accurately and reliably by judging the data transmission status.
  • the SerDes link group before determining the bit error parameter corresponding to the SerDes link group according to the test signal and the feedback signal, it is also necessary to determine that the SerDes link group is in a locked state according to the test signal and the feedback signal, that is, determine the SerDes link group.
  • the ability to send and receive data normally is a small premise for obtaining the bit error parameters.
  • it is in an unlocked state it can be directly determined that the SerDes link group is in an abnormal working state. Therefore, by setting the detection of the locked state, the Optimized the process of judging the working status of SerDes link groups, making it easier to determine the working status of SerDes link groups.
  • step S320 includes but is not limited to:
  • Step S321 in the case that the bit error parameter is greater than the bit error threshold, it is determined that the SerDes link group is in an abnormal working state.
  • bit error parameter when the bit error parameter is greater than the bit error threshold, it means that the corresponding bit error data in the SerDes link group exceeds the amount of bit error data in the normal state, which means that the data in the SerDes link group is The transmission accuracy rate has not reached the standard corresponding to the bit error threshold. Therefore, it can be determined that the SerDes link group is in an abnormal working state.
  • the error threshold may be preset, and for those skilled in the art, the error threshold may be set according to a corresponding formula, which is relatively common in the art, so it is not described here. Repeat.
  • step S320 further includes but is not limited to:
  • Step S322 when the bit error parameter is less than or equal to the bit error threshold, it is determined that the SerDes link group is in a normal working state.
  • the error parameter when the error parameter is less than or equal to the error threshold, it means that the corresponding error data in the SerDes link group is within the range of the error data amount in the normal state, then it means that the SerDes chain The data transmission accuracy rate in the link group has reached the standard corresponding to the bit error threshold. Therefore, it can be determined that the SerDes link group is in a normal working state.
  • steps S400 and S500 are also included but not limited to.
  • Step S400 obtaining the working parameters of the SerDes link group and the working parameters of the second device;
  • Step S500 Determine the reason why the SerDes link group is in an abnormal working state according to the working parameters of the SerDes link group and the working parameters of the second device.
  • the working parameters of the SerDes link group and the working parameters of the second device can be obtained, and the obtained parameters can be analyzed accordingly.
  • the staff In order to further determine the reason why the SerDes link group is in the abnormal working state, it is convenient for the staff to adjust or update the SerDes link group according to the determined reason, and finally make the SerDes link group return to the normal working state.
  • the working parameters of the SerDes link group include, but are not limited to, the transmission data parameters of the first SerDes link and the transmission data parameters of the second SerDes link, etc.
  • the transmission data parameters may be the transmission rate.
  • transmission range, total amount of transmitted data, eye width and eye height of the eye diagram, and the working parameters of the second device include but are not limited to: hardware environment parameters of the second device (for example, including temperature and humidity, etc.), hardware internal parameters (for example, including heat dissipation and throughput, etc.), which are not limited in this embodiment.
  • the other one may not be obtained. parameters, that is, only the working parameters of the SerDes link group or the working parameters of the second device need to be acquired, which can reduce the difficulty of executing the steps in this embodiment under corresponding circumstances.
  • FIG. 8 is a flowchart of a link state testing method provided by another embodiment of the present application, and the link state testing method may be applied to the second device in the test platform of the embodiment shown in FIG. 2 .
  • test methods include but are not limited to:
  • Step S600 acquiring the test signal sent by the first device through the first SerDes link
  • Step S700 sending a feedback signal to the first device through the second SerDes link, so that the first device determines the working state of the SerDes link group according to the test signal and the feedback signal, wherein the feedback signal and the test signal are of the same origin.
  • the feedback signal is directly sent to the first device.
  • the feedback signal is that the test signal passes through the first SerDes link, the second device and the second SerDes link. so that the first device can directly determine the working state of the SerDes link group through the test signal and the feedback signal, so as to find out the corresponding hidden problems of the SerDes link group, so as to facilitate the detection of the SerDes link group according to the known hidden problems.
  • the performance of the link group and the corresponding hardware equipment is improved, and there is no need to wait until the SerDes link group has a problem before starting to find the cause of the problem step by step from its corresponding business logic layer, thus reducing the burden of the staff to find the problem.
  • the method of this embodiment can reduce the workload of searching for SerDes link group problems, improve the search efficiency for SerDes link group problems, and help improve the number of times corresponding to SerDes link groups.
  • the performance of the second device can reduce the workload of searching for SerDes link group problems, improve the search efficiency for SerDes link group problems, and help improve the number of times corresponding to SerDes link groups.
  • the feedback signal may also be that the test signal passes through the first SerDes link, the second device, the third SerDes link, the third device, the fourth SerDes link, the second device and the second SerDes link in sequence After that, the working state of the SerDes link group composed of the first SerDes link, the second SerDes link, the third SerDes link and the fourth SerDes link can be determined through the test signal and the feedback signal, thereby Find out the potential problems and hidden dangers existing in the SerDes link group, thereby helping to improve the use performance of the second device corresponding to the entire SerDes link group.
  • step S700 includes but is not limited to:
  • Step S710 sending a feedback signal to the first device through the second SerDes link, so that the first device obtains the first bit error parameter according to the test signal and the feedback signal, and enables the first device to determine the SerDes link according to the first bit error parameter The working status of the group.
  • the bit error parameter is used to represent the accuracy of data transmission within the SerDes link group in a certain time period, so that the first device can determine the bit error parameter through the test signal and the feedback signal, that is, can determine the SerDes The data transmission state of the link group, and then its working state can be accurately and reliably determined by judging the data transmission state.
  • the testing method further includes but is not limited to:
  • Step S800 determining a second bit error parameter corresponding to the first SerDes link according to the test signal and the preset test reference signal;
  • Step S900 determining the working state of the first SerDes link according to the second bit error parameter.
  • the second device since the second device has a programmable logic function, for example, the second device is provided with an FPGA chip, after acquiring the test signal sent by the first device through the first SerDes link, the test The signal and the preset test reference signal determine the second bit error parameter and determine the working state of the first SerDes link based on it, that is, the second device itself can determine the working state of the first SerDes link, which is equivalent to using the first SerDes link.
  • One more test is performed on the basis of the test of one device. In practical applications, sometimes the test of a certain link may be inaccurate, which will affect the judgment of the test result of the whole link. This test can summarize and compare the corresponding test results, so as to obtain more accurate test results, which greatly improves the accuracy of the overall link test.
  • the link test for the specific port can be performed in the corresponding manner, for example, if the first port of the second device is and the second port are respectively adapted to the FPGA chip and the Retimer chip, then for the SerDes link of the first port, the working state of the SerDes link can be determined by the second device and the first device at the same time, and for the SerDes link of the second port.
  • the second device For a SerDes link, the second device itself cannot determine the working state of the SerDes link, but only the first device can determine the working state of the SerDes link.
  • the test reference signal may be preset by the user, or may be set by the second device according to the actual test signal, or may be set in other similar ways, which is not limited in this embodiment. .
  • step S900 also includes but is not limited to:
  • Step S910 when the second error parameter is greater than the error threshold, it is determined that the first SerDes link is in an abnormal working state.
  • step S900 also includes but is not limited to:
  • Step S920 when the second bit error parameter is less than or equal to the bit error threshold, determine that the first SerDes link is in a normal working state.
  • test method further includes but is not limited to:
  • Step S1000 obtaining the working parameters of the first SerDes link and the working parameters of the second device
  • Step S1100 Determine the reason why the first SerDes link is in an abnormal working state according to the working parameters of the first SerDes link and the working parameters of the second device.
  • steps 910, 920, and steps 1000 to 1100 belong to the same inventive concept as the embodiments shown in the above steps S321, S322, and steps S400 to S500
  • steps 910, 920 and steps 1000 to 1100 belong to the same inventive concept as the embodiments shown in the above steps S321, S322, and steps S400 to S500
  • steps 910, 920 and steps 1000 to 1100 For the specific implementation of the embodiment shown in steps 1000 to 1100, reference may be made to the specific implementation of the embodiment shown in the above steps S321, S322, and steps S400 to S500.
  • step 910, step 920 and step 1000 The specific implementations of the embodiments shown in to 1100 are not repeated here.
  • an embodiment of the present application provides a first device 100 , the first device 100 includes: a first memory 110 , a first processor 120 , and a first device 100 that is stored on the first memory 110 and can be processed by the first A computer program running on the server 120.
  • the first processor 120 and the first memory 110 may be connected through a first bus or in other ways.
  • first device 100 in this embodiment can be applied to the test platform in the embodiment shown in FIG. 1 or FIG. 2 , and the first device 100 in this embodiment can form the structure shown in FIG. 1 or FIG. 2 .
  • these embodiments all belong to the same inventive concept, so these embodiments have the same implementation principles and technical effects, and will not be described in detail here.
  • the non-transitory software programs and instructions required to implement the link state testing method of the above embodiment are stored in the first memory 110, and when executed by the first processor 120, the link state testing method of the above embodiment is executed, for example , execute the above-described method steps S100 to S300 in FIG. 3 , method steps S310 to S320 in FIG. 4 , method step S321 in FIG. 5 , method step S322 in FIG. 6 or method steps S400 to S500 in FIG. 7 .
  • an embodiment of the present application provides a second device 200 , the second device 200 includes: a second memory 210 , a second processor 220 , and the second device 200 is stored in the second memory 210 and can be processed in the second A computer program running on the server 220.
  • the second processor 220 and the second memory 210 may be connected through a second bus or in other ways.
  • the second device in this embodiment can be applied to the test platform in the embodiment shown in FIG. 1 or FIG. 2
  • the first device in this embodiment can constitute the implementation shown in FIG. 1 or FIG. 2 .
  • the non-transitory software programs and instructions required to implement the link state testing method of the foregoing embodiment are stored in the second memory 210, and when executed by the second processor 220, the link state testing method of the foregoing embodiment is executed, for example , execute the method steps S600 to S700 in FIG. 8 , the method steps S710 in FIG. 9 , the method steps S800 to S900 in FIG. 10 , the method steps S910 to S920 or the method steps S1000 to S1100 described above.
  • an embodiment of the present application also provides a computer-readable storage medium, where the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are executed by a processor or controller, for example, by the above-mentioned Executed by a processor in the node embodiment, the above-mentioned processor can execute the link state testing method in the above-mentioned embodiment, for example, execute the above-described method steps S100 to S300 in FIG. 3 and method step S310 in FIG. 4 . to S320, method step S321 in FIG. 5, method step S322 in FIG. 6, method steps S400 to S500 in FIG. 7, method steps S600 to S700 in FIG. 8, method step S710 in FIG. method steps S800 to S900, method steps S910 to S920, or method steps S1000 to S1100.
  • the embodiments of the present application include: a link state testing method, applied to a first device, where the first device is connected to a second device through a SerDes link group, and the SerDes link group includes a first SerDes link and a second SerDes link, the The test method includes: sending a test signal to a second device through a first SerDes link, obtaining a feedback signal from the second device through a second SerDes link, and determining the working state of the SerDes link group according to the test signal and the feedback signal, The feedback signal and the test signal are of the same origin.
  • the test signal is sent to the second device through the first SerDes link, and obtained through the second SerDes link
  • the feedback signal from the second device is homologous to the test signal, so that the working state of the SerDes link group can be determined according to the test signal and the feedback signal, that is, the SerDes can be determined only based on the relevant communication detection signal between the two hardware devices.
  • the working status of the link group so as to find out the corresponding hidden problems of the SerDes link group, so as to improve the performance of the SerDes link group and the corresponding hardware devices according to the known hidden problems, without waiting for the SerDes link group to appear.
  • the solution provided by the embodiment of the present application can reduce the workload of finding the SerDes link group problem. , to improve the search efficiency for the SerDes link group problem, which is beneficial to improve the use performance of the hardware device corresponding to the SerDes link group.
  • Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cartridges, magnetic tape, magnetic disk storage or other magnetic storage devices, or may Any other medium used to store desired information and which can be accessed by a computer.
  • communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and can include any information delivery media, as is well known to those of ordinary skill in the art .

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Abstract

一种链路状态测试方法及其装置、计算机可读存储介质。其中，所述链路状态测试方法应用于第一装置，第一装置通过SerDes链路组与第二装置连接，SerDes链路组包括第一SerDes链路和第二SerDes链路，该测试方法包括：通过第一SerDes链路向第二装置发送测试信号，并通过第二SerDes链路获取来自第二装置的反馈信号，并根据测试信号和反馈信号确定SerDes链路组的工作状态，其中，反馈信号与测试信号同源。

Description

链路状态测试方法及其装置、计算机可读存储介质
相关申请的交叉引用
本申请基于申请号为202110377293.5、申请日为2021年4月8日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请实施例涉及但不限于通信技术领域，尤其涉及一种链路状态测试方法及其装置、计算机可读存储介质。
背景技术
目前，对于大多数的硬件设备来说，为了匹配日益扩展的通信网络，只能够不断提升自身的设计容量、通信速率以及功能类型，相应地，这对于硬件设备所应用的串行解串(Serializer-Deserializer，SerDes)链路的性能要求也越来越高。目前，在产业上，随着产品的复杂度不断增大，在硬件所对应的SerDes链路出现问题后，工作人员才会从其对应的业务逻辑层开始逐步的查找问题原因，这会耗费其很大的时间成本。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本申请实施例提供了一种链路状态测试方法及其装置、计算机可读存储介质。
第一方面，本申请实施例提供了一种链路状态测试方法，应用于第一装置，所述第一装置通过串行解串SerDes链路组与第二装置连接，所述SerDes链路组包括第一SerDes链路和第二SerDes链路，所述方法包括：通过所述第一SerDes链路向所述第二装置发送测试信号；通过所述第二SerDes链路获取来自所述第二装置的反馈信号，其中，所述反馈信号与所述测试信号同源；根据所述测试信号和所述反馈信号确定所述SerDes链路组的工作状态。
第二方面，本申请实施例还提供了一种链路状态测试方法，应用于第二装置，所述第二装置通过SerDes链路组与第一装置连接，所述SerDes链路组包括第一SerDes链路和第二SerDes链路，所述方法包括：获取由所述第一装置通过所述第一SerDes链路发送的测试信号；通过所述第二SerDes链路向所述第一装置发送反馈信号，以使所述第一装置根据所述测试信号和所述反馈信号确定所述SerDes链路组的工作状态，其中，所述反馈信号与所述测试信号同源。
第三方面，本申请实施例还提供了第一装置，包括：存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，所述处理器执行所述计算机程序时实现如上所述第一方面的链路状态测试方法。
第四方面，本申请实施例还提供了第二装置，包括：存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，所述处理器执行所述计算机程序时实现如上所述第二方面的链路状态测试方法。
第五方面，本申请实施例还提供一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令用于执行如上第一方面或第二方面所述的链路状态测试方法。
本申请的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本申请而了解。本申请的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本申请技术方案的进一步理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1是本申请一个实施例提供的用于执行链路状态测试方法的测试平台的示意图；
图2是本申请另一个实施例提供的用于执行链路状态测试方法的测试平台的示意图；
图3是本申请一个实施例提供的链路状态测试方法的流程图；
图4是本申请一个实施例提供的链路状态测试方法中确定SerDes链路组的工作状态的流程图；
图5是本申请另一个实施例提供的链路状态测试方法中确定SerDes链路组的工作状态的流程图；
图6是本申请另一个实施例提供的链路状态测试方法中确定SerDes链路组的工作状态的流程图；
图7是本申请另一个实施例提供的链路状态测试方法在确定SerDes链路组处于非正常工作状态的情况下的流程图；
图8是本申请另一个实施例提供的链路状态测试方法的流程图；
图9是本申请一个实施例提供的链路状态测试方法中使第一装置确定SerDes链路组的工作状态的流程图；
图10是本申请一个实施例提供的链路状态测试方法在获取测试信号之后的流程图；
图11是本申请一个实施例提供的第一装置的示意图；
图12是本申请一个实施例提供的第二装置的示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
需要说明的是，虽然在装置示意图中进行了功能模块划分，在流程图中示出了逻辑顺序，但是在某些情况下，可以以不同于装置中的模块划分，或流程图中的顺序执行所示出或描述的步骤。说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
本申请提供了一种链路状态测试方法及其装置、计算机可读存储介质，在第一装置通过SerDes链路组与第二装置进行连接的情况下，通过第一SerDes链路向第二装置发送测试信号，并通过第二SerDes链路获取来自第二装置的与测试信号同源的反馈信号，从而能够根据测试信号和反馈信号以确定SerDes链路组的工作状态，即，能够仅基于两个硬件装置之间的 相关通讯检测信号确定SerDes链路组的工作状态，从而查找出SerDes链路组相应存在的问题隐患，以便于根据所了解的问题隐患对SerDes链路组及相应的硬件设备进行性能完善，而不用等到SerDes链路组出现问题后才从其对应的业务逻辑层开始逐步地查找问题原因，从而减轻了工作人员查找问题的负担，因此，采用本申请实施例提供的方案，能够减小查找SerDes链路组问题的工作负担，提高对于SerDes链路组问题的查找效率，有利于提升与SerDes链路组对应的硬件设备的使用性能。
下面结合附图，对本申请实施例作进一步阐述。
如图1所示，图1是本申请一个实施例提供的用于执行链路状态测试方法的测试平台的示意图。
在图1的示例中，测试平台包括但不限于有第一装置和第二装置，其中，第一装置通过串行解串(Serializer-Deserializer，SerDes)链路组与第二装置连接，该SerDes链路组包括但不限于有第一SerDes链路和第二SerDes链路，其中，第一SerDes链路可供第一装置发送从第一装置至第二装置的下行信号，第二SerDes链路可供第一装置接收从第二装置至第一装置的上行信号，且上行信号与下行信号同源。
在一实施例中，如图1所示，第二装置可以设置有若干端口，每个端口与对应的SerDes链路适配，在这种情况下，第一装置可以与第二装置中的各个端口通过其对应的SerDes链路实现连接，若某个端口的连接状态显示为未连接，则第一装置无法连接该端口，说明该端口无法适配SerDes链路以进行相应地测试，工作人员可据此排查该端口可能出现的故障。
在一实施例中，如图1所示，第一装置的端口与第二装置的相应端口能够进行匹配从而便于建链，以实现第一装置通过SerDes链路组与第二装置连接。
在一实施例中，第一装置可以但不限于为各种类型的线卡，线卡在连接到第二装置的情况下，能够为第二装置提供相应的供电电源、时钟驱动等工作条件，其中，在线卡中集成有链路测试芯片，链路测试芯片通过SerDes链路与第二装置连接，用于实现对于SerDes链路的状态检测，链路测试芯片的类型在本实施例中并不作限制，可以采用各种类型的以太网交换芯片，比如，采用由博通公司所生产的博通(BROADCOM，BCM)芯片，或者，也可以根据实际应用中的SerDes链路来对应选择链路测试芯片。
在一实施例中，第二装置可以包括但不限于为具有通信性能的各种类型的硬件装置，该硬件装置可以集成并适用于电子设备或系统，比如控制器、计算机、控制器系统和计算机系统等，比如，第二装置可以是附加于计算机适配卡的子卡(Daughter Board)，子卡无需匹配与计算机主板上的插槽接触设计，而是通过与母卡的接触点来传输相关信号，其类型可以包括但不限于有动态图像专家组(Moving Picture Experts Group，MPEG)子卡、采集化子卡以及电视调谐子卡等，并且，根据实际情况，子卡可以选择为携带CPU的子卡或者为不携带CPU的子卡，这在本实施例中并未限制。
在一实施例中，第二装置设置有信号调理芯片,通过信号调理芯片能够进一步对第二SerDes链路中的上行信号进行信号均衡和增强，以便于第一装置能够获得更加稳定可靠的上行信号，其中，信号调理芯片的具体类型可以根据上行信号的实际情况进行设定，比如，设置重定时器(Retimer)芯片以提高上行信号的传输能量，从而对上行信号进行时钟重构扩展，或者，设置驱动器(Redriver)芯片以提高上行信号的通讯质量等，这在本实施例中并未限制。
在图1的示例中，测试平台还可以包括但不限于有第三装置(未示出)，SerDes链路组还可以包括但不限于有第三SerDes链路和第四SerDes链路，第二装置通过第三SerDes链路和第四SerDes链路与第三装置连接，其中，第三SerDes链路可供第二装置发送从第二装置至第三装置的下行信号，第四SerDes链路可供第二装置获取从第三装置至第二装置的上行信号，且上行信号与下行信号可以设置为同源；第三装置可以匹配第二装置以作为第二装置的负载，在这种情况下，第三装置可以设置为只传输相关通讯信号以辅助进行SerDes链路组的状态测试，而不涉及对于SerDes链路组的状态的具体判定。
在一实施例中，第三装置可以包括但不限于为各种类型的光模块夹具及其集合，或者，模拟光模块夹具而得到的仿真光模块夹具及其集合，一般而言，不同的光模块夹具满足不同的通信协议，因此，为了匹配第二装置所能够应用的通信协议，可以对应设置与其匹配的光模块夹具，这在本实施例中并未限制。
需要说明的是，以第三装置采用多个光模块夹具的集合为例，由于光模块夹具与第二装置之间可以采用各个端口对应配合的方式进行匹配，即，只需保证有对应端口使得光模块夹具与第二装置进行匹配，因此，除了选择单个光模块夹具与第二装置进行匹配，也可以选择合适的多个光模块夹具与第二装置进行匹配，例如，第二装置具有20个端口待匹配，一种情况是，若某一光模块夹具也至少具有20个对应端口进行匹配，则第三装置仅设置该光模块夹具即可，另一种情况是，若一个光模块夹具有15个对应端口，另一个光模块夹具有5个对应端口，则第三装置可以同时设置如上所示的两个光模块，整体上也能够达到与第二装置进行匹配的效果。
在一实施例中，在进行链路状态测试时，可以将第三装置与第二装置的相应端口进行配合以实现测试，可以通过配置第三装置的SerDes参数使其与第二装置的相应端口进行匹配，如果参数配置失败，则可以确定第三装置或者第二装置的相应端口存在故障问题，可以通过更换第三装置或者第二装置的相应端口进行确认，可以理解地是，采用该种方式使第二装置和第三装置能够更容易进行适配测试，从而满足测试需求，其中，SerDes参数是本领域技术人员所熟知的硬件参数，对于不同的第三装置而言，SerDes参数可以进行相应设定，比如为端口速率、串行数据参数、串行时钟参数以及两线式串行参数等，这在本实施例中并未限制。
在一实施例中，当初始配置第二装置的端口速率时，为使其与第三装置进行匹配，可以将其设置为最大端口速率，若能够匹配，则说明以小于最大端口速率的相应速率也能够与第三装置进行匹配，由于端口速率是可调的，因此，通过这种方式能够使得第二装置与第三装置更容易进行匹配，可以理解地是，若能够直接较为准确地将两个装置的端口速率进行匹配，则可以不必在初始时将端口速率设置为最大。
如图2所示，图2是本申请另一个实施例提供的用于执行链路状态测试方法的测试平台的示意图。
在图2的示例中，测试平台包括但不限于有第一装置和第二装置，其中，第一装置通过串行解串(Serializer-Deserializer，SerDes)链路组与第二装置连接，该SerDes链路组包括但限于有第一SerDes链路和第二SerDes链路，其中，第一SerDes链路可供第二装置获取从第一装置至第二装置的下行信号，第二SerDes链路可供第二装置发送从第二装置至第一装置的上行信号，且上行信号与下行信号同源，在这种情况下，通过上行信号与下行信号的组合能够实现相应的链路状态测试。
在一实施例中，如图2所示，第一装置的端口与第二装置的相应端口能够进行匹配从而便于建链，以实现第一装置通过SerDes链路组与第二装置连接。
在一实施例中，第二装置设置有可编程逻辑芯片,该可编程逻辑芯片具有测试能力，通过可编程逻辑芯片可以获取第一SerDes链路的工作状态，以便于准确地了解第一SerDes链路及上行信号的工作状态，其中，可编程逻辑芯片的具体类型可以根据上行信号的实际情况进行设定，比如，可以设置为现场可编程逻辑门阵列(Field Programmable Gate Array，FPGA)芯片，或者，设置为具有类似功能的可编程逻辑芯片等，这在本实施例中并未限制。
在图2的示例中，测试平台还可以包括但不限于有第三装置，SerDes链路组还可以包括但不限于有第三SerDes链路和第四SerDes链路，第二装置通过第三SerDes链路和第四SerDes链路与第三装置连接，其中，第三SerDes链路可供第二装置发送从第二装置至第三装置的下行信号，第四SerDes链路可供第二装置获取从第三装置至第二装置的上行信号，且上行信号与下行信号可以设置为同源，在这种情况下，通过上行信号与下行信号的组合能够实现相应的链路状态测试。
需要说明的是，本申请实施例描述的测试平台以及应用场景是为了更加清楚的说明本申请实施例的技术方案，并不构成对于本申请实施例提供的技术方案的限定，本领域技术人员可知，随着测试平台的演变和新应用场景的出现，本申请实施例提供的技术方案对于类似的技术问题，同样适用。
本领域技术人员可以理解的是，图1或图2中示出的测试平台的结构并不构成对本申请实施例的限定，可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置。
在图1或图2所示的测试平台中，第一装置或第二装置可以分别调用其储存的链路状态测试程序，以执行链路状态测试方法。
基于上述测试平台的结构，提出本申请的链路状态测试方法的各个实施例。
如图3所示，图3是本申请一个实施例提供的链路状态测试方法的流程图，该链路状态测试方法可以应用于如图1所示实施例的测试平台中的第一装置，测试方法包括但不限于步骤S100、步骤S200和步骤S300。
步骤S100，通过第一SerDes链路向第二装置发送测试信号。
在一实施例中，测试信号可以设置为任意形式，只要其能够实现在第一SerDes链路中进行发送并发送至第二装置即可，比如，测试信号可以设置为数字码、字符串以及图形场景等形式，数字码可以设置为随机或固定的，字符串的长度及大小可以变化设置，图形场景的范围也可相应设置，这在本实施例中均并未限制。
在一实施例中，在通过第一SerDes链路向第二装置发送测试信号之前，可以初始化第一装置和第二装置，通过初始化操作清除第一装置和第二装置的历史信号数据，以防止第一装置和第二装置的历史信号数据对于链路状态测试产生干扰影响，避免造成较大的链路状态测试误差，以便于提高链路状态测试的准确性。
在一实施例中，测试信号可以采用数字码形式发送，例如为伪随机二进制序列码(Pseudo-Random Binary Sequence，PRBS)，PRBS作为测试信号进行发送，可以测试作为高速串行通道的第一SerDes链路的实时状态，由于PRBS是本领域技术人员所熟知的，故在此不作赘述。
步骤S200，通过第二SerDes链路获取来自第二装置的反馈信号，其中，反馈信号与测试信号同源。
步骤S300，根据测试信号和反馈信号确定SerDes链路组的工作状态。
在一实施例中，反馈信号作为与测试信号的同源信号，因此反馈信号与测试信号的基本信号功能及其性质是相对应的，两者之间的相应差异性及由该差异性所带来的状态更新均是在链路传输时所造成的，具体地，由于测试信号经过第一SerDes链路所发送，且反馈信号经过第二SerDes链路所发送，所以反馈信号与测试信号之间的差异及由该差异性所带来的状态更新是基于第一SerDes链路和第二SerDes链路而造成的，因此，可以通过测试信号和反馈信号来直接地确定SerDes链路组的工作状态，从而查找出SerDes链路组相应存在的问题隐患，以便于根据所了解的问题隐患对SerDes链路组及相应的硬件设备进行性能完善，而不用等到SerDes链路组出现问题后才从其对应的业务逻辑层开始逐步地查找问题原因，从而减轻了工作人员查找问题的负担，可以理解地是，相比于传统技术，采用本实施例的方式，能够减小查找SerDes链路组问题的工作负担，提高对于SerDes链路组问题的查找效率，有利于提升与SerDes链路组对应的第二装置的使用性能。
可以理解地是，反馈信号与测试信号同源是指测试信号和反馈信号的来源相同，即，反馈信号实质上是测试信号经过链路传输后而形成的，换言之，反馈信号可以为测试信号依次经过第一SerDes链路、第二装置和第二SerDes链路之后而得到，因此，反馈信号与测试信号的基本信号功能及其性质是相对应的，两者之间的相应差异性及由该差异性所带来的状态更新是由于链路传输而造成的，因此，可以基于两个信号来确定SerDes链路组的工作状态。
在一实施例中，链路状态测试方法还可以应用于如图2所示实施例的测试平台中的第一装置，在这种情况下，测试信号通过第二装置会进一步传输到第三装置并进行反馈，即，反馈信号可以为测试信号依次经过第一SerDes链路、第二装置、第三SerDes链路、第三装置、第四SerDes链路、第二装置和第二SerDes链路之后而得到，因此，可以通过测试信号和反馈信号确定由第一SerDes链路、第二SerDes链路、第三SerDes链路和第四SerDes链路所组成的SerDes链路组的工作状态，从而查找出SerDes链路组相应存在的问题隐患，进而有利于提升与整个SerDes链路组所对应的第二装置的使用性能。
进一步地，如图4所示，步骤S300包括但不限于为：
步骤S310，根据测试信号和反馈信号确定与SerDes链路组对应的误码参数；
步骤S320，根据误码参数确定SerDes链路组的工作状态。
在一实施例中，误码参数用于表示在某一时间段的SerDes链路组内的数据传输准确性，通过测试信号和反馈信号确定误码参数，即，能够确定SerDes链路组的数据传输状态，进而通过判定数据传输状态以准确可靠地确定其工作状态。
在一实施例中，在根据测试信号和反馈信号确定与SerDes链路组对应的误码参数之前，还需要根据测试信号和反馈信号确定SerDes链路组处于锁定状态，即，确定SerDes链路组能够进行正常的数据收发，这是获取误码参数的一个小前提，反之，若其处于未锁定状态，则可以直接判定SerDes链路组处于非正常工作状态，因此，通过设置锁定状态的检测可以优化对于SerDes链路组的工作状态的判断流程，更方便于确定SerDes链路组的工作状态。
具体地，如图5所示，步骤S320包括但不限于有：
步骤S321,在误码参数大于误码阈值的情况下，确定SerDes链路组处于非正常工作状态。
在一实施例中，在误码参数大于误码阈值的情况下，则说明SerDes链路组中对应的误码数据超过了正常状态下的误码数据量，则说明SerDes链路组内的数据传输准确率没有达到与误码阈值对应的标准，因此，可以据此确定SerDes链路组处于非正常工作状态。
在一实施例中，误码阈值可以是预先设置好的，对于本领域技术人员而言，可以根据相应公式设置误码阈值，这在本领域中是较为常见的，故在此对其不做赘述。
具体地，如图6所示，步骤S320还包括但不限于有：
步骤S322,在误码参数小于或等于误码阈值的情况下，确定SerDes链路组处于正常工作状态。
在一实施例中，在误码参数小于或等于误码阈值的情况下，则说明SerDes链路组中对应的误码数据在正常状态下的误码数据量的范围之内，则说明SerDes链路组内的数据传输准确率已经达到与误码阈值对应的标准，因此，可以据此确定SerDes链路组处于正常工作状态。
此外，如图7所示，在根据步骤321确定SerDes链路组处于非正常工作状态的情况下，还包括但不限于有步骤S400和步骤S500。
步骤S400，获取SerDes链路组的工作参数和第二装置的工作参数；
步骤S500，根据SerDes链路组的工作参数和第二装置的工作参数确定SerDes链路组处于非正常工作状态的原因。
在一实施例中，当确定SerDes链路组处于非正常工作状态的情况，则可以通过获取SerDes链路组的工作参数和第二装置的工作参数，并对所获取的参数进行相应地分析，以便于进一步确定SerDes链路组处于非正常工作状态的原因，进而方便工作人员根据所确定的原因对SerDes链路组进行调整或更新，最终使得SerDes链路组回到正常工作的状态。
在一实施例中，SerDes链路组的工作参数包括但不限于有：第一SerDes链路的传输数据参数和第二SerDes链路的传输数据参数等，具体地，传输数据参数可以为传输速率、传输范围、传输数据总量、眼图的眼宽以及眼高等，第二装置的工作参数包括但不限于有：第二装置的硬件环境参数(比如，包括温度和干湿度等)、硬件内部参数(比如，包括散热量和吞吐量等)，这在本实施例中并未限制。
在一实施例中，若通过SerDes链路组的工作参数和第二装置的工作参数中的其中一种参数就能够确定SerDes链路组处于非正常工作状态的原因，则可以不获取另外一种参数，即，只需获取SerDes链路组的工作参数或第二装置的工作参数，这能够在相应情况下降低本实施例的步骤流程的执行难度。
如图8所示，图8是本申请另一个实施例提供的链路状态测试方法的流程图，该链路状态测试方法可以应用于如图2所示实施例的测试平台中的第二装置，测试方法包括但不限于：
步骤S600，获取由第一装置通过第一SerDes链路发送的测试信号；
步骤S700，通过第二SerDes链路向第一装置发送反馈信号，以使第一装置根据测试信号和反馈信号确定SerDes链路组的工作状态，其中，反馈信号与测试信号同源。
在一实施例中，在获取到测试信号的情况下，直接向第一装置发送反馈信号，在这种情况下，反馈信号为测试信号经过第一SerDes链路、第二装置和第二SerDes链路而得到，以使第一装置通过测试信号和反馈信号来直接地确定SerDes链路组的工作状态，从而查找出SerDes链路组相应存在的问题隐患，以便于根据所了解的问题隐患对SerDes链路组及相应的硬件设备进行性能完善，而不用等到SerDes链路组出现问题后才从其对应的业务逻辑层开 始逐步地查找问题原因，从而减轻了工作人员查找问题的负担，可以理解地是，相比于传统技术，采用本实施例的方式，能够减小查找SerDes链路组问题的工作负担，提高对于SerDes链路组问题的查找效率，有利于提升与SerDes链路组对应的第二装置的使用性能。
在一实施例中，反馈信号也可以为测试信号依次经过第一SerDes链路、第二装置、第三SerDes链路、第三装置、第四SerDes链路、第二装置和第二SerDes链路之后而得到，因此，可以通过测试信号和反馈信号确定由第一SerDes链路、第二SerDes链路、第三SerDes链路和第四SerDes链路所组成的SerDes链路组的工作状态，从而查找出SerDes链路组相应存在的问题隐患，进而有利于提升与整个SerDes链路组所对应的第二装置的使用性能。
如图9所示，步骤S700包括但不限于：
步骤S710，通过第二SerDes链路向第一装置发送反馈信号，以使第一装置根据测试信号和反馈信号得到第一误码参数，并使得第一装置根据第一误码参数确定SerDes链路组的工作状态。
在一实施例中，误码参数用于表示在某一时间段的SerDes链路组内的数据传输准确性，使得第一装置能够通过测试信号和反馈信号确定误码参数，即，能够确定SerDes链路组的数据传输状态，进而通过判定数据传输状态以准确可靠地确定其工作状态。
此外，如图10所示，在步骤S600之后，测试方法还包括但不限于：
步骤S800，根据测试信号和预置的测试参考信号确定与第一SerDes链路对应的第二误码参数；
步骤S900，根据第二误码参数确定第一SerDes链路的工作状态。
在一实施例中，由于第二装置具有可编程逻辑功能，比如，第二装置设置有FPGA芯片，则在获取到由第一装置通过第一SerDes链路发送的测试信号之后，进而能够根据测试信号和预置的测试参考信号确定第二误码参数并基于其判定第一SerDes链路的工作状态，即，第二装置自身即可确定第一SerDes链路的工作状态，相当于在由第一装置进行测试的基础上执行了多一次的测试，由于在实际应用中，有时会出现某条链路测试不准确的情况，进而影响到对于整体链路的测试结果的判定，因此，通过两次测试可以汇总比较相应的测试结果，从而得到更加准确的测试结果，大大提高了整体链路测试的准确度。
需要说明的是，若第二装置的端口对应的SerDes链路是与不同芯片所适配的，则针对具体端口的链路测试可以分别按照对应方式进行，比如，若第二装置的第一端口和第二端口分别对应适配于FPGA芯片和Retimer芯片，则针对第一端口的SerDes链路，可以由第二装置和第一装置同时确定该SerDes链路的工作状态，而针对第二端口的SerDes链路，则无法由第二装置自身确定该SerDes链路的工作状态，而只能由第一装置来确定该SerDes链路的工作状态。
在一实施例中，测试参考信号可以由用户预先设置好，也可以由第二装置根据实际的测试信号进行相应设定，或者以其他类似方式进行设定，这在本实施例中并未限制。
具体地，步骤S900还包括但不限于：
步骤S910，在第二误码参数大于误码阈值的情况下，确定第一SerDes链路处于非正常工作状态。
并且，步骤S900还包括但不限于：
步骤S920，在第二误码参数小于或等于误码阈值的情况下，确定第一SerDes链路处于 正常工作状态。
此外，在根据步骤910确定第一SerDes链路处于非正常工作状态的情况下，测试方法还包括但不限于：
步骤S1000，获取第一SerDes链路的工作参数和第二装置的工作参数；
步骤S1100，根据第一SerDes链路的工作参数和第二装置的工作参数确定第一SerDes链路处于非正常工作状态的原因。
需要说明的是，由于步骤910、步骤920以及步骤1000至1100所示的实施例与上述步骤S321、步骤S322以及步骤S400至S500所示的实施例属于同一发明构思，因此步骤910、步骤920以及步骤1000至1100所示的实施例的具体实施方式，可以参照上述步骤S321、步骤S322以及步骤S400至S500所示的实施例的具体实施方式，为避免冗余，步骤910、步骤920以及步骤1000至1100所示的实施例的具体实施方式在此不再赘述。
另外，参照图11，本申请的一个实施例提供了第一装置100，该第一装置100包括：第一存储器110、第一处理器120及存储在第一存储器110上并可在第一处理器120上运行的计算机程序。
第一处理器120和第一存储器110可以通过第一总线或者其他方式连接。
需要说明的是，本实施例中的第一装置100，可以应用于如图1或图2所示实施例中的测试平台，本实施例中的第一装置100能够构成图1或图2所示实施例中的测试平台的一部分，这些实施例均属于相同的发明构思，因此这些实施例具有相同的实现原理以及技术效果，此处不再详述。
实现上述实施例的链路状态测试方法所需的非暂态软件程序以及指令存储在第一存储器110中，当被第一处理器120执行时，执行上述实施例的链路状态测试方法，例如，执行以上描述的图3中的方法步骤S100至S300、图4中的方法步骤S310至S320、图5中的方法步骤S321、图6中的方法步骤S322或图7中的方法步骤S400至S500。
另外，参照图12，本申请的一个实施例提供了第二装置200，该第二装置200包括：第二存储器210、第二处理器220及存储在第二存储器210上并可在第二处理器220上运行的计算机程序。
第二处理器220和第二存储器210可以通过第二总线或者其他方式连接。
需要说明的是，本实施例中的第二装置，可以应用于如图1或图2所示实施例中的测试平台，本实施例中的第一装置能够构成图1或图2所示实施例中的测试平台的一部分，这些实施例均属于相同的发明构思，因此这些实施例具有相同的实现原理以及技术效果，此处不再详述。
实现上述实施例的链路状态测试方法所需的非暂态软件程序以及指令存储在第二存储器210中，当被第二处理器220执行时，执行上述实施例的链路状态测试方法，例如，执行以上描述的图8中的方法步骤S600至S700、图9中的方法步骤S710、图10中的方法步骤S800至S900、方法步骤S910至S920或方法步骤S1000至S1100。
此外，本申请的一个实施例还提供了一种计算机可读存储介质，该计算机可读存储介质存储有计算机可执行指令，该计算机可执行指令被一个处理器或控制器执行，例如，被上述节点实施例中的一个处理器执行，可使得上述处理器执行上述实施例中的链路状态测试方法，例如，执行以上描述的图3中的方法步骤S100至S300、图4中的方法步骤S310至S320、图 5中的方法步骤S321、图6中的方法步骤S322、图7中的方法步骤S400至S500、图8中的方法步骤S600至S700、图9中的方法步骤S710、图10中的方法步骤S800至S900、方法步骤S910至S920或方法步骤S1000至S1100。
本申请实施例包括：链路状态测试方法，应用于第一装置，第一装置通过SerDes链路组与第二装置连接，SerDes链路组包括第一SerDes链路和第二SerDes链路，该测试方法包括：通过第一SerDes链路向第二装置发送测试信号，并通过第二SerDes链路获取来自第二装置的反馈信号，并根据测试信号和反馈信号确定SerDes链路组的工作状态，其中，反馈信号与测试信号同源。根据本申请实施例提供的方案，在第一装置通过SerDes链路组与第二装置进行连接的情况下，通过第一SerDes链路向第二装置发送测试信号，并通过第二SerDes链路获取来自第二装置的与测试信号同源的反馈信号，从而能够根据测试信号和反馈信号以确定SerDes链路组的工作状态，即，能够仅基于两个硬件装置之间的相关通讯检测信号确定SerDes链路组的工作状态，从而查找出SerDes链路组相应存在的问题隐患，以便于根据所了解的问题隐患对SerDes链路组及相应的硬件设备进行性能完善，而不用等到SerDes链路组出现问题后才从其对应的业务逻辑层开始逐步地查找问题原因，从而减轻了工作人员查找问题的负担，因此，采用本申请实施例提供的方案，能够减小查找SerDes链路组问题的工作负担，提高对于SerDes链路组问题的查找效率，有利于提升与SerDes链路组对应的硬件设备的使用性能。
本领域普通技术人员可以理解，上文中所公开方法中的全部或某些步骤、系统可以被实施为软件、固件、硬件及其适当的组合。某些物理组件或所有物理组件可以被实施为由处理器，如中央处理器、数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。这样的软件可以分布在计算机可读介质上，计算机可读介质可以包括计算机存储介质(或非暂时性介质)和通信介质(或暂时性介质)。如本领域普通技术人员公知的，术语计算机存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、程序模块或其他数据)的任何方法或技术中实施的易失性和非易失性、可移除和不可移除介质。计算机存储介质包括但不限于RAM、ROM、EEPROM、闪存或其他存储器技术、CD-ROM、数字多功能盘(DVD)或其他光盘存储、磁盒、磁带、磁盘存储或其他磁存储装置、或者可以用于存储期望的信息并且可以被计算机访问的任何其他的介质。此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、程序模块或者诸如载波或其他传输机制之类的调制数据信号中的其他数据，并且可包括任何信息递送介质。
以上是对本申请的一些实施方式进行的具体说明，但本申请并不局限于上述实施方式，熟悉本领域的技术人员在不违背本申请范围的前提下还可作出种种的等同变形或替换，这些等同的变形或替换均包含在本申请权利要求所限定的范围内。

Claims (13)

  1. 一种链路状态测试方法，应用于第一装置，所述第一装置通过串行解串SerDes链路组与第二装置连接，所述SerDes链路组包括第一SerDes链路和第二SerDes链路，所述方法包括：
    通过所述第一SerDes链路向所述第二装置发送测试信号；
    通过所述第二SerDes链路获取来自所述第二装置的反馈信号，其中，所述反馈信号与所述测试信号同源；
    根据所述测试信号和所述反馈信号确定所述SerDes链路组的工作状态。
  2. 根据权利要求1所述的链路状态测试方法，其中，所述根据所述测试信号和所述反馈信号确定所述SerDes链路组的工作状态，包括：
    根据所述测试信号和所述反馈信号确定与所述SerDes链路组对应的误码参数；
    根据所述误码参数确定所述SerDes链路组的工作状态。
  3. 根据权利要求2所述的链路状态测试方法，其中，所述根据所述误码参数确定所述SerDes链路组的工作状态，包括：
    在所述误码参数大于误码阈值的情况下，确定所述SerDes链路组处于非正常工作状态；
    在所述误码参数小于或等于误码阈值的情况下，确定所述SerDes链路组处于正常工作状态。
  4. 根据权利要求3所述的链路状态测试方法，其中，在确定所述SerDes链路组处于非正常状态的情况下，所述方法还包括：
    获取所述SerDes链路组的工作参数和所述第二装置的工作参数；
    根据所述SerDes链路组的工作参数和所述第二装置的工作参数
    确定所述SerDes链路组处于非正常工作状态的原因。
  5. 根据权利要求1所述的链路状态测试方法，其中，所述SerDes链路组还包括第三SerDes链路和第四SerDes链路，所述第二装置通过所述第三SerDes链路和所述第四SerDes链路与第三装置连接，所述反馈信号为所述测试信号依次经过所述第一SerDes链路、所述第二装置、所述第三SerDes链路、所述第三装置、所述第四SerDes链路、所述第二装置和所述第二SerDes链路之后而得到。
  6. 一种链路状态测试方法，应用于第二装置，所述第二装置通过SerDes链路组与第一装置连接，所述SerDes链路组包括第一SerDes链路和第二SerDes链路，所述方法包括：
    获取由所述第一装置通过所述第一SerDes链路发送的测试信号；
    通过所述第二SerDes链路向所述第一装置发送反馈信号，以使所述第一装置根据所述测试信号和所述反馈信号确定所述SerDes链路组的工作状态，其中，所述反馈信号与所述测试信号同源。
  7. 根据权利要求6所述的链路状态测试方法，其中，所述通过所述第二SerDes链路向所述第一装置发送反馈信号，以使所述第一装置根据所述测试信号和所述反馈信号确定所述SerDes链路组的工作状态，包括：
    通过所述第二SerDes链路向所述第一装置发送反馈信号，以使所述第一装置根据所述测试信号和所述反馈信号得到第一误码参数，并使得所述第一装置根据所述第一误码参数确定 所述SerDes链路组的工作状态。
  8. 根据权利要求6所述的链路状态测试方法，其中，在获取由所述第一装置通过所述第一SerDes链路发送的测试信号之后，还包括：
    根据所述测试信号和预置的测试参考信号确定与所述第一SerDes链路对应的第二误码参数；
    根据所述第二误码参数确定所述第一SerDes链路的工作状态。
  9. 根据权利要求8所述的链路状态测试方法，其中，所述根据所述第二误码参数确定所述第一SerDes链路的工作状态，包括：
    在所述第二误码参数大于误码阈值的情况下，确定所述第一SerDes链路处于非正常工作状态；
    在所述第二误码参数小于或等于误码阈值的情况下，确定所述第一SerDes链路处于正常工作状态。
  10. 根据权利要求9所述的链路状态测试方法，其中，在确定所述第一SerDes链路处于非正常工作状态的情况下，所述方法还包括：
    获取所述第一SerDes链路的工作参数和所述第二装置的工作参数；
    根据所述第一SerDes链路的工作参数和所述第二装置的工作参数确定所述第一SerDes链路处于非正常工作状态的原因。
  11. 第一装置，包括：存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，其中，所述处理器执行所述计算机程序时实现如权利要求1至5中任意一项所述的链路状态测试方法。
  12. 第二装置，包括：存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，其中，所述处理器执行所述计算机程序时实现如权利要求6至10中任意一项所述的链路状态测试方法。
  13. 一种计算机可读存储介质，存储有计算机可执行指令，其中，所述计算机可执行指令用于执行如权利要求1至5中任意一项所述的链路状态测试方法，或者执行如权利要求6至10中任意一项所述的链路状态测试方法。
PCT/CN2022/075681 2021-04-08 2022-02-09 链路状态测试方法及其装置、计算机可读存储介质 WO2022213719A1 (zh)

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