WO2022206497A1

WO2022206497A1 - Mems resonator and processing method therefor, and clock device

Info

Publication number: WO2022206497A1
Application number: PCT/CN2022/082379
Authority: WO
Inventors: 吴国强; 陈文�; 贾文涵; 冯志宏; 徐景辉
Original assignee: 华为技术有限公司
Priority date: 2021-03-31
Filing date: 2022-03-23
Publication date: 2022-10-06
Also published as: CN115149921A

Abstract

Disclosed in the embodiments of the present application is an MEMS resonator, which is applied to fields such as communications and clock devices. The MEMS resonator comprises a fixing component, a harmonic oscillator and a support beam. The harmonic oscillator is connected to the fixing component by means of the support beam. The harmonic oscillator comprises an upper electrode layer, a piezoelectric layer and a device layer. The piezoelectric layer is between the upper electrode layer and the device layer. A buffer layer is arranged between the piezoelectric layer and the device layer. The material temperature coefficient of the piezoelectric layer is greater than that of the buffer layer, and the material temperature coefficient of the buffer layer is greater than that of the device layer. In the present application, the buffer layer is added in a perpendicular direction such that the process difficulty is reduced on the basis of reducing a thermal elastic loss.

Description

MEMS resonator and its processing method, clock device

This application claims the priority of the Chinese patent application with the application number CN202110349998.6 and the application name "MEMS resonator and its processing method, clock device" submitted to the State Intellectual Property Office of China on March 31, 2021, and its entire content Incorporated herein by reference.

technical field

The present application relates to the field of clock devices, in particular to a MEMS resonator and a processing method thereof, and a clock device.

Background technique

Compared with traditional electronic devices, Micro Electro Mechanical System (MEMS) devices have the advantages of small size, light weight and low power consumption.

The main performance parameters of MEMS resonators include resonant frequency, quality factor (Q) value, dynamic impedance, and frequency temperature coefficient. The Q-value is the result of a combination of various energy losses in the MEMS resonator. Various energy losses include air damping losses, thermoelastic dissipation (TED), material losses, anchor losses, and electrical load losses. Among them, the thermoelastic loss is the main factor restricting the Q value. Thermoelastic losses are caused by thermal gradients created by the MEMS resonator during vibration. The thermal gradient is flanked by the hot and cold ends. In order to reduce the thermoelastic loss, an etched isolation trench can be formed at the boundary line where the thermal gradient exists. The isolation trenches can reduce the heat flow between the hot and cold ends, thereby reducing the thermoelastic losses of the MEMS resonator.

However, the resonator of the resonant mode MEMS resonator is a multilayer composite structure in the vertical direction. The thermal gradients that produce thermoelastic losses are also vertically distributed. Therefore, it is necessary to etch isolation grooves on the sides of the resonator. In the processing flow of the MEMS resonator, the side etching process is more complicated.

SUMMARY OF THE INVENTION

The present application provides a MEMS resonator and a processing method thereof, and a clock device. By adding a buffer layer in the vertical direction, the process difficulty can be reduced on the basis of reducing the thermal elastic loss.

A first aspect of the present application provides a MEMS resonator. A MEMS resonator includes a stationary part, a resonator, and a support beam. The resonator is connected with the fixed part through the support beam. The resonator includes an upper electrode layer, a piezoelectric layer and a device layer. The piezoelectric layer is between the upper electrode layer and the device layer. A buffer layer is provided between the piezoelectric layer and the device layer. The material temperature coefficient of the piezoelectric layer is greater than the material temperature coefficient of the buffer layer, and the material temperature coefficient of the buffer layer is greater than the material temperature coefficient of the device layer. Among them, the material temperature coefficient

α is the coefficient of thermal expansion, E is Young's modulus, ρ is mass density, C is specific heat capacity, and v is Poisson's ratio.

In the present application, the temperature coefficient of material between the piezoelectric layer, buffer layer and device layer varies in a gradient. Therefore, the buffer layer can reduce the heat flow between the piezoelectric layer and the device layer, reduce the thermoelastic loss of the MEMS resonator, and thus improve the Q value. Moreover, the process of adding the buffer layer in the vertical direction is simpler than etching the isolation trenches on the side. Therefore, the present application can reduce the difficulty of the process.

In an alternative to the first aspect, a lower electrode layer is included between the piezoelectric layer and the device layer. The buffer layer is between the lower electrode layer and the device layer. In the present application, the piezoelectric layer is defined, and the temperature coefficient of the material between the buffer layer and the device layer changes in a gradient, thus defining the selectable range of the material of the buffer layer. Moreover, when the device layer is used as the lower electrode layer of the resonator, in order to improve the working efficiency of the resonator, the buffer layer needs to be a conductive material. Therefore, the present application adds a lower electrode layer. The lower electrode layer is between the buffer layer and the piezoelectric layer. Thus the buffer layer may be a non-conductive material. Therefore, the present application increases the optional range of materials for the buffer layer.

In an optional manner of the first aspect, the buffer layer is a non-conductive material.

In an optional manner of the first aspect, the material temperature coefficient of the lower electrode layer is greater than the material temperature coefficient of the buffer layer, and the material temperature coefficient of the lower electrode layer is smaller than the material temperature coefficient of the piezoelectric layer. Among them, the present application defines that the material temperature coefficients of the piezoelectric layer, the lower electrode layer, the buffer layer and the device layer change in a gradient. At this time, the lower electrode layer also acts as a buffer layer. Because, the present application can further reduce the thermoelastic loss.

In an optional manner of the first aspect, the material of the buffer layer is germanium. Wherein, when the material of the piezoelectric layer is aluminum nitride, the material temperature coefficient of the piezoelectric layer is about 1.11. When the material of the device layer is single crystal silicon, the material temperature coefficient of the device layer is about 0.337. The material temperature coefficient of germanium is about 0.767. Therefore, the material temperature coefficient of germanium is approximately equal to the intermediate value of the material temperature coefficient of the device layer and the material temperature coefficient of the piezoelectric layer. Therefore, the present application can further reduce the heat flow between the piezoelectric layer and the device layer, and reduce the thermoelastic loss of the MEMS resonator.

In an optional manner of the first aspect, the buffer layer includes a plurality of buffer sublayers. In the direction from the device layer to the piezoelectric layer, the material temperature coefficients of the plurality of buffer sub-layers gradually increase. Among them, by adding a plurality of buffer sub-layers, the thermal gradient between each layer between the device layer and the piezoelectric layer can be further reduced. Therefore, the present application can further reduce the heat flow between the piezoelectric layer and the device layer, and reduce the thermoelastic loss of the MEMS resonator.

In an optional manner of the first aspect, the material of at least one buffer sublayer in the plurality of buffer sublayers is silicon germanium. Wherein, when the ratio of silicon and germanium in the silicon germanium is different, the material temperature coefficient of the silicon germanium is different. By adding SiGe to multiple buffer sublayers, the positions of different buffer sublayers can be flexibly adjusted. Therefore, the present application can increase the flexibility of arranging multiple buffer sublayers.

In an optional manner of the first aspect, the material of the plurality of buffer sub-layers further includes any one or more of gallium arsenide, silicon nitride, diamond or germanium. Each material corresponds to one buffer sublayer of the plurality of buffer sublayers. For example, when the material of the plurality of buffer sublayers further includes gallium arsenide, the buffer layer includes two buffer sublayers. The materials of the two buffer sub-layers are silicon germanium and gallium arsenide respectively.

In an optional manner of the first aspect, along the direction from the device layer to the piezoelectric layer, the materials of the multiple cache sub-layers are silicon germanium, gallium arsenide, silicon nitride, diamond, germanium; or, The materials of the multiple cache sub-layers are gallium arsenide, silicon germanium, silicon nitride, diamond, and germanium in sequence; or, the materials of the multiple cache sub-layers are gallium arsenide, silicon nitride, silicon germanium, and diamond in sequence. germanium; or, the materials of the multiple cache sub-layers are gallium arsenide, silicon nitride, diamond, silicon germanium, germanium in sequence.

In an optional manner of the first aspect, the buffer layer serves as the lower electrode layer of the resonator. Among them, when the buffer layer is used as the lower electrode layer, the thickness of the resonator can be reduced. Specifically, when the buffer layer is not used as the lower electrode layer, the resonator includes an upper electrode layer, a piezoelectric layer, a lower electrode layer, a buffer layer and a device layer. When the buffer layer is used as the lower electrode layer, the resonator includes an upper electrode layer, a piezoelectric layer, a buffer layer and a device layer.

In an optional manner of the first aspect, the thickness of the buffer layer is smaller than the thickness of the device layer.

In an optional manner of the first aspect, the thickness of the buffer layer is 0.1 micrometers to 10 micrometers.

In an optional manner of the first aspect, the fixing member includes a substrate and an upper cavity wall. A cavity is formed between the substrate and the upper cavity wall. Among them, the harmonic oscillator is suspended in the cavity through the support beam.

In an optional manner of the first aspect, the junction of the substrate and the upper cavity wall includes a conductive layer. The conductive layer and the device layer have the same thickness.

In an optional manner of the first aspect, a silicon oxide layer is included above the substrate. Wherein, the silicon oxide layer is used to isolate the electrical connection between the substrate and the conductive layer.

A second aspect of the present application provides a method for manufacturing a MEMS resonator. The method includes providing a silicon on insulator (SOI) wafer including a substrate and a device layer. A buffer layer is deposited on the device layer. A piezoelectric layer is deposited on the buffer layer. An upper electrode layer is deposited on the piezoelectric layer. The device layers are etched to form resonators and support beams. The resonator is sealed by the upper cavity wall. The material temperature coefficient of the piezoelectric layer is greater than the material temperature coefficient of the buffer layer, and the material temperature coefficient of the buffer layer is greater than the material temperature coefficient of the device layer. Material temperature coefficient

In an optional manner of the second aspect, before depositing the piezoelectric layer on the buffer layer, the method further includes: depositing a lower electrode layer on the buffer layer.

In an optional manner of the second aspect, the buffer layer is a non-conductive material.

In an optional manner of the second aspect, the material temperature coefficient of the lower electrode layer is greater than that of the buffer layer, and the material temperature coefficient of the lower electrode layer is smaller than the material temperature coefficient of the piezoelectric layer.

In an optional manner of the second aspect, the material of the buffer layer is germanium.

In an optional manner of the second aspect, the buffer layer includes a plurality of buffer sublayers. Wherein, along the direction from the device layer to the piezoelectric layer, the material temperature coefficients of the plurality of buffer sub-layers gradually increase.

In an optional manner of the second aspect, the material of at least one buffer sublayer in the plurality of buffer sublayers is silicon germanium.

In an optional manner of the second aspect, the materials of the plurality of buffer sublayers further include any one or more of gallium arsenide, silicon nitride, diamond or germanium, and each material corresponds to the plurality of buffer sublayers A buffer sublayer in .

In an optional manner of the second aspect, along the direction from the device layer to the piezoelectric layer, the materials of the plurality of cache sub-layers are silicon germanium, gallium arsenide, silicon nitride, diamond, germanium; or, The materials of the multiple cache sub-layers are gallium arsenide, silicon germanium, silicon nitride, diamond, and germanium in sequence; or, the materials of the multiple cache sub-layers are gallium arsenide, silicon nitride, silicon germanium, and diamond in sequence. germanium; or, the materials of the multiple cache sub-layers are gallium arsenide, silicon nitride, diamond, silicon germanium, germanium in sequence.

In an optional manner of the second aspect, the buffer layer serves as the lower electrode layer of the resonator.

In an optional manner of the second aspect, the thickness of the buffer layer is smaller than the thickness of the device layer.

In an optional manner of the second aspect, the thickness of the buffer layer is 0.1 micrometers to 10 micrometers.

In an optional manner of the second aspect, the fixing member includes a substrate and an upper cavity wall. A cavity is formed between the substrate and the upper cavity wall. Among them, the harmonic oscillator is suspended in the cavity through the support beam.

In an optional manner of the second aspect, the junction of the substrate and the upper cavity wall includes a conductive layer. Wherein, the thickness of the conductive layer and the device layer are the same.

In an optional manner of the second aspect, a silicon oxide layer is included over the substrate. Wherein, the silicon oxide layer is used to isolate the electrical connection between the substrate and the conductive layer.

A third aspect of the present application provides a clock device including a MEMS resonator and a hold circuit. The hold circuit provides closed-loop oscillatory excitation for the MEMS resonator. The MEMS resonator generates a clock signal by oscillating excitation. Wherein, the MEMS resonator is the MEMS resonator described in the foregoing first aspect.

A fourth aspect of the present application provides a terminal, where the terminal includes a clock device and a processor. Clock devices are used to provide clock signals to the processor. The processor performs arithmetic processing according to the clock signal. The clock device is the clock device described in the third aspect.

A fifth aspect of the present application provides a computer storage medium, characterized in that, the computer storage medium stores instructions, and when the instructions are executed on a computer, the computer is made to execute any one of the second aspect or the second aspect. The method of one embodiment.

A sixth aspect of the present application provides a computer program product, characterized in that, when the computer program product is executed on a computer, the computer causes the computer to execute the method according to the second aspect or any one of the implementation manners of the second aspect. .

Description of drawings

1 is a schematic flowchart of a method for processing a MEMS resonator provided in the application;

2a to 2f are schematic structural diagrams of the MEMS resonator provided in the application in different processing processes;

3 is a top view of the MEMS resonator provided in the application;

4 is a schematic structural diagram of the MEMS resonator provided in the application;

Fig. 5 is a structural representation of the harmonic oscillator provided in the application;

Fig. 6 is another structural schematic diagram of the harmonic oscillator provided in this application;

Fig. 7 is another structural schematic diagram of the harmonic oscillator provided in the application;

8 is a schematic diagram of the relationship between the Q value of the MEMS resonator provided in the application and the thickness of the buffer layer;

9 is a schematic diagram of the relationship between the Q value of the MEMS resonator provided in the application and the thickness of the lower electrode layer;

10 is a schematic structural diagram of a clock device provided in the application;

FIG. 11 is a schematic structural diagram of a terminal provided in this application.

Detailed ways

It should be understood that the use of "first", "second", etc. in the description of the embodiments of the present application is only for the purpose of distinguishing the description, and cannot be understood as indicating or implying relative importance, nor can it be understood as indicating or implying a sequence.

It should be understood that this application may only briefly describe the various processing steps and/or components of the MEMS resonator because those of ordinary skill in the art are familiar with the steps and/or components in the processing method. Also, different processing steps and/or devices to achieve the same purpose may be substituted for each other. Accordingly, this application describes specific examples of processing steps and/or components to simplify the technical solutions disclosed herein. Of course, these examples are not intended to be limiting. Additionally, for brevity and clarity, reference numbers and/or letters are repeated in various embodiments of the present application. Repetition does not imply a strictly limiting relationship between the various embodiments and/or configurations.

FIG. 1 is a schematic flowchart of a method for manufacturing a MEMS resonator provided in this application. In order to facilitate the description of the processing method of the MEMS resonator, the corresponding description will be made in the following in conjunction with the schematic diagrams of the structure of the MEMS resonator in different processing processes. Specifically, FIGS. 2 a to 2 f are schematic structural diagrams of the MEMS resonator provided in the present application in different processing processes. As shown in Figure 1, the processing method includes the following steps.

In step 101, an SOI wafer including a substrate and device layers is provided.

SOI wafers are also called carrier wafers, and carrier wafers are silicon wafers. As shown in FIG. 2 a , the SOI wafer includes a substrate 201 , a silicon oxide layer 202 , and a device layer 203 . The silicon oxide layer 202 is located between the substrate 201 and the device layer 203 for realizing electrical isolation of the substrate 201 and the device layer 203 . The silicon oxide layer 202 may be silicon oxide obtained by thermal oxygen growth. The substrate 201 is also referred to as a substrate. The materials of the substrate 201 and the device layer 203 may be the same or different. For example, the materials of the substrate 201 and the device layer 203 are silicon-based materials, ceramic materials or polymer materials. Besides, the substrate 201 and the device layer 203 may also include other elemental semiconductors (eg, germanium), or other compound semiconductors (eg, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, etc.). Since the materials of the substrate 201 and the device layer 203 do not affect the realization of the technical solution, the present application does not limit the materials of the substrate 201 and the device layer 203 .

A cavity is included between the device layer 203 and the silicon oxide layer 202 . The shape of the cavity can be a cuboid, cylindrical, prismatic or pyramidal structure. In other embodiments, the shape of the cavity is adapted to the shape of the resonator. For example, if the shape of the cavity is a cylinder, the shape of the harmonic oscillator is a cylinder with a smaller radius. For example, if the shape of the cavity is a rectangle, the shape of the harmonic oscillator is a similar rectangle. Through the subsequent etching process, the resonator can be suspended above the cavity.

In step 102, a buffer layer is deposited on the device layer.

Buffer layer 204 is deposited and patterned on device layer 203 as shown in FIG. 2b. The deposition method may be physical vapor deposition, chemical vapor deposition or epitaxial growth. The material temperature coefficient of the buffer layer 204 is greater than the material temperature coefficient of the device layer. Material temperature coefficient

α is the coefficient of thermal expansion, E is Young's modulus, ρ is mass density, C is specific heat capacity, and v is Poisson's ratio. The thickness of the buffer layer 204 ranges from 0.1 micrometers to 10 micrometers. The area of the buffer layer 204 is smaller than or equal to that of the device layer 203 .

The material of the buffer layer 204 is a conductive material. For example, gallium arsenide (GaAs), germanium (Ge) or silicon germanium (SixGe1-x), etc. The conductive material may also be a doped semiconductor material. Wherein, the subscripts x and 1-x in the silicon germanium (SixGe1-x) indicate that the ratio of silicon and germanium in the silicon germanium can be adjusted. Buffer layer 204 may include one or more buffer sublayers. A 2-layer buffer sublayer is shown in Figure 2b. The ellipsis between the two buffer sublayers indicates that the buffer layer 204 can have more buffer sublayers. When the buffer layer 204 includes a plurality of buffer sub-layers, the deposition order of the plurality of buffer sub-layers is the order of the temperature material coefficient from low to high. The material of the plurality of buffer sub-layers may be any one or more of gallium arsenide, silicon germanium or germanium. Each material corresponds to one buffer sublayer of the plurality of buffer sublayers. For example, when the material of the plurality of buffer sublayers includes gallium arsenide, silicon germanium and germanium. The buffer layer 204 includes three buffer sublayers. By adjusting the ratio of silicon and germanium in silicon germanium, silicon germanium with different temperature material coefficients can be obtained. At this time, the SiGe may be in different positions in the 3 buffer sublayers. Specifically, the deposition sequence of the three buffer sublayers may be silicon germanium, gallium arsenide, and germanium. Alternatively, the deposition sequence of the three buffer sublayers may be GaAs, SiGe, and Ge. Alternatively, alternatively, the deposition sequence of the three buffer sublayers may be GaAs, Ge, SiGe.

In step 103, a piezoelectric layer is deposited on the buffer layer.

As shown in FIG. 2c , a piezoelectric layer 205 is included on the buffer layer 204 . Specifically, the piezoelectric layer 205 with a thickness of 0.3 μm to 1.5 μm is sputtered on the buffer layer 204 by a method of magnetron sputtering. The material of the piezoelectric layer 205 may be aluminum nitride (AlN), aluminum scandium nitride (AlScN), lead zirconate titanate (PZT), lithium niobate (LiNbO3), or the like.

As shown in FIG. 2d , after the piezoelectric layer 205 is deposited, the piezoelectric layer 205 is etched to form opening 1 and opening 2 . The area between the opening 1 and the opening 2 serves as the area where the resonator is formed subsequently. Opening 1 and Opening 2 serve as areas forming the support beam.

In step 104, an upper electrode layer is deposited on the piezoelectric layer.

As shown in FIG. 2e , an upper electrode layer 206 is included on the piezoelectric layer 205 . Specifically, the upper electrode layer 206 is deposited on the piezoelectric layer 205 by a low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) or a physical vapor deposition (Physicacl Vapor Deposition, PVD) method. The material of the upper electrode layer 206 may be polysilicon or metal, and the metal may be molybdenum, platinum, titanium, aluminum, or the like.

In step 105, the device layer is etched to form the resonator and the support beam.

As shown in FIG. 2f, by etching the device layer 203,

openings

3 and 4 are formed. Opening 3 is below opening 1 and opening 4 is below opening 2 . The area between the opening 3 and the opening 4 is the area of the resonator, and the area of the opening 3 and the opening 4 is the area of the support beam. Specifically, FIG. 3 is a top view of the MEMS resonator provided in this application. FIG. 2f can be understood as a schematic cross-sectional view obtained by cutting along the dotted line in FIG. 3 . As shown in FIG. 3 , the MEMS resonator includes a fixed part 303 , a resonator 301 and a support beam 302 . By etching the device layer 203, a cavity between the resonator 301 and the fixed part is formed. Specifically, it is the opening 3 and the opening 4 in FIG. 2f.

The fixing member 303 may be the substrate 201 in FIG. 2f , or the device layer 203 , or a combination of the substrate 201 and the device layer 203 .

The resonator 301 includes the device layer 203, the buffer layer 204, the piezoelectric layer 205 and the upper electrode layer 206 in FIG. 2f. The resonator 301 and the fixed part 303 are connected through the support beam 302 and are suspended in the cavity. In FIG. 3 , the MEMS resonator includes four support beams 302 . It should be understood that the support beam shown in FIG. 3 is only a schematic representation. In practical applications, the number of support beams may be one or more. Moreover, the support beams may be straight beams, T-shaped beams, or cross beams, and the like.

In step 106, the resonator is sealed.

In the aforementioned step 105 , the resonator is obtained by etching the device layer 203 . In order to reduce the air damping loss of the resonator during operation, the resonator in the MEMS resonator is vacuum packaged. The packaging method includes, but is not limited to, epitaxial growth of the upper cavity wall, bonding of the upper cavity wall, and the like. The sealed resonator will be described below as an example of epitaxially growing the upper cavity wall.

After the harmonic oscillator is obtained by etching the device layer 203, a sacrificial layer is deposited on the harmonic oscillator. The sacrificial layer is etched, and a barrier layer is epitaxially grown on the sacrificial layer so that the resonator is in the region where the barrier layer and the substrate are formed. Vias are etched on the barrier layer. Hydrofluoric acid vapor is injected through the vent hole to corrode the sacrificial layer in the region formed by the barrier layer and the substrate, so that the resonator is suspended in the cavity through the support beam. A sealing layer is epitaxially grown on the barrier layer to seal the vent holes. At this time, the barrier layer acts as the upper cavity wall of the MEMS resonator.

In addition to sealing the resonator, electrical connections also need to be made. Electrical connections require conductive structures. The conductive structure includes an upper electrode conductive structure and a lower electrode conductive structure. The upper electrode conductive structure and the lower electrode conductive structure are used to provide excitation for the resonator, so that the resonator vibrates in the cavity. The present application does not limit the positions and shapes of the upper electrode conductive structure and the lower electrode conductive structure. In the present application, the upper electrode conductive structure is connected to the upper electrode layer 206 of the resonator, and the lower electrode conductive structure and the resonator have various electrical connection modes. According to the above description, the buffer layer 204 may include one or more buffer sub-layers. The following descriptions are made respectively.

When the buffer layer 204 includes one buffer sublayer, the buffer layer 204 may not serve as the lower electrode layer, and the buffer layer 204 may serve as the lower electrode layer of the resonator alone, or together with the device layer 203 as the lower electrode layer of the resonator. When the buffer layer 204 is not used as the lower electrode layer, the lower electrode conductive structure is connected to the device layer 203 . The lower electrode conductive structure provides excitation for the resonator through the device layer 203 . When the buffer layer 204 alone serves as the lower electrode layer of the resonator, the conductive structure of the lower electrode is connected to the buffer layer 204 of the resonator. The lower electrode conductive structure provides excitation for the resonator through the buffer layer 204 . When the buffer layer 204 and the device layer 203 together serve as the lower electrode layer of the resonator, the conductive structure of the lower electrode is connected to the buffer layer 204 and the device layer 203 of the resonator at the same time. The lower electrode conductive structure provides excitation for the resonator through the buffer layer 204 and the device layer 203 .

When the buffer layer 204 includes a plurality of buffer sublayers, the buffer sublayer closest to the piezoelectric layer 205 is referred to as the first buffer sublayer. When the plurality of buffer sublayers are all conductive materials, the plurality of buffer sublayers can be regarded as one buffer layer. At this time, the electrical modes of the conductive structure of the lower electrode and the resonator are similar to those described above when the buffer layer 204 includes one buffer sublayer. When the first buffer sub-layer is made of conductive material and other buffer sub-layers have non-conductive materials, the first buffer sub-layer can be used alone as the lower electrode layer of the resonator. At this time, the conductive structure of the lower electrode is connected to the first buffer sublayer. The lower electrode conductive structure provides excitation for the resonator through the first buffer sublayer.

It should be understood that the above-described fabrication methods for MEMS resonators are only one or more examples. In practical applications, because those skilled in the art are familiar with the steps and/or components in the processing method, those skilled in the art can make adaptive changes to the steps in the above-mentioned processing method or the structure of the MEMS resonator.

For example, to pattern the piezoelectric layer 205 after the piezoelectric layer 205 is deposited. In the aforementioned step 103, by etching the piezoelectric layer 205, the opening 1 and the opening 2 are formed. In practical applications, the step of etching the piezoelectric layer 205 may be performed after depositing the upper electrode layer 206 . Specifically, the piezoelectric layer 205 may be etched in step 106 .

For example, the mode of the MEMS resonator in this application is a resonance mode. Resonant modes include width extension mode (SE mode), length extension mode (LE mode) and breathing mode, etc. The harmonic oscillator shown in Fig. 3 is a rectangle of the SE mode. The harmonic oscillator may also be a rectangle in the LE mode, a square in the LE mode or in the SE mode, a circular ring in the breathing mode, or the shape of an interdigitated electrode in the breathing mode, and the like.

For example, in the aforementioned step 103, by etching the piezoelectric layer 205, the opening 1 and the opening 2 are formed. At this time, the piezoelectric layer 205 is divided into two parts. The first part is the piezoelectric layer 205 between the opening 1 and the opening 2, and the second part is other regions. In the technique of epitaxially growing the upper cavity wall, the piezoelectric layer 205 of the second portion can be used to achieve electrical isolation of the upper cavity wall and the device layer 203 . In practical applications, when the piezoelectric layer 205 is etched in step 103, the second part of the piezoelectric layer 205 may also be etched away. In the subsequent process, the corresponding electrical isolation function is implemented by epitaxially growing a sacrificial layer or an electrical isolation layer in the device layer 203 .

For example, the device layer 203 does not serve as the lower electrode layer of the resonator, and the resonator also includes a separate lower electrode layer. Specifically, before depositing the piezoelectric layer 205, a metal is deposited on the buffer layer 204 as a lower electrode layer of the resonator, and the metal includes molybdenum, platinum, titanium, aluminum, and the like. At this time, in the subsequent electrical connection process, the conductive structure is connected to the lower electrode layer. The conductive structure provides excitation for the resonator through the lower electrode layer.

At this time, the material of the buffer layer 203 may not only be a conductive material, but also a non-conductive material. The non-conductive material may be silicon nitride (Si3N4), diamond (Diamond (100)), or the like. When the buffer layer 203 includes a plurality of buffer sublayers, and the materials of the plurality of buffer sublayers include silicon germanium, gallium arsenide, silicon nitride, diamond and germanium, the buffer layer 204 includes five buffer sublayers. In the direction from the device layer 203 to the piezoelectric layer 205, the order of the five buffer sub-layers is the order of the temperature material coefficient from low to high. Specifically, the deposition sequence of the five buffer sublayers may be silicon germanium, gallium arsenide, silicon nitride, diamond, and germanium. Alternatively, the deposition sequence of the five buffer sublayers may be gallium arsenide, silicon germanium, silicon nitride, diamond, germanium. Alternatively, alternatively, the deposition sequence of the five buffer sublayers may be gallium arsenide, silicon nitride, silicon germanium, diamond, germanium. Alternatively, the deposition sequence of the five buffer sublayers may be gallium arsenide, silicon nitride, diamond, silicon germanium, germanium.

At this time, during the electrical connection process, the upper electrode conductive structure is connected to the upper electrode layer 206 of the resonator, and the lower electrode conductive structure can be connected to the lower electrode layer. The conductive structure provides excitation for the resonator through the upper electrode layer 206 and the lower electrode layer.

The processing method of the MEMS resonator in the present application has been described above. The MEMS resonator in this application is a multi-layer composite structure in the vertical direction. The vertical direction is the Y-axis direction in Figure 2f. The multilayer composite structure includes an upper electrode layer 206 , a piezoelectric layer 205 and a device layer 203 . In the process of the resonator vibrating in the cavity with excitation, a thermal gradient exists between the device layer 203 and the piezoelectric layer 205, and the thermal gradient is distributed in the vertical direction. Thermal gradients cause thermoelastic losses. To reduce thermoelastic losses, isolation trenches may be etched between piezoelectric layer 205 and device layer 203 . Isolation trenches are used to isolate heat flow between piezoelectric layer 205 and device layer 203 . However, in the processing flow of the MEMS resonator, it is difficult to perform the side etching process. Therefore, the present application adds a buffer layer 204 between the piezoelectric layer 205 and the device layer 203 . The buffer layer 204 can reduce the heat flow between the piezoelectric layer 205 and the device layer 203, reduce the thermoelastic loss of the MEMS resonator, and thereby improve the Q value. Moreover, the process of adding the buffer layer in the vertical direction is simpler than etching the isolation trenches on the side. Therefore, the present application can reduce the difficulty of the process.

The MEMS resonator in this application is described below. FIG. 4 is a schematic structural diagram of the MEMS resonator provided in this application. As shown in FIG. 4 , the MEMS resonator includes a fixed part 401 , a resonator 402 and a support beam (not shown in the figure). The resonator 402 is connected with the fixed part 401 through the support beam. The resonator 402 includes a device layer 403 , a piezoelectric layer 405 and an upper electrode layer 406 . A buffer layer 404 is provided between the piezoelectric layer 405 and the device layer 403 . The temperature coefficient of material between the piezoelectric layer 405 , the buffer layer 404 and the device layer 403 varies in a gradient. Specifically, the material temperature coefficient of the piezoelectric layer 405 is greater than the material temperature coefficient of the buffer layer 404 , and the material temperature coefficient of the buffer layer 404 is greater than the material temperature coefficient of the device layer 403 .

The MEMS resonator in FIG. 4 may refer to the aforementioned FIGS. 2 a to 2 f , or the MEMS resonator in FIG. 3 . For example, the fixing member 401 can refer to the substrate 201, the silicon oxide layer 202, the device layer 203 (excluding the device layer 203 between the openings 3 and 4), the piezoelectric layer 205 (excluding the openings 3 and 4), and the piezoelectric layer 205 in the aforementioned FIG. 2f Piezoelectric layer 205 between openings 4). The resonator 402 and the support beam may refer to the aforementioned resonator 301 and the support beam 302 in FIG. 3 .

In other embodiments, the material of the buffer layer 404 is germanium. Wherein, when the material of the piezoelectric layer is aluminum nitride, the material temperature coefficient of the piezoelectric layer is about 1.11. When the material of the device layer is single crystal silicon, the material temperature coefficient of the device layer is about 0.337. The material temperature coefficient of germanium is about 0.767. Therefore, the material temperature coefficient of germanium is approximately equal to the intermediate value of the material temperature coefficient of the device layer and the material temperature coefficient of the piezoelectric layer. The median value is equal to 0.7235. Therefore, the present application can further reduce the heat flow between the piezoelectric layer and the device layer, and reduce the thermoelastic loss of the MEMS resonator. It should be understood that the above material temperature coefficients are dimensionless values. In practical applications, the unit of the material temperature coefficient can be calculated according to the aforementioned formula for obtaining the material temperature coefficient W.

In the present application, the piezoelectric layer 405 is defined, and the temperature coefficient of the material between the buffer layer 404 and the device layer 403 changes in a gradient, thus defining the selectable range of the material of the buffer layer 404 . Moreover, when the device layer 403 is used as the lower electrode layer of the resonator, in order to improve the working efficiency of the resonator, the buffer layer 404 needs to be a conductive material. Therefore, the present application may add a lower electrode layer between the buffer layer 404 and the piezoelectric layer 405 . At this time, the buffer layer may be a non-conductive material. FIG. 5 is a schematic structural diagram of the harmonic oscillator provided in this application. As shown in FIG. 5 , the resonator includes a device layer 403 , a buffer layer 404 , a lower electrode layer 501 , a piezoelectric layer 405 , and an upper electrode layer 406 . When the buffer layer 404 is a non-conductive material, the lower electrode structure can provide excitation for the resonator through the lower electrode layer 501 . When the buffer layer 404 is a conductive material, the lower electrode structure can provide excitation for the resonator through any one or more layers of the device layer 403 , the buffer layer 404 , and the lower electrode layer 501 .

In this case, in order to further reduce the thermoelastic loss. The lower electrode layer 501 can also be used as a buffer layer. The temperature coefficient of the material between the piezoelectric layer 405, the lower electrode layer 501, the buffer layer 404 and the device layer 403 varies in a gradient. Specifically, the material temperature coefficient of the piezoelectric layer 405 is greater than that of the lower electrode layer 501 ; the material temperature coefficient of the lower electrode layer 501 is greater than that of the buffer layer 404 ; the material temperature coefficient of the buffer layer 404 is greater than that of the device layer 403 Material temperature coefficient.

In other embodiments, the lower electrode layer may not be added by adding the lower electrode layer 501 . Specifically, as shown in FIG. 4 , the buffer layer 404 serves as the lower electrode layer.

In the present application, the buffer layer 404 may include multiple buffer sublayers. Wherein, along the direction from the device layer to the piezoelectric layer, the material temperature coefficients of the plurality of buffer sub-layers gradually increase. FIG. 6 is another schematic structural diagram of the harmonic oscillator provided in this application. As shown in FIG. 6 , the resonator includes a device layer 403 , a buffer layer 404 , a piezoelectric layer 405 , and an upper electrode layer 406 . The buffer layer 404 includes a plurality of buffer sublayers. When the material of the plurality of buffer sub-layers includes gallium arsenide, silicon germanium and germanium. The buffer layer 404 includes three buffer sublayers. By adjusting the ratio of silicon and germanium in silicon germanium, silicon germanium with different temperature material coefficients can be obtained. At this time, the SiGe may be in different positions in the 3 buffer sublayers. Specifically, the deposition sequence of the three buffer sublayers may be silicon germanium, gallium arsenide, and germanium. Alternatively, the deposition sequence of the three buffer sublayers may be GaAs, SiGe, and Ge. Alternatively, alternatively, the deposition sequence of the three buffer sublayers may be GaAs, Ge, SiGe.

In the case where the buffer layer 404 may include a plurality of buffer sub-layers, the resonator may increase the material selection range of the buffer layer 404 by adding a lower electrode layer. For example, the material of the buffer layer 404 can also be silicon nitride or diamond. FIG. 7 is another schematic structural diagram of the harmonic oscillator provided in this application. As shown in FIG. 7 , the resonator includes a device layer 403 , a buffer layer 404 , a lower electrode layer 501 , a piezoelectric layer 405 , and an upper electrode layer 406 . The buffer layer 404 includes a plurality of buffer sublayers. When the materials of the plurality of buffer sublayers include silicon germanium, gallium arsenide, silicon nitride, diamond and germanium, the buffer layer 404 includes five buffer sublayers. The deposition sequence of the five buffer sub-layers can be silicon germanium, gallium arsenide, silicon nitride, diamond, germanium. Alternatively, the deposition sequence of the five buffer sublayers may be gallium arsenide, silicon germanium, silicon nitride, diamond, germanium. Alternatively, alternatively, the deposition sequence of the five buffer sublayers may be gallium arsenide, silicon nitride, silicon germanium, diamond, germanium. Alternatively, the deposition sequence of the five buffer sublayers may be gallium arsenide, silicon nitride, diamond, silicon germanium, germanium.

In other embodiments, when the thickness of the buffer layer is too large, other losses (eg, anchor losses) are increased, resulting in a decrease in the Q of the resonator. When the thickness of the buffer layer is small, the thermal insulation function of the buffer layer is reduced, and the Q value of the resonator cannot be improved. To this end, the present application defines the thickness of the buffer layer to be 0.1 micrometers to 10 micrometers. FIG. 8 is a schematic diagram of the relationship between the Q value of the MEMS resonator and the thickness of the buffer layer provided in this application. As shown in FIG. 8 , the abscissa of FIG. 8 is the thickness of the buffer layer, and the unit is micrometer. The buffer layer is germanium. The ordinate of FIG. 8 is the Q value. As shown in Figure 8, as the thickness of the buffer layer changes, the Q value of the MEMS resonator also changes. When the thickness of the buffer layer is 6 microns, the Q value of the MEMS resonator is the highest. Further, the thickness of the buffer layer is smaller than the thickness of the device layer.

In other embodiments, the junction of the substrate and the upper cavity wall includes a conductive layer. As shown in Fig. 2f. The fixed part of the MEMS resonator includes the substrate 201 and the device layer 203 of the second part (excluding the device layer 203 between the opening 3 and the opening 4). The MEMS resonator also includes an upper cavity wall, and the region between the upper cavity wall and the substrate is a cavity. Wherein, the junction of the upper cavity wall and the substrate includes the second part of the device layer 203 . The device layer 203 of the second part is connected to the device layer 203 of the first part of the resonator through the support beam. When the first part of the device layer 203 serves as the lower electrode layer of the resonator, the second part of the device layer 203 serves as the conductive layer. In the electrical connection, the conductive structure of the lower electrode is connected to the device layer 203 of the first part through the conductive layer. The conductive layer and the device layer have the same thickness.

In other embodiments, a silicon oxide layer is further included over the substrate. As shown in Figure 2f, the MEMS resonator further includes a silicon oxide layer 202 between the substrate 201 and the device layer 203. The silicon oxide layer 202 is used to isolate the electrical connection between the substrate 201 and the conductive layer. The conductive layer is the first part of the device layer 203 .

It should be understood that the aforementioned FIG. 1 and FIG. 2a to FIG. 2f illustrate various processing methods of the MEMS resonator. A variety of fabrication methods can yield the MEMS resonators provided in this application. Therefore, in practical applications, there are more processing methods to obtain the MEMS resonator provided in this application. The processing methods listed in this application are only specific examples of many processing methods. Therefore, the aforementioned processing method of the MEMS resonator can be used as a reference for the MEMS resonator provided in this application, and should not be regarded as a limitation.

The MEMS resonators provided in this application were previously described. As shown in FIG. 4 , in the present application, the resonator of the MEMS resonator includes a buffer layer 404 . The buffer layer 404 is between the device layer 403 and the piezoelectric layer 405 . In the working engineering of the resonator, a thermal gradient exists between the device layer 403 and the piezoelectric layer 405 . Thermal gradients cause thermoelastic losses in the MEMS resonator, reducing the Q value. The buffer layer 404 can reduce the heat flow between the piezoelectric layer 405 and the device layer 403, reduce the thermoelastic loss of the MEMS resonator, and thus improve the Q value.

Specifically, FIG. 9 is a schematic diagram of the relationship between the Q value of the MEMS resonator and the thickness of the lower electrode layer provided in this application. As shown in FIG. 9 , the abscissa of FIG. 9 is the thickness of the lower electrode layer, and the unit is micrometer. The lower electrode layer is a buffer layer and a device layer. The material of the device layer is silicon, and the material of the buffer layer is germanium. The ordinate of FIG. 9 is the Q value. The device layer that does not include the buffer layer in the MEMS resonator is referred to as the first lower electrode layer, and the device layer and the buffer layer that include the buffer layer in the MEMS resonator are referred to as the second lower electrode layer. As the thicknesses of the first lower electrode layer and the second lower electrode layer increase, the Q value of the MEMS resonator increases continuously. However, in the case where the thicknesses of the first lower electrode layer and the second lower electrode layer are the same, the Q value of the MEMS resonator including the buffer layer is higher. Therefore, it is beneficial to increase the Q value of the MEMS resonator by adding a buffer layer between the device layer 403 and the piezoelectric layer 405 without increasing the volume of the resonator.

The clock device in this application is described below. FIG. 10 is a schematic structural diagram of the clock device provided in this application. As shown in FIG. 10 , the clock device includes a MEMS resonator 1001 and a holding circuit 1002 . Holding circuit 1002 provides closed-loop oscillatory excitation for MEMS resonator 1001 . The MEMS resonator 1001 generates a clock signal by oscillating excitation. For the MEMS resonator 1001, reference may be made to the MEMS resonator provided in the foregoing application.

The clock device provided in this application is described above, and the terminal in this application is described below. FIG. 11 is a schematic structural diagram of a terminal provided in this application. The terminal can be a mobile phone, a computer, a base station, etc. As shown in FIG. 11 , the terminal 1103 includes a clock device 1101 and a processor 1102 . The clock device 1101 is used to provide the processor 1102 with a clock signal. The processor 1102 performs arithmetic processing according to the clock signal.

The processor 1102 may be a central processing unit (CPU), a network processor (NP), or a combination of CPU and NP. The processor 1101 may further include hardware chips or other general-purpose processors. The above-mentioned hardware chip may be an application specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof.

The clock device 1101 may be a MEMS clock device. Specifically, the clock device 1101 may refer to the aforementioned clock devices provided in this application.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, and should cover within the scope of protection of this application.

Claims

A microelectromechanical MEMS resonator, characterized in that it comprises:

Fixed parts, harmonic oscillators and support beams;

the resonator is connected with the fixed part through the support beam;

The resonator includes an upper electrode layer, a piezoelectric layer and a device layer, and the piezoelectric layer is between the upper electrode layer and the device layer;

A buffer layer is arranged between the piezoelectric layer and the device layer;

The material temperature coefficient of the piezoelectric layer is greater than the material temperature coefficient of the buffer layer, and the material temperature coefficient of the buffer layer is greater than the material temperature coefficient of the device layer;

Among them, the material temperature coefficient
α is the coefficient of thermal expansion, E is Young's modulus, ρ is mass density, C is specific heat capacity, and v is Poisson's ratio.
The MEMS resonator of claim 1, wherein a lower electrode layer is included between the piezoelectric layer and the device layer;

Wherein, the buffer layer is between the lower electrode layer and the device layer.
The MEMS resonator of claim 2, wherein the buffer layer is a non-conductive material.
The MEMS resonator according to claim 2 or 3, wherein the material temperature coefficient of the lower electrode layer is greater than the material temperature coefficient of the buffer layer, and the material temperature coefficient of the lower electrode layer is smaller than that of the piezoelectric The material temperature coefficient of the layer.
The MEMS resonator according to any one of claims 1 to 4, wherein the material of the buffer layer is germanium.
The MEMS resonator according to any one of claims 1 to 4, wherein the buffer layer comprises a plurality of buffer sublayers;

Wherein, along the direction from the device layer to the piezoelectric layer, the material temperature coefficients of the plurality of buffer sub-layers gradually increase.
The MEMS resonator according to claim 6, wherein the material of at least one buffer sublayer in the plurality of buffer sublayers is silicon germanium.
The MEMS resonator according to claim 7, wherein the material of the plurality of buffer sublayers further comprises any one or more of gallium arsenide, silicon nitride, diamond or germanium, and each material corresponds to A buffer sublayer of the plurality of buffer sublayers.
The MEMS resonator according to claim 7 or 8, characterized in that, along the direction from the device layer to the piezoelectric layer,

The materials of the plurality of cache sub-layers are silicon germanium, gallium arsenide, silicon nitride, diamond, germanium; or,

The materials of the multiple cache sub-layers are gallium arsenide, silicon germanium, silicon nitride, diamond, germanium; or,

The materials of the plurality of cache sub-layers are gallium arsenide, silicon nitride, silicon germanium, diamond, germanium; or,

The materials of the plurality of cache sub-layers are gallium arsenide, silicon nitride, diamond, silicon germanium, germanium in sequence.
The MEMS resonator according to claim 1, wherein the buffer layer serves as a lower electrode layer of the resonator.
The MEMS resonator according to any one of claims 1 to 10, wherein the thickness of the buffer layer is smaller than the thickness of the device layer.
The MEMS resonator according to any one of claims 1 to 11, wherein the buffer layer has a thickness of 0.1 μm to 10 μm.
The MEMS resonator according to any one of claims 1 to 12, wherein the fixed part comprises a substrate and an upper cavity wall;

A cavity is formed between the substrate and the upper cavity wall;

Wherein, the resonator is suspended from the cavity through the support beam.
The MEMS resonator of claim 13, wherein the junction of the substrate and the upper cavity wall comprises a conductive layer;

Wherein, the thickness of the conductive layer and the device layer are the same.
The MEMS resonator according to claim 14, wherein the upper part of the substrate comprises a silicon oxide layer;

Wherein, the silicon oxide layer is used to isolate the electrical connection between the substrate and the conductive layer.
A method for processing a microelectromechanical MEMS resonator, comprising:

Provide silicon-on-insulator SOI wafers including substrate and device layers;

depositing a buffer layer on the device layer;

depositing a piezoelectric layer on the buffer layer;

depositing an upper electrode layer on the piezoelectric layer;

etching the device layer to form a resonator and a support beam;

sealing the resonator by the upper cavity wall;

Wherein, the material temperature coefficient of the piezoelectric layer is greater than the material temperature coefficient of the buffer layer, and the material temperature coefficient of the buffer layer is greater than the material temperature coefficient of the device layer;

Material temperature coefficient
α is the coefficient of thermal expansion, E is Young's modulus, ρ is mass density, C is specific heat capacity, and v is Poisson's ratio.
A clock device, characterized in that it comprises a microelectromechanical MEMS resonator and a holding circuit;

the holding circuit is used to provide closed-loop oscillation excitation for the MEMS resonator;

the MEMS resonator generates a clock signal by the oscillation excitation;

Wherein, the MEMS resonator is the MEMS resonator described in any one of the preceding claims 1 to 15 .
A terminal, characterized by comprising the clock device and the processor of claim 17;

the clock device is used to provide a clock signal for the processor;

The processor is configured to perform arithmetic processing according to the clock signal.