WO2022204969A1

WO2022204969A1 - Transceiver and electronic device

Info

Publication number: WO2022204969A1
Application number: PCT/CN2021/084066
Authority: WO
Inventors: 周佳
Original assignee: 华为技术有限公司
Priority date: 2021-03-30
Filing date: 2021-03-30
Publication date: 2022-10-06
Also published as: CN116848770A

Abstract

The present application provides a transceiver and an electronic device. The transceiver comprises: a power supply circuit and a load circuit, wherein the load circuit comprises at least one of a transmission channel and a receiving channel, the transmission channel comprising at least one load device from among a digital-to-analog converter, a mixer, a filter and a power amplifier, the receiving channel comprising at least one load device from among a low-noise amplifier, a mixer, a filter and an analog-to-digital converter, and the transmission channel and the receiving channel being used for working in a time division duplex mode; the power supply circuit comprises a bias circuit, a filter circuit, a power line and a bias voltage line; the load circuit is respectively coupled to the power line and the bias voltage line; the bias circuit is coupled to the bias voltage line and is used for outputting a bias voltage to the bias voltage line; and the filter circuit is coupled between the bias circuit and the load circuit, and is used for filtering the bias voltage and a power source voltage provided by the power line, and providing the filtered power source voltage and the filtered bias voltage to the load circuit. By means of the present application, the working performance of a power supply circuit can be improved.

Description

Transceivers and Electronics

technical field

The present application relates to communication technology, and in particular, to a transceiver and an electronic device.

Background technique

In communication circuits, the startup and shutdown of circuit modules is an important design feature. In order to save power consumption, the circuit of the corresponding link can be put to sleep in the non-working time slot, and its circuit can be restarted in the working time slot. However, the performance of the start-up circuit needs to be improved.

SUMMARY OF THE INVENTION

The present application provides a transceiver, a power supply circuit and an electronic device, which are used to improve the working performance of the power supply.

In a first aspect, the present application provides a transceiver, including: a power supply circuit and a load circuit, the load circuit includes at least one of a transmit channel and a receive channel; wherein the transmit channel includes a digital-to-analog converter, a mixer , at least one load device in a filter and a power amplifier, the receiving channel includes at least one load device in a low noise amplifier, a mixer, a filter and an analog-to-digital converter, and the transmitting channel and the receiving channel use working in a time division duplex mode; the power supply circuit includes a bias circuit, a filter circuit, a power supply line and a bias voltage line; the load circuit is respectively coupled with the power supply line and the bias voltage line; the A bias circuit is coupled to the bias voltage line for outputting a bias voltage to the bias voltage line; the filter circuit is coupled between the bias circuit and the load circuit for outputting a bias voltage to the bias voltage line; The bias voltage and the power supply voltage provided by the power supply line are filtered, and the filtered power supply voltage and the bias voltage are provided to the load circuit.

In the embodiment of the present application, a filter circuit is provided, and the filter circuit is used to filter the bias voltage provided by the bias circuit and the power supply voltage provided by the power supply line, so as to filter out the noise of the bias voltage and the noise of the power supply voltage, thereby improving the input to the load. The reliability of each voltage signal of the circuit is beneficial to improve the signal transmission quality of the transceiver.

In a possible implementation manner, the load circuit includes at least one first transistor; a source of the at least one first transistor is coupled to the power supply line, and a drain of the at least one first transistor is coupled to the load The power supply terminal of at least one load device in the circuit is correspondingly coupled; the gate of the at least one first transistor is coupled to the bias voltage line.

By arranging the first transistor, the power supply circuit can supply power to the load device or stop the power supply, and each load device can be connected or disconnected from the power source by controlling the transistor to be turned on or off. The source of the first transistor is coupled to the power supply line, that is, connected to a high potential, and the gate is coupled to the bias voltage line. When the potential of the gate becomes low (the voltage of the bias voltage line is lower than the voltage of the power supply line), the first transistor conducts. is turned on, the high potential of the source flows to the drain through the transconductance between the source and the drain, so that the load device coupled with the first transistor will start to work; when the potential of the gate becomes high (the bias voltage line When the voltage is higher than the voltage of the power line), the first transistor is turned off, so that the load device coupled with the first transistor stops working.

In a possible implementation, the bias circuit includes a second transistor; the source of the second transistor is coupled to the power supply line, and the drain of the second transistor is coupled to the bias voltage line .

The source of the second transistor is coupled to the power line, ie, connected to a high potential, to provide a bias voltage through the second transistor.

In one possible implementation, the bias circuit further includes a current source coupled in series between the drain of the second transistor and the common ground.

In the embodiment of the present application, the current source is used to provide current to the second transistor.

In a possible implementation manner, the bias circuit further includes a third transistor; the source of the third transistor is coupled with the drain of the second transistor; the drain of the third transistor passes through the A current source is coupled to common ground; the gate of the third transistor is coupled to the drain of the third transistor.

In a possible implementation manner, the bias circuit further includes a first resistor; a first end of the first resistor is coupled to the drain of the second transistor; a second end of the first resistor passes through The current source is coupled to common ground; the gate of the second transistor is coupled to the second end of the first resistor.

In a possible implementation manner, the power supply circuit further includes a driving circuit, and the driving circuit is coupled to the bias circuit and the bias voltage line; the driving circuit is configured to obtain the bias circuit from the bias circuit. A bias voltage is supplied to the bias voltage line.

By setting the driving circuit in the embodiment of the present application, the isolation between the bias circuit and the first transistor can be realized, the change of the gate potential of the second transistor caused by the charge released by the gate of the first transistor can be avoided, and the bias circuit can be improved. In addition, the drive circuit is also used to extract the charge from the gate of the first transistor when the first transistor is turned from the off state to the on state to improve the charge release speed and reduce the load device from the power-down state to stable. The duration of the working state.

The driving circuit provided in the embodiments of the present application may include various implementation manners.

Mode 1: when the bias circuit includes the second transistor and the third transistor, the drive circuit includes a fourth transistor and a fifth transistor; the source of the fourth transistor is connected to the power supply line coupled; the drain of the fourth transistor is coupled to the source of the fifth transistor; the drain of the fifth transistor is coupled to common ground; the drain of the fourth transistor and the drain of the fifth transistor The source is coupled to the bias voltage line; the gate of the fourth transistor is coupled to the gate of the second transistor; and the gate of the fifth transistor is coupled to the gate of the third transistor.

Based on the first manner, in a possible implementation manner, the driving circuit further includes a first switch; the drain of the fifth transistor is coupled to a common ground through the first switch.

Mode 2: In the case where the bias circuit includes the second transistor and the first resistor, the drive circuit includes an operational amplifier; the inverting input terminal of the operational amplifier and the output terminal of the operational amplifier coupling; the output terminal of the operational amplifier is coupled to the bias voltage line; the non-inverting input terminal of the operational amplifier is coupled to the gate of the second transistor.

In a possible implementation manner, the filter circuit includes a capacitor and a second resistor; wherein a first end of the capacitor is coupled to a gate of the first transistor, and a second end of the capacitor is coupled to the gate of the first transistor. The power line is coupled; the first end of the second resistor is coupled with the first end of the capacitor; the second end of the second resistor is coupled to the gate of the second transistor.

In a possible implementation manner, when the power supply circuit includes the filter circuit, the power supply circuit further includes a short circuit; the short circuit includes a second switch; the second switch and the second resistor are connected in parallel.

By setting the short circuit, the filter circuit can be short-circuited in the initial stage when the first transistor is turned from the off state to the on state, so that the charge on the gate of the first transistor can be quickly released to the common ground through the bias circuit or the drive circuit , to speed up the release speed of the gate charge of the first transistor, which is beneficial to shorten the transition time of the first transistor from the off state to the on state, thereby shortening the time for the transceiver to change from the sleep state to the stable working state, and improving the performance of the transceiver .

In a possible implementation manner, the power supply circuit further includes a control circuit; the control circuit is configured to control the second switch to be turned on or off.

The control circuit provided by the embodiments of the present application may include various implementation manners.

Mode 1: The control circuit includes a delay, a first inverter, a second inverter, an AND gate and an XOR gate; wherein,

The input end of the delay device is used for inputting the first signal, the output end of the delay device is coupled with the first input end of the AND gate; the second input end of the AND gate is used for inputting the first signal ; The output end of the AND gate is coupled with the first input end of the XOR gate; the input end of the first inverter is used to input the first signal; the input end of the second inverter is coupled with the output end of the first inverter; the output end of the second inverter is coupled with the second input end of the XOR gate; the output end of the XOR gate is used to output a control signal, to control the second switch to be turned on or off.

Mode 2: the control circuit includes a comparator and an AND gate; wherein the first input terminal of the comparator is used to input a first voltage; the second input terminal of the comparator is coupled to the gate of the first transistor pole; the output end of the comparator is coupled with the first input end of the AND gate; the second input end of the AND gate is used to input the first signal; the output end of the AND gate is used to output the control signal, to control the second switch to be turned on or off.

In a possible implementation manner, the power supply circuit further includes a third switch; one end of the third switch is coupled to the power supply line, and the other end of the third switch is connected to the gate of the first transistor coupling.

By setting the third switch, when the load device needs to be powered, the third switch is turned off, the gate of the first transistor is coupled to the bias voltage line, and the second transistor provides the bias voltage to the first transistor through the bias voltage line; When the power supply to the load device is stopped, the third switch is turned on, the gate electrode and the source electrode of the first transistor are both coupled to the power supply line, and the first transistor is turned off.

In a possible implementation manner, the power supply circuit further includes a fourth switch; one end of the fourth switch is coupled to the power supply line, and the other end of the fourth switch is connected to the gate of the second transistor Extremely coupled.

By setting the fourth switch, when each load device coupled with the bias circuit is in an idle state, the fourth switch is turned on, and the bias circuit is powered off; when each load device coupled with the bias circuit is in the working state, The fourth switch is turned off, and the bias circuit is powered on to provide a bias voltage to the bias voltage line.

In a possible implementation manner, the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are P-channel metal oxide semiconductors.

In a possible implementation manner, the operational amplifier is a unipolar operational amplifier or a multi-stage operational amplifier; wherein, the unipolar operational amplifier includes a five-tube structure amplifier, a symmetrical transconductance amplifier, a sleeve type or a folded cascode.

In a second aspect, the present application provides a transceiver, including: a power supply circuit and a load circuit, the load circuit includes at least one of a transmit channel and a receive channel; wherein the transmit channel includes a digital-to-analog converter, a mixer , at least one load device in a filter and a power amplifier, the receiving channel includes at least one load device in a low noise amplifier, a mixer, a filter and an analog-to-digital converter, and the transmitting channel and the receiving channel use working in a time division duplex mode; the power supply circuit includes a bias circuit, a drive circuit, a power supply line and a bias voltage line; the load circuit is respectively coupled with the power supply line and the bias voltage line; the The power supply line is used for supplying the power supply voltage to the power supply circuit; the driving circuit is coupled with the bias circuit and the bias voltage line; the driving circuit is used for obtaining the mirrored bias voltage from the bias circuit , the bias voltage is supplied to the load circuit through the bias voltage line.

In a possible implementation, the bias circuit further includes a current source coupled in series between the drain of the second transistor and the common ground.

In a possible implementation manner, the power supply circuit further includes a filter circuit, the filter circuit is coupled between the drive circuit and the load circuit, and is used to provide the bias voltage and the power supply line The power supply voltage is filtered, and the filtered power supply voltage and the bias voltage are provided to the load circuit.

In a third aspect, embodiments of the present application provide a power supply circuit, where the power supply circuit includes the power supply circuit described in any one of the first aspect and the second aspect.

In a fourth aspect, the present application provides an electronic device, including a memory, a processor, and the transceiver according to any one of the first to third aspects above.

It should be understood that the second to fourth aspects of the present application are consistent with the technical solutions of the first aspect of the present application, and the beneficial effects obtained by each aspect and the corresponding feasible implementation manner are similar, and will not be repeated.

Description of drawings

1 is a schematic structural diagram of a transceiver provided by an embodiment of the present application;

FIG. 2 is a working sequence diagram of the transceiver as shown in FIG. 1 provided by an embodiment of the present application;

3 is another schematic structural diagram of a transceiver provided by an embodiment of the present application;

4 is a schematic structural diagram of a power supply circuit provided by an embodiment of the present application;

5 is another schematic structural diagram of a power supply circuit provided by an embodiment of the present application;

6 is another schematic structural diagram of a power supply circuit provided by an embodiment of the present application;

7 is another schematic structural diagram of a power supply circuit provided by an embodiment of the present application;

8 is another schematic structural diagram of a power supply circuit provided by an embodiment of the present application;

9 is a schematic diagram of a control sequence of the power supply circuit shown in FIG. 8 provided by an embodiment of the present application;

10 is another schematic structural diagram of a power supply circuit provided by an embodiment of the present application;

11 is a schematic structural diagram of a control circuit provided by an embodiment of the present application;

12 is another schematic structural diagram of a control circuit provided by an embodiment of the present application;

13 is another schematic structural diagram of a power supply circuit provided by an embodiment of the present application;

FIG. 14 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below with reference to the accompanying drawings in the present application. Obviously, the described embodiments are part of the embodiments of the present application. , not all examples. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

The terms "first", "second", etc. in the description, embodiments and claims of the present application and the drawings are only used for the purpose of distinguishing and describing, and should not be construed as indicating or implying relative importance, nor should they be construed as indicating or implied order. Furthermore, the terms "comprising" and "having" and any variations thereof, are intended to cover non-exclusive inclusion, eg, comprising a series of steps or elements. A method, system, product or device is not necessarily limited to those steps or units expressly listed, but may include other steps or units not expressly listed or inherent to the process, method, product or device.

It should be understood that, in this application, "at least one (item)" refers to one or more, and "a plurality" refers to two or more. "And/or" is used to describe the relationship between related objects, indicating that there can be three kinds of relationships, for example, "A and/or B" can mean: only A, only B, and both A and B exist , where A and B can be singular or plural. The character "/" generally indicates that the associated objects are an "or" relationship. "At least one item(s) below" or similar expressions thereof refer to any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (a) of a, b or c, can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c" ", where a, b, c can be single or multiple.

The transceiver 100 shown in the embodiments of the present application may be applied in various communication scenarios. The multiple scenarios may include but are not limited to 5G communication scenarios or frequency modulated continuous wave (Frequency Modulated Continuous Wave) radar detection scenarios.

Please refer to FIG. 1 , which is a schematic structural diagram of a transceiver provided by an embodiment of the present application. In FIG. 1, the transceiver 100 includes a power supply circuit 10, a transmit channel TS and a receive channel RS. The signal output end of the transmit channel TS is coupled to the transmit antenna TX, and the transmit channel TS is used for transmitting radio frequency signals through the transmit antenna TX. The signal input end of the receiving channel RS is coupled to the receiving antenna RX, and the receiving channel RS is used for receiving radio frequency signals from the receiving antenna RX. The transmit channel TS includes load devices such as digital-to-analog converters, mixers, filters, and power amplifiers; the receive channel RS includes load devices such as low-noise amplifiers, mixers, filters, and analog-to-digital converters. The power supply circuit 10 is used to supply power to a load circuit, and the load circuit includes at least one load device in the transmit channel TS and the receive channel RS. The power supply here can be understood as supplying power to the load device when the load device in the transmitting channel TS and the receiving channel RS is in a working state; when the load device is in an idle state, stop supplying power to the load device.

Based on the transmitter 100 shown in FIG. 1 , in this embodiment of the present application, the transmitter 100 may work in a time division duplex mode. At this time, the transmitter can use the same frequency band to transmit and receive signals in different time slots. For example, transmitter 100 transmits a signal in time slot T1, transmitter 100 neither transmits nor receives a signal in time slot T2, transmitter 100 receives a signal in time slot T3 . . . as shown in FIG. 2 . Based on the example shown in FIG. 2 , each load device in the transmit channel TS is in a working state in the time slot T1, and is in an idle state in the time slot T2 and time slot T3; each load device in the receive channel RS is in the time slot T1 and time slot T1. Slot T2 is in an idle state and is in an active state in time slot T3. Therefore, the power supply circuit 10 can supply power to each load device in the transmission channel TS in the time slot T1, stop supplying power to each load device in the transmission channel TS in the time slot T2 and the time slot T3, and in the time slot T1 and time slot T2 Stop supplying power to each load device in the receiving channel RS, and supply power to each load device in the receiving channel RS in the time slot T3. Since each load device in the transmit channel TS and the receive channel RS is usually a heavy load device, it has a large power consumption; when the load device is idle, it stops supplying power to the load device, which can make each load device enter a sleep state or a power-off state. This saves the power consumption of the transceiver.

In addition, the transmitter 100 may also operate in a frequency division duplex mode. At this time, the transmitter can use different frequency bands to transmit and receive signals in the same time slot. This working mode is not described again in this embodiment of the present application.

The transceiver 100 described in this embodiment of the present application may be an in-phase quadrature (IQ, In-phase Quadrature) transceiver, including multiple types of transceivers, for example, including but not limited to superheterodyne transceivers, direct conversion transceivers, or Low-IF transceivers, etc. Taking the direct-conversion transceiver as an example below, the transceiver 100 in the example of the application itself will be further described with reference to FIG. 3 . In FIG. 3 , the transmit channel TS includes two branches, each branch includes a digital-to-analog converter, a filter and a mixer, and the transmit channel TS also includes a power amplifier. One of the branches is used to receive the I1 signal, after digital-to-analog conversion and filtering, the I1 signal is mixed with the local oscillator signal to generate the first radio frequency signal; After conversion and filtering, it is mixed with the local oscillator signal to generate a second radio frequency signal. The first radio frequency signal and the second radio frequency signal are superimposed and input to the power amplifier, which is amplified by the power amplifier and then transmitted through the antenna TX. Wherein, the I1 signal and the Q1 signal are in-phase quadrature signals, and the I1 signal and the Q1 signal may be a fundamental frequency signal or an intermediate frequency signal. The receiving channel RS includes two branches, and each branch includes a mixer, a filter and an analog-to-digital converter. In addition, the receive path RS also includes a low noise amplifier. The receiving antenna RX amplifies the received signal by the low noise amplifier, and then separates the signal to generate a third radio frequency signal and a fourth radio frequency signal, which are respectively provided to the two branches. One of the branches uses the local oscillator signal to down-convert the third RF signal, and then goes through filter filtering and analog-to-digital conversion to obtain the I2 signal. The other branch uses the local oscillator signal to down-convert the fourth RF signal and then passes through the filter. After filtering and analog-to-digital conversion, the Q2 signal is obtained. The I2 signal and the Q2 signal are in-phase and quadrature signals, and the I2 signal and the Q2 signal can be a base frequency signal or an intermediate frequency signal. It should be noted that each transmit channel TS and receive channel RS of the transceiver 100 may also include more or less devices. For example, devices such as phase shifters, variable gain amplifiers, etc. may also be included. In addition, the front and rear positions of the components included in the transmission channel TS and the front and rear positions of the components included in the reception channel RS may be interchanged, which is not specifically limited in this embodiment of the present application. In the transceiver 100 shown in FIG. 3 , a local oscillator is also included, and the local oscillator is used to input a local oscillator signal to the mixers in the transmit channel TS and the receive channel RS. The local oscillator signal input to the transmit channel TS and the local oscillator signal input to the receive channel RS can be provided by the same local oscillator, the local oscillator signal input to the transmit channel TS and the local oscillator signal input to the receive channel RS. The vibration signal can also be provided by different local oscillators, and Fig. 3 schematically shows the situation provided by the same local oscillator.

In the embodiment of the present application, the power supply circuit 10 supplies power to the load device or stops the power supply by controlling the on or off of the transistor coupled to each load device. The transmitting channel RS and the receiving channel TS respectively include a plurality of transistors M0, wherein the number of the transistors M0 is the same as the number of the load devices to be powered. The following description will be made with reference to FIG. 4 by taking the transmit channel TS and the three load devices including the digital-to-analog converter, the mixer and the power amplifier as an example in the transmit channel TS. In FIG. 4, the emission channel TS includes three transistors M0, the first poles of the three transistors M0 are all coupled to the power supply line Vcc, and the second poles of the three transistors M0 are respectively coupled to the digital-to-analog converter, the mixer and the power supply terminal of the power amplifier. It can be seen from FIG. 4 that each load device can be connected to or disconnected from the power supply by controlling the transistor M0 to be turned on or off. Specifically, in the embodiment of the present application, the power supply circuit 10 includes a power supply line Vcc, a bias voltage line Vb, and a bias circuit 101, and the output terminal of the bias circuit 101 and the gate of the transistor M0 are both coupled to the bias voltage line Vb, The output terminal of the bias circuit 101 inputs a bias voltage to the gate of each transistor M0 via a bias voltage line Vb. Usually, the bias voltage output by the bias circuit 101 and the power supply voltage provided by the power supply line Vcc have noise. A filter circuit 102 is also provided between the transistors M0, and the filter circuit 102 is used to filter out the noise of the bias voltage output by the bias circuit 101 and the noise of the power supply voltage provided by the power supply line Vcc. In the embodiments of the present application, the transistor M0 may be a P-type metal-oxide-semiconductor (PMOS) field effect transistor, or may be an N-type metal-oxide-semiconductor (N type metal-oxide). -semiconductor, NMOS) field effect transistor, can also be a bipolar junction transistor (Bipolar Junction Transistor, BJT). The figure schematically shows the case where the transistor M0 is a PMOS transistor. At this time, the first electrode of the transistor M0 is the source electrode and the second electrode is the drain electrode. The remaining transistors will not be described in detail.

Based on the circuit structure shown in FIG. 4 and the principle of supplying power or stopping power supply to the load devices in the transmit channel TS and the receive channel RS, the following describes the power supply circuit 10 provided by the embodiments of the present application through the embodiments shown in FIGS. 5 to 11 . The structure and working principle are described in more detail.

Please refer to FIG. 5 , which is a schematic structural diagram of a power supply circuit 10 provided by an embodiment of the present application. In FIG. 5 , the power supply circuit 10 includes a bias circuit 101 and a filter circuit 102 . The bias circuit 101 includes a transistor M1, the first electrode of the transistor M1 is coupled to the power supply line Vcc, the second electrode and the gate of the transistor M1 are coupled to the common ground Gnd, and the gate of the transistor M0 and the gate of the transistor M1 are both coupled to the bias. Set the voltage line Vb. The gate of transistor M1 is coupled with the second pole to form a current mirror. Usually, the voltage output by the power line Vcc is a fixed value. In order to provide each load device with power suitable for the load device, the power supply circuit 10 can also adjust the output power by adjusting the current output by the second pole of the transistor M0. By setting the ratio between the physical size of the transistor M1 and the physical size of the transistor M0, an appropriate current can be output. The physical dimensions here may refer to the ratio of the width and length of the conduction channel of the transistor. In addition, the bias circuit 101 may also be provided with a current source I, and the current source I is used to supply current to the transistor M1. The transistor M1 may be one of an NMOS transistor, a PMOS transistor and a BJT. FIG. 5 schematically shows the case where the transistor M1 is a PMOS transistor. At this time, the first electrode of the transistor M1 is the source electrode, and the second electrode of the transistor M1 is the drain electrode. The filtering circuit 102 may be one of a low-pass filtering circuit, a high-pass filtering circuit and a band-pass filtering circuit. Preferably, the filter circuit 102 provided in this embodiment of the present application may be a low-pass filter circuit. FIG. 5 schematically shows a schematic structural diagram of the filter circuit 102 being a low-pass filter circuit. The filter circuit 102 may include a resistor R1 and a capacitor C1, the resistor R1 is connected in series on the bias voltage line Vb, that is, it is coupled in series between the gate of the transistor M0 and the gate of the transistor M1, and the capacitor C1 is coupled to the gate of the transistor M0 and the power line Vcc.

Based on the structure of the power supply circuit 10 shown in FIG. 5 , in order to realize the power supply or stop power supply to the load device by controlling the on or off of the transistor M0 as described in FIG. 4 , in a possible implementation manner, the power supply circuit 10 is also provided with a switch K1, which is coupled between the power supply line Vcc and the gate of the transistor M0. When it is necessary to supply power to the load device, the switch K1 is turned off, the gate of the transistor M0 is coupled to the gate of the transistor M1, and the transistor M1 provides a bias voltage to the transistor M0; when the power supply to the load device is stopped, the switch K1 is turned on, and the transistor M1 is turned on. The gate and source of M0 are both coupled to the power supply line Vcc, and the transistor M0 is turned off.

In order to further reduce the power consumption of the transmitter 100 shown in FIG. 1 and FIG. 3 , when each load device coupled to the bias circuit 101 is in an idle state, the bias circuit 101 may also enter a sleep state or a power-off state. Based on this, in a possible implementation manner, the power supply circuit 10 further includes a switch K2, and the switch K2 is coupled between the power supply line Vcc and the drain of the transistor M1. When the bias circuit 101 enters the sleep state, the switch K2 is turned on, the gate and source of the transistor M1 are both coupled to the power supply line Vcc, and the transistor M1 is turned off.

In the power supply circuit 10 shown in FIG. 4 and FIG. 5 , when the transistor M0 is in the off state, the gate is coupled to the power supply line Vcc, that is, the gate potential of the transistor M0 is equal to the source potential, and when the transistor M0 is turned off by When the state is switched to the on state, the gate of the transistor M0 needs to release part of the charge to form a voltage difference with the source, so that the transistor M0 is turned on. Generally, due to the existence of the filter circuit 102, it takes a certain time for the gate of the transistor M0 to recover from the common power supply voltage to the bias voltage, which depends on the product of the resistance and the capacitance in the filter circuit. In order to speed up the release speed of the gate charge of the transistor M0 and reduce the transition time of the transistor M0 from the off state to the on state, in a possible implementation manner, when the power supply circuit 10 includes the filter circuit 102, the power supply circuit 10 also A short circuit 103 is included. The short-circuit circuit 103 is used to short-circuit the filter circuit in the initial stage when the transistor M0 is turned from the off-state to the on-state, so that the charge on the gate of the transistor M0 can be quickly released to the common ground through the bias circuit 101, and the gate of the transistor M0 can be quickly released. The release speed of the polar charge is beneficial to shorten the time for the transistor M0 to change from the off state to the on state, thereby shortening the time for the transceiver 100 to change from the sleep state to the stable working state, and improving the performance of the transceiver 100 . In a possible implementation, the short circuit 103 may include a switch K3. When the filter circuit 10 is the low-pass filter circuit shown in FIG. 5 , the switch K3 is connected in parallel with both ends of the resistor R1 , as shown in FIG. 6 . In the initial stage when the transistor M0 is turned from the off state to the on state, the switch K3 is turned on, and the charge on the gate of the transistor M0 is released to the common ground Gnd through the bias circuit 101; after a certain period of time, the gate potential of the transistor M0 gradually decreases When the gate potential of the transistor M1 is reached, the switch K3 is turned off, and the bias circuit 101 provides a stable signal to the transistor M0 through the filter circuit 102 .

In the power supply circuit 10 shown in FIG. 5 and FIG. 6 , since the gate of the transistor M0 is coupled with the gate of the transistor M1 through the resistor R1 or directly coupled, in the initial stage when the transistor M0 is turned from the off state to the on state, the transistor M0 The charge released from the gate of M0 affects the gate potential of transistor M1, causing the gate potential of transistor M1 to change. However, it also takes a certain period of time for the bias circuit 101 to recover to a stable state, thereby increasing the time period for the load component to change from a power-off state to a stable working state. In order to improve the stability of the bias circuit 101 and further reduce the transition duration of the transistor M0 from the off state to the on state, in a possible implementation manner, the power supply circuit 10 may further include a drive circuit 104, and the drive circuit 104 is coupled to the Between the bias circuit 101 and the transistor M0, as shown in FIG. 7 . The driving circuit 104 is used to obtain the mirror voltage from the bias circuit 101 to realize isolation between the bias circuit 101 and the transistor M0. In addition, the driving circuit 104 is also used to extract charges from the gate of the transistor M0 when the transistor M0 is turned from an off state to an on state, so as to improve the discharge speed of the charges. The driving circuit 104 shown in FIG. 7 includes various implementations. Similarly, for the driving circuits 104 of different structures, the bias circuit 101 may also include various implementations. The bias circuit 101 and the driving circuit 104 in the power supply circuit 10 shown in FIG. 7 will be described in detail below through the embodiments shown in FIG. 8 to FIG. 10 .

In a first possible implementation manner, the driving circuit 104 may include a source follower; in a second possible implementation manner, the driving circuit 104 may include an operational amplifier F1, wherein the specific description of the second possible implementation manner Reference is made to the embodiment shown in FIG. 10 . The first possible implementation manner is described in detail below. The source follower includes transistor M3 and transistor M4, as shown in FIG. 8 . The first pole of the transistor M3 is coupled to the power supply line Vcc, the second pole of the transistor M3 and the first pole of the transistor M4 are both coupled to the bias voltage line Vb, and the second pole of the transistor M4 is coupled to the common ground Gnd. The gate of transistor M3 is coupled to the gate of transistor M1. The first electrode of the transistor M4 (or the second electrode of the transistor M3 ) supplies a bias voltage to the gate of the transistor M0 through the bias voltage line Vb. Bias circuit 101 also includes transistor M2, the gate of which is coupled to the gate of transistor M2. The gate and second pole of transistor M2 are coupled together to form a current mirror. The first terminal of the transistor M2 is coupled to the second terminal of the transistor M1, and the gate and second terminal of the transistor M2 are coupled to the common ground Gnd through the current source I. In addition, in FIG. 8 , the driving circuit 104 further includes a switch K4, and the switch K4 is used to control the second pole of the transistor M4 to be connected or disconnected from the common ground Gnd. The transistors M2, M3 and M4 shown in FIG. 8 may be PMOS transistors, NMOS transistors or BJTs. The figure schematically shows the case where the transistor M2, the transistor M3 and the transistor M4 are PMOS transistors. At this time, the transistor M2, the transistor M3 and the transistor M4 have a first pole of a source and a second pole of a drain. In FIG. 8, transistor M1 provides mirror current to transistor M3, and transistor M2 provides mirror current to transistor M4. In the embodiment of the present application, the size of the conductive channel of the transistor M1 and the size of the conductive channel of the transistor M3 have a first proportional relationship, and similarly, the size of the conductive channel of the transistor M2 and the size of the conductive channel of the transistor M4 have a second proportional relationship, The above-mentioned first proportional relationship is the same as the second proportional relationship. The size of the above-mentioned conductive channel may be the length and width of the conductive channel, or may be the ratio of the length to the width. Taking the transistor M1 and the transistor M3 as examples, the length of the conduction channel of the transistor M1 and the length of the conduction channel of the transistor M3, and the width of the conduction channel of the transistor M1 and the width of the conduction channel of the transistor M3 all have the above-mentioned first proportional relationship. . The specific numerical values of the first proportional relationship and the second proportional relationship are determined by the gate voltage when the transistor M0 is turned on. When the gate voltage when the transistor M0 is turned on is relatively high, that is, the voltage output by the first pole of the transistor M4 is relatively high, the above-mentioned first proportional relationship and the second proportional relationship can be improved at this time; when the transistor M0 is turned on, the voltage When the gate voltage is low, that is, the voltage output by the first pole of the transistor M4 is low, the above-mentioned first proportional relationship and the second proportional relationship can be reduced. In the embodiment shown in FIG. 8 , by setting the driving circuit 104 , the bias circuit 101 and the transistor M0 can be decoupled to avoid the bias caused by the change of the gate voltage when the transistor M0 is turned from the off state to the on state. The change of the voltage in the circuit 101 is set to improve the stability of the circuit. In addition, in the process of restoring the gate voltage of the transistor M0 from the common power supply voltage to the working voltage, the excess charges on the gate of the transistor M0 can be released to the common ground Gnd through the transistor M4, which speeds up the charge release speed and reduces the transition of the transistor M0 from the off state. is the transition time for steady state operation.

The following takes transistor M0, transistor M1, transistor M2, transistor M3 and transistor M4 as PMOS transistors as an example, the first proportional relationship and the second proportional relationship are 1 as an example, switch K1, switch K2, switch K3 and switch K4 are NMOS transistors Taking a transistor as an example, the working principle of the power supply circuit 10 shown in FIG. 8 will be described with reference to the timing sequence shown in FIG. 9 . In FIG. 9, C1 represents the control sequence of the switch K1 and the switch K2, C2 represents the control sequence of the switch K4, and C3 represents the control sequence of the switch K3.

In period T1, the control terminals of switches K1 and K2 are high-level signals, and the control terminals of switches K3 and K4 are low-level signals. At this time, switches K1 and K2 are turned on, and switches K3 and K4 are turned off. The gate of the transistor M0 is coupled to the power supply line Vcc, the gate of the transistor M0 is equal to the source potential, and the transistor M0 is turned off; the source and drain potentials of the transistor M3 are equal, and the transistor M3 is turned off; the charge accumulated at the drain of the transistor M4 cannot be It flows to the common ground Gnd, and the transistor M4 is turned off. That is, the power supply to the load device is stopped at this time, the load device and the driving circuit are both powered off, and the transceiver 100 as shown in FIG. 1 enters a low power consumption state.

In the first sub-period t1 of the period T2, that is, in the initial period of the period T2, a low-level signal is provided to the control terminals of the switch K1 and the switch K2, and a high-level signal is provided to the control terminals of the switch K3 and the switch K4, and the switches K1 and switch K2 are turned off, and switch K3 and switch K4 are turned on. The gate potential of transistor M3 is the same as the gate potential of transistor M1, the source potential of transistor M1 is the same as the source potential of transistor M3, the gate potential of transistor M4 is the same as the gate potential of transistor M2, the drain potential of transistor M4 is the same The potential is the same as the drain potential of the transistor M2, and the source potential of the transistor M4 is the same as the gate potential of the transistor M0, which is the potential of the power supply line Vcc. Since the drain potential of the transistor M3 is higher than the gate potential, the charge raised by the drain of the transistor M3 is released to the common ground Gnd through the transistor M4. When the drain potential of the transistor M3 is equal to the gate potential, the power supply circuit 10 enters the Second sub-period of period T2. In the second sub-period t2 of the period T2, the gate potential of the transistor M0, the source potential of the transistor M4 and the gate potential of the transistor M1 are all equal, and the power supply circuit 10 and the transistor M0 enter a stable working state. At this time, the states of the switch K1, the switch K2 and the switch K4 are kept unchanged, a low-level signal is provided to the switch K3, and the switch K3 is turned off. The bias circuit 101 provides a stable bias voltage to the transistor M0 through the filter circuit 102 . In the circuit shown in FIG. 8, the time period for the potential of the gate of transistor M0 to drop from the potential of power supply line Vcc to the potential of the gate of transistor M1 is determined by the voltage difference between the gate and source of transistor M4, and Compared with the time length determined by the current source I shown in FIG. 4 , the release speed of the gate charge of the transistor M0 can be accelerated, and the time length of the transceiver from the low power consumption state to the stable working state can be shortened.

Based on the power supply circuit 10 shown in FIG. 7 , in a second possible implementation manner, the driving circuit 104 may include an operational amplifier F, as shown in FIG. 10 . The operational amplifier F can be a unipolar operational amplifier or a multi-stage operational amplifier. Wherein, when the operational amplifier F is a unipolar operational amplifier, it may include a five-tube structure amplifier, a symmetrical (symmetrical) transconductance amplifier (OTA), a telescopic (telescopic) OTA or a folded cascode ( folded-cascode) OTA. The embodiment of the present application does not specifically limit the operational amplifier F. The non-inverting input terminal "+" of the operational amplifier F is coupled to the gate of the transistor M1, the inverting input terminal "-" of the operational amplifier F is coupled to the output terminal of the operational amplifier F, and the output terminal of the operational amplifier F is coupled to the bias voltage line Vb, for supplying a bias voltage to the gate of the transistor M0 through the bias voltage line Vb. In FIG. 10 , the bias circuit 101 includes a transistor M1 and a current source I. The connection relationship between the transistor M1 and the current source I1 and the connection relationship with other components are the same as the transistor M1 and the current source I1 shown in FIG. 6 . Referring to the related description in FIG. 6 , details are not repeated here. The operational amplifier F shown in the embodiment of the present application constitutes a unit buffer due to the coupling between the inverting input terminal and the output terminal. The voltage is the same, that is, the same as the gate voltage of the transistor M1.

Based on the structure of the bias circuit 101 and the structure of the drive circuit 104 shown in FIG. 10 , when the switch K1 and the switch K2 are turned from on to off in the initial stage, the potential of the output terminal of the operational amplifier F is the same as the gate potential of the transistor M0 , is the potential of the power supply line Vcc. At this time, the potential of the output terminal of the operational amplifier F is higher than the potential of the non-inverting input terminal, the potential of the non-inverting input terminal is the same as the potential of the transistor M1, and the higher charge of the output terminal of the operational amplifier F is released to the common ground Gnd through the transistor M1. When the terminal potential is equal to the gate potential of the transistor M1, the power supply circuit 10 and the transistor M0 enter a stable working state. The control sequence of the switch K1 and the switch K2 shown in FIG. 10 may refer to the relevant description of the control sequence C1 shown in FIG. 9 , and the control sequence of the switch K3 may refer to the relevant description of the control sequence C3 shown in FIG. 9 . No longer.

It should be noted that the power supply circuit 10 shown in FIG. 7 , FIG. 8 and FIG. 10 may include more or less devices. For example, in some embodiments, the filter circuit 102 and the switch K2 may not be provided. In this case, the switch K1 may control the turn-on and turn-off of the transistor M0 and the transistor M1 at the same time, that is, simultaneously control the bias circuit 101 and the load device to enter Sleep state or enter working state. In the embodiment of the present application, when the power supply circuit 10 includes the filter circuit 102 and the short circuit 103, that is, when the power supply circuit 10 has the structure shown in FIG. 4-FIG. 8 and FIG. 10, in a possible implementation manner, Based on the power supply circuit 10 shown in any of FIG. 6 , FIG. 8 , and FIG. 10 , the power supply circuit 10 described in this embodiment of the present application further includes a control circuit 105 . The control circuit 105 is used for outputting a control signal to control the turn-on or turn-off of the switch K3 shown in any of the embodiments shown in FIG. 6 , FIG. 8 and FIG. 10 . The output terminal Vo1 of the control circuit 105 is coupled to the control terminal of the switch K3. The control circuit 105 described in this embodiment of the present application may include, but is not limited to, a programmable logic controller (PLC, Programmable Logic Controller), a digital signal processor (DSP, digital signal processor), a signal generator, etc. The control circuit 105 may also Including discrete devices. The control circuit 105 will be described in detail below through the embodiments shown in FIGS. 11-12 .

Please refer to FIG. 11 , which shows a schematic structural diagram of the control circuit 105 provided by an embodiment of the present application. In FIG. 11 , the control circuit 105 includes a delay 51 , an inverter 52 , an inverter 53 , an AND gate 54 and an exclusive OR gate 55 . The input terminal of the delay device 51 is used to input the signal S1 from the outside, the input terminal of the inverter 52 and the second input terminal of the AND gate 54 are both coupled to the input terminal of the delay device 51, and the output terminal of the delay device 51 is coupled to The first input of AND gate 54, the output of AND gate 54 is coupled to the first input of XOR gate 55, the output of inverter 52 is coupled to the input of inverter 53, and the output of inverter 53 The terminal is coupled to the second input terminal of the XOR gate 55 , and the output terminal of the XOR gate 55 is used as the output terminal Vo1 of the control circuit 105 to output the control signal S2 . In the structure of the control circuit 105 shown in FIG. 11 , the signal S1 may be a signal that controls the switch K4 shown in FIG. 8 to be turned on or off. The control signal S2 is used to control the switch K3 shown in any of the embodiments of FIG. 6 , FIG. 8 and FIG. 10 to be turned on or off. Wherein, the timing of the signal S1 is the same as the control timing C2 shown in FIG. 9 , and the timing of the control signal S2 is the same as the control timing C3 shown in FIG.

Based on the control circuit 105 shown in FIG. 11 , in a possible implementation manner, the control circuit 105 further includes an output end Vo2 , wherein the output end of the inverter 52 is the output end Vo2 of the control circuit 105 , and the output end Vo2 can be respectively Coupled to the control terminals of switches K1 and K2 as shown in Figure 5, Figure 6, Figure 8 and Figure 10, the output terminal of the inverter 52 is used to output a signal S3 to control the conduction of switches K1 and K2 or off. The timing sequence of the signal S3 is the same as the control timing sequence C1 shown in FIG. 9 , and the specific reference is made to the related description, which will not be repeated here.

Please refer to FIG. 12 . FIG. 12 shows another schematic structural diagram of the control circuit 105 provided by the embodiment of the present application. In FIG. 12 , the control circuit 105 includes a comparator 56 and an AND gate 57 . The first input terminal of the comparator 56 is used for the input signal S4, the second input terminal of the comparator 56 is coupled to the gate g of the transistor M0 as described in the above embodiments, and the control terminal of the comparator 56 is used for the input signal S1 , the output terminal of the comparator 56 is coupled to the first input terminal of the AND gate 57 , the second input terminal of the AND gate 57 is used for the input signal S1 , and the output terminal of the AND gate 57 is used as the output terminal Vo1 of the control circuit 105 to output the control timing. In the embodiment of the present application, the timing sequence of the signal S1 may be the same as the control timing sequence C3 shown in FIG. 9 , that is, the control timing sequence of the control switch K1 and the switch K2 are reversed; the signal S4 is a fixed voltage signal, and the fixed voltage signal is high at the gate voltage of the transistor M1 as shown in the above embodiments. Taking the switch K3 as an NMOS transistor as an example, the working principle of the control circuit 105 shown in FIG. 12 will be described. The comparator 56 is controlled by the signal S1 to trigger the comparison. When the voltage of the signal S4 is lower than the gate voltage of the transistor M0, the comparator 56 outputs a high level. At this time, the signal S1 is a high level, and the AND gate 57 outputs a high level. , the switch K3 is turned on; when the voltage of the signal S4 is higher than the gate voltage of the transistor M0, the comparator 56 outputs a low level, and no matter what state the signal S1 is at this time, the AND gate 57 outputs a high and low level, and the switch K3 is turned off.

Based on the structure of the control circuit 105 shown in FIG. 12 , in a possible implementation manner, the bias circuit 101 further includes a resistor R2 on the basis of the embodiment shown in FIG. 10 , and the resistor R2 is connected in series with the transistor M1 between the second pole and the current source I, as shown in Figure 13. The second pole of the transistor M1 leads to the output terminal Vs4, which is coupled to the first input terminal of the comparator 56 in the control circuit 105 as shown in FIG. 12 to input the signal S4 to the comparator 56 . In addition, in FIG. 13 , node b is formed where resistor R2 is coupled with current source I, and the gate of transistor M1 is coupled to node b, that is, node b is used to input a signal to the non-inverting input terminal of operational amplifier F.

This embodiment of the present application further provides an electronic device, as shown in FIG. 14 . FIG. 14 is a schematic structural diagram of an electronic device provided by an embodiment of the present application, as shown in FIG. 14 . The electronic device 1400 includes a memory 1401, a processor 1402, and the transceiver 100 shown in FIG. 1 above. The transceiver includes the power supply circuit 10 shown in any one of the embodiments of FIGS. 4-8, 10 and 13. The memory 1401 is coupled to the processor 1402 , and the processor 1402 is coupled to the transceiver 100 .

It should be understood that the electronic device here may specifically be a terminal device such as a smart phone, a computer, and a smart watch. Taking the terminal device as an example of a smart phone, it may specifically include a processor, a memory, a transceiver, and an input and output device. The processor is mainly used to process the communication protocol and communication data, control the entire smartphone, execute software programs, and process the data of the software programs, for example, to support the smartphone to realize various communication functions (such as making calls, sending messages, etc.). or live chat, etc.). The memory is mainly used to store software programs and data. The transceiver is mainly used for the conversion of baseband signal and radio frequency signal and the processing of radio frequency signal. Transceivers are mainly used to send and receive radio frequency signals in the form of electromagnetic waves. Input and output devices, such as touch screens, display screens, and keyboards, are mainly used to receive data input by users and output data to users.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited to this. should be covered within the scope of protection of this application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

A transceiver, characterized by comprising: a power supply circuit and a load circuit, the load circuit including at least one of a transmit channel and a receive channel; wherein,

The transmit channel includes at least one load device among a digital-to-analog converter, a mixer, a filter, and a power amplifier, and the receive channel includes at least one of a low-noise amplifier, a mixer, a filter, and an analog-to-digital converter a load device, the transmitting channel and the receiving channel are used for working in a time division duplex mode;

The power supply circuit includes a bias circuit, a filter circuit, a power supply line and a bias voltage line;

the load circuit is coupled to the power supply line and the bias voltage line, respectively;

the bias circuit is coupled to the bias voltage line for outputting a bias voltage to the bias voltage line;

The filter circuit is coupled between the bias circuit and the load circuit, and is used for filtering the bias voltage and the power supply voltage provided by the power supply line, and providing the filtered power supply voltage and the bias voltage to a the load circuit.
The transceiver of claim 1, wherein the load circuit comprises at least one first transistor; a source of the at least one first transistor is coupled to the power supply line, and a source of the at least one first transistor is coupled to the power supply line. A drain is correspondingly coupled to a power supply terminal of at least one load device in the load circuit, and a gate of the at least one first transistor is coupled to the bias voltage line.
The transceiver according to claim 1 or 2, wherein the bias circuit comprises a second transistor; the source of the second transistor is coupled to the power supply line, and the gate of the second transistor and the A drain is coupled to the bias voltage line.
The transceiver of claim 3, wherein the bias circuit further comprises a current source coupled in series between the drain of the second transistor and a common ground.
The transceiver according to claim 4, wherein the bias circuit further comprises a third transistor; the source of the third transistor is coupled to the drain of the second transistor, and the third transistor has The drain is coupled to common ground through the current source, and the gate of the third transistor is coupled to the drain of the third transistor.
The transceiver according to claim 4, wherein the bias circuit further comprises a first resistor; a first end of the first resistor is coupled to the drain of the second transistor, the first resistor The second terminal of the second transistor is coupled to the common ground through the current source, and the gate of the second transistor is coupled to the second terminal of the first resistor.
The transceiver according to any one of claims 2-6, wherein the filter circuit comprises a capacitor and a second resistor; wherein a first end of the capacitor is coupled to a gate of the first transistor , the second end of the capacitor is coupled to the power line; the first end of the second resistor is coupled to the first end of the capacitor, and the second end of the second resistor is coupled to the second transistor gate.
The transceiver according to claim 5 or 6, wherein the power supply circuit further comprises a driving circuit, and the driving circuit comprises a fourth transistor and a fifth transistor;

The source of the fourth transistor is coupled to the power supply line, the drain of the fourth transistor is coupled to the source of the fifth transistor, the drain of the fifth transistor is coupled to the common ground, and the fourth transistor is coupled to the common ground. The drain of the fourth transistor and the source of the fifth transistor are coupled to the bias voltage line, the gate of the fourth transistor is coupled to the gate of the second transistor, the gate of the fifth transistor is coupled coupled to the gate of the third transistor.
The transceiver according to claim 8, wherein the driving circuit further comprises a first switch; and the drain of the fifth transistor is coupled to a common ground through the first switch.
The transceiver according to any one of claims 2-4, wherein the power supply circuit further comprises a driving circuit, and the driving circuit comprises an operational amplifier;

The inverting input terminal of the operational amplifier is coupled to the output terminal of the operational amplifier; the output terminal of the operational amplifier is coupled to the bias voltage line; the non-inverting input terminal of the operational amplifier is coupled to the output terminal of the second transistor. gate coupling.
The transceiver according to claim 7, wherein the power supply circuit further comprises a short circuit, and the short circuit comprises a second switch; the second switch is connected in parallel with both ends of the second resistor.
The transceiver according to claim 11, wherein the power supply circuit further comprises a control circuit; the control circuit is configured to control the second switch to be turned on or off.
The transceiver according to claim 12, wherein the control circuit comprises a delay, a first inverter, a second inverter, an AND gate and an exclusive OR gate; wherein,

The input end of the delay device is used for inputting the first signal, the output end of the delay device is coupled with the first input end of the AND gate; the second input end of the AND gate is used for inputting the first signal ; The output end of the AND gate is coupled with the first input end of the XOR gate; the input end of the first inverter is used to input the first signal; the input end of the second inverter is coupled with the output end of the first inverter; the output end of the second inverter is coupled with the second input end of the XOR gate; the output end of the XOR gate is used to output a control signal, to control the second switch to be turned on or off.
The transceiver of claim 12, wherein the control circuit comprises a comparator and an AND gate; wherein,

The first input terminal of the comparator is used for inputting the first voltage; the second input terminal of the comparator is coupled to the gate of the first transistor; the output terminal of the comparator is connected to the first voltage of the AND gate. An input end is coupled; the second input end of the AND gate is used for inputting a first signal; the output end of the AND gate is used for outputting a control signal to control the second switch to be turned on or off.
The transceiver according to any one of claims 3-14, wherein the power supply circuit further comprises a third switch and a fourth switch; one end of the third switch is coupled to the power line, and the The other end of the third switch is coupled to the gate of the first transistor; one end of the fourth switch is coupled to the power supply line, and the other end of the fourth switch is coupled to the gate of the second transistor .
An electronic device, characterized by comprising a memory, a processor, and the transceiver according to any one of claims 1 to 15.