WO2022204875A1 - 测量方法及网络设备 - Google Patents

测量方法及网络设备 Download PDF

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Publication number
WO2022204875A1
WO2022204875A1 PCT/CN2021/083612 CN2021083612W WO2022204875A1 WO 2022204875 A1 WO2022204875 A1 WO 2022204875A1 CN 2021083612 W CN2021083612 W CN 2021083612W WO 2022204875 A1 WO2022204875 A1 WO 2022204875A1
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Prior art keywords
processing
processing module
measurement packet
module
packet
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PCT/CN2021/083612
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English (en)
French (fr)
Inventor
高岑
许辛达
彭云粮
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2021/083612 priority Critical patent/WO2022204875A1/zh
Priority to EP21933561.9A priority patent/EP4311189A4/en
Priority to CN202180090701.7A priority patent/CN116746126A/zh
Publication of WO2022204875A1 publication Critical patent/WO2022204875A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0852—Delays
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/06—Management of faults, events, alarms or notifications
    • H04L41/0677—Localisation of faults
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/34—Signalling channels for network management communication
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/10—Active monitoring, e.g. heartbeat, ping or trace-route
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/50—Testing arrangements

Definitions

  • the embodiments of the present application relate to the field of communications, and in particular, to a measurement method and a network device.
  • forwarding delay is a very important indicator to measure chip capability, and forwarding delay has a great impact on service performance.
  • the delay measurement of the forwarding path in the prior art usually adopts end-to-end measurement. For example, you can test the round-trip delay from one device to the other, or measure the one-way delay from one device to the other. However, when there are multi-hop devices on the forwarding path, the end-to-end measurement method cannot accurately locate the faulty device.
  • the present application provides a measurement method and a network device.
  • the electronic device or chip can obtain the total duration of packet processing, so as to obtain the forwarding delay of each hop of the electronic device on the end-to-end forwarding path, so that the faulty device can be accurately located.
  • an embodiment of the present application provides a measurement method.
  • the method includes: the apparatus receives a first measurement message.
  • the apparatus acquires the processing duration for processing the first measurement packet by each processing module in the at least one processing module.
  • the apparatus acquires, based on the processing duration of each processing module processing the first measurement packet, the total processing duration of at least one processing module processing the first measurement packet.
  • the electronic device may include multiple modules, and at least one processing module is a part or all of the multiple modules.
  • the total processing duration is the sum of the processing durations of each processing module.
  • the first measurement packet includes indication information, where the indication information is used to indicate that the processing duration of the first measurement packet needs to be measured.
  • indication information is used to indicate that the processing duration of the first measurement packet needs to be measured.
  • test packet may be an individual packet or a data packet.
  • the indication information may be in the frame header part of the packet.
  • receiving the first measurement packet includes: the device, in response to the received first measurement packet, generates an indication signal, where the indication signal is used to instruct at least one process
  • the module starts to process the first measurement message, it sends a trigger signal.
  • the processing module in the chip can be triggered to perform delay measurement by generating an indication signal.
  • the embodiment of the present application adopts a first-in, first-out test method, that is, each processing module sends a trigger signal when it starts to process. That is, when each processing module starts processing, the delay test is started.
  • receiving the first measurement packet includes: in response to the received first measurement packet, identifying whether the first measurement packet includes specified feature information; when It is recognized that the first measurement packet includes specified feature information, and an indication signal is generated, and the indication signal is used to instruct at least one processing module to start processing the first measurement packet, and send a trigger signal.
  • the embodiment of the present application further provides another delay measurement triggering method, and the device can determine that the delay test needs to be performed on the message by identifying the specified feature information in the message.
  • acquiring the processing duration for processing the first measurement packet by each processing module in the at least one processing module includes: responding to each received processing The trigger signal sent by the module records the start time when each processing module processes the first measurement message. In this way, the processing time of each module can be obtained by recording the start time of each module.
  • each processing module is connected in series, and the processing duration of each processing module is the difference between the start times of the two processing modules connected in series.
  • acquiring the processing duration for processing the first measurement packet by each processing module in the at least one processing module includes: one of the two processing modules connected in series. After the previous processing module completes the processing of the first measurement packet, it transmits the processed first measurement packet and the indication signal to the next processing module. In this way, each processing module is continuously triggered to measure the processing delay in a relay manner.
  • the specified feature information is at least one of the following: destination MAC address information, source MAC address information, destination IP address information, source IP address information, and label information.
  • the chip can match the message by identifying the specified feature information, such as any of the above addresses. When the match is successful, the delay measurement of the packet can be performed.
  • an embodiment of the present application provides a network device.
  • the network device includes: a receiving module for receiving a first measurement packet; an acquisition module for acquiring a processing time duration for each processing module in the at least one processing module to process the first measurement packet; an acquisition module, further using Based on the processing duration of each processing module processing the first measurement packet, the total processing duration of at least one processing module processing the first measurement packet is acquired.
  • the first measurement packet includes indication information, where the indication information is used to indicate that the processing duration of the first measurement packet needs to be measured.
  • the receiving module is configured to: in response to the received first measurement packet, generate an indication signal, where the indication signal is used to instruct at least one processing module to start measuring the first measurement packet.
  • a trigger signal is sent.
  • the receiving module is configured to: in response to the received first measurement packet, identify whether the first measurement packet includes specified feature information; A measurement message includes specified feature information, and an indication signal is generated, where the indication signal is used to instruct at least one processing module to send a trigger signal when starting to process the first measurement message.
  • the acquisition module is configured to: in response to the received trigger signal sent by each processing module, record that each processing module processes the first measurement packet start time.
  • each processing module is connected in series, and the processing duration of each processing module is the difference between the start times of the two processing modules connected in series.
  • the second aspect after processing the first measurement packet by the previous processing module in the two processing modules connected in series, it processes the completed first measurement packet and the Indicates that the signal is transmitted to the next processing module.
  • the specified feature information is at least one of the following: destination MAC address information, source MAC address information, destination IP address information, source IP address information, and label information.
  • the second aspect and any implementation manner of the second aspect correspond to the first aspect and any implementation manner of the first aspect, respectively.
  • the technical effects corresponding to the second aspect and any implementation manner of the second aspect reference may be made to the technical effects corresponding to the first aspect and any implementation manner of the first aspect, which will not be repeated here.
  • embodiments of the present application provide a computer-readable medium for storing a computer program, where the computer program includes instructions for executing the method in the first aspect or any possible implementation manner of the first aspect.
  • the third aspect and any implementation manner of the third aspect correspond to the first aspect and any implementation manner of the first aspect, respectively.
  • the technical effects corresponding to the third aspect and any implementation manner of the third aspect reference may be made to the technical effects corresponding to the first aspect and any implementation manner of the first aspect, which will not be repeated here.
  • an embodiment of the present application provides a computer program, where the computer program includes instructions for executing the method in the first aspect or any possible implementation manner of the first aspect.
  • the fourth aspect and any implementation manner of the fourth aspect correspond to the first aspect and any implementation manner of the first aspect, respectively.
  • the technical effects corresponding to the fourth aspect and any implementation manner of the fourth aspect reference may be made to the technical effects corresponding to the first aspect and any implementation manner of the first aspect, which will not be repeated here.
  • an embodiment of the present application provides a chip, where the chip includes a processing circuit and a transceiver pin.
  • the transceiver pin and the processing circuit communicate with each other through an internal connection path, and the processing circuit executes the method in the first aspect or any possible implementation manner of the first aspect to control the receiving pin to receive a signal to Control the send pin to send the signal.
  • the fifth aspect and any implementation manner of the fifth aspect correspond to the first aspect and any implementation manner of the first aspect, respectively.
  • the technical effects corresponding to the fifth aspect and any implementation manner of the fifth aspect reference may be made to the technical effects corresponding to the first aspect and any implementation manner of the first aspect, which will not be repeated here.
  • an embodiment of the present application provides a network device.
  • the network device may be configured to send the first packet to the destination device through a data link, where the data link includes at least one intermediate device.
  • the network device is further configured to receive first processing delay information sent by each intermediate device in the at least one intermediate device, where the first processing delay information is used to instruct at least one processing module in the intermediate device to process the first packet. processing duration; and receiving second processing delay information sent by the destination device, where the second processing delay information is used to indicate the processing duration for processing the first packet by at least one processing module in the destination device.
  • the network device is further configured to determine, according to the first processing delay information and the second processing delay information, whether there is a fault processing module in the at least one intermediate device and the destination device. In this way, the network device can locate the faulty module based on the processing time corresponding to each processing module fed back by each device, so as to accurately locate the forwarding fault on the link and quickly locate the faulty device and the faulty module.
  • FIG. 1 is a schematic diagram of an exemplary communication system
  • FIG. 2 is a schematic structural diagram of an exemplary device
  • 3a is a schematic structural diagram of an exemplary chip
  • Figure 3b is a schematic diagram of an exemplary measurement flow
  • FIG. 4 is a schematic structural diagram of an exemplary chip
  • FIG. 5 is a schematic structural diagram of an exemplary chip
  • FIG. 6 is a schematic structural diagram of a communication device according to an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a chip according to an embodiment of the present application.
  • first and second in the description and claims of the embodiments of the present application are used to distinguish different objects, rather than to describe a specific order of the objects.
  • first target object and the second target object, etc. are used to distinguish different target objects, not to describe a specific order of the target objects.
  • words such as “exemplary” or “for example” are used to represent examples, illustrations or illustrations. Any embodiments or designs described in the embodiments of the present application as “exemplary” or “such as” should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as “exemplary” or “such as” is intended to present the related concepts in a specific manner.
  • multiple processing units refers to two or more processing units; multiple systems refers to two or more systems.
  • FIG. 1 it is a schematic diagram of a communication system according to an embodiment of the present application.
  • the communication system includes device 1 , device 2 , device 3 and device 4 .
  • Device 1 is communicatively connected to device 2
  • device 2 is communicatively connected to device 3
  • device 3 is communicatively connected to device 4. Any two devices from Device 1 to Device 4 can communicate.
  • the devices in the device 1 to the device 4 may be devices such as a computer, a smart phone, and a server.
  • the communication connections in the device 1 to the device 4 may be wired or wireless.
  • the connection relationship and the number of devices shown in FIG. 1 in the embodiment of the present application are only illustrative examples, which are not discussed in the present application. Do limit.
  • Figure 2 is a schematic structural diagram of a device.
  • Figure 2 is a schematic structural diagram of a device.
  • the device includes at least one processor 101 , at least one memory 102 , at least one transceiver 103 , at least one network interface 104 and one or more antennas 105 .
  • the processor 101, the memory 102, the transceiver 103 and the network interface 104 are connected, for example, via a bus.
  • the antenna 105 is connected to the transceiver 103 .
  • the network interface 104 is used to connect the device with other communication devices through a communication link. In this embodiment of the present application, the connection may include various types of interfaces, transmission lines, or buses, which are not limited in this embodiment.
  • the device 100 shown in FIG. 2 is only an example, and the device 100 may have more or fewer components than those shown in the figure, may combine two or more components, or may have different component configuration.
  • the device shown in FIG. 2 may be any of the devices 1 to 4 in FIG. 1 .
  • the processor in this embodiment of the present application may include at least one of the following types: a general-purpose central processing unit (Central Processing Unit, CPU), a digital signal processor (Digital Signal Processor, DSP), a microprocessor, Application-Specific Integrated Circuit (ASIC), Microcontroller Unit (MCU), Field Programmable Gate Array (FPGA), or an integrated circuit for implementing logic operations .
  • the processor 101 may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. At least one processor 101 may be integrated in one chip or located on multiple different chips.
  • the memory in this embodiment of the present application may include at least one of the following types: read-only memory (ROM) or other types of static storage devices that can store static information and instructions, random access memory (random access memory, RAM) or other types of dynamic storage devices that can store information and instructions, or electrically erasable programmable read-only memory (Electrically erasable programmable read-only memory, EEPROM).
  • ROM read-only memory
  • RAM random access memory
  • EEPROM electrically erasable programmable read-only memory
  • EEPROM electrically erasable programmable read-only memory
  • the memory may also be compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.) , a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, without limitation.
  • CD-ROM compact disc read-only memory
  • optical disc storage including compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.
  • magnetic disk storage medium or other magnetic storage device or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, without limitation.
  • the memory 102 may exist independently and be connected to the processor 101 .
  • the memory 102 can also be integrated with the processor 101, for example, integrated in one chip.
  • the memory 102 can store program codes for implementing the technical solutions of the embodiments of the present application, and is controlled and executed by the processor 101 .
  • the processor 101 is configured to execute the computer program codes stored in the memory 102, thereby implementing the technical solutions in the embodiments of the present application.
  • the memory 102 can also be connected to the processor 101 through an interface outside the chip.
  • the transceiver 103 may be used to support the reception or transmission of radio frequency signals between the device and other devices, and the transceiver 103 may be connected to the antenna 105 .
  • the transceiver 103 includes a transmitter Tx and a receiver Rx.
  • one or more antennas 105 may receive radio frequency signals
  • the receiver Rx of the transceiver 103 is configured to receive the radio frequency signals from the antennas, convert the radio frequency signals into digital baseband signals or digital intermediate frequency signals, and convert the digital
  • the baseband signal or the digital intermediate frequency signal is provided to the processor 101 so that the processor 101 performs further processing on the digital baseband signal or the digital intermediate frequency signal, such as demodulation processing and decoding processing.
  • the transmitter Tx in the transceiver 103 is also used to receive the modulated digital baseband signal or digital intermediate frequency signal from the processor 101, and convert the modulated digital baseband signal or digital intermediate frequency signal into a radio frequency signal, and pass a or multiple antennas 105 transmit the radio frequency signal.
  • the receiver Rx can selectively perform one or more stages of down-mixing processing and analog-to-digital conversion processing on the radio frequency signal to obtain a digital baseband signal or a digital intermediate frequency signal. The order of precedence is adjustable.
  • the transmitter Tx can selectively perform one or more stages of up-mixing processing and digital-to-analog conversion processing on the modulated digital baseband signal or digital intermediate frequency signal to obtain a radio frequency signal, and the up-mixing processing and digital-to-analog conversion processing
  • the sequence of s is adjustable.
  • Digital baseband signals and digital intermediate frequency signals can be collectively referred to as digital signals.
  • any one of the devices 1 to 4 can initiate a delay test process.
  • the device 1 initiates a delay test as an example for description.
  • device 2 and device 3 as intermediate devices between device 1 and device 4, can be used to forward the data of device 1 to device 4, or to transfer device 4. data is forwarded to Device 1.
  • the data packets described in the embodiments of the present application may be Ethernet packets, IP packets, tunnel packets, etc., which are not limited in this application.
  • test process is described below with specific application scenarios.
  • Device 1 sends a packet to device 2, device 2 forwards the packet to device 3, and device 3 forwards the packet to device 4.
  • device 1 sends the packet to the device 4, if the forwarding delay of the packet is relatively large, the user can trigger the device 1 to test the transmission delay of the packet.
  • the device 1 receives a user instruction, where the user instruction is used to instruct to test a specified packet.
  • the specified message may be indicated based on the message address.
  • a user command may be used to instruct a test for a message with a specified address (e.g., device 4), that is, device 1 will initiate a transmission delay test for a message with a specified address in response to the user command.
  • the specified packet may also be indicated based on the type of the packet.
  • a user instruction can be used to instruct a test to be performed on a message of a specified type. That is to say, in response to the user instruction, the device 1 will initiate a test for the transmission delay of the message with the specified type.
  • the user can also trigger the device to test the specified transmission path.
  • a user instruction may be used to instruct device 1 to test the forwarding path between device 1 and device 4 .
  • the forwarding path includes Device 1, Device 2, Device 3, and Device 4.
  • device 1 may test the transmission delay of the transmission path based on any packet transmitted on the transmission path.
  • the device 1 may also generate a test packet, such as a Ping packet, for testing.
  • This application is not limited. That is to say, in this embodiment of the present application, when the transmission delay on the transmission path is tested, it may be a data packet or a test packet, which is not limited in this application.
  • the data message carries the data sent by the device 1 to the device 4, and also carries the indication information, which is used to instruct each device on the transmission path to test the delay of the device. .
  • the user instructs the device 1 to test the packet sent to the device 4, that is, the packet with the specified address (the address of the device 4) as an example for description.
  • the device 1 generates a data packet in response to the received user instruction.
  • the data message includes but is not limited to: address information of device 1, address information of device 4, data information, and indication information.
  • the indication information is used to instruct each device on the transmission path to test the delay of the device based on the data packet.
  • the indication information may be carried in a specified field of the data packet.
  • the specified field may be included in the packet header of the data packet, or may be included in the data portion of the data packet, or the like. This application is not limited. It should be noted that each device on the transmission path needs to support parsing the specified field. That is to say, when each device receives a packet containing indication information, it can correctly parse a specified field in the packet to obtain the indication information.
  • device 1 sends the generated data packet to device 2. It should be noted that the forwarding process between the device 1 to the device 4, for example, the process of querying the path forwarding table and other processes may refer to the specific details in the prior art embodiments, which will not be repeated in this application.
  • device 2 receives a data packet sent by device 1 .
  • the device 2 parses the data packet to obtain the indication information in the specified field in the data packet.
  • the device 2 tests the transmission delay of the device 2 in response to the acquired indication information.
  • FIG. 3 a is a schematic structural diagram exemplarily showing a chip of the device 2 .
  • the chip exemplarily includes but is not limited to: a Profile (configuration) module 301 , a processing module 302 , a processing module 303 , a processing module 304 , a processing module 305 and a recording module 306 .
  • the Profile module 301 is connected to the processing module 302, the processing module 302 is connected to the processing module 303, the processing module 303 is connected to the processing module 304, the processing module 304 is connected to the processing module 305, and the processing modules 302 to 305 are respectively Connect with the recording module 306 .
  • the connection between the modules may be through a bus, or may be based on other lines, which is not limited in this application. It should be noted that the names and numbers of modules in FIG. 3a are only illustrative examples, and are not limited in this application.
  • Fig. 3b is a schematic diagram of an exemplary measurement flow.
  • the chip 300 receives a data packet.
  • the specified field is carried in the header of the message as an example for description.
  • the Profile module 301 may parse the header part of the data packet to obtain the indication information. Specifically, the Profile module 301 may store the correspondence between the message type and the specified field. As described above, the embodiments of the present application can be applied to testing different types of packets. Optionally, the specified fields of different packet types may be different. Correspondingly, the Profile module 301 can identify the type of the message based on the header of the message. The specified field corresponding to the type of the packet can be acquired based on the corresponding relationship between the packet type and the specified field. Exemplarily, the Profile module 301 may read a specified field corresponding to the packet to detect whether the packet carries specified information.
  • the instruction information carried in the data packet read by the Profile module 301 is taken as an example for description. It should be noted that, if the indication information is not read, it means that the data packet does not need to be tested for transmission delay, and can be processed according to the normal processing flow.
  • the Profile module 301 detects that the data packet carries the indication information, and determines that the data packet needs to be tested for transmission delay.
  • the Profile module 301 generates an indication signal after detecting the indication information. The indication signal is used to instruct at least one module in the chip that processes the data packet to perform a transmission delay test.
  • the Profile module 301 outputs the indication signal to the processing module 302 .
  • the processing module 302 acquires the data message from the interface of the chip, and receives the instruction signal input by the Profile module 301 .
  • each processing module may also transmit a vld(valid) signal to indicate that the packet being transmitted is a valid packet.
  • vld(valid) signal may indicate that the packet being transmitted is a valid packet.
  • the processing module 302 receives the data message and the indication signal. In response to the received indication signal, the processing module 302 may determine that it is necessary to test the transmission delay of the data packet. Exemplarily, the processing module 302 may generate the trigger signal 1 and output the trigger signal 1 to the recording module 306 . At the same time, the processing module 302 performs corresponding processing on the data message.
  • each processing module in the embodiment of the present application may process the message in the same manner or in a different manner.
  • the chip in the embodiment of the present application may include more modules.
  • the chip may include 10 processing modules, and the processing modules for processing the data packets are only part of the processing modules, for example, the processing modules 302 to 305 in FIG. 3b. Other processing modules may not do any processing.
  • Each module in the chip can be enabled based on the type of the received message. That is to say, for different types of packets, the modules enabled in the chip may be the same or different. This application is not limited. In this embodiment of the present application, when the transmission delay is measured, only the delay of at least one processing module that processes the packet is counted.
  • the recording module 306 may be provided with a plurality of registers.
  • Each register corresponds to a processing module.
  • the chip may include more processing modules, for example, 10 modules, the registers may optionally include 10 registers, and each register corresponds to one processing module.
  • the recording module receives the trigger signal 1 input by the processing module 302 .
  • the recording module 306 may determine that the trigger signal 1 is input by the processing module 302 based on the connection path with the processing module 302 .
  • the recording module can query the register corresponding to the processing module 302 (eg register 1), and write the timestamp corresponding to the current time into register 1.
  • the clock maintained by the recording module 306 may be the same as the real world clock.
  • the clock maintained by the recording module 306 may also be a relative clock, for example, the clock maintained by the recording module 306 starts timing after the device 1 is started. This application is not limited.
  • the clock maintained by the recording module 306 may also be updated periodically to ensure the accuracy of the recorded clock.
  • the processing module 302 after processing the data packet, the processing module 302 outputs the data packet and the indication signal to the processing module 303 .
  • the processing module 302 may also output the vld signal to the processing module 303 (for the concept, refer to the above).
  • the processing module 303 receives the data message and the indication signal.
  • the processing module 303 determines, in response to the received indication signal, that it is necessary to measure the transmission delay of the data packet.
  • the processing module 303 generates the trigger signal 2 and outputs the trigger signal 2 to the recording module. At the same time, the processing module 303 processes the data packet.
  • the recording module 306 receives the trigger signal 2 input by the processing module 303 , and can record the current time stamp 2 into the register 2 corresponding to the processing module 2 .
  • the recording module 306 receives the trigger signal 2 input by the processing module 303 , and can record the current time stamp 2 into the register 2 corresponding to the processing module 2 .
  • both the processing module 304 and the processing module 305 perform the above steps, and accordingly, the recording module 306 records the corresponding time stamps (including the time stamp 3 and the time stamp 4) based on the trigger signal input by the processing module 304 and the processing module 305. .
  • the processing module 302 records the corresponding time stamps (including the time stamp 3 and the time stamp 4) based on the trigger signal input by the processing module 304 and the processing module 305.
  • the processing module 305 outputs the processed data packet to other chips or devices (eg, device 3 ).
  • the trigger signal 5 may be sent to the recording module 306 .
  • the recording module 306 records the corresponding timestamp.
  • the time difference between the time stamp corresponding to the trigger signal 4 sent by the processing module 305 and the time stamp corresponding to the trigger signal 5 sent by the processing module 305 is the processing duration of the processing module 305 .
  • the processing duration of the processing module 305 can be set to a preset value, that is, in the subsequent statistical process, the total processing duration of the chip can be compensated based on the preset value, that is, adding the corresponding processing module 305 The preset value of the processing time.
  • the processing module 305 sends the trigger signal 5 after the processing is completed as an example for description.
  • one or more chips may be included in the device 2 .
  • FIG. 4 is a schematic structural diagram of the exemplarily shown device 2 .
  • the device 2 includes a chip 300 and a chip 400 .
  • the chip 400 includes but is not limited to: a processing module 401 , a processing module 402 , a processing module 403 , a processing module 404 , and a recording module 405 .
  • the chip 2 may include a Profile module, or may not include a Profile module, which is not limited in this application.
  • the processing module 305 outputs the data message and the instruction signal to the processing module 401 in the chip 400 through the interface with the chip 400 .
  • the processing module 401 receives the data message and the instruction signal, generates a trigger signal, and outputs the trigger signal to the recording module 405 .
  • the logging module 405 may log the timestamp 6 .
  • the recording module 405 can record the time stamps corresponding to the processing modules 402 to 404 .
  • the recording module 306 in the chip 300 can optionally output multiple stored timestamps (including timestamp 1 to timestamp 5) to the processor.
  • the processor may, according to requirements, perform statistics on the acquired timestamps to obtain the transmission delay of each processing module (also referred to as processing delay or processing duration), and/or the total processing duration of the chip 300 .
  • the total processing time is the transmission delay (also referred to as forwarding delay) when the chip 300 transmits (or forwards) the data packet.
  • the processor and the chip 300 described above are different devices, that is, the processor is outside the chip 300 and is connected through a connection such as a bus.
  • the transmission delay of the processing module 302 is the difference between timestamp 1 and timestamp 2 (ie, timestamp 2 minus timestamp 1).
  • the transmission delay of the processing module 303 is the difference between timestamp 3 and timestamp 2 (ie timestamp 3 minus timestamp 2).
  • the transmission delay of the processing module 304 is the difference between timestamp 4 and timestamp 3 (ie timestamp 4 minus timestamp 3).
  • the transmission delay of the processing module 305 is the difference between timestamp 5 and timestamp 4 (ie timestamp 5 minus timestamp 4).
  • the total processing duration of the chip 300 may be obtained by the sum of the transmission delays of each processing module.
  • the total processing duration of the chip 300 may also be obtained by the difference between timestamp 1 and timestamp 5 (ie, timestamp 5 minus timestamp 1).
  • the processor may feed back the acquired measurement results to the upper-layer application.
  • the measurement result includes the transmission delay of each processing module and/or the transmission delay of the chip (ie, device 2 ).
  • the upper-layer application can transmit the measurement result to device 1.
  • the device 2 After the device 2 processes the data packet, it sends the data packet to the device 3 .
  • Device 3 and Device 4 may measure the transmission delay sequentially based on the above-mentioned measurement methods, and feed back the measurement result to Device 1 .
  • the device 1 optionally displays the measurement results corresponding to each device in the display window.
  • the device 1 may also count the total transmission delay.
  • the total transmission delay is the sum of the transmission delays of each device.
  • the device 1 may locate the faulty device based on the acquired multiple measurement results. For example, the device 1 may be set with a range corresponding to different devices or corresponding to the processing duration (ie, transmission delay) of each processing module in the device. If the transmission delay of a certain device is greater than the set threshold, it can be determined that the device is a problem device (or a faulty device). Exemplarily, the device 1 may further determine the problem module by comparing the delays corresponding to the processing modules in the device and the preset ranges corresponding to the modules.
  • device 1 can obtain the transmission delay between devices based on the timestamp corresponding to each device. For example, the difference between the last timestamp of device 2 and the first timestamp of device 3 is the time taken for device 2 to transmit the packet to device 3 (ie, the transmission delay). In another example, if the clocks of device 1 to device 4 are not synchronized.
  • the device 1 may acquire the total duration of the packet transmission from the device 1 to the device 4, and the total duration may be acquired through the Ping message. The total duration includes the processing duration of each device and the transmission delay when transmitting packets between devices.
  • the device 1 may obtain the sum of the total duration and the processing duration of each device obtained through measurement, so as to obtain the transmission delay of the actual transmission packet.
  • the processing time of each device obtained by measurement is less than the set threshold, that is, under the condition that no abnormality occurs in each device, if the transmission delay of the actual transmission packet is greater than the set threshold, it can be determined that the impact of the report is affected.
  • the factor of text transmission is the transmission cable between the devices. For the fault location of the cable, reference may be made to the prior art, which is not limited in this application.
  • FIG. 5 is a schematic structural diagram of an exemplary chip 500 .
  • the chip 500 includes, but is not limited to, a Profile module 501 , a processing module 502 , a processing module 503 , a processing module 504 , a processing module 505 , a processing module 506 and a recording module 507 .
  • the processing module 503 processes the data packet by saving the data packet. That is to say, the processing by the processing module 503 will not affect the transmission delay of the data packet.
  • the Profile module 501 may send a data packet and an indication signal to the processing module 502 to instruct the processing module 502 to measure the transmission delay of the data packet.
  • the Profile module may send a data packet to the processing module 503 without sending an indication signal.
  • the processing module 503 performs corresponding processing on the data message.
  • the Profile module 501 may send a data message and an indication signal to the processing module 502 and the processing module 503 . After the processing module 503 receives the data packet and the indication signal, it does not generate a trigger signal, and only performs corresponding processing on the data packet.
  • the Profile module 501 may send a data message and an indication signal to the processing module 502 and the processing module 503 .
  • processing module 502 and processing module 503 can be viewed as parallel processing modules. The processing module 502 and the processing module 503 can generate a trigger signal and output the trigger signal to the recording module 507 .
  • the processor may determine that the processing module 502 and the processing module 503 are parallel processing modules based on the time stamps of the processing module 502 and the processing module 503 .
  • the processor may use the processing duration corresponding to the module with the longest processing duration as the transmission delay of the parallel processing module.
  • a key module may be set in advance, where the key module is one or more processing modules among multiple processing modules that process packets. That is, in this embodiment of the present application, only the processing delay of at least one processing module in the multiple processing modules may be counted.
  • the device 1 may also periodically initiate the above-mentioned test process to realize automatic detection of automatic transmission delay.
  • the transmission delay of the chip is optionally the sum of the delays of each processing module.
  • the processing delay of the processing module is equal to the recorded timestamp difference.
  • the delay can be set as a default value, and the set default value can be subtracted when the transmission delay of each processing module is counted.
  • the transmission delays of the trigger signals of the processing modules are also different.
  • the processor may pre-record the trigger signal transmission delay corresponding to each processing module, and the trigger signal transmission delay corresponding to each processing module may be the same or different, which is not limited in this application.
  • the transmission delay of each processing module is counted, the transmission delay of the trigger signal corresponding to each module can be subtracted.
  • the transmission delay of the trigger signal is relatively small, it can also be ignored.
  • the processing of the Profile module also takes a certain period of time.
  • the processing duration of the Profile module can also be a set default value, and the set default value of the Profile module can be subtracted when the transmission delay of the chip is counted.
  • the processing time of the Profile module is relatively small and negligible.
  • time between multiple devices may be synchronized or not. That is to say, even if the time between multiple devices is not synchronized, the statistics of the transmission delay of a single device will not be affected.
  • Device 1 sends a packet to device 2, device 2 forwards the packet to device 3, and device 3 forwards the packet to device 4.
  • device 1 sends a packet to device 4
  • the message includes, but is not limited to, address information and data information, wherein the address information includes source address information and destination address information.
  • the user may issue an instruction through the device 1, or configure at least one device from the device 1 to the device 4 by means of manual configuration.
  • the device 1 to the device 4 update the matching mode of the Profile module, so that the Profile module can identify the data message containing the specified feature information.
  • the identification mode may be further configured to be periodic, for example, each period (for example, 10 minutes) performs a delay test on packets containing specified feature information.
  • the specified feature information includes, but is not limited to, destination address information and source address information in the packet.
  • the destination address information and source address information may be destination MAC (Media Access Control Address, Media Access Control Address) address information and source MAC address information, or may be destination IP (Internet Protocol Address, Internet Protocol Address) address information and source IP address information, which is not limited in this application.
  • the Profile module may identify the address information of the message.
  • the message carries the specified address information
  • other processing modules in the chip are triggered to perform a delay test on the message.
  • a delay test for other undescribed details, please refer to the description in scenario 1, which will not be repeated here.
  • FIG. 6 is a schematic structural diagram of a communication device according to an embodiment of the present application.
  • the communication apparatus 600 may include: a processor 601 , a transceiver 605 , and optionally a memory 602 .
  • the transceiver 605 may be referred to as a transceiver unit, a transceiver, or a transceiver circuit, etc., for implementing a transceiver function.
  • the transceiver 605 may include a receiver and a transmitter, the receiver may be called a receiver or a receiving circuit, etc., for implementing a receiving function; the transmitter may be called a transmitter or a transmitting circuit, etc., for implementing a transmitting function.
  • the processor 601 Stored in memory 602 may be a computer program or software code or instructions 604, which may also be referred to as firmware.
  • the processor 601 can control the MAC layer and the PHY layer by running the computer program or software code or instruction 603 therein, or by calling the computer program or software code or instruction 604 stored in the memory 602, so as to realize the following aspects of the present application.
  • the OM negotiation method provided by the embodiment.
  • the processor 601 can be a central processing unit (central processing unit, CPU), and the memory 602 can be, for example, a read-only memory (read-only memory, ROM), or a random access memory (random access memory, RAM).
  • the processor 601 and transceiver 605 described in this application may be implemented in integrated circuits (ICs), analog ICs, radio frequency integrated circuits (RFICs), mixed-signal ICs, application specific integrated circuits (ASICs), printed circuits board (printed circuit board, PCB), electronic equipment, etc.
  • ICs integrated circuits
  • RFICs radio frequency integrated circuits
  • ASICs application specific integrated circuits
  • PCB printed circuits board
  • electronic equipment etc.
  • the above-mentioned communication apparatus 600 may further include an antenna 606, and each module included in the communication apparatus 600 is only for illustration, which is not limited in this application.
  • the communication device described in the above embodiments may be an access point or a station, but the scope of the communication device described in this application is not limited thereto, and the structure of the communication device may not be limited by FIG. 29 .
  • the communication apparatus may be a stand-alone device or may be part of a larger device.
  • the implementation form of the communication device may be:
  • Independent integrated circuit IC or chip, or, chip system or subsystem
  • a set of one or more ICs optionally, the IC set may also include storage for storing data and instructions components; (3) modules that can be embedded within other devices; (4) others, and so on.
  • the chip shown in FIG. 7 includes a processor 701 and an interface 702 .
  • the number of processors 701 may be one or more, and the number of interfaces 702 may be multiple.
  • the chip or chip system may include memory 703 .
  • embodiments of the present application further provide a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and the computer program includes at least a piece of code, and the at least piece of code can be executed by an electronic device to control The electronic device is used to implement the above method embodiments.
  • an embodiment of the present application further provides a computer program, which is used to implement the above method embodiments when the computer program is executed by an electronic device.
  • the program may be stored in whole or in part on a storage medium packaged with the processor, or may be stored in part or in part in a memory not packaged with the processor.
  • an embodiment of the present application further provides a processor, and the processor is used to implement the above method embodiments.
  • the above-mentioned processor may be a chip.
  • an embodiment of the present application further provides a communication system, where the communication system includes each node and a control device in the above method embodiments.
  • the steps of the method or algorithm described in conjunction with the disclosure of the embodiments of this application may be implemented in a hardware manner, or may be implemented in a manner in which a processor executes software instructions.
  • Software instructions can be composed of corresponding software modules, and software modules can be stored in random access memory (Random Access Memory, RAM), flash memory, read only memory (Read Only Memory, ROM), erasable programmable read only memory ( Erasable Programmable ROM, EPROM), Electrically Erasable Programmable Read-Only Memory (Electrically EPROM, EEPROM), registers, hard disk, removable hard disk, CD-ROM, or any other form of storage medium known in the art.
  • RAM Random Access Memory
  • ROM read only memory
  • EPROM erasable programmable read only memory
  • registers hard disk, removable hard disk, CD-ROM, or any other form of storage medium known in the art.
  • An exemplary storage medium is coupled to the processor, such that the processor can read information from, and write information to, the storage medium.
  • the storage medium can also be an integral part of the processor.
  • the processor and storage medium may reside in an ASIC.
  • the ASIC may be located in a network device.
  • the processor and storage medium may also exist in the network device as discrete components.
  • Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.
  • a storage medium can be any available medium that can be accessed by a general purpose or special purpose computer.

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Abstract

本申请实施例提供了一种测量方法及网络设备，该方法包括：在对待测量的报文进行处理的过程中，获取至少一个处理模块中的每个处理模块的处理时长。基于每个处理模块的处理时长，得到至少一个处理模块对报文的处理总时长。本申请实施例可在对报文进行处理的过程中，获取到电子设备或单一芯片对报文的转发延时。从而可在端到端时延测量的场景中，获取到每一跳电子设备的转发时延，以实现对报文转发过程中的问题电子设备进行精准定位。

Description

测量方法及网络设备 技术领域
本申请实施例涉及通信领域，尤其涉及一种测量方法及网络设备。
背景技术
目前，对于网络处理器数据转发类芯片来说，转发延时是衡量芯片能力的一个非常重要的指标，转发延时对业务性能存在很大影响。
已有技术中对转发路径的时延测量，通常是采用端到端测量。例如，可以测试一端设备到另一端设备之间的往返时延，或者是，测量一端设备到另一端设备的单程时延。但是，在转发路径上存在多跳设备时，端到端测量方式将无法对故障设备进行准确定位。
发明内容
为了解决上述技术问题，本申请提供一种测量方法及网络设备。在该方法中，电子设备或芯片可获取到对报文处理的总时长，以实现对端到端转发路径上的每一跳电子设备的转发时延的获取，从而可对故障设备进行准确定位。
第一方面，本申请实施例提供一种测量方法。该方法包括：装置接收第一测量报文。装置获取至少一个处理模块中的每个处理模块对第一测量报文进行处理的处理时长。以及，装置基于每个处理模块对第一测量报文进行处理的处理时长，获取至少一个处理模块对第一测量报文进行处理的处理总时长。这样，本申请实施例通过对转发路径上的每个电子设备中的单一处理模块进行时延统计，从而可获取到每个设备的处理时延，从而可对传输路径上的故障设备及故障模块进行精准定位。
示例性的，电子设备可以包括多个模块，至少一个处理模块为多个模块中的部分或全部模块。
示例性的，处理总时长为每个处理模块的处理时长的总和。
根据第一方面，第一测量报文包含指示信息，指示信息用于指示需要对第一测量报文的处理时长进行测量。这样，可通过添加指示信息的方式，生成测试报文。
示例性的，测试报文可以是单独的报文，也可以是数据报文。
示例性的，指示信息可以在报文的帧头部分。
根据第一方面，或者以上第一方面的任意一种实现方式，接收第一测量报文，包括：装置响应于接收到的第一测量报文，生成指示信号，指示信号用于指示至少一个处理模块开始对第一测量报文进行处理时，发送触发信号。这样，在识别到当前报文携带指示信息后，可通过生成指示信号，触发芯片中的处理模块进行时延测量。
示例性的，本申请实施例采用先进先出测试方式，即每个处理模块在开始进行处理 时，发送触发信号。也就是说，每个处理模块开始进行处理时，启动时延测试。
根据第一方面，或者以上第一方面的任意一种实现方式，接收第一测量报文，包括：响应于接收到的第一测量报文，识别第一测量报文是否包括指定特征信息；当识别到第一测量报文包括指定特征信息，生成指示信号，指示信号用于指示至少一个处理模块开始对第一测量报文进行处理时，发送触发信号。这样，本申请实施例还提供了另一种时延测量触发方式，装置可通过识别报文中的指定特征信息，确定需要对报文进行时延测试。
根据第一方面，或者以上第一方面的任意一种实现方式，获取至少一个处理模块中的每个处理模块对第一测量报文进行处理的处理时长，包括：响应于接收到的每个处理模块发送的触发信号，记录每个处理模块对第一测量报文进行处理的起始时间。这样，可通过记录每个模块的起始时间，进而获取到每个模块的处理时长。
根据第一方面，或者以上第一方面的任意一种实现方式，每个处理模块为串联连接，每个处理模块的处理时长为串联的两个处理模块的起始时间之差。
示例性的，对于并行处理的模块，可只统计处理时长最长的模块作为并行的两个模块的处理时长。
根据第一方面，或者以上第一方面的任意一种实现方式，获取至少一个处理模块中的每个处理模块对第一测量报文进行处理的处理时长，包括：串联的两个处理模块中的上一个处理模块对第一测量报文处理完成后，将处理完成后的第一测量报文以及指示信号传输至下一个处理模块。这样，以接力的方式连续触发各处理模块对处理时延的测量。
根据第一方面，或者以上第一方面的任意一种实现方式，指定特征信息为以下至少之一：目的MAC地址信息、源MAC地址信息、目的IP地址信息、源IP地址信息、标签信息。这样，芯片可通过识别指定特征信息，例如上述任一地址的方式，对报文进行匹配。当匹配成功时，可对报文进行时延测量。
第二方面，本申请实施例提供一种网络设备。该网络设备包括：接收模块，用于接收第一测量报文；获取模块，用于获取至少一个处理模块中的每个处理模块对第一测量报文进行处理的处理时长；获取模块，还用于基于每个处理模块对第一测量报文进行处理的处理时长，获取至少一个处理模块对第一测量报文进行处理的处理总时长。
根据第二方面，第一测量报文包含指示信息，指示信息用于指示需要对第一测量报文的处理时长进行测量。
根据第二方面，或者以上第二方面的任意一种实现方式，接收模块，用于：响应于 接收到的第一测量报文，生成指示信号，指示信号用于指示至少一个处理模块开始对第一测量报文进行处理时，发送触发信号。
根据第二方面，或者以上第二方面的任意一种实现方式，接收模块，用于：响应于接收到的第一测量报文，识别第一测量报文是否包括指定特征信息；当识别到第一测量报文包括指定特征信息，生成指示信号，指示信号用于指示至少一个处理模块开始对第一测量报文进行处理时，发送触发信号。
根据第二方面，或者以上第二方面的任意一种实现方式，获取模块，用于：响应于接收到的每个处理模块发送的触发信号，记录每个处理模块对第一测量报文进行处理的起始时间。
根据第二方面，或者以上第二方面的任意一种实现方式，每个处理模块为串联连接，每个处理模块的处理时长为串联的两个处理模块的起始时间之差。
根据第二方面，或者以上第二方面的任意一种实现方式，串联的两个处理模块中的上一个处理模块对第一测量报文处理完成后，将处理完成后的第一测量报文以及指示信号传输至下一个处理模块。
根据第二方面，或者以上第二方面的任意一种实现方式，指定特征信息为以下至少之一：目的MAC地址信息、源MAC地址信息、目的IP地址信息、源IP地址信息、标签信息。
第二方面以及第二方面的任意一种实现方式分别与第一方面以及第一方面的任意一种实现方式相对应。第二方面以及第二方面的任意一种实现方式所对应的技术效果可参见上述第一方面以及第一方面的任意一种实现方式所对应的技术效果，此处不再赘述。
第三方面，本申请实施例提供了一种计算机可读介质，用于存储计算机程序，该计算机程序包括用于执行第一方面或第一方面的任意可能的实现方式中的方法的指令。
第三方面以及第三方面的任意一种实现方式分别与第一方面以及第一方面的任意一种实现方式相对应。第三方面以及第三方面的任意一种实现方式所对应的技术效果可参见上述第一方面以及第一方面的任意一种实现方式所对应的技术效果，此处不再赘述。
第四方面，本申请实施例提供了一种计算机程序，该计算机程序包括用于执行第一方面或第一方面的任意可能的实现方式中的方法的指令。
第四方面以及第四方面的任意一种实现方式分别与第一方面以及第一方面的任意一种实现方式相对应。第四方面以及第四方面的任意一种实现方式所对应的技术效果可参见上述第一方面以及第一方面的任意一种实现方式所对应的技术效果，此处不再赘述。
第五方面，本申请实施例提供了一种芯片，该芯片包括处理电路、收发管脚。其中，该收发管脚、和该处理电路通过内部连接通路互相通信，该处理电路执行第一方面或第一方面的任一种可能的实现方式中的方法，以控制接收管脚接收信号，以控制发送管脚发送信号。
第五方面以及第五方面的任意一种实现方式分别与第一方面以及第一方面的任意一种实现方式相对应。第五方面以及第五方面的任意一种实现方式所对应的技术效果可参见上述第一方面以及第一方面的任意一种实现方式所对应的技术效果，此处不再赘述。
第五方面，本申请实施例提供了一种网络设备。该网络设备可以用于通过数据链路向目的设备发送第一报文，数据链路中包括至少一个中间设备。网络设备还用于接收至少一个中间设备中的每个中间设备发送的第一处理时延信息，第一处理时延信息用于指示中间设备中的至少一个处理模块对第一报文进行处理的处理时长；以及，接收目的设备发送的第二处理时延信息，第二处理时延信息用于指示目的设备中的至少一个处理模块对第一报文进行处理的处理时长。网络设备还用于根据第一处理时延信息和第二处理时延信息，确定至少一个中间设备与目的设备中是否存在故障处理模块。这样，网络设备可基于各设备反馈的各处理模块对应的处理时长，对故障模块进行定位，从而实现链路上的转发故障的精准定位，可快速定位到故障设备及故障模块。
附图说明
图1为示例性示出的通信系统示意图；
图2为示例性示出的设备的结构示意图；
图3a为示例性示出的芯片的结构示意图；
图3b为示例性示出的测量流程示意图；
图4为示例性示出的芯片的结构示意图；
图5为示例性示出的芯片的结构示意图；
图6为本申请实施例提供的一种通信装置的结构示意图；
图7为本申请实施例提供的一种芯片的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。
本申请实施例的说明书和权利要求书中的术语“第一”和“第二”等是用于区别不同的对象，而不是用于描述对象的特定顺序。例如，第一目标对象和第二目标对象等是 用于区别不同的目标对象，而不是用于描述目标对象的特定顺序。
在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
在本申请实施例的描述中，除非另有说明，“多个”的含义是指两个或两个以上。例如，多个处理单元是指两个或两个以上的处理单元；多个系统是指两个或两个以上的系统。
在对本申请实施例的技术方案说明之前，首先结合附图对本申请实施例的通信系统进行说明。参见图1，为本申请实施例提供的一种通信系统示意图。该通信系统中包括设备1、设备2、设备3和设备4。设备1与设备2通信连接，设备2与设备3通信连接，设备3与设备4通信连接。设备1～设备4中的任意两个设备可进行通信。在本申请实施例具体实施的过程中，设备1～设备4中的设备可以为电脑、智能手机、服务器等设备。示例性的，设备1～设备4中的通信连接可以是有线的，也可以是无线的，本申请实施例中图1所示的连接关系以及设备数量仅为示意性举例，本申请对此不做限定。
图2是一种设备的结构示意图。在图2中：
设备中包括至少一个处理器101、至少一个存储器102、至少一个收发器103、至少一个网络接口104和一个或多个天线105。处理器101、存储器102、收发器103和网络接口104相连，例如通过总线相连。天线105与收发器103相连。网络接口104用于使得设备通过通信链路，与其它通信设备相连。在本申请实施例中，所述连接可包括各类接口、传输线或总线等，本实施例对此不做限定。应该理解的是，图2所示设备100仅是一个范例，并且设备100可以具有比图中所示的更多的或者更少的部件，可以组合两个或多个的部件，或者可以具有不同的部件配置。图2中所示出的设备可以是图1中的设备1～设备4中的任意设备。
本申请实施例中的处理器，例如处理器101，可以包括如下至少一种类型：通用中央处理器(Central Processing Unit，CPU)、数字信号处理器(Digital Signal Processor，DSP)、微处理器、特定应用集成电路专用集成电路(Application-Specific Integrated Circuit，ASIC)、微控制器(Microcontroller Unit，MCU)、现场可编程门阵列(Field Programmable Gate Array，FPGA)、或者用于实现逻辑运算的集成电路。例如，处理器101可以是一个单核(single-CPU)处理器或多核(multi-CPU)处理器。至少一个处理器101可以是集成在一个芯片中或位于多个不同的芯片上。
本申请实施例中的存储器，例如存储器102，可以包括如下至少一种类型：只读存储器(read-only memory，ROM)或可存储静态信息和指令的其他类型的静态存储设备，随机存取存储器(random access memory，RAM)或者可存储信息和指令的其他类型的动态存储设备，也可以是电可擦可编程只读存储器(Electrically erasable programmabler-only memory，EEPROM)。在某些场景下，存储器还可以是只读光盘(compact disc read-only memory，CD-ROM)或其他光盘存储、光碟存储(包括压缩光碟、激光碟、光碟、数字通用光碟、蓝光光碟等)、磁盘存储介质或者其他磁存储设备、或者能够用于携带或存 储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质，但不限于此。
存储器102可以是独立存在，与处理器101相连。可选的，存储器102也可以和处理器101集成在一起，例如集成在一个芯片之内。其中，存储器102能够存储执行本申请实施例的技术方案的程序代码，并由处理器101来控制执行，被执行的各类计算机程序代码也可被视为是处理器101的驱动程序。例如，处理器101用于执行存储器102中存储的计算机程序代码，从而实现本申请实施例中的技术方案。可选的，存储器102还可以在芯片之外，通过接口与处理器101相连。
收发器103可以用于支持设备与其它设备之间射频信号的接收或者发送，收发器103可以与天线105相连。收发器103包括发射机Tx和接收机Rx。具体地，一个或多个天线105可以接收射频信号，该收发器103的接收机Rx用于从天线接收所述射频信号，并将射频信号转换为数字基带信号或数字中频信号，并将该数字基带信号或数字中频信号提供给所述处理器101，以便处理器101对该数字基带信号或数字中频信号做进一步的处理，例如解调处理和译码处理。此外，收发器103中的发射机Tx还用于从处理器101接收经过调制的数字基带信号或数字中频信号，并将该经过调制的数字基带信号或数字中频信号转换为射频信号，并通过一个或多个天线105发送所述射频信号。具体地，接收机Rx可以选择性地对射频信号进行一级或多级下混频处理和模数转换处理以得到数字基带信号或数字中频信号，所述下混频处理和模数转换处理的先后顺序是可调整的。发射机Tx可以选择性地对经过调制的数字基带信号或数字中频信号时进行一级或多级上混频处理和数模转换处理以得到射频信号，所述上混频处理和数模转换处理的先后顺序是可调整的。数字基带信号和数字中频信号可以统称为数字信号。
结合上述如图1所示的通信系统示意图，下面介绍本申请的具体实施方案：
示例性的，在对图1中的通信系统的时延进行测试时，可由设备1～设备4中的任一设备发起时延测试流程。示例性的，本申请实施例中以设备1发起时延测试为例进行说明。
示例性的，设备1与设备4进行数据交互的过程中，设备2和设备3作为设备1与设备4之间的中间设备，可用于将设备1的数据转发至设备4，或者，将设备4的数据转发至设备1。
可选地，本申请实施例中所述的数据报文可以是以太网报文、IP报文、隧道报文等，本申请不做限定。
下面以具体应用场景对测试过程进行说明。
场景一
设备1向设备2发送报文，设备2将报文转发至设备3，设备3将报文转发至设备4。在设备1向设备4发送报文的过程中，若该报文的转发延时较大，用户可触发设备1对该报文的传输延时进行测试。
示例性的，设备1接收到用户指令，该用户指令用于指示对指定的报文进行测试。示例性的，指定的报文可以是基于报文地址进行指示。例如，用户指令可用于指示对具有指定地址(例如设备4)的报文进行测试，也就是说，设备1响应于用户指令，将发起 对具有指定地址的报文的传输时延的测试。示例性的，指定的报文也可以是基于报文的类型进行指示。例如，用户指令可用于指示对具有指定类型的报文进行测试。也就是说，设备1响应于用户指令，将发起对具有指定类型的报文的传输时延的测试。
在一种可能的实现方式中，用户除可以触发设备对指定的报文进行测试，还可以触发设备对指定的传输路径进行测试。例如，用户指令可用于指示设备1对设备1与设备4之间的转发路径进行测试。转发路径包括设备1、设备2、设备3和设备4。在该场景中，设备1可以基于在该传输路径上传输的任一报文，对该传输路径的传输时延进行测试。示例性的，设备1也可以生成测试报文，例如生成Ping报文，以进行测试。本申请不做限定。也就是说，本申请实施例中，对传输路径上的传输时延进行测试时，可以是数据报文，也可以是基于测试报文，本申请不做限定。其中，若基于数据报文进行设置，则数据报文中除携带有设备1发送给设备4的数据外，还携带有指示信息，用于指示传输路径上的各设备对本设备的时延进行测试。
示例性的，本申请实施例中以用户指示设备1对发送给设备4的报文，即具有指定地址(设备4的地址)的报文进行测试的方式为例进行说明。示例性的，设备1响应于接收到的用户指令，生成数据报文。该数据报文中包括但不限于：设备1的地址信息、设备4的地址信息、数据信息以及指示信息。其中，指示信息即用于指示传输路径上的各设备基于该数据报文，对本设备的时延进行测试。
示例性的，指示信息可被携带在数据报文的指定字段中。可选地，指定字段可以被包含于数据报文的报文头部，也可以被包含于数据报文的数据部分等。本申请不做限定。需要说明的是，传输路径上的各设备需要支持对指定字段进行解析。也就是说，各设备在接收到包含指示信息的报文时，可对报文中的指定字段进行正确解析，以获取到指示信息。
示例性的，设备1将生成的数据报文发送给设备2。需要说明的是，设备1～设备4之间的转发流程，例如，查询路径转发表等过程可参照已有技术实施例中的具体细节，本申请不再赘述。
示例性的，设备2接收到设备1发送的数据报文。设备2对数据报文进行解析，以获取到数据报文中的指定字段中的指示信息。设备2响应于获取到的指示信息，对设备2的传输时延进行测试。
下面对设备2对本设备的传输时延进行测试的流程进行详细说明。图3a为示例性示出设备2的芯片的结构示意图。请参照图3a，示例性的，芯片上包括但不限于：Profile(配置)模块301、处理模块302、处理模块303、处理模块304、处理模块305以及记录模块306。示例性的，Profile模块301与处理模块302连接、处理模块302与处理模块303连接、处理模块303与处理模块304连接，处理模块304与处理模块305连接、并且，处理模块302～处理模块305分别与记录模块306连接。可选地，各模块之间的连接可以是通过总线，也可以是基于其它线路，本申请不做限定。需要说明的是，图3a中的模块的名称以及数量仅为示意性举例，本申请不做限定。
在图3a的技术上，图3b为示例性示出的测量流程示意图。请参照图3b，示例性的，芯片300接收到数据报文。本申请实施例中，以指定字段携带于报文的头部为例进行说 明。
示例性的，Profile模块301可对数据报文中报头部分进行解析，以获取到所述指示信息。具体的，Profile模块301可存储有报文类型与指定字段的对应关系。如上文所述，本申请实施例中可应用于对不同类型的报文进行测试。可选地，不同的报文类型的指定字段可以不相同。相应的，Profile模块301可基于报文的头部，识别出报文的类型。并可基于报文类型与指定字段的对应关系，获取到与该报文的类型对应的指定字段。示例性的，Profile模块301可读取对应于该报文的指定字段，以检测该报文是否携带指定信息。在本申请实施例中，以Profile模块301读取到数据报文中携带指示信息为例进行说明。需要说明的是，若未读取到指示信息，则说明该数据报文无需进行传输时延测试，按照正常处理流程进行处理即可。
示例性的，Profile模块301检测到数据报文携带指示信息，确定需要对该数据报文进行传输时延的测试。示例性的，Profile模块301在检测到指示信息后，生成指示信号。其中，指示信号用于指示芯片中对数据报文进行处理的至少一个模块进行传输时延测试。
仍参照图3b，示例性的，Profile模块301将指示信号输出至处理模块302。处理模块302从芯片的接口获取到数据报文，并且，接收到Profile模块301输入的指示信号。
可选地，各处理模块之间在传输数据报文的同时，还可以传输vld(valid)信号，以指示正在传输的报文为有效报文。需要说明的是，该信号的传输以及生成经过可参照已有技术中的实施例，本申请不再赘述。
示例性的，处理模块302接收到数据报文以及指示信号。处理模块302响应于接收到的指示信号，可确定需要对该数据报文的传输时延进行测试。示例性的，处理模块302可生成触发信号1，并将触发信号1输出至记录模块306。同时，处理模块302对数据报文进行相应处理。
需要说明的是，本申请实施例中的各处理模块对报文处理的方式可以相同，也可以不同。
进一步需要说明的是，本申请实施例中的芯片中可以包括更多的模块。例如，芯片中可以包括10个处理模块，而对所述数据报文进行处理的处理模块仅为部分处理模块，例如图3b中的处理模块302～处理模块305。其它处理模块可能不做任何处理。芯片中的各模块可基于接收到的报文的类型使能。也就是说，对于不同类型的报文，芯片中使能的模块可以相同，也可以不同。本申请不做限定。在本申请实施例中，在测量传输时延时，仅统计对报文进行处理的至少一个处理模块的时延。
请继续参照图3，示例性的，记录模块306可设置有多个寄存器。每个寄存器对应一个处理模块。需要说明的是，如上文所述，芯片中可能包括更多的处理模块，例如10个模块，寄存器中可选地包括10个寄存器，每个寄存器对应一个处理模块。
示例性的，记录模块接收到处理模块302输入的触发信号1。可选地，记录模块306可基于与处理模块302之间的连接通路，确定触发信号1是由处理模块302输入的。相应的，记录模块可查询到对应于处理模块302的寄存器(例如寄存器1)，并将当前时间对应的时间戳写入寄存器1中。
可选地，记录模块306维持的时钟可以是与现实世界的时钟相同的。可选地，记录 模块306维持的时钟也可以是相对时钟，例如，记录模块306维持的时钟是从设备1启动后开始计时的。本申请不做限定。可选地，记录模块306维持的时钟也可以是周期性更新的，以保证记录的时钟的准确性。
示例性的，处理模块302对数据报文进行处理后，向处理模块303输出该数据报文和指示信号。可选地，处理模块302还可以向处理模块303输出vld信号(概念可参照上文)。
示例性的，处理模块303接收到数据报文和指示信号。处理模块303响应于接收到的指示信号，确定需要对数据报文进行传输时延测量。处理模块303生成触发信号2，并向记录模块输出触发信号2。同时，处理模块303对数据报文进行处理。
示例性的，记录模块306接收到处理模块303输入的触发信号2，可将当前时间戳2记录到处理模块2对应的寄存器2中。其它细节可参照上文，此处不再赘述。
示例性的，处理模块304和处理模块305均执行上述步骤，相应的，记录模块306基于处理模块304和处理模块305输入的触发信号，记录对应的时间戳(包括时间戳3和时间戳4)。具体细节可参照处理模块302相关描述，此处不再赘述。
示例性的，处理模块305对数据报文处理后，将处理后的数据报文输出至其他芯片或设备(例如设备3)。
可选地，一个示例中，处理模块305对数据报文处理完成后，可向记录模块306发送触发信号5。相应的，记录模块306记录对应的时间戳。可以理解为，处理模块305发送的触发信号4对应的时间戳与处理模块305发送的触发信号5对应的时间戳之间的时间差，即为处理模块305的处理时长。另一个示例中，处理模块305的处理时长可以设置为预设值，也就是说，在后续的统计过程中，可基于预设值对芯片的处理总时长进行补偿，即加上处理模块305对应的处理时长的预设值。本申请实施例中，以处理模块305在处理完成后，发送触发信号5为例进行说明。
可选地，设备2中可包括一个或多个芯片。示例性的，若设备2中的多个芯片对数据报文进行处理。则每个芯片可执行与本申请实施例中所述芯片300相同的处理步骤。
举例说明，图4为示例性示出的设备2的结构示意图。请参照图4，示例性的，设备2中包括芯片300和芯片400。芯片300的描述可参照图3a和图3b，此处不再赘述。芯片400中包括但不限于：处理模块401、处理模块402、处理模块403和处理模块404，以及记录模块405。可选地，芯片2中可以包括Profile模块，也可以不包括Profile模块，本申请不做限定。
示例性的，芯片300中的各模块按照图3b所示的流程步骤进行处理后，处理模块305通过与芯片400之间的接口，将数据报文和指示信号输出至芯片400中的处理模块401。处理模块401接收到数据报文和指示信号，生成触发信号，并将触发信号输出至记录模块405。记录模块405可记录时间戳6。处理模块402～处理模块404的处理可参照芯片300中的描述，此处不再赘述。相应的，记录模块405可记录处理模块402～处理模块404对应的时间戳。
示例性的，仍以图3b中的芯片300为例。示例性的，芯片300中的记录模块306在接收到处理模块305输入的触发信号后，可选地将保存的多个时间戳(包括时间戳1～时 间戳5)输出至处理器。处理器可根据需求，对获取到的多个时间戳进行统计，以获取每个处理模块的传输时延(也可以称为处理时延或处理时长)，和/或，芯片300的处理总时长。该处理总时长即为芯片300在对数据报文进行传输(或转发)时的传输时延(也可以称为转发时延)。需要说明的是，上文所述处理器与芯片300为不同的器件，即，处理器在芯片300外，并通过总线等连接方式连接。
示例性的，处理模块302的传输时延即为时间戳1与时间戳2的差值(即时间戳2减时间戳1)。处理模块303的传输时延即为时间戳3与时间戳2的差值(即时间戳3减时间戳2)。处理模块304的传输时延即为时间戳4与时间戳3的差值(即时间戳4减时间戳3)。处理模块305的传输时延即为时间戳5与时间戳4的差值(即时间戳5减时间戳4)。
示例性的，芯片300的处理总时长的获取方式可以为每个处理模块的传输时延之和。示例性的，芯片300的处理总时长的获取方式还可以为时间戳1与时间戳5之间的差值(即时间戳5减之间戳1)。
处理器可向上层应用反馈获取到的测量结果。测量结果包括各处理模块的传输时延和/或芯片(即设备2)的传输时延。上层应用可将测量结果传输至设备1。
如上文所述，设备2对数据报文处理后，将数据报文发送至设备3。设备3和设备4可依次基于上文所述的测量方式，对传输时延进行测量，并将测量结果反馈至设备1。
示例性的，设备1可选地在显示窗口中显示各设备对应的测量结果。可选地，设备1还可以统计传输总时延。传输总时延即为各设备的传输时延相加。
示例性的，若传输总时延超过设定的阈值，设备1可基于获取到的多个测量结果对问题设备进行定位。举例说明，设备1可设置有对应于不同的设备或者是对应于设备中的各处理模块的处理时长(即传输时延)的范围。若某个设备的传输时延大于设定的阈值，则可确定该设备为问题设备(或故障设备)。示例性的，设备1可进一步基于该设备中各处理模块对应的时延，以及预设的各模块对应的范围进行比较，以进一步确定问题模块。
需要说明的是，一个示例中，若设备1～设备4的时钟同步，则设备1可基于每个设备对应的时间戳，获取到设备间的传输时延。例如，设备2的最后一个时间戳与设备3的第一个时间戳之间的差值，即为设备2将报文传输至设备3的过程所占时长(即传输时延)。另一个示例中，若设备1～设备4的时钟不同步。可选地，设备1可获取设备1将报文传输至设备4的总时长，该总时长可以是通过Ping报文获取到的。该总时长中包括各设备的处理时长以及设备之间传输报文时的传输时延。示例性的，设备1可获取总时长与通过测量的方式获取到的各设备处理时长的总和，以获取实际传输报文的传输时延。示例性的，在测量获取到的各设备处理时长均小于设定的阈值，即各设备未出现异常的情况下，若实际传输报文的传输时延大于设定的阈值，则可确定影响报文传输的因素为设备间的传输线缆。线缆的故障定位可参照已有技术，本申请不做限定。
在一种可能的实现方式中，图5为示例性示出的芯片500的结构示意图。芯片500包括但不限于：Profile模块501、处理模块502、处理模块503、处理模块504、处理模块505、处理模块506以及记录模块507。示例性的，处理模块503对数据报文处理方式 为保存数据报文。也就是说，处理模块503的处理不会对数据报文的传输时延产生影响。可选地，Profile模块501可向处理模块502发送数据报文和指示信号，以指示处理模块502对数据报文进行传输时延测量。Profile模块可向处理模块503发送数据报文，而不发送指示信号。处理模块503对数据报文进行相应处理。另一个示例中，Profile模块501可向处理模块502和处理模块503发送数据报文和指示信号。处理模块503接收到数据报文和指示信号后，不生成触发信号，仅对数据报文进行相应处理。又一个示例中，Profile模块501可向处理模块502和处理模块503发送数据报文和指示信号。在该示例中，处理模块502和处理模块503可以看作为并行处理模块。处理模块502和处理模块503可生成触发信号，并将触发信号输出至记录模块507。相应的，处理器在统计处理模块的处理时长时，可基于处理模块502和处理模块503的时间戳，确定处理模块502和处理模块503为并行处理模块。对于并行处理模块，处理器可将处理时长最长的模块对应的处理时长作为并行处理模块的传输时延。
在另一种可能的实现方式中，可以提前设置关键模块，其中，关键模块为对报文进行处理的多个处理模块中的一个或多个处理模块。也就是说，在本申请实施例中，可以只统计多个处理模块中的至少一个处理模块的处理时延。
在一种可能的实现方式中，设备1也可以周期性地发起上述测试流程，以实现自动传输时延的自动检测。
需要说明的是，上文实施例中，芯片的传输时延可选地为各处理模块的时延总和。示例性的，在理想状态下，处理模块的处理时延与记录的时间戳差值相等。但是，由于处理模块向记录模块输出触发信号，触发信号的传输以及记录模块响应也可能存在一定的时延。可选地，该时延可以为设定为默认数值，在统计各处理模块的传输时延时，可减去该设定的默认数值。可选地，由于各处理模块与记录模块之间距离不同，各处理模块的触发信号的传输时延也不相同。相应的，处理器可预先记录各处理模块对应的触发信号传输时延，各处理模块对应的触发信号传输时延可以相同，也可以不同，本申请不做限定。在统计个处理模块的传输时延时，可减去各模块对应的触发信号传输时延。可选地，由于该触发信号的传输时延相对较小，也可以忽略不计。
进一步需要说明的是，Profile模块的处理也占用一定的时长。可选地，Profile模块的处理时长也可以为设定的默认数值，在统计芯片的传输时延时，可减去Profile模块的设定的默认数值。可选地，Profile模块的处理时长相对较小，也可以忽略不计。
进一步需要说明的是，多个设备之间的时间可以是同步的，也可以是不同步的。也就是说，即使多个设备之间的时间不同步，也不会影响单个设备的传输时延的统计。
场景二
设备1向设备2发送报文，设备2将报文转发至设备3，设备3将报文转发至设备4。在设备1向设备4发送报文的过程中，若该传输路径上的报文的转发延时较大，用户可触发设备1～设备4对该报文的传输延时进行测试。举例说明，如上文所述，报文包括但不限于地址信息和数据信息，其中，地址信息包括源地址信息和目的地址信息。
示例性的，用户可通过设备1下发指令，或者通过手动配置的方式，分别对设备1～ 设备4中的至少一个设备进行配置。设备1～设备4响应于接收到的用户指令，更新Profile模块的匹配方式，以使得Profile模块可识别包含指定特征信息的数据报文。可以理解为，通过该种识别方式，可以触发传输路径上的任一设备进行时延测试。可选地，也可以进一步将识别方式配置为周期性的，例如，每个周期(例如10分钟)对包含指定特征信息的报文进行时延测试。
可选地，指定特征信息包括但不限于报文中的目的地址信息和源地址信息。其中，目的地址信息和源地址信息可以为目的MAC(Media Access Control Address，媒体存取控制位址)地址信息和源MAC地址信息，也可以是目的IP(Internet Protocol Address，互联网协议地址)地址信息和源IP地址信息，本申请不做限定。
示例性的，Profile模块接收到报文后，可对报文的地址信息进行识别。示例性的，若识别到报文携带有指定地址信息，则触发芯片中的其它处理模块对该报文进行时延测试。其它未描述细节可参照场景一中的描述，此处不再赘述。
下面介绍本申请实施例提供的一种装置。如图6所示：
图6为本申请实施例提供的一种通信装置的结构示意图。如图6所示，该通信装置600可包括：处理器601、收发器605，可选的还包括存储器602。
所述收发器605可以称为收发单元、收发机、或收发电路等，用于实现收发功能。收发器605可以包括接收器和发送器，接收器可以称为接收机或接收电路等，用于实现接收功能；发送器可以称为发送机或发送电路等，用于实现发送功能。
存储器602中可存储计算机程序或软件代码或指令604，该计算机程序或软件代码或指令604还可称为固件。处理器601可通过运行其中的计算机程序或软件代码或指令603，或通过调用存储器602中存储的计算机程序或软件代码或指令604，对MAC层和PHY层进行控制，以实现本申请下述各实施例提供的OM协商方法。其中，处理器601可以为中央处理器(central processing unit，CPU)，存储器602例如可以为只读存储器(read-only memory，ROM)，或为随机存取存储器(random access memory，RAM)。
本申请中描述的处理器601和收发器605可实现在集成电路(integrated circuit，IC)、模拟IC、射频集成电路RFIC、混合信号IC、专用集成电路(application specific integrated circuit，ASIC)、印刷电路板(printed circuit board，PCB)、电子设备等上。
上述通信装置600还可以包括天线606，该通信装置600所包括的各模块仅为示例说明，本申请不对此进行限制。
如前所述，以上实施例描述中的通信装置可以是接入点或者站点，但本申请中描述的通信装置的范围并不限于此，而且通信装置的结构可以不受图29的限制。通信装置可以是独立的设备或者可以是较大设备的一部分。例如所述通信装置的实现形式可以是：
(1)独立的集成电路IC，或芯片，或，芯片系统或子系统；(2)具有一个或多个IC的集合，可选的，该IC集合也可以包括用于存储数据，指令的存储部件；(3)可嵌入在其他设备内的模块；(4)其他等等。
对于通信装置的实现形式是芯片或芯片系统的情况，可参见图7所示的芯片的结构示意图。图7所示的芯片包括处理器701和接口702。其中，处理器701的数量可以是一 个或多个，接口702的数量可以是多个。可选的，该芯片或芯片系统可以包括存储器703。
其中，上述方法实施例涉及的各步骤的所有相关内容均可以援引到对应功能模块的功能描述，在此不再赘述。
基于相同的技术构思，本申请实施例还提供一种计算机可读存储介质，该计算机可读存储介质存储有计算机程序，该计算机程序包含至少一段代码，该至少一段代码可由电子设备执行，以控制电子设备用以实现上述方法实施例。
基于相同的技术构思，本申请实施例还提供一种计算机程序，当该计算机程序被电子设备执行时，用以实现上述方法实施例。
所述程序可以全部或者部分存储在与处理器封装在一起的存储介质上，也可以部分或者全部存储在不与处理器封装在一起的存储器上。
基于相同的技术构思，本申请实施例还提供一种处理器，该处理器用以实现上述方法实施例。上述处理器可以为芯片。
基于相同的技术构思，本申请实施例还提供一种通信系统，该通信系统包括上述方法实施例中各节点和控制设备。
结合本申请实施例公开内容所描述的方法或者算法的步骤可以硬件的方式来实现，也可以是由处理器执行软件指令的方式来实现。软件指令可以由相应的软件模块组成，软件模块可以被存放于随机存取存储器(Random Access Memory，RAM)、闪存、只读存储器(Read Only Memory，ROM)、可擦除可编程只读存储器(Erasable Programmable ROM，EPROM)、电可擦可编程只读存储器(Electrically EPROM，EEPROM)、寄存器、硬盘、移动硬盘、只读光盘(CD-ROM)或者本领域熟知的任何其它形式的存储介质中。一种示例性的存储介质耦合至处理器，从而使处理器能够从该存储介质读取信息，且可向该存储介质写入信息。当然，存储介质也可以是处理器的组成部分。处理器和存储介质可以位于ASIC中。另外，该ASIC可以位于网络设备中。当然，处理器和存储介质也可以作为分立组件存在于网络设备中。
本领域技术人员应该可以意识到，在上述一个或多个示例中，本申请实施例所描述的功能可以用硬件、软件、固件或它们的任意组合来实现。当使用软件实现时，可以将这些功能存储在计算机可读介质中或者作为计算机可读介质上的一个或多个指令或代码进行传输。计算机可读介质包括计算机存储介质和通信介质，其中通信介质包括便于从一个地方向另一个地方传送计算机程序的任何介质。存储介质可以是通用或专用计算机能够存取的任何可用介质。
上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本申请的保护之内。

Claims (20)

  1. 一种测量方法，其特征在于，包括：
    接收第一测量报文；
    获取至少一个处理模块中的每个处理模块对所述第一测量报文进行处理的处理时长；
    基于所述每个处理模块对所述第一测量报文进行处理的处理时长，获取所述至少一个处理模块对所述第一测量报文进行处理的处理总时长。
  2. 根据权利要求1所述的方法，其特征在于，所述第一测量报文包含指示信息，所述指示信息用于指示需要对所述第一测量报文的处理时长进行测量。
  3. 根据权利要求2所述的方法，其特征在于，所述接收第一测量报文，包括：
    响应于接收到的所述第一测量报文，生成指示信号，所述指示信号用于指示所述至少一个处理模块开始对所述第一测量报文进行处理时，发送触发信号。
  4. 根据权利要求1所述的方法，其特征在于，所述接收第一测量报文，包括：
    响应于接收到的所述第一测量报文，识别所述第一测量报文是否包括指定特征信息；
    当识别到所述第一测量报文包括所述指定特征信息，生成指示信号，所述指示信号用于指示所述至少一个处理模块开始对所述第一测量报文进行处理时，发送触发信号。
  5. 根据权利要求3或4所述的方法，其特征在于，所述获取至少一个处理模块中的每个处理模块对所述第一测量报文进行处理的处理时长，包括：
    响应于接收到的每个处理模块发送的触发信号，记录所述每个处理模块对所述第一测量报文进行处理的起始时间。
  6. 根据权利要求5所述的方法，其特征在于，所述每个处理模块为串联连接，所述每个处理模块的处理时长为串联的两个处理模块的起始时间之差。
  7. 根据权利要求6所述方法，其特征在于，所述获取至少一个处理模块中的每个处理模块对所述第一测量报文进行处理的处理时长，包括：
    串联的两个处理模块中的上一个处理模块对所述第一测量报文处理完成后，将处理完成后的所述第一测量报文以及所述指示信号传输至下一个处理模块。
  8. 根据权利要求4所述的方法，其特征在于，所述指定特征信息为以下至少之一：
    目的MAC地址信息、源MAC地址信息、目的IP地址信息、源IP地址信息、标签信息。
  9. 一种网络设备，其特征在于，包括：
    接收模块，用于接收第一测量报文；
    获取模块，用于获取至少一个处理模块中的每个处理模块对所述第一测量报文进行处理的处理时长；
    所述获取模块，还用于基于所述每个处理模块对所述第一测量报文进行处理的处理时长，获取所述至少一个处理模块对所述第一测量报文进行处理的处理总时长。
  10. 根据权利要求9所述的装置，其特征在于，所述第一测量报文包含指示信息，所述指示信息用于指示需要对所述第一测量报文的处理时长进行测量。
  11. 根据权利要求10所述的装置，其特征在于，所述接收模块，用于：
    响应于接收到的所述第一测量报文，生成指示信号，所述指示信号用于指示所述至少一个处理模块开始对所述第一测量报文进行处理时，发送触发信号。
  12. 根据权利要求10所述的装置，其特征在于，所述接收模块，用于：
    响应于接收到的所述第一测量报文，识别所述第一测量报文是否包括指定特征信息；
    当识别到所述第一测量报文包括所述指定特征信息，生成指示信号，所述指示信号用于指示所述至少一个处理模块开始对所述第一测量报文进行处理时，发送触发信号。
  13. 根据权利要求11或12所述的装置，其特征在于，所述获取模块，用于：
    响应于接收到的每个处理模块发送的触发信号，记录所述每个处理模块对所述第一测量报文进行处理的起始时间。
  14. 根据权利要求12所述的装置，其特征在于，所述每个处理模块为串联连接，所述每个处理模块的处理时长为串联的两个处理模块的起始时间之差。
  15. 根据权利要求13所述装置，其特征在于，串联的两个处理模块中的上一个处理模块对所述第一测量报文处理完成后，将处理完成后的所述第一测量报文以及所述指示信号传输至下一个处理模块。
  16. 根据权利要求9所述的装置，其特征在于，所述指定特征信息为以下至少之一：
    目的MAC地址信息、源MAC地址信息、目的IP地址信息、源IP地址信息、标签信息。
  17. 一种装置，其特征在于，包括至少一个处理器和接口；所述处理器通过所述接口接收或发送数据；所述至少一个处理器被配置为调用存储在存储器中的软件程序，以执行如权利要求1至7任一项所述的方法。
  18. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质存储有计算机程序，当所述计算机程序运行在计算机或处理器上时，使得所述计算机或所述处理器执行如权利要求1至7任一项所述的方法。
  19. 一种计算机程序产品，其特征在于，所述计算机程序产品包含软件程序，当所述软件程序被计算机或处理器执行时，使得权利要求1至7任一项所述的方法被执行。
  20. 一种网络设备，其特征在于，包括：
    通过数据链路向目的设备发送第一报文，所述数据链路中包括至少一个中间设备；
    接收所述至少一个中间设备中的每个中间设备发送的第一处理时延信息，所述第一处理时延信息用于指示所述中间设备中的至少一个处理模块对所述第一报文进行处理的处理时长；以及，
    接收所述目的设备发送的第二处理时延信息，所述第二处理时延信息用于指示所述目的设备中的至少一个处理模块对所述第一报文进行处理的处理时长；
    根据所述第一处理时延信息和所述第二处理时延信息，确定所述至少一个中间设备与所述目的设备中是否存在故障处理模块。
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