WO2022199043A1

WO2022199043A1 - Method and system for implementing vsetli instruction in risv_v vector instruction set

Info

Publication number: WO2022199043A1
Application number: PCT/CN2021/129454
Authority: WO
Inventors: 李长林; 张弛
Original assignee: 广东赛昉科技有限公司
Priority date: 2021-03-22
Filing date: 2021-11-09
Publication date: 2022-09-29

Abstract

The present invention relates to the technical field of CPUs, and in particular, to a method and system for implementing a vsetli instruction in a risv_v vector instruction set. The method comprises: when a CPU executes out of order, allocating vectag[n:0] information in a rename module and determine whether an instruction is vsetli; if the instruction is vsetli, adding 1 to vectag, and if the instruction is not a vsetli instruction, keeping the vectag unchanged; transmitting to an execution unit, and distributing the vsetli instruction to a csr module; distributing corresponding other vector instructions to a vpu module; when it is determined that the vectag of the instruction is consistent with vectag broadcasted by ROB, transmitting the instruction from a reserver station to the execution unit; and after execution of the instruction is completed, graduating in sequence in the ROB module, updating vectag of a register at the time of graduation, and ending the execution. In the present invention, the execution efficiency of a non-vsetl{i}Vector instruction is high. Data is selected using a mask mode, and thus, the power consumption is reduced; moreover, the execution period can be reduced, the latency is reduced, and the present invention has a wide market application prospect.

Description

Implementation method and system of risv_v vector instruction set vsetli instruction

technical field

The invention relates to the technical field of CPUs, in particular to a method and a system for implementing a risv_v vector instruction set vsetli instruction.

Background technique

The isc_v instruction set has only recently announced the complete instruction set, and there are basically no implementations that can be referred to at present. In order to achieve simplicity, the easiest way is to refresh the pipeline when the vsetli instruction graduates, and at the same time, the execution unit, regardless of the inactive element part, is sent to the execution unit for execution, resulting in an increase in the execution cycle.

The existing vsetli instruction needs to refresh the pipeline when it graduates, resulting in low CPU execution efficiency. The Vector instruction is also executed in the execution unit for the inactive element part. Finally, the data is selected by the mask method. In fact, the mask data is originally There is no need to enter the execution unit, which results in a waste of power consumption and an increase in the execution cycle of the instruction.

SUMMARY OF THE INVENTION

Aiming at the deficiencies of the prior art, the present invention discloses a method and a system for implementing a risv_v vector instruction set vsetli instruction, which are used to solve the above-mentioned problems.

The present invention is achieved through the following technical solutions:

In the first aspect, the present invention discloses a method for realizing a risv_v vector instruction set vsetli instruction, comprising the following steps:

When the S1CPU executes out of order, it allocates vectag[n:0] information in the rename module to determine whether the instruction is vsetli;

S2 If the instruction is vsetli, vectag+1 will be added, and if it is not a vsetli instruction, the vectag will remain unchanged;

S3 is sent to the execution unit, and the vsetli instruction is distributed to the csr module; the corresponding other vector instructions are distributed to the vpu module;

When S4 judges that the instruction vectag is consistent with the vectag broadcast by the ROB, the instruction is transmitted from the serverstation to the execution unit;

The execution of the S5 instruction is completed, and in the ROB module, it graduates in sequence, and the register vectag is updated when it graduates, and the execution ends.

Further, in the method, 0-5 instructions are issued in each cycle.

Further, in the method, if the vsetli instruction is accepted, the cycle only transmits the vsetli, and each cycle is assigned a vectag, and other instructions wait until the next cycle to transmit.

Further, in the method, the inactive is transmitted to the execution unit, and 2*ncycles are executed to complete, the inactive is not transmitted to the execution unit, and the execution is completed for n cycles.

Further, in the described method, the instruction vectag in the vpu module reserve station needs to be compared with the register vectag, and only in the case of consistency, the instruction can be transmitted to the execution unit.

Further, in the method, vectag[n:0] is allocated in the rename as a condition for the vpu instruction to be sent to the execution unit, so that the pipeline is not refreshed when the vsetli instruction is executed.

In a second aspect, the present invention discloses a system for implementing a risv_v vector instruction set vsetli instruction, the system is used for implementing the risv_v vector instruction set vsetli instruction implementation method described in the first aspect, including a rename module, a dispatch module, a vpu modules and ROB modules.

The beneficial effects of the present invention are:

The non-vsetl{i}Vector instruction of the present invention only needs to be executed according to the youngest instruction in the vsetl{i} older than itself before entering the execution unit, which is much higher than the current refresh pipeline efficiency.

The Vector instruction of the present invention is also executed in the execution unit for the part of the inactive element, and finally the data is selected by means of a mask, which can reduce power consumption, and at the same time, can reduce the execution cycle and latency.

Description of drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained according to these drawings without creative efforts.

Fig. 1 is a kind of principle step diagram of the realization method of risv_v vector instruction set vsetli instruction;

2 is a basic block diagram of an out-of-order CPU according to an embodiment of the present invention;

FIG. 3 is a comparison block diagram of unactive emission according to an embodiment of the present invention.

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments These are some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

Example 1

The present embodiment discloses a method for realizing a risv_v vector instruction set vsetli instruction as shown in FIG. 1 , including the following steps:

When S4 judges that the instruction vectag is consistent with the vectag broadcast by the ROB, the instruction is transmitted from the server station to the execution unit;

In this embodiment, 0-5 instructions are issued in each cycle. If the vsetli instruction is accepted, the cycle only emits vsetli, each cycle is assigned a vectag, and other instructions wait until the next cycle to launch.

In this embodiment, the inactive is transmitted to the execution unit, and the execution is completed in 2*n cycles, and the inactive is not transmitted to the execution unit, and the execution is completed in n cycles.

In this embodiment, the instruction vectag in the reserve station of the vpu module needs to be compared with the register vectag, and the instruction can be transmitted to the execution unit only when they are consistent.

In this embodiment, vectag[n:0] is allocated in rename as a condition for the vpu instruction to be sent to the execution unit, so that the pipeline is not refreshed when the vsetli instruction is executed.

In this embodiment, the pipeline does not need to be refreshed when the vsetli instruction is graduated, and the inactive element part does not need to be sent to the execution unit for execution, which can reduce power consumption and execution cycle.

Example 2

This embodiment refers to an out-of-order CPU, and its basic block is shown in FIG. 2 . This embodiment discloses a system for implementing a risv_v vector instruction set vsetli instruction, which includes four modules: rename, dispatch, ROB, and vpu.

In the rename module of this embodiment, a vectag[n:0] information will be allocated in the rename module. If it is vsetli, vectag+1 will be added, and the vectag of non-vsetli instructions will remain unchanged. The executed instruction can be sent to the execution unit for execution only when the vectag of the instruction in the reserve station is consistent with the vectage broadcasted by the csr.

The function of the dispatch module in this embodiment is to distribute instructions to different datapaths according to the type of the instructions, corresponding to the vsetli instruction, distribute them to the csr module; corresponding to other vector instructions, distribute them to the vpu module. Each cycle can issue 5 instructions. If a vsetli instruction is encountered, the cycle will only issue vsetli, and other instructions will wait until the next cycle to issue, so only one vectag needs to be allocated for each cycle.

In the vpu module of this embodiment, the vector instruction datapath, an important condition for the instruction to be transmitted from the reserverstation (reservation station) to the execution unit is that the instruction vectag of this entry needs to be consistent with the vectag broadcasted by the ROB before it can be transmitted to the execution unit. As shown in Figure 3, transmitting the inactive to the execution unit requires 2*n cycles to complete. If the inactive is not transmitted to the execution unit, only n cycles are required to complete. It can reduce power consumption while reducing latency.

In the ROB module of this embodiment, after each instruction is executed, it must be graduated in sequence, and the register vectag will be updated at the same time when the instruction is graduated.

The vectag allocation updates the vectage register, and the timeline table of the conditions that the vector instruction can emit is as follows

To sum up, the non-vsetl{i}Vector instruction of the present invention only needs to be executed according to the youngest instruction in the vsetl{i} older than itself before entering the execution unit, which is much more efficient than the current refresh pipeline. The refresh pipeline needs to start from a new instruction fetch, instead of refreshing just waiting in the reservation station, and waiting until the youngest instruction in the vsetl{i} older than itself is executed before it can be executed in the execution unit.

The above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The recorded technical solutions are modified, or some technical features thereof are equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

A realization method of risv_v vector instruction set vsetli instruction, is characterized in that, described method comprises the following steps:

When the S1CPU executes out of order, it allocates vectag[n:0] information in the rename module to determine whether the instruction is vsetli;

S2 If the instruction is vsetli, vectag+1 will be added, and if it is not a vsetli instruction, the vectag will remain unchanged;

S3 is sent to the execution unit, and the vsetli instruction is distributed to the csr module; the corresponding other vector instructions are distributed to the vpu module;

When S4 judges that the instruction vectag is consistent with the vectag broadcast by the ROB, the instruction is transmitted from the server station to the execution unit;

The execution of the S5 instruction is completed, and in the ROB module, it graduates in sequence, and the register vectag is updated when it graduates, and the execution ends.
The realization method of risv_v vector instruction set vsetli instruction according to claim 1, is characterized in that, in described method, each cycle transmits 0-5 instruction.
The method for realizing the risv_v vector instruction set vsetli instruction according to claim 2, wherein in the method, if the vsetli instruction is accepted, the cycle only transmits the vsetli, and each cycle allocates a vectag, and other instructions wait until the next cycle and launch again.
The method for realizing the risv_v vector instruction set vsetli instruction according to claim 1, wherein in the method, inactive is sent to the execution unit, and 2*n cycles are executed to complete, the inactive is not sent to the execution unit, and n is executed. cycle is complete.
The realization method of risv_v vector instruction set vsetli instruction according to claim 1, is characterized in that, in the described method, the instruction vectag in the vpu module reserve station all needs to compare with the register vectag, only under the consistent situation, this instruction can Emitted to the execution unit.
The realization method of risv_v vector instruction set vsetli instruction according to claim 1, is characterized in that, in described method, in rename, allocate vectag[n:0], as a condition that vpu instruction is transmitted to execution unit, in order to The pipeline is not flushed when executing vsetli instructions.
A realization system of risv_v vector instruction set vsetli instruction, described system is used for carrying out the realization method of risv_v vector instruction set vsetli instruction as described in any one of claim 1-6, it is characterized in that, comprise rename module, dispatch module , vpu module and ROB module.