WO2022198530A1

WO2022198530A1 - Semiconductor device and manufacturing method therefor

Info

Publication number: WO2022198530A1
Application number: PCT/CN2021/082845
Authority: WO
Inventors: 郑辉; 高山; 刘长泽
Original assignee: 华为技术有限公司
Priority date: 2021-03-24
Filing date: 2021-03-24
Publication date: 2022-09-29
Also published as: CN116982149A

Abstract

The present application provides a semiconductor device and a manufacturing method therefor. The semiconductor device comprises a silicon substrate and a first dielectric layer on a surface thereof; a through substrate via is provided in the silicon substrate; a first through hole is provided in the first dielectric layer; the first through hole is in communication with the through substrate via, and a difference between the diameter of one end of the first through hole facing the silicon substrate and the diameter of one end of the through substrate via facing the first through hole is within 20%; an insulating layer and a substrate conductor located therein are provided on the inner wall of the through substrate via, and the insulating layer is located between the substrate conductor and the inner wall of the through substrate via; a first metal barrier layer is provided on an inner wall of the first through hole, a first conductor is provided in the first through hole, and the first metal barrier layer is located between the first conductor and the inner wall of the first through hole and is in direct contact with the inner wall of the first through hole. In the semiconductor device of the present application, damage to the first through hole caused by over-deep etching depth can be avoided, and no insulating layer is provided in the first dielectric layer, thereby avoiding the effect of moisture, and increasing the flow capacity.

Description

Semiconductor device and method of making the same

technical field

The present application relates to the technical field of semiconductors, and in particular, to a semiconductor device and a preparation method thereof.

Background technique

Continuing to maintain Moore's Law is increasingly difficult as integrated circuit manufacturing process constraints continue. Three-dimensional integrated circuit (3DIC) integrates chips in the vertical direction, and can use lower-tech manufacturing processes to achieve high performance in the same area, so 3DIC is an important way to maintain and surpass Moore's Law. Silicon Through-via (TSV) is the key technology to realize 3DIC, which provides vertical power and signal channels to stacked chips through metal through-holes that run through part or the entire chip. The typical process of TSV includes in substrate, FEOL and BEOL. TSV is formed by etching. When it is necessary to vertically interconnect the electronic components on the substrate and the BEOL, one of the current methods is to directly form through holes through the BEOL and the substrate (as shown in Figure 2a). The etching depth of the hole is very deep, which will cause serious damage to the through hole in the interconnection layer 1, which will further reduce the insulation and time-dependent dielectric breakdown (TDDB) reliability of the low-k medium in the BEOL, and even cause the BEOL metal Oxidation and diffusion, electromigration (EM) reliability degradation, etc; shown), wherein the through hole 11 is used to realize the electrical connection in the vertical direction, the trench 12 is used to connect the device above, and the size of the through hole 11 is generally relatively small, so that the maximum current that the metal in the through hole 11 bears is limited , will become the bottleneck of the flow capacity of the TSV in the BEOL, limiting the flow capacity of the TSV, and the through hole 11 and the trench 12 in the TSV require two-step process etching, and the process is complicated.

SUMMARY OF THE INVENTION

The present application provides a semiconductor device in which the dielectric layer has better flow capacity and can reduce the etching damage of the dielectric layer.

In a first aspect, the present application provides a semiconductor device, including a silicon substrate, and a first dielectric layer provided on a surface of the silicon substrate;

The silicon substrate is provided with a substrate through hole;

The first medium layer is provided with a first through hole penetrating two opposite surfaces of the first medium layer;

The first through hole is connected to the substrate through hole, and the diameter of one end of the first through hole facing the silicon substrate and the diameter of the end of the substrate through hole facing the first through hole differ within 20%;

An insulating layer is arranged on the inner wall of the substrate through hole, a substrate conductor is arranged in the substrate through hole, and the insulating layer is located between the substrate conductor and the inner wall of the substrate through hole;

A first metal barrier layer is arranged on the inner wall of the first through hole, a first conductor is arranged in the first through hole, and the first metal barrier layer is located between the first conductor and the inner wall of the first through hole. and in direct contact with the inner wall of the first through hole.

Wherein, the first dielectric layer is electrically connected to the electronic components on the upper and lower surfaces through the first conductor. The dielectric material of the first dielectric layer is generally a low dielectric constant dielectric, which can be at least one of organic silicate glass, porous silicon oxide and methyl silsesquioxane. Groups are easily lost during the etching process to form dangling bonds. These dangling bonds make this type of medium easy to absorb water vapor. The deeper the etching depth, the more serious the damage to the medium. Wherein, in this application, the diameter of the end of the first through hole facing the silicon substrate and the diameter of the end of the substrate through hole facing the first through hole have a difference, indicating that the first through hole and the substrate through hole are formed separately. The difference between the diameter of the end of the first through hole facing the silicon substrate and the diameter of the end of the substrate through hole facing the first through hole is changed to 0 according to the process precision.

The substrate through-hole may be a through hole that passes through the upper and lower surfaces of the silicon substrate, or a blind hole that does not pass through the upper and lower surfaces of the silicon substrate. The material of the substrate through-hole is generally at least one of silicon, SOI, and silicon carbide. One, it can also be doped with gallium nitride or gallium arsenide. The material of the substrate through-hole makes the substrate through-hole conductive under certain conditions, which will affect the electrical properties of the substrate conductor. An insulating layer is disposed thereon to isolate the substrate conductor and the silicon substrate, wherein the insulating layer is made of at least one of SiO ₂ , SIN, an organic insulating layer or an air gap. The insulating layer is not provided in the first through hole, because the material of the insulating layer is a material that can easily absorb water vapor, and it is easy to generate water vapor during the formation process, and the water vapor will enter the first medium with low dielectric constant. layer, thereby reducing the insulation and time-dependent dielectric breakdown (TDDB) reliability of low-k dielectrics, and even causing BEOL metal oxidation and diffusion, deterioration of electromigration (EM) reliability, etc. In this application, The above problem can be avoided by not disposing an insulating layer on the inner wall of the first through hole.

In the present application, a first metal barrier layer is provided on the inner wall of the first through hole to prevent the first conductor from diffusing into the medium in the first dielectric layer, wherein the material of the first metal barrier layer is a metal material, which will not cause Water vapor, specifically titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), tungsten carbide ( At least one of WC), ruthenium (Ru), cobalt (Co), manganese (Mn), nickel (Ni), and the like.

In the present application, the difference between the diameter of the end of the first through hole facing the silicon substrate and the diameter of the end of the substrate through hole facing the first through hole is within 20%, so that the current capacity of the conductors in the first through hole and the substrate through hole change less. , thereby improving the signal transmission performance between the substrate through hole and the first through hole. The difference in diameter is within 20%, including that the diameter of the end of the first through hole facing the silicon substrate is less than 20% of the diameter of the end of the substrate through hole facing the first through hole or the diameter of the end of the first through hole facing the silicon substrate is larger than the diameter of the end of the substrate through hole facing the first through hole. Within 20% of the diameter of one perforated end.

In the semiconductor device provided by the present application, on the one hand, the first through hole in the first dielectric layer and the substrate through hole in the silicon substrate are formed step by step, and the etching depth is reduced to avoid damage to the first through hole caused by too deep etching; On the one hand, the insulating layer is not provided in the first through hole, which can avoid the decrease of the insulation and time-dependent dielectric breakdown (TDDB) reliability of the low dielectric constant medium in the first dielectric layer due to the formation of the insulating layer; in another aspect, The difference between the diameter of the end of the first through hole facing the silicon substrate and the diameter of the end of the substrate through hole facing the first through hole is within 20%, which has good flow capacity and is not limited by the local narrow size. Signal transmission performance between a puncture.

In a possible implementation manner, the first perforation is an integrated structure.

In a possible implementation manner, the section plane of the first through hole is one of a trapezoid, a rectangle or a square.

In a possible implementation manner, the aperture of the first through hole gradually decreases from an end away from the silicon substrate to an end close to the silicon substrate.

In a possible implementation manner, the aperture of the first through hole gradually increases from an end away from the silicon substrate to an end close to the silicon substrate.

In a possible implementation manner, a base barrier layer is further provided in the substrate through hole, the base barrier layer is located between the substrate conductor and the insulating layer, and the insulating layer is located between the base barrier layer and the inner wall of the substrate through hole. The base barrier layer is used to prevent the substrate conductor from diffusing into the dielectric in the silicon substrate when the substrate conductor is formed in the substrate via. The material of the bottom barrier layer is titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), tungsten carbide At least one of (WC), ruthenium (Ru), cobalt (Co), manganese (Mn), nickel (Ni), etc., the base barrier layer may be formed as a single layer or multiple layers.

In a possible implementation manner, there is an interface between the first conductor and the substrate conductor.

In a possible implementation manner, the semiconductor device further includes a second dielectric layer located in the first dielectric layer away from the silicon substrate, and the second dielectric layer is provided with penetrating through the second dielectric layer. Second through holes on opposite surfaces, a second metal barrier layer is arranged on the inner wall of the second through hole, a second conductor is arranged in the second through hole, and the second metal barrier layer is located between the second conductor and the second through hole. The inner walls of the second through holes are in direct contact with and between the inner walls of the second through holes, the second through holes communicate with the first through holes, and the second conductor and the substrate conductor pass through the first through holes The conductors are electrically connected, and the second through hole is an integrated structure.

In a possible implementation manner, the diameter of the end of the second through hole facing the first through hole and the diameter of the end of the first through hole facing the second through hole differ within 20%. The change of the flow capacity between the second through hole and the first through hole is made smaller, so that the signal transmission performance between the second through hole and the first through hole can be improved.

In a possible implementation manner, the semiconductor device further includes a second etch stop layer, and the second etch stop layer is located on a side of the second dielectric layer away from the silicon substrate.

In a possible implementation manner, the first through hole and the second through hole are an integrated structure, and the first conductor and the second conductor are an integrated structure.

In a possible implementation manner, the first perforation includes a first opening facing the second perforation, the second perforation includes a second opening facing the first perforation, and the first opening is connected to the second perforation. The second opening coincides, and the included angle between the peripheral wall of the first through hole and the central axis of the first through hole is the included angle between the peripheral wall of the second through hole and the central axis of the second through hole equal.

In a possible implementation manner, the substrate through hole includes a fifth opening disposed toward the first dielectric layer, the diameter of the third opening is within 20% of the diameter of the fifth opening, and the diameter of the third opening is smaller than the diameter of the fifth opening The diameter of the opening.

In one embodiment, the third opening accounts for more than 80% of the area of the fifth opening.

In some embodiments, the orthographic projection of the first via on the two or both of the two on the silicon substrate at least partially overlaps the orthographic projection of the substrate via on the silicon substrate.

In a possible implementation manner, the semiconductor device further includes a third dielectric layer, the third dielectric layer is located on a side of the second dielectric layer away from the first dielectric layer, the third dielectric layer There is a third through hole penetrating through the opposite two surfaces of the third dielectric layer, a third conductor is arranged in the third through hole, the third conductor is electrically connected with the second conductor, and the third through hole is Integrated structure.

In a possible implementation manner, the diameter of the end of the third through hole facing the second through hole and the diameter of the end of the second through hole facing the third through hole differ within 20%. The change of the flow capacity between the second through hole and the third through hole is made smaller, so that the signal transmission performance between the second through hole and the third through hole can be improved.

In a possible implementation manner, the second through hole and the third through hole are an integrated structure, and the second conductor and the third conductor are an integrated structure.

In a possible implementation manner, the semiconductor device further includes a fourth dielectric layer, the fourth dielectric layer is located on a side of the second dielectric layer away from the first dielectric layer, and the fourth dielectric layer A fourth through hole is arranged in the fourth through hole, a fourth conductor is arranged in the fourth through hole, and the orthographic projection of the fourth conductor on the second dielectric layer covers the second conductor on the second dielectric layer. Orthographic projection.

In a possible implementation manner, the aperture of the substrate through hole gradually decreases from an end close to the first dielectric layer to an end far from the first dielectric layer.

In a possible implementation manner, the aperture of the substrate through hole gradually increases from an end close to the first dielectric layer to an end away from the first dielectric layer.

In a possible implementation manner, the semiconductor device further includes a first etch stop layer, and the first etch stop layer is located on a side of the first dielectric layer away from the substrate.

In a possible implementation manner, the first dielectric layer is further provided with a fifth through hole and a trench that communicate with each other, a fifth conductor is provided in the fifth through hole and the trench, and the fifth through hole and the trench are provided with a fifth conductor. The through hole is disposed farther from the silicon substrate than the trench, the fifth through hole includes an eighth opening toward the trench, and the trench includes a ninth opening toward the fifth through hole , the orthographic projection of the eighth opening on the silicon substrate is located within the range of the orthographic projection of the ninth opening on the silicon substrate.

In a second aspect, the present application also provides a method for preparing a semiconductor device, and the method for preparing a semiconductor device includes:

Provide silicon substrate;

A substrate through hole is formed in the silicon substrate, an insulating layer is formed on the inner wall of the substrate through hole, a substrate conductor is formed in the substrate through hole, and the insulating layer is formed on the substrate conductor and all the between the inner walls of the substrate perforation;

A first dielectric layer is formed on the surface of the substrate, and first through holes penetrating two opposite surfaces of the first dielectric layer are formed in the first dielectric layer, and the first through holes and the substrate through holes lead to and the diameter of the end of the first through hole facing the silicon substrate and the diameter of the end of the substrate through hole facing the first through hole are within 20%, and a first through hole is formed on the inner wall of the first through hole. a metal barrier layer forming a first conductor in the first through hole, the first metal barrier layer being located between the first conductor and the inner wall of the first through hole and in direct contact with the inner wall of the first through hole .

In a possible implementation manner, after forming the first dielectric layer and the first conductor, the manufacturing method of the semiconductor device further includes:

A second dielectric layer is formed on the surface of the first dielectric layer away from the silicon substrate, a second through hole is formed in the second dielectric layer through two opposite surfaces of the second dielectric layer, and a second through hole is formed in the second dielectric layer. A second metal barrier layer is formed on the inner wall of the two through holes, a second conductor is formed in the second through hole, and the second metal barrier layer is located between the second conductor and the inner wall of the second through hole and is connected to the second through hole. The inner wall of the second through hole is in direct contact, the second conductor and the substrate conductor are electrically connected through the first conductor, and the second through hole is an integrated structure.

In a possible implementation manner, after forming the first dielectric layer, the preparation method of the semiconductor device further includes:

A second dielectric layer is formed on the surface of the first dielectric layer away from the silicon substrate, and a first through hole and a second through hole are formed in the first dielectric layer and the second dielectric layer at the same time. The first metal barrier layer and the second metal barrier layer are respectively formed on the inner walls of the first through hole and the second through hole, and the first conductor and the first conductor are integrally formed in the first through hole and the second through hole. Two conductors, the second metal barrier layer is located between the second conductor and the inner wall of the second through hole and is in direct contact with the inner wall of the second through hole, wherein the first through hole and the second through hole For an integrated structure, the first conductor and the second conductor are an integrated structure.

In a possible implementation manner, after the first dielectric layer, the first conductor, the second dielectric layer and the second conductor are formed on the surface of the silicon substrate, the method for fabricating the semiconductor device further includes:

A third dielectric layer is formed on the side of the second dielectric layer away from the first dielectric layer, wherein a third through hole is formed in the third dielectric layer, and the third through hole is formed in the third dielectric layer. For an integrated structure, a third conductor is formed in the third through hole, and the third conductor is electrically connected to the second conductor.

A second dielectric layer and a third dielectric layer are sequentially formed on the surface of the first dielectric layer away from the silicon substrate, and the second dielectric layer and the third dielectric layer are integrally formed through the first dielectric layer. The second through hole of the second medium layer and the third through hole passing through the third medium layer, the second through hole and the third through hole are an integrated structure, and are integrated in the second through hole and the third through hole A second conductor and a third conductor are formed, and the second conductor and the third conductor are an integrated structure.

In a third aspect, the present application provides a method for preparing a semiconductor device, and the method for preparing a semiconductor device includes:

Provide silicon substrate;

A first dielectric layer is formed on one side of the silicon substrate, a first through hole is formed in the first dielectric layer penetrating two opposite surfaces of the first dielectric layer, a first metal barrier layer is formed on the inner wall of the first through hole, and a first metal barrier layer is formed on the inner wall of the first through hole. A first conductor is formed in the through hole, and the first metal barrier layer is located between the first conductor and the inner wall of the first through hole and is in direct contact with the inner wall of the first through hole;

The silicon substrate is etched from the surface of the silicon substrate away from the first dielectric layer to the surface of the silicon substrate adjacent to the first dielectric layer to form a substrate through hole in the silicon substrate, an insulating layer is formed on the inner wall of the substrate through hole, and The substrate conductor is formed in the substrate via, the insulating layer is formed between the substrate conductor and the inner wall of the substrate via, the first via and the substrate via are conductive, and the diameter of one end of the first via facing the silicon substrate and the substrate via The diameters towards the end of the first perforation differ within 20%.

Description of drawings

FIG. 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application;

2a is a schematic structural diagram of a semiconductor device in the prior art;

2b is a schematic structural diagram of a semiconductor device in the prior art;

3 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application;

4a is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application;

4b is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application;

5 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application;

6 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application;

7 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application;

FIG. 8 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application;

FIG. 9 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application;

10 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application;

11 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application;

12 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application;

13 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application;

14 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application;

FIG. 15 is a flowchart of a method for fabricating a semiconductor device provided by an embodiment of the present application;

FIG. 16 is a sub-flow chart of step S300 in the method for fabricating a semiconductor device provided by an embodiment of the present application;

17 is a schematic diagram of a method for fabricating a semiconductor device provided by an embodiment of the present application;

18 is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present application;

19 is a schematic diagram of a method for fabricating a semiconductor device provided by an embodiment of the present application;

20 is a schematic diagram of some steps in a method for fabricating a semiconductor device provided by an embodiment of the present application;

21 is a sub-flow chart of step S300 in the method for fabricating a semiconductor device provided by an embodiment of the present application;

22 is a schematic diagram of a method for fabricating a semiconductor device provided by an embodiment of the present application;

23 is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present application;

24 is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present application;

FIG. 25 is a flowchart of a method for fabricating a semiconductor device provided by an embodiment of the present application.

Detailed ways

Herein, the terms "first", "second", etc. are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature defined as "first" or "second" may expressly or implicitly include one or more of that feature. In the description of this application, unless stated otherwise, "plurality" means two or more.

In addition, herein, orientation terms such as "upper" and "lower" are defined relative to the orientation in which the structures in the accompanying drawings are schematically placed, and it should be understood that these directional terms are relative concepts, and they are used relative to descriptions and clarifications, which can vary accordingly depending on the orientation in which the structure is placed.

For the convenience of understanding, the English abbreviations and related technical terms involved in the embodiments of the present application are explained and described below.

TSV: Through silicon via, through silicon via.

FEOL: front end of line, front process.

SOI: Silicon-On-Insulator, that is, silicon on an insulating substrate, this technology introduces a buried oxide layer between the top silicon and the back substrate.

TDDB: Time dependent dielectric breakdown, dielectric breakdown over time.

BEOL: Back end of line, back-end craftsmanship.

EM: electro-migrationeffect, electromigration.

Referring to FIG. 1 , an embodiment of the present application provides a semiconductor device 10 , which includes a silicon substrate 200 and a first dielectric layer 100 provided on the surface of the silicon substrate 200 ; a substrate through-hole 210 is provided in the silicon substrate 200 ; The first dielectric layer 100 is provided with a first through hole 110 penetrating the opposite surfaces of the first dielectric layer 100; The diameter of the end of the bottom through hole 210 facing the first through hole 110 is within 20%; the inner wall of the substrate through hole 210 is provided with an insulating layer 230 , the substrate through hole 210 is provided with a substrate conductor 220 , and the insulating layer 230 is located on the substrate conductor 220 and the inner wall of the substrate through hole 210; a first metal barrier layer 130 is arranged on the inner wall of the first through hole 110, a first conductor 120 is arranged in the first through hole 110, and the first metal barrier layer 130 is located between the first conductor 120 and the The inner walls of the first through holes 110 are in direct contact with and between the inner walls of the first through holes 110 .

Wherein, the first dielectric layer 100 is electrically connected to the electronic components on the upper and lower surfaces through the first conductor 120 . The dielectric material of the first dielectric layer 100 is generally a low dielectric constant dielectric, which can be at least one of organic silicate glass, porous silicon oxide and methyl silsesquioxane. Organic groups are easily lost during the etching process to form dangling bonds. These dangling bonds make this type of medium easy to absorb water vapor. The deeper the etching depth, the more serious the damage to the medium. Wherein, in the present application, the diameter of the end of the first through hole 110 facing the silicon substrate 200 and the diameter of the end of the substrate through hole 210 facing the first through hole 110 have a difference value, indicating that the first through hole 110 and the substrate through hole 210 are formed separately. In some cases, the difference between the diameter of the end of the first through hole 110 facing the silicon substrate 200 and the diameter of the end of the substrate through hole 210 facing the first through hole 110 can be changed to 0 by improving the process accuracy.

The substrate through-hole 210 may be a through hole passing through the upper and lower surfaces of the silicon substrate 200, or may be a blind hole that does not pass through the upper and lower surfaces of the silicon substrate 200. The material of the substrate through-hole 210 is generally silicon, SOI, carbide At least one of the silicon can also be doped with gallium nitride or gallium arsenide. The material of the through-substrate through-hole 210 makes the through-substrate through-hole 210 conductive under certain conditions, which will affect the electrical properties of the substrate conductor 220. An insulating layer 230 needs to be provided on the inner wall of the substrate through hole 210 to isolate the substrate conductor 220 and the silicon substrate 200, wherein the insulating layer 230 is made of SiO ₂ , SIN, an organic insulating layer or at least one of the air gaps. A sort of. The insulating layer is not provided in the first through hole 110, because the insulating layer is made of a material that can easily absorb water vapor, and it is easy to generate water vapor during the formation process, and the water vapor will enter the first hole with a low dielectric constant. In the dielectric layer 100, the insulating properties of the low dielectric constant dielectric and the reliability of the time-dependent dielectric breakdown (TDDB) are reduced, and even the BEOL metal oxidation and diffusion, the deterioration of the electromigration (EM) reliability, etc., are caused in this application. , the above problem can be avoided by not disposing an insulating layer on the inner wall of the first through hole 110 .

In the present application, a first metal barrier layer 130 is disposed on the inner wall of the first through hole 110 to prevent the first conductor 120 from diffusing into the medium in the first dielectric layer 100 , wherein the material of the first metal barrier layer 130 is metal Material that does not generate water vapor, specifically titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN) ), at least one of tungsten carbide (WC), ruthenium (Ru), cobalt (Co), manganese (Mn), nickel (Ni), and the like.

The technical solutions in this application are applied in the semiconductor device 10 for electrically connecting the silicon substrate 200 with the top electronic components of the dielectric layer in the subsequent process. As shown in FIG. 2a, one way in the prior art is to integrate the interconnection layer 1 and the through hole in the silicon substrate 200, wherein the interconnection layer 1 can be one or more dielectric layers, so as to form a through hole. The through-silicon vias 220 of the interconnection layer 1 and the silicon substrate 200, the depth of the etched through-holes includes the depths of the silicon substrate 200 and the interconnection layer 1, and the through-holes in the interconnection layer 1 will be seriously damaged due to the deep etching depth , the damaged interconnect layer is more likely to absorb water vapor, and the water vapor will enter the interconnect layer 1 with a low dielectric constant medium, so that the insulation and time-dependent dielectric breakdown (TDDB) of the low dielectric constant medium are improved. The reliability is degraded, even causing metal oxidation and diffusion in the interconnect layer 1, deterioration of electromigration (EM) reliability, and the like. In the present application, the substrate through-hole 210 in the silicon substrate 200 and the first through-hole 310 in the first dielectric layer 300 are formed in steps (as shown in FIG. 1 ), and the first through-hole 210 is formed in the first dielectric layer 100 . The etching depth of the through hole 110 is small, which can avoid damage to the inner wall of the first through hole 110 in the first dielectric layer 100 due to the excessive depth, and there is no insulating layer on the inner wall of the first through hole 310 in the present application. It can be avoided that water vapor is generated during the formation process, so that the water vapor can be prevented from entering the first dielectric layer 100 with a low dielectric constant, so that the insulation and the time-dependent dielectric breakdown (TDDB) of the low dielectric constant medium are reliable. Degradation of properties, and even cause BEOL metal oxidation and diffusion, electromigration (EM) reliability deterioration, etc.

In the present application, the diameter of the end of the first through hole 110 facing the silicon substrate 200 and the diameter of the end of the substrate through hole 210 facing the first through hole 110 differ within 20%, so that the conductors in the first through hole 110 and the substrate through hole 210 have a difference within 20%. The change of the current capacity is small, so that the signal transmission performance between the substrate through hole 210 and the first through hole 110 can be improved. The diameters differ within 20%, including that the diameter of the end of the first through hole 110 facing the silicon substrate 200 is less than 20% of the diameter of the end of the substrate through hole 210 facing the first through hole 110 or the diameter of the end of the first through hole 110 facing the silicon substrate 200 It is larger than 20% of the diameter of the end of the substrate through hole 210 facing the first through hole 110 .

Another way in the prior art is shown in Figure 2b. The interconnection layer 1 in Figure 2b is used to electrically connect the electronic components on the upper and lower surfaces. The interconnection layer 1 is provided with through holes 11 and trenches 12. The through holes 11 and the trench 12 are filled with metal. Since the through hole 11 is used to realize the electrical connection in the vertical direction, and the metal in the trench 12 is used to electrically connect the devices above, the aperture size of the general through hole 11 is smaller than that of the trench. 12, the area of the cut surface of the through hole 11 is smaller than the area of the cut surface of the groove 12, that is to say, the pore diameter change from the groove 12 to the through hole 11 is very large, so that the smaller size of the through hole 11 The flow capacity determines the flow capacity of the interconnect layer 1, and the pore size of the through hole 11 in this structure is generally small, only tens of nanometers to sub-micron, and the metal size in the through hole 11 is also relatively small. The flow capacity in the interconnection layer 1 is limited to the vias 11 . Generally, the diameter of the substrate through hole 210 is in the range of submicron to tens of micrometers. In the present application, the diameter of the end of the first through hole 110 facing the silicon substrate 200 and the diameter of the end of the substrate through hole 210 facing the first through hole 110 differ by 20 μm. %, that is to say, the diameter of the connecting position of the first through hole 110 and the substrate through hole 210 is not much different, so that the change of the flow capacity is small, and the signal transmission between the substrate through hole 210 and the first through hole 110 can be improved. performance.

The semiconductor device 10 provided by the present application, on the one hand, forms the first through hole 110 in the first dielectric layer 100 and the substrate through hole 210 in the silicon substrate 200 in steps, and reduces the etching depth to avoid the first through hole caused by the excessive etching depth. 110 damage; on the other hand, the first through hole 110 is not provided with an insulating layer, which can avoid the insulation and time-dependent dielectric breakdown (TDDB) of the low dielectric constant medium in the first dielectric layer 100 due to the formation of the insulating layer. On the other hand, the diameter of the end of the first through hole 110 facing the silicon substrate 200 and the diameter of the end of the substrate through hole 210 facing the first through hole 110 are within 20%, which has good flow capacity and is not affected by The limitation of the local narrow size improves the signal transmission performance between the substrate through hole 210 and the first through hole 110 .

Please continue to refer to FIG. 1 , in a possible implementation manner, the first through hole 110 is an integrated structure. The first through hole 110 is an integrated structure, which means that the change of the pore size of the first through hole 110 from the end away from the silicon substrate 200 to the end close to the silicon substrate 200 is continuous, and the pore size can be gradually larger, smaller or different. Therefore, the inner wall of the first through hole 110 has no obvious interface, and the through hole makes the change of the hole diameter of the first conductor 120 formed therein continuous, and the hole diameter of the first conductor 120 has no sudden change. In the present application, the first through hole 110 is obtained by one etching process. Specifically, the first through hole 110 can pass from the surface of the first dielectric layer 100 away from the silicon substrate 200 to the surface of the first dielectric layer 100 adjacent to the silicon substrate 200 . The first dielectric layer 100 is obtained by surface etching. Generally, the diameter of the first through hole 110 is sub-micron to several tens of microns. Compared with the separate formation of the through hole 11 and the trench 12 in FIG. 2b, the formation process of the first through hole 110 of the integrated structure in the present application is simpler, and the first through hole 110 of the integrated structure is interconnected compared with that in FIG. 2b. The through-hole process of the layer is simpler, the first conductor 120 formed in the first through-hole 110 has no sudden change in size, the flow capacity is not limited by the local narrow size, and the overall flow capacity is more uniform, compared with FIG. 2a. The conductors of the interconnect layer have good electrical conductivity.

In one embodiment, the cut surface of the first through hole 110 is one of a trapezoid, a rectangle or a square. Wherein, the cut surface of the first through hole 110 refers to a cut surface obtained by cutting the first through hole 110 with a line perpendicular to the first dielectric layer 100 . The trapezoid can be a normal trapezoid or an inverted trapezoid. A normal trapezoid means that the side of the trapezoid away from the silicon substrate 200 is smaller than the side of the side close to the silicon substrate 200 (as shown in FIG. 3 ), and the inverted trapezoid means that the trapezoid is far away from the silicon substrate 200 . The side length of one side of the silicon substrate 200 is larger than the side length of the side close to the silicon substrate 200 (as shown in FIG. 1 ). When the cross-sectional surface of the first through hole 110 is a normal trapezoid, the aperture of the first through hole 110 gradually increases from the end away from the silicon substrate 200 to the end close to the silicon substrate 200 . When the cut surface of the first through hole 110 is an inverted trapezoid, the hole diameter of the first through hole 110 gradually decreases from the end far from the silicon substrate 200 to the end close to the silicon substrate 200 . The first conductor in the first through hole 110 The size of one end of the 120 away from the silicon substrate 200 is larger, which can increase the contact area of the first conductor 120 for electrical connection with the electronic components above. In FIG. 1 , the sectional plane of the first through hole 110 is an inverted trapezoid. It should be noted that, within the range of process error, each side of the trapezoid is approximately straight, and the two waist sides of the trapezoid are continuous and approximately straight.

The sectional plane of the first through hole 110 is a trapezoid, so that the sectional plane of the first conductor 120 formed in the first through hole 110 is a trapezoid. Generally, electrochemical deposition, electroless plating or physical vapor deposition can be used in the first through hole. The first conductor 120 is formed in 110. The size of the first conductor 120 with a trapezoidal cross-section is gradually changed, and there is no particularly small part. good conductivity.

In this embodiment, the diameter of the through-substrate via 210 gradually decreases from the end close to the first dielectric layer 100 to the end far from the first dielectric layer 100 .

Continuing to refer to FIG. 1 , in this embodiment, the substrate through-hole 210 is further provided with a base barrier layer 240 , the base barrier layer 240 is located between the substrate conductor 220 and the insulating layer 230 , and the insulating layer 230 is located between the base barrier layer 240 and the liner between the inner walls of the bottom through holes 210 . The base barrier layer 240 is used to prevent the substrate conductors 220 from diffusing into the dielectric in the silicon substrate 200 when the substrate conductors 220 are formed in the substrate vias 210 . The material of the bottom barrier layer 240 is titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), carbide The base barrier layer 240 may be formed as a single layer or multiple layers of at least one of tungsten (WC), ruthenium (Ru), cobalt (Co), manganese (Mn), nickel (Ni), and the like.

In this embodiment, there is an interface between the first conductor 120 and the substrate conductor 220, which means that the first conductor 120 and the substrate conductor 220 are formed in steps. The material of the substrate conductor 220 , the first conductor 120 and the second conductor 320 may be at least one of conductive materials such as Cu, Al, W, Au, Ag, or carbon nanotubes, respectively.

Referring to FIG. 4a, in a possible implementation manner, the semiconductor device 10 further includes a second dielectric layer 300 located in the first dielectric layer 100 away from the substrate 200, and the second dielectric layer 300 is provided with a penetration through the second dielectric layer 300. The second through holes 310 on the opposite two surfaces (as shown in FIG. 4 a ), a second metal barrier layer 330 is formed on the inner wall of the second through hole 310 , a second conductor 320 is arranged in the second through hole 310 , and the second metal barrier layer 330 Located between the second conductor 320 and the inner wall of the second through hole 310 and in direct contact with the inner wall of the second through hole 310 , the second through hole 310 communicates with the first through hole 110 , and the second conductor 320 and the substrate conductor 220 pass through the first conductor 120 For electrical connection, the second through hole 310 is an integrated structure.

The fact that the second through hole 310 is an integrated structure means that the diameter of the second through hole 310 changes continuously from the end away from the silicon substrate 200 to the end close to the silicon substrate 200 , and the diameter of the second through hole 310 may gradually increase , gradually become smaller or the pore size remains unchanged, the inner wall of the second through hole 310 has no obvious interface, this through hole makes the pore size change of the second conductor 320 formed therein continuous, and there is no sudden change in the pore size of the second conductor 320 . In the present application, the second through hole 310 is obtained by one etching process, and the second through hole 320 can be etched from the surface of the second dielectric layer 300 away from the silicon substrate 200 to the surface of the second dielectric layer 300 adjacent to the silicon substrate 200 The second dielectric layer 300 is obtained.

In this embodiment, the cross section of the second through hole 310 is one of a trapezoid, a rectangle or a square. The cross section of the second through hole 310 refers to the area where the second through hole 310 is cut along a line perpendicular to the second dielectric layer 300 . In the obtained sectional plane, the trapezoid can be a regular trapezoid or an inverted trapezoid. In the embodiment of FIG. 4a , the cross-sectional surface of the second through hole 310 is an inverted trapezoid, and the hole diameter of the second through hole 310 gradually decreases from the end away from the silicon substrate 200 to the end close to the silicon substrate 200 , and is formed in the second through hole 310 . The cut surface of the second conductor 320 in 320 is also trapezoidal, and generally the second conductor 320 can be formed in the second through hole 320 by methods such as electrochemical deposition, electroless plating or physical vapor deposition.

In the embodiment shown in FIG. 4 a , the second through holes 310 in the second dielectric layer 300 are of an integrated structure, which can improve the current flow capacity of the second dielectric layer 300 , thereby improving the substrate conductors 220 and the second conductors 320 The current capacity between the first conductor 120 and the first conductor 120 improves the signal transmission performance of the semiconductor device 10 . And the first perforation 110 and the second perforation 310 are formed in steps, so that the aperture size of the first perforation 110 and the second perforation 310 can be adjusted. The electronic components above the layer 100 are electrically connected to the area, and the material composition of the first conductor 120 and the second conductor 320 can be adjusted to improve design flexibility.

In this embodiment, a second metal barrier layer 330 is disposed on the inner wall of the second through hole 310 to prevent the second conductor 320 from diffusing into the medium in the second dielectric layer 300 , wherein the material of the second metal barrier layer 330 is It is a metal material that does not generate water vapor, and can be titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride ( At least one of WN), tungsten carbide (WC), ruthenium (Ru), cobalt (Co), manganese (Mn), nickel (Ni), and the like.

In this embodiment, the diameter of the end of the second through hole 310 facing the first through hole 110 and the diameter of the end of the first through hole 110 facing the second through hole 310 are within 20%, so that the diameter between the second through hole 310 and the first through hole 110 is within 20%. The change of the flow capacity is small, so that the signal transmission performance between the second through hole 310 and the first through hole 110 can be improved.

Wherein, the first metal barrier layer 130 and the second metal barrier layer 330 may be formed by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process and/or an atomic layer deposition (ALD) process. When the first metal barrier layer 130 is formed on the inner wall of the first through hole 110 , the material forming the first metal barrier layer 130 will be volatilized and deposited on the surface of the substrate conductor 220 facing the first through hole 110 , and formed on the inner wall of the second through hole 310 When the second metal barrier layer 330 is formed, the material for forming the second metal barrier layer 330 is volatilized and deposited on the surface of the first conductor 120 facing the second through hole 310 .

The semiconductor device 10 further includes a first etch stop layer 140 , and the first etch stop layer 140 is located on the side of the first dielectric layer 100 away from the silicon substrate 200 . The first etch stop layer 140 covers the first conductor 120 and the first dielectric layer 100 and is used to protect the dielectric layer and the first conductor 110 in the first dielectric layer 100 during etching. The material of the first etch stop layer 140 may be nitrogen At least one of silicon nitride, silicon oxynitride, silicon carbide or silicon carbonitride.

The semiconductor device 10 further includes a second etch stop layer 340, and the second etch stop layer 340 is located on the side of the second dielectric layer 340 away from the silicon substrate 200 (as shown in FIG. 13 ). The second etch stop layer 340 is used to protect the dielectric layer and the second conductor 320 in the second dielectric layer 300 during etching. The material of the second etch stop layer 340 may be at least one of silicon nitride, silicon oxynitride, silicon carbide or silicon carbonitride.

In one embodiment, the first dielectric layer 100 may also be provided with other metal traces 102 (as shown in FIG. 4 a ) or through holes different from the first conductor 120 , so as to realize the connection between the first dielectric layer 100 and other Electrical connections between electronic devices or layers.

Referring to FIG. 4b, in a possible implementation manner, the first through hole 110 and the second through hole 310 are an integrated structure, and the first conductor 120 and the second conductor 320 are an integrated structure. The integrated structure means that the first through hole 110 and the second through hole 210 are formed by one process. During preparation, the first dielectric layer 100 and the second dielectric layer 300 are etched from the surface of the second dielectric layer 300 away from the silicon substrate 200 to the surface of the first dielectric layer 100 close to the silicon substrate 200 to obtain an integrated first dielectric layer 100 and the second dielectric layer 300 . Compared with forming the first through hole 110 and the second through hole 310 in the first dielectric layer 100 and the second dielectric layer 300 respectively, the integrated structure of the through hole 110 and the second through hole 310 can save the process. In addition, the integrated structure of the first conductor 120 and the second conductor 320 can reduce the interface impedance between the first conductor 120 and the second conductor 320, thereby improving the electrical conductivity between the first conductor 120 and the second conductor 320, This improves the signal transmission capability.

Referring to FIG. 5 , in a possible implementation manner, the first through hole 110 includes a first opening 111 facing the second through hole 310 , the second through hole 310 includes a second opening 311 facing the first through hole 110 , and the first opening 111 Coinciding with the second opening 311, and the included angle β between the peripheral wall of the first through hole 110 and the central axis O1 of the first through hole 110 and the included angle α between the peripheral wall of the second through hole 310 and the central axis O2 of the second through hole equal. That is to say, when the first through hole 110 and the second through hole 310 are integrated structures, the hole walls of the first through hole 110 and the second through hole 310 are continuous, and the peripheral wall of the first through hole 110 and the peripheral wall of the second through hole 310 are inclined The angles are the same, so that the included angle α and the included angle β are equal. The peripheral wall of the first through hole 110 and the peripheral wall of the second through hole 310 respectively refer to the first through hole 110 and the second through hole 310 when the first through hole 110 and the second through hole 310 are cut with the same line perpendicular to the first dielectric layer 100 and the second dielectric layer 300 . The cut surface of the perforation 110 is the waist edge on the same side as the cut surface of the second perforation 310 . The integrated first through-hole 110 and second through-hole 310 are regarded as a whole structure, and the whole structure is denoted as interconnection through-hole 101 . One end gradually becomes smaller or larger, and the pore size change of the entire interconnection via 101 is gradually continuous. The conductor formed in this interconnection via 101 is compared with the two-layer interconnection layer in the prior art (as shown in FIG. 2b ). ), the metal conductor in the through hole has lower impedance and stronger signal transmission capability.

In this embodiment, the interconnection through hole 101 is of a wide-top and bottom-narrow structure, and one end of the interconnection through hole 101 away from the silicon substrate 200 is larger in size, which is favorable for electrical connection with the electronic components above. The first through hole 110 further includes a third opening 112 disposed opposite to the first opening 111 , the second through hole 310 further includes a fourth opening 312 disposed opposite to the second opening 311 , and the diameter of the second through hole 310 is from the fourth opening 312 to The second opening 311 gradually becomes smaller, and the diameter of the first through hole 110 gradually decreases from the first opening 111 to the third opening 112 .

Continuing to refer to FIG. 5 , in a possible implementation manner, the through-substrate through-hole 210 includes a fifth opening 211 disposed toward the first dielectric layer 100 , and the diameter of the third opening 112 and the diameter of the fifth opening 211 differ within 20% , and the diameter of the third opening 112 is smaller than the diameter of the fifth opening 211 . In this embodiment, the orthographic projection of the third opening 112 on the silicon substrate 200 is located in the orthographic projection of the fifth opening 211 on the silicon substrate 200 . In some embodiments, the third opening 112 may be larger in size than the fifth opening 211 such that the second conductor 320 covers the substrate conductor 220 .

Generally, the size of the fifth opening 211 is from sub-micron to several tens of microns, or the aperture size of the substrate through hole 210 is from sub-micron to several tens of microns. In one embodiment, the third opening 112 accounts for more than 80% of the area of the fifth opening 211, which indicates that the first through hole 110 is different from the through hole 11 in the interconnection layer 1 in the prior art (as shown in FIG. 2b ). ), in the prior art, the size of the through hole 11 is generally several tens of nanometers to submicron. In the present application, the size of the first through hole 110 is large and the resistance is small, which is conducive to signal transmission. In addition, when the through hole 11 of the interconnection layer 1 is connected to the substrate conductor 220 in the silicon substrate 200 or indirectly connected to the TSV in the FEOL in the prior art, the size of the substrate conductor 220 and the TSV in the FEOL are generally compared. When the TSV or the substrate conductor 220 in the FEOL is extruded by force, it will exert a force on the through hole 11, which may cause deformation of the smaller through hole 11 and the trench 12 in the interconnection layer 1 or cause the through hole. The actual size and height of 11 and trench 12 vary, and when the substrate conductor 220 is extruded by force, it will cause greater stress at the via hole 11 and trench 12 directly connected to it, which will cause the interconnection layer 1 to be electrically The reliability of migration, dielectric breakdown, etc. deteriorates. However, in this embodiment, the size of the first through hole 110 is not much different from the size of the substrate through hole 210, and the size of the first conductor 120 is relatively large, which has strong structural strength and is not easily deformed, thereby avoiding electromigration and dielectric shock. Wear and other reliability problems.

In some embodiments, the orthographic projection of the first via 110 on the silicon substrate 200 and the orthographic projection of the substrate via 210 on the silicon substrate 200 at least partially overlap. That is, the same substrate via 210 may be electrically connected to two or both of the first vias 110 . Referring to FIG. 6 , in the semiconductor device 10 , there are two interconnect vias 101 penetrating the first dielectric layer 100 and the second dielectric layer 300 simultaneously, and the conductors in the second via 310 of each interconnect via 101 and the substrate The conductors in the through holes 210 are electrically connected.

In some embodiments, the interconnect via 101 can penetrate through three dielectric layers and more than three layers at the same time. As shown in FIG. 7 , the semiconductor device 10 further includes a third dielectric layer 400 , the third dielectric layer 400 is located on the side of the second dielectric layer 300 away from the first dielectric layer 100 , and a third through hole 410 is formed in the third dielectric layer 400 , a third conductor 420 is set in the third through hole 410 , wherein the third through hole 410 , the first through hole 110 and the second through hole 310 are an integrated structure.

In some embodiments, for the same semiconductor device 10 , there may be interconnect vias 101 penetrating two dielectric layers or three dielectric layers at the same time. As shown in FIG. 8 , in the semiconductor device 10 , the interconnect vias 101 a penetrate through The first dielectric layer 100 and the second dielectric layer 300 , and the interconnection through hole 101b penetrates through the first dielectric layer 100 , the second dielectric layer 300 and the third dielectric layer 400 . In actual products, the number of layers that can penetrate the dielectric layer can be set according to actual needs.

Referring to FIG. 9 , in a possible implementation manner, different from the embodiment shown in FIG. 1 , the semiconductor device 10 further includes a third dielectric layer 400 , and the third dielectric layer 400 is located in the first dielectric layer 100 away from the second dielectric layer 400 . On one side of the dielectric layer 300 , the third dielectric layer 400 is provided with a third through hole 410 penetrating two opposite surfaces of the third dielectric layer 400 , the third through hole 410 is provided with a third conductor 420 , and the third conductor 420 is connected with the first conductor 120 is electrically connected, and the third through hole 410 is an integrated structure.

The third through hole 410 is an integrated structure, which means that the change of the diameter of the third through hole 410 from the end far from the silicon substrate 200 to the end close to the silicon substrate 200 is continuous. When the aperture becomes smaller or the aperture remains unchanged, the inner wall of the third through hole 410 has no obvious interface. This through hole makes the aperture change of the third conductor 420 formed therein continuous, and the aperture of the third conductor 420 has no sudden change. In the present application, the third through hole 410 is obtained by one etching process.

The cut surface of the third through hole 410 is one of a trapezoid, a rectangle or a square. The section plane of the third through hole 410 refers to the section plane obtained by cutting the third through hole 410 along a line perpendicular to the third dielectric layer 400 , wherein the trapezoid can be a normal trapezoid or an inverted trapezoid. In this embodiment, the sectional surface of the third through hole 410 is an inverted trapezoid, the hole wall of the third through hole 410 is continuous, the third through hole 410 includes a sixth opening 411 and a seventh opening 412 arranged oppositely, and the sixth opening 411 Compared with the arrangement of the seventh opening 412 away from the first dielectric layer 100 , the diameter of the third through hole 410 gradually decreases from the sixth opening 411 to the seventh opening 412 .

In this embodiment, the diameter of the end of the third through hole 410 facing the second through hole 310 and the diameter of the end of the second through hole 310 facing the third through hole 410 differ within 20%, so that the difference between the second through hole 310 and the third through hole 410 is within 20%. The change of the current capacity is small, so that the signal transmission performance between the second through hole 310 and the third through hole 410 can be improved.

The orthographic projection of the seventh opening 412 on the second dielectric layer 300 at least partially overlaps the orthographic projection of the fourth opening 312 in the second through hole 310 on the first dielectric layer 100 . In one embodiment, the orthographic projection of the seventh opening 412 on the first dielectric layer 100 is located in the orthographic projection of the fourth opening 312 in the second through hole 310 on the second dielectric layer 300 , and the seventh opening 412 occupies the third The area of the four openings 312 accounts for more than 80%. This shows that the third through hole 410 is different from the through hole 11 in the interconnection layer 1 in the prior art (as shown in FIG. 2b ). In this embodiment, the size of the third through hole 410 is sub-micron to several tens of microns, and has better flow capacity.

Referring to FIG. 10 , in a possible implementation manner, different from the embodiment shown in FIG. 9 , the semiconductor device 10 further includes a third dielectric layer 400 , and the third dielectric layer 400 is located in the first dielectric layer 100 away from the second dielectric layer 400 . On one side of the dielectric layer 300 , a third through hole 410 is formed in the third dielectric layer 400 , and a third conductor 420 is formed in the third through hole 410 , wherein the third through hole 410 and the second through hole 310 are an integrated structure.

Referring to FIG. 11 , in a possible implementation manner, different from the embodiment shown in FIG. 4 b , the semiconductor device 10 further includes a third dielectric layer 400 , and the third dielectric layer 400 is located on the first dielectric layer 100 away from the second dielectric layer 400 . On one side of the dielectric layer 300 , the third dielectric layer 400 is provided with a third through hole 410 penetrating two opposite surfaces of the third dielectric layer 400 , the third through hole 410 is provided with a third conductor 420 , and the third conductor 420 is connected to the first conductor 120 is electrically connected, and the third through hole 410 is an integrated structure.

Referring to FIG. 12 , in a possible implementation manner, the aperture of the substrate through hole 210 gradually increases from an end close to the first dielectric layer 100 to an end far from the first dielectric layer 100 . In this embodiment, the through-substrate via 210 in the silicon substrate 200 can be formed after the first dielectric layer 100 and the second dielectric layer 300 are formed, and the through-substrate via 210 can be away from the silicon substrate 200 from the first dielectric layer 100 The surface of the silicon substrate 200 is obtained by etching the surface of the silicon substrate 200 close to the first dielectric layer 100 .

Referring to FIG. 13 , in a possible implementation manner, the semiconductor device 10 further includes a fourth dielectric layer 500 . The fourth dielectric layer 500 is located on the side of the second dielectric layer 300 away from the first dielectric layer 100 . The fourth dielectric layer A fourth through hole 510 is provided in the 500, a fourth conductor 520 is arranged in the fourth through hole 510, and the orthographic projection of the fourth conductor 520 on the second dielectric layer 300 covers the orthographic projection of the second conductor 320 on the second dielectric layer 300 . In this embodiment, the fourth conductor 520 in the fourth dielectric layer 500 is used to increase the connection area between the first dielectric layer 100 and the electronic components in the BEOL, which is beneficial to the electrical connection between the first dielectric layer 100 and the electronic components on the BEOL .

Referring to FIG. 14, in a possible implementation manner, at least one of the first dielectric layer 100 and the second dielectric layer 300 is further provided with a fifth through hole 201 and a trench 202 that communicate with each other. The fifth through hole A fifth conductor 203 is provided in the trench 201 and the trench 202. The fifth through hole 201 is disposed farther from the silicon substrate 200 than the trench 202. The fifth through hole 201 includes an eighth opening 204 facing the trench 202. The trench 202 Including the ninth opening 205 facing the fifth through hole 201 , the orthographic projection of the eighth opening 204 on the silicon substrate 200 is located within the range of the orthographic projection of the ninth opening 205 on the silicon substrate 200 . The fifth through hole 201 and the trench 202 in this embodiment are the same as the through hole 11 and the trench 12 in the interconnection layer 1 in FIG. 2b, respectively. The diameter of the fifth through hole 201 is tens of nanometers to submicrometers. That is to say, this embodiment is compatible with the first through hole 110 of the integrated structure of the present application and the through hole 11 and the trench 12 in FIG. 2 b to realize the electrical connection between the upper and lower surfaces of the dielectric layer, so that the semiconductor device 10 The structure is more flexible and can be applied to semiconductor devices 10 with different requirements. For example, some lines need to have higher signal transmission capability to improve the signal transmission accuracy. At this time, the through holes of the integrated structure in this application can be set for vertical interconnection. The fifth through hole 201 and the trench 202 can be used for vertical interconnection when the line does not need better signal transmission accuracy.

Referring to FIG. 15 and FIG. 1 , an embodiment of the present application further provides a method for fabricating a semiconductor device 10 , and the method for fabricating the semiconductor device 10 includes step S100 , step S200 and step S300 . The detailed steps are described below.

In step S100, a silicon substrate 200 is provided. The material of the silicon substrate 200 can be at least one of silicon, SOI or silicon carbide, and can also be doped with gallium nitride or gallium arsenide.

Step S200, forming through-substrate through-holes 210 in the silicon substrate 200, insulating layers 230 on the inner walls of through-substrate through-holes 210, forming substrate conductors 220 in the through-substrate through-holes 210, and forming insulating layers 230 on the substrate conductors 220 and the lining between the inner walls of the bottom through holes 210 . Generally, the pore size of the substrate through hole 210 is sub-micron to several tens of microns. The method for forming the through-substrate through-hole 210 includes: firstly depositing a photoresist on the silicon substrate 200, and performing exposure and development to define the position and aperture size of the through-substrate through-hole 210, where a hard mask can be used if necessary. The process improves the etching ratio; then, the substrate through-holes 210 of a specific depth are etched by the reactive ion etching method; and then wet and dry cleaning is performed to remove the residual reaction products, solvents, etc. formed by the photoresist and the etching process. In this embodiment, the aperture size of the through-substrate vias 210 is submicron to several tens of microns.

In this embodiment, the manufacturing method of the semiconductor device 10 further includes forming a base barrier layer 240 on the inner wall of the substrate through hole 210 , wherein the base barrier layer 240 is formed between the substrate conductor 220 and the insulating layer 230 . The insulating layer 230 is used to electrically insulate the substrate conductor 220 from the dielectric in the silicon substrate 200 . The base barrier layer 240 is used to prevent the substrate conductors 220 from diffusing into the dielectric in the silicon substrate 200 when the substrate conductors 220 are formed in the substrate vias 210 . The insulating layer 230 can be formed by chemical vapor deposition (CVD), and the material of the insulating layer 230 is at least one of SiO ₂ , SIN, an organic insulating layer or an air gap. The base barrier layer 240 may be formed by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process and/or an atomic layer deposition (ALD) process, and the material of the base barrier layer 240 may be titanium (Ti), titanium nitride (TiN), Titanium Tungsten (TiW), Tantalum (Ta), Tantalum Nitride (TaN), Tungsten (W), Tungsten Nitride (WN), Tungsten Carbide (WC), Ruthenium (Ru), Cobalt (Co), At least one of manganese (Mn), nickel (Ni), and the like, the base barrier layer 240 may be formed as a single layer or multiple layers.

In this embodiment, the method of fabricating the semiconductor device 10 further includes forming a seed layer on the base barrier layer 240 , wherein the seed layer is used to grow a metal film from the metal seed layer by electroplating to form a substrate filling the substrate through holes 210 The conductor 220 and the seed layer may be made of at least one of metal materials such as Cu, Al, W, Au or Ag.

In one embodiment, when forming the insulating layer 230 , the base barrier layer 240 or the seed layer, the uniformity of the film layer may also be improved by a heavy sputtering process.

In this embodiment, the substrate conductor 220 may be formed by electrochemical deposition or electroless plating, wherein the substrate conductor 220 may be at least one of conductive materials such as Cu, Al, W, Au, Ag, or carbon nanotubes . After the substrate conductor 220 is formed, there may be excess insulating layer 230, base barrier layer 240 or raw material of the base conductor on the surface of the silicon substrate 200. At this time, the surface of the silicon substrate 200 may be subjected to chemical mechanical polishing Planarization removes excess material on the surface of the silicon substrate 200 .

Step S300 , a first dielectric layer 100 is formed on one side of the silicon substrate 200 , a first through hole 110 is formed in the first dielectric layer 100 penetrating two opposite surfaces of the first dielectric layer 100 , and the first through hole 110 and the substrate through hole 210 lead to each other. and the diameter of the end of the first through hole 110 facing the silicon substrate 200 and the diameter of the end of the substrate through hole 210 facing the first through hole 110 are within 20%, and the first metal barrier layer 130 is formed on the inner wall of the first through hole 110, The first conductor 120 is formed in the first through hole 110 , and the first metal barrier layer 130 is located between the first conductor 120 and the inner wall of the first through hole 110 and is in direct contact with the inner wall of the first through hole 110 .

In the semiconductor device 10 prepared by the preparation method provided in the present application, on the one hand, the first through holes 110 in the first dielectric layer 100 and the substrate through holes 210 in the silicon substrate 200 are formed step by step, and the etching depth is reduced to avoid excessive etching depth. This causes damage to the first through hole 110 ; on the other hand, no insulating layer is formed in the first through hole 110 , which can avoid the insulating properties and time-dependent dielectric properties of the low dielectric constant medium in the first dielectric layer 100 due to the formation of the insulating layer. On the other hand, the diameter of the end of the first through-hole 110 facing the silicon substrate 200 and the diameter of the end of the substrate through-hole 210 facing the first through-hole 110 are within 20%, which has a better pass-through. The flow capability is not limited by the local narrow size, and the signal transmission performance between the substrate through hole 210 and the first through hole 110 is improved.

In this embodiment, the first through hole 110 is an integrated structure, the first through hole 110 of the integrated structure enables the first conductor 120 in the first through hole 110 to have better flow capacity, and the formation process of the first through hole 110 is more convenient Simple.

In this embodiment, step S300 further includes forming a second dielectric layer 300 on the side of the first dielectric layer 100 away from the silicon substrate 200 , and forming two opposite surfaces through the second dielectric layer 300 in the second dielectric layer 300 A second metal barrier layer 330 is formed on the inner wall of the second through hole 310 , a second conductor 320 is formed in the second through hole 310 , and the second metal barrier layer 330 is located between the second conductor 320 and the second through hole 310 Between the inner walls of and directly contact with the inner wall of the second through hole 310, the second conductor 320 and the substrate conductor 220 are electrically connected through the first conductor 120, and the second through hole 310 is an integrated structure. The second through hole 310 of the integrated structure has a simple process and enables the second conductor 320 in the second through hole 310 to have better flow capacity.

16 and 17, in one embodiment, step S300 specifically includes step S310-I, step S320-I, step S330-I, step S340-I, step S350-I, step S360-I, step S370 -I and step S380-I. The detailed steps are described below.

Step S310-I, forming a base etch stop layer 250 on one side of the silicon substrate 200 . The base etch stop layer 250 is used to protect the surface of the silicon substrate 200 and the substrate conductor 220 from being damaged during the etching process. The base etch stop layer 250 is generally made of at least one of silicon nitride, silicon oxynitride, silicon carbide or silicon carbonitride.

Step S320-I, forming the first dielectric layer 100 on the side of the base etch stop layer 250 away from the silicon substrate 200 . The first dielectric layer 100 covers the first etch stop layer 140 .

Step S330-I, forming a first through hole 110 penetrating the first dielectric layer 100 and the base etching stop layer 250, the first through hole 110 is an integrated structure, the first through hole 110 and the substrate through hole 210 are connected, and the first through hole 110 The diameter of the end facing the silicon substrate 200 and the diameter of the end of the substrate through hole 210 facing the first through hole 110 differ within 20%. Specifically, etching is performed from the surface of the first dielectric layer 100 away from the silicon substrate 200 to the surface of the base etch stop layer 250 adjacent to the silicon substrate 200 to form the first through holes 110 . In this embodiment, the first through holes 110 are etched. The sectional plane is an inverted trapezoid.

The method for forming the first through hole 110 includes: firstly depositing a photoresist on the first dielectric layer 100, and performing exposure and development to define the position and aperture size of the first through hole 110, where a hard mask can be used if necessary. and other processes to improve the etching ratio; then, the first through holes 110 with a specific depth are etched by reactive ion etching; and then wet and dry cleaning is performed to remove residual reaction products and solvents formed during the photoresist and etching process. In some embodiments, damage repair (eg, UV repair) and moisture removal (eg, baking) may also be performed on the medium on the inner surface of the first through hole 110 . In this embodiment, the pore size of the first through holes 110 is submicron to several tens of microns. In one embodiment, the substrate through hole 210 includes a fifth opening 211 disposed toward the first dielectric layer 100 , the first through hole 110 includes a third opening 112 , and the orthographic projection of the third opening 112 on the silicon substrate 200 is the same as the fifth opening 211 . The orthographic projections of the openings 211 on the silicon substrate 200 at least partially coincide to enable the substrate conductor 220 and the second conductor 320 to be electrically connected. In this embodiment, the orthographic projection of the third opening 112 on the silicon substrate 200 is located in the orthographic projection of the fifth opening 211 on the silicon substrate 200 , and the size of the fifth opening 211 is larger than that of the third opening 112 .

In step S340-I, a first metal barrier layer 130 is formed on the inner wall of the first through hole 110, a first conductor 120 is formed in the first through hole 110, and the first metal barrier layer 130 is located between the first conductor 120 and the first through hole 110. The inner walls are in direct contact with the inner walls of the first through holes 110 . The sectional plane of the first conductor 120 is a trapezoid, so that the first conductor 120 has better current capacity. The first metal barrier layer 130 is used to prevent the first conductor 120 from diffusing into the dielectric in the first dielectric layer 100 when the first conductor 120 is formed in the first through hole 110 . In this embodiment, a seed layer is also formed on the first metal barrier layer 130, wherein the seed layer is used to grow a metal film from the metal seed layer by electroplating, so as to form the first conductor 120 filling the first through hole 110, the seed layer The layer may be at least one of metal materials such as Cu, Al, W, Au or Ag.

In one embodiment, when forming the first metal barrier layer 130 or the seed layer, the uniformity of the film layer may also be improved by a heavy sputtering process. In one embodiment, after the first conductor 120 is formed, there may be excess first metal barrier layer 130 or raw material of the first conductor 120 on the surface of the first dielectric layer 100 . The surface of the first dielectric layer 100 is planarized to remove excess material on the surface of the first dielectric layer 100 .

Step S350-I, forming a first etch stop layer 140 on the surface of the first dielectric layer 100 and the first conductor 120 away from the silicon substrate 200 .

In step S360-I, a second dielectric layer 300 is formed on the surface of the first etch stop layer 140 away from the silicon substrate 200 .

Step S370-I, forming a second through hole 310 penetrating the second dielectric layer 300 and the first etch stop layer 140, the second through hole 310 is an integrated structure, the first through hole 110 and the second through hole 310 are connected, and the second through hole 310 is connected The diameter of the end of the first through hole 110 facing the first through hole 110 and the diameter of the end of the first through hole 110 facing the second through hole 310 differ within 20%. Specifically, etching is performed from the surface of the second dielectric layer 300 away from the silicon substrate 200 to the surface of the first etch stop layer 140 adjacent to the silicon substrate 200 to form the second through hole 310. In this embodiment, the second through hole is The sectional plane of 310 is an inverted trapezoid.

The method for forming the second through holes 310 includes: firstly depositing a photoresist on the second dielectric layer 300, and performing exposure and development to define the positions and aperture sizes of the second through holes 310, where a hard mask can be used if necessary. and other processes to improve the etching ratio; then, the second through holes 310 with a specific depth are etched by reactive ion etching; and then wet and dry cleaning is performed to remove residual reaction products, solvents, etc. formed by the photoresist and the etching process. In some embodiments, damage repair (eg, UV repair) and moisture removal (eg, baking) may also be performed on the medium on the inner surface of the second through hole 310 .

In step S380-I, a second metal barrier layer 330 is formed on the inner wall of the second through hole 310, a second conductor 320 is formed in the second through hole 310, and the second metal barrier layer 330 is located between the second conductor 320 and the second through hole 310. between the inner walls and in direct contact with the inner walls of the second through holes 310 . The cut surface of the second conductor 320 is a trapezoid, so that the second conductor 320 has a better current capacity. The second metal barrier layer 330 is used to block the diffusion of the second conductor 320 into the dielectric in the second dielectric layer 300 . In this embodiment, forming a seed layer on the second metal barrier layer 330 is further included, wherein the seed layer is used to grow a metal film from the metal seed layer by electroplating to form the second conductor 320 filling the second through hole 310 . In this embodiment, after the second conductor 320 is formed, the surface of the silicon substrate 200 away from the first dielectric layer 100 is ground flat to expose one end of the substrate conductor 220 away from the first dielectric layer 100 .

In one embodiment, when forming the second metal barrier layer 330 or the seed layer, the uniformity of the film layer may also be improved by a heavy sputtering process. In one embodiment, after the second conductor 320 is formed, there may be an excess of the second metal barrier layer 330 or the raw material of the second conductor 320 on the surface of the second dielectric layer 300 . The surface of the second dielectric layer 300 is planarized to remove excess material on the surface of the second dielectric layer 300 .

In this embodiment, the materials of the first dielectric layer 100 and the second dielectric layer 300 are generally low dielectric constant dielectrics, which can be at least one of organic silicate glass, porous silicon oxide, and methylsilsesquioxane The organic groups doped in this type of medium are easily lost during the etching process to form dangling bonds. These dangling bonds make this type of medium easy to absorb water vapor, so after the etching process on this type of medium, it is usually damaged. Repair (eg UV repair) and moisture removal (eg bake). In this embodiment, the first dielectric layer 100 may be one or more layers, and the second dielectric layer 300 may be one or more layers, which may be set according to actual needs. When the first dielectric layer 100 is multiple layers , the material of each layer of the first dielectric layer 300 may be the same or different. When the second dielectric layer 300 is multi-layered, the material of each second dielectric layer 300 may be the same or different, and at least one layer is formed therein. The first dielectric layer 100 and the second dielectric layer 300 may be formed by a chemical vapor deposition process.

Generally, when the perforation is etched, the deeper the perforation is, the more serious the damage to the peripheral wall of the perforation is, the more dangling bonds are formed, and the water is easily absorbed. For example, in the solution shown in FIG. 2a, the through-holes in the interconnect layer 1 and the silicon substrate 200 are formed by one-time etching, and the etched through-hole depth includes the depths of the silicon substrate 200 and the interconnect layer 1. Due to the etching depth If the depth is too deep, the through hole in the interconnection layer 1 will be seriously damaged, and the insulating layer 230 is integrally formed on the inner wall of the through hole in the interconnection layer 1 and the inner wall of the through hole of the silicon substrate 200 , and the material of the insulating layer 230 is generally It is silicon oxide or other oxides, and it is easy to generate water vapor during the formation process, and the water vapor will enter the dielectric layer in the interconnect layer 1 with low dielectric constant, so that the insulation and durability of the low dielectric constant dielectric are improved. Dielectric breakdown (TDDB) reliability decreases, and even causes BEOL metal oxidation and diffusion, electromigration (EM) reliability deterioration, etc. In this embodiment, the substrate through-hole 210 in the silicon substrate 200 , the first through-hole 110 of the first dielectric layer 100 and the second through-hole 310 of the second dielectric layer 300 are formed in steps, which can avoid excessive depth due to excessive depth. It is too large to cause damage to the inner wall of the first through hole 110 in the first dielectric layer 100 , and there is no need to form an insulating layer in the first through hole 110 and the second through hole 310 . In addition, in this embodiment, the dielectric layer and the silicon substrate 200 are formed in steps, so that the material, size and height of the filled conductors in each layer of the dielectric layer and the silicon substrate 200 are also flexibly adjustable, so that the semiconductor device 10 can be flexibly formed. Designed for easy customization. In addition, the diameter of the end of the first through hole 110 facing the silicon substrate 200 and the diameter of the end of the substrate through hole 210 facing the first through hole 110 are within 20%, which can improve the flow capacity between the first through hole 110 and the substrate through hole 210. The diameter of the end of the second through hole 310 facing the first through hole 110 and the diameter of the end of the first through hole 110 facing the second through hole 310 are within 20%, which can improve the flow capacity between the first through hole 110 and the second through hole 310 .

Wherein, the first etch stop layer 140 and the base etch stop layer 250 can be formed by a chemical vapor deposition process, and the materials of the first etch stop layer 140 and the base etch stop layer 250 are generally silicon nitride, silicon oxynitride, silicon carbide or At least one of silicon carbonitride.

Wherein, the first metal barrier layer 130 and the second metal barrier layer 330 may be formed by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process and/or an atomic layer deposition (ALD) process, and the first metal barrier layer The material of 130 and the second metal barrier layer 330 may be titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), tungsten carbide (WC), ruthenium (Ru), cobalt (Co), manganese (Mn), nickel (Ni), etc., the first metal barrier layer 130 and the second metal barrier layer 330 may Formed as a single layer or multiple layers.

The first conductor 120 and the second conductor 320 may be formed by electrochemical deposition or electroless plating, wherein the first conductor 120 and the second conductor 320 may be conductive such as Cu, Al, W, Au, Ag, or carbon nanotubes. at least one of the materials.

In a possible implementation, the fabricated semiconductor device 10 has three dielectric layers. Please refer to FIGS. 18 and 9 . Different from the embodiment in FIG. 15 , in this embodiment, after step S300 , the method for fabricating the semiconductor device 10 further includes step S400 -I.

Step S400-I, a third dielectric layer 400 is formed on the side of the second dielectric layer 300 away from the first dielectric layer 100, wherein a third through hole 410 is formed in the third dielectric layer 400, and a third through hole 410 is formed in the third dielectric layer 400. The through hole 410 is an integrated structure, and a third conductor 420 is formed in the third through hole 410 , and the third conductor 420 is electrically connected to the first conductor 120 .

The formation method of the third through hole 410 is the same as that of the first through hole 110 , and the formation method of the third conductor 420 is similar to that of the first conductor 120 . In one embodiment, before the third conductor 420 is formed, the third barrier layer 430 and the seed layer are formed on the inner wall of the third through hole 410 , the method for forming the third barrier layer 430 and the method for forming the first barrier layer 130 The same is not repeated here.

It should be noted that, the number of layers of the dielectric layer can be prepared and formed according to actual needs, and is not limited to two layers or three layers in the above embodiments. The number of through holes in each dielectric layer is not limited to 1, and the number of through holes can be set according to actual needs, for example, the number of the second through holes 310 and the second conductors 220 in the second dielectric layer 300 can be 2 For another example, the number of the third through holes 410 and the third conductors 420 in the third dielectric layer 400 may be three.

Please refer to FIG. 19 and FIG. 14 . Different from the embodiment in FIG. 9 , in this embodiment, the first dielectric layer 100 and the second dielectric layer 300 are further provided with fifth through holes 201 and grooves that communicate with each other. The slot 202 , the fifth through hole 201 and the fifth conductor 203 are disposed in the trench 202 . The fifth through hole 201 is disposed farther from the silicon substrate 200 than the trench 202 . Eight openings 204, the trench 202 includes a ninth opening 205 facing the fifth through hole 201, and the orthographic projection of the eighth opening 204 on the silicon substrate 200 is located within the range of the orthographic projection of the ninth opening 205 on the silicon substrate 200 .

Specifically, two substrate through holes 210 and two substrate conductors 220 are formed in the silicon substrate 200 (as shown in step S10 in FIG. 19 ).

In the first dielectric layer 100 , two first through holes 110 respectively located on the two base conductors 200 are formed, and a fifth through hole 201 and a trench 202 are formed (as shown in step S20 in FIG. 19 ), wherein the first dielectric The fifth through hole 201 and the trench 202 in the layer 100 do not overlap with the orthographic projection of the substrate through hole 210 in the silicon substrate 200 on the silicon substrate 200 ; the aperture size of the fifth through hole 201 is smaller than that of the first through hole 110 The aperture size of the fifth through hole 201 is generally tens of nanometers to submicron, and the size of the second through hole 310 is submicron to tens of microns.

The first conductors 120 are formed in the two first through holes 110 and the fifth conductors 203 are formed in the fifth through holes 201 and the trenches 202 respectively (as shown in step S30 in FIG. 19 ).

In the second dielectric layer 300, a second through hole 310 is formed on the side of one of the first conductors 120 away from the silicon substrate 200, and two fifth through holes are formed on the side of the other first conductor 120 away from the silicon substrate 200. A hole 201 and two grooves 202 (as shown in step S40 in FIG. 19 ).

A second conductor 320 is formed in the second through hole 310 and a fifth conductor 203 is formed in the fifth through hole 201 and the trench 202 (as shown in step S50 in FIG. 19 ).

A third through hole 410 and a third conductor 420 are formed in the third dielectric layer 400 (as shown in step S60 in FIG. 19 ). In this step, after the third conductor 420 is also formed, the surface of the silicon substrate 200 away from the first dielectric layer 100 is smoothed to expose one end of the substrate conductor 220 away from the first dielectric layer 100 .

In this embodiment, the two first through holes 110 , the fifth through holes 201 , the trenches 202 and the conductors located therein in the first dielectric layer 100 can be formed by the metal Damas process or the dual Damas process at the same time. , including simultaneous baking, photolithography, development, etching, deposition, etc., the height of the first through hole 110 of the first dielectric layer 100 formed is the height of the fifth through hole 201 and the groove 202 in the first dielectric layer 100 height and. Similarly, the second through holes 310 , the fifth through holes 201 , the trenches 202 and the conductors located therein in the second dielectric layer 300 may be formed by a metal Damasce process or a double Damas process, and the formed second dielectric The height of the second through hole 310 of the layer 300 is the sum of the heights of the fifth through hole 201 and the trench 202 in the second dielectric layer 300 . In this embodiment, the semiconductor device 10 has both the through hole of the integrated structure and the conventional fifth through hole 201 and the trench 202 in the present application, so that the structure of the semiconductor device 10 is more flexible and can be applied to semiconductor devices with different requirements 10. For example, some lines need to have higher signal transmission capacity to improve the signal transmission accuracy. At this time, the perforations using the integrated structure in this application can be set for vertical interconnection. When some lines do not need better signal transmission accuracy, the fifth pass can be used. The holes 201 and the trenches 202 are vertically interconnected.

Referring to FIG. 20 , different from the embodiment shown in FIG. 19 , in one embodiment, the two first through holes 110 , the fifth through holes 201 and the trenches 202 in the first dielectric layer 100 are formed separately. First, two first through holes 110 are formed (step S21 in FIG. 20 ), and then the two first through holes 110 are covered with a photoresist 301 to form fifth through holes 201 and trenches 202 (step S22 in FIG. 20 ) , and then remove the photoresist 301 to expose the first through hole 110 (step S23 in FIG. 20 ). Since the aperture size of the fifth through hole 201 is relatively small, and the aperture size of the first through hole 110 is relatively large, the aperture size accuracy requirements of the two through holes are different, especially for the fifth through hole with the aperture size ranging from tens of nanometers to submicrons. 201 , the accuracy requirements are higher, and in this embodiment, the step-by-step formation is beneficial to improve the dimensional accuracy of the fifth through hole 201 . In some embodiments, the fifth through hole 201 and the trench 202 can also be formed first, and then the fifth through hole 201 and the trench 202 are covered with a photoresist, and then the first through hole 110 is formed, and then the photoresist is removed to expose the fifth through hole 201.

Different from the embodiment shown in FIG. 17 , in one embodiment, the first through hole 110 and the second through hole 310 are integrally formed, the first conductor 120 and the second conductor 320 are integrally formed, and the structure of the semiconductor device 10 is As shown in FIG. 4 b , the step 300 is to form the second dielectric layer 300 on the surface of the first dielectric layer 100 away from the silicon substrate 200 , and to form the first dielectric layer 100 and the second dielectric layer 300 at the same time. Through the through holes 110 and the second through holes 310, the first metal barrier layer 130 and the second metal barrier layer 330 are respectively formed on the inner walls of the first through holes 110 and the second through holes 310, and are integrated into the first through holes 110 and the second through holes 310. The first conductor 120 and the second conductor 320 are formed, the second metal barrier layer 330 is located between the second conductor 320 and the inner wall of the second through hole 310 and is in direct contact with the inner wall of the second through hole 310, wherein the first through hole 110 and the second through hole 310 The two through holes 310 are of an integrated structure, and the first conductor 120 and the second conductor 320 are of an integrated structure.

Specifically, please refer to FIG. 21 and FIG. 22 , step S300 specifically includes step S310-II, step S320-II, step S330-II, step S340-II and step S350-II. The detailed steps are described below.

In step S310-II, a base etch stop layer 250 is formed on one side of the silicon substrate 200 .

In step S320-II, the first dielectric layer 100 is formed on the side of the base etching stop layer 250 away from the silicon substrate 200 .

In step S330-II, a second dielectric layer 300 is formed on the surface of the first dielectric layer 100 away from the silicon substrate 200 .

Step S340-II, integrally forming the first through hole 110 penetrating the base etching stop layer 250 and the first dielectric layer 140 and forming the second through hole 310 penetrating the second dielectric layer 340, the first through hole 110 and the second through hole 310 are integrated structure. Specifically, etching is performed from the surface of the second dielectric layer 300 away from the silicon substrate 200 to the surface of the base etch stop layer 250 adjacent to the silicon substrate 200 to form interconnections penetrating the first dielectric layer 100 and the second dielectric layer 300 The via 101 and the interconnect via 101 include a first via 110 in the first dielectric layer 100 and a second via 310 in the second dielectric layer 300 . In this embodiment, the first through-hole 110 and the second through-hole 310 are integrally formed. Compared with the step-by-step formation of the first through-hole 110 and the second through-hole 310 in the first dielectric layer 100 and the second dielectric layer 300 , the Save process.

The method for integrally forming the first through hole 110 and the second through hole 310 includes: firstly depositing a photoresist on the second dielectric layer 300 , and performing exposure and development to define the position and location of the first through hole 110 or the second through hole 310 . Aperture size, if necessary, the etching ratio can be improved by a process such as a hard mask; then the first through hole 110 and the second through hole 310 with a specific depth are etched by the reactive ion etching method; and then wet and dry cleaning is performed. To remove residual reaction products, solvents, etc. formed during photoresist and etching processes. In some embodiments, damage repair (eg, UV repair) and moisture removal (eg, baking) may also be performed on the medium on the inner surface of the second through hole 310 .

In step S350-II, the first metal barrier layer 130 and the second metal barrier layer 330 are integrally formed on the inner walls of the first through hole 110 and the second through hole 310, and the first metal barrier layer 130 and the second metal barrier layer 330 are integrally formed in the first through hole 110 and the second through hole 310. A conductor 120 and a second conductor 320, the first metal barrier layer 130 is located between the first conductor 120 and the inner wall of the first through hole 110, and the second metal barrier layer 330 is located between the second conductor 320 and the inner wall of the second through hole 310 . The first conductor 120 and the second conductor 320 are formed at the same time. From a structural point of view, the first conductor 120 and the second conductor 320 are an integrated structure, which can reduce the interface impedance between the first conductor 120 and the second conductor 320. Therefore, the electrical conductivity between the first conductor 120 and the second conductor 320 can be improved, thereby improving the signal transmission capability. The first metal barrier layer 130 is used for preventing the first conductor 120 from diffusing into the dielectric in the first dielectric layer 100 when the first conductor 120 is formed in the first through hole 110 , and the second metal barrier layer 330 is used for forming the first conductor 120 in the second through hole When the second conductor 320 is formed in 310 , the diffusion of the second conductor 320 into the medium in the second dielectric layer 300 is blocked. In this embodiment, it also includes forming a seed layer on the first metal barrier layer 130 and the second metal barrier layer 330, wherein the seed layer is used to grow a metal film from the metal seed layer by electroplating to form the first conductor 120 and the first conductor Two conductors 320 . In this embodiment, after the first conductor 120 and the second conductor 320 are integrally formed, the surface of the silicon substrate 200 away from the first dielectric layer 100 is ground flat to expose the substrate conductor 220 away from the first dielectric layer 100 at one end.

In one embodiment, the fabricated semiconductor device 10 has three dielectric layers. Please refer to FIG. 23 and FIG. 10 . Different from the embodiment in FIG. 1 , in this embodiment, after step S200 , the method for fabricating the semiconductor device 10 further includes step S400 - II.

In step S400-II, the second dielectric layer 300 and the third dielectric layer 400 are sequentially formed on the side of the first dielectric layer 100 away from the silicon substrate 200, and the second dielectric layer 300 and the third dielectric layer 400 are integrated to form a through-hole. The second through hole 310 of the second dielectric layer 300 and the third through hole 410 penetrating through the third dielectric layer 400 , the second through hole 320 and the third through hole 410 are an integrated structure, and are integrated in the second through hole 310 and the third through hole 410 The third conductor 420 is formed, and the third conductor 420 and the second conductor 320 are an integrated structure.

In one embodiment, the fabricated semiconductor device 10 has three dielectric layers. Please refer to FIG. 24 and FIG. 11 . Different from the embodiment in FIG. 21 , in this embodiment, after step S300 , the method for fabricating the semiconductor device 10 further includes step S400 - III.

In step S400-III, a third dielectric layer 400 is formed on the side of the second dielectric layer 300 away from the first dielectric layer 100 , wherein a third through hole 410 is formed in the third dielectric layer 400 penetrating the third dielectric layer 400 , and the third dielectric layer 400 is formed. The through hole 410 is an integrated structure, and a third conductor 420 is formed in the third through hole 410 , and the third conductor 420 is electrically connected to the second conductor 320 .

In one embodiment, the fabricated semiconductor device 10 has three dielectric layers, wherein the through holes in the three dielectric layers are integrally formed. Please refer to FIG. 7 again. Different from the embodiment in FIG. 21 , in this embodiment, the step S300 includes forming the second dielectric layer 300 , the first dielectric layer 100 and the third dielectric layer 300 on one side of the silicon substrate 200 . In the dielectric layer 400 , the second through holes 310 in the second dielectric layer 300 , the first through holes 110 in the first dielectric layer 100 and the third through holes 410 in the third dielectric layer 400 are integrally formed.

Referring to FIG. 13 again, in one embodiment, the method for fabricating the semiconductor device 10 further includes forming a fourth dielectric layer 500 , the fourth dielectric layer 500 is formed on the side of the second dielectric layer 300 away from the first dielectric layer 100 , and the fourth dielectric layer 500 is formed on the side of the second dielectric layer 300 away from the first dielectric layer 100 A fourth through hole 510 is formed in the four dielectric layers 500 , a fourth conductor 520 is formed in the fourth through hole 510 , and the orthographic projection of the fourth conductor 520 on the second dielectric layer 300 covers the positive projection of the second conductor 320 on the second dielectric layer 300 projection. In this embodiment, the fourth conductor 520 in the fourth dielectric layer 500 is used to increase the connection area between the first dielectric layer 100 and the electronic components other than the BEOL, which is beneficial to the electrical connection between the first dielectric layer 100 and the electronic components other than the BEOL .

In some embodiments, the semiconductor device 10 has four dielectric layers, including a first dielectric layer 100 , a second dielectric layer 300 , a third dielectric layer 400 and a fourth dielectric layer 500 that are stacked in sequence, wherein the first dielectric layer 100. The through holes in the second dielectric layer 300 and the third dielectric layer 400 are integrally formed, and the orthographic projection of the fourth conductor 520 in the fourth dielectric layer 500 on the third dielectric layer 400 covers the third conductor 420 on the third dielectric layer 400. Orthographic projection on the dielectric layer 400 .

In the above-mentioned several embodiments, before the formation of the dielectric layer, the through-substrate via 210 and the substrate conductor 220 are formed in the silicon substrate 200, and the aperture size of the through-substrate via 210 in the silicon substrate 200 is One end of the dielectric layer 300 gradually becomes smaller toward the end away from the second dielectric layer 300 .

Referring to FIGS. 25 and 12 , an embodiment of the present application further provides another method for fabricating a semiconductor device 10 . In this embodiment, a second dielectric layer 300 and a first dielectric layer are formed on one side of the silicon substrate 200 After 100, the silicon substrate 200 is etched on the other side of the silicon substrate 200, and the aperture size of the through-substrate through-hole 210 in the formed silicon substrate 200 is from the end close to the first dielectric layer 100 to the distance away from the first dielectric layer 100. one end gradually becomes larger. Specifically, the manufacturing method of the semiconductor device 10 includes step S100-I, step S200-I and step S300-I. The detailed steps are described below.

In step S100-I, a silicon substrate 200 is provided.

In step S200-I, a first dielectric layer 100 is formed on one side of the silicon substrate 200. The first dielectric layer 100 is formed with a first through hole 110 penetrating two opposite surfaces of the first dielectric layer 100, and an inner wall of the first through hole 110 is formed. A first metal barrier layer 130 is formed thereon, a first conductor 120 is formed in the first through hole 110 , and the first metal barrier layer 130 is located between the first conductor 120 and the inner wall of the first through hole 100 and is in direct contact with the inner wall of the first through hole .

Step S300-I, etching the silicon substrate 200 from the surface of the silicon substrate 200 away from the first dielectric layer 100 to the surface of the silicon substrate 200 adjacent to the first dielectric layer 100, so as to form the substrate through-hole 210 in the silicon substrate 200, An insulating layer 230 is formed on the inner wall of the substrate through hole 210, the substrate conductor 220 is formed in the substrate through hole 210, the insulating layer 230 is formed between the substrate conductor 220 and the inner wall of the substrate through hole 210, the first through hole 110 and the liner The bottom through hole 210 is turned on, and the diameter of the end of the first through hole 110 facing the silicon substrate 200 and the diameter of the end of the substrate through hole 210 facing the first through hole 110 are within 20%.

In this embodiment, the method of forming the substrate barrier layer in the silicon substrate 200 is the same as that of the above-mentioned embodiment, and the method of forming through holes, conductors, and barrier layers in each dielectric layer is the same as that of the above-mentioned embodiment, and will not be repeated here. Repeat.

In this application, the manufacturing method of the semiconductor device 10 further includes forming a unit device on one side of the silicon substrate 200 by FEOL process, the unit device includes but not limited to metal oxide semiconductor field effect transistor, system large scale integration device, CMOS imaging At least one of a sensor, a microelectromechanical system, an active device, a passive device, and the like.

The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention. should be included within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

A semiconductor device, comprising a silicon substrate and a first dielectric layer provided on the surface of the silicon substrate;

The silicon substrate is provided with a substrate through hole;

The first medium layer is provided with a first through hole penetrating two opposite surfaces of the first medium layer;

The first through hole is connected to the substrate through hole, and the diameter of one end of the first through hole facing the silicon substrate and the diameter of the end of the substrate through hole facing the first through hole differ within 20%;

An insulating layer is arranged on the inner wall of the substrate through hole, a substrate conductor is arranged in the substrate through hole, and the insulating layer is located between the substrate conductor and the inner wall of the substrate through hole;

A first metal barrier layer is arranged on the inner wall of the first through hole, a first conductor is arranged in the first through hole, and the first metal barrier layer is located between the first conductor and the inner wall of the first through hole. and in direct contact with the inner wall of the first through hole.
The semiconductor device of claim 1, wherein the first through hole is an integrated structure.
The semiconductor device according to claim 1, wherein the cross section of the first through hole is one of a trapezoid, a rectangle or a square.
The semiconductor device according to claim 1, wherein the aperture of the first through hole gradually decreases from an end away from the silicon substrate to an end close to the silicon substrate.
The semiconductor device according to claim 1, wherein the aperture of the first through hole gradually increases from an end away from the silicon substrate to an end close to the silicon substrate.
The semiconductor device of claim 1, wherein the first conductor and the substrate conductor have an interface.
The semiconductor device according to claim 1, characterized in that, the semiconductor device further comprises a second dielectric layer located in the first dielectric layer away from the silicon substrate, wherein the second dielectric layer is provided with through-holes in the second dielectric layer. The second through holes on the opposite surfaces of the second dielectric layer, the inner walls of the second through holes are provided with a second metal barrier layer, the second through holes are provided with a second conductor, and the second metal barrier layer is located at the between the second conductor and the inner wall of the second through hole and in direct contact with the inner wall of the second through hole, the second through hole communicates with the first through hole, the second conductor and the substrate conductor The second through hole is an integrated structure by being electrically connected by the first conductor.
8. The semiconductor device of claim 7, wherein the first through hole and the second through hole are an integrated structure, and the first conductor and the second conductor are an integrated structure.
8. The semiconductor device of claim 7, wherein the first through hole includes a first opening toward the second through hole, the second through hole includes a second opening toward the first through hole, and the The first opening coincides with the second opening, and the angle between the peripheral wall of the first through hole and the central axis of the first through hole is the same as the peripheral wall of the second through hole and the central axis of the second through hole. The included angles are equal.
The semiconductor device according to claim 7, wherein the semiconductor device further comprises a third dielectric layer, the third dielectric layer is located on a side of the second dielectric layer away from the first dielectric layer, The third dielectric layer is provided with a third through hole penetrating two opposite surfaces of the third dielectric layer, a third conductor is provided in the third through hole, and the third conductor is electrically connected with the second conductor, so The third perforation is an integrated structure.
11. The semiconductor device of claim 10, wherein the second through hole and the third through hole are an integrated structure, and the second conductor and the third conductor are an integrated structure.
The semiconductor device according to any one of claims 7-10, wherein the semiconductor device further comprises a fourth dielectric layer, and the fourth dielectric layer is located in the second dielectric layer and away from the first dielectric layer On one side of the second dielectric layer, a fourth through hole is provided in the fourth dielectric layer, a fourth conductor is provided in the fourth through hole, and the orthographic projection of the fourth conductor on the second dielectric layer covers the second orthographic projection of the conductor on the second dielectric layer.
The semiconductor device according to any one of claims 1-12, wherein the aperture of the substrate through hole gradually decreases from an end close to the first dielectric layer to an end away from the first dielectric layer.
The semiconductor device according to any one of claims 1-12, wherein an aperture of the substrate through hole gradually increases from an end close to the first dielectric layer to an end far from the first dielectric layer.
The semiconductor device of claim 1, wherein the semiconductor device further comprises a first etch stop layer, the first etch stop layer is located on a side of the first dielectric layer away from the substrate.
The semiconductor device according to any one of claims 1-15, wherein the first dielectric layer is further provided with a fifth through hole and a trench that communicate with each other, and the fifth through hole and the trench are A fifth conductor is provided, the fifth through hole is disposed farther from the silicon substrate than the trench, the fifth through hole includes an eighth opening facing the trench, and the trench includes an eighth opening facing the trench. The ninth opening of the fifth through hole, the orthographic projection of the eighth opening on the silicon substrate is located within the range of the orthographic projection of the ninth opening on the silicon substrate.
The semiconductor device according to any one of claims 1-16, wherein the material of the silicon substrate is at least one of silicon, SOI and silicon carbide.
A preparation method of a semiconductor device, characterized in that the preparation method of the semiconductor device comprises:

Provide silicon substrate;

A substrate through hole is formed in the silicon substrate, an insulating layer is formed on the inner wall of the substrate through hole, a substrate conductor is formed in the substrate through hole, and the insulating layer is formed on the substrate conductor and all the between the inner walls of the substrate perforation;

A first dielectric layer is formed on the surface of the substrate, and first through holes penetrating two opposite surfaces of the first dielectric layer are formed in the first dielectric layer, and the first through holes and the substrate through holes lead to and the diameter of the end of the first through hole facing the silicon substrate and the diameter of the end of the substrate through hole facing the first through hole are within 20%, and a first through hole is formed on the inner wall of the first through hole. a metal barrier layer forming a first conductor in the first through hole, the first metal barrier layer being located between the first conductor and the inner wall of the first through hole and in direct contact with the inner wall of the first through hole .
The method for fabricating a semiconductor device according to claim 18, wherein after forming the first dielectric layer and the first conductor, the method for fabricating the semiconductor device further comprises:

A second dielectric layer is formed on the surface of the first dielectric layer away from the silicon substrate, a second through hole is formed in the second dielectric layer through two opposite surfaces of the second dielectric layer, and a second through hole is formed in the second dielectric layer. A second metal barrier layer is formed on the inner wall of the two through holes, a second conductor is formed in the second through hole, and the second metal barrier layer is located between the second conductor and the inner wall of the second through hole and is connected to the second through hole. The inner wall of the second through hole is in direct contact, the second conductor and the substrate conductor are electrically connected through the first conductor, and the second through hole is an integrated structure.
The method for fabricating a semiconductor device according to claim 18, wherein after the first dielectric layer is formed, the method for fabricating the semiconductor device further comprises:

A second dielectric layer is formed on the surface of the first dielectric layer away from the silicon substrate, and a first through hole and a second through hole are formed in the first dielectric layer and the second dielectric layer at the same time. The first metal barrier layer and the second metal barrier layer are respectively formed on the inner walls of the first through hole and the second through hole, and the first conductor and the first conductor are integrally formed in the first through hole and the second through hole. Two conductors, the second metal barrier layer is located between the second conductor and the inner wall of the second through hole and is in direct contact with the inner wall of the second through hole, wherein the first through hole and the second through hole For an integrated structure, the first conductor and the second conductor are an integrated structure.
The method for manufacturing a semiconductor device according to claim 19, wherein after forming a first dielectric layer, a first conductor, a second dielectric layer and a second conductor on the surface of the silicon substrate, the semiconductor device The preparation method also includes:

A third dielectric layer is formed on the side of the second dielectric layer away from the first dielectric layer, wherein a third through hole is formed in the third dielectric layer, and the third through hole is formed in the third dielectric layer. For an integrated structure, a third conductor is formed in the third through hole, and the third conductor is electrically connected to the second conductor.
The method for fabricating a semiconductor device according to claim 18, wherein after forming the first dielectric layer and the first conductor, the method for fabricating the semiconductor device further comprises:

A second dielectric layer and a third dielectric layer are sequentially formed on the surface of the first dielectric layer away from the silicon substrate, and the second dielectric layer and the third dielectric layer are integrally formed through the first dielectric layer. The second through hole of the second medium layer and the third through hole passing through the third medium layer, the second through hole and the third through hole are an integrated structure, and are integrated in the second through hole and the third through hole A second conductor and a third conductor are formed, and the second conductor and the third conductor are an integrated structure.
A preparation method of a semiconductor device, characterized in that the preparation method of the semiconductor device comprises:

Provide silicon substrate;

A first dielectric layer is formed on one side of the silicon substrate, a first through hole is formed in the first dielectric layer penetrating two opposite surfaces of the first dielectric layer, and a first through hole is formed on the inner wall of the first through hole. a metal barrier layer forming a first conductor in the first through hole, the first metal barrier layer is located between the first conductor and the inner wall of the first through hole and directly with the inner wall of the first through hole touch;

The silicon substrate is etched from a surface of the silicon substrate remote from the first dielectric layer to a surface of the silicon substrate adjacent to the first dielectric layer to form substrate vias in the silicon substrate, An insulating layer is formed on the inner wall of the substrate through hole, a substrate conductor is formed in the substrate through hole, the insulating layer is formed between the substrate conductor and the inner wall of the substrate through hole, the first A through hole is connected to the substrate through hole, and the diameter of one end of the first through hole facing the silicon substrate and the diameter of the end of the substrate through hole facing the first through hole differ within 20%.