WO2022194571A1

WO2022194571A1 - A pixel unit, a pixel array, a time-of-flight imaging sensor and an electronic device

Info

Publication number: WO2022194571A1
Application number: PCT/EP2022/055544
Authority: WO
Inventors: Arastoo KHALILI
Original assignee: Sony Semiconductor Solutions Corporation; Sony Depthsensing Solutions Sa/Nv
Priority date: 2021-03-17
Filing date: 2022-03-04
Publication date: 2022-09-22
Also published as: EP4308965A1

Abstract

Disclosed is a pixel unit having an absorber region, which is to capture light, and two taps arranged on different sides of the absorber region and, which are to collect photogenerated carriers generated in the absorber region. A vertical current-assisted photonic demodulator, CARD, pixel (1), comprises an absorber region (20). A read-out circuit (25) is arranged on top of the absorber region, and a dump circuit (27) is arranged at the bottom of the absorber region. An n+ epi layer (21) is located on the top of the absorber region (20) and an n+ epi layer (23) is located on the bottom of the absorber region (20), such that the n+ epi layers (21, 23) are placed on opposite sides of the absorber region (20). A top p+ isolated region (22) is located within the n+ epi layer (21) and a bottom p+ epi layer (24) is located on the bottom of the absorber region (20). The p+ region (22) is a detector tap and is connected to the read-out circuit (25). The bottom p+ epi layer (24) is a dump tap and is connected to the dump circuit (27). A mixer circuit (26) is connected to the n+ epi layer (21) and to the n + epi layer (23). The pixel unit (1) generates a vertical electric field for modulation from the mix voltage applied by the mix circuit (26). The vertical CARD pixel unit (1) may be realized with both single wafer and stacking processes.

Description

A PIXEL UNIT, A PIXEL ARRAY, A TIME-OF-FLIGHT IMAGING SENSOR AND AN ELECTRONIC DEVICE

TECHNICAL FIELD

The present disclosure generally pertains to the field of Time-of-Flight distance measurements, and in particular to pixel units, pixel arrays, Time-of-Flight imaging sensors and electronic devices.

TECHNICAL BACKGROUND

A time-of-flight camera is a range imaging camera system that determines the distance of objects measuring the Time-of-Flight (ToF) of a light signal between the camera and the object for each point of the image. A time-of-flight camera receives a depth map of a scene. Generally, a time-of- flight camera has an illumination unit that illuminates a region of interest with modulated light, and a pixel array which comprises multiple pixel units that collect light reflected from the same region of interest.

The pixels of a ToF camera typically comprise one or more photosensitive elements (e.g. photodi odes). A photosensitive element converts the incoming light into a current. Typically, in the field of Time-of-Flight, the pixels included in the ToF imaging sensors are for example, Current-Assisted Photonic Demodulator (CAPD) pixels, gated iToF etc. Switches (e.g. transfer gates) that are con nected to the photo diode direct the current to one or more memory elements (e.g. capacitors) that act as accumulation elements that accumulate and/ or store charge. All unit pixels in the ToF sensor are typically controlled by a modulation signal coming from one or more mixing drivers.

A typical ToF camera pixel develops a charge that represents a correlation between the illuminated light and the backscattered light. To enable the correlation between the illuminated light and the backscattered light, each pixel is controlled by the common modulation input coming from the one or more mixing drivers. The modulation input to the pixels is typically synchronous with an illumi nation block modulation.

The load of the mixing drivers is typically capacitive. The power consumed is described by the well- known equation CV²f, where C is the total load capacitance, V is the supply voltage and f is the switching speed of the mixing drivers (or modulation frequency). The mixing drivers consume a lot of power especially when the load capacitance is large, or the modulation frequency is high.

Conventionally the power consumption is reduced by reducing the load capacitance, for example by reducing the photogate/ transfer-gate capacitance. However, it is generally desirable to reduce power consumption and to improve a pixel’s response to the incident light as far as possible. SUMMARY

According to a first aspect the disclosure provides a pixel unit comprising an absorber region config ured to capture light, and two taps arranged on different sides of the absorber region and configured to collect photogenerated carriers generated in the absorber region.

According to a second aspect the disclosure provides a pixel array comprising multiple pixel units, each of the multiple pixel units comprising an absorber region configured to capture light, and two taps arranged on different sides of the absorber region and configured to collect photogenerated carriers generated in the absorber region.

According to a third aspect the disclosure provides a Time-of-Flight imaging sensor comprising a pixel array, the pixel array comprising multiple pixel units, each of the multiple pixel units compris ing an absorber region configured to capture light, and two taps arranged on different sides of the absorber region and configured to collect photogenerated carriers generated in the absorber region.

According to a fourth aspect the disclosure provides an electronic device comprising a Time-of- Flight imaging sensor comprising a pixel array, the pixel array comprising multiple pixel units, each of the multiple pixel units comprising an absorber region configured to capture light, and two taps arranged on different sides of the absorber region and configured to collect photogenerated carriers generated in the absorber region, wherein the electronic device is a Time-of-Flight camera.

Further aspects are set forth in the dependent claims, the following description and the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments are explained by way of example with respect to the accompanying drawings, in which:

Fig. 1 schematically illustrates, in a cross-sectional view, a conventional Current-Assisted Photonic Demodulator (CAPD) pixel, wherein both mix and collector taps are located on the same side of the CAPD pixel;

Fig. 2 schematically illustrates an embodiment of a vertical CAPD pixel, wherein a detector tap, and a dump tap are located in different sides of the vertical CAPD pixel;

Fig. 3 schematically illustrates a vertical cross section of a pixel array structure comprising a plurality of vertical CAPD pixel structures, according to an embodiment;

Fig. 4 schematically illustrates, in a top view, an embodiment of a ToF sensor structure comprising a pixel array in its center and surrounded by global contacts for modulation signal and for dump tap;

Fig. 5 schematically illustrates, in a cross-sectional view, an embodiment of the vertical CAPD pixel array described with regard to Fig. 3, wherein a vertical cut line is depicted; Fig. 6a schematically illustrates an energy band diagram of the vertical CAPD pixel array in the de tection mode;

Fig. 6b schematically illustrates an energy band diagram of the vertical CAPD pixel array in the dump mode;

Fig. 7 schematically illustrates an embodiment of a vertical CAPD pixel having alternate doping po larity, wherein the polarity of the p+ and n+ regions are altered compared to the respective polari ties of the vertical CAPD pixel of Fig. 3;

Fig. 8 schematically illustrates an embodiment of a vertical CAPD pixel having graded doping for n+ epi layers;

Fig. 9 schematically illustrates an embodiment of a vertical CAPD pixel having wide band gap mate rials for the epi layers and wide band gap materials for the isolated regions;

Fig. 10 schematically illustrates an embodiment of a quantum well vertical CAPD pixel array form ing a quantum well infrared photodetector;

Fig. 11 schematically illustrates an embodiment of a quantum dot vertical CAPD pixel array forming a quantum dot infrared photodetector;

Fig. 12 schematically illustrates an embodiment of a stacking process of two half vertical CAPD pixel array implementation using liftoff and stacking techniques; and

Fig. 13 schematically illustrates an embodiment of a two-tap vertical CAPD pixel array, which is im plemented using the stacking process of Fig. 12.

DETAILED DESCRIPTION OF EMBODIMENTS

Before a detailed description of the embodiments under reference of Figs. 1 to 13, general explana tions are made.

As mentioned in the outset, a time-of-flight camera has an illumination unit that illuminates a region of interest with modulated light, and a pixel array which comprises multiple pixel units that collect light reflected from the same region of interest. The pixel units are typically based on the semicon ductor technology. In a semiconductor, free charge carriers, such as electron-hole pairs are created by excitation of electron from valence band to the conduction band. This excitation left a hole in the valence band which behaves as positive charge and an electron-hole pair is created.

The embodiments described below provide a pixel unit comprising an absorber region configured to capture light, and two taps arranged on different sides of the absorber region and configured to col lect photogenerated carriers generated in the absorber region. The absorber region may be a region of the pixel unit that captures the incident light. By absorbing the photons of incident light, the electrons of the valence band become excited. Photogenerated car riers such as photogenerated holes and photogenerated electrons are generated, in the absorber re gion, by the excitation of the electrons from valence band to the conduction band. The absorber region may be an intrinsic absorber region, a lightly doped absorber region, or the like. For materials with high photon absorption capability like GaAs based material, 1.5 to 5 mth thick absorber region may be sufficient to absorb most of the photons with energy higher than the bandgap. For silicon the thickness of the absorber region may be similar to Current- Assisted Photonic Demodulator (CAPD) (5 mth ~ 1 mth). Depending on the material used for the pixel unit and the thickness of the absorber region, different voltage levels may be applied to the pixel unit.

The pixel unit may be a CAPD pixel unit having two taps arranged on different sides of the ab sorber region, such that the photogenerated carrier transport may be only a drift process and not a pardy diffusion and pardy drift transport, therefore the response to the incident light may be im proved and a pixel unit with a relatively small pixel size may be fabricated with different semicon ductor materials, such as for example III-V semiconductor materials, or die like. The pixel unit may use vertical electric field for modulation and may have global contacts for modulation signal.

Traditional Current-Assisted Photonic Demodulator (CAPD) structures have both mix taps and col lector taps on the same side. CAPD pixels are often planar which means the mix signal, and the tap are located on one side of the pixel, which results in a relatively large pixel size. In addition, realizing traditional CAPD pixels with isolated taps is not feasible with some materials, such as with InGaAs for Short-Wave InfraRed (SWIR) application. Arranging the taps on different sides of the absorber region as disclosed in the embodiments allows to realize CAPD pixels with isolated taps with materi als such as with InGaAs for Short-Wave InfraRed (SWIR) application.

Additionally, in traditional CAPD pixels, where both taps on the same side typically limits the scala bility of the pixel. Arranging the taps on different sides of the absorber region as disclosed in the embodiments enhances the scalability of the pixel.

Moreover, in gated iToF, vertical transport of the photogenerated carriers is partly diffusion and partly drift. Diffusion transport causes photogenerated carriers to move randomly which results in degradation of the demodulation contrast. Gated iToF may scale to smaller pixel pitch compared to traditional CAPD pixels. However, the vertical transport mechanism of photogenerated carriers in those pixels is partially diffusion and partially drift.

The different sides of the absorber region at which the taps are located may include a first side and a second side which are opposite sides. For example, a first side may be on the top of the pixel unit and a second side may be at the bottom of the pixel unit, or the like. Since the taps may not on the same side and the pixel unit size may not be limited by tap spacing. The taps may be a n+/ p+ iso lated region, and/ or an n/ p epitaxial layer, or a pin located on the n+/ p+ isolated region, and/ or on the n/ p epitaxial layer, or the like.

The two taps may include a tap on a top of the absorber region, and a tap at a bottom of the ab sorber region. The bottom of the absorber region may be a light incident side. For example, in a back illuminated pixel unit, the light incident side is the bottom of the absorber region. Alternatively, the pixel unit may be a front illuminated pixel unit. In a front illuminated pixel unit, the light inci dent side is the top of the absorber region.

In some embodiments the tap on the top of the absorber region is a detector tap configured to col lect photogenerated holes. A detector tap is typically arranged to be connected to readout circuit in order to supply collected charge to the readout circuit. For example, in a detection mode, photogen erated holes may be collected by the detector tap through a p+ isolated region located on the top of the absorber region. Alternatively, the detector tap may be the p+ isolated region located on the top of the absorber region in which the photogenerated holes are collected. The detector tap may be connected to read-out circuits that read out the signals from the p+ isolated region.

In some embodiments, the tap at the bottom of the absorber region may be a dump tap. The dump tap may for example be configured to collect photogenerated holes in a dump mode. The photogen erated holes may for example be collected to the dump tap through a p+ epitaxial layer at the bot tom of the absorber region. Alternatively, the dump tap may be the p+ epitaxial layer at the bottom of the absorber region in which the photogenerated holes are collected. The dump tap may be con nected to a dump circuit, such that the bottom p+ epitaxial layer can provide signals regarding the dumped photogenerated carries.

In some embodiments, the pixel unit further comprises an n+ epitaxial layer on the top of the ab sorber region and an n+ epitaxial layer at the bottom of the absorber region. The n+ epitaxial layers may be configured to collect photogenerated electrons, and the n+ epitaxial layers may be biased to create a drift field and may be configured to generate a modulation field in the absorber, such that a vertical electric field is generated when a voltage is applied. The n+ layers are on both sides of the absorber region and may be collect photogenerated electrons. The n+ layers, which are highly doped regions are n+ guiding regions which can be implemented as epitaxial layers or n-well depending on the material. For example, regarding the highly doped regions, depending on the material, for exam ple, in silicon, if the processing allows, the n+ epi layers can be n-well. It allows for subgrouping pix els and applying different mix signals to each group of pixels with local contacts instead of global, e.g. by etching or other process techniques. Also, the dump contact can be realized locally for each group optionally. Therefore, the guiding signal can be implemented globally for the whole array or by sub-groups if it is realized with n-wells.

In some embodiments, the pixel unit may further comprise a p+ epitaxial layer at the bottom of the absorber region, wherein the n+ epitaxial layer may be located between the absorber region and the p+ epitaxial layer at the bottom of the absorber region.

The bottom p+ epitaxial layer may be implemented as a global dump tap, such that in a case of a pixel array including multiple pixel units, the multiple pixel units have a common p+ epitaxial layer at the bottom of the absorber region, i.e. a global common (n+, p+) layer.

The bottom p+ epitaxial layer and the n+ epitaxial layer located on the top and at the bottom of the absorber region, may be global contacts. The bottom p+ global contact may be used to connect the p+ epitaxial layer to the dump circuit. The n+ global contacts may be used for modulation signal. These global contacts may be implemented optionally at all sides. Global connections may be as sisted by metal connection, such that resistance is reduced.

The pixel unit may further comprise a p+ isolated region within an n+ epitaxial layer on the top of the absorber region, the p+ isolated region may be configured to collect photogenerated holes. Dif ferent layout shapes may be used to implement isolated taps. Additionally, the thickness of each doped region, such as the p+ isolated regions, may be chosen differently, depending on the material, the process conditions and the design specification. The size of n+ and p+ regions are relatively small compare to the size of the absorber region, e.g. few 10s of nanometer to few 100s of nanome ter, without limiting the present disclosure in that regard. Moreover, on the illuminated side, n+ and p+ layers may be thin to allow the photons to reach the absorber region, for example a few nm to few 10s of nm, without limiting the present disclosure in that regard. In a case of using Wide Band Gap (WBG) layers, keeping n+ and p+ layers thin may not be a restriction. On the detector side, e.g. on the side of the p+ isolated region, the encapsulation of n+ over p+ may be chosen differ ently depending on the design specification, however it may be thin for enhancing the collection of holes.

Alternatively, an implementation with alternate polarity of p and n regions may be performed. For example, the pixel unit may comprise an n+ isolated region within a p+ epitaxial layer on the top of the absorber region, the n+ isolated region may be configured to collect photogenerated electrons, and an n+ epitaxial layer and a p+ epitaxial layer at the bottom of the absorber region, wherein the p+ epitaxial layer is located between the absorber region and the n+ epitaxial layer.

In some embodiments, the pixel unit comprises a mixer circuit connected to the n+ epitaxial layer on top of the absorber region and to the n+ epitaxial layer at the bottom of the absorber region. This mixer circuit is arranged to connect the pixel unit to a modulation circuitry configured to sup ply a mix signal. The mixer circuit may for example be connected to a global connector for connect ing the pixel unit to a modulation circuitry.

The n+ epitaxial layer on the top of the absorber region and the n+ epitaxial layer at the bottom of the absorber region may generate a modulated vertical electric field within the absorber region. For example, vertical electric field modulation is implemented with n+ epitaxial layers at the top and the bottom of the absorber that are connected to MIX (modulation) circuitry. When a vertical electric field is generated and based on which side of the absorber region a voltage is applied to, the holes are collected to the detector tap at/ through the p+ isolated region or to the dump tap at/ through the p+ epitaxial layer, or the like. For any modulation voltage applied to the pixel unit, all n+ / p+ junctions may be at reverse bias. Depending on the material used for the pixel unit and the thickness of the absorber region, different voltage levels may be applied to the pixel unit.

The n+ epitaxial layer on the top and on the bottom of the absorber region may be a graded doped n+ epitaxial layer.

The n+ epitaxial layer on the top and on the bottom of the absorber region may be a wide band gap epitaxial layer. For example, in case of III-V materials, a wide gap material may be employed for highly doped epitaxial layers.

In some embodiments, the p+ isolated region may be implemented as a detector tap. Alternatively, a pin located on the p+ isolated region may be implemented as a detector tap. Still alternatively, an n+ isolated region or a pin located on the n+ isolated region may be implemented as a detector tap.

In some embodiments, the p+ epitaxial layer may be implemented as a dump tap. Alternatively, a pin located on the p+ epitaxial layer may be implemented as a dump tap. Still alternatively, a n+ epi taxial layer or a pin located on the n+ epitaxial layer may be implemented as a dump tap.

The p+ epitaxial layer may be a wide band gap epitaxial layer.

In some embodiments, the pixel unit further comprises an n+ isolated region within an p+ epitaxial layer on the top of the absorber region, and a p+ epitaxial layer and n+ epitaxial layer at the bottom of the absorber region. For example, the p+ epitaxial layer may be located between the absorber re gion and the n+ epitaxial layer. Different layout shapes may be used to implement isolated taps. Ad ditionally, the thickness of each doped region, such as the n+ isolated regions, may be chosen differently, depending on the material, the process conditions and the design specification.

In some embodiments, the pixel unit is a vertical CAPD pixel unit. In such a vertical CAPD pixel unit the mix signal may be applied across the absorber region and both the photogenerated electron and the photogenerated holes may be collected via the detector tap and the dump tap at each side of the absorber region.

A vertical CAPD pixel unit may be implemented with alternate doping polarity, with graded doping for epitaxial layers, employing wide band gap (WBG) material for highly doped epitaxial layers, or the like. The vertical CAPD pixel unit may be fabricated with liftoff and stacking techniques, or the like. The vertical CAPD pixel unit may be also realized with both single wafer and stacking pro cesses, or the like. The vertical CAPD pixel unit may be realized with thin film approaches by re moving the substrate, or the like. Light trapping and light management techniques may be employed to enhance light absorption, or the like. Light diffusion filters, light diffraction patterns, ARC and lenses may be additionally employed.

In some embodiments, a quantum-dot stack may be formed within the absorber region. The quan tum-dot (QD) stack may be a QD infrared photodetector having narrow absorption spectrum that can be tailored to match Short-Wave InfraRed (SWIR), Medium-Wave InfraRed (MWIR) and Long- Wave InfraRed (LWIR) bands by engineering the quantum confined states. The QD infrared photo detector may be made using wide range of materials or maybe made using III-V semiconductors based on GaAs or InP substrates, or the like.

In some embodiments, a quantum-well stack may be formed within the absorber region.

In some embodiments, the taps on the top and at the bottom of the absorber region may be a detec tor tap. Such a pixel unit may be fabricated with liftoff and stacking techniques and a dump node may be isolated and may be implemented like a detector tap connected to a readout circuit in order to realize vertical CAPD with two taps.

The embodiments also disclose a pixel array comprising multiple pixel units, each of the multiple pixel units comprising an absorber region configured to capture light, and two taps arranged on dif ferent sides of the absorber region and configured to collect photogenerated carriers generated in the absorber region. Such a pixel array may for example have no need for n+ isolation taps to imple ment CAPD with InGaAs for SWIR applications.

The embodiments also disclose a Time-of-Flight imaging sensor comprising a pixel array comprising multiple pixel units, each of the multiple pixel units comprising an absorber region configured to capture light, and two taps arranged on different sides of the absorber region and configured to col lect photogenerated carriers generated in the absorber region.

The embodiments also disclose an electronic device comprising a Time-of-Flight imaging sensor comprising a pixel array comprising multiple pixel units, each of the multiple pixel units comprising an absorber region configured to capture light, and two taps arranged on different sides of the ab sorber region and configured to collect photogenerated carriers generated in the absorber region.

For example, the electronic device may be a Time-of-Flight camera.

Conventional CAPD pixel and Gated iToF pixel

Typically, a conventional Time-of-Flight (ToF) sensor comprises a pixel array, such as a CAPD pixel array. The ToF CAPD pixel array comprises a plurality of conventional CAPD pixels, such as the conventional CAPD pixel described with regards to Fig. 1 below.

Fig. 1 schematically illustrates, in a cross-sectional view, a conventional Current- Assisted Photonic Demodulator (CAPD) pixel, wherein both mix taps and collector taps are located on the same side of the CAPD pixel.

The conventional pixel of Fig. 1 is a two-tap Current- Assisted Photonic Demodulator (CAPD) hav ing two different kind of taps, i.e. different kind of terminals, namely mix taps and collector taps.

The conventional CAPD pixel of Fig. 1 has a low doped substrate 14, n+ isolated regions 12 and p+ isolated regions 13 inside the substrate 14 and two collector taps 10 and two mix taps 11, all located on the same side of the conventional CAPD pixel, e.g. on the top of the pixel. The collector taps 10 (i.e. detector taps) are located on top of the n+ isolated regions 12 and the mix taps 11 are located on top of the p+ isolated regions 13. The width of the pixel may for example be 5 mth.

An electrical field is setup to move the electrons to collector taps 10. The collector taps 10 consist of reverse biased diodes. Modulation is achieved by alternately changing the direction of the voltage applied between the mix taps 11. Due to this modulating field applied within the substrate, electrons that are generated deep in the substrate can be collected. The voltage used for demodulation con trols the electric field intensity and thus the drift velocity of the generated electrons.

Vertical CAPD pixel

Fig. 2 schematically illustrates an embodiment of a vertical CAPD pixel, wherein a detector tap, and a dump tap are located on different sides of the vertical CAPD pixel. The vertical CAPD pixel 1 , comprises an absorber region 20. A read-out circuit 25 is arranged on top of the absorber region, and a dump circuit 27 is arranged at the bottom of the absorber region. The absorber region 20 is an intrinsic or lightly doped absorber epitaxial (epi). An n+ epi layer 21 is located on the top of the ab sorber region 20 and an n+ epi layer 23 is located on the bottom of the absorber region 20, such that the n+ epi layers 21 and 23 are placed on opposite sides of the absorber region 20. A top p+ isolated region 22 is located within the n+ epi layer 21 on the top of the absorber region 20 and a bottom p+ epi layer 24 is located on the bottom of the absorber region 20. The n+ epi layer 23 is placed between the p+ epi layer 24 and the absorber region 20. The p+ region 22 on the top of the pixel unit 1 is a detector tap and is connected to the read-out circuit 25, such that the p+ region 22 provides signals for the vertical CAPD pixel 1 and the read-out circuit 25 reads out the signals from the p+ region 22 being the detector tap. The bottom p+ epi layer 24 is a dump tap and is connected to the dump circuit 27, such that the bottom p+ epi layer 24 provides signals regarding dumped car riers. A mixer circuit 26 which provides a mix signal to the pixel is connected to the n+ epi layer 21 on top of the pixel unit 1 and to the n+ epi layer 23 at the bottom of the pixel unit 1. The pixel unit 1 generates a vertical electric field for modulation from the mix voltage applied by the mix circuit 26 to the pixel array 3. The vertical CAPD pixel unit 1 may be also realized with both single wafer and stacking processes, or the like.

A pixel, such as the vertical CAPD pixel 1 is part of a time-of-flight (ToF) system that has a modu lated light source, such as pulse or sinusoid or the like, wherein the modulated light source emits modulated radiation towards a scene. The reflected radiation has a certain phase shift with respect to the emitted light depending on the depth of the scene. Mixing the absorbed light in the pixel, such as vertical CAPD pixel 1 in Fig. 2, with set of demodulation signals (MIX) that are phase shifted ver sions of emitted light signals, the phase deference between the received light signal and the emitted one can be extracted. In the embodiment of Fig. 2, the MIX are applied vertically by MIX circuit and the signal is read out from the detector tap, such as the p+ region 22.

In the embodiment of Fig. 2, the detector tap is implemented as the p+ region 22 on the top of the pixel unit 1. Alternatively, the detector tap may be implemented as a pin located on the p+ region 22 and that connects the p+ region 22 to the read-out circuit 25, such as the pin 42 in Fig. 4. In the em bodiment of Fig. 2, the n+ epi layer 21 on top of the pixel unit 1 and to the n+ epi layer 23 at the bottom of the pixel unit 1 are the mix taps that connect the mixer circuit 26 to the n+ epi layers 21 and 23. Alternatively, the mix taps may be implemented as contacts located on the n+ epi layers 21 and 23, such as the n-top contact 41 (see Fig. 4) that connects the n+ epi layer 21 to the mixer cir cuit 26 and such as the n-bot contact 43 (see Fig. 4) that connects the n+ epi layer 23 to the mixer circuit 26. In the embodiment of Fig. 2, the bottom p+ epi layer 24 is the dump tap, without limiting the present embodiment in that regard. Alternatively, the dump tap may be implemented as contact located on the bottom p+ epi layer 24 and that is connected to the dump circuit 27, such as the p dump contact 44 in Fig. 4.

In the embodiment of Fig. 2, the read-out circuits 25 arranged on top of the absorber region 20, and the dump circuit 27 is arranged at the bottom of the absorber region 20, without limiting the present embodiment in that regard. For example, the read-out circuit 25 and the dump circuit 27 may be lo cated anywhere, for example, to the top, to the bottom, or the like. However, the read-out circuit 25 is connected to the p+ isolated region 22 and the dump circuit 27 is connected to the bottom of the vertical CAPD (by etching or other techniques).

A ToF sensor according to the embodiments comprises a plurality of pixel units, such as the vertical CAPD pixel 1 shown in Fig. 2.

The absorber region 20 may for example be implemented as an intrinsic or lightly doped absorption region, such as a GaAs based material, a Silicon based material, InGaAs, any III-V material, or mate rials such as FlgCdTe, Si, or the like. For example, materials with high photon absorption capability like GaAs based materials may be used. The absorption region thickness may for example be 1 mth to 5 mth. An absorber of such thickness absorbs most of the photons with energy higher than the bandgap. For an absorption region made of Silicon, the thickness of the absorber may be, for exam ple 3 mth to 7 mΐh. The n+ epi layers 21 and 23 are preferably thin regions in order to facilitate the collection of holes by the p+ region 22. The voltage level of the mixer circuit 26 may for example be 1.5 V and 3 V, the voltage level of the read-out circuit 25 may for example be 0.5 V, and the voltage level of the dump circuit 27 may for example be 0.5 V, without limiting the disclosure in that regard. For any modulation voltage, all n+/p+ junctions are at reverse bias. The dump circuit 27 voltage level may not be equal to the voltage level of the read-out circuit 25 but it is desirable to be lower than the voltage level of the mixer circuit 26 to preserve reverse bias of n+/ p+ junction. Depending on the material used for the vertical CAPD pixel 1 and the thickness of the absorber region 20, the voltage levels can be different.

The n+ layers, which are highly doped regions are n+ guiding regions which can be implemented as epitaxial layers or n-well depending on the material. For example, regarding the highly doped re gions, depending on the material, for example, in silicon, if the processing allows, the n+ epi layers can be n-well. It allows for subgrouping pixels and applying different mix signals to each group of pixels with local contacts instead of global, e.g. by etching or other process techniques. Also, the dump contact can be realized locally for each group optionally. Thus, the guiding signal can be im plemented globally for the whole array or by sub-groups if it is realized with n-wells.

In the embodiment of Fig. 2, the vertical CAPD pixel 1 is a backside illumination pixel, without lim iting the present invention in that regard. Alternatively, the vertical CAPD pixel 1 may be a frontside illumination pixel. In case of backside illumination, the vertical CAPD pixel may have a substrate of material with larger bandgap to avoid absorption of the photons within the substrate. For example, in a case where the material of the absorber region 20 is InGaAs, the substrate can be InP. Alterna tively, to avoid absorption of the photons within the substrate, the vertical CAPD pixel may have no substrate, for example, thin film structure, such that the vertical CAPD pixel may have on the bot tom of the pixel structure the n+ epi layer 23 and the p+ epi layer 24, as the vertical CAPD pixel 1 described with regards to Fig. 2.

In the embodiment of Fig. 2, the thickness of each doped region, such as the p+ isolated regions, may be chosen differently, depending on the material, the process conditions and the design specifi cation. The size of n+ and p+ regions are relatively small compare to the size of the absorber re gion. For example, the thickness of the p+ isolated regions (see 22 in Fig. 2) and the thickness of the n+ and p+ layers (see 21, 23 and 24 in Fig. 2) is few 10s of nanometer, and the thickness of the ab sorber region (see 20 in Fig. 2) is a few 100s of nanometers, without limiting the present embodi ment in that regard. For example, the thickness of the absorber region may be from few 100s of nanometers to few micrometers. Moreover, on the illuminated side, n+ and p+ layers (see 21, 23 and 24 in Fig. 2) may be thin to allow the photons to reach the absorber region (see 20 in Fig. 2), for example a few nm to few 10s of nm, without limiting the present embodiment in that regard. On the detector side, e.g. on the side of the p+ isolated region (see 22 in Fig. 2), the encapsulation of n+ over p+ may be chosen differently depending on the design specification, however it may be thin for enhancing the collection of holes.

Fig. 3 schematically illustrates a vertical cross section of a pixel array structure comprising a plurality of vertical CAPD pixel structures, according to an embodiment. A vertical CAPD pixel array 2 com prises a plurality of vertical CAPD pixels 1, e.g. CAPD pixels as described with regard to Fig. 2 above. The vertical CAPD pixel array 2 comprises an absorber region 30 with a plurality of read-out circuits 35 arranged on top of the absorber region 30, and one dump circuit 37 arranged at the bot tom of the absorber region 30. The absorber region 30 may for example be an intrinsic or lightly doped absorber epitaxial (Int/n-). An n+ epi layer 31 is on the top of the absorber region 30 and an n+ epi layer 33 is on the bottom of the absorber region30, such that the n+ epi layers 31 and 33 are placed on opposite sides of the absorber region 30. A top p+ isolated region 32 is within the n+ epi layer 31 on the top of the absorber region 30 and a bottom p+ epi layer 34 is placed on the bottom of the absorber region30. The n+ epi layer 33 is placed between the p+ epi layer 34 and the ab sorber region 30. The p+ regions 32 on the top of the pixel array 2 are detector taps, and each one of the p+ regions 32 are connected to a respective read-out circuit 35, such that the p+ regions 32 provide signals for the vertical CAPD pixel 2 and the read-out circuits 35 read out the signals from the p+ regions 32. The bottom p+ epi layer 34 is a dump tap and is connected to the dump circuit 37, such that the bottom p+ epi layer 34 provides signals regarding dumped carries. In Fig. 3, a pixel unit comprised in the vertical CAPD pixel array 2 is represented by dashed rectangle 38. A mixer cir cuit 36 is connected to the n+ epi layer 31 on top of the pixel array 2 and to the n+ epi layer 33 at the bottom of the pixel array 2, and is used to apply mix voltage to the pixel array 2, such that a ver tical electric field is generated between the n+ epi layers 31 and 34. The vertical CAPD pixel array 2 comprises a plurality of pixel units 1 (see Fig. 2), which can be realized with both single wafer and stacking processes, or the like.

In the embodiment of Fig. 3, the plurality of read-out circuits 35 arranged on top of the absorber region 30, and the dump circuit 37 is arranged at the bottom of the absorber region 30, without lim iting the present embodiment in that regard. For example, the read-out circuits 35 and the dump cir cuit 37 may be located anywhere, for example, to the top, to the bottom, or the like. Flowever, the read-out circuits 35 are connected to the p+ isolated regions 32 and the dump circuit 37 is con nected to the bottom of the vertical CAPD (by etching or other techniques).

In the embodiment of Fig. 3, the detector tap is implemented as the p+ region 32 on the top of the pixel array 2. Alternatively, the detector tap may be implemented as a pin located on the p+ region 32 and that connects the p+ region 32 to the read-out circuit 35, such as the pin 42 in Fig. 4. In the embodiment of Fig. 3, the n+ epi layer 31 on top of the pixel array 2 and to the n+ epi layer 33 at the bottom of the pixel array 2 are the mix taps that connect the mixer circuit 36 to the n+ epi layers 31 and 33. Alternatively, the mix taps may be implemented as contacts located on the n+ epi layers 31 and 33, such as the n-top contact 41 (see Fig. 4) that connects the n+ epi layer 31 to the mixer circuit 36 and such as the n-bot contact 43 (see Fig. 4) that connects the n+ epi layer 33 to the mixer circuit 36. In the embodiment of Fig. 3, the bottom p+ epi layer 34 is the dump tap, without limiting the present embodiment in that regard. Alternatively, the dump tap may be implemented as contact located on the bottom p+ epi layer 34 and that is connected to the dump circuit 37, such as the p dump contact 44 in Fig. 4.

In the pixel array 2 of Fig. 3, vertical arrows 39 having a dotted pattern and a dashed pattern repre sent a vertical electric field (used for modulation) between the n+ epi layers 31 and 33. The gradient of the vertical electric field, which is represented by a dotted curved line, in the pixel array 2 of Fig. 3, corresponds to a dump mode in which holes are collected at the bottom p+ epi layer 34. The gradient of the vertical electric field, which is represented by a dashed-dotted curved line, in the pixel array 2 of Fig. 3, corresponds to a detection mode in which holes are collected at the p+ region 32.

In the embodiment of Fig. 3, the n+ epi layers 31 and 33 and the p+ epi layer 34 are global contacts, wherein the bottom p+ global contact is used to connect the p+ epitaxial layer 34 to the dump cir cuit 37 and to keep the n+ / p+ diode at reverse bias, and the n+ global contact is used for a modula tion signal. These layers are common layers for the plurality of vertical CAPD pixels comprised in the vertical CAPD pixel array 2. The bottom p+ epi layer 34 is a global dump tap of the vertical CAPD pixel array 2 and which transmits the signal regarding the dumped carriers to the dump cir cuit 37. The vertical CAPD pixel array 2 described in the embodiment with regard to Fig. 3, may be a part of a vertical CAPD pixel array comprised in a ToF sensor.

The n+ layers, which are highly doped regions are n+ guiding regions which can be implemented as epitaxial layers or n-well depending on the material. For example, regarding the highly doped re gions, depending on the material, for example, in silicon, if the processing allows, the n+ epi layers can be n-well. It allows for subgrouping pixels and applying different mix signals to each group of pixels with local contacts instead of global, e.g. by etching or other process techniques. Also, the dump contact can be realized locally for each group optionally. Hence, the guiding signal can be im plemented globally for the whole array or by sub-groups if it is realized with n-wells.

In the embodiment of Fig. 3, the thickness of each doped region, such as the p+ isolated regions, may be chosen differently, depending on the material, the process conditions and the design specifi cation. The size of n+ and p+ regions are relatively small compare to the size of the absorber re gion. For example, the thickness of the p+ isolated regions (see 32 in Fig. 3) and the thickness of the n+ and p+ layers (see 31, 33 and 34 in Fig. 3) is few 10s of nanometer, and the thickness of the ab sorber region (see 30 in Fig. 3) is a few 100s of nanometer, without limiting the present embodiment in that regard. For example, the thickness of the absorber region may be from few 100s of nanome ters to few micrometers. Moreover, on the illuminated side, n+ and p+ layers (see 31, 33 and 34 in Fig. 3) may be thin to allow the photons to reach the absorber region (see 30 in Fig. 3), for example a few nm to few 10s of nm, without limiting the present embodiment in that regard. On the detector side, e.g. on the side of the p+ isolated region (see 32 in Fig. 3), the encapsulation of n+ over p+ may be chosen differendy depending on the design specification, however it may be thin for enhanc ing the collection of holes.

Fig. 4 schematically illustrates, in a top view, an embodiment of a ToF sensor structure comprising a pixel array in its center, including detector contacts and surrounded by global contacts for modula tion signal and for dump circuit. The top view of the ToF sensor structure of Fig. 4 comprises a pixel array, such as the vertical CAPD pixel array 2 described with regard to Fig. 3. In Fig. 4, possi ble locations of global contacts, such as the p dump contacts and the n top/bottom contacts are il lustrated.

A plurality of p dump contacts 44, represented in the top view of Fig. 4 by rectangles having a dot ted pattern, are located on the p+ epi layer 34, and they are the junction(s) from the semiconductor to the dump circuit (see 37 in Fig. 3), wherein the dump circuit can be located anywhere. A plurality of n+ contacts described with regard to Fig. 3, are the n-top contacts 43 and n-bottom contacts 41 , represented in the top view of Fig. 4 by rectangles having a dashed pattern. The n-top contacts 43 are located on the n+ epi layer 31 and the n-bottom contacts 41 are located on the n+ epi layer 33, and they are in correspondence with the junction(s). The mixer circuit 36 of Fig. 3 can be located anywhere. On the top of the absorber region (see 30 in Fig. 3) are placed the p+ isolated regions 32 within the n+ epi layer 31. A plurality of the p+ contacts 42, which are located on top of the p+ iso lated regions 32, are represented by squares having dotted pattern.

In the embodiment of Fig. 4, the global contacts for the modulation signal and for the dump, namely the p dump contacts 44, the n-top contacts 43 and n-bottom contacts 41 , are implemented at all sides of the vertical CAPD pixel array 2, without limiting the present embodiment in that regard. Alternatively, the global contacts for modulation signal and for the dump may be implemented on one side, or the like. For example, the vertical CAPD pixel array 2 may have one p dump contact 44, and one n-top contact 41 and one n-bottom contact 42, such that to be connected to the dump cir cuit 37 and the mixer circuit 36 of Fig. 3, respectively.

Fig. 5 schematically illustrates, in a cross-sectional view, an embodiment of the vertical CAPD pixel array 2 described with regard to Fig. 3, wherein a vertical cut line is depicted. The dashed line 50 in Fig. 5 represents a vertical cut line that has a start cut point pi at the top of the p+ region 32, where the detector tap is located and an end cut point p2 at the bottom of the p+ epi layer 34 of the verti cal CAPD pixel array 2, where the dump tap is located. The n+ epi layers 31 and 33 collect photo generated electrons and the p+ isolated regions 32 collect photogenerated holes. The n+ epi layers 31 and 33, at front and the backside of the vertical CAPD pixel array 2, are biased to create a drift field. This bias condition is such that it guarantees that the n+/p+ diodes are always at reverse bias. At the cut pl-p2, an energy band is obtained with an applied modulation signal, as described in Fig. 6 in the following.

In a case where incident electromagnetic radiation such as light in the form of a photon is incident within the vertical CAPD pixel array 2, the energy associated with the photon is absorbed, and an electron hole pair is generated. In the energy band diagram, E_c is the conduction band and E_v is the valence band. In Figs. 6a and 6b, an energy band diagram of the vertical CAPD pixel array 2 (see Figs. 3 and 5) on a detection mode and on a dump mode is described respectively, wherein the en ergy band bends due to the applied reverse bias. The cut point pi (see Fig. 5) which is located on the detector tap (see 32 and 42 in Figs. 3, 4 and 5) is the pl(Det), in the energy band diagram shown in Figs. 6a and 6b, and the cut point p2 (see Fig. 5) which is located on the dump tap (see 34 in Figs. 3 and 5) is the p2(Dump), in the energy band diagram shown in Figs. 6a and 6b. The black arrows in dicate the direction of movement of the photogenerated electrons and of the photogenerated holes. The detection mode and the dump mode are created by a modulation by applying a modulation sig nal which is related to modulation frequency of the light source at sensor level with a predetermined phase-shift. The photogenerated carriers, i.e. photogenerated electrons and holes, go up and down based on a mix voltage applied by the mix circuit 36. The applied mix voltage generates a vertical electric field between n+ epi layers while n+/p+ junctions are kept at reverse bias. The detection mode is a detection cycle in which the vertical electric field guides the carriers towards the detector tap, that is the p+ region 32, which is connected to the read-out circuit 35 that reads out the photo generated signal. The dump mode is a dump cycle in which the vertical electric field guides the carri ers towards the dump tap, that is the p+ epi layer 34, which is connected to the dump circuit 37, to make an alternate reading of the detector taps. In a two tap pixel case, at one cycle one tap is read out and on other cycle the other tap is read out. The isolated p+ regions 32 (detector taps) provide signals for each individual pixel and, the p+ epi layer 34 (dump tap) at the bottom is connected to dump circuit.

Fig. 6a schematically illustrates an energy band diagram of the vertical CAPD pixel array in the de tection mode. The potential of the holes is the valence band E_v and the potential of the electrons is the conduction band E_c. In the detection mode, the photogenerated holes are collected by the p+ isolated regions 32 at the top of the vertical CAPD pixel array, and the photogenerated electrons are collected by the n+ epi layer 33 at the bottom of the vertical CAPD pixel array.

Fig. 6b schematically illustrates an energy band diagram of the vertical CAPD pixel array in the dump mode. The potential of the holes is the valence band E_y and the potential of the electrons is the conduction band E_c. In the dump mode, the photogenerated holes are collected by the p+ epi layer 34 at the bottom of the vertical CAPD pixel array, and the photogenerated electrons are col lected by the n+ epi layer 31 at the top of the vertical CAPD pixel array.

Alternative implementations

Fig. 7 schematically illustrates an embodiment of a vertical CAPD pixel having alternate doping po larity, wherein the polarity of the p+ and n+ regions are altered compared to the respective polari ties of the vertical CAPD pixel of Fig. 3. The vertical CAPD pixel array 3 comprises a plurality of vertical CAPD pixels. A vertical CAPD pixel comprised in the vertical CAPD pixel array 3 is repre sented by dashed rectangle 78. The vertical CAPD pixel array 3 comprises an absorber region 70, with a plurality of read-out circuits 75 arranged on top of the absorber region 70, and a dump circuit 77 arranged at the bottom of the absorber region 70. The absorber region 70 may be an intrinsic or lightly doped absorber epitaxial (Int/p-). A p+ epi layer 71 is located on the top of the absorber re gion 70 and an p+ epi layer 73 is located on the bottom of the absorber region 70, such that the p+ epi layers 71 and 73 are placed on opposite sides of the absorber region 70. An n+ isolated region 72 is located within the p+ epi layer 71 on the top of the absorber region 70 and an n+ epi layer 74 is placed on the bottom of the absorber region 70. The p+ epi layer 73 is placed between the n+ epi layer 74 and the absorber region 70. The n+ isolated region 72 are detector taps, and each one of the n+ isolated region 72 are connected to a respective read-out circuit 75, such that the n+ isolated re gion 72 provide signals for the vertical CAPD pixel 3 and the read-out circuits 75 read out the sig nals from the n+ isolated region 72. The bottom n+ epi layer 74 is a dump tap and is connected to the dump circuit 77, such that the bottom p+ epi layer 74 provides signals regarding dumped carries. A mixer circuit 76 is connected to the p+ epi layer 71 on top of the pixel array 3 and to the p+ epi layer 73 at the bottom of the pixel array 3, and is used to apply mix voltage to the pixel array 3, such that a vertical electric field is generated between the p+ epi layers 71 and 74.

In the embodiment of Fig. 7, the plurality of read-out circuits 75 arranged on top of the absorber region 70, and the dump circuit 77 is arranged at the bottom of the absorber region 70, without lim iting the present embodiment in that regard. For example, the read-out circuits 75 and the dump cir cuit 77 may be located anywhere, for example, to the top, to the bottom, or the like. However, the read-out circuits 75 are connected to the n+ isolated regions 72 and the dump circuit 77 is con nected to the bottom of the vertical CAPD (by etching or other techniques).

In the embodiment of Fig. 7, the p+ epi layers 71 and 73 and the n+ epi layer 74 are global contacts, wherein the bottom n+ global contact is used to connect the n+ epitaxial layer 74 to the dump cir cuit 77 and to keep the n+/ p+ diode at reverse bias, and the p+ global contact is used for the mod ulation signal supplied via mixer circuit 76, since these layers are common layers for the plurality of vertical CAPD pixels comprised in the vertical CAPD pixel array 3. The dump circuit 77 is a global dump circuit connected to the global dump tap of the vertical CAPD pixel array 3, that is the n+ epi layer 74. The vertical CAPD pixel array 3 described in the embodiment with regard to Fig. 7 can be a part of a vertical CAPD pixel array comprised in a ToF sensor.

In the embodiment of Fig. 7, the detector tap is implemented as the n+ region 72 on the top of the pixel array 3. Alternatively, the detector tap may be implemented as a pin located on the n+ region 72 and that connects the n+ region 72 to the read-out circuit 75. In the embodiment of Fig. 7, the p+ epi layer 71 on top of the pixel array 3 and to the p+ epi layer 73 at the bottom of the pixel array 3 are the mix taps that connect the mixer circuit 76 to the p+ epi layers 71 and 73. Alternatively, the mix taps may be implemented as contacts located on the p+ epi layers 71 and 73 that connects the p+ epi layer 71 to the mixer circuit 76 and the p+ epi layer 73 to the mixer circuit 76. In the embodi ment of Fig. 7, the bottom n+ epi layer 74 is the dump tap, without limiting the present embodi ment in that regard. Alternatively, the dump tap may be implemented as contact located on the bottom n+ epi layer 74 and that is connected to the dump circuit 77.

Fig. 8 schematically illustrates an embodiment of a vertical CAPD pixel array, such as the vertical CAPD pixel array 2 described with regard to Fig. 3, wherein the vertical CAPD pixel array has graded doping for n+ epi layers. The vertical CAPD pixel array 4 comprises a plurality of the vertical CAPD pixels 1 such as described with regard to Fig. 2. The vertical CAPD pixel array 4 comprises an absorber region 30 (see Fig. 3), with a plurality of circuits arranged at the top of the absorber re gion 30, such as the read-out circuit 35 (see Fig. 3), and one circuit arranged at the bottom, here the dump circuit 37 (see Fig. 3). The absorber region 30 may be an intrinsic or lightly doped absorber epitaxial (Int/ n-). A graded doped n+ epi layer 80 is provided on the top of the absorber region 30. A graded doped n+ epi layer 81 is provided on the bottom of the absorber region 30, such that the graded doped n+ epi layers 80 and 81 are placed on opposite sides of the absorber region 30. A top p+ isolated region 32 (see Fig. 3) is located within the graded doped n+ epi layer 80 on the top of the absorber region 30 and a p+ epi layer 34 (see Fig. 3) is placed on the bottom of the absorber re gion 30. The graded doped n+ epi layer 81 is placed between the p+ epi layer 34 and the absorber region 30. The p+ regions 32 on the top of the pixel array 4 are detector taps, and each one of the p+ regions 32 are connected to a respective read-out circuit 35, such that the p+ regions 32 provide signals for the vertical CAPD pixel array 4 and the read-out circuits 35 read out the signals from the p+ regions 32. The bottom p+ epi layer 34 is a dump tap and is connected to the dump circuit 37, such that the bottom p+ epi layer 34 provides signals regarding dumped carries. A mixer circuit 36 (see Fig. 3) is connected to the graded doped n+ epi layer 80 on top of the pixel array 4 and to the graded doped n+ epi layer 81 at the bottom of the pixel array 4, and is used to apply mix voltage to the pixel array 4, such that a vertical electric field is generated between the graded doped n+ epi lay ers 80 and 81.

In the embodiment of Fig. 8, the plurality of read-out circuits 35 arranged on top of the absorber region 30, and the dump circuit 37 is arranged at the bottom of the absorber region 30, without lim iting the present embodiment in that regard. For example, the read-out circuits 35 and the dump cir cuit 37 may be located anywhere, for example, to the top, to the bottom, or the like. However, the read-out circuits 35 are connected to the p+ isolated regions 32 and the dump circuit 37 is con nected to the bottom of the vertical CAPD (by etching or other techniques).

In the embodiment of Fig. 8, the absorber region 30 may be an intrinsic or lightly doped absorption region, such as a GaAs based material, a Silicon based material, InGaAs, any III-V material, or mate rials such as HgCdTe, Si, or the like. The graded doping described in the embodiment of Fig. 8 can be employed optionally for the absorber and epi layers.

Fig. 9 schematically illustrates an embodiment of a vertical CAPD pixel array, such as the vertical CAPD pixel array 2 described with regard to Fig. 3, wherein the vertical CAPD pixel array has wide band gap materials for the epi layers and wide band gap materials for the isolated regions. A vertical CAPD pixel array 5 comprises a plurality of the vertical CAPD pixels 1 as described with regard to Fig. 2. The vertical CAPD pixel array 5 comprises an absorber region 30 (see Fig. 3). The absorber region 30 has a plurality of read-out circuits 35 (see Fig. 3) arranged on top of the absorber region 30, and one dump circuit 37 (see Fig. 3) arranged at the bottom of the absorber region 30, without limiting the present embodiment in that regard. The dump circuit 37 may be arranged any where, for example, at the top, at the bottom, or the like, since its connection to pixel array 5 is through the junction to the bottom vertical CAPD pixel array 5, i.e. the p+ epi layer. The absorber region 30 may be an intrinsic or lightly doped absorber epitaxial (Int/n-) of an III-V material. A wide band gap (WBG) n+ epi layer 90 is provided, which is made of a wide band gap material, is lo cated on the top of the absorber region 30. A WBG n+ epi layer 91 is provided, which is made of a wide band gap material, is located on the bottom of the absorber region 30, such that the WBG n+ epi layers 90 and 91 are placed on opposite sides of the absorber region 30. The top p+ isolated re gion 93 (see Fig. 9), which is a WBG isolated region, is within the WBG n+ epi layer 90 on the top of the absorber region 30 and a WBG p+ epi layer 92 is placed on the bottom of the absorber re gion 30. The WBG n+ epi layer 91 is placed between the WBG p+ epi layer 92 and the absorber re gion 30. The WBG p+ regions 93 on the top of the pixel array 5 are detector taps and each one of the p+ regions 93 are connected to a respective read-out circuit 35, such that the WBG p+ regions 93 provide signals for the vertical CAPD pixel array 5 and the read-out circuits 35 read out the sig nals from the p+ regions 93. The bottom WBG p+ epi layer 92 is a dump tap and is connected to the dump circuit 37, such that the bottom WBG p+ epi layer 92 provides signals regarding dumped carries. A mixer circuit 36 (see Fig. 3) is connected to the WBG n+ epi layer 90 on top of the pixel array 5 and to the WBG n+ epi layer 91 at the bottom of the pixel array 5, and is used to apply mix voltage to the pixel array 5, such that a vertical electric field is generated between the WBG n+ epi layers 90 and 91.

Quantum-Well vertical CAPD pixel array

Fig. 10 schematically illustrates an embodiment of a quantum well vertical CAPD pixel array form ing a quantum well infrared photodetector. The vertical CAPD pixel array 6 comprises a plurality of vertical CAPD pixels. The vertical CAPD pixel array 6 comprises an absorber region 30 (see Fig. 3) in which a doped Multiple Quantum Well (MQW) stack 100 of, for example, InP/InGaAs is formed, without limiting the present embodiment in that regard. The MQW may be doped MQW or undoped MQW, which is formed by two materials, wherein one is the host, e.g. wider band gap like InP, and the other is the localizer, e.g. smaller bandgap like InGaAs. The absorber region 30 has a plurality of read-out circuits 35 (see Fig. 3) arranged on top of the absorber region 30, and one dump circuit 37 arranged at the bottom of the absorber region 30 (see Fig. 3). The absorber region 30 may for example be an intrinsic or lightly doped absorber epitaxial (Int/low dop/low epi) of an III-V material. A wide band gap (WBG) n+ epi layer 90 is provided as a highly doped epi layer made of a wide band gap material and is located on the top of the absorber region 30. A WBG n+ epi layer 91 is provided as a highly doped epi layer made of a wide band gap material and is located on the bottom of the absorber region 30, such that the WBG n+ epi layers 90 and 91 are placed on op posite sides of the absorber region 30. The top p+ isolated region 32 (see Fig. 3) is within the WBG n+ epi layer 90 on the top of the absorber region 30 and a WBG p+ epi layer 92 is placed on the bottom of the absorber region 30. The WBG n+ epi layer 91 is placed between the WBG p+ epi layer 92 and the absorber region 30. The p+ regions 32 on the top of the pixel array 6 are detector taps and each one of the p+ regions 32 are connected to a respective read-out circuit 35, such that the p+ regions 32 provide signals for the vertical CAPD pixel 6 and the read-out circuits 35 read out the signals from the p+ regions 32. The bottom WBG p+ epi layer 92 is a dump tap and is con nected to the dump circuit 37, such that the bottom WBG p+ epi layer 92 provides signals regarding dumped carries. A mixer, such as the mixer circuit 36 (see Fig. 3), is connected to the WBG n+ epi layer 90 on top of the pixel array 6 and to the WBG n+ epi layer 91 at the bottom of the pixel array 6, and is used to apply mix voltage to the pixel array 6, such that a vertical electric field is generated between the WBG n+ epi layers 90 and 91.

In the embodiment of Fig. 10, the QW is formed using two materials, with different bandgaps, wherein one has smaller bandgap. The material with smaller bandgap is surrounded by the material with higher bandgap which leads to localization of carriers inside the QW For example, InGaAs well surrounded by GaAs forms a GaAs/InGaAs QW, and InGaAs well surrounded by InP forms an InGaAs /InP QW.

In the embodiment of Fig. 10, the pixel array 6 is a backside illumination pixel array having at the bottom a WBG p+ epi layer 92, without a substrate being formed, such that absorption of the pho tons within the substrate is avoided. Alternatively, in a case of backside illumination, the substrate may be a thick substrate of material with larger bandgap to avoid absorption of the photons within the substrate. For example, in Short Wave InfraRed (SWIR) absorber like InGaAs, the substrate may be InP, without limiting the present embodiment in that regard. Still alternatively, in a case where the pixel array 6 is illuminated at a long wavelength, i.e. Long Wave InfraRed (LWIR), a wide gap substrate is not mandatory.

Quantum Well (QW) and Quantum-Dot (QD) infrared photodetectors which have narrow absorp tion spectrum may match SWIR, Medium Wave InfraRed (MWIR) and Long Wave InfraRed (LWIR) bands by engineering the quantum confined states. Such QW and QD infrared photodetec tors be made using III-V semiconductors based on GaAs or InP substrates, or the like.

Quantum-Dot vertical CAPD pixel array Fig. 11 schematically illustrates an embodiment of a quantum dot vertical CAPD pixel array forming a quantum dot infrared photodetector. The vertical CAPD pixel array 7 comprises a plurality of the vertical CAPD pixels. The vertical CAPD pixel array 7 comprises an absorber region 30 (see Fig. 3), in which a Quantum Dot (QD) stack 110 is formed. The absorber region 30 has a plurality of read out circuits 35 (see Fig. 3) arranged on the top of the absorber region 30, and one dump circuit 37 (see Fig. 3) arranged at the bottom of the absorber region 30. The absorber region 30 may be an in trinsic or lighdy doped absorber epitaxial (Int/low dop/low epi) of an III-V material. A WBG n+ epi layer 90 is provided as a highly doped epi layer made of a wide band gap material and is located on the top of the absorber region 30. A WBG n+ epi layer 91 is provided as a highly doped epi layer made of a wide band gap material and is located on the bottom of the absorber region 30, such that the WBG n+ epi layers 90 and 91 are placed on opposite sides of the absorber region 30. The top p+ isolated region 32 (see Fig. 3) is within the WBG n+ epi layer 90 on the top of the absorber re gion 30 and a WBG p+ epi layer 92 is placed on the bottom of the absorber region 30. The WBG n+ epi layer 91 is placed between the WBG p+ epi layer 92 and the absorber region 30. The p+ re gions 32 on the top of the pixel array 7 are detector taps and each one of the p+ regions 32 are con nected to a respective read-out circuit 35, such that the p+ regions 32 provide signals for the vertical CAPD pixel 7 and the read-out circuits 35 read out the signals from the p+ regions 32. The bottom WBG p+ epi layer 92 is a dump tap and is connected to the dump circuit 37, such that the bottom WBG p+ epi layer 92 provides signals regarding dumped carries. A mixer, such as the mixer tap 36 (see Fig. 3), is connected to the WBG n+ epi layer 90 on top of the pixel array 7 and to the WBG n+ epi layer 91 at the bottom of the pixel array 7, and is used to apply mix voltage to the pixel array 7, such that a vertical electric field is generated between the WBG n+ epi layers 90 and 91.

In the embodiment of Fig. 11 , the pixel array 7 is a backside illumination pixel array having at the bottom a WBG p+ epi layer 92, without a substrate being formed, such that absorption of the pho tons within the substrate is avoided. Alternatively, in a case of backside illumination, the substrate may be a thick substrate of material with larger bandgap to avoid absorption of the photons within the substrate. For example, in Short Wave InfraRed (SWIR) InGaAs, the substrate may be InP, without limiting the present embodiment in that regard. Still alternatively, in a case where the pixel array 7 is illuminated at a long wavelength, i.e. Long Wave InfraRed (LWIR), a wide gap substrate is not mandatory.

In the embodiment of Fig. 11, in a case where the QD stack structure 110 within the QD vertical CAPD pixel array 7 is doped with charges, without limiting the present embodiment in that regard. The QD may be doped QD or undoped QD. In a case where the QD is an undoped QD, charges are created by illumination in the QDs and then they can be extracted by applying electric field. In a case where the QD is a doped QD, charges in QDs are excited by absorbing illumination with en- ergy hv that matches with the transition(s) from the QD confined states to the continuum. In other words, a current is created with illumination energy hv, and the charges are highly localized, and can be excited by absorbing illumination with enough energy higher than their excitation energy from localized quantum bands. QD infrared photodetectors which have narrow absorption spectrum may match SWIR, MWIR and LWIR bands by engineering the quantum confined states, and since longer wavelength range can be used, robustness with respect to scattering in ToF sensors may be im proved.

Two-tap vertical CAPD pixel array

Fig. 12 schematically illustrates an embodiment of a stacking process of two half vertical CAPD pixel array implementation using liftoff and stacking techniques.

In the embodiment of Fig. 12, a stacking process of two half vertical CAPD pixel array structures 8a and 8b is illustrated, wherein in the upper part of Fig. 12, a half vertical CAPD pixel array structure 8a and in the lower part of Fig. 12, a half vertical CAPD pixel array structure 8b is illustrated. Each one of the two half vertical CAPD pixel array structures 8a and 8b comprises an absorber region, such as the absorber region 120, with a plurality of read-out circuits at the top of the absorber region 120, such as the read-out circuits 133 (see Fig. 13). The absorber region 120 is an intrinsic or lightly doped absorber epitaxial (Int/ n-). An n+ epi layer 31 is on the top of the absorber region 120. A top p+ isolated region 32 is within the n+ epi layer 31 on the top of the absorber region 120.

Each one of the two half vertical CAPD pixel array structures 8a and 8b may be formed on a sub strate which is removed using liftoff techniques, such that the two half vertical CAPD pixel array structures 8a and 8b to be stacked together as to form a two-tap vertical CAPD pixel array (see 9 in Fig. 13).

In the embodiment of Fig. 12, liftoff and stacking techniques are used for realizing the two tap verti cal CAPD pixel array (see 9 in Fig. 13), without limiting the present embodiment in that regard. Al ternatively, any other techniques known to the skilled person may be used to form the two-tap vertical CAPD pixel array.

Fig. 13 schematically illustrates an embodiment of a two-tap vertical CAPD pixel array, which is im plemented using the stacking process of Fig. 12. The two-tap vertical CAPD pixel array 9 comprises a plurality of vertical CAPD pixels. The two-tap vertical CAPD pixel array 9 comprises an absorber region 130, with a plurality of read-out circuits 133 (“RO A” and “RO B”) at the top and at the bot tom of the absorber region 130. The absorber region 130 is an intrinsic or lightly doped absorber epitaxial (Int/n-). A first n+ epi layer 131 (see 31 in Fig. 12) is provided on the top of the absorber region 130, and a second n+ epi layer 131 is provided at the bottom of the absorber region 130 such that the n+ epi layers 131 are placed on opposite sides of the absorber region 130. A plurality of p+ isolated regions 132 (see 32 in Fig. 12) are arranged within the n+ epi layers 131 on the top and at the bottom of the absorber region 130. The plurality of the p+ regions 132 on the top of the pixel array 9 are detector taps and each one of the p+ regions 132 are connected to a respective read-out circuit 133, such that the p+ regions 132 provide signals for the vertical CAPD pixel 9 and the read out circuits 133 read out the signals from the p+ regions 132. A mixer circuit 134 is connected to the n+ epi layers 131 on top and at the bottom of the pixel array 9, and is used to apply mix voltage to the pixel array 9, such that a vertical electric field is generated between the n+ epi layers 131.

In the embodiment of Fig. 13, detector taps 133 (Tap A and Tap B) are used in both sides, such that the dump tap, described in Figs. 2 to 11, is isolated and implemented like a detector tap. These de tector taps 133 may be connected to a readout circuit.

Note that the present technology can also be configured as described below.

(1) A pixel unit (1) comprising an absorber region (20; 30; 70; 130) configured to capture light, and two taps (22, 24; 32, 34; 92) arranged on different sides of the absorber region (20; 30; 70; 130) and configured to collect photogenerated carriers generated in the absorber region (20; 30; 70; 130).

(2) The pixel unit (1) of (1), wherein the different sides of the absorber region (20; 30; 70; 130) include a first side and a second side which are opposite sides.

(3) The pixel unit (1) of anyone of (1) or (2), wherein the two taps include a tap on a top of the absorber region (20; 30; 70; 130), and a tap at a bottom of the absorber region (20; 30; 70; 130), the bottom of the absorber region (20; 30; 70; 130) being a light incident side.

(4) The pixel unit (1) of anyone of (1) to (3), wherein the tap on the top of the absorber region (20; 30; 70; 130) is a detector tap (22; 32; 42; 72; 132) configured to collect photogenerated holes.

(5) The pixel unit (1) of anyone of (1) to (4), wherein the tap at the bottom of the absorber re gion (20; 30; 70; 130) is a dump tap (24; 34; 44; 74).

(6) The pixel unit (1) of anyone of (1) to (5) further comprising an n+ epitaxial layer (21; 31; 80; 90; 131) on the top of the absorber region (20; 30; 130) and an n+ epitaxial layer (23; 33; 81; 91; 131) at the bottom of the absorber region (20; 30; 130), wherein the n+ epitaxial layers are configured to collect photogenerated electrons.

(7) The pixel unit (1) of (6), further comprising a p+ epitaxial layer (24; 34; 92) at the bottom of the absorber region (20; 30; 70; 130), wherein the n+ epitaxial layer (23; 33; 81; 91; 131) is located between the absorber region (20; 30; 70; 130) and the p+ epitaxial layer (24; 34; 92) at the bottom of the absorber region (20; 30; 70; 130).

(8) The pixel unit (1) of (6), further comprising a p+ isolated region (22; 32; 93; 132) within an n+ epitaxial layer (21; 31; 80; 90; 131) on the top of the absorber region (20; 30; 70; 130), the p+ iso lated region (22; 32; 93; 132) being configured to collect photogenerated holes.

(9) The pixel unit (1) of (6), further comprising a mixer circuit (26; 36; 134) connected to the n+ epitaxial layer (21; 31; 80; 90; 131) on top of the absorber region (20; 30; 70; 130) and to the n+ epi taxial layer (23; 33; 81; 91; 131) at the bottom of the absorber region (20; 30; 70; 130).

(10) The pixel unit (1) of (9), wherein the n+ epitaxial layer (21; 31; 80; 90; 131) on top of the ab sorber region (20; 30; 70; 130) and the n+ epitaxial layer (23; 33; 81; 91; 131) at the bottom of the absorber region (20; 30; 70; 130) generate a modulated vertical electric field (39) within the absorber region (20; 30; 70; 130).

(11) The pixel unit (1) of (10), wherein the mixer circuit (26; 36; 134) connects the pixel unit to a modulation circuitry configured to demodulate a generated modulation signal.

(12) The pixel unit (1) of (6), wherein the n+ epitaxial layer (80, 81) on the top and on the bottom of the absorber region (30) is a graded doped n+ epitaxial layer.

(13) The pixel unit (1) of (6), wherein the n+ epitaxial layer (90, 91) on the top and on the bottom of the absorber region (30) is a wide band gap epitaxial layer.

(14) The pixel unit (1) of (8), wherein the p+ isolated region (22; 32; 93; 132) is implemented as a detector tap (25; 35; 133).

(15) The pixel unit (1) of (7), wherein the p+ epitaxial layer (24; 34; 92) is implemented as a dump tap (27; 37).

(16) The pixel unit (1) of (15), wherein the p+ epitaxial layer (92) is a wide band gap epitaxial layer.

(17) The pixel unit (1) of anyone of (1) to (16), further comprising an n+ isolated region (72) within an p+ epitaxial layer (71) on the top of the absorber region (70), and a p+ epitaxial layer (73) and n+ epitaxial layer (74) at the bottom of the absorber region (70).

(18) The pixel unit (1) of (17), wherein the p+ epitaxial layer (73) is located between the absorber region (70) and the n+ epitaxial layer (74).

(19) The pixel unit (1) of anyone of (1) to (18), wherein the pixel unit (1) is a vertical CAPD pixel unit. (20) The pixel unit (1) of anyone of (1) to (19), wherein a quantum-dot stack (110) is formed within the absorber region (30).

(21) The pixel unit (1) of anyone of (1) to (20), wherein a quantum-well stack (100) is formed within the absorber region (30). (22) The pixel unit (1) of (3), wherein the two taps on the top and at the bottom of the absorber region (130) are a detector tap (133).

(23) A pixel array (2; 3; 4; 5; 6; 7; 9) comprising multiple pixel units (1) in accordance with claim

1.

(24) A Time-of-Flight imaging sensor comprising a pixel array (2; 3; 4; 5; 6; 7; 9) in accordance with claim 23.

(25) An electronic device comprising a Time-of-Flight imaging sensor in accordance with claim 24, wherein the electronic device is a Time-of-Flight camera.

Claims

1. A pixel unit comprising an absorber region configured to capture light, and two taps ar ranged on different sides of the absorber region and configured to collect photogener ated carriers generated in the absorber region.

2. The pixel unit of claim 1, wherein the different sides of the absorber region include a first side and a second side which are opposite sides.

3. The pixel unit of claim 1, wherein the two taps include a tap on a top of the absorber re gion, and a tap at a bottom of the absorber region, the bottom of the absorber region being a light incident side.

4. The pixel unit of claim 1, wherein the tap on the top of the absorber region is a detector tap configured to collect photogenerated holes.

5. The pixel unit of claim 1, wherein the tap at the bottom of the absorber region is a dump tap.

6. The pixel unit of claim 1 further comprising an n+ epitaxial layer on the top of the ab sorber region and an n+ epitaxial layer at the bottom of the absorber region, wherein the n+ epitaxial layers are configured to collect photogenerated electrons.

7. The pixel unit of claim 6 further comprising a p+ epitaxial layer at the bottom of the ab sorber region, wherein the n+ epitaxial layer is located between the absorber region and the p+ epitaxial layer at the bottom of the absorber region.

8. The pixel unit of claim 6, further comprising a p+ isolated region within an n+ epitaxial layer on the top of the absorber region, the p+ isolated region being configured to col lect photogenerated holes.

9. The pixel unit of claim 6 further comprising a mixer circuit connected to the n+ epitaxial layer on top of the absorber region and to the n+ epitaxial layer at the bottom of the ab sorber region.

10. The pixel unit of claim 9, wherein the n+ epitaxial layer on top of the absorber region and the n+ epitaxial layer at the bottom of the absorber region generate a modulated ver tical electric field within the absorber region.

11. The pixel unit of claim 10, wherein the mixer circuit connects the pixel unit to a modula tion circuitry configured to demodulate a generated modulation signal.

12. The pixel unit of claim 6, wherein the n+ epitaxial layer on the top and on the bottom of the absorber region is a graded doped n+ epitaxial layer.

13. The pixel unit of claim 6, wherein the n+ epitaxial layer on the top and on the bottom of the absorber region is a wide band gap epitaxial layer.

14. The pixel unit of claim 8, wherein the p+ isolated region is implemented as a detector tap.

15. The pixel unit of claim 7, wherein the p+ epitaxial layer is implemented as a dump tap.

16. The pixel unit of claim 15, wherein the p+ epitaxial layer is a wide band gap epitaxial layer.

17. The pixel unit of claim 1, further comprising an n+ isolated region within an p+ epitaxial layer on the top of the absorber region, and a p+ epitaxial layer and n+ epitaxial layer at the bottom of the absorber region.

18. The pixel unit of claim 17, wherein the p+ epitaxial layer is located between the absorber region and the n+ epitaxial layer.

19. The pixel unit of claim 1, wherein the pixel unit is a vertical CAPD pixel unit.

20. The pixel unit of claim 1, wherein a quantum-dot stack is formed within the absorber re- gion.

21. The pixel unit of claim 1, wherein a quantum-well stack is formed within the absorber region.

22. The pixel unit of claim 3, wherein the two taps on the top and at the bottom of the ab sorber region are a detector tap.

23. A pixel array comprising multiple pixel units in accordance with claim 1.

24. A Time-of-Flight imaging sensor comprising a pixel array in accordance with claim 23.

25. An electronic device comprising a Time-of-Flight imaging sensor in accordance with claim 24, wherein the electronic device is a Time-of-Flight camera.