WO2022188306A1 - Procédé et dispositif d'attribution de tâches - Google Patents

Procédé et dispositif d'attribution de tâches Download PDF

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Publication number
WO2022188306A1
WO2022188306A1 PCT/CN2021/103160 CN2021103160W WO2022188306A1 WO 2022188306 A1 WO2022188306 A1 WO 2022188306A1 CN 2021103160 W CN2021103160 W CN 2021103160W WO 2022188306 A1 WO2022188306 A1 WO 2022188306A1
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core
information
task
processor
cores
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PCT/CN2021/103160
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English (en)
Chinese (zh)
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尹文
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华为技术有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals

Definitions

  • the present application relates to the field of computer technology, and in particular, to a task assignment method and device.
  • the task allocation method of the current multi-core processor will ensure that each core of the processor works at a higher frequency as much as possible to ensure processing performance.
  • a higher voltage is required to support the cores of the processor operating at that frequency. High voltage will accelerate the aging of transistor circuits in the processor core, reducing the life of the processor core. If the core has been working at the highest frequency, the lifespan will drop off a cliff, shortening to months or even days. A core with exhausted or insufficient lifespan will operate at a significantly reduced frequency.
  • Embodiments of the present application provide a task allocation method and apparatus, so as to improve the service life of a processor core.
  • an embodiment of the present application provides a task allocation method, which can be applied to a computer system with multiple processor cores to improve the service life of the cores in the computer system.
  • the method can be implemented by task allocation, and the task allocation device can be a computer system, and the computer system can be a computer system with multiple processor cores to which the method is applied, or other computer systems.
  • the method includes: the task allocation apparatus may obtain first information of multiple cores of the processor, where the first information is used to describe the service life of the cores.
  • the task allocation apparatus may further determine, according to the respective first information of the multiple cores, a first core for processing the first task from the multiple cores, where the first task is a task to be processed.
  • the task allocation apparatus may determine the first core according to the respective first information of the multiple cores and the task amount information of the first task.
  • the task allocation device may also allocate cores according to the number of cores in the physical core group. determine the first physical core group corresponding to the first task, and according to the first information of the cores in the first physical core group, determine from the cores of the first physical core group that each thread in the first task corresponds to the nucleus.
  • the task allocation apparatus may further store updated first information of the first core, where the updated first information is determined according to the first information of the first core and the task amount information of the first task.
  • the lifespan information of the first core can be updated according to the task amount information of the first task, so the lifespan information of the core can be obtained more accurately, and the lifespan balancing effect of subsequent task assignment can be improved.
  • the first information of the kth core of the processor includes the remaining lifetime information of the kth core; and/or the first information includes the used lifetime information of the kth core.
  • the remaining lifetime information of the kth core may be determined according to the total lifetime information and the used lifetime information of the kth core.
  • the lifetime information of the kth core may be based on the historical operation time of the kth core, the frequency and historical operation time of the kth core, the voltage and historical operation time of the kth core, the kth core
  • the position of the core on the processor, the total memory access time of the kth core, the historical instruction number of the kth core and the average running time of the instructions, or the frequency of the kth core and the total memory access time are determined by at least one information. .
  • an embodiment of the present application provides a task allocation method, which can be applied to a computer system with multiple processors, so as to improve the service life of cores in the computer system.
  • the method can be implemented by task allocation, and the task allocation device can be a computer system, and the computer system can be a computer system with multiple processor cores to which the method is applied, or other computer systems.
  • the method includes: the task distribution device may acquire third information of the multiple processors, where the third information is used to describe the service life of the processors.
  • the task allocating apparatus may further determine, according to the respective first information of the multiple processors, a first processor for processing the second task from the multiple processors, and the second task is a to-be-processed task.
  • the task allocation device may determine the first processor according to the respective third information of the multiple processors and the task amount information of the second task, so as to further improve the rationality of task allocation sex.
  • an embodiment of the present application provides a task assignment apparatus, which can be applied to a computer system having multiple processor cores, and the task assignment apparatus can specifically implement the behavior of the task assignment method in the first aspect or the second aspect.
  • the task assignment device may be a hardware or software unit in a computer system, and may include at least one module, and the at least one module is used to implement the task assignment method described in the first aspect or the second aspect and any possible designs thereof. .
  • an embodiment of the present application provides a task allocation apparatus, including at least one processor, the at least one processor is coupled with at least one memory: the at least one processor is configured to execute the at least one memory A computer program or instructions stored to cause the apparatus to perform the method of the first aspect or the second aspect and any possible designs thereof.
  • the apparatus further includes a communication interface to which the processor is coupled.
  • the communication interface may be a transceiver or an input/output interface; when the device is a chip included in a network device, the communication interface may be an input/output interface of the chip.
  • the transceiver may be a transceiver circuit, and the input/output interface may be an input/output circuit.
  • an embodiment of the present application provides a computing device, including a processor and a memory, where the processor includes multiple processor cores; the memory is used for storing computer programs or instructions; the processor is used for The computer program or instructions are executed to implement the task assignment method described in the first aspect or the second aspect and any possible designs thereof.
  • an embodiment of the present application provides a computer system
  • the computer system may include a recording module, a task allocation module, and multiple processor cores
  • the task allocation module may be configured to
  • the respective first information implements the method described in the first aspect and any possible designs thereof.
  • the recording module may include an editable memory for storing the respective first information of the plurality of processor cores, or for reading the respective first information of the multiple processor cores from the editable memory.
  • an embodiment of the present application provides a computer system
  • the computer system may include a recording module, a task allocation module, and multiple processors
  • the task allocation module may be configured to
  • the first information implements the method described in the second aspect and any possible designs thereof.
  • the recording module may include an editable memory for storing the respective third information of the plurality of processors, or for reading the respective third information of the plurality of processors from the editable memory.
  • an embodiment of the present application provides a readable storage medium for storing an instruction, when the instruction is executed, the method described in the first aspect or the second aspect and any possible designs thereof is enabled is realized.
  • the embodiments of the present application provide a computer program product containing instructions, which, when run on a computer, cause the computer to execute the method described in the first aspect or the second aspect and any possible designs thereof.
  • an embodiment of the present application provides a chip system, including: a processor, the processor is coupled to a memory, the memory is used to store programs or instructions, the chip system may further include an interface circuit, the interface circuit It is used to receive programs or instructions and transmit them to a processor; when the programs or instructions are executed by the processor, the system-on-a-chip enables the method in the first aspect or the second aspect and any possible designs thereof.
  • the number of processors in the chip system may be one or more.
  • the processor can be implemented by hardware or by software.
  • the processor may be a logic circuit, an integrated circuit, or the like.
  • the processor may be a general-purpose processor implemented by reading software codes stored in memory.
  • the memory may be integrated with the processor, or may be provided separately from the processor, which is not limited in this application.
  • the memory may be a non-transitory processor, such as a read-only memory (ROM), which may be integrated with the processor on the same chip, or may be separately provided on different chips.
  • ROM read-only memory
  • the type of memory and the manner in which the memory and the processor are arranged are not particularly limited.
  • the present application may further combine to provide more implementations.
  • Fig. 1 is the schematic diagram of EAS technology under Linux operating system
  • FIG. 2 is a schematic flowchart of a task allocation method provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a thread allocation process according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of the location of a core on a CPU according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of the location of another core on a CPU provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of an implementation manner of a task allocation method provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of an implementation manner of another task allocation method provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of the architecture of a CPU and GPU heterogeneous system according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of an implementation manner of another task allocation method provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a task assignment apparatus provided by an embodiment of the application.
  • FIG. 11 is a schematic structural diagram of another task allocation apparatus provided by an embodiment of the present application.
  • the embodiments of the present application provide a task allocation method and apparatus, which help to improve the service life of cores in a multi-core processor.
  • the method and the device are based on the same technical concept. Since the principles of the method and the device to solve the problem are similar, the implementation of the device and the method can be referred to each other, and the repetition will not be repeated.
  • a computer system consists of hardware (sub)systems and software (sub)systems.
  • the hardware (sub) system includes the organic combination of various physical components (such as processors, etc.) composed of electrical, magnetic, optical, mechanical and other principles, and is the entity on which the system works;
  • the software (sub) system includes various Procedures and documents for directing the entire system to work according to specified requirements.
  • modern computer systems are as small as microcomputers and personal computers, as large as supercomputers and their networks, with various shapes and characteristics, and have been widely used in scientific computing, transaction processing and process control. field and have a profound impact on the progress of society.
  • the computer system in the embodiment of the present application may be a computer system in a terminal device, which is a device that provides business services to users and has functions such as voice or data connectivity.
  • the terminal device may also be referred to as a terminal device, and may also be referred to as user equipment (UE), a mobile station (mobile station, MS), a mobile terminal (mobile terminal, MT), etc.
  • UE user equipment
  • MS mobile station
  • MT mobile terminal
  • the terminal device may also be a chip.
  • a terminal device is taken as an example for specific description.
  • the terminal device may be a handheld device with a wireless connection function, a vehicle-mounted device, or the like.
  • some examples of terminal devices are: mobile phone (mobile phone), tablet computer, notebook computer, PDA, mobile internet device (MID), smart point of sale (POS), wearable device, Virtual reality (VR) equipment, augmented reality (AR) equipment, wireless terminals in industrial control, wireless terminals in self driving, remote medical surgery wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, Class smart meters (smart water meter, smart electricity meter, smart gas meter), etc.
  • the computer system in this embodiment of the present application may be a server, which is a device that provides a data connection service. Since the server can respond to the service request of the terminal device and process it, generally speaking, the server should have the ability to undertake and guarantee the service.
  • the server may be a server located in a data network (DN), such as a common server, a server in a cloud platform; or a multi-access edge computing (multi-access edge) located in the core network computing, MEC) server, etc.
  • DN data network
  • MEC multi-access edge computing
  • the computer system in this embodiment of the present application may also be a processor, a chip, or a chip system.
  • OS Operating system
  • OS is the most basic system software running on a computer system, such as windows system, Android system, IOS system, windows server system, Netware system, Unix system, Linux system.
  • the kernel is the first layer of software expansion based on hardware, providing the most basic functions of the operating system. For example, the processes, memory, drivers, files, and network systems responsible for managing the system determine the performance and stability of the system.
  • the core of the processor, or the core is the core chip in the processor.
  • the number of cores of a processor refers to how many cores a processor consists of. The more cores, the faster the processor runs and the better the performance. If the number of cores of a processor is greater than or equal to 2, the processor can be called a multi-core processor.
  • Homogeneous processors or homogeneous multi-core processors.
  • the structure of each processor core of a homogeneous multi-core processor is exactly the same, and the status is also the same.
  • different cores can share the same code, or different cores can execute different codes respectively.
  • a CPU isomorphic processor as an example, a plurality of cores in the processor are all CPU cores, or the computing modules included in the processor are all called CPU computing modules.
  • Heterogeneous processors or heterogeneous multi-core processors.
  • Different cores of a heterogeneous multi-core processor may employ cores with different functions.
  • Heterogeneous multi-core processors are often used for special applications, such as signal processing.
  • some cores are generally used for management and scheduling, and other cores are used for specific performance acceleration.
  • the processor cores are interconnected through shared buses, crossbar switches, and on-chip networks.
  • the processor may include at least one CPU core and at least one xPU (such as GPU or NPU, etc.) core, or the computing module included in the processor includes at least a CPU computing module and a xPU (such as GPU or NPU, etc.) computing module, in which the CPU core can be used for management and scheduling.
  • the CPU core can be used for management and scheduling.
  • Process and thread (tread).
  • a process is the smallest unit of resource allocation, and a thread or logical thread is the smallest unit of program execution.
  • a thread can include one or more instructions, so the processing running time of each thread may be different. That is, resources are allocated to a process, and all threads within the same process share all resources of that process. Among them, a thread can only belong to one process, and a process can have multiple threads, but at least one thread.
  • a thread is a single sequential flow of control in a process.
  • a process can have multiple threads concurrently, and each thread can execute different tasks in parallel. For multi-core processors, different cores can be used to execute different threads, thus enabling parallelization of tasks.
  • a thread can be understood as the smallest pipeline unit in a processor performing specific data processing. It should be understood that a core may correspond to one or more pipelines in order to achieve multitasking parallel processing.
  • task refers to an activity completed by the software.
  • An application may contain one or more tasks.
  • a task can be either a process or a thread, or can include multiple processes and/or multiple threads.
  • task allocation refers to allocating processes and/or threads included in a task
  • thread allocation refers to allocating threads to processor pipelines so that threads are processed through pipelines.
  • a task could be to read data and put it in memory.
  • This task can be implemented as a process or as a thread (or as an interrupt task).
  • the following takes thread allocation as an example to illustrate the way of task allocation in the current multi-core processor.
  • the prior art mainly realizes thread allocation through a software scheduling method at the operating system (operation system, OS) layer.
  • OS operating system
  • the complete fair schedule (CFS) invoker and load balancing of the Linux kernel are mainly for the priority of server performance, so multiple threads are evenly distributed to the system
  • CFS complete fair schedule
  • the Linux kernel 5.3 adopts the energy-aware scheduler (EAS) technology, which can make full use of the differences in core power consumption, performance and frequency to achieve the optimal balance between performance and power consumption.
  • EAS energy-aware scheduler
  • the Linux scheduler in EAS can execute CFS
  • the Linux CPU idle mechanism represented as the idle mechanism in Figure 1
  • the Linux CPU frequency conversion mechanism determines when to increase or decrease the CPU frequency
  • the energy model can be used to balance the energy consumption between the Linux scheduler, the Linux CPU idle mechanism, and the Linux CPU frequency conversion mechanism.
  • Embodiments of the present application provide a task allocation method and apparatus, which can allocate a task to be processed to a first core of a processor according to life information of multiple cores of a processor, and the first core processes the task. Since tasks are allocated according to the lifetime information of the cores, the lifetimes of multiple cores of the processor can be balanced, so that each core can work at a higher frequency.
  • the task assignment method can be performed by a task assignment apparatus, and the task assignment apparatus may be a computer system.
  • the apparatus can be implemented by a combination of software and hardware or by hardware.
  • the task allocation method may be implemented by the operating system executing software, or by the chip executing software solidified in the chip or the like.
  • the task allocation can be implemented by firmware (BIOS) and/or a task allocation layer (such as a scheduler) of an operating system, or can be implemented by a processor (or processor chip) such as a CPU, which is not specifically described in this application. limited.
  • the task allocation method provided in this application can be applied to a homogeneous processor or a heterogeneous processor.
  • the homogeneous processors are, for example, CPU homogeneous processors
  • the heterogeneous processors are, for example, heterogeneous processors of CPU and xPU.
  • the method may include the following steps:
  • the task distribution apparatus acquires respective lifetime information of multiple cores of the processor, where the lifetime information can be used to describe the lifetime of the cores. It should be understood that the lifetime information may be referred to as the first information in the textual description and drawings of the present application.
  • life information or service life information may be used to determine the remaining lifetime and/or the used lifetime of the core, that is, the lifetime information may include remaining lifetime information and/or used lifetime information.
  • the total lifetime information can be used to describe the maximum working time that the core can support.
  • the used life information can be related to information such as the running time of the nuclear historical task or the workload of the historical task, etc., and can be used to describe the time length of the core that has been consumed.
  • the remaining life information can be determined according to the total life information and the used life information, and describes the remaining available time of the core. It should be understood that, unless otherwise specified in this application, the lifetime information may be any one or more items of remaining lifetime information or used lifetime information.
  • the lifetime information may be time information used to indicate the service life, or, for the convenience of calculation, the lifetime information may be a value quantified by normalization and other methods according to the time information.
  • the life information can be 5 years, Can also be 100.
  • the duration corresponding to the total lifetime information of different cores may be different, generally around 5 years (or other time information), there may be a deviation of about 5%, and it can be considered that the total lifetime of the core
  • the size of the information is a Gaussian distribution, and the normalized value may fluctuate around 100.
  • the remaining service life and/or the used service life of the core can also be normalized to a numerical value to obtain the remaining service life information and/or the used service life information, respectively.
  • the task allocation apparatus determines, according to the respective lifetime information of the multiple cores, a first core for processing the first task from the multiple cores, where the first core is one of the multiple cores of the processor.
  • the lifespan information includes remaining lifespan information
  • the task distribution device may select the core with the largest remaining lifespan information as the first core, and/or the lifespan information includes used lifespan information, and the task distribution device may select the core with the smallest used lifespan information as the first core.
  • first nucleus the first core may be selected from the cores whose remaining life information is greater than or equal to the first threshold and/or whose used life information is less than or equal to the second threshold, and the selection method at this time may include random selection.
  • the cores may be sorted according to the lifetime information of each core, for example, the weight of each core is determined according to the lifetime information, and the assignment is performed according to the weight of each core during task allocation.
  • the weight of the core may indicate the possibility of the core being selected as the first core, and the higher the weight is, the more likely the corresponding core is to be determined as the first core.
  • the weights of the cores may be positively correlated with the remaining lifetime information of the cores, and/or negatively correlated with the used lifetime information of the cores.
  • the tasks to be processed can be allocated to the first core of the processor according to the life information of multiple cores of the processor, so that the service life of each core can be balanced, so as to prolong the life of the processor core as much as possible. lifetime, allowing the core to operate at higher frequencies for longer periods of time.
  • the process of determining the first core in S102 is a process of task allocation, which can be regarded as a process of determining the mapping relationship between the threads included in the task and the first core.
  • the task allocation device may, according to the respective second information of the physical core clusters, select from the plurality of physical core clusters.
  • a first physical core group corresponding to the first task is determined in the group, and the cores of the first physical core group include the first core. It should be understood that caches may be shared among the cores of a physical core group.
  • the second information may be lifetime information of the physical core group, for example, the second information includes remaining lifetime information and/or used lifetime information of the physical core group, and the second information may also be the average lifetime information of the cores in the physical core group and / or the lifetime information of the core with the least remaining lifetime in the physical core group, etc.
  • the remaining lifetime information of the physical core group may be the sum of the remaining lifetime information of the cores included in the physical core group, or may be other parameters or indicators used to measure the remaining lifetime of the physical core group.
  • the used life information of the physical core set may be the sum of the used life information of the cores included in the physical core set, or may be other parameters or indicators used to measure the used life of the physical core set.
  • the average lifetime information of the cores in the physical core group may be determined according to the remaining lifetime information or the used lifetime information of each core in the physical core group, and the lifetime information of the core with the least remaining lifetime information in the physical core group may be the core with the least remaining lifetime information. life remaining information and/or used life information.
  • the core corresponding to each thread of the first task may be determined according to the lifetime information of the cores in the first physical core group. It should be understood that when determining the physical core group corresponding to the task according to the second information, for example, the physical core group with larger remaining life information, smaller used life information, or larger life information of the core with the least remaining life in the group may be used as the first physical core group.
  • a physical nucleus group to further equalize the lifetime information of the nucleus, thereby further improving the lifetime of the nucleus.
  • task 1 and task N respectively include three threads, which are denoted as thread 1 to thread 3.
  • the task allocating apparatus may determine the mapping relationship between the task and the physical core group of the CPU.
  • a physical core group may include one or more cores, and FIG. 3 is illustrated by taking the number of cores in each physical core group as 3 as an example.
  • the task assignment device may determine that task 1 corresponds to physical core group 1, and therefore assign thread 1 to thread 3 of task 1 to cores in physical core group 1 (the assignment relationship is shown in FIG. 3 by not cutting
  • the task allocation device may determine that task N corresponds to physical core group N, and allocate thread 1 to thread 3 of task N to cores in physical core group N.
  • the first physical core group includes at least one second core.
  • the task allocation apparatus may select a physical core group corresponding to the task from a physical core group including at least one second core according to the second information of the physical core group.
  • the second core may be a core whose remaining life information is greater than or equal to the third threshold and/or whose used life information is less than or equal to the fourth threshold, for example, the remaining life information of the cores in a certain physical core group is less than the third threshold
  • a threshold such as 5, indicates that all cores in the physical core group are about to run out of life, and tasks can be assigned to cores in other physical core groups.
  • the second core in physical core group 1 may include core 2 and core 3
  • the second core in physical core group N may include core 2 and core 3 .
  • the task allocation device may select the physical core group corresponding to the task according to the weight of the physical core group.
  • the weight of the physical core group is positively correlated with the remaining lifetime information of the core (or the second core) in the physical core group, and/or, is formed with the used lifetime information of the core (or the second core) in the physical core group Anticorrelation.
  • the physical core group with the largest remaining life information of the core may be used as the physical core group corresponding to the task, or the core (or the second core) ), the physical core group with the smallest used life information is used as the physical core group corresponding to the task, or, a physical core group whose remaining life information of the core (or the second core) is greater than or equal to the fifth threshold is used as the corresponding physical core group for the first task A physical core group, or a physical core group whose used life information of the core (or the second core) is less than or equal to the sixth threshold is used as the physical core group corresponding to the task.
  • the task assignment device may assign the threads included in the task to the cores in the physical core group corresponding to the task according to the lifetime information of the cores in the physical core group, so as to form a mapping relationship between the cores and the threads.
  • the total number of threads to be allocated included in task 1 and task N may be the same as the total number of cores included in physical core group 1 and physical core group N participating in the allocation.
  • the allocation apparatus when the task allocation apparatus allocates threads to cores in a physical core group, the allocation may be performed according to the weight of the cores.
  • the remaining life information of core 1 in physical core group 1 is 1
  • the remaining life information of core 2 and core 3 is 10
  • the remaining life information of core 3 is 15, the weight of core 3 in physical core group 1 is higher than that of core 2 and the weight of core 2 is higher than that of core 1.
  • the thread can be assigned to the core first. 3.
  • the second priority is allocated to core 2, and not allocated to core 1 as much as possible. For example, as shown in FIG. 3 , thread 2 and thread 3 can be assigned to core 3, and thread 1 can be assigned to core 2, that is, core 1 does not need to assign the thread of task 1.
  • the lifetime information of the kth core may be based on the historical running time of the kth core, the frequency and historical running time of the kth core, the kth core voltage and historical running time, the position of the kth core on the processor, the total memory access time of the kth core, the historical number of instructions and the average running time of the instructions of the kth core, or the frequency of the kth core ( or voltage or the position of the core on the processor) and at least one of the total memory access time.
  • 1 ⁇ k ⁇ K, k and K are both positive integers.
  • the specific instructions are as follows:
  • the historical running time of the core may indicate the historical working time of the core, for example, it may be the total working time of the core since it was first run. It should be understood that the greater the historical run time of the core, the greater the used life information and/or the less the remaining life information of the core.
  • the running duration may refer to the clock cycles consumed by the core executing the instruction.
  • a counter can be started to count the clock cycles consumed by the core executing the instruction. The length of the period determines the historical run time.
  • the historical instruction number of the kth core and the average running time of the instructions can be used to determine the historical running time of the kth core. Therefore, the kth core can be determined according to the historical instruction number and the average running time of the kth core. Lifetime information.
  • the number of historical instructions refers to the total number of instructions included in all historical tasks that have been processed by the core.
  • the number of historical instructions of the kth core may be the total number of instructions included in all historical tasks executed by the kth core before the first task is allocated.
  • the average running time of an instruction refers to the average running time of executing one instruction, which can be determined according to the running time of multiple instructions and the number of instructions of multiple instructions.
  • the frequency of the kth core may be the average power of the core during a period of time (eg, historical running time) or in the process of completing a certain task (eg, all historical tasks). It can be understood that in the case of the same historical running time, the greater the frequency of the core, the greater the loss of the core, that is, the smaller the used life information and/or the greater the remaining life information, therefore, the frequency of the core can be passed. and historical runtime to determine the lifetime information of the core.
  • the voltage of the kth core may be the average voltage of the core during a period of time (eg, historical running time) or during the completion of a certain task (eg, all historical tasks). It can be understood that under the same historical operating time, the greater the voltage of the core, the greater the loss of the core, that is, the smaller the used life information and/or the greater the remaining life information. Therefore, the voltage that can pass through the core is larger. and historical runtime to determine the lifetime information of the core.
  • the location of the core on the processor may also affect the lifetime information of the core, where the location refers to the physical location of the core on the chip, and/or the relative location between the cores.
  • the thermal density is different, and the thermal density is related to the position of the core on the processor.
  • the thermal density is higher the closer to the center of the chip, or the highest thermal density is closer to the center of the area where the physical core group is dense, and the higher the thermal density under the same frequency and/or historical operating time
  • the junction temperature refers to the temperature of the semiconductor transistor. Under the same operating time, the life of the core decreases faster at a higher junction temperature.
  • Tj1, Tj2 and Tj3 represent the junction temperatures of position 1, position 2 and position 3 shown in Figure 4, respectively, where Tj1, Tj2 and Tj3 are respectively away from the center of the chip
  • the distance of the positions increases sequentially, that is to say, the distance between Tj1 and the center of the chip is less than the distance between Tj2 and the center of the core array, and the distance between Tj2 and the center of the chip is less than the distance between Tj3 and the center of the chip, then Tj1 , Tj2 and Tj3 satisfy the following relationship: Tj1>Tj2>Tj3.
  • Tj, Tj2 and Tj3 respectively represent the junction temperature of position 1, position 2 and position 3 shown in Figure 5, wherein Tj1, Tj2 and Tj3
  • the remaining life information and/or the used life information of the core may be determined according to the junction temperature of the core. For example, in the case of the same historical operating time, the greater the junction temperature, the greater the used life information, and/or, The remaining life information is smaller.
  • the chip space can be divided into multiple areas by the chip temperature, and a limited number of temperature sensors can be placed in different areas.
  • different temperature sensors obtain The junction temperature of the junction temperature can be fed back to the task distribution device in real time, which can be used to determine the junction temperature of the area where each junction temperature detector is located.
  • the memory access time of the core is the memory access time of the core, which can also be called the access time. It refers to the time elapsed from the start of a memory operation to the completion of the operation by the core.
  • Memory operations include memory access, such as reading memory. data in .
  • the memory access time is related to the hardware parameters of the processor, which can be understood as the same memory access time for the same core.
  • the total memory access time of a core refers to the sum of the memory access times in the core processing at least one historical task. It can be understood that the longer the total memory access time of the core, the more memory access times required for the tasks processed by the core.
  • the remaining lifetime information and/or the used lifetime information of the core may be determined according to the total memory access time of the core. The longer the total core access time is, the larger the used lifetime information and/or the smaller the remaining lifetime information of the core. .
  • the total memory access time of the core may also be replaced by the hidden total memory access time of the core or the unhidden total memory access time of the core.
  • the total hidden fetch time for a core is the sum of the hidden fetch times in which the core processes at least one task.
  • the hidden memory access time means that the core performs other operations than the memory operation during the memory operation, so that the core performs the memory operation during the memory operation (the period is the memory access time, or a part of the time period of the memory access time. If there is no idling in the memory operation, the time when other operations are performed in the memory access time corresponding to this memory operation is called the hidden memory access time.
  • the task assignment device may tend to assign tasks to cores with less total hidden fetch time.
  • the total unhidden fetch time is the sum of the unhidden fetch times in the core processing at least one task.
  • the unhidden memory access time refers to the time when no other operations other than memory operations are performed during the memory access time.
  • the task assignment device may tend to assign tasks to cores with less total fetch time that are not hidden.
  • the task allocation device may be based on the frequency of the kth core, the voltage of the kth core, the position of the kth core on the CPU, the historical running time of the kth core, or the memory access of the kth core. Any information in the total time determines the used life information of the k-th core, and can also be based on the frequency of the k-th core, the voltage of the k-th core, the position of the k-th core on the CPU, and the k-th core. Multiple pieces of information in the historical running time, or the total fetch time of the kth core, determine the elapsed lifetime information of the kth core.
  • the weights are respectively set for the information, and the used life information of the kth core is determined according to the multiple pieces of information and the weights corresponding to the multiple pieces of information.
  • the core lifetime information can be further determined in combination with the core frequency, voltage or the position of the core on the processor.
  • the lifetime information is determined. For example, when the historical running time of two cores is the same, the used life information of the core with a higher frequency or voltage, or the core located closer to the center of the processor chip or the center of the area where the physical core group is dense The larger and/or the smaller the remaining life information.
  • the manner of determining the lifetime information shown above is merely an example, and in actual use, an extended manner such as permutation and combination may be performed on the basis of the manner exemplified above to determine the lifetime information of the kth core.
  • the lifetime information can also be determined according to the historical running time, frequency, voltage and position of the core on the processor.
  • the used life information of the kth core may be based on the number of historical instructions of the kth core, the average running time of instructions, the frequency of the kth core, and the memory access of the kth core time, and the ratio between the unhidden memory access time in at least one historical task (eg, all historical tasks) of the kth core and the total running time of the at least one historical task.
  • the number of historical instructions of the kth core, the average running time of instructions, the frequency of the kth core, and the memory access time of the kth core may refer to the foregoing description.
  • the memory access time that is not hidden in the at least one historical task of the kth core may be the memory access time during the execution of the at least one historical task by the kth core, and the total running time of the at least one historical task may be the memory access time of the kth core Clock cycles consumed to execute the at least one historical task.
  • the used life information of the k th core may conform to the following formula 1:
  • T comp represents the used life information of the k th core
  • F represents the frequency of the k th core
  • CPI k represents the average running time of the kth core executing instructions.
  • CPI k can be unchanged. Indicates the access time of the kth core.
  • the remaining lifetime information of the core may be determined according to the total lifetime information and the used lifetime information.
  • T core_total the total lifetime information of the k th core
  • T core_total the remaining lifetime information of the k th core
  • T core complies with the following formula 2:
  • T core T core_total -T comp .
  • the frequency of the kth core, the voltage of the kth core, the historical running time of the kth core, or the total memory access time of the kth core, or according to the kth core The number of historical instructions, the average running time of instructions, the frequency of the kth core, the memory access time of the kth core, and the total unhidden memory access time of at least one historical task of the kth core and the historical task.
  • the ratio between the running times, after determining the used life information of the k th core, the used life information of the k th core can also be corrected according to the position of the k th core on the CPU.
  • the junction temperature Tj of the kth core can be determined according to the position of the kth core on the processor, then the relationship between the used life information of the kth core before and after the correction and Tj can conform to Equation 3:
  • T comp ′ represents the used life information of the k-th core after correction
  • T comp represents the used life information of the k-th core before correction
  • a is a correction coefficient, which can be a set value.
  • the remaining life information of the k th core can be corrected according to the position of the k th core on the CPU, and the remaining life information of the k th core before and after the correction Equation 4 can be satisfied between Tj:
  • T core ′ represents the remaining life information of the k th core after correction
  • T core represents the remaining life information of the k th core before the correction
  • a is a correction coefficient, which can be a set value.
  • the first core may be determined according to the respective lifetime information of the multiple cores and the task amount information of the first task.
  • the task amount information of the first task may indicate the number of instructions included in the first task, and the number of instructions may be used to determine the running time for executing the first task.
  • the running time for the core to execute the first task may be determined according to the average running time of any core for executing one instruction and the number of instructions included in the first task.
  • the task amount information of the first task may also indicate the running time of the first task.
  • the first task is a thread as an example for description.
  • the first core may also be determined according to the task amount information of the thread and the respective lifetime information of the multiple cores of the processor.
  • the task amount information of the thread can be used to determine the running time of executing the thread. Taking the life information as the time information of the remaining life or the time information of the used life as an example, the running time of the thread can be determined according to the task amount information of the thread, and the difference between the time information corresponding to the remaining life and the running time of executing the thread can be determined.
  • the first core is selected among the cores greater than or equal to the seventh threshold, and/or the cores whose sum of the used life information and the task amount information of the thread is less than or equal to the eighth threshold.
  • the selection manner of selecting the first core may be random selection or selection based on remaining life information and/or already service life information, or the like.
  • the remaining lifetime information of the selected first core may be limited to be not less than the task amount information of the thread, so as to prevent the core from running out of lifetime after executing the thread.
  • At least one of the first threshold, second threshold, third threshold, fourth threshold, fifth threshold, sixth threshold, seventh threshold or eighth threshold involved in this application may be determined according to the processor.
  • the average lifespan information of other cores other than one core is determined, or is determined according to the average lifespan information of all cores of the processor.
  • the remaining life information and/or the used life information of the first core can be updated and stored according to the task amount information of the thread, and used as the core's information in subsequent task allocation. Lifetime information.
  • the update of the lifetime information of the core may be performed according to the set duration, or the lifetime information of the core may be updated after the core executes one or more tasks.
  • the method of updating the used life information of the core can be described with reference to the foregoing method of determining the used life information of the core.
  • the processor determines, according to Formula 1, at time 1 before executing the first task, the respectively used lifetime information of the K cores, and determines the first core from the K cores.
  • the processor may update the used life information of the first core before time 2 according to the information of the tasks (for example, including the first task) that have been executed by the first core.
  • the used life information T comp ′ updated by the first core may conform to formula 5:
  • F represents the frequency of the processor
  • CPI k represents the average running time for the kth core to execute an instruction.
  • the used life information of the core can also be updated according to other methods than Formula 1, which is not specifically limited in this application.
  • the duration of the core executing the first task can also be counted by a counter, and the used life information of the first core before time 2 is obtained according to the duration and the used life information of the first core before time 1.
  • the updated remaining lifetime information of the kth core may be determined according to the total lifetime information of the kth core and the updated used lifetime information of the kth core.
  • Equation 2 can be referred to.
  • the core lifetime information may be stored in the BIOS.
  • a core lifetime recorder unit or simply a record unit may be added to the BIOS to store the core lifetime information.
  • the module or unit performing the task assignment can obtain the life information of the core from the recording unit.
  • the updated lifetime information of the cores may also be stored to the recording unit.
  • Manner 1 The task allocation method provided by the embodiment of the present application is implemented by executing software on the operating system of the processor.
  • the Linux scheduler can execute the software (such as executing computer program instructions), so that the Linux scheduler can perform task allocation according to the life information of the core, that is, determine the relationship between the core and the core according to the life information of the core. Mapping relationship between tasks/threads.
  • the Linux scheduler can store computer program instructions, or acquire and execute program instructions from a memory, so as to implement the task allocation method.
  • the task allocation process may include: after the application program runs, the tasks of the application program are processed by the Linux operating system (represented as operation in FIG. 6 ).
  • the application programming interface (API) of the system) performs resource allocation, the driver of the Linux operating system sends the task to the Linux scheduler, and the Linux scheduler executes the software, and realizes the following steps: obtain the life information of the core from the recording unit of the BIOS (In other words, the core life information stored in the recording unit is transparently transmitted to the Linux scheduler), and the mapping relationship between the threads included in the task and the core is determined according to the core life information, that is, task allocation is realized.
  • each thread is executed by the core corresponding to the thread, and then the lifespan information of the core corresponding to the thread is updated after the thread ends, and the updated lifespan information is stored in the recording unit of the BIOS, so that subsequent downloads can be performed according to the updated lifespan information of the core.
  • Manner 2 The task allocation method provided by the embodiment of the present application is implemented by a processor.
  • the CPU can execute the software solidified in the CPU (such as executing computer program instructions), so that the CPU can allocate tasks according to the life information of the core, that is, determine the threads included in the core and the task according to the life information of the core. the mapping relationship between them.
  • computer program instructions can also be obtained by the CPU from a storage system or a memory other than the CPU, so as to implement the task allocation method.
  • the task allocation process may include: after the application program runs, the tasks of the application program perform resource allocation through the API of the Linux operating system (represented as operating system in FIG. 7 ).
  • the Linux operating system The driver sends the task to the Linux scheduler (represented as the scheduler in Figure 7), the Linux scheduler sends the task to the CPU, and the CPU executes the software to implement the following steps: Obtain the core's data from the recording unit of the BIOS through the hardware interface of the CPU.
  • the lifespan information (or, in other words, the lifespan information of the cores stored in the recording unit is transparently transmitted to the CPU), and the mapping relationship between the threads and the cores is determined according to the lifespan information of the cores.
  • Each thread is executed by the core corresponding to the thread. After the thread ends, the life information of the core corresponding to the thread is updated by the CPU, and the updated life information is stored in the recording unit of the BIOS through the hardware interface, so as to follow the updated life of the core. information for the next task assignment.
  • Mode 3 Application of the task allocation method provided by the embodiment of the present application in a heterogeneous processor.
  • the CPU can be used to schedule tasks of the GPU.
  • the CPU and the GPU can be connected through a fast peripheral component interconnect (PCIe) bus (bus) or other means.
  • PCIe peripheral component interconnect
  • the operating system of the CPU can perform the task of the GPU according to the life information of the GPU core.
  • the PCIe bus can be used to connect the dynamic random access memory (DRAM) of the CPU and the DRAM of the GPU.
  • the CPU may further include a control unit, an arithmetic and logic unit (arithmetic and logic unit, ALU) and a cache memory (Cache).
  • the Linux operating system of the CPU can obtain the lifespan information of the GPU core through the PCIe bus and store it in the recording unit of the BIOS of the CPU.
  • the Linux operating system of the CPU can obtain the parameters of the GPU core for determining the lifetime information through the PCIe bus, for example, the total lifetime information of the kth core of the GPU, the frequency of the processor, the number of historical instructions of the kth core, At least one of the average task volume information of instructions, the fetch time of the kth core, or the ratio between the unhidden fetch time of the kth core in executing at least one task and the running time of at least one task information, determine the lifespan information of the GPU core according to the acquired parameters, and store it in the recording unit of the CPU BIOS.
  • the lifetime information of the GPU core and/or the parameters for determining the lifetime information of the GPU core may be stored in the DRAM of the GPU.
  • the task of the GPU can be performed by the Linux scheduler of the Linux operating system of the CPU or the CPU according to the life information of the GPU core stored in the recording unit of the BIOS. Allocation, that is, determining the mapping relationship between the threads included in the tasks of the GPU and the cores of the GPU.
  • the manner in which the GPU task allocation is performed by the Linux scheduler may refer to the description in the foregoing manner 1, and the manner in which the CPU performs the GPU task assignment may refer to the description in the foregoing manner 2, which will not be repeated here.
  • the CPU determines the mapping relationship between the threads and the cores of the GPU, the CPU can notify the GPU of the mapping relationship through the bus.
  • the lifespan information of the GPU core can be updated by the Linux scheduler or the CPU, and the updated lifespan information of the GPU core is stored in the recording unit.
  • the embodiments of the present application propose a multi-core management software and hardware system design in scenarios such as homogeneous processors and heterogeneous processors, so that the task allocation process is performed according to the life information of the cores, and the load balancing problem of the CPU cores is solved. , in order to prolong the life of the nucleus. Due to the extended core lifetime, the core can operate at a higher frequency, thus improving the performance of the processor.
  • an embodiment of the present application provides another task assignment method. Taking the task assignment device executing the method as an example, the method may include the following steps:
  • the task allocating apparatus acquires third information respectively of the multiple processors, where the third information is used to describe the service life of the processors.
  • the third information may be lifetime information of the processor.
  • the third information includes remaining lifetime information and/or used lifetime information of the processor, and the third information may also be the average lifetime information and/or processing information of cores in the processor.
  • the lifetime information of the core with the least remaining lifetime in the processor may be the sum of remaining lifetime information of the cores included in the processor, or may be other parameters or indicators used to measure the remaining lifetime of the processor.
  • the used life information of the processor may be the sum of the used life information of the cores included in the processor, or may be other parameters or indicators used to measure the used life of the processor.
  • the average lifetime information of the cores in the processor may be determined according to the remaining lifetime information or the used lifetime information of each core in the processor.
  • the lifetime information of the core with the least remaining lifetime in the processor may be the remaining lifetime information and/or the used lifetime information of the core with the least remaining lifetime information.
  • the task assignment device may be one of multiple processors, or may be a computer system other than multiple processors.
  • the task allocation apparatus determines, according to the third information of the multiple processors, a first processor for processing a second task from the multiple processors, and the second task is a task to be processed.
  • the task allocating apparatus may select the first processor from processors whose remaining life information indicated by the third information is larger and/or whose used life information is smaller.
  • the task assignment device can perform task assignment according to the third messages of the multiple processors, so the life spans of the multiple processors are balanced to prolong the life span of the processor system composed of the multiple processors.
  • the task allocation apparatus may determine the first processor according to the respective third information of the multiple processors and the task amount information of the second task.
  • the first processor according to the third information of the multiple processors and the task amount information of the second task respectively refer to S102 to determine the first processor according to the life information of the multiple cores and the task amount information of the first task respectively. cores to avoid running out of processor life due to the execution of the first task. For example, the remaining life information indicated by the third information or the processor that is not lower than the task amount information of the second task may be determined as the first processor.
  • the embodiments of the present application further provide a task assignment device, which is used to implement the steps shown in the above method embodiments.
  • the device may include the structure shown in FIG. 10 and/or FIG. 11 .
  • the task assignment apparatus can be applied to a computer system with multiple processor cores, and can be used to implement the task assignment method shown in FIG. 2 and/or FIG. 9 .
  • the task assignment apparatus may include a recording module 1010 and a task assignment module 1020 .
  • the recording module 1010 may be configured to acquire respective first information of multiple cores of the processor, where the first information is used to describe the service life of the cores.
  • the task allocation module 1020 may be configured to determine, according to the respective first information of the multiple cores, a first core for processing the first task from the multiple cores, and the first task is a task to be processed.
  • the task assignment apparatus in this embodiment of the present application may be implemented by software, for example, a computer program or instruction having the functions of the recording module 1010 and/or the task assignment module 1020 described above, and the corresponding computer program or instruction may be stored.
  • the above-mentioned functions of the recording module 1010 and/or the task assignment module 1020 are realized by the processor reading the corresponding computer program or instruction in the memory.
  • the task allocation apparatus in the embodiment of the present application may also be implemented by hardware.
  • the task allocation module 1020 may include a processor (eg, a CPU or a processor in a system chip).
  • the logging module 1010 may include a memory, or include a communication interface, such as a transceiver or an input/output interface, that supports communication with the memory, for the task assignment module 1020 to obtain the first information of the core from the memory.
  • the task allocation module 1020 may determine the first core according to the respective first information of the multiple cores and the task amount information of the first task.
  • the task allocation module 1020 can be based on the physical core group.
  • the first information of the cores in the first physical core group is determined, and the first physical core group corresponding to the first task is determined, and according to the first information of the cores in the first physical core group, each cores corresponding to each thread.
  • the recording module 1010 is further configured to store updated first information of the first core, and the updated first information is determined according to the first information of the first core and the task amount information of the first task.
  • the updated first information may be determined by the task assignment module 1020 .
  • the first information of the kth core of the processor includes remaining lifetime information of the kth core; and/or the first information includes the used lifetime information of the kth core.
  • the remaining lifetime information of the kth core is determined according to the total lifetime information and the used lifetime information of the kth core.
  • the lifetime information of the kth core may be based on the historical running time of the kth core, the frequency and historical running time of the kth core, the voltage and historical running time of the kth core, the kth core.
  • the position of the cores on the processor, the total memory access time of the kth core, the historical instruction count and average execution time of the kth core, or the frequency of the kth core and the total memory access time at least one piece of information Sure.
  • the recording module 1010 belongs to the firmware, or the recording module 1010 may acquire the respective first information of the multiple cores of the processor from the firmware.
  • the recording module includes an editable memory in the firmware, and the editable memory can be used to store at least one of the first information, the second information or the third information designed in this application.
  • the programmable memory is an erasable programmable read-only memory (EPROM) or an electrically erasable programmable read-only memory (EEPROM).
  • the recording module includes a performance monitor unit (performance monitor unit, PMU) of the processor, for the processor to obtain at least one of the first information, the second information or the third information from the firmware.
  • a performance monitor unit performance monitor unit, PMU
  • the task allocation module 1020 includes a task scheduler.
  • the task allocation module 1020 is a Linux scheduler in the Linux operating system.
  • the recording module 1010 may acquire third information of multiple processors respectively, where the third information is used to describe the service life of the processors.
  • the task allocation module 1020 may determine, according to the respective first information of the multiple processors, a first processor for processing the second task from the multiple processors, and the second task is a to-be-processed task.
  • the task allocation module 1020 may specifically determine the first processor according to the respective third information of the multiple processors and the task amount information of the second task.
  • the embodiments of the present application further provide another task allocation apparatus that may include the structure shown in FIG. 11 for executing the actions of the task allocation methods provided in the embodiments of the present application in FIG. 2 , FIG. 9 and/or the present application.
  • the task allocation apparatus may include a processor 1110 and a memory 1120 .
  • the processor 1110 may include multiple cores.
  • the memory 1120 may be used to store lifetime information of a plurality of cores.
  • the processor 1110 may be configured to execute the task allocation method described in the foregoing embodiments. It should be understood that in FIG. 11 , only one processor 1110 and one memory 1120 are used as an example for description, and the task allocation apparatus provided in this application may include other numbers of memories 1120 and processors 1110 .
  • the processor 1110 and the memory 1120 are connected to each other through a bus.
  • the bus may be a peripheral component interconnect standard (peripheral component interconnect, PCI) bus or an extended industry standard architecture (extended industry standard architecture, EISA) bus, or the like.
  • PCI peripheral component interconnect
  • EISA extended industry standard architecture
  • the bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of presentation, only one thick line is used in FIG. 11, but it does not mean that there is only one bus or one type of bus.
  • the at least one processor 1110 may include at least one of the following: a CPU, a microprocessor, an application specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the programs of the present application.
  • the CPU may include a power consumption controller and at least one processor core, and the power consumption controller can acquire the failure information of the at least one processor core, and convert the failure information of the at least one processor core stored in the memory 1120 .
  • the memory 1120 can be ROM or other types of static storage devices that can store static information and instructions, RAM or other types of dynamic storage devices that can store information and instructions, or can be EEPROM, compact disc read-only memory. , CD-ROM) or other optical disk storage, optical disk storage (including compact disk, laser disk, optical disk, digital versatile disk, Blu-ray disk, etc.), magnetic disk storage medium or other magnetic storage device, or capable of carrying or storing instructions or The desired program code in the form of a data structure and any other medium that can be accessed by a computer, but not limited thereto.
  • the memory can exist independently and be connected to the processor through a bus.
  • the memory can also be integrated with the processor.
  • the memory 1120 is used for storing computer-executed instructions for executing the solutions of the present application, and the execution is controlled by the processor 1110 .
  • the processor 1110 is configured to execute the computer-executed instructions stored in the memory 1120, thereby implementing the task scheduling method provided by the above embodiments of the present application.
  • the function of the task allocation module 1020 shown in FIG. 10 can be implemented by the processor 1110 .
  • the function of the recording module 1010 shown in FIG. 10 can be implemented by the memory 1120, that is, acquiring the first information of the core, and/or storing the updated first information of the core.
  • the task assignment shown in FIG. 11 may further include a communication interface, such as a transceiver or an input/output interface.
  • a communication interface such as a transceiver or an input/output interface.
  • the first information of the core may be acquired from other memories (or other storage media) by the interface, and/or the updated first information of the core may be sent to other memories.
  • the computer program instructions in the embodiments of the present application may also be referred to as application program codes, which are not specifically limited in the embodiments of the present application.
  • Embodiments of the present application further provide a computer-readable storage medium, where the computer-readable storage medium is used to store a computer program, and when the computer program is executed by a computer, the computer can implement the processes related to the foregoing method embodiments.
  • Embodiments of the present application further provide a computer program product, where the computer program product is used to store a computer program, and when the computer program is executed by a computer, the computer can implement the processes related to the foregoing method embodiments.
  • Embodiments of the present application further provide a chip or a chip system (or circuit), where the chip may include a processor, and the processor may be configured to call a program or an instruction in a memory to execute the connection between the network device and/or the network device and/or the method provided by the foregoing method embodiments. Terminal related processes.
  • the chip system may include components such as the chip, memory or transceiver.
  • the embodiments of the present application may be provided as a method, a system, or a computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
  • computer-usable storage media including, but not limited to, disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory result in an article of manufacture comprising instruction means, the instructions
  • the apparatus implements the functions specified in the flow or flow of the flowcharts and/or the block or blocks of the block diagrams.

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Abstract

La présente invention se rapporte au domaine technique des ordinateurs et concerne un procédé et un dispositif d'attribution de tâches. Le procédé peut être appliqué à un système informatique comportant une pluralité de cœurs de processeur, et comprend les étapes suivantes : obtenir des premières informations de chaque cœur d'une pluralité de cœurs d'un processeur, les premières informations étant utilisées pour décrire la durée de vie d'un cœur; et selon les premières informations de la pluralité de cœurs, déterminer, à partir de la pluralité de cœurs du processeur, un premier cœur pour le traitement d'une première tâche, la première tâche étant une tâche à traiter. Au moyen de la conception, dans le système informatique comportant la pluralité de cœurs de processeur, une tâche peut être ordonnancée selon des informations de durée de vie des cœurs de processeur, ce qui permet de réaliser autant que possible l'égalisation d'usure entre les cœurs de la pluralité de cœurs de processeur, ce qui assure la durée de vie d'un dispositif, et assure que le cœur puisse fonctionner à une fréquence plus élevée pendant une plus longue durée.
PCT/CN2021/103160 2021-03-09 2021-06-29 Procédé et dispositif d'attribution de tâches WO2022188306A1 (fr)

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US20170031412A1 (en) * 2015-07-29 2017-02-02 Intel Corporation Masking a power state of a core of a processor
CN108509014A (zh) * 2017-02-27 2018-09-07 三星电子株式会社 计算设备和分配功率到每个计算设备中的多个核的方法
CN111105837A (zh) * 2018-10-29 2020-05-05 三星电子株式会社 管理退化程度的电子装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
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CN105830034A (zh) * 2013-12-18 2016-08-03 高通股份有限公司 针对增加的工作寿命和最大化的性能的多核系统设计的运行时间优化
US20170031412A1 (en) * 2015-07-29 2017-02-02 Intel Corporation Masking a power state of a core of a processor
CN108509014A (zh) * 2017-02-27 2018-09-07 三星电子株式会社 计算设备和分配功率到每个计算设备中的多个核的方法
CN111105837A (zh) * 2018-10-29 2020-05-05 三星电子株式会社 管理退化程度的电子装置

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