WO2022178668A1 - 处理多图层图像的方法、装置及终端设备 - Google Patents

处理多图层图像的方法、装置及终端设备 Download PDF

Info

Publication number
WO2022178668A1
WO2022178668A1 PCT/CN2021/077474 CN2021077474W WO2022178668A1 WO 2022178668 A1 WO2022178668 A1 WO 2022178668A1 CN 2021077474 W CN2021077474 W CN 2021077474W WO 2022178668 A1 WO2022178668 A1 WO 2022178668A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
layers
area
pixels
target area
Prior art date
Application number
PCT/CN2021/077474
Other languages
English (en)
French (fr)
Inventor
宋丹娜
孟飚
王伯庆
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP21927115.2A priority Critical patent/EP4287113A4/en
Priority to CN202180092782.4A priority patent/CN116868225A/zh
Priority to PCT/CN2021/077474 priority patent/WO2022178668A1/zh
Publication of WO2022178668A1 publication Critical patent/WO2022178668A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T11/00—2D [Two Dimensional] image generation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T11/00—2D [Two Dimensional] image generation
    • G06T11/40—Filling a planar surface by adding surface attributes, e.g. colour or texture

Definitions

  • the present application relates to the technical field of image processing, and in particular, to a method, apparatus and terminal device for processing multi-layer images.
  • the display screen of the mobile phone is getting bigger and bigger, the applications (application, APP) installed on the mobile phone are becoming more and more abundant, and the functions are more and more diversified.
  • multiple screens can be displayed on the display screen.
  • APP window In a multi-window display scenario, multiple APP windows are actually superimposed by multiple layers.
  • its display content may also be superimposed by multiple layers.
  • the more layers the greater the memory read bandwidth and the greater the power consumption.
  • the refresh rate of the display is high (for example, 120Hz)
  • a large number of layers will lead to the boosting of the display's voltage and frequency, resulting in an increase in the memory read bandwidth and an increase in power consumption, thus affecting the user experience.
  • the present application provides a method, device and terminal device for processing multi-layer images, which solve the problems of large memory read bandwidth and power consumption in the prior art when the image to be displayed includes a large number of layers.
  • the present application provides a method for processing a multi-layer image, the method comprising: determining each first image in the M first layers according to pixel transparency information of the M first layers and the relationship between upper and lower layers The target area of the layer, the target area includes a transparent area and/or a covered area; and read the pixels in the M first layers except the target area to obtain M second layers; then display the M first layers In an image obtained by superimposing two layers, the total number of pixels in the M second layers is less than the total number of pixels in the M first layers.
  • the above-mentioned covered area is an area covered by the opaque area of the upper layer layer, the pixel transparency information corresponding to the pixel in the opaque area indicates that the pixel is opaque, and the pixel transparency information corresponding to the pixel in the transparent area indicates that the pixel is transparent, and M is Integer greater than 1.
  • the transparency and/or coverage of the layers can be analyzed according to the pixel transparency components in the multiple layers and the relationship between the upper and lower layers of the layers, and the transparent areas and/or the transparent areas in the layers can be determined. covered area. Since the transparent area and/covered area do not contribute to the display effect when displayed, the content of these areas can be skipped and not read, so when reading the layer, the content that contributes to the display effect in the layer is selected to be read, These transparent areas and/or covered areas are skipped and not read, which can reduce the read bandwidth and power consumption.
  • the M first layers include a top layer first layer, a middle layer first layer, and a bottom layer first layer
  • the pixel transparency according to the M first layers determine the target area of each first layer in the M first layers, including:
  • the reading the pixels in the M first layers except the target area, to obtain M second layers including:
  • the M second layers include the top second layer, the middle second layer and the bottom second layer.
  • the layer before reading the layer, it can be determined whether there is a transparent area and/or a covered area in the layer.
  • the top layer of multiple layers may have transparent areas, but there may be no covered areas; the middle layer or bottom layer of multiple layers may have transparent areas and may have covered areas.
  • the embodiment of the present application proposes: before reading the layer, it is possible to analyze whether there is a transparent area in the layer, and the pixels in the transparent area can be skipped and not read.
  • the embodiment of the present application proposes that: before reading the layer, it is possible to analyze whether there is any covered area in the layer. area, the pixels of the covered area can be skipped and not read.
  • the method further includes: marking a mask in the target area of each of the M first layers, the pixels in the area indicated by the mask are not allowed to be read.
  • the reading the pixels in the M first layers except the target area includes: reading the image areas in the M first layers that are not marked with the mask and do not read the pixels in the image area marked with the mask in the M first layers.
  • whether the pixel is transparent may be determined according to the A component in the pixel data in the layer, and mask marking is performed for the transparent pixel in the layer or the area where the transparent pixel is located.
  • the area marked with the mask can be referred to as the mask area.
  • mask marking can be performed on the covered pixels in the layer or the area where the covered pixels are located.
  • the area marked with a mask may be referred to as a mask area.
  • the mask is marked for that pixel so that it cannot be read.
  • the A component indicates that the pixel is opaque, and that pixel will cover the pixel in the lower position, then the pixel in the lower position is marked with a mask so that it cannot be read.
  • the above-mentioned mask may be a string of binary codes to perform AND operation on the field corresponding to the pixel to mask the current field corresponding to the pixel.
  • the fields corresponding to the masked pixels will not be read. That is to say, the above-mentioned mask area can also be understood as a mask area, and the pixels in the mask area will not be read.
  • the transparent area and/covered area in the layer can be determined, and the transparent area and/covered area can be masked and marked, thereby Get the mask area.
  • the terminal device can read the pixels in the image areas that are not marked with masks in the M first layers, and may not read the pixels in the image areas marked with masks in the M first layers at this time. . Since some pixels that contribute to the display effect are selected to be read when the layers are read, the total number of pixels in the M second layers obtained by reading is less than the total number of pixels in the M first layers.
  • the embodiment of the present application analyzes the coverage and/or transparency of the layer before reading the layer, and determines the data that cannot be read according to the coverage and/or transparency of the layer, so that when the layer is read, the data that cannot be read is determined.
  • These masked areas can be skipped and not read to reduce read bandwidth and power consumption.
  • the method before the determining of the target area of each first layer in the M first layers, the method further includes: obtaining the M first layers by drawing through an image processor GPU Layers, the M first layers have the upper-lower hierarchical relationship.
  • the GPU when the program is running, the GPU performs corresponding processing on the program running process and results according to the instructions and related data provided by the CPU, and converts them into text and image display signals that the display can accept. Specifically, firstly, M first layers are obtained by drawing on the GPU, then the plurality of layer data is written into the memory, and then the plurality of layer data is read from the memory and displayed on the display.
  • the method further includes: acquiring the M first layers according to pixel data of the M first layers pixel transparency information of the layer; write the M first layers and the pixel transparency information into the memory.
  • the reading the pixels in the M first layers except the target area includes: reading from the memory the pixels in the M first layers except the target area outside the pixels.
  • This application uses hardware to prejudge the layer transparency and coverage properties before layer stacking, and determines the transparent area and/or covered area in the layer according to the layer transparency and coverage properties. Or the covered area can be skipped without reading, thereby reducing the layer reading bandwidth and display power consumption.
  • the acquiring the pixel transparency information of the M first layers includes: dividing each of the M first layers into N tiles, where N is an integer greater than 1; traverses all pixel data in each tile, and obtains the pixel transparency information corresponding to each tile.
  • the writing the M first layers and the pixel transparency information into the memory includes: compressing each block in the M first layers and the corresponding pixel transparency information then write to the memory.
  • the layer is compressed, and an identifier may be used to perform statistics on the A component of each pixel in each block during compression.
  • a field corresponding to each tile in the M first layers includes a header field and a data field
  • the header field corresponding to each tile includes each tile Transparency information of all the pixels or part of the pixels in the transparent area and/or the opaque area
  • the data field corresponding to each tile includes all the pixels in the each tile pixel value.
  • compressing each block in the M first layers and writing the corresponding pixel transparency information into the memory includes: compressing each block in the M first layers The header field and the data field corresponding to each tile are written into the memory.
  • the determining the target area of each first layer in the M first layers according to the pixel transparency information of the M first layers and the relationship between upper and lower layers includes: according to the M first layers The respective header fields and data fields of the N blocks in each first layer in the first layer determine the target area of each first layer.
  • the M first layers are images in an RGBA or ARGB data format, wherein R, G, and B respectively represent the color components of the pixels, and A represents the transparency components of the pixels.
  • the displaying an image obtained by superimposing the M second layers includes: determining the upper and lower layers of the M second layers according to the upper and lower hierarchical relationships of the M first layers Hierarchical relationship; superimposing the M second layers according to the upper and lower hierarchical relationship of the M second layers to obtain a target image; displaying the target image on the display screen.
  • the present application provides an apparatus for processing a multi-layer image, the apparatus comprising a unit for performing the method in the above-mentioned first aspect.
  • the apparatus may correspond to executing the method described in the first aspect.
  • the description of the units in the apparatus please refer to the description of the first aspect. For brevity, details are not repeated here.
  • the method described in the first aspect above may be implemented by hardware, or may be implemented by executing corresponding software by hardware.
  • the hardware or software includes one or more modules or units corresponding to the above functions, such as a processing module or unit, a reading module or unit, a display module or unit, and the like.
  • the present application provides a terminal device, the terminal device includes a processor, the processor is coupled with a memory, the memory is used for storing computer programs or instructions, and the processor is used for executing the computer programs or instructions stored in the memory, so that the first The methods in the aspect are executed.
  • the processor is configured to execute computer programs or instructions stored in the memory, so that the terminal device executes the method in the first aspect.
  • the present application provides a computer-readable storage medium on which a computer program (which may also be referred to as instructions or codes) for implementing the method in the first aspect is stored.
  • the computer program when executed by a computer, causes the computer to perform the method of the first aspect.
  • the present application provides a chip including a processor.
  • the processor is adapted to read and execute the computer program stored in the memory to perform the method of the first aspect and any possible implementations thereof.
  • the chip further includes a memory, and the memory is connected to the processor through a circuit or a wire.
  • the present application provides a chip system including a processor.
  • the processor is adapted to read and execute the computer program stored in the memory to perform the method of the first aspect and any possible implementations thereof.
  • the chip system further includes a memory, and the memory is connected to the processor through a circuit or a wire.
  • the present application provides a computer program product, the computer program product comprising a computer program (also referred to as instructions or codes), which when executed by a computer causes the computer to implement the method in the first aspect .
  • a computer program also referred to as instructions or codes
  • FIG. 1 is a schematic diagram of the architecture of an operating system to which a method for processing a multi-layer image provided by an embodiment of the present application is applied;
  • FIG. 2 is one of the schematic flowcharts of the method for processing a multi-layer image provided by an embodiment of the present application
  • FIG. 3 is a schematic diagram of determining a transparent area of a layer in a method for processing a multi-layer image provided by an embodiment of the present application;
  • FIG. 4 is one of the schematic diagrams of determining the covered area of a layer in the method for processing a multi-layer image provided by an embodiment of the present application;
  • FIG. 5 is the second schematic diagram of determining the covered area of a layer in the method for processing a multi-layer image provided by an embodiment of the present application;
  • FIG. 6 is a schematic diagram of applying the method for processing a multi-layer image provided by an embodiment of the present application to a multi-layer image including a fully transparent layer;
  • FIG. 7 is a schematic diagram of applying the method for processing a multi-layer image provided by an embodiment of the present application to a multi-layer image including an opaque layer;
  • FIG. 8 is a schematic block diagram of an image display principle to which the method for processing a multi-layer image provided by an embodiment of the present application is applicable;
  • FIG. 9 is a second schematic flowchart of a method for processing a multi-layer image provided by an embodiment of the present application.
  • FIG. 10 is a schematic block diagram of the method for processing multi-layer images provided by an embodiment of the present application when processing consecutive multi-frame images;
  • FIG. 11 is a schematic structural diagram of an apparatus for processing a multi-layer image provided by an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a terminal device provided by an embodiment of the present application.
  • first and second and the like in the specification and claims herein are used to distinguish between different objects, rather than to describe a particular order of the objects.
  • first layer and the second layer, etc. are used to distinguish different layers, not to describe a specific order of layers.
  • words such as “exemplary” or “for example” are used to represent examples, illustrations or illustrations. Any embodiments or designs described in the embodiments of the present application as “exemplary” or “such as” should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as “exemplary” or “such as” is intended to present the related concepts in a specific manner.
  • plural refers to two or more, for example, a plurality of processing units refers to two or more processing units, etc.; a plurality of An element refers to two or more elements or the like.
  • the APP installed on the mobile phone has become more and more abundant, and the use functions have become more and more diversified.
  • multiple APP windows can be displayed on the display screen in a split screen.
  • multiple APP windows are actually superimposed by multiple layers.
  • its display content may also be superimposed by multiple layers.
  • the more layers the greater the memory read bandwidth and the greater the power consumption.
  • the bandwidth is used to characterize the data transmission capability of signal transmission, the amount of data passing through the link per unit time, and the display capability of the display. As the refresh rate of the display increases, the demand for the bandwidth of the display increases.
  • the refresh rate of the display is high (for example, 120Hz)
  • a large number of layers will lead to the boosting of the display's voltage and frequency, resulting in an increase in the memory read bandwidth and an increase in power consumption, thus affecting the user experience.
  • the display screen of a monitor usually adopts a command mode (command mode) and a video mode (video mode).
  • command mode command mode
  • video mode video mode
  • the partial refresh method can be used to reduce the bandwidth, but the cost is high.
  • lower cost video mode displays can be used.
  • a display screen in video mode if the display content is a still image, a single layer obtained by superimposing multiple layers can be sent to the display screen for display (referred to as “send display” for short), which can reduce bandwidth and power consumption.
  • the display screen in the video mode still faces great pressure on bandwidth and power consumption for a scene where multiple layers of the non-still image are superimposed.
  • the embodiments of the present application provide a method, device and terminal device for processing multi-layer images, which can determine each of the M first layers according to the pixel transparency information of the M first layers and the relationship between the upper and lower levels.
  • a target area of the first layer the target area includes a transparent area and/or a covered area (that is, the area covered by the opaque area of the upper layer layer); then read the M first layers except the target area.
  • M second layers are obtained; then the image obtained by superimposing M second layers is displayed, and the total number of pixels in the M second layers is less than the total number of pixels in the M first layers. quantity.
  • the transparency and/or coverage of the layers can be analyzed according to the pixel transparency components in the multiple layers and the relationship between the upper and lower layers of the layers, so as to determine the transparent area and/or coverage of the layers. /covered area. Since the transparent area and/covered area do not contribute to the display effect when displayed, the content of these areas can be skipped and not read, that is, when reading the layer, select to read the content in the layer that contributes to the display effect, These transparent areas and/or covered areas are skipped and not read, which can reduce the read bandwidth and power consumption.
  • the terminal device includes a hardware layer, an operating system layer running on the hardware layer, and an application layer running on the operating system layer.
  • the hardware layer may include hardware such as a central processing unit (CPU), a memory management unit (MMU), and memory (also called main memory).
  • the operating system of the operating system layer may be any one or more computer operating systems that implement business processing through processes, such as Linux operating systems, Unix operating systems, Android operating systems, iOS operating systems, or Windows operating systems, etc. It may also be other possible operating systems, which are not specifically limited in this embodiment of the present application.
  • the application layer may include applications such as video players, browsers, address books, word processing software, and instant messaging software.
  • the following takes the Android operating system as an example to introduce the software environment to which the media data processing method provided by the embodiment of the present application is applied.
  • FIG. 1 it is a schematic diagram of the architecture of a possible Android operating system provided by an embodiment of the present application.
  • the architecture of the Android operating system includes four layers, namely: an application layer, an application framework layer, a system runtime layer, and a kernel layer (specifically, a Linux kernel layer).
  • the application layer includes various applications (including system applications and third-party applications) in the Android operating system.
  • the application framework layer is the framework of the application, and developers can develop some applications based on the application framework layer under the condition of complying with the development principles of the framework of the application.
  • the system runtime layer includes libraries (also called system libraries) and the Android operating system runtime environment.
  • the library mainly provides various resources required by the Android operating system.
  • the Android operating system operating environment is used to provide a software environment for the Android operating system.
  • the kernel layer is the operating system layer of the Android operating system and belongs to the bottom layer of the Android operating system software layer.
  • the kernel layer provides core system services and hardware-related drivers for the Android operating system based on the Linux kernel.
  • a developer can develop a software program for implementing the media data processing method provided by the embodiment of the present application based on the system architecture of the Android operating system as shown in FIG.
  • the media data processing method may run based on the Android operating system as shown in FIG. 1 . That is, the processor or the terminal device can implement the media data processing method provided by the embodiments of the present application by running the software program in the Android operating system.
  • the terminal device in this embodiment of the present application may be a mobile terminal or a non-mobile terminal.
  • the mobile terminal may be a mobile phone, a tablet computer, a notebook computer, a palmtop computer, a vehicle-mounted terminal, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (personal digital assistant, PDA), etc.
  • the non-mobile terminal may be a personal computer (personal computer, PC), a television (television, TV), a teller machine or a self-service machine, etc., which are not specifically limited in the embodiments of the present application.
  • the execution subject of the media data processing method provided by the embodiment of the present application may be the above-mentioned terminal device, or may be a functional module and/or functional entity in the terminal device capable of implementing the media data processing method, and the specific implementation may be based on actual usage requirements. It is confirmed that the embodiments of the present application are not limited.
  • the media data processing method provided by the embodiment of the present application is exemplarily described below by taking a terminal device as an example and with reference to the accompanying drawings.
  • FIG. 2 is a schematic flowchart of a method for processing a multi-layer image provided by an embodiment of the present application. As shown in FIG. 2, the method 100 includes the following steps S110-S130.
  • S110 Determine a target area of each of the M first layers according to the pixel transparency information of the M first layers and the relationship between upper and lower layers, where the target area includes a transparent area and/or a covered area.
  • the covered area is an area covered or blocked by the opaque area of the upper layer layer.
  • the transparency information corresponding to the pixels in the opaque area indicates that the pixels are opaque, and these opaque pixels are simply referred to as opaque pixels.
  • the transparency information corresponding to the pixels in the transparent area indicates that the pixels are transparent, and these transparent pixels are simply referred to as transparent pixels.
  • the above-mentioned pixel transparency information may use percentage to represent transparency, for example, 100% represents complete transparency, and 0% represents complete opacity.
  • the above-mentioned pixel transparency information may also use other forms to represent transparency, for example, using hexadecimal representation, 00 represents complete transparency, and FF represents complete opacity.
  • the specific representation form of the pixel transparency information may be determined according to actual usage requirements, which is not limited in this embodiment of the present application.
  • the pixel data of each of the above-mentioned first layers includes pixel transparency information, and whether the pixel is transparent or opaque can be determined based on the pixel transparency information.
  • each of the above-mentioned first layers may be an image in an RGBA data format, or an image in an ARGB data format, wherein R, G, and B respectively represent the color components of the pixel, and A represents the transparency of the pixel weight.
  • R, G, and B respectively represent the color components of the pixel
  • A represents the transparency of the pixel weight.
  • it can be determined whether the pixel is transparent or opaque according to the A component in the pixel data in the layer. In this way, by analyzing the A component, the transparency of the layer can be determined, and the transparent area of the layer can be determined. coverage area.
  • the A component of a pixel in the layer is 00, it can be determined that the pixel is completely transparent, and if the A component of a pixel in the layer is FF, it can be determined that the pixel is completely opaque.
  • the A component of a pixel in the layer is 0%, it can be determined that the pixel is completely transparent, and if the A component of a pixel in the layer is 100%, it can be determined that the pixel is completely opaque.
  • the pixels in the transparent area are transparent, when a multi-layer image is displayed, the pixels in the transparent area will not be visible due to transparency, that is, the pixels in the transparent area will not contribute to the display effect when displayed, so
  • the embodiment of the present application proposes that, before reading the layer, it is possible to analyze whether there is a transparent area in the layer, and the pixels in the transparent area can be skipped and not read.
  • layer 21 is an upper layer
  • layer 22 is a lower layer.
  • the multi-layer image to be processed in this embodiment of the present application includes at least two layers (the above-mentioned M is an integer greater than 1), and the at least two layers have an upper-lower hierarchy relationship.
  • the multiple layers When displaying the multiple layers, the multiple layers will be superimposed and displayed based on the upper-lower hierarchical relationship. Due to the hierarchical relationship between multiple layers, the upper layer may cover the lower layer between the layers. From the overlay display effect, the opaque area of the upper layer will cover a part of the lower layer. , since the partial area is covered, the partial area is called the covered area. It should be noted that, since the transparent area of the upper layer has no effect on the display of the lower layer, the embodiment of the present application mainly considers the situation that the opaque area of the upper layer covers or blocks the lower layer.
  • layer 23 is an upper layer and includes an opaque area 231
  • layer 24 is a lower layer.
  • the layer 23 is on the top and the layer 24 is on the bottom, wherein the opaque area 231 of the layer 23 will cover or block the area 241 of the layer 24 (as shown by the black area in FIG. 4 ). shown), so the pixels in the area 241 of this layer 24 can be skipped and not read.
  • the transparent area or semi-transparent area in the layer 23 has no influence on the display of the layer 24 .
  • layer 25 is the top layer and includes an opaque area 251
  • layer 26 is a middle layer and includes an opaque area 262
  • layer 27 is the bottom layer. layer.
  • layer 25 is at the top
  • layer 26 is in the center
  • layer 27 is at the bottom, wherein the opaque area 251 of layer 25 will cover area 261 of layer 26 (as shown in FIG. 5 ).
  • the transparent or semi-transparent areas in the layer 25 have no effect on the display of the layers 26 and 27
  • the transparent or semi-transparent areas in the layer 26 have no effect on the display of the layer 27 .
  • the M first layers in this embodiment of the present application may also be four or more layers, which are a top layer, at least two middle layers, and a top layer, respectively.
  • layers coverage please refer to The description of the coverage of the above three layers is not limited in this embodiment of the present application.
  • the transparent area is a circle or a rectangle and the opaque area is a circle or a rectangle as an example for illustrative description.
  • the embodiments of the present application do not limit the The shape of transparent and opaque areas.
  • the embodiments of the present application do not limit the positions of the transparent areas and the opaque areas in the layer, and do not limit the sizes of the transparent areas and the opaque areas, which can be determined according to actual usage requirements, and are not limited in the embodiments of the present application.
  • the embodiment of the present application proposes: before reading the layer, it is possible to analyze whether there is a covered area in the layer, and the covered area is covered. Regions of pixels can be skipped without reading.
  • the layer before reading the layer, it can be determined whether there is a transparent area and/or a covered area in the layer. In actual implementation, there may be the following situations: (1) There is no transparent area in the layer , there is no covered area; or (2) there is a transparent area in the layer, but there is no covered area; or (3) there is a covered area in the layer, but there is no transparent area; or (4) the layer There are both transparent areas and covered areas. It is understandable that the top layer of multiple layers may have transparent areas, but there may be no covered areas; the middle layer or bottom layer of multiple layers may have transparent areas and may have covered areas.
  • the above S110 includes the following S111-S113.
  • S111 Determine the transparent area in the first layer of the top layer as the target area of the first layer of the top layer (referred to as the first target area).
  • S112 Determine the transparent area in the first layer of the middle layer and/or the area covered by the opaque area of the first layer of the top layer as the target area of the first layer of the middle layer (referred to as the second target area).
  • S113 Determine the transparent area in the bottom first layer, the area covered by the opaque area of the top first layer, and/or the area covered by the opaque area of the middle first layer as the target of the bottom first layer area (called the third target area).
  • this embodiment of the present application does not limit the execution order of the above S111, S112, and S113.
  • S111, S112, and S113 may be executed in sequence; or S111 and S112 may be executed simultaneously, and then S113 may be executed simultaneously; S112 and S113 may be specifically determined according to actual usage requirements, which are not limited in this embodiment of the present application.
  • the terminal device may Target area marking mask, the pixels in the area indicated by this mask will not be read.
  • whether the pixel is transparent may be determined according to the A component in the pixel data in the layer, and mask marking is performed for the transparent pixel in the layer or the area where the transparent pixel is located.
  • mask marking can be performed on the covered pixels in the layer or the area where the covered pixels are located.
  • the area marked with a mask may be referred to as a mask area.
  • the above-mentioned mask may be a string of binary codes to perform AND operation on the field corresponding to the pixel to mask the current field corresponding to the pixel.
  • the fields corresponding to the masked pixels will not be read. That is to say, the above-mentioned mask area can also be understood as a mask area, and the pixels in the mask area will not be read.
  • the mask is marked for that pixel so that it cannot be read.
  • the A component is 00 or 100%, a mask can be marked for the pixel so that the pixel will not be read.
  • the pixel in the lower position is marked with a mask so that it cannot be read.
  • a mask may be marked for the pixel located below the pixel, so that the pixel located below the pixel will not be read.
  • the transparent area and/covered area in the layer can be determined, and the transparent area and/covered area can be masked and marked, thereby Get the mask area.
  • the embodiment of the present application analyzes the coverage and/or transparency of the layer before reading the layer, and determines the data that cannot be read according to the coverage and/or transparency of the layer, so that when the layer is read, the data that cannot be read is determined. These masked areas can be skipped and not read to reduce read bandwidth and power consumption.
  • S120 Read the pixels in the M first layers except the target area to obtain M second layers.
  • the terminal device may read the unmarked mask in the M first layers.
  • the pixels in the image area marked with the mask in the M first layers may not be read. Since some pixels that contribute to the display effect are selected to be read when the layers are read, the total number of pixels in the M second layers obtained by reading is less than the total number of pixels in the M first layers.
  • the pixels in the transparent area will not be visible due to transparency, and will not contribute to the display effect when displayed, so when reading the layer, you can read the image.
  • Pixels in layers other than transparent areas without reading pixels in transparent areas of the layer which reduces read bandwidth and power consumption. For example, taking two layers as an example, layer 1 is the upper layer, and layer 2 is the lower layer. If there is a transparent layer in layer 1, when displaying the image obtained by superimposing these two layers, Pixels in the transparent area of layer 1 are invisible because they are transparent, so when reading layer 1, it is not necessary to read pixels in the transparent area of layer 1.
  • the pixels in the covered area will not be visible due to being covered, and will not contribute to the display effect when displayed, so when reading the layers, you can Reading pixels in a layer other than the covered area without reading pixels in the covered area of the layer reduces read bandwidth and power consumption.
  • the opaque layer in layer 1 will cover the lower layer layer 2.
  • the above describes the situation of first judging whether there is a transparent area in the layer, and then reading all or part of the pixels in the layer according to the judgment result.
  • the situation of reading all or part of the pixels in the layer is analyzed by combining the above two situations, that is, to determine whether there is a transparent area and/or a covered area in the layer, and then read the data in the layer according to the judgment result. All pixels or some pixels may exist in the following situations in actual implementation:
  • the transparent area in the layer can be skipped and not read; or, when the layer is read, the covered area in the layer can be skipped and not read. Read; or, when reading a layer, you can skip both the transparent area and the covered area in the layer. Which areas in a specific layer are selected to be skipped and not read can be determined according to actual usage requirements, which is not limited in this embodiment of the present application.
  • the above S120 includes the following S121-S123.
  • S121 Read the pixels in the first layer on the top layer except the first target area (ie, the transparent area in the first layer) to obtain the second layer on the top layer.
  • the first target area ie, the transparent area in the first layer
  • S122 read the pixels in the first layer of the middle layer except the second target area (that is, the transparent area in the first layer of the middle layer and/or the area covered by the opaque area in the first layer of the top layer), and obtain the middle layer Second layer.
  • the second target area that is, the transparent area in the first layer of the middle layer and/or the area covered by the opaque area in the first layer of the top layer
  • S123 Read the first layer of the bottom layer except the third target area (that is, the transparent area in the first layer of the bottom layer, the area covered by the opaque area of the first layer of the top layer and/or the opaque area of the first layer in the middle Pixels outside the area covered by the area) get the bottom second layer.
  • the third target area that is, the transparent area in the first layer of the bottom layer, the area covered by the opaque area of the first layer of the top layer and/or the opaque area of the first layer in the middle Pixels outside the area covered by the area
  • the above-mentioned M second layers include a top second layer, a middle layer second layer, and a bottom second layer. Moreover, according to the upper and lower hierarchical relationships of the M first layers, the upper and lower hierarchical relationships of the M second layers can be determined.
  • this embodiment of the present application does not limit the execution order of the above S121, S122 and S123.
  • S121, S122 and S123 may be executed in sequence; or S121 and S122 may be executed at the same time first, and then S123 may be executed; S122 and S123 may be specifically determined according to actual usage requirements, which are not limited in this embodiment of the present application.
  • the pixels in the image regions that are not marked with masks in the M first layers can be read without reading the pixels marked with masks in the M first layers.
  • the pixels in the image area of the code are read to obtain M second layers with an upper and lower hierarchical relationship.
  • the terminal device can superimpose the M second layers according to the upper-lower hierarchical relationship to obtain the target image. Further, the terminal device may display the target image on the display screen.
  • the read bandwidth can be reduced by the solution provided by the present application.
  • the read bandwidth can be reduced by the solution provided by the present application.
  • the layer before reading the layer, it is judged whether the layer has a covered area and/or a fully transparent area. If there is a covered area and/or a fully transparent area in the layer to be read, Then, when the layer is read, the covered area and/or the fully transparent area may not be read, so that the reading bandwidth can be reduced, thereby reducing power consumption.
  • FIG. 8 is a schematic block diagram of an image display principle.
  • the image display principle is exemplarily described below with reference to FIG. 8 , and the method for processing a multi-layer image provided by an embodiment of the present application will be described in conjunction with the image display principle.
  • a central processing unit (CPU) 41 and a graphics processing unit (GPU) 42 are connected through a bus 43
  • a display sub-system (DSS) 44 includes a display memory 441 , a display controller 442 and a display screen 443 .
  • the bitmap output by the CPU 41 can be uploaded to the GPU 42 via the bus 43, and the GPU 42 performs layer rendering and texture synthesis on the bitmap after acquiring the bitmap, and then puts the rendered result into the display memory 441, and the display controller 442
  • the screen display content (eg, multiple layers) is extracted from the display memory 441 at a specified time according to the vertical synchronization signal, and then displayed on the display screen 443 (ie, the mobile phone screen).
  • the GPU when the program is running, the GPU performs corresponding processing on the program running process and results according to the instructions and related data provided by the CPU, and converts them into text and image display signals that the display can accept. Specifically, firstly, M first layers are obtained by drawing on the GPU, then the plurality of layer data is written into the display memory, and then the plurality of layer data is read from the display memory, and displayed on the display.
  • the above-mentioned display memory is also called a frame buffer, a frame buffer or a video memory, and is used for storing rendering data that has been processed by the GPU or is about to be extracted.
  • the method 100 for processing a multi-layer image provided by the embodiment of the present application further includes the following S140 .
  • M first layers are obtained by drawing on the GPU, and the M first layers have an upper-lower hierarchy relationship.
  • the CPU issues instructions to the GPU
  • the GPU draws to obtain multiple layers
  • the multiple layer data into the memory.
  • the method 100 for processing a multi-layer image provided by this embodiment of the present application may further include the following S150 and S160 .
  • S150 Acquire pixel transparency information of the M first layers according to the pixel data of the M first layers.
  • the terminal device may divide each of the M first layers into N tiles (N is greater than 1) Integer), and then traverse all pixel data in each tile, and then obtain the pixel transparency information corresponding to each tile. Further, the terminal device may compress each block in the M first layers and the corresponding pixel transparency information and write it into the memory. Still further, pixels other than the transparent area and/or the covered area in the M first layers may be read from the memory to obtain M second layers (see S121 in FIG. 9 ).
  • the above-mentioned memory may be a double data rate synchronous dynamic random access memory (double data rate synchronous dynamic random access memory), abbreviated as DDR.
  • DDR double data rate synchronous dynamic random access memory
  • This application uses hardware to prejudge the layer transparency and coverage properties before layer stacking, and determines the transparent area and/or covered area in the layer according to the layer transparency and coverage properties. Or the covered area can be skipped without reading, thereby reducing the layer reading bandwidth and display power consumption.
  • the fields corresponding to each tile in the above-mentioned M first layers may include a header field and a data field.
  • the header field and data field corresponding to each tile in the M first layers can be written into the memory, so that each tile in the M first layers and the corresponding pixel transparency information can be compressed and written. into memory.
  • the data field corresponding to each tile may include pixel values of all pixels in each tile, and for the content in the header field corresponding to each tile, the present application provides the following two possible implementations .
  • the header field corresponding to each tile may include transparency information of all pixels in each tile.
  • the header field corresponding to tile 1 includes transparency information of all pixels in tile 1 .
  • the header field corresponding to each tile may include transparency information of a part of pixels in each tile, and the part of pixels is located in a transparent area and/or an opaque area. Since the information for determining the transparent area and/or the covered area of the layer only needs to be stored in the header field, information redundancy can be reduced.
  • the header field corresponding to the tile 1 includes the transparency information of the pixels in the transparent area and/or the opaque area in the tile 1, for example, the header field includes the following indication information of a specific pixel: pixel 1 corresponds to 00 or 100%, or some other flag that means the pixel is transparent; pixel 2 corresponds to FF or 0%, or some other flag that means the pixel is opaque.
  • the headers corresponding to the N tiles in each of the M first layers can be Part fields and data fields that determine the transparent and/or covered areas of each first layer.
  • a compression algorithm in the process of writing the layer into the memory after the GPU draws the layer, in order to reduce the bandwidth, a compression algorithm is used, and the compression algorithm traverses all pixel data in each block of the layer.
  • the function of statistic on the A component can be added in the compression process, and the statistic result can be stored in the memory in the form of header data (that is, the above-mentioned header field).
  • DSS When DSS sends the S-th frame (representing the previous frame), after the GPU draws the S+1-th frame (representing the next frame), DSS can display the headers of the blocks of each layer in the S+1-th frame
  • the data is analyzed to obtain the transparency or coverage of the entire layer, and when the S+1 frame is displayed, the content of the transparent area of each layer in the S+1 frame and/or the content covered by other layers is skipped. Do not read, thus saving bandwidth.
  • the layer is compressed after the layer is drawn by the GPU, and an identifier may be used to perform statistics on the A component of each pixel in each block during compression.
  • a 2-bit flag (flag) can be used to mark the statistical result: if the A component is 00, the flag 1 is used in the header data to indicate that the A component is all 00; if the A component is all FF, then the header Mark 2 is used in the data to indicate that A is all FF. Then, the header data containing the identification information of each block is written into the memory, so as to facilitate the identification of the statistical results.
  • the first stage when the DSS sends the S-th frame, after the GPU draws the S+1-th frame, the software configures the DSS to enter the background analysis process to detect the identifier in the header field of the S+1-th frame information, after the detection is completed, the software calculates the coordinates of the mask area (such as the transparent area and/or covered area) of each layer of the S+1 frame.
  • a hardware composer (hardware composer, HWC) can be used to perform layer composition on each layer of the S+1 frame.
  • the second stage when the DSS sends and displays the S+1 frame, the mask area that does not need to be read can be skipped according to the coordinates of the mask area of each layer to save bandwidth.
  • the reading and display of the subsequent S+2 frame, S+3 frame, etc. are similar to the reading and display of the S+1 frame, which will not be repeated here.
  • the layer transparency information is counted at the GPU of the drawing, and the multi-layer and its transparency information are written into the memory.
  • the DSS background is used to analyze the coverage and coverage of each layer in the frame of image. / or transparent case. Then, when the frame image is read, the covered area and/or the fully transparent area in the layer can be skipped according to the analysis result of the layer coverage and/or transparency, thereby reducing the read bandwidth and power consumption.
  • the method for processing a multi-layer image can determine the target area of each first layer in the M first layers according to the pixel transparency information of the M first layers and the relationship between the upper and lower layers.
  • the target area includes a transparent area and/or a covered area (that is, the area covered by the opaque area of the upper layer); then read the pixels in the M first layers except the target area to obtain M second images layer; and then displaying an image obtained by superimposing M second layers, the total number of pixels in the M second layers is less than the total number of pixels in the M first layers.
  • the transparency and/or coverage of the layers can be analyzed according to the pixel transparency components in the multiple layers and the relationship between the upper and lower layers of the layers, so as to determine the transparent area and/or coverage of the layers. /covered area. Since the transparent area and/or covered area do not contribute to the display effect when displayed, the content of these areas can be skipped and not read, and then select to read the content in the layer that contributes to the display effect when reading the layer. These transparent areas and/or covered areas are skipped and not read, which can reduce read bandwidth and power consumption.
  • the methods and operations implemented by the terminal device in the foregoing method embodiments may also be implemented by components (for example, chips or circuits) that can be used in the terminal device.
  • the terminal device implementing the method includes corresponding hardware structures and/or software modules for executing each function.
  • the present application can be implemented in hardware or a combination of hardware and computer software with the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein. Whether a function is performed by hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Skilled artisans may use different methods to implement the described functions for each particular application, but such implementations should not be considered outside the scope of protection of this application.
  • the terminal device may be divided into functional modules according to the foregoing method examples.
  • each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module.
  • the above-mentioned integrated modules can be implemented in the form of hardware, and can also be implemented in the form of software function modules. It should be noted that the division of modules in the embodiments of the present application is illustrative, and is only a logical function division, and other feasible division manners may be used in actual implementation. The following description will be given by taking as an example that each function module is divided corresponding to each function.
  • FIG. 11 is a schematic block diagram of a media data processing apparatus 800 provided by an embodiment of the present application.
  • the apparatus 800 may be used to perform the actions performed by the terminal device in the above method embodiments.
  • the apparatus 800 includes a processing unit 810 , a reading unit 820 and a display unit 830 .
  • the processing unit 810 is configured to determine the target area of each first layer in the M first layers according to the pixel transparency information of the M first layers and the relationship between the upper and lower layers, where the target area includes a transparent area and/or covered area;
  • the reading unit 820 is configured to read the pixels other than the target area in the above-mentioned M first layers to obtain M second layers, and the total number of pixels in the M second layers is less than the M the total number of pixels in the first layer;
  • a display unit 830 configured to display the images obtained by superimposing the above-mentioned M second layers
  • the covered area is an area covered by the opaque area of the upper layer, the pixel transparency information corresponding to the pixels in the opaque area indicates that the pixel is opaque, and the pixel transparency information corresponding to the pixels in the transparent area indicates that the pixel is transparent, and M is Integer greater than 1.
  • the processing unit 810 is specifically configured to:
  • the reading unit 820 is specifically used to:
  • the M second layers include the top second layer, the middle second layer, and the bottom second layer.
  • the processing unit 810 is further configured to, after determining the target area of each of the above-mentioned M first layers, Target area marking mask, the pixels in the area indicated by the mask are not allowed to be read;
  • the reading unit 820 is specifically configured to read the pixels in the image areas not marked with masks in the above-mentioned M first layers, and not read the pixels in the image areas marked with masks in the above-mentioned M first layers .
  • the processing unit 810 is further configured to obtain the above-mentioned M first layers by drawing through the image processor GPU before determining the target area of each of the above-mentioned M first layers, the The M first layers have an upper-lower hierarchy relationship.
  • the processing unit 810 is further configured to obtain the pixel transparency of the M first layers according to the pixel data of the M first layers after the M first layers are obtained by drawing on the GPU information; and the above-mentioned M first layers and the above-mentioned pixel transparency information are written into the memory;
  • the reading unit 820 is specifically configured to read the pixels other than the target area in the above-mentioned M first layers from the above-mentioned memory.
  • processing unit 810 is specifically configured to:
  • Each block in the above-mentioned M first layers and the corresponding pixel transparency information are compressed and written into the above-mentioned memory.
  • a field corresponding to each tile in the above-mentioned M first layers includes a header field and a data field
  • the header field corresponding to each tile includes a header field in each tile
  • Transparency information of all pixels or part of pixels the part of pixels is located in the above-mentioned transparent area and/or opaque area
  • the data field corresponding to each tile includes pixel values of all pixels in each tile
  • the processing unit 810 is specifically configured to write the header field and data field corresponding to each tile in the above-mentioned M first layers into the above-mentioned memory; and according to each first layer in the above-mentioned M first layers The respective corresponding header fields and data fields of the N blocks in the above determine the target area of each first layer.
  • the above-mentioned M first layers are images in the RGBA or ARGB data format, wherein R, G, and B respectively represent the color components of the pixels, and A represents the transparency components of the pixels.
  • the processing unit 810 is further configured to determine the upper and lower hierarchical relationships of the M second layers according to the upper and lower hierarchical relationships of the M first layers;
  • the display unit 830 is specifically configured to superimpose the M second layers according to the upper and lower hierarchical relationship of the M second layers to obtain a target image; and display the target image on the display screen of the device 800 .
  • An embodiment of the present application provides an apparatus for processing multi-layer images, which can determine the target area of each first layer in the M first layers according to the pixel transparency information of the M first layers and the relationship between the upper and lower layers,
  • the target area includes a transparent area and/or a covered area (that is, the area covered by the opaque area of the upper layer layer); and the device reads the M pixels in the first layer except the target area, and obtains M pixels second layer; then the apparatus displays an image obtained by superimposing M second layers, and the total number of pixels in the M second layers is less than the total number of pixels in the M first layers.
  • the transparency and/or coverage of the layers can be analyzed according to the pixel transparency components in the multiple layers and the relationship between the upper and lower layers of the layers, so as to determine the transparent area and/or coverage of the layers. /covered area. Since the transparent area and/covered area do not contribute to the display effect when displayed, the content of these areas can be skipped and not read, that is, when reading the layer, select to read the content in the layer that contributes to the display effect, These transparent areas and/or covered areas are skipped and not read, which can reduce the read bandwidth and power consumption.
  • the apparatus 800 may correspond to executing the methods described in the embodiments of the present application, and the above-mentioned and other operations and/or functions of the units in the apparatus 800 are respectively to implement the corresponding processes of the methods, and are not described herein for the sake of brevity. Repeat.
  • FIG. 12 is a schematic structural diagram of a terminal device 900 provided by an embodiment of the present application.
  • the terminal device 900 includes: a processor 910 , a memory 920 , a communication interface 930 , and a bus 940 .
  • the processor 910 can be connected with the memory 920 .
  • the memory 920 may be used to store the program codes and data. Therefore, the memory 920 may be a storage unit within the processor 910 , or may be an external storage unit independent of the processor 910 , or may include a storage unit within the processor 910 and an external storage unit independent of the processor 910 . part.
  • the processor 910 in the terminal device 900 shown in FIG. 12 may correspond to the processing unit 810 in the apparatus 800 in FIG. 11 .
  • the terminal device 900 may further include a bus 940 .
  • the memory 920 and the communication interface 930 may be connected to the processor 910 through the bus 940 .
  • the bus 940 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus or the like.
  • PCI peripheral component interconnect
  • EISA extended industry standard architecture
  • the bus 940 can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one line is shown in FIG. 12, but it does not mean that there is only one bus or one type of bus.
  • the processor 910 may adopt a central processing unit (central processing unit, CPU).
  • the processor may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), off-the-shelf programmable gate arrays (FPGAs) or other Programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • DSPs digital signal processors
  • ASICs application specific integrated circuits
  • FPGAs off-the-shelf programmable gate arrays
  • a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
  • the processor 810 uses one or more integrated circuits to execute related programs, so as to implement the technical solutions provided by the embodiments of the present application.
  • the memory 920 which may include read-only memory and random access memory, provides instructions and data to the processor 910 .
  • a portion of processor 910 may also include non-volatile random access memory.
  • the processor 910 may also store device type information.
  • the processor 910 executes the computer-executed instructions in the memory 920 to perform the operation steps of the above method.
  • terminal device 900 may correspond to the apparatus 800 in the embodiment of the present application, and the above-mentioned and other operations and/or functions of each unit in the apparatus 800 are used to implement the corresponding flow of the method, for the sake of brevity , and will not be repeated here.
  • the embodiments of the present application further provide a computer-readable medium, where the computer-readable medium stores program codes, and when the computer program codes are executed on a computer, the computer executes the program code.
  • the computer-readable medium stores program codes, and when the computer program codes are executed on a computer, the computer executes the program code.
  • the embodiments of the present application further provide a computer program product, where the computer program product includes computer program code, and when the computer program code runs on a computer, causes the computer to execute each of the above method in aspect.
  • the embodiments of the present application do not specifically limit the specific structure of the execution body of the methods provided by the embodiments of the present application, as long as the program in which the codes of the methods provided by the embodiments of the present application are recorded can be executed to execute the methods according to the embodiments of the present application.
  • the layer image can be processed.
  • the execution body of the method provided by the embodiment of the present application may be a terminal device, or a functional module in the terminal device that can call a program and execute the program.
  • Computer readable media may include, but are not limited to, magnetic storage devices (eg, hard disks, floppy disks, or magnetic tapes, etc.), optical disks (eg, compact discs (CDs), digital versatile discs (DVDs), etc. ), smart cards and flash memory devices (eg, erasable programmable read-only memory (EPROM), cards, stick or key drives, etc.).
  • magnetic storage devices eg, hard disks, floppy disks, or magnetic tapes, etc.
  • optical disks eg, compact discs (CDs), digital versatile discs (DVDs), etc.
  • smart cards and flash memory devices eg, erasable programmable read-only memory (EPROM), cards, stick or key drives, etc.
  • Various storage media described herein may represent one or more devices and/or other machine-readable media for storing information.
  • the term "machine-readable medium” may include, but is not limited to, wireless channels and various other media capable of storing, containing, and/or carrying instructions and/or data.
  • processors mentioned in the embodiments of the present application may be a CPU, and may also be other general-purpose processors, digital signal processors (digital signal processors, DSPs), application specific integrated circuits (application specific integrated circuits, ASICs), ready-made Field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • DSPs digital signal processors
  • ASICs application specific integrated circuits
  • FPGA Field programmable gate array
  • a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
  • the memory mentioned in the embodiments of the present application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically programmable Erase programmable read-only memory (electrically EPROM, EEPROM) or flash memory.
  • Volatile memory may be random access memory (RAM).
  • RAM can be used as an external cache.
  • RAM may include the following forms: static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM) , double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchronous link dynamic random access memory (synchlink DRAM, SLDRAM) and Direct memory bus random access memory (direct rambus RAM, DR RAM).
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • SDRAM synchronous dynamic random access memory
  • SDRAM double data rate synchronous dynamic random access memory
  • ESDRAM enhanced synchronous dynamic random access memory
  • SLDRAM synchronous link dynamic random access memory
  • Direct memory bus random access memory direct rambus RAM, DR RAM
  • the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components
  • the memory storage module
  • memory described herein is intended to include, but not be limited to, these and any other suitable types of memory.
  • the disclosed system, apparatus and method may be implemented in other manners.
  • the apparatus embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, which may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the functions, if implemented in the form of software functional units and sold or used as independent products, may be stored in a computer-readable storage medium.
  • the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution can be embodied in the form of a computer software product, and the computer software product is stored in a storage
  • the computer software product includes several instructions, the instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage medium may include, but is not limited to, various media that can store program codes, such as a U disk, a removable hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

Abstract

本申请提供了一种处理多图层图像的方法、装置及终端设备，涉及图像处理技术领域。通过本申请方案，在读取图层之前，可以先根据多个图层中的像素透明度分量以及图层上下层级关系，分析图层的透明和/或覆盖情况，确定图层中的透明区域和/被覆盖区域。由于透明区域和/被覆盖区域在显示时对于显示效果没有贡献，因此这些区域的内容可以跳过不读，进而在读取图层时选择读取图层中对显示效果有贡献的内容，将这些透明区域和/被覆盖区域跳过不读，如此可以减小读取带宽，降低功耗。

Description

处理多图层图像的方法、装置及终端设备 技术领域
本申请涉及图像处理技术领域，尤其涉及一种处理多图层图像的方法、装置及终端设备。
背景技术
随着终端技术的发展，手机的显示屏越来越大，手机安装的应用程序(application，APP)越来越丰富，使用功能越来越多样化，例如可以在显示屏上分屏显示多个APP窗口。在多窗口显示的场景中，多个APP窗口实际上是由多个图层叠加而成。此外，对于单个APP而言，其显示内容也可能是由多个图层叠加而成。
然而，图层越多，显存读取带宽越大，功耗也越大。当显示器的刷新率较高(例如120Hz)时，大量的图层会导致显示器的升压提频，造成显存读取带宽的增加及功耗的上升，从而影响用户体验。
发明内容
本申请提供一种处理多图层图像的方法、装置及终端设备，解决了现有技术中在待显示图像包括大量图层的情况下显存读取带宽和功耗较大的问题。
为达到上述目的，本申请采用如下技术方案：
第一方面，本申请提供一种处理多图层图像的方法，该方法包括：根据M个第一图层的像素透明度信息和上下层级关系，确定M个第一图层中每个第一图层的目标区域，该目标区域包括透明区域和/或被覆盖区域；并且读取M个第一图层中除该目标区域之外的像素，得到M个第二图层；然后显示M个第二图层叠加得到的图像，该M个第二图层中的像素的总数量小于M个第一图层中的像素的总数量。
其中，上述被覆盖区域为被上层图层的不透明区域覆盖的区域，该不透明区域中的像素对应的像素透明度信息指示像素不透明，该透明区域中的像素对应的像素透明度信息指示像素透明，M为大于1的整数。
通过上述方案，在读取图层之前，可以先根据多个图层中的像素透明度分量以及图层上下层级关系，分析图层的透明和/或覆盖情况，确定图层中的透明区域和/被覆盖区域。由于透明区域和/被覆盖区域在显示时对于显示效果没有贡献，因此这些区域的内容可以跳过不读，由此在读取图层时选择读取图层中对显示效果有贡献的内容，将这些透明区域和/被覆盖区域跳过不读，如此可以减小读取带宽，降低功耗。
在一些可能实施例中，在所述M个第一图层包括顶层第一图层、中层第一图层和底层第一图层的情况下，所述根据M个第一图层的像素透明度信息和上下层级关系，确定所述M个第一图层中每个第一图层的目标区域，包括：
将所述顶层第一图层中的透明区域，确定为所述顶层第一图层的第一目标区域；
将所述中层第一图层中的透明区域和/或被所述顶层第一图层中的不透明区域覆盖的区域，确定为所述中层第一图层的第二目标区域；
将所述底层第一图层中的透明区域、被所述顶层第一图层的不透明区域覆盖的区域和/或被所述中间第一图层的不透明区域覆盖的区域，确定为所述底层第一图层的第三目标区域。
在一些可能实施例中，所述读取所述M个第一图层中除所述目标区域之外的像素，得到M个第二图层，包括：
读取所述顶层第一图层中除所述第一目标区域之外的像素，得到顶层第二图层；
读取所述中层第一图层中除所述第二目标区域之外的像素，得到中层第二图层；
读取所述底层第一图层中除所述第三目标区域之外的像素，得到底层第二图层。
其中，所述M个第二图层包括所述顶层第二图层、所述中层第二图层和所述底层第二图层。
可选的，在读取图层之前，可以判断图层中是否存在透明区域和/或被覆盖区域，在实际实现时可能存在如下几种情况：(1)图层中不存在透明区域，也不存在被覆盖区域；或者(2)图层中存在透明区域，而不存在被覆盖区域；或者(3)图层中存在被覆盖区域，而不存在透明区域；或者(4)图层中既存在透明区域，也存在被覆盖区域。可以理解，多个图层中的顶层图层可能存在透明区域，但是不存在被覆盖区域；多个图层中的中层图层或底层图层可能存在透明区域，并且可能存在被覆盖区域。
一方面，由于透明区域中的像素为透明的，因此在显示多图层图像时，透明区域中的像素会由于透明而不可见，也就是说，透明区域中的像素在显示时对于显示效果没有贡献，因此本申请实施例提出：在读取图层之前，可以先分析图层中是否存在透明区域，透明区域的像素可以跳过不读。
另一方面，由于被覆盖区域被上层图层的不透明区域覆盖，即该被覆盖区域中的像素被上层图层的不透明区域覆盖，因此在显示多图层图像时，被覆盖区域中的像素会由于被覆盖而不可见，也就是说，被覆盖区域中的像素在显示时对于显示效果没有贡献，因此本申请实施例提出：在读取图层之前，可以先分析图层中是否存在被覆盖区域，被覆盖区域的像素可以跳过不读。
在一些可能实施例中，在所述确定所述M个第一图层中每个第一图层的目标区域之后，所述读取所述M个第一图层中除所述目标区域之外的像素之前，所述方法还包括：在所述M个第一图层中每个第一图层的目标区域标记掩码，所述掩码指示的区域中的像素不允许被读取。
在此情况下，所述读取所述M个第一图层中除所述目标区域之外的像素，包括：读取所述M个第一图层中未标记所述掩码的图像区域中的像素；并且不读取所述M个第一图层中标记所述掩码的图像区域中的像素。
在一些实施例中，可以根据图层中像素数据中的A分量，判断像素是否透明，并且针对图层中透明像素或者该透明像素所在区域进行掩码标记。可以将标记有掩码的区域称为掩码区域。或者，可以针对图层中被覆盖像素或者该被覆盖像素所在区域进行掩码标记。为了便于描述，可以将标记有掩码的区域称为掩码区域。
一方面，若A分量指示像素透明，则对该像素标记掩码，使其不会被读取。另一方面，若A分量指示像素不透明，该像素会覆盖位于下方位置的像素，则对位于下方位置的像素标记掩码，使其不会被读取。
可选的，上述掩码可以是一串二进制代码对像素对应字段进行与运算，屏蔽当前的该像素对应字段。在读取图层的场景中，对于屏蔽后的像素对应字段，将不会被读取。也就是说，上述掩码区域也可以理解为屏蔽区域，该屏蔽区域中的像素不会被读取。
这样，通过分析多个图层中的像素透明度分量以及图层上下层级关系，可以确定图层中的透明区域和/被覆盖区域，并对该透明区域和/被覆盖区域进行掩码标记，从而得到掩码区域。进一步地，终端设备可以读取M个第一图层中未标记掩码的图像区域中的像素，此时可以不读取该M个第一图层中标记有掩码的图像区域中的像素。由于在读取图层时选择读取对显示效果有贡献的部分像素，因此读取得到的M个第二图层中的像素的总数量小于M个第一图层中的像素的总数量。
如此，本申请实施例通过在读取图层之前先分析图层的覆盖和/或透明情况，根据图层覆盖和/或透明情况，确定可跳过不读的数据，从而在读取图层时可以将这些掩码区域跳过不读，以降低读取带宽和功耗。
在一些可能实施例中，在所述确定所述M个第一图层中每个第一图层的目标区域之前，所述方法还包括：通过图像处理器GPU绘制得到所述M个第一图层，所述M个第一图层具有所述上下层级关系。
其中，GPU在程序运行时根据CPU提供的指令和有关数据，将程序运行过程和结果进行相应的处理并转换成显示器能够接受的文字和图像显示信号。具体地，先通过GPU绘制得到M个第一图层，然后将该多个图层数据写入存储器，再从该存储器中读取多个图层数据，并通过显示器显示出来。
在一些可能实施例中，在所述通过GPU绘制得到所述M个第一图层之后，所述方法还包括：根据所述M个第一图层的像素数据，获取所述M个第一图层的像素透明度信息；将所述M个第一图层和所述像素透明度信息写入存储器。
在此情况下，所述读取所述M个第一图层中除所述目标区域之外的像素，包括：从所述存储器读取所述M个第一图层中除所述目标区域之外的像素。
本申请采用硬件在图层叠加前预判图层透明及覆盖属性，根据图层透明及覆盖属性确定图层中的透明区域和/或被覆盖区域，在读取图层时对于透明区域和/或被覆盖区域可以跳过不读，从而降低图层读取带宽，降低显示功耗。
在一些可能实施例中，所述获取所述M个第一图层的像素透明度信息，包括：将所述M个第一图层中的每个第一图层划分成N个图块，N为大于1的整数；遍历每个图块中的所有像素数据，获取所述每个图块对应的像素透明度信息。
在此情况下，所述将所述M个第一图层和所述像素透明度信息写入存储器，包括：将所述M个第一图层中的每个图块以及对应的像素透明度信息压缩后写入所述存储器。
可选的，在GPU绘制图层之后对图层进行压缩，压缩时可以采用标识对各分块内的各像素A分量进行统计。
通过本方案，在GPU绘制图层结束，将图层写入存储器的过程中，为了降低带宽，会使用压缩算法，压缩算法会遍历图层各分块内的所有像素数据。利用该功能，可以在压缩过程中增加对透明度分量统计的功能，并将统计结果以头部数据(即上述头部字段)的形式存入存储器。在从存储器读取图层的过程中，将各图层的透明区域的内 容和/或被其他图层覆盖的内容跳过不读，从而节省带宽。
在一些可能实施例中，所述M个第一图层中的每个图块对应的字段包括头部字段和数据字段，所述每个图块对应的头部字段包括所述每个图块中的所有像素或者部分像素的透明度信息，所述部分像素位于所述透明区域中和/或所述不透明区域，所述每个图块对应的数据字段包括所述每个图块中的所有像素的像素值。
在此情况下，所述将所述M个第一图层中的每个图块以及对应的像素透明度信息压缩后写入所述存储器，包括：将所述M个第一图层中的每个图块对应的头部字段和数据字段写入所述存储器。
在此情况下，所述根据M个第一图层的像素透明度信息和上下层级关系，确定所述M个第一图层中每个第一图层的目标区域，包括：根据所述M个第一图层中每个第一图层中的N个图块各自对应的头部字段和数据字段，确定所述每个第一图层的目标区域。
在一些可能实施例中，所述M个第一图层为采用RGBA或者ARGB数据格式的图像，其中R、G和B分别代表像素的颜色分量，A代表像素的透明度分量。
在一些可能实施例中，所述显示所述M个第二图层叠加得到的图像，包括：根据所述M个第一图层的上下层级关系，确定所述M个第二图层的上下层级关系；按照所述M个第二图层的上下层级关系叠加所述M个第二图层，得到目标图像；在显示屏上显示所述目标图像。
第二方面，本申请提供一种处理多图层图像的装置，该装置包括用于执行上述第一方面中的方法的单元。该装置可对应于执行上述第一方面中描述的方法，该装置中的单元的相关描述请参照上述第一方面的描述，为了简洁，在此不再赘述。
其中，上述第一方面描述的方法可以通过硬件实现，也可以通过硬件执行相应的软件实现。硬件或软件包括一个或多个与上述功能相对应的模块或单元，例如处理模块或单元、读取模块或单元、显示模块或单元等。
第三方面，本申请提供一种终端设备，所述终端设备包括处理器，处理器与存储器耦合，存储器用于存储计算机程序或指令，处理器用于执行存储器存储的计算机程序或指令，使得第一方面中的方法被执行。
例如，处理器用于执行存储器存储的计算机程序或指令，使得终端设备执行第一方面中的方法。
第四方面，本申请提供一种计算机可读存储介质，其上存储有用于实现第一方面中的方法的计算机程序(也可称为指令或代码)。
例如，该计算机程序被计算机执行时，使得该计算机可以执行第一方面中的方法。
第五方面，本申请提供一种芯片，包括处理器。处理器用于读取并执行存储器中存储的计算机程序，以执行第一方面及其任意可能的实现方式中的方法。
可选地，所述芯片还包括存储器，存储器与处理器通过电路或电线连接。
第六方面，本申请提供一种芯片系统，包括处理器。处理器用于读取并执行存储器中存储的计算机程序，以执行第一方面及其任意可能的实现方式中的方法。
可选地，所述芯片系统还包括存储器，存储器与处理器通过电路或电线连接。
第七方面，本申请提供一种计算机程序产品，所述计算机程序产品包括计算机程 序(也可称为指令或代码)，所述计算机程序被计算机执行时使得所述计算机实现第一方面中的方法。
可以理解的是，上述第二方面至第七方面的有益效果可以参见上述第一方面中的相关描述，在此不再赘述。
附图说明
图1为本申请实施例提供的处理多图层图像的方法应用的操作系统的架构示意图；
图2为本申请实施例提供的处理多图层图像的方法的流程示意图之一；
图3为本申请实施例提供的处理多图层图像的方法中确定图层透明区域的示意图；
图4为本申请实施例提供的处理多图层图像的方法中确定图层被覆盖区域的示意图之一；
图5为本申请实施例提供的处理多图层图像的方法中确定图层被覆盖区域的示意图之二；
图6为本申请实施例提供的处理多图层图像的方法应用于包含全透明图层的多图层图像的示意图；
图7为本申请实施例提供的处理多图层图像的方法应用于包含不透明图层的多图层图像的示意图；
图8为本申请实施例提供的处理多图层图像的方法所适用的图像显示原理的示意框图；
图9为本申请实施例提供的处理多图层图像的方法的流程示意图之二；
图10为本申请实施例提供的处理多图层图像的方法在处理连续多帧图像时的示意框图；
图11为本申请实施例提供的处理多图层图像的装置的结构示意图；
图12为本申请实施例提供的终端设备的结构示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本文中术语“和/或”，是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。本文中符号“/”表示关联对象是或者的关系，例如A/B表示A或者B。
本文中的说明书和权利要求书中的术语“第一”和“第二”等是用于区别不同的对象，而不是用于描述对象的特定顺序。例如，第一图层和第二图层等是用于区别不同的图层，而不是用于描述图层的特定顺序。
在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
在本申请实施例的描述中，除非另有说明，“多个”的含义是指两个或者两个以上，例如，多个处理单元是指两个或者两个以上的处理单元等；多个元件是指两个或者两个以上的元件等。
随着终端技术的发展，手机安装的APP越来越丰富，使用功能越来越多样化，例如可以在显示屏上分屏显示多个APP窗口。在多窗口显示的场景中，多个APP窗口实际上是由多个图层叠加而成。此外，对于单个APP而言，其显示内容也可能是由多个图层叠加而成。然而，图层越多，显存读取带宽越大，功耗也越大。其中，带宽用于表征信号传输的数据传输能力、单位时间内通过链路的数据量，以及显示器的显示能力。当显示器的刷新率提高时，对显示器的带宽的需求会增大。在实际实现时，当显示器的刷新率较高(例如120Hz)时，大量的图层会导致显示器的升压提频，造成显存读取带宽的增加及功耗的上升，从而影响用户体验。
举例来说，显示器的显示屏通常采用命令模式(command mode)和视频模式(video mode)。对于采用命令模式的显示屏，可以采用局部刷新的方法降低带宽，但成本较高。为了降低成本，可使用较低成本的视频模式的显示屏。对于视频模式的显示屏，如果显示内容为静止画面，可以将多个图层进行叠加得到的单图层发送给显示屏进行显示(简称为送显)，可以降低带宽和功耗。但是，当显示内容为非静止画面(即动态图像)时，对于非静止画面的多图层叠加的场景，视频模式的显示屏仍面临带宽和功耗较大的压力。也就是说，针对视频模式的显示屏，在显示非静止画面时出现的多图层叠加场景，如果使用较高的刷新帧率，会出现非常高的数据带宽，有时会引起显存升压，带来很高的功耗，从而引起终端设备发热现象，影响用户体验。
针对上述场景，本申请实施例提供一种处理多图层图像的方法、装置及终端设备，可以根据M个第一图层的像素透明度信息和上下层级关系，确定M个第一图层中每个第一图层的目标区域，该目标区域包括透明区域和/或被覆盖区域(即被上层图层的不透明区域覆盖的区域)；然后读取M个第一图层中除该目标区域之外的像素，得到M个第二图层；然后显示M个第二图层叠加得到的图像，该M个第二图层中的像素的总数量小于M个第一图层中的像素的总数量。
通过本申请方案，在读取图层之前，可以先根据多个图层中的像素透明度分量以及图层上下层级关系，分析图层的透明和/或覆盖情况，确定图层中的透明区域和/被覆盖区域。由于透明区域和/被覆盖区域在显示时对于显示效果没有贡献，因此这些区域的内容可以跳过不读，即在读取图层时选择读取该图层中对显示效果有贡献的内容，将这些透明区域和/被覆盖区域跳过不读，如此可以减小读取带宽，降低功耗。
在本申请实施例中，终端设备包括硬件层、运行在硬件层之上的操作系统层，以及运行在操作系统层上的应用层。其中，硬件层可以包括中央处理器(central processing unit，CPU)、内存管理单元(memory management unit，MMU)和内存(也称为主存)等硬件。操作系统层的操作系统可以是任意一种或多种通过进程(process)实现业务处理的计算机操作系统，例如，Linux操作系统、Unix操作系统、Android操作系统、iOS操作系统或windows操作系统等，还可以为其他可能的操作系统，本申请实施例不作具体限定。应用层可以包含视频播放器，浏览器、通讯录、文字处理软件、即时通信软件等应用。
下面以安卓操作系统为例，介绍一下本申请实施例提供的媒体数据处理方法所应用的软件环境。
如图1所示，为本申请实施例提供的一种可能的安卓操作系统的架构示意图。在图1中，安卓操作系统的架构包括4层，分别为：应用程序层、应用程序框架层、系统运行库层和内核层(具体可以为Linux内核层)。
其中，应用程序层包括安卓操作系统中的各个应用程序(包括系统应用程序和第三方应用程序)。
应用程序框架层是应用程序的框架，开发人员可以在遵守应用程序的框架的开发原则的情况下，基于应用程序框架层开发一些应用程序。
系统运行库层包括库(也称为系统库)和安卓操作系统运行环境。库主要为安卓操作系统提供其所需的各类资源。安卓操作系统运行环境用于为安卓操作系统提供软件环境。
内核层是安卓操作系统的操作系统层，属于安卓操作系统软件层次的最底层。内核层基于Linux内核为安卓操作系统提供核心系统服务和与硬件相关的驱动程序。
以安卓操作系统为例，本申请实施例中，开发人员可以基于上述如图1所示的安卓操作系统的系统架构，开发实现本申请实施例提供的媒体数据处理方法的软件程序，从而使得该媒体数据处理方法可以基于如图1所示的安卓操作系统运行。即处理器或者终端设备可以通过在安卓操作系统中运行该软件程序实现本申请实施例提供的媒体数据处理方法。
本申请实施例中的终端设备可以为移动终端，也可以为非移动终端。示例性的，移动终端可以为手机、平板电脑、笔记本电脑、掌上电脑、车载终端、可穿戴设备、超级移动个人计算机(ultra-mobile personal computer，UMPC)、上网本或者个人数字助理(personal digital assistant，PDA)等，非移动终端可以为个人计算机(personal computer，PC)、电视机(television，TV)、柜员机或者自助机等，本申请实施例不作具体限定。
本申请实施例提供的媒体数据处理方法的执行主体可以为上述的终端设备，也可以为该终端设备中能够实现该媒体数据处理方法的功能模块和/或功能实体，具体的可以根据实际使用需求确定，本申请实施例不作限定。下面以终端设备为例，结合附图对本申请实施例提供的媒体数据处理方法进行示例性的说明。
图2是本申请实施例提供的处理多图层图像的方法的流程示意图。如图2所示，该方法100包括下述的步骤S110-S130。
S110，根据M个第一图层的像素透明度信息和上下层级关系，确定M个第一图层中每个第一图层的目标区域，该目标区域包括透明区域和/或被覆盖区域。
其中，上述被覆盖区域为被上层图层的不透明区域所覆盖或遮挡的区域，该不透明区域中的像素对应的透明度信息指示像素是不透明的，这些不透明的像素简称为不透明像素。上述透明区域中的像素对应的透明度信息指示像素是透明的，这些透明的像素简称为透明像素。
可选的，上述像素透明度信息可以采用百分比表示透明度，例如100％代表完全透明，0％代表完全不透明，可以理解，(0％，100％)范围内的百分比数值代表半透明。当然，上述像素透明度信息还可以采用其他形式表示透明度，例如采用十六进制表示， 00代表完全透明，FF代表完全不透明。像素透明度信息的具体表示形式可以根据实际使用需求确定，本申请实施例不作限定。
在本申请实施例中，上述每个第一图层的像素数据中包含像素透明度信息，基于像素透明度信息可以判断像素是否透明或者不透明。在一些实施例中，上述每个第一图层可以是采用RGBA数据格式的图像，也可以是采用ARGB数据格式的图像，其中R、G和B分别表征像素的颜色分量，A表征像素的透明度分量。在此情况下，可以根据图层中像素数据中的A分量，判断像素是否透明或者不透明。如此，通过对A分量进行分析，可以确定图层的透明情况，以确定图层的透明区域，并且结合各图层的上下层级关系，可以确定图层的被覆盖情况，以确定图层的被覆盖区域。
示例性的，若图层中某像素的A分量为00，则可以确定该像素完全透明，若图层中某像素的A分量为FF，则可以确定该像素完全不透明。或者，若图层中某像素的A分量为0％，则可以确定该像素完全透明，若图层中某像素的A分量为100％，则可以确定该像素完全不透明。
由于透明区域中的像素为透明的，因此在显示多图层图像时，透明区域中的像素会由于透明而不可见，也就是说，透明区域中的像素在显示时对于显示效果没有贡献，因此本申请实施例提出：在读取图层之前，可以先分析图层中是否存在透明区域，透明区域的像素可以跳过不读。
例如，以两个图层为例，如图3所示，图层21为上层图层，图层22为下层图层。图层21中有透明区域211，图层22中有透明区域221。由于图层21的透明区域211中的像素透明而不可见，因此该透明区域211中的像素可以跳过不读。由于图层22的透明区域221中的像素透明而不可见，因此该透明区域221中的像素可以跳过不读。
需要说明的是，本申请实施例要处理的多图层图像包括至少两个图层(上述M为大于1的整数)，且该至少两个图层具有上下层级关系。在显示这多个图层时，会基于该上下层级关系将该多个图层进行叠加显示。由于多个图层存在上下层级关系，因此各图层之间可能会存在上层图层覆盖下层图层的情况，从叠加显示效果来看，上层图层的不透明区域会覆盖下层图层的一部分区域，由于该部分区域被覆盖，因此将该部分区域称为被覆盖区域。需要说明的是，由于上层图层的透明区域对下层图层的显示是没有影响的，因此本申请实施例主要考虑上层图层的不透明区域覆盖或遮挡下层图层的情况。
示例性的，以两个图层为例，如图4所示，图层23为上层图层且包含不透明区域231，图层24为下层图层。在叠加显示这两个图层时，图层23在上且图层24在下，其中，图层23中的不透明区域231会覆盖或遮挡图层24的区域241(如图4中的黑色区域所示)，因此该图层24的区域241中的像素可以跳过不读。其中，图层23中的透明区域或半透明区域对图层24的显示没有影响。
再示例性的，以三个图层为例，如图5所示，图层25为顶层图层且包含不透明区域251，图层26为中层图层且包含不透明区域262，图层27为底层图层。在叠加显示这三个图层时，图层25在最上方、图层26居中且图层27在下方，其中，图层25中的不透明区域251会覆盖图层26的区域261(如图5中的黑色矩形区域所示)，也会覆盖图层27的区域271(如图5中的黑色矩形区域所示)，并且图层26中的不透明 区域262会覆盖图层27的区域272(如图5中的黑色椭圆形区域所示)。其中，图层25中的透明区域或半透明区域对图层26和图层27的显示没有影响，且图层26中的透明区域或半透明区域对图层27的显示没有影响。
当然，本申请实施例中的M个第一图层还可以为四个或更多个图层，分别为顶层图层、至少两个中层图层和顶层图层，图层覆盖情况具体可以参照上述三个图层的覆盖情况的描述，本申请实施例不作限定。
需要说明的是，为了便于描述，上述实施例中以透明区域为圆形或矩形形状，以及不透明区域为圆形或矩形形状为例进行示例性说明，在实际实现时，本申请实施例不限定透明区域和不透明区域的形状。并且，本申请实施例不限定透明区域和不透明区域在图层中的位置，以及不限定透明区域和不透明区域的尺寸，具体可以根据实际使用需求确定，本申请实施例不作限定。
由于被覆盖区域被上层图层的不透明区域覆盖，即该被覆盖区域中的像素被上层图层的不透明区域覆盖，因此在显示多图层图像时，被覆盖区域中的像素会由于被覆盖而不可见，也就是说，被覆盖区域中的像素在显示时对于显示效果没有贡献，因此本申请实施例提出：在读取图层之前，可以先分析图层中是否存在被覆盖区域，被覆盖区域的像素可以跳过不读。
在一些实施例中，在读取图层之前，可以判断图层中是否存在透明区域和/或被覆盖区域，在实际实现时可能存在如下几种情况：(1)图层中不存在透明区域，也不存在被覆盖区域；或者(2)图层中存在透明区域，而不存在被覆盖区域；或者(3)图层中存在被覆盖区域，而不存在透明区域；或者(4)图层中既存在透明区域，也存在被覆盖区域。可以理解，多个图层中的顶层图层可能存在透明区域，但是不存在被覆盖区域；多个图层中的中层图层或底层图层可能存在透明区域，并且可能存在被覆盖区域。
举例来说，以M个第一图层包括顶层第一图层、中层第一图层和底层第一图层为例，上述S110包括下述的S111-S113。
S111，将顶层第一图层中的透明区域，确定为顶层第一图层的目标区域(称为第一目标区域)。
S112，将中层第一图层中的透明区域和/或被顶层第一图层中的不透明区域覆盖的区域，确定为中层第一图层的目标区域(称为第二目标区域)。
S113，将底层第一图层中的透明区域、被顶层第一图层的不透明区域覆盖的区域和/或被中间第一图层的不透明区域覆盖的区域，确定为底层第一图层的目标区域(称为第三目标区域)。
需要说明的是，本申请实施例不限定上述S111、S112和S113的执行顺序，例如可以依次执行S111、S112和S113；或者可以先同时执行S111和S112，后执行S113；或者可以同时执行S111、S112和S113，具体可以根据实际使用需求确定，本申请实施例不作限定。
可选的，在一些实施例中，在终端设备确定M个第一图层中每个第一图层的目标区域之后，终端设备可以在M个第一图层中每个第一图层的目标区域标记掩码，该掩码指示的区域中的像素不会被读取。
在一些实施例中，可以根据图层中像素数据中的A分量，判断像素是否透明，并且针对图层中透明像素或者该透明像素所在区域进行掩码标记。或者，可以针对图层中被覆盖像素或者该被覆盖像素所在区域进行掩码标记。为了便于描述，可以将标记有掩码的区域称为掩码区域。
可选的，上述掩码可以是一串二进制代码对像素对应字段进行与运算，屏蔽当前的该像素对应字段。在读取图层的场景中，对于屏蔽后的像素对应字段，将不会被读取。也就是说，上述掩码区域也可以理解为屏蔽区域，该屏蔽区域中的像素不会被读取。
一方面，若A分量指示像素透明，则对该像素标记掩码，使其不会被读取。示例性的，若A分量为00或者100％，则可以对该像素标记掩码，使该像素不会被读取。
另一方面，若A分量指示像素不透明，该像素会覆盖位于下方位置的像素，则对位于下方位置的像素标记掩码，使其不会被读取。示例性的，若A分量为FF或者0％，则可以对位于该像素下方位置的像素标记掩码，使位于该像素下方位置的像素不会被读取。
这样，通过分析多个图层中的像素透明度分量以及图层上下层级关系，可以确定图层中的透明区域和/被覆盖区域，并对该透明区域和/被覆盖区域进行掩码标记，从而得到掩码区域。如此，本申请实施例通过在读取图层之前先分析图层的覆盖和/或透明情况，根据图层覆盖和/或透明情况，确定可跳过不读的数据，从而在读取图层时可以将这些掩码区域跳过不读，以降低读取带宽和功耗。
S120，读取M个第一图层中除目标区域之外的像素，得到M个第二图层。
在一些实施例中，在终端设备确定图层的透明区域和/被覆盖区域，并对透明区域和/被覆盖区域标记掩码之后，终端设备可以读取M个第一图层中未标记掩码的图像区域中的像素，此时可以不读取该M个第一图层中标记有掩码的图像区域中的像素。由于在读取图层时选择读取对显示效果有贡献的部分像素，因此读取得到的M个第二图层中的像素的总数量小于M个第一图层中的像素的总数量。
一方面，如上所述，在显示多图层图像的场景中，透明区域中的像素会由于透明而不可见，在显示时对于显示效果没有贡献，因此在读取图层时，可以读取图层中除透明区域之外的像素，而无需读取该图层的透明区域中的像素，这样可以降低读取带宽和功耗。例如，以两个图层为例，图层1为上层图层，图层2为下层图层，若图层1中有透明图层，则在显示这两个图层叠加得到的图像时，图层1的透明区域中的像素由于透明而不可见，因此在读取图层1时，可以无需读取图层1的透明区域中的像素。
另一方面，如上所述，在显示多图层图像的场景中，被覆盖区域中的像素会由于被覆盖而不可见，在显示时对于显示效果没有贡献，因此在读取图层时，可以读取图层中除被覆盖区域之外的像素，而无需读取该图层的被覆盖区域中的像素，这样可以降低读取带宽和功耗。例如，仍然以两个图层为例，若上层图层1中有不透明图层，则在显示这两个图层叠加得到的图像时，图层1中的不透明图层会覆盖下层图层2的部分区域(即被覆盖区域)，使得下层图层2的被覆盖区域中的像素由于被覆盖而不可见，因此在读取下层图层2时，可以无需读取下层图层2的被覆盖区域中的像素。
上文介绍了先判断图层中是否存在透明区域，再根据判断结果读取图层中的全部像素或部分像素的情况，还介绍了先判断图层中是否存在被覆盖区域，再根据判断结果读取图层中的全部像素或部分像素的情况，下面综合上述两种情况进行分析，即判断图层中是否存在透明区域和/或被覆盖区域，然后再根据判断结果读取图层中的全部像素或部分像素，在实际实现时可能存在如下几种情况：
情况1，若图层中不存在透明区域，也不存在被覆盖区域，则在读取该图层时，读取图层中的全部像素。
情况2，若图层中存在透明区域而不存在被覆盖区域，则在读取该图层时，只需读取图层中除透明区域之外的部分像素，而无需读取透明区域中的像素，这样可以降低读取带宽和功耗。
情况3，若图层中存在被覆盖区域而不存在透明区域，则在读取该图层时，只需读取图层中除被覆盖区域之外的部分像素，而无需读取被覆盖区域中的像素，这样可以降低读取带宽和功耗。
情况4，若图层中既存在透明区域，也存在被覆盖区域，则在读取该图层时，只需读取图层中除透明区域和被覆盖区域之外的部分像素，而无需读取透明区域和被覆盖区域中的像素，这样可以降低读取带宽和功耗。
可选的，在本申请实施例中，在读取图层时可以将图层中的透明区域跳过不读；或者，在读取图层时可以将图层中的被覆盖区域跳过不读；或者，在读取图层时可以将图层中的透明区域和被覆盖区域均跳过不读。具体图层中哪些区域被选择跳过不读，可以根据实际使用需求确定，本申请实施例不作限定。
举例来说，仍然以M个第一图层包括顶层第一图层、中层第一图层和底层第一图层为例，上述S120包括下述的S121-S123。
S121，读取顶层第一图层中除第一目标区域(即第一图层中的透明区域)之外的像素，得到顶层第二图层。
S122，读取中层第一图层中除第二目标区域(即中层第一图层中的透明区域和/或被顶层第一图层中的不透明区域覆盖的区域)之外的像素，得到中层第二图层。
S123，读取底层第一图层中除第三目标区域(即底层第一图层中的透明区域、被顶层第一图层的不透明区域覆盖的区域和/或被中间第一图层的不透明区域覆盖的区域)之外的像素，得到底层第二图层。
可以理解，上述M个第二图层包括顶层第二图层、中层第二图层和底层第二图层。并且，根据M个第一图层的上下层级关系，即可确定M个第二图层的上下层级关系。
需要说明的是，本申请实施例不限定上述S121、S122和S123的执行顺序，例如可以依次执行S121、S122和S123；或者可以先同时执行S121和S122，后执行S123；或者可以同时执行S121、S122和S123，具体可以根据实际使用需求确定，本申请实施例不作限定。
S130，显示M个第二图层叠加得到的图像。
如上所述，在读取多图层的场景中，可以读取M个第一图层中未标记掩码的图像区域中的像素，而不读取该M个第一图层中标记有掩码的图像区域中的像素，从而读取得到具有上下层级关系的M个第二图层。然后，终端设备可以按照上下层级关系叠 加该M个第二图层，得到目标图像。进一步的，终端设备可以在显示屏上显示该目标图像。
下面通过举例说明本申请实施例提供的处理多图层图像的方法的具体实现方式。
场景1：显示屏显示动态画面，如图6所示，该动态画面包括叠加的两个全屏图层，图层31为全透明图层，位于上层，采用ARGB数据格式；图层32为非透明图层，位于下层，采用XRGB数据格式，即可以包含A分量，也可以不包含A分量。假设显示屏的刷新率为120Hz，显示屏的分辨率为720*1560，像素格式为32位，那么按照传统方案，需要读取图层31和图层32，并且读取这两个图层所需要的带宽为：720*1560*32*120*2＝8.62Gbps。而通过本申请实施例提供的方法，在读取图层时，读取对显示效果有贡献的非透明图层32即可，而无需读取对显示效果没有贡献的全透明图层31，在此情况下读取图层所需要的带宽为：720*1560*32*120＝4.31Gbps。与传统方案相比较，通过本申请提供的方案可以减少读取带宽。
场景2：如图7所示，待显示图像为叠加的五个全屏图层，这个全屏图层均为不透明图层，且均采用ARGB数据格式。假设显示屏的刷新率为60Hz，显示屏的分辨率为1440*2560，像素格式为32位，那么按照传统方案，需要读取五个不透明图层，其中读取五个不透明图层所需要的带宽为：1440*2560*32*60*5＝35.38Gbps。而通过本申请实施例提供的方法，在读取图层时，读取对显示效果有贡献的顶层不透明图层即可，其中读取顶层不透明图层所需要的带宽为：1440*2560*32*60＝7.07Gbps，而无需读取对显示效果没有贡献的被覆盖图层(如图7中的黑色区域所示)，即少读取4个全屏图层。与传统方案相比较，通过本申请提供的方案可以减少读取带宽。
在本申请实施例中，在读取图层之前先判断图层是否存在被覆盖区域和/或全透明区域的情况，如果待读取的图层中存在被覆盖区域和/或全透明区域，那么在读取图层时可以不读取被覆盖区域和/或全透明区域，如此可以减小读取带宽，进而降低功耗。
图8为图像显示原理的示意性框图，下面参考图8示例性地说明图像显示原理，并结合图像显示原理对本申请实施例提供的处理多图层图像的方法进行说明。如图8所示，中央处理器(central processing unit，CPU)41和图像处理器(graphics processing unit，GPU)42通过总线43连接，显示子系统(display sub-system，DSS)44包括显示存储器441、显示控制器442和显示屏443。CPU 41输出的位图经由总线43可以上传给GPU 42，GPU 42在获取到位图之后对位图进行图层渲染、纹理合成，然后将渲染好的结果放到显示存储器441，由显示控制器442根据垂直同步信号在指定时间从显示存储器441中提取屏幕显示内容(例如多个图层)，然后在显示屏443(即手机屏幕)上进行显示。
其中，GPU在程序运行时根据CPU提供的指令和有关数据，将程序运行过程和结果进行相应的处理并转换成显示器能够接受的文字和图像显示信号。具体地，先通过GPU绘制得到M个第一图层，然后将该多个图层数据写入显示存储器，再从该显示存储器中读取多个图层数据，并通过显示器显示出来。
其中，上述显示存储器也称为帧缓冲器、帧缓存或显存，用于存储GPU处理过或者即将提取的渲染数据。
基于上述图像显示原理，在本申请实施例中，结合图2，如图9所示，在上述S110 之前，本申请实施例提供的处理多图层图像的方法100还包括下述的S140。
S140，通过GPU绘制得到M个第一图层，该M个第一图层具有上下层级关系。
其中，由CPU向GPU发布指令，GPU绘制得到多个图层，然后将该多个图层数据写入存储器。
在一些实施例中，如图9所示，在上述S140之后，本申请实施例提供的处理多图层图像的方法100还可以包括下述的S150和S160。
S150，根据M个第一图层的像素数据，获取M个第一图层的像素透明度信息。
S160，将M个第一图层和像素透明度信息写入存储器。
在本申请实施例中，在通过GPU绘制得到M个第一图层之后，终端设备可以将M个第一图层中的每个第一图层划分成N个图块(N为大于1的整数)，然后遍历每个图块中的所有像素数据，进而获取每个图块对应的像素透明度信息。进一步的，终端设备可以将M个第一图层中的每个图块以及对应的像素透明度信息压缩后写入存储器。再进一步的，可以从存储器读取M个第一图层中除透明区域和/或被覆盖区域之外的像素，得到M个第二图层(参见图9中的S121)。
其中，上述存储器可以为双倍数据率同步动态随机存取存储器(double data rate synchronous dynamic random access memory)，简称为DDR。
本申请采用硬件在图层叠加前预判图层透明及覆盖属性，根据图层透明及覆盖属性确定图层中的透明区域和/或被覆盖区域，在读取图层时对于透明区域和/或被覆盖区域可以跳过不读，从而降低图层读取带宽，降低显示功耗。
可选的，在实际实现时，上述M个第一图层中的每个图块对应的字段可以包括头部(header)字段和数据字段。可以将M个第一图层中的每个图块对应的头部字段和数据字段写入存储器，从而实现将M个第一图层中的每个图块以及对应的像素透明度信息压缩后写入存储器。其中，每个图块对应的数据字段可以包括每个图块中的所有像素的像素值，对于每个图块对应的头部字段中的内容，本申请给出了如下两种可能的实现方式。
方式一，每个图块对应的头部字段可以包括每个图块中的所有像素的透明度信息。
示例性的，图块1对应的头部字段包括图块1中的所有像素的透明度信息。
方式二，每个图块对应的头部字段可以包括每个图块中的部分像素的透明度信息，该部分像素位于透明区域和/或不透明区域。由于在头部字段存储了用于确定图层的透明区域和/或被覆盖区域的信息即可，如此可以减少信息冗余。
示例性的，图块1对应的头部字段包括图块1中的透明区域和/或不透明区域的像素的透明度信息，例如头部字段包括如下部分特定像素的指示信息：像素1对应于00或100％，或者表示像素透明的其他标志；像素2对应于FF或0％，或者表示像素不透明的其他标志。
这样，在头部字段和数据字段包含各图层的像素透明度信息和上下层级关系的情况下，可以根据M个第一图层中每个第一图层中的N个图块各自对应的头部字段和数据字段，确定每个第一图层的透明区域和/或被覆盖区域。
具体到本申请实施例，在GPU绘制图层结束，将图层写入存储器的过程中，为了降低带宽，会使用压缩算法，压缩算法会遍历图层各分块内的所有像素数据。利用该 功能，可以在压缩过程中增加对A分量统计的功能，并将统计结果以头部数据(即上述头部字段)的形式存入存储器。在DSS送显第S帧(代表前一帧)时，在GPU绘制完成第S+1帧(代表后一帧)之后，DSS可以对第S+1帧中各图层的分块的头部数据进行分析，获得整个图层的透明或覆盖特性，并在送显第S+1帧时将第S+1帧中各图层的透明区域的内容和/或被其他图层覆盖的内容跳过不读，从而节省带宽。
其中，在GPU绘制图层之后对图层进行压缩，压缩时可以采用标识对各分块内的各像素A分量进行统计。示例性的，可以采用2bit的标识(flag)来标记统计结果：若A分量为00，则在头部数据中采用标识1表征A分量全为00；若A分量全为FF，则在头部数据中采用标识2表征A全为FF。然后，将各分块的包含标识信息的头部数据写入存储器，以便于统计结果的识别。
下面结合图10对本申请实施例提供的上述方案进行示例性的说明。如图10所示，第一阶段：在DSS送显第S帧时，GPU绘制完第S+1帧后，软件配置DSS进入后台分析流程，检测第S+1帧的头部字段中的标识信息，检测完成后，软件计算出第S+1帧的各图层的掩码区域(例如透明区域和/被覆盖区域)的坐标。并且可以采用硬件合成器(hardware composer，HWC)对第S+1帧的各个图层进行图层合成。第二阶段：在DSS送显第S+1帧时，可按照各图层的掩码区域的坐标，跳过不需要读的掩码区域，节省带宽。对于后续的第S+2帧、第S+3帧等的读取及显示类似于对第S+1帧的读取及显示，此处不再赘述。
综上所述，在绘图的GPU处统计图层透明度信息，并将多图层及其透明度信息写入存储器，在读取某帧图像之前，利用DSS后台分析该帧图像中各个图层覆盖和/或透明情况。然后，在读取该帧图像时，可以根据图层覆盖和/或透明的分析结果，跳过图层中的被覆盖区域和/或全透明区域，从而降低读带宽和功耗。
本申请实施例提供的处理多图层图像的方法，可以根据M个第一图层的像素透明度信息和上下层级关系，确定M个第一图层中每个第一图层的目标区域，该目标区域包括透明区域和/或被覆盖区域(即被上层图层的不透明区域覆盖的区域)；然后读取M个第一图层中除该目标区域之外的像素，得到M个第二图层；然后显示M个第二图层叠加得到的图像，该M个第二图层中的像素的总数量小于M个第一图层中的像素的总数量。通过本申请方案，在读取图层之前，可以先根据多个图层中的像素透明度分量以及图层上下层级关系，分析图层的透明和/或覆盖情况，确定图层中的透明区域和/被覆盖区域。由于透明区域和/被覆盖区域在显示时对于显示效果没有贡献，因此这些区域的内容可以跳过不读，进而在读取图层时选择读取图层中对显示效果有贡献的内容，将这些透明区域和/被覆盖区域跳过不读，如此可以减小读取带宽，降低功耗。
本文中描述的各个实施例可以为独立的方案，也可以根据内在逻辑进行组合，这些方案都落入本申请的保护范围中。
可以理解的是，上述各个方法实施例中由终端设备实现的方法和操作，也可以由可用于终端设备的部件(例如芯片或者电路)实现。
上文描述了本申请提供的方法实施例，下文将描述本申请提供的装置实施例。应理解，装置实施例的描述与方法实施例的描述相互对应，因此，未详细描述的内容可以参见上文方法实施例，为了简洁，这里不再赘述。
上文主要从方法步骤的角度对本申请实施例提供的方案进行了描述。可以理解的是，为了实现上述功能，实施该方法的终端设备包含了执行各个功能相应的硬件结构和/或软件模块。本领域技术人员应该可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，本申请能够以硬件或硬件和计算机软件的结合形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的保护范围。
本申请实施例可以根据上述方法示例，对终端设备进行功能模块的划分，例如，可以对应各个功能划分各个功能模块，也可以将两个或两个以上的功能集成在一个处理模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。需要说明的是，本申请实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有其它可行的划分方式。下面以采用对应各个功能划分各个功能模块为例进行说明。
图11为本申请实施例提供的媒体数据处理装置800的示意性框图。该装置800可以用于执行上文方法实施例中终端设备所执行的动作。该装置800包括处理单元810、读取单元820和显示单元830。
处理单元810，用于根据M个第一图层的像素透明度信息和上下层级关系，确定该M个第一图层中每个第一图层的目标区域，该目标区域包括透明区域和/或被覆盖区域；
读取单元820，用于读取上述M个第一图层中除目标区域之外的像素，得到M个第二图层，该M个第二图层中的像素的总数量小于该M个第一图层中的像素的总数量；
显示单元830，用于显示上述M个第二图层叠加得到的图像；
其中，上述被覆盖区域为被上层图层的不透明区域覆盖的区域，该不透明区域中的像素对应的像素透明度信息指示像素不透明，上述透明区域中的像素对应的像素透明度信息指示像素透明，M为大于1的整数。
在一些实施例中，在上述M个第一图层包括顶层第一图层、中层第一图层和底层第一图层的情况下，处理单元810具体用于：
将顶层第一图层中的透明区域，确定为顶层第一图层的第一目标区域；
将中层第一图层中的透明区域和/或被顶层第一图层中的不透明区域覆盖的区域，确定为中层第一图层的第二目标区域；
将底层第一图层中的透明区域、被顶层第一图层的不透明区域覆盖的区域和/或被中间第一图层的不透明区域覆盖的区域，确定为底层第一图层的第三目标区域。
在一些实施例中，读取单元820具体用于：
读取上述顶层第一图层中除上述第一目标区域之外的像素，得到顶层第二图层；
读取上述中层第一图层中除上述第二目标区域之外的像素，得到中层第二图层；
读取上述底层第一图层中除上述第三目标区域之外的像素，得到底层第二图层；
其中，上述M个第二图层包括上述顶层第二图层、上述中层第二图层和上述底层第二图层。
在一些实施例中，处理单元810，还用于在确定上述M个第一图层中每个第一图层的目标区域之后，在上述M个第一图层中每个第一图层的目标区域标记掩码，该掩码指示的区域中的像素不允许被读取；
读取单元820，具体用于读取上述M个第一图层中未标记掩码的图像区域中的像素，以及不读取上述M个第一图层中标记掩码的图像区域中的像素。
在一些实施例中，处理单元810，还用于在确定上述M个第一图层中每个第一图层的目标区域之前，通过图像处理器GPU绘制得到上述M个第一图层，该M个第一图层具有上下层级关系。
在一些实施例中，处理单元810，还用于在通过GPU绘制得到上述M个第一图层之后，根据上述M个第一图层的像素数据，获取上述M个第一图层的像素透明度信息；并将上述M个第一图层和上述像素透明度信息写入存储器；
读取单元820，具体用于从上述存储器读取上述M个第一图层中除目标区域之外的像素。
在一些实施例中，处理单元810具体用于：
将上述M个第一图层中的每个第一图层划分成N个图块，N为大于1的整数；
遍历每个图块中的所有像素数据，获取所述每个图块对应的像素透明度信息；
将上述M个第一图层中的每个图块以及对应的像素透明度信息压缩后写入上述存储器。
在一些实施例中，上述M个第一图层中的每个图块对应的字段包括头部字段和数据字段，所述每个图块对应的头部字段包括所述每个图块中的所有像素或者部分像素的透明度信息，该部分像素位于上述透明区域中和/或不透明区域，所述每个图块对应的数据字段包括所述每个图块中的所有像素的像素值；
处理单元810，具体用于将上述M个第一图层中的每个图块对应的头部字段和数据字段写入上述存储器；并且根据上述M个第一图层中每个第一图层中的N个图块各自对应的头部字段和数据字段，确定所述每个第一图层的目标区域。
在一些实施例中，上述M个第一图层为采用RGBA或者ARGB数据格式的图像，其中R、G和B分别代表像素的颜色分量，A代表像素的透明度分量。
在一些实施例中，处理单元810，还用于根据上述M个第一图层的上下层级关系，确定上述M个第二图层的上下层级关系；
显示单元830，具体用于按照上述M个第二图层的上下层级关系叠加上述M个第二图层，得到目标图像；并且在装置800的显示屏上显示该目标图像。
本申请实施例提供一种处理多图层图像的装置，可以根据M个第一图层的像素透明度信息和上下层级关系，确定M个第一图层中每个第一图层的目标区域，该目标区域包括透明区域和/或被覆盖区域(即被上层图层的不透明区域覆盖的区域)；并且该装置读取M个第一图层中除该目标区域之外的像素，得到M个第二图层；然后该装置显示M个第二图层叠加得到的图像，该M个第二图层中的像素的总数量小于M个第一图层中的像素的总数量。通过本申请方案，在读取图层之前，可以先根据多个图层中的像素透明度分量以及图层上下层级关系，分析图层的透明和/或覆盖情况，确定图层中的透明区域和/被覆盖区域。由于透明区域和/被覆盖区域在显示时对于显示效果 没有贡献，因此这些区域的内容可以跳过不读，即在读取图层时选择读取该图层中对显示效果有贡献的内容，将这些透明区域和/被覆盖区域跳过不读，如此可以减小读取带宽，降低功耗。
根据本申请实施例的装置800可对应于执行本申请实施例中描述的方法，并且装置800中的单元的上述和其它操作和/或功能分别为了实现方法的相应流程，为了简洁，在此不再赘述。
图12是本申请实施例提供的终端设备900的结构性示意性图。所述终端设备900包括：处理器910、存储器920、通信接口930、总线940。
其中，该处理器910可以与存储器920连接。该存储器920可以用于存储该程序代码和数据。因此，该存储器920可以是处理器910内部的存储单元，也可以是与处理器910独立的外部存储单元，还可以是包括处理器910内部的存储单元和与处理器910独立的外部存储单元的部件。需要说明的是，图12所示的终端设备900中的处理器910可以对应于图11中的装置800中的处理单元810。
可选的，终端设备900还可以包括总线940。其中，存储器920、通信接口930可以通过总线940与处理器910连接。总线940可以是外设部件互连标准(peripheral component interconnect，PCI)总线或扩展工业标准结构(extended industry standard architecture，EISA)总线等。所述总线940可以分为地址总线、数据总线、控制总线等。为便于表示，图12中仅用一条线表示，但并不表示仅有一根总线或一种类型的总线。
应理解，在本申请实施例中，该处理器910可以采用中央处理单元(central processing unit，CPU)。该处理器还可以是其它通用处理器、数字信号处理器(digital signal processor，DSP)、专用集成电路(application specific integrated circuit，ASIC)、现成可编程门阵列(field programmable gate Array，FPGA)或者其它可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。或者该处理器810采用一个或多个集成电路，用于执行相关程序，以实现本申请实施例所提供的技术方案。
该存储器920可以包括只读存储器和随机存取存储器，并向处理器910提供指令和数据。处理器910的一部分还可以包括非易失性随机存取存储器。例如，处理器910还可以存储设备类型的信息。
在终端设备900运行时，所述处理器910执行所述存储器920中的计算机执行指令以执行上述方法的操作步骤。
应理解，根据本申请实施例的终端设备900可对应于本申请实施例中的装置800，并且装置800中的各个单元的上述和其它操作和/或功能用于实现方法的相应流程，为了简洁，在此不再赘述。
可选地，在一些实施例中，本申请实施例还提供了一种计算机可读介质，所述计算机可读介质存储有程序代码，当所述计算机程序代码在计算机上运行时，使得计算机执行上述各方面中的方法。
可选地，在一些实施例中，本申请实施例还提供了一种计算机程序产品，所述计算机程序产品包括计算机程序代码，当所述计算机程序代码在计算机上运行时，使得 计算机执行上述各方面中的方法。
本申请实施例并未对本申请实施例提供的方法的执行主体的具体结构进行特别限定，只要能够通过运行记录有本申请实施例提供的方法的代码的程序，以根据本申请实施例提供的方法对图层图像进行处理即可。例如，本申请实施例提供的方法的执行主体可以是终端设备，或者，是终端设备中能够调用程序并执行程序的功能模块。
本申请的各个方面或特征可以实现成方法、装置或使用标准编程和/或工程技术的制品。本文中使用的术语“制品”可以涵盖可从任何计算机可读器件、载体或介质访问的计算机程序。例如，计算机可读介质可以包括但不限于：磁存储器件(例如，硬盘、软盘或磁带等)，光盘(例如，压缩盘(compact disc，CD)、数字通用盘(digital versatile disc，DVD)等)，智能卡和闪存器件(例如，可擦写可编程只读存储器(erasable programmable read-only memory，EPROM)、卡、棒或钥匙驱动器等)。
本文描述的各种存储介质可代表用于存储信息的一个或多个设备和/或其它机器可读介质。术语“机器可读介质”可以包括但不限于：无线信道和能够存储、包含和/或承载指令和/或数据的各种其它介质。
应理解，本申请实施例中提及的处理器可以是CPU，还可以是其他通用处理器、数字信号处理器(digital signal processor，DSP)、专用集成电路(application specific integrated circuit，ASIC)、现成可编程门阵列(field programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
还应理解，本申请实施例中提及的存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(read-only memory，ROM)、可编程只读存储器(programmable ROM，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(random access memory，RAM)。例如，RAM可以用作外部高速缓存。作为示例而非限定，RAM可以包括如下多种形式：静态随机存取存储器(static RAM，SRAM)、动态随机存取存储器(dynamic RAM，DRAM)、同步动态随机存取存储器(synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(double data rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(direct rambus RAM，DR RAM)。
需要说明的是，当处理器为通用处理器、DSP、ASIC、FPGA或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件时，存储器(存储模块)可以集成在处理器中。
还需要说明的是，本文描述的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技 术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的保护范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。此外，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上，或者说对现有技术做出贡献的部分，或者该技术方案的部分，可以以计算机软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，该计算机软件产品包括若干指令，该指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。前述的存储介质可以包括但不限于：U盘、移动硬盘、ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (24)

  1. 一种处理多图层图像的方法，其特征在于，包括：
    根据M个第一图层的像素透明度信息和上下层级关系，确定所述M个第一图层中每个第一图层的目标区域，所述目标区域包括透明区域和/或被覆盖区域；
    读取所述M个第一图层中除所述目标区域之外的像素，得到M个第二图层，所述M个第二图层中的像素的总数量小于所述M个第一图层中的像素的总数量；
    显示所述M个第二图层叠加得到的图像；
    其中，所述被覆盖区域为被上层图层的不透明区域覆盖的区域，所述不透明区域中的像素对应的像素透明度信息指示像素不透明，所述透明区域中的像素对应的像素透明度信息指示像素透明，M为大于1的整数。
  2. 根据权利要求1所述的方法，其特征在于，在所述M个第一图层包括顶层第一图层、中层第一图层和底层第一图层的情况下，所述根据M个第一图层的像素透明度信息和上下层级关系，确定所述M个第一图层中每个第一图层的目标区域，包括：
    将所述顶层第一图层中的透明区域，确定为所述顶层第一图层的第一目标区域；
    将所述中层第一图层中的透明区域和/或被所述顶层第一图层中的不透明区域覆盖的区域，确定为所述中层第一图层的第二目标区域；
    将所述底层第一图层中的透明区域、被所述顶层第一图层的不透明区域覆盖的区域和/或被所述中间第一图层的不透明区域覆盖的区域，确定为所述底层第一图层的第三目标区域。
  3. 根据权利要求2所述的方法，其特征在于，所述读取所述M个第一图层中除所述目标区域之外的像素，得到M个第二图层，包括：
    读取所述顶层第一图层中除所述第一目标区域之外的像素，得到顶层第二图层；
    读取所述中层第一图层中除所述第二目标区域之外的像素，得到中层第二图层；
    读取所述底层第一图层中除所述第三目标区域之外的像素，得到底层第二图层；
    其中，所述M个第二图层包括所述顶层第二图层、所述中层第二图层和所述底层第二图层。
  4. 根据权利要求1至3中任一项所述的方法，其特征在于，在所述确定所述M个第一图层中每个第一图层的目标区域之后，所述读取所述M个第一图层中除所述目标区域之外的像素之前，所述方法还包括：
    在所述M个第一图层中每个第一图层的目标区域标记掩码，所述掩码指示的区域中的像素不允许被读取；
    其中，所述读取所述M个第一图层中除所述目标区域之外的像素，包括：
    读取所述M个第一图层中未标记所述掩码的图像区域中的像素；
    不读取所述M个第一图层中标记所述掩码的图像区域中的像素。
  5. 根据权利要求1至4中任一项所述的方法，其特征在于，在所述确定所述M个第一图层中每个第一图层的目标区域之前，所述方法还包括：
    通过图像处理器GPU绘制得到所述M个第一图层，所述M个第一图层具有所述上下层级关系。
  6. 根据权利要求5所述的方法，其特征在于，在所述通过GPU绘制得到所述M个第一图层之后，所述方法还包括：
    根据所述M个第一图层的像素数据，获取所述M个第一图层的像素透明度信息；
    将所述M个第一图层和所述像素透明度信息写入存储器；
    其中，所述读取所述M个第一图层中除所述目标区域之外的像素，包括：
    从所述存储器读取所述M个第一图层中除所述目标区域之外的像素。
  7. 根据权利要求6所述的方法，其特征在于，所述获取所述M个第一图层的像素透明度信息，包括：
    将所述M个第一图层中的每个第一图层划分成N个图块，N为大于1的整数；
    遍历每个图块中的所有像素数据，获取所述每个图块对应的像素透明度信息；
    其中，所述将所述M个第一图层和所述像素透明度信息写入存储器，包括：
    将所述M个第一图层中的每个图块以及对应的像素透明度信息压缩后写入所述存储器。
  8. 根据权利要求7所述的方法，其特征在于，所述M个第一图层中的每个图块对应的字段包括头部字段和数据字段，所述每个图块对应的头部字段包括所述每个图块中的所有像素或者部分像素的透明度信息，所述部分像素位于所述透明区域中和/或所述不透明区域，所述每个图块对应的数据字段包括所述每个图块中的所有像素的像素值；
    所述将所述M个第一图层中的每个图块以及对应的像素透明度信息压缩后写入所述存储器，包括：
    将所述M个第一图层中的每个图块对应的头部字段和数据字段写入所述存储器；
    其中，所述根据M个第一图层的像素透明度信息和上下层级关系，确定所述M个第一图层中每个第一图层的目标区域，包括：
    根据所述M个第一图层中每个第一图层中的N个图块各自对应的头部字段和数据字段，确定所述每个第一图层的目标区域。
  9. 根据权利要求1至8中任一项所述的方法，其特征在于，所述M个第一图层为采用RGBA或者ARGB数据格式的图像，其中R、G和B分别代表像素的颜色分量，A代表像素的透明度分量。
  10. 根据权利要求1至9中任一项所述的方法，其特征在于，所述显示所述M个第二图层叠加得到的图像，包括：
    根据所述M个第一图层的上下层级关系，确定所述M个第二图层的上下层级关系；
    按照所述M个第二图层的上下层级关系叠加所述M个第二图层，得到目标图像；
    在显示屏上显示所述目标图像。
  11. 一种处理多图层图像的装置，其特征在于，包括处理单元、读取单元和显示单元；
    所述处理单元，用于根据M个第一图层的像素透明度信息和上下层级关系，确定所述M个第一图层中每个第一图层的目标区域，所述目标区域包括透明区域和/或被覆盖区域；
    所述读取单元，用于读取所述M个第一图层中除所述目标区域之外的像素，得到M个第二图层，所述M个第二图层中的像素的总数量小于所述M个第一图层中的像素的总数量；
    所述显示单元，用于显示所述M个第二图层叠加得到的图像；
    其中，所述被覆盖区域为被上层图层的不透明区域覆盖的区域，所述不透明区域中的像素对应的像素透明度信息指示像素不透明，所述透明区域中的像素对应的像素透明度信息指示像素透明，M为大于1的整数。
  12. 根据权利要求11所述的装置，其特征在于，在所述M个第一图层包括顶层第一图层、中层第一图层和底层第一图层的情况下，所述处理单元具体用于：
    将所述顶层第一图层中的透明区域，确定为所述顶层第一图层的第一目标区域；
    将所述中层第一图层中的透明区域和/或被所述顶层第一图层中的不透明区域覆盖的区域，确定为所述中层第一图层的第二目标区域；
    将所述底层第一图层中的透明区域、被所述顶层第一图层的不透明区域覆盖的区域和/或被所述中间第一图层的不透明区域覆盖的区域，确定为所述底层第一图层的第三目标区域。
  13. 根据权利要求12所述的装置，其特征在于，所述读取单元具体用于：
    读取所述顶层第一图层中除所述第一目标区域之外的像素，得到顶层第二图层；
    读取所述中层第一图层中除所述第二目标区域之外的像素，得到中层第二图层；
    读取所述底层第一图层中除所述第三目标区域之外的像素，得到底层第二图层；
    其中，所述M个第二图层包括所述顶层第二图层、所述中层第二图层和所述底层第二图层。
  14. 根据权利要求11至13中任一项所述的装置，其特征在于，
    所述处理单元，还用于在确定所述M个第一图层中每个第一图层的目标区域之后，在所述M个第一图层中每个第一图层的目标区域标记掩码，所述掩码指示的区域中的像素不允许被读取；
    所述读取单元，具体用于读取所述M个第一图层中未标记所述掩码的图像区域中的像素，以及不读取所述M个第一图层中标记所述掩码的图像区域中的像素。
  15. 根据权利要求11至14中任一项所述的装置，其特征在于，
    所述处理单元，还用于在确定所述M个第一图层中每个第一图层的目标区域之前，通过图像处理器GPU绘制得到所述M个第一图层，所述M个第一图层具有所述上下层级关系。
  16. 根据权利要求15所述的装置，其特征在于，
    所述处理单元，还用于在所述通过GPU绘制得到所述M个第一图层之后，根据所述M个第一图层的像素数据，获取所述M个第一图层的像素透明度信息；并将所述M个第一图层和所述像素透明度信息写入存储器；
    所述读取单元，具体用于从所述存储器读取所述M个第一图层中除所述目标区域之外的像素。
  17. 根据权利要求16所述的装置，其特征在于，所述处理单元具体用于：
    将所述M个第一图层中的每个第一图层划分成N个图块，N为大于1的整数；
    遍历每个图块中的所有像素数据，获取所述每个图块对应的像素透明度信息；
    将所述M个第一图层中的每个图块以及对应的像素透明度信息压缩后写入所述存储器。
  18. 根据权利要求17所述的装置，其特征在于，所述M个第一图层中的每个图块对应的字段包括头部字段和数据字段，所述每个图块对应的头部字段包括所述每个图块中的所有像素或者部分像素的透明度信息，所述部分像素位于所述透明区域中和/或所述不透明区域，所述每个图块对应的数据字段包括所述每个图块中的所有像素的像素值；
    所述处理单元，具体用于将所述M个第一图层中的每个图块对应的头部字段和数据字段写入所述存储器；并且根据所述M个第一图层中每个第一图层中的N个图块各自对应的头部字段和数据字段，确定所述每个第一图层的目标区域。
  19. 根据权利要求11至18中任一项所述的装置，其特征在于，所述M个第一图层为采用RGBA或者ARGB数据格式的图像，其中R、G和B分别代表像素的颜色分量，A代表像素的透明度分量。
  20. 根据权利要求11至19中任一项所述的装置，其特征在于，
    所述处理单元，还用于根据所述M个第一图层的上下层级关系，确定所述M个第二图层的上下层级关系；
    所述显示单元，具体用于按照所述M个第二图层的上下层级关系叠加所述M个第二图层，得到目标图像；并且在所述装置的显示屏上显示所述目标图像。
  21. 一种终端设备，其特征在于，包括处理器，所述处理器与存储器耦合，所述处理器用于执行所述存储器中存储的计算机程序或指令，以使得所述终端设备实现如权利要求1至10中任一项所述的方法。
  22. 一种芯片，其特征在于，所述芯片包括处理器，所述处理器与存储器耦合，所述处理器用于读取并执行所述存储器中存储的计算机程序，以实现如权利要求1至10中任一项所述的方法。
  23. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质存储有计算机程序，当所述计算机程序在终端设备上运行时，使得所述终端设备执行如权利要求1至10中任一项所述的方法。
  24. 一种计算机程序产品，其特征在于，所述计算机程序产品包括计算机程序，当所述计算机程序被计算机执行时，使得所述计算机实现如权利要求1至10中任一项所述的方法。
PCT/CN2021/077474 2021-02-23 2021-02-23 处理多图层图像的方法、装置及终端设备 WO2022178668A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP21927115.2A EP4287113A4 (en) 2021-02-23 2021-02-23 METHOD AND DEVICE FOR PROCESSING A MULTILAYER IMAGE AND TERMINAL DEVICE
CN202180092782.4A CN116868225A (zh) 2021-02-23 2021-02-23 处理多图层图像的方法、装置及终端设备
PCT/CN2021/077474 WO2022178668A1 (zh) 2021-02-23 2021-02-23 处理多图层图像的方法、装置及终端设备

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/077474 WO2022178668A1 (zh) 2021-02-23 2021-02-23 处理多图层图像的方法、装置及终端设备

Publications (1)

Publication Number Publication Date
WO2022178668A1 true WO2022178668A1 (zh) 2022-09-01

Family

ID=83048576

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/077474 WO2022178668A1 (zh) 2021-02-23 2021-02-23 处理多图层图像的方法、装置及终端设备

Country Status (3)

Country Link
EP (1) EP4287113A4 (zh)
CN (1) CN116868225A (zh)
WO (1) WO2022178668A1 (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000068887A1 (en) * 1999-05-10 2000-11-16 Apple Computer, Inc. Rendering translucent layers
CN106127721A (zh) * 2015-05-05 2016-11-16 联发科技股份有限公司 用于显示由叠加图像层合成的混合图像的图形系统及方法
CN106201512A (zh) * 2016-07-11 2016-12-07 无锡天脉聚源传媒科技有限公司 一种图片展示的方法及装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3462867B2 (ja) * 2001-09-14 2003-11-05 株式会社アクセル 画像圧縮方法および装置、画像圧縮プログラムならびに画像処理装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000068887A1 (en) * 1999-05-10 2000-11-16 Apple Computer, Inc. Rendering translucent layers
CN106127721A (zh) * 2015-05-05 2016-11-16 联发科技股份有限公司 用于显示由叠加图像层合成的混合图像的图形系统及方法
CN106201512A (zh) * 2016-07-11 2016-12-07 无锡天脉聚源传媒科技有限公司 一种图片展示的方法及装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4287113A4 *

Also Published As

Publication number Publication date
CN116868225A (zh) 2023-10-10
EP4287113A4 (en) 2024-04-10
EP4287113A1 (en) 2023-12-06

Similar Documents

Publication Publication Date Title
US8384738B2 (en) Compositing windowing system
US9355493B2 (en) Device and method for compositing video planes
US11972514B2 (en) Animation file processing method and apparatus, computer-readable storage medium, and computer device
US20110292060A1 (en) Frame buffer sizing to optimize the performance of on screen graphics in a digital electronic device
US20230367953A1 (en) Display rendering method and system
CN110913262B (zh) 图像叠加方法和装置
CN112596843B (zh) 图像处理方法、装置、电子设备及计算机可读存储介质
US20190349558A1 (en) Media processing systems
WO2023134128A1 (zh) 一种视频压缩处理方法、装置及介质
JP5057895B2 (ja) 画像出力装置および画面構成方法
US7852339B2 (en) Video composition optimization by the identification of transparent and opaque regions
US7830397B2 (en) Rendering multiple clear rectangles using a pre-rendered depth buffer
US8358314B2 (en) Method for reducing framebuffer memory accesses
US5319382A (en) Method and apparatus for manipulating a full motion video presentation in a data processing system
WO2022178668A1 (zh) 处理多图层图像的方法、装置及终端设备
US20060033753A1 (en) Apparatuses and methods for incorporating an overlay within an image
EP1376473A2 (en) System and method for employing non-alpha channel image data in an alpha-channel-aware environment
CN111683213A (zh) 基于感兴趣区域灰度图像的自适应字符叠加系统及方法
CN113625923A (zh) 基于远程云桌面的鼠标处理方法、装置、存储介质及设备
US20020081030A1 (en) System and method for detecting text in mixed graphics data
US20050021552A1 (en) Video playback image processing
US9800801B2 (en) Techniques for processing subtitles
US20220028360A1 (en) Method, computer program and apparatus for generating an image
WO2023015949A1 (zh) 屏幕显示方法和终端设备
US20090080802A1 (en) Information processing apparatus and method for generating composite image

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21927115

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 202180092782.4

Country of ref document: CN

ENP Entry into the national phase

Ref document number: 2021927115

Country of ref document: EP

Effective date: 20230829

NENP Non-entry into the national phase

Ref country code: DE