WO2022178339A1 - Multiplicateur-accumulateur de produit scalaire à virgule flottante - Google Patents

Multiplicateur-accumulateur de produit scalaire à virgule flottante Download PDF

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WO2022178339A1
WO2022178339A1 PCT/US2022/017126 US2022017126W WO2022178339A1 WO 2022178339 A1 WO2022178339 A1 WO 2022178339A1 US 2022017126 W US2022017126 W US 2022017126W WO 2022178339 A1 WO2022178339 A1 WO 2022178339A1
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exp
floating point
mantissa
exponent
stage
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PCT/US2022/017126
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English (en)
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Dylan FINCH
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Redpine Signals Inc
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Priority claimed from US17/180,831 external-priority patent/US11983237B2/en
Priority claimed from US17/180,856 external-priority patent/US11893360B2/en
Application filed by Redpine Signals Inc filed Critical Redpine Signals Inc
Publication of WO2022178339A1 publication Critical patent/WO2022178339A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N20/00—Machine learning

Definitions

  • the present invention relates to a Multiplier- Accumulator for performing dot product computations between an input multiplicand matrix and a coefficient multiplicand matrix, forming a result from the sum of products.
  • a first object of the invention is a pipelined floating point multiplier having a sign processor, an exponent processor and a mantissa processor for performing multiply-accumulate operations on a linear array of N input floating point numbers with a linear array of N coefficient floating point numbers, each input floating point number and coefficient floating point number comprising a sign bit, an exponent comprising a plurality of exponent bits, and a mantissa comprising a plurality of exponent bits, the floating point multiplier comprising: a plurality of pipeline stages, each pipeline stage comprising a first pipeline stage and a second pipeline stage; the first pipeline stage having an exponent processor forming an exponent sum from the input exponent and coefficient exponent, and identifying a maximum exponent (MAX_EXP) and an exponent difference (EXP_DIFF) of MAX_EXP less the exponent sum, the sign processor forming a sign bit by exclusive ORing (XOR) the input floating point sign and coefficient floating point sign, each first stage also forming a normal
  • a second object of the invention is a process for a unit element multiplier-accumulator (UE MAC) forming a floating point sum of products from a plurality N of floating point input values multiplied by a corresponding floating point coefficient, each floating point value and each coefficient value having a sign bit, a plurality of exponent bits, and a plurality of mantissa bits, the process comprising: forming a plurality of N sums of input value exponents and corresponding coefficient exponent and selecting MAX_EXP as the largest sum from the plurality of N sums; for each of the N input values and coefficient values: separating a sign, mantissa, and exponent value; forming a sign bit by exclusive ORing (XOR) an input value sign and a coefficient value sign; forming a mantissa multiplication product by multiplying an input mantissa with hidden bit restored with a coefficient mantissa with hidden bit restored; normalizing the mantissa multiplication by setting EXP_IN
  • MAX_EXP if EXP_DIFF is 0 and EXP_INC is set and sending a signal MAX_INC to other stages; a processing stage which has EXP_DIFF greater than 0 incrementing EXP_DIFF if EXP_INC is not set and MAX_INC is set; a processing stage which has EXP_DIFF greater than 0 decrementing EXP_DIFF if EXP_INC is set and MAX_INC is not set; padding the normalized mantissa multiplication with leading Os and trailing Os; replacing the padded normalized mantissa multiplication with a twos complement of the padded normalized mantissa multiplication if the sign bit is 1; generating an output by shifting the padded normalized mantissa multiplication to the right by EXP_DIFF bits; summing the outputs to form an integer form fraction; generating a floating point result by normalizing the integer form fraction by extracting a floating
  • a unit element multiplier-accumulator for multiplying an input lxn vector with an nxm coefficient matrix receives the lxn input vector and nxl column vector selected from the b coefficient matrix.
  • Each first stage includes a sign bit processor which performs an exclusive OR (XOR) operation on the pair of sign bits to determine a sign, a mantissa processor which performs a multiplication and normalization of the mantissa parts and also an exponent increment (EXP_INC) output indicating a mantissa overflow, and an exponent processor which sums corresponding input and coefficient exponent.
  • a central maximum exponent finder examines all exponent sums to determine a maximum exponent (MAX_EXP) as well as a difference from MAX_EXP for the corresponding exponent sum.
  • Each first stage thereby produces a sign bit, normalized multiplication result, exponent increment (EXP_INC) result from the mantissa multiplication, and from the plurality of first stages, a maximum exponent (MAX_EXP) value is found, and each first stage thereby computes a difference value (EXP_DIFF) from that stage's exponent sum to the MAX_EXP, which is passed to the corresponding second stage as a difference value EXP_DIFF.
  • the second pipeline stage thereby receives from each corresponding first pipeline stage the sign bit, the normalized multiplication result, EXP_INC value from the mantissa multiplication indicating a mantissa overflow, the MAX EXP value, and exponent difference EXP_DIFF.
  • Adjustment stages which have EXP_DIFF>0 second pipeline stages which do not have the largest exponent sum
  • EXP_INC adjustment stages with EXP_INC set and MAX_INC not set decrement EXP_DIFF
  • Adjustment stages with EXP_INC set and MAX_INC also set do not change EXP_DIFF
  • adjustment stages with EXP_ INC not set and MAX_INC set do not change EXP_DIFF.
  • Each second pipeline stage takes the normalized mantissa multiplication result and modifies it in three steps, referred to as normalized mantissa Pad, Complement, Shift (Mantissa PCS).
  • the normalized mantissa multiplication result from 208 is padded by pre pended with Os to accommodate the maximum value that may result from addition of N normalized values, and also appended with Os for a desired precision by the addition of N stages.
  • the sign input to the second pipeline stage is negative, the two's complement of the resulting value is substituted, otherwise the resulting value is unchanged.
  • the value is shifted to the right by the number bits of the exponent difference (EXP_DIFF) from the first stage, accommodating any exponent adjustments as may be necessary.
  • the N pipeline stages each generating an output from the mantissa Pad, Complement and Shift (PCS) stage thereby generate N integer form fractions, which are summed in pairs until a single integer value representing the sum of all integer form fractions remains.
  • the summed integer form fraction is a signed value which is converted to an unsigned integer value (such as by 2's complement) with the sign extracted and used for the floating point result sign bit, and the summed integer form fraction is normalized to become the mantissa component, and MAX_EXP value is then used provide the exponent component, thereby forming a floating point result with sign bit, exponent, and mantissa that represents the sum of N products formed by each input and coefficient value.
  • Figures 1A and IB show a block diagram for a pipelined floating point multiplier according to a current example of the invention.
  • Figure 2A shows an example multiplication for the first part of an example floating point format.
  • Figure 2B shows an example computation of figure 2A for a 1x2 matrix with a 2x2 matrix.
  • Figure 2C shows an example multiplication for the second part of the example floating point format of figure 2A
  • Figure 2D shows an example multiplication for the second part of the example of figure 2C.
  • Figures 2E and 2F show example operations for the processing of figures 2B and 2D.
  • Figure 2G shows the second example multiplication for figure 2A.
  • Figure 2H shows the second example multiplication for figure 2A.
  • Figures 3A, 3B, 3C, and 3D show a flowchart for operation of the floating point multiplier-accumulator.
  • FIG. 1A shows a block diagram for an example Unit Element 100 of the present invention.
  • the previously described dot product multiplication-accumulation is performed on individual columns of the B coefficient matrix, each multiplier-accumulator (MAC) multiplying and accumulating the A row (input) matrix by one of the B column (coefficient) matrices known and is known as a "unit element" performing a MAC function which generates a single sum of input/coefficient products in floating point format.
  • the complete MAC comprises, m such unit elements, each of the m unit elements operating on a unique coefficient column k of the m coefficient columns as: [0025]
  • An input row vector 101 such as [ a i a 2 a n]
  • N simultaneously operating pipeline stages comprising first pipeline stage 107 coupled to a respective second pipeline stage 109 and an adder stage 119, which may be part of the second pipeline stage.
  • the adder stage 119 may be performed separately since there are N second pipeline stages outputting results a binary tree of adders, for example 8 adders 124 feeding 4 adders 140 feeding 2 adders 142 and a final single adder 144. For this reason, the adder stage 119 is shown separate from the second pipeline stage, where each of the N pipeline stages contains identical processing blocks.
  • the first pipeline stage 107 separates the components (sign, exponent, and mantissa) from the pair of multiplicands (in the present example, one of the example sixteen input 101 terms and a corresponding coefficient 103 term), each term a floating point value comprising a sign bit, 8 exponent bits and 7 mantissa bits).
  • An example floating point value may be represented by: where S is the sign bit, and [bn..b0] is the mantissa (for n bits), and E is the exponent (as an unsigned integer, in the range 0-128 for the present example). It is important to note that the mantissa leading term 1 which precedes b n * 2 ⁇ 1 in the above expression is known as a "hidden bit" in the representation of the floating point number, as it is implied by the floating point format but is not expressly present in the floating point format. Accordingly, the range of a mantissa of the above format is always in the range from 1.0 to less than 2.0.
  • Each first pipeline stage 107 has a sign bit processor comprising 102 and 110, a mantissa processor comprising 104, 112, and 116, and an exponent processor comprising 106 and 118.
  • the Find Max Exponent 114 function is shown in dashed lines as it is a separate module which receives exponent sums from all N exponent summers 106 and provides its output to all exponent processors 108.
  • the first pipeline stage mantissa processor comprises mantissa separation 104, mantissa multiply 112, and mantissa normalize 116.
  • the mantissa multiply 112 inputs a pair of 7 bit associated mantissa components from floating point input 101 and floating point coefficient 103, restores the "hidden bit” and generates a 16 bit integer mantissa multiply 112 result as an output.
  • Multiplication of mantissas which represent a range from 1.0 to 1.99X, where X is specific to the floating point format. For example, the maximum value for a bfloatl6 type is 1.9921875, the maximum value for a half precision type
  • the multiplication of the two floating point values may generate a result as large as 3.99Y (Y indicating additional digits not shown), which requires a scaling by 2 to bring the multiplication result into the a range less than 2.0.
  • Such an overflow from mantissa multiplication 112 results in the EXP_INC bit 105 being set by the mantissa normalizer 116.
  • EXP_INC may result in a subsequent adjustment to the exponent difference (EXP_DIFF) or maximum exponent MAX_EXP, handled by the second pipeline exponent adjustment stage 120, which performs an adjustment where needed to MAX_EXP for a stage with the largest exponent sum and EXP_INC set, or alternatively, for other stages which have EXP_DIFF>0, increment or decrement EXP_DIFF based on EXP_INC and whether MAX_EXP was incremented by the stage with the largest MAX_EXP.
  • Restoring the mantissa into a range from 1.0 to less than 2.0 is done by setting the adjust exponent (EXP_INC) bit which is fed to the second pipeline stage.
  • the overflow result may be determined by checking to see if the most significant bit is set after performing the multiply, so for multiplication of two 8 bit values a[7:0*b[7:0] generating a result c[15:0], an overflow occurred if the c[15] bit is set, resulting in the assertion of EXP_INC.
  • the first pipeline stage exponent processor comprises exponent summer 106 which computes the sum of the exponents extracted from the input 101 and coefficient 103 terms for each particular first pipeline stage 107 handling the respective one of the input and coefficient pairs, and operates with commonly shared find max exponent stage 114, which receives exponent sums 106 from all N first pipeline stages and outputs the largest exponent from the exponent sums, known as MAX_EXP 115.
  • the compute exponent difference 118 block also returns a difference for the current exponent sum output by stage 106 compared to the MAX_EXP.
  • the largest MAX_EXP will have an exponent difference (EXP_DIFF) value of 0.
  • the second pipeline stage 109 is operative to receive the corresponding first pipeline stage outputs and perform additional operations.
  • the other stages with smaller exponent sums receive the EXP_INC flag, and for those stages, the EXP_DIFF is incremented if EXP_INC is not set but MAX_INC is set, and alternatively, EXP_DIFF is decremented if EXP_INC is set but MAX_INC is not set.
  • PCS mantissa Pad/Complement Shift
  • the normalized mantissa integer 117 having 8 bits may be padded with four 0 bits prepended (to accommodate 16 maximum non-overflow addition operations), and seventeen Os may be appended to form a first integer form fraction of 29 bits.
  • number of lower bits to preserve to maintain a desired accuracy during the mantissa additions.
  • the integer form fractions output by the Mantissa PCS stage 122 may range from 16 to 32 bits or an even wider range, depending on these parameters.
  • a second step of PCS 122 is to substitute a two's complement of the first integer form fraction if the sign bit 113 is negative, otherwise the first integer form fraction remains unmodified.
  • a third step of PCS 122 is to perform a right shift by the number of positions indicated by adjusted exponent difference (EXP_DIFF) from adjustment stage 120, which uses the difference value 111 from the first pipeline stage and a binary exponent adjust value 105 from normalization, indicating that the multiplication 112 generated an increment in exponent.
  • EXP_DIFF adjusted exponent difference
  • the third step mantissa shift operation of 122 is governed by adjustment stage 120 which uses the adjusted EXP_DIFF 121 to determine how many bit positions the associated mantissa will shift according to the adjusted EXP_DIFF. Certain special cases are also considered by the adjustment 120. For the stage with the largest exponent sum, if EXP_INC from normalizer stage 116 is set indicating a mantissa multiplication overflow and EXP_DIFF is 0 (indicating this is the largest exponent), then MAX_EXP is incremented by 1 and the new value of MAX_INC is sent to the other stages, the increment of MAX_EXP shown as the value MAX_EXP+1.
  • EXP_DIFF For stages other than the stage with the largest exponent sum (stages with EXP_DIFF>0), if EXP_INC from normalizer stage 116 is set and MAX_INC is not set, then EXP_DIFF 121 is decremented by one to acknowledge the change in exponent,whereas if EXP_INC from normalizer stage 116 is not set and MAX_INC is set, then EXP_DIFF is incremented. Other conditions of EXP_INC and MAX_INC do not cause a change in EXP_DIFF. The updated EXP_DIFF value is incorporated into the shift used in the third operation of the mantissa PCS stage 122.
  • the N output values from the Mantissa PCS 122 stage are summed in adder stage 119 as a binary tree of adders 124, 140, 142, and 144, resulting in a single integer form fraction value sent to output stage 146. If the integer form fraction input to 146 is negative, then a negative sign bit component is generated, and a 2s complement of the integer form fraction input to 146 is generated, along with a normalization step to round to the nearest mantissa number and truncated to the mantissa component output format, in the present example, 7 bits (without hidden "1.” bit as previously described), and the exponent component is the MAX_EXP 128 output by adjustment stage 120 with 127 subtracted, as shown in the examples.
  • the sign bit component is 0
  • the mantissa component is rounded and truncated to the number of bits required, and the exponent component is computed as before.
  • the floating point output value is then the sign bit component, the exponent component, and the mantissa component such as 260 of figure 2A.
  • Figure 2A shows the simplified multiplication example of a 1x2 A matrix [ala2] with a 2x2 B matrix ⁇ ll ⁇ 12 - b u 21 b u 2,2 ⁇ showing specific computational examples for further understanding of the invention.
  • the example format of the values is 16 bit floating point format as shown 260, comprising a sign bit 262 followed by 7 bit mantissa 264 and 8 bit exponent 266.
  • the resulting multiplication generates a 1x2 output result, each result is demonstrated in the examples shown in figures 2B and 2D.
  • A2 3BE2 (00111011 1110 0010) becomes:
  • Figures 2B and 2D shows the computational steps of computing al*bll (shown in figure 2B) + a2*b21 (shown in figure 2D) and summed and normalized in figure 2E, according to the process and apparatus of figures 1A and IB.
  • Figures 2G and 2H similarly show the computational steps of computing al*bl2 (shown in figure 2G) + a2*b22 (shown in figure 2H), which are summed and normalized in figure 2F.
  • the first stage mantissa processor comprises extraction stage 204A (corresponding to 104), mantissa multiply stage 206A (corresponding to 112) and mantissa normalize 204A (corresponding to 116). Extraction stage 204A extracts the mantissa plus hidden bit as C8 and CA, as was previously described previously in the floating point number decompositions.
  • exponent processor is shown in figure 2B for the first term as exponent extraction steps 210A, exponent summer 212A generating the value 9'hOFF, and the second term exponent sum is shown in figure 2D as 9'hOEB.
  • the maximum exponent finder 114 indicates 9'hOFF as the MAX_EXP, which is shown in figure 2B 214A and figure 2D 214B.
  • the second pipeline stage operating on the first product and shown in figure 2B receives the sign bit, normalized mantissa, exponent increment, MAX_EXP, and EXP_DIFF values from the first stage.
  • the second pipeline stage operating on the second product and shown in figure 2D receives the sign bit, normalized mantissa, exponent increment, MAX_EXP, and EXP_DIFF values from the first stage.
  • Step 226A performs a normalization of the adder result, in this case, the 5 leading Os match the 5 leading Os of the padding of the PCS step 222A, so no exponent adjustment is necessary, a mantissa rounding is performed from 9DFFF2 to 9E, and the hidden bit is removed to generate mantissa IE, the value is positive, so the sign bit is 0, and the exponent is MAX_EXP -127, or 8'h81, resulting in the output value 16'h409E.
  • Figure 2G and 2H show similar computations for the second column of the B matrix shown in figures 2A and 2C.
  • Figure 2G for the first product shows Sign processor 202C generates sign bit 0, and the mantissa multiplication 206C generates 6D60, which becomes 8'hDA by adding the hidden bit, with an exponent increment of 0, and the exponent processor provides a maximum exponent sum of 9'hFD with difference (EXP_DIFF) of 0.
  • Step 302 computes a determination of MAX_EXP from the sum of exponent terms for each product term across the floating point exponent component of all N terms.
  • Step 304 initiates a series of steps 306, 308, 310, 312, 314, 316, 318, and figure 3B steps of the adjustment stage compute any changes in MAX_EXP and EXP_DIFF, with Figure 3C 340, 342, 344, 346, and 348 performed for each of the N product terms.
  • Step 306 is the separation of sign, mantissa, and exponent, as was previously described in figure 1A.
  • Step 308 performs the sign bit process, performing an exclusive OR of the sign bits and returning a sign bit for later use in step 342.
  • Step 310 restores the hidden mantissa bits prior to multiplication 312, and normalization 314, corresponding to 112 and 116 of figure 1A as previously described.
  • the mantissa is normalized 314, which also generates the EXP_ADJ value previously described.
  • the exponent sum 316 is computed for each result, or preferably is provided for each of the N product terms as part of step 302, which performed this step as part of determining MAX_EXP.
  • the exponent difference (EXP_DIFF) from MAX_EXP is computed in step 318, which leads to step 319 of figure 3B.
  • FIG. 3B shows the adjustment stage 120 for each of the N second pipeline stages of figure 1A.
  • Other combinations of EXP_INC and MAX_INC do not adjust EXP_DIFF 326.
  • Figure 3C shows a continuation of processing of figure 3B, showing the mantissa PCS steps of figure 1A 122, as padding 340, conditional ones complement 344 if the sign bit is negative 342 from step 308, shifting by EXP_DIFF in step 346, and the output of a single integer form fraction in step 348.
  • Each of the N product terms generates the integer form fraction output 348.
  • Figure 3D shows the summing 346 of all product terms output in step 348, after which the sum is normalized to 8 bits, sign adjustments made (taking the two's complement and setting the sign bit to 1 if a negative sum results), and adjusting the exponent, as was described in step 146 of figure IB.
  • N integer form fractions
  • first pipeline stage 107 and second pipeline stage 109 may be used in sequence with each coefficient pair, the output values being sent to an accumulating adder stage 119, which simply adds the new result to the previous one N for each of the N cycles until complete, with the normalization 146 occurring as before.
  • MAX_EXP for the sum of exponents of the N pairs of floating point values must be determined prior to the sequential processing.
  • a separate MAX_EXP processor which determines MAX_EXP may be used to scan the N pairs of exponents.
  • the apparatus may be practiced as N pipeline stages operating concurrently, each pipeline stage forming an integer form fraction for use by a summing stage, with a first and second pipeline stage, so that each clock cycle generates a new MAC result.
  • the apparatus may be practiced as N pipeline stages operating concurrently, each pipeline stage forming an integer form fraction for use by a summing stage, with a first and second pipeline stage, so that each clock cycle generates a new MAC result.
  • the invention may be practiced as an apparatus or as a process without limitation to the examples provided merely for understanding the invention.

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Abstract

Un multiplicateur de produit scalaire de vecteur reçoit un vecteur de rangée et un vecteur de colonne en tant que nombres de virgule flottante dans un format de bits de signe plus exposant plus bits de mantisse. Le multiplicateur de produit en points génère une valeur de produit scalaire unique en traitant séparément les bits de signe, les bits d'exposant et les bits de mantisse dans quelques étages de pipeline. Un premier étage de pipeline génère un bit de signe, une mantisse normalisée formée en multipliant des éléments de multiplicandes de paires, et des informations d'exposant. Un second étage de pipeline reçoit les paires multipliées de mantisses normalisées, effectue un ajustement, effectue un remplissage, un complément et un décalage, et additionne les résultats dans un étage d'additionneur. L'entier résultant est normalisé pour générer un bit de signe, un exposant et une mantisse du résultat de virgule flottante.
PCT/US2022/017126 2021-02-21 2022-02-20 Multiplicateur-accumulateur de produit scalaire à virgule flottante WO2022178339A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US17/180,831 US11983237B2 (en) 2021-02-21 2021-02-21 Floating point dot product multiplier-accumulator
US17/180,856 US11893360B2 (en) 2021-02-21 2021-02-21 Process for a floating point dot product multiplier-accumulator
US17/180,856 2021-02-21
US17/180,831 2021-02-21

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4336344A1 (fr) * 2022-09-08 2024-03-13 STMicroelectronics S.r.l. Unité de calcul pour opérations de multiplication et d'accumulation

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070061391A1 (en) * 2005-09-14 2007-03-15 Dimitri Tan Floating point normalization and denormalization
US7493470B1 (en) * 2001-12-07 2009-02-17 Arc International, Plc Processor apparatus and methods optimized for control applications
US20180336028A1 (en) * 2017-05-18 2018-11-22 Fujitsu Limited Processing device and control method of processing device
US20190196785A1 (en) * 2017-12-21 2019-06-27 Qualcomm Incorporated System and method of floating point multiply operation processing
US20200089472A1 (en) * 2018-09-19 2020-03-19 Xilinx, Inc. Multiply and accumulate circuit
WO2020191417A2 (fr) * 2020-04-30 2020-09-24 Futurewei Technologies, Inc. Techniques de calcul de produit scalaire rapide
US20200401414A1 (en) * 2019-06-21 2020-12-24 Flex Logix Technologies, Inc. Multiplier-Accumulator Circuitry and Pipeline using Floating Point Data, and Methods of using Same

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7493470B1 (en) * 2001-12-07 2009-02-17 Arc International, Plc Processor apparatus and methods optimized for control applications
US20070061391A1 (en) * 2005-09-14 2007-03-15 Dimitri Tan Floating point normalization and denormalization
US20180336028A1 (en) * 2017-05-18 2018-11-22 Fujitsu Limited Processing device and control method of processing device
US20190196785A1 (en) * 2017-12-21 2019-06-27 Qualcomm Incorporated System and method of floating point multiply operation processing
US20200089472A1 (en) * 2018-09-19 2020-03-19 Xilinx, Inc. Multiply and accumulate circuit
US20200401414A1 (en) * 2019-06-21 2020-12-24 Flex Logix Technologies, Inc. Multiplier-Accumulator Circuitry and Pipeline using Floating Point Data, and Methods of using Same
WO2020191417A2 (fr) * 2020-04-30 2020-09-24 Futurewei Technologies, Inc. Techniques de calcul de produit scalaire rapide

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4336344A1 (fr) * 2022-09-08 2024-03-13 STMicroelectronics S.r.l. Unité de calcul pour opérations de multiplication et d'accumulation

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