WO2022170898A1 - 信号处理装置及方法 - Google Patents

信号处理装置及方法 Download PDF

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Publication number
WO2022170898A1
WO2022170898A1 PCT/CN2022/070575 CN2022070575W WO2022170898A1 WO 2022170898 A1 WO2022170898 A1 WO 2022170898A1 CN 2022070575 W CN2022070575 W CN 2022070575W WO 2022170898 A1 WO2022170898 A1 WO 2022170898A1
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signal
unit
signal input
output end
baseband
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PCT/CN2022/070575
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English (en)
French (fr)
Inventor
时留成
张万春
王喜瑜
袁静
张作锋
戴征坚
宁东方
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中兴通讯股份有限公司
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Publication of WO2022170898A1 publication Critical patent/WO2022170898A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H04B2001/0408—Circuits with power amplifiers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the present application relates to the field of communication technologies, and in particular, to a signal processing apparatus and method.
  • the conventional signal processing apparatus for amplifying a signal has the problem of low power amplifier efficiency in the process of processing the baseband signal of at least one frequency to obtain the amplified signal.
  • the main purpose of the embodiments of the present application is to provide a signal processing apparatus and method, aiming at realizing a signal processing apparatus with high power amplifier efficiency.
  • an embodiment of the present application provides a signal processing apparatus, where the signal processing apparatus includes a baseband signal input module, a signal separation module, a signal modulation module, and a dual-band power amplifier.
  • the baseband signal input module includes N signal input ends and N signal output ends, and the N signal input ends of the baseband signal input module are configured to input N kinds of baseband signals, wherein the N kinds of the baseband signals are The frequency category is greater than or equal to 1 and less than or equal to N, where N is an integer greater than or equal to 1.
  • the signal separation module includes K1 first signal separation units and K2 second signal separation units, wherein the K1 is an integer, the K2 is an integer, and the sum of the values of the K1 and the K2 is equal to the value of N.
  • the signal input end of the first signal separation unit is connected to the signal output end of the baseband signal input module, and the first signal separation unit is configured
  • the first signal separation unit is configured
  • two decomposed signals with the same amplitude and opposite phases are obtained, wherein the modulus value of the integrated baseband signal is at least one of the baseband signals.
  • Two kinds of decomposition signals are obtained by changing according to the inherent change amount; wherein the Ni is an integer greater than or equal to 1 and less than or equal to N, the Nj is an integer greater than or equal to 1 and less than or equal to N, and the parameter includes the amplitude and/or phase.
  • the signal input end of the signal modulation module is connected to the signal output end of the signal separation module, and the signal modulation module is configured to convert 2N kinds of the decomposed signals into synthetic analog signals.
  • the signal input end of the dual-band power amplifier is connected to the signal output end of the signal modulation module, and the dual-band power amplifier is configured to amplify and output the synthesized analog signal.
  • the signal processing apparatus further includes a channel performance compensation module, the channel performance compensation module includes 2N channel performance compensation units, and the signal input of the channel performance compensation unit is The channel performance compensation unit is connected to the signal output end of the signal separation module, the signal output end of the channel performance compensation unit is connected to the signal input end of the signal modulation module, and the channel performance compensation unit is configured to compensate for the separation caused by discrete devices. The difference produced by the parameters of the signal.
  • the embodiments of the present application further provide a signal processing method, which is implemented by the signal processing apparatus described in any of the above technical solutions.
  • FIG. 1 is a schematic structural diagram of a signal processing apparatus provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of another signal processing apparatus provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another signal processing apparatus provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of another signal processing apparatus provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of another signal processing apparatus provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of another signal processing apparatus provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of another signal processing apparatus provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a delay control unit
  • FIG. 9 is a schematic structural diagram of another signal processing apparatus provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of another signal processing apparatus provided by an embodiment of the present application.
  • the conventional signal processing apparatus for amplifying a signal has the problem of low power amplifier efficiency in the process of processing the baseband signal of at least one frequency to obtain the amplified signal.
  • the signal processing device first decomposes the baseband signal to obtain the decomposed signal, and then outputs the amplified analog signal through the dual-frequency power amplifier, so as to ensure that the amplitude and/or phase of the baseband signal is changed to obtain the decomposed signal.
  • the embodiments of the present application provide the following technical solutions, which aim to realize a signal processing device with high power amplifier efficiency.
  • FIG. 1 is a schematic structural diagram of a signal processing apparatus provided by an embodiment of the present application.
  • the signal processing device includes: a baseband signal input module 1, a signal separation (Signal Component Separetion, SCS) module 2, a signal modulation module 3 and a dual-band power amplifier 4;
  • the baseband signal input module 1 includes N signal input terminals 1a and N signal output terminals 1b, the N signal input terminals 1a of the baseband signal input module 1 are used to input N kinds of baseband signals, wherein the frequency types of the N kinds of baseband signals are greater than or equal to 1 and less than or equal to N, where N is an integer greater than or equal to 1;
  • the signal separation module 2 includes K1 first signal separation units 20 and K2 second signal separation units 21, wherein K1 is an integer, K2 is an integer, and the sum of the values of K1 and K2 is equal to The value of N;
  • the signal input end 20a of the first signal separation unit 20 is connected to the signal output end 1b of the baseband signal input module 1, and the first signal separation unit 20 is used for
  • the parameters of the Nith baseband signal are changed according to the amount of change determined by the modulo value of the integrated baseband signal to obtain two decomposed signals with the same amplitude and opposite phases, wherein the modulo value of the integrated baseband signal is the sum of the modulo values of at least one baseband signal;
  • the signal input end 21a of the second signal separation unit 21 is connected to the signal output end 1b of the baseband signal input module 1, and the second signal separation unit 21 is used to change the parameters of the Njth baseband signal according to the inherent change amount to obtain two kinds of decomposition signal; wherein, Ni is an integer greater than or equal to 1 and less than or equal to N, Nj is an integer greater than or equal to 1 and less than or equal to N, and the parameters include amplitude and/or phase;
  • the signal processing apparatus further includes a channel performance compensation module 5, the channel performance compensation module 5 includes 2N channel performance compensation units 50, and the signal input end 50a of the channel performance compensation unit 50 is connected to the signal separation module 2 is connected to the signal output terminal 2, and the signal output terminal 50b of the channel performance compensation unit 50 is connected to the signal input terminal 3a of the signal modulation module 3.
  • the channel performance compensation unit 50 is used to compensate the discrete device for the difference in the parameters of the decomposed signal.
  • FIG. 1a shows a schematic structural diagram of a signal processing apparatus when K1 is 1 and K2 is 1.
  • Fig. 1b shows a schematic structural diagram of the signal processing apparatus when K1 is 2 and K2 is 0.
  • Fig. 1c shows a schematic structural diagram of the signal processing apparatus when K1 is 0 and K2 is 2.
  • the embodiments of the present application do not specifically limit the number of the first signal separation unit 20 and the second signal separation unit 21 in FIG. 1a, and do not specifically limit the number of the first signal separation unit 20 in FIG. 1b.
  • the number of separation units 21 is not particularly limited.
  • the signal processing apparatus shown in FIG. 1 when the value of N is 1, the signal processing apparatus can amplify and output a baseband signal of one frequency.
  • the signal processing apparatus can amplify and output multiple baseband signals of one frequency.
  • the signal processing apparatus shown in FIG. 1a, FIG. 1b and FIG. 1c when the value of N is greater than or equal to 2, and the frequencies of N kinds of the baseband signals are greater than 1, the signal processing apparatus can realize the processing of at least two kinds of baseband signals.
  • the baseband signal of the frequency is amplified and output.
  • the baseband signal input module 1 includes N signal input ends 1a and N signal output ends 1b, so that the signal processing apparatus can access N kinds of baseband signals.
  • the principle that the signal separation module 2 changes the parameters of N kinds of baseband signals to obtain 2N kinds of decomposed signals is as follows:
  • the principle that the first signal separation unit 20 is used to obtain two decomposed signals with the same amplitude and opposite phases by changing the parameters of the Nith baseband signal according to the change amount determined by the modulus value of the integrated baseband signal is as follows:
  • the first signal separation unit 20 can obtain two decomposed signals with the same amplitude and opposite phases for the same baseband signal. For example, the first signal separation unit 20 uses the modulus value of the Ni-th baseband signal as the modulus value of the integrated baseband signal to determine the amount of change in the parameters of the Ni-th baseband signal, and then obtains two decomposed signals from the Ni-th baseband signal.
  • the two decomposed signals are signals of the same amplitude and opposite phases.
  • the first signal separation unit 20 may determine the amount of change to the parameter of the Ni-th baseband signal according to the sum of the modulus value of the Ni-th baseband signal and the modulus value of at least one of the other baseband signals, and then the Ni-th baseband signal is determined by the Ni-th type of baseband signal.
  • a baseband signal is used to obtain two decomposed signals.
  • the first signal separation unit 20 is used to change the parameters of the Nith baseband signal according to the change amount determined by the modulus value of the integrated baseband signal to obtain two decomposed signals with the same amplitude and opposite phases, and pass the signal of the first signal separation unit 20.
  • the output terminal 20b outputs.
  • the principle that the second signal separation unit 21 is used to obtain two kinds of decomposed signals by changing the parameters of the Njth baseband signal according to the inherent change amount is as follows:
  • the second signal separation unit 21 changes the parameters of the Njth baseband signal according to the inherent change amount of the parameters of the baseband signal to obtain two kinds of decomposed signals, and the parameters of the two kinds of decomposed signals may be the same or different.
  • the second signal separation unit 21 is configured to change the parameters of the Njth baseband signal according to the inherent change amount to obtain two kinds of decomposed signals, which are output through the signal output terminal 21 b of the second signal separation unit 21 . It should be noted that the values of Ni and Nj may be the same or different.
  • the signal separation module 2 includes a first signal separation unit 20 and a second signal separation unit 21 at the same time, so that the signal separation module 2 separates two kinds of baseband signals to obtain 4 kinds of decomposed signals.
  • the signal separation module 2 separates N kinds of baseband signals to obtain 2N kinds of decomposed signals, wherein N is greater than or equal to 2 .
  • the first signal separation unit 20 can change the parameters of the Nith baseband signal according to the change amount determined by the modulus value of the integrated baseband signal to obtain two decomposed signals with the same amplitude and opposite phases, its internal structure is relatively complex, and usually requires multiplication It also needs the cooperation of the modulo circuit to obtain the modulo value of the integrated baseband signal. Therefore, the above-mentioned signal separation module 2 reduces the complexity of the signal separation module 2 and the architecture of the entire signal processing apparatus compared to the signal separation module 2 that only includes the first signal separation unit 20 , thereby reducing the discrete components of discrete devices.
  • the difference generated by the parameters ensures that the parameters of the synthesized analog signal entering the dual-band power amplifier 4 are matched, thereby optimizing the linearity index of the amplified signal output by the dual-band power amplifier 4, and improving the power amplifier efficiency of the signal processing device.
  • the above-mentioned signal separation module 2 can change the parameters of the Njth baseband signal by the second signal separation unit 21 according to the inherent change amount of the parameters of the baseband signal to obtain two signals.
  • This kind of decomposition signal can also change the amount of change determined by the parameter of the Nith baseband signal and the modulus value of the integrated baseband signal to obtain two decomposed signals with the same amplitude and opposite phases, which improves the amount of change of the parameters of the baseband signal by the signal processing device. Therefore, the difference between the parameters of the decomposed signals obtained from different baseband signals is reduced, so as to ensure that the parameters of the synthesized analog signal entering the dual-band power amplifier 4 are matched, and the amplified signal output by the dual-band power amplifier 4 is optimized.
  • the linear index improves the power amplifier efficiency of the signal processing device.
  • the signal separation module 2 only includes the first signal separation unit 20, or only includes the second signal separation unit 21, and the signal separation module 5 compensates for the separation of the discrete device pair through the channel performance compensation unit 50
  • the difference generated by the parameters of the signal reduces the difference generated by the discrete type of the discrete device to the parameters of the decomposed signal, so as to ensure that the parameters of the synthesized analog signal entering the dual-band power amplifier 4 are matched, thereby optimizing the output of the dual-band power amplifier 4.
  • the linear index of the amplified signal improves the power amplifier efficiency of the signal processing device.
  • the number of the first signal separation units 20 in FIG. 1b is greater than 1, and when the number of the second signal separation units 21 in FIG. 1c is greater than 1, the signal separation module 2 separates N kinds of baseband signals to obtain 2N kinds of decomposed signals, where N is greater than 1 or equal to 2.
  • the signal processing apparatus can amplify a baseband signal of at least one frequency and output a high-power amplified signal.
  • the signal separation module 2 in the signal processing device includes the technical solution of the first signal separation unit 20 and the second signal separation unit 21.
  • both Two kinds of decomposed signals can be obtained by changing the parameters of the same baseband signal by the second signal separation unit 21 according to the inherent change of the parameters of the baseband signal, and the parameters of the same baseband signal can be changed according to the modulo value of the integrated baseband signal.
  • Two kinds of decomposed signals with the same amplitude and opposite phases are obtained by changing the amount of the signal processing device, which improves the accuracy of the change of the parameters of the baseband signal by the signal processing device, thereby reducing the difference in the parameters of the decomposed signals obtained by different baseband signals.
  • the parameters of the synthesized analog signal entering the dual-band power amplifier 4 are matched, thereby optimizing the linearity index of the amplified signal output by the dual-band power amplifier 4 and improving the power amplifier efficiency of the signal processing device.
  • the signal separation module 2 in the signal processing apparatus only includes the technical solution of the first signal separation unit 20 or the second signal separation unit 21, and the channel performance compensation unit 50 compensates for the difference in the parameters of the decomposed signal generated by the discrete devices, reducing the number of discrete devices.
  • the discrete type is the difference between the parameters of the decomposed signal to ensure that the parameters of the synthesized analog signal entering the dual-band power amplifier 4 are matched, thereby optimizing the linearity index of the amplified signal output by the dual-band power amplifier 4, and improving the signal processing device. amplifier efficiency.
  • the embodiments of the present application also provide the following technical solutions:
  • FIG. 2 is a schematic structural diagram of another signal processing apparatus provided by an embodiment of the present application. Based on the above technical solution, referring to FIG. 2 , when K1 is greater than or equal to 1, and K2 is greater than or equal to 1, the signal processing apparatus further includes a channel performance compensation module 5 .
  • the signal separation module 2 in the signal processing device includes the technical solution of the first signal separation unit 20 and the second signal separation unit 21.
  • Both the parameters of the same baseband signal can be obtained by changing the parameters of the same baseband signal by the second signal separation unit 21 according to the inherent change amount of the parameters of the baseband signal, and the parameters of the same baseband signal can be determined according to the modulus value of the integrated baseband signal.
  • the change amount is changed to obtain two decomposed signals with the same amplitude and opposite phase, which improves the change accuracy of the signal processing device for the change amount of the parameters of the baseband signal, and the channel performance compensation unit 50 compensates the discrete device for the parameters of the decomposed signal.
  • the difference reduces the difference between the discrete components of the discrete device and the parameters of the decomposed signal, so as to further ensure that the parameters of the synthesized analog signal entering the dual-band power amplifier 4 match, and further optimize the output of the dual-band power amplifier.
  • the linear index further improves the power amplifier efficiency of the signal processing device.
  • the specific structure of the first signal separation unit 20 is detailed below. Taking the signal processing apparatus shown in FIG. 2 as an example, the structure of the first signal separation unit 20 is refined to obtain a schematic structural diagram of another signal processing apparatus provided by the embodiment of the present application shown in FIG. 3 .
  • the first signal separation unit 20 includes a first memory 201 storing a first lookup table, a first multiplier 202, a second memory 203 storing a second lookup table, and a second memory 203 storing a second lookup table.
  • the first lookup table (Lookup Table, LUT) includes the variation of the M groups of parameters, and the second lookup table includes the variation of the M groups of parameters, where M is an integer greater than or equal to 1;
  • the first multiplier The first signal input end 202a of 202 is connected to the signal output end 201a of the first memory 201, the second signal input end 202b of the first multiplier 202 is connected to the signal output end 1b of the baseband signal input module 1, and the first multiplier 202
  • the signal output terminal 202c of the first signal separation unit 20 is used as the signal output terminal 20b;
  • the first signal input terminal 204a of the second multiplier 204 is connected to the signal output terminal 203a of the second memory 203, and the second multiplier 204
  • the signal input end 204b is connected to the signal output end 1b of the baseband signal input and output module 1, and the signal output end 204c of the second multiplier 204 is used as the signal output end 20b of the first signal separation unit 20;
  • the signal input end 6a of the modulo circuit 6 in FIG. 3 is connected to a signal output end 1b of the baseband signal input module 1, and the modulo circuit 6 is used to perform modulo processing on a baseband signal to obtain a comprehensive baseband signal.
  • Modulo value where the modulo value of the integrated baseband signal is the modulo value of a baseband signal.
  • the number of the signal output ends 1b connected between the signal input end 6a of the modulo circuit 6 and the signal input module 1 is not limited.
  • the modulo circuit 6 sends the modulo value of the integrated baseband signal to the first memory 201 and the second memory 203, and the first memory 201 finds the variation of the parameter corresponding to the first multiplier 202 according to the modulo value of the integrated baseband signal.
  • the multiplier 202 is configured to change the parameter of the Ni-th baseband signal according to the variation of the parameter corresponding to the first multiplier 202 to obtain the first decomposed signal.
  • the second memory 203 finds the variation of the parameter corresponding to the second multiplier 204 according to the modulo value of the integrated baseband signal. The change amount is changed to obtain the second decomposition signal.
  • the difference between the change amount of the parameter corresponding to the first multiplier 202 and the change amount of the parameter corresponding to the second multiplier 204 is used to realize the first decomposed signal and the second decomposed signal with the same amplitude and opposite phases. Signal.
  • the first memory 201 includes a control unit, and the control unit sends a selection signal according to the modulo value of the integrated baseband signal to find the variation of the parameter corresponding to the first multiplier 202 .
  • the second memory 203 includes a control unit, and the control unit sends a selection signal according to the modulo value of the integrated baseband signal to find the variation of the parameter corresponding to the second multiplier 204 .
  • the dual-frequency power amplifier when the dual-frequency power amplifier is in the saturation region, it can linearly amplify the input signal, and the amplification factor is precisely controllable. If the linearity of the dual-band power amplifier is not high, it will cause nonlinear distortion of the amplified signal output by the dual-band power amplifier 4 and the input signal.
  • the signal processing device for amplifying and outputting the baseband signal of at least one frequency, on the basis of ensuring that the signal processing device has a certain efficiency for the amplified signal output by the dual-band power amplifier 4, in order to further improve the signal processing
  • the linearity of the device the following technical solutions are also provided in the embodiments of the present application:
  • FIG. 4 is a schematic structural diagram of another signal processing apparatus provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of another signal processing apparatus provided by an embodiment of the present application. 4 and 5, the baseband signal input module 1 includes N digital predistortion units 10; the modulo circuit 6 includes P modulo units 60, when P is equal to 1; the signal processing device Also includes a multi-channel signal selection unit 70, the first signal input terminal 70a of the multi-channel signal selection unit 70 is connected to the signal input terminal 10a of the digital predistortion unit 10, and the second signal input terminal 70b of the multi-channel signal selection unit 70 is connected to the signal input terminal 10a of the digital predistortion unit 10.
  • the signal output end 10b of the digital predistortion unit 10 is connected, and the signal output end 70c of the multi-channel signal selection unit 70 is connected with the signal input end 60a of the modulo unit 60.
  • the modulo unit 60 is used to obtain the modulo of the integrated baseband signal according to the baseband signal.
  • the signal output terminal 60b of the modulo unit 60 is connected to the signal input terminal 201b of the first memory 201 and the signal input terminal 203b of the second memory 203, respectively.
  • the signal processing apparatus further includes P multiplex signal selection units 70 and a first signal synthesis unit 71; the first signal input end 70a of the multiplex signal selection unit 70 is connected to the digital The signal input terminal 10a of the predistortion unit 10 is connected, the second signal input terminal 70b of the multi-channel signal selection unit 70 is connected to the signal output terminal 10b of the digital pre-distortion unit 10, and the signal output terminal 70c of the multi-channel signal selection unit 70 is connected to the fetcher.
  • the signal input end of the modulo unit 60 is connected, and the modulo unit 60 is used to obtain the modulo value of the baseband signal according to the baseband signal; the signal input end 71a of the first signal synthesis unit 71 is connected with the signal output end 60b of the modulo unit 60, the first The signal synthesis unit 71 is used for summing the modulo values of at least one baseband signal to obtain the modulo value of the integrated baseband signal.
  • the signal input terminal 203b of the second memory 203 is connected.
  • the baseband signal input module 1 adopts N digital predistortion (Digital Predistortion, DPD) units 10 to perform predistortion processing on N kinds of baseband signals respectively, so as to ensure that the signal processing apparatus can perform predistortion processing on the dual-band signals.
  • DPD Digital Predistortion
  • the first signal combining unit 71 is an adder, but the specific device selection of the first combining unit 71 in this embodiment of the present application is not limited thereto.
  • the multi-channel signal selection unit 70 in FIG. 4 can select the baseband signal before entering the digital predistortion unit 10 and send it to the modulo unit 60, or can select the baseband signal processed by the digital predistortion unit 10 and send it to the extractor. Mold unit 60 .
  • FIG. 4 only shows that the multi-channel signal selection unit 70 is connected to the signal input end 10a or the signal output end 10b of one digital predistortion unit 10, and may also be connected to the signals of two or more digital predistortion units 10. The input end 10a or the signal output end 10b is connected, which is not limited in this embodiment of the present application.
  • the multiplex signal selection unit 70 can select the baseband signal before entering any digital predistortion unit 10 and send it to the modulo unit 60 , or can select any baseband signal processed by the digital predistortion unit 10 and send it to the modulo unit 60 .
  • the modulo unit 60 performs modulo processing according to a baseband signal to obtain the modulo value of the integrated baseband signal
  • the first memory 201 finds the corresponding modulo value of the first multiplier 202 according to the modulo value of the integrated baseband signal.
  • the first multiplier 202 is used to change the parameter of the Nith baseband signal according to the variation of the parameter corresponding to the first multiplier 202 to obtain the first decomposed signal.
  • the second memory 203 finds the variation of the parameter corresponding to the second multiplier 204 according to the modulo value of the integrated baseband signal. The change amount is changed to obtain the second decomposition signal.
  • the number of the multi-channel signal selection unit 70 and the modulo unit 60 is no longer limited to one, each modulo unit 60 performs modulo processing according to a baseband signal, and a plurality of modulo units 60 can obtain the modulo values of various baseband signals, and the first signal synthesis unit 71 can perform summation processing on the modulo values of the various baseband signals to obtain the modulo value of the integrated baseband signal.
  • the first memory 201 finds the variation of the parameter corresponding to the first multiplier 202 according to the modulo value of the integrated baseband signal. The amount is changed to obtain the first decomposed signal.
  • the second memory 203 finds the variation of the parameter corresponding to the second multiplier 204 according to the modulo value of the integrated baseband signal. The change amount is changed to obtain the second decomposition signal.
  • the embodiment of the present application also provides the following technical solutions:
  • FIG. 6 is a schematic structural diagram of another signal processing apparatus provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of another signal processing apparatus provided by an embodiment of the present application. 6 and 7, the signal processing apparatus further includes a coupler 72, a power detection unit 73 and an adaptive parameter extraction unit 74; the signal input end 72a of the coupler 72 and the dual-band power amplifier 4
  • the signal output terminal 72b of the coupler 72 is connected to the antenna;
  • the signal input terminal 73a of the power detection unit 73 is connected to the second signal output terminal 72c of the coupler 72 for detecting the dual-band power amplifier 4
  • the signal input end 74a of the adaptive parameter extraction unit 74 is connected to the signal output end 73b of the power detection unit 73, and the adaptive parameter extraction unit includes 2*K1 signal output ends 74b, the first memory 201
  • the control terminal 201c is connected to the signal output terminal 74b of the adaptive parameter extraction unit 74,
  • the adaptive parameter extraction unit 74 is used to The numerical relationship between the power of the amplified signal output by the power amplifier 4 and the preset power, adjust the variation of the parameter output by the signal output terminal 201a of the first memory 201, and the variation of the parameter output by the signal output terminal 203a of the second memory 203 .
  • the power detection unit 73 is used for detecting the power of the amplified signal output by the dual-band power amplifier 4
  • the adaptive parameter extraction unit 74 is used for the numerical relationship between the power of the amplified signal output by the dual-band power amplifier 4 and the preset power, Sending an adjustment signal, the first memory 201 adjusts the variation of the parameter output by the signal output end 201a of the first memory 201 based on the adjustment signal; the second memory 203 adjusts the change of the parameter output by the signal output end 203a of the second memory 203 based on the adjustment signal
  • the parameters of the two decomposed signals obtained by the first signal separation unit 20 are adjusted accordingly.
  • the above technical solution realizes that the baseband signal of at least one frequency is amplified on the basis of ensuring that the power of the amplified signal output by the dual-band power amplifier 4 is equal to the preset power, thereby improving the power amplifier efficiency of the signal processing device.
  • the second signal separation unit 21 includes a first amplitude and phase adjuster 210 and a second amplitude and phase adjuster 211.
  • the signal of the first amplitude and phase adjuster 210 The input end 210a is connected to the signal output end of the baseband signal input module 1 (that is, the signal output end 10b of the digital predistortion unit 10 in the figure), and the first amplitude and phase adjuster 210 is used to adjust the parameters of the Njth baseband signal according to The first intrinsic component change is changed to obtain a third decomposed signal; the signal input end 211a of the second amplitude and phase adjuster 211 is connected to the signal output end of the baseband signal input module 1, and the second amplitude and phase adjuster 211 is used for The parameters of the Njth baseband signal are changed according to the second intrinsic component change amount to obtain a fourth decomposed signal.
  • the first amplitude and phase adjuster 210 changes the parameters of the Njth baseband signal according to the inherent change amount of the parameters of the baseband signal to obtain a third decomposed signal
  • the second amplitude and phase adjuster 211 is used for the Njth type of baseband signal.
  • the parameters of the baseband signal are changed according to the second intrinsic component change to obtain the fourth decomposed signal, and the parameters of the two decomposed signals may be the same or different.
  • the first amplitude and phase adjuster 210 outputs the third decomposed signal through the signal output terminal 210b of the first amplitude and phase adjuster 210, and the second amplitude and phase adjuster 211 passes the fourth decomposed signal through the second amplitude and phase adjuster.
  • the signal output terminal 211b of 211 outputs.
  • the signal processing device further includes a delay control module, and the delay control module includes 2N delay control units 80 ;
  • the signal input end 80a of the unit 80 is connected to the signal output end of the signal separation module 2, or the signal input end of the delay control unit 80 is connected to the signal output end of the channel performance compensation unit 50;
  • the signal output end of the delay control unit 80 80 b is connected to the signal input end of the signal modulation module 3 , and the time delay control unit 80 is used for synchronously inputting the decomposed signal to the signal input end of the dual-band power amplifier 4 .
  • the setting can ensure that the synthesized analog signal enters the dual-band power amplifier 4 synchronously, thereby improving the power amplifier efficiency of the signal processing device.
  • the delay control unit 80 can realize the synchronization of different signals by controlling the time interval of the sampling points of the signals through a common delay control circuit.
  • the technical solution in which the signal input end 80a of the delay control unit 80 is directly connected to the signal output end of the signal separation module 2 is a further improvement on the solution shown in FIG. 1a.
  • the signal input end 80a of the delay control unit 80 is directly connected to the signal output end 50b of the channel performance compensation unit 50, which is a further improvement of the solutions shown in FIGS. 1b, 1c and 2 .
  • the structure of the delay control unit 80 is further refined below.
  • FIG. 8 is a schematic structural diagram of a delay control unit.
  • the delay control unit 80 includes a coarse delay control subunit 801 and a fine delay control subunit 802 .
  • the signal input end 801a is connected to the signal output end of the signal separation module 2, or the signal input end 801a of the coarse delay control subunit 801 is connected to the signal output end 50b of the channel performance compensation unit 50;
  • the signal input end 802a is connected to the signal output end 801b of the coarse delay control subunit 801, and the signal output end 802b of the fine delay control subunit 802 is connected to the signal input end of the signal modulation module 3, wherein the coarse delay control subunit
  • the control accuracy of 801 for synchronously inputting the decomposed signal to the signal input terminal of the dual-band power amplifier is less than that of the precise delay control subunit 802 for synchronously inputting the decomposed signal to the signal input terminal of the dual-band power amplifier 4 .
  • the technical solution in which the signal input end 801a of the coarse delay control subunit 801 is directly connected to the signal output end of the signal separation module 2 is a further improvement on the solution shown in FIG. 1a.
  • the signal input end 801a of the coarse delay control subunit 801 is directly connected to the signal output end 50b of the channel performance compensation unit 50, which is a further improvement of the solutions shown in FIGS. 1b, 1c and 2 .
  • the delay control unit 80 can realize the synchronization of different signals by controlling the time interval of the sampling points of the signals through a common delay control circuit.
  • the time interval between the sampling points of the signal by the coarse delay control subunit 801 is greater than the time interval between the sampling points of the signal by the fine delay control subunit 802, so that the coarse delay control subunit 801 can synchronously input the decomposed signal to the dual-band power
  • the control precision of the signal input terminal of the amplifier is less than the control precision of the fine delay control subunit 802 for synchronously inputting the decomposed signal to the signal input terminal of the dual-band power amplifier 4 .
  • the coarse delay control subunit 801 and the fine delay control subunit 802 jointly complete the control of the synchronization of the decomposed signals, which improves the control accuracy and the power amplifier efficiency of the signal processing device.
  • the specific structure of the signal modulation module 3 is further refined below.
  • FIG. 9 is a schematic structural diagram of another signal processing apparatus provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of another signal processing apparatus provided by an embodiment of the present application.
  • the signal modulation module 3 includes a first digital-analog converter (Digital-Analog Converter, DAC) unit 30 and a first Two digital-to-analog conversion units 31;
  • the signal input terminal 30a of the first digital-to-analog conversion unit 30 is used as the signal input terminal of the signal modulation module 3
  • the signal output terminal 30b of the first digital-to-analog conversion unit 30 is used as the signal output terminal of the signal modulation module 3
  • the first digital-to-analog conversion unit 30 is used to convert one of the two decomposed signals into an analog signal
  • the signal input end 31a of the second digital-to-analog conversion unit 31 is used as the signal input end of the signal modulation module 3
  • the signal output terminal 31b of the conversion unit 31 serves as the signal output terminal of the signal modulation module 3, and the second digital-to-analog conversion unit 31 is used to convert the other of the two decomposed signals into an analog signal.
  • the signal modulation module includes a first digital-to-analog conversion unit 30, a second digital-to-analog conversion unit 31, a second signal synthesis unit 32 and a first digital-to-analog conversion unit 31.
  • the signal input end 32a of the second signal synthesis unit 32 serves as the signal input end of the signal modulation module 3, the signal input end 30a of the first digital-to-analog conversion unit 30 and the signal output end of the second signal synthesis unit 32 32b is connected, and the signal output end 32b of the second signal synthesis unit 32 is used as the signal output end of the signal modulation module 3;
  • the second signal synthesis unit 32 is used for synthesizing N kinds of decomposed signals in the 2N kinds of decomposed signals into the first synthesized signal;
  • the signal input end 33a of the third signal synthesis unit 33 is used as the signal input end of the signal modulation module 3, the signal input end 31a of the second digital-to-analog conversion unit 31 is connected to the signal output end 33b of the third signal synthesis unit 33, and the third signal
  • the signal output end 33b of the synthesis unit 33 is used as the signal output end of the signal modulation module 3;
  • the third signal synthesis unit 33 is used for synthesizing the other N
  • the second signal synthesis unit 32 and the third signal synthesis unit 33 are adders, but the specific device selection of the second signal synthesis unit 32 and the third signal synthesis unit 33 is not limited in this embodiment of the present application.
  • the baseband signal is one type, and the first digital-to-analog conversion unit 30 is used to convert one of the two decomposed signals into an analog signal; the second digital-to-analog conversion unit 31 is used to convert the other of the two decomposed signals to an analog signal.
  • the second signal synthesis unit 32 is used for synthesizing N kinds of decomposed signals among the 2N kinds of decomposed signals into a first synthesized signal
  • the third signal synthesis unit 33 is used for decomposing the 2N kinds of decomposed signals
  • the other N kinds of decomposed signals in the signal are synthesized into a second synthesized signal
  • the first digital-to-analog conversion unit 30 is used to convert the first synthesized signal into a first synthesized analog signal
  • the second digital-to-analog conversion unit 31 is used to convert the second synthesized signal.
  • the signal is converted to a second composite analog signal.
  • the signal modulation module 3 is used to convert 2N kinds of decomposed signals into synthetic analog signals, thereby realizing that the signal processing device can amplify the baseband signal of at least one frequency and output the amplified signal with high power.
  • the dual-band power amplifier 4 is an analog device and can only amplify analog signals.
  • the first digital-to-analog conversion unit 30 is used to convert the first synthesized signal into a first synthesized analog signal
  • the second digital The analog conversion unit 31 is used to convert the second synthesized signal into a second synthesized analog signal, so that the input terminal of the dual-band power amplifier 4 can input the first synthesized analog signal and the second synthesized analog signal, and then amplify and output them.
  • the embodiments of the present application also provide the following technical solutions;
  • the signal processing device further includes a frequency adjustment module, and the frequency adjustment module includes 2N frequency adjustment units 90,
  • the signal input end 90a of the frequency adjustment unit 90 is connected to the signal output end of the signal separation module 2, or the signal input end 90a of the frequency adjustment unit 90 is connected to the signal output end 50b of the channel performance compensation unit 50; the signal of the frequency adjustment unit 90
  • the output end 90b is connected to the signal input end of the signal modulation module 3, and the frequency adjustment unit 90 is used for adjusting the frequency of the decomposed signal to a preset intermediate frequency frequency.
  • the frequency adjustment module includes 2N frequency adjustment units 90, and the technical solution that the signal input end 90a of the frequency adjustment unit 90 is directly connected to the signal output end of the signal separation module 2 is a further improvement for the solution shown in FIG. 1a. .
  • the technical solution that the signal input end 90a of the frequency adjustment unit 90 is directly connected to the signal output end 50b of the channel performance compensation unit 50 is a further improvement to the solutions shown in FIGS. 1b , 1c and 2 .
  • the frequency adjustment unit 90 may increase or decrease the frequency of the decomposed signal, and set the frequency of the decomposed signal to be the same as the preset intermediate frequency.
  • This embodiment of the present application further provides a signal processing method, which is implemented by the signal processing apparatuses in the above technical solutions.
  • the implementation principle and technical effect of the signal processing method provided by this embodiment are similar to those of the above-mentioned embodiments, and no Repeat.
  • the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be composed of several physical components Components execute cooperatively.
  • Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit .
  • Such software may be distributed on computer-readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media).
  • Computer storage media includes both volatile and nonvolatile implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules or other data flexible, removable and non-removable media.
  • Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cartridges, magnetic tape, magnetic disk storage or other magnetic storage devices, or may Any other medium used to store desired information and which can be accessed by a computer.
  • communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and can include any information delivery media, as is well known to those of ordinary skill in the art .

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Abstract

一种信号处理装置及方法。该信号处理装置包括：基带信号输入模块(1)、信号分离模块(2)、信号调制模块(3)和双频段功率放大器(4)；基带信号输入模块配置为(1)输入N种基带信号；信号分离模块(2)包括K1个第一信号分离单元(20)和K2个第二信号分离单元(21)；第一信号分离单元(20)配置为对第Ni种基带信号的参数按照综合基带信号模值确定的改变量进行改变得到两种分解信号；第二信号分离单元(21)配置为对第Nj种基带信号的参数按照固有改变量进行改变得到两种分解信号；K1为0或者K2为0时，信号处理装置还包括用于补偿分立器件对分解信号的参数产生的差异的通道性能补偿模块(5)。

Description

信号处理装置及方法
相关申请的交叉引用
本申请基于申请号为202110181839.X、申请日为2021年2月09日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及通信技术领域，尤其涉及一种信号处理装置及方法。
背景技术
随着无线通信技术的发展，对于将至少一种频率的基带信号进行放大并射频发射的信号处理装置的需求越大越大。
传统的对信号进行放大的信号处理装置为了应对这一境况，在将至少一种频率的基带信号进行处理得到放大信号的过程中，存在功放效率低的问题。
发明内容
本申请实施例的主要目的是提出一种信号处理装置及方法，旨在实现一功放效率高的信号处理装置。
为实现上述目的，本申请实施例提供了信号处理装置，所述信号处理装置包括基带信号输入模块、信号分离模块、信号调制模块和双频段功率放大器。
所述基带信号输入模块包括N个信号输入端和N个信号输出端，所述基带信号输入模块的N个所述信号输入端配置为输入N种基带信号，其中，N种所述基带信号的频率种类大于或等于1且小于或等于N，所述N为大于或等于1的整数。
所述信号分离模块包括K1个第一信号分离单元和K2个第二信号分离单元，其中，所述K1为整数，所述K2为整数，且所述K1和所述K2的取值之和等于所述N的取值。
所述K1大于或等于1，且所述K2大于或等于1时，所述第一信号分离单元的信号输入端与所述基带信号输入模块的信号输出端连接，所述第一信号分离单元配置为对第Ni种所述基带信号的参数按照综合基带信号模值确定的改变量进行改变得到两种振幅相同且相位相反的分解信号，其中所述综合基带信号模值为至少一种所述基带信号的模值之和；所述第二信号分离单元的信号输入端与所述基带信号输入模块的信号输出端连接，所述第二信号分离单元配置为对第Nj种所述基带信号的参数按照固有改变量进行改变得到两种分解信号；其中所述Ni为大于或等于1且小于或等于N的整数，所述Nj为大于或等于1且小于或等于N的整数，所述参数包括振幅和/或相位。
所述信号调制模块的信号输入端与所述信号分离模块的信号输出端连接，所述信号调制模块配置为将2N种所述分解信号中转换为合成模拟信号。
所述双频段功率放大器的信号输入端与所述信号调制模块的信号输出端连接，所述双频段功率放大器配置为放大所述合成模拟信号并输出。
或者，所述K1为0或者所述K2为0时，所述信号处理装置还包括通道性能补偿模块，所述通道性能补偿模块包括2N个通道性能补偿单元，所述通道性能补偿单元的信号输入端与所述信号分离模块的信号输出端连接，所述通道性能补偿单元的信号输出端与所述信号调制模块的信号输入端连接，所述通道性能补偿单元配置为补偿分立器件对所述分解信号的参数产生的差异。
为实现上述目的，本申请实施例还提供了一种信号处理方法，通过上述技术方案中任意所述的信号处理装置实现。
附图说明
图1是本申请实施例提供的一种信号处理装置的结构示意图；
图2是本申请实施例提供的另一种信号处理装置的结构示意图；
图3是本申请实施例提供的又一种信号处理装置的结构示意图
图4是本申请实施例提供的又一种信号处理装置的结构示意图；
图5是本申请实施例提供的又一种信号处理装置的结构示意图；
图6是本申请实施例提供的又一种信号处理装置的结构示意图；
图7是本申请实施例提供的又一种信号处理装置的结构示意图；
图8是时延控制单元的结构示意图；
图9是本申请实施例提供的又一种信号处理装置的结构示意图；以及
图10是本申请实施例提供的又一种信号处理装置的结构示意图。
具体实施方式
应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
在后续的描述中，使用用于表示元件的诸如“模块”、“部件”或“单元”的后缀仅为了有利于本申请的说明，其本身没有特有的意义。因此，“模块”、“部件”或“单元”可以混合地使用。
正如上述技术背景技术中所述，传统的对信号进行放大的信号处理装置在将至少一种频率的基带信号进行处理得到放大信号的过程中，存在功放效率低的问题。究其原因，现有技术中信号处理装置先对基带信号进行分解，得到分解信号，然后通过双频功率放大器输出放大的模拟信号，在保证对基带信号的振幅和/或相位进行改变得到分解信号的过程中，要么是在为了实现对于基带信号的振幅和/或相位的改变量精准控制，导致器件复杂度过高；要么是器件复杂度不高，但是对于基带信号的振幅和/或相位的该变量的精准度不高，上述情况均会造成进入信号处理装置的双频段功率放大器的合成模拟信号的参数不匹配，存在功放效率低的问题。
针对上述技术问题，本申请实施例提供了如下技术方案，旨在实现一功放效率高的信号处理装置。
图1是本申请实施例提供的一种信号处理装置的结构示意图。参见图1，该信号处理装置包括：基带信号输入模块1、信号分离(Signal Component Separetion，SCS)模块2、信号调制模块3和双频段功率放大器4；基带信号输入模块1包括N个信号输入端1a和N个信号输出端1b，基带信号输入模块1的N个信号输入端1a用于输入N种基带信号，其中，N种基带信号的频率种类大于或等于1且小于或等于N，N为大于或等于1的整数；信号分离模块2包括K1个第一信号分离单元20和K2个第二信号分离单元21，其中，K1为整数，K2为整数，且K1和K2的取值之和等于N的取值；
所述K1大于或等于1，且所述K2大于或等于1时，第一信号分离单元20的信号输入端20a与基带信号输入模块1的信号输出端1b连接，第一信号分离单元20用于对第Ni种基带信号的参数按照综合基带信号模值确定的改变量进行改变得到两种振幅相同且相位相反的分解信号，其中综合基带信号模值为至少一种基带信号的模值之和；第二信号分离单元21的信号输入端21a与基带信号输入模块1的信号输出端1b连接，第二信号分离单元21用于对第Nj种基带信号的参数按照固有改变量进行改变得到两种分解信号；其中，Ni为大于或等于1且小于或等于N的整数，Nj为大于或等于1且小于或等于N的整数，参数包括振幅和/或相位；信号调制模块3的信号输入端3a与信号分离模块2的信号输出端连接，信号调制模块3用于将2N种分解信号转换为合成模拟信号；双频段功率放大器(Power Amplifier,PA)4的信号输入端与信号调制模块3的信号输出端3b连接，双频段功率放大器4用于放大合成模拟信号并输出；
或者，K1为0或者K2为0时，信号处理装置还包括通道性能补偿模块5，通道性能补偿模块5包括2N个通道性能补偿单元50，通道性能补偿单元50的信号输入端50a与信号分离模块2的信号输出端连接，通道性能补偿单元50的信号输出端50b与信号调制模块3的信号输入端3a连接，通道性能补偿单元50用于补偿分立器件对分解信号的参数产生的差异。
示例性的，图1a示出了K1取值为1，且K2取值为1时的信号处理装置的结构示意图。图1b示出了K1取值为2，且K2取值为0时的信号处理装置的结构示意图。图1c示出了K1取值为0，且K2取值为2时的信号处理装置的结构示意图。本申请实施例对于图1a中第一信号分离单元20和第二信号分离单元21的数量不作具体限定，对于图1b中第一信号分离单元20的数量不作具体限定，对于图1c中第二信号分离单元21的数量不作具体限定。且图1示出的信号处理装置，当N的取值为1时，信号处理装置可以实现对一种频率的基带信号进行放大并输出。或者，当N的取值 大于1时，N种所述基带信号的频率为1种时，信号处理装置可以实现对多个一种频率的基带信号进行放大并输出。对于图1a、图1b和图1c示出的信号处理装置，当N的取值大于或等于2时，且N种所述基带信号的频率大于1种时，信号处理装置可以实现对至少两种频率的基带信号进行放大并输出。
具体的，基带信号输入模块1包括N个信号输入端1a和N个信号输出端1b，以信号处理装置对于N种基带信号的接入。
信号分离模块2对N种基带信号的参数进行改变得到2N种分解信号的原理如下：
其中，第一信号分离单元20用于对第Ni种基带信号的参数按照综合基带信号模值确定的改变量进行改变得到两种振幅相同且相位相反的分解信号的原理如下：
综合基带信号模值与基带信号的参数改变量之间存在预先设定的映射关系，数量不同的基带信号的模值以及某一种基带信号的模值不同时可以确定不同的综合基带信号模值，不同的综合基带信号模值可以确定出基带信号的参数的不同改变量。第一信号分离单元20针对同一种基带信号可以得到两种振幅相同且相位相反的分解信号。例如，第一信号分离单元20以第Ni种基带信号的模值作为综合基带信号模值确定对第Ni种基带信号的参数的改变量，进而由第Ni种基带信号得到两种分解信号，这两种分解信号是振幅相同且相位相反的信号。或者，第一信号分离单元20可以根据第Ni种基带信号的模值以及其它基带信号中的至少一种的模值之和来确定对第Ni种基带信号的参数的改变量，进而由第Ni种基带信号得到两种分解信号。第一信号分离单元20用于对第Ni种基带信号的参数按照综合基带信号模值确定的改变量进行改变得到两种振幅相同且相位相反的分解信号,并通过第一信号分离单元20的信号输出端20b输出。
第二信号分离单元21用于对第Nj种基带信号的参数按照固有改变量进行改变得到两种分解信号的原理如下：
第二信号分离单元21按照基带信号的参数的固有改变量对第Nj种基带信号的参数进行改变得到两种分解信号，这两种分解信号的参数可以相同，也可以不同。第二信号分离单元21用于对第Nj种基带信号的参数按照固有改变量进行改变得到两种分解信号，并通过第二信号分离单元21的信号输出端21b输出。需要说明的是，Ni和Nj的取值可以相同，可以不同。
针对图1a示出的方案，信号分离模块2同时包括第一信号分离单元20和第二信号分离单元21，以实现信号分离模块2将两种基带信号分离得到4种分解信号。当第一信号分离单元20的数量大于1，和/或，第二信号分离单元21的数量大于1时，信号分离模块2将N种基带信号分离得到2N种分解信号,其中N大于或等于2。由于第一信号分离单元20可以实现对第Ni种基带信号的参数按照综合基带信号模值确定的改变量进行改变得到两种振幅相同且相位相反的分解信号，其内部结构比较复杂，通常需要乘法器、存储有查询表格的存储器并且还需要取模电路的配合来得到综合基带信号模值。因此，上述信号分离模块2相对仅仅包括第一信号分离单元20的信号分离模块2，降低了信号分离模块2和整个信号处理装置构架的复杂度，从而降低了分立器件的离散型对分解信号的参数产生的差异，以保证进入双频段功率放大器4的合成模拟信号的参数相匹配，进而优化了双频段功率放大器4输出的放大信号的线性指标，提高了信号处理装置的功放效率。上述信号分离模块2相对仅仅包括第二信号分离单元21的信号分离模块2，既可以通过第二信号分离单元21按照基带信号的参数的固有改变量对第Nj种基带信号的参数进行改变得到两种分解信号，又可以对第Ni种基带信号的参数综合基带信号模值确定的改变量进行改变得到两种振幅相同且相位相反的分解信号，提高了信号处理装置对于基带信号的参数的改变量的改变精度，从而降低了不同基带信号得到的分解信号的参数产生的差异，以保证进入双频段功率放大器4的合成模拟信号的参数相匹配，进而优化了双频段功率放大器4输出的放大信号的线性指标，提高了信号处理装置的功放效率。
针对图1b和图1c示出的方案，信号分离模块2仅仅包括第一信号分离单元20，或者，仅仅包括第二信号分离单元21，信号分离模块5通过通道性能补偿单元50补偿分立器件对分解信号的参数产生的差异，降低了分立器件的离散型对分解信号的参数产生的差异，以保证进入双频段功率放大器4的合成模拟信号的参数相匹配，进而优化了双频段功率放大器4输出的放大信号的 线性指标，提高了信号处理装置的功放效率。图1b中第一信号分离单元20的数量大于1，图1c中第二信号分离单元21的数量大于1时，以实现信号分离模块2将N种基带信号分离得到2N种分解信号,其中N大于或等于2。
本申请实施例提供的技术方案，信号处理装置可以实现对至少一种频率的基带信号进行放大并将高功率的放大信号输出。其中，信号处理装置中的信号分离模块2同时包括第一信号分离单元20和第二信号分离单元21的技术方案，在降低信号分离模块2和整个信号处理装置构架的复杂度的基础上，既可以通过第二信号分离单元21按照基带信号的参数的固有改变量对同一种基带信号的参数进行改变得到两种分解信号，又可以对同一种基带信号的参数按照综合基带信号模值确定的改变量进行改变得到两种振幅相同且相位相反的分解信号，提高了信号处理装置对于基带信号的参数的改变量的改变精度，从而降低了不同基带信号得到的分解信号的参数产生的差异，以保证进入双频段功率放大器4的合成模拟信号的参数相匹配，进而优化了双频段功率放大器4输出的放大信号的线性指标，提高了信号处理装置的功放效率。信号处理装置中的信号分离模块2仅包括第一信号分离单元20或者第二信号分离单元21的技术方案，通过通道性能补偿单元50补偿分立器件对分解信号的参数产生的差异，降低了分立器件的离散型对分解信号的参数产生的差异，以保证进入双频段功率放大器4的合成模拟信号的参数相匹配，进而优化了双频段功率放大器4输出的放大信号的线性指标，提高了信号处理装置的功放效率。
为了进一步提高同时包括第一信号分离单元20和第二信号分离单元21的信号处理装置的功放效率，本申请实施例还提供了如下技术方案：
图2是本申请实施例提供的另一种信号处理装置的结构示意图。在上述技术方案的基础上，参见图2，K1大于或等于1，且K2大于或等于1时，信号处理装置还包括通道性能补偿模块5。
具体的，信号处理装置中的信号分离模块2同时包括第一信号分离单元20和第二信号分离单元21的技术方案，在降低信号分离模块2和整个信号处理装置构架的复杂度的基础上，既可以通过第二信号分离单元21按照基带信号的参数的固有改变量对同一种基带信号的参数进行改变得到两种分解信号，又可以对同一种基带信号的参数按照综合基带信号模值确定的改变量进行改变得到两种振幅相同且相位相反的分解信号，提高了信号处理装置对于基带信号的参数的改变量的改变精度，并且通过通道性能补偿单元50补偿分立器件对分解信号的参数产生的差异，降低了分立器件的离散型对分解信号的参数产生的差异，以进一步保证进入双频段功率放大器4的合成模拟信号的参数相匹配，进而进一步优化了双频段功率放大器4输出的放大信号的线性指标，进一步提高了信号处理装置的功放效率。
下面具体细化第一信号分离单元20的具体结构。以图2示出的信号处理装置为例对第一信号分离单元20的结构进行细化，得到图3示出的本申请实施例提供的又一种信号处理装置的结构示意图。
在上述技术方案的基础上，参见图3，第一信号分离单元20包括存储有第一查询表格的第一存储器201、第一乘法器202、存储有第二查询表格的第二存储器203和第二乘法器204，其中，第一查询表格(Lookup Table,LUT)包括M组参数的变化量，第二查询表格包括M组参数的变化量，M为大于或等于1的整数；第一乘法器202的第一信号输入端202a与第一存储器201的信号输出端201a连接，第一乘法器202的第二信号输入端202b与基带信号输入模块1的信号输出端1b连接，第一乘法器202的信号输出端202c作为第一信号分离单元20的信号输出端20b；第二乘法器204的第一信号输入端204a与第二存储器203的信号输出端203a连接，第二乘法器204的第二信号输入端204b与基带信号出入模块1的信号输出端1b连接，第二乘法器204的信号输出端204c作为第一信号分离单元20的信号输出端20b；信号处理装置还包括取模电路6；取模电路6的信号输入端6a与基带信号输入模块1的至少一个信号输出端1b连接，取模电路6用于对至少一种基带信号进行取模处理，得到综合基带信号模值，其中，综合基带信号模值为至少一种基带信号的模值之和；取模电路6的信号输出端6b分别与第一存储器201的信号输入端201b和第二存储器203的信号输入端203b连接，第一存储器201用于根据综合基带信号模值确定与第一乘法器202对应的参数的变化量，第二存储器203用于根据基带信号模值确定与第二乘法器204对应的参数的 变化量；第一乘法器202用于对第Ni种基带信号的参数按照与第一乘法器202对应的参数的变化量进行改变得到第一分解信号，第二乘法器204用于对第Ni种基带信号的参数按照与第二乘法器204对应的参数的变化量进行改变得到第二分解信号。
示例性的，图3中取模电路6的信号输入端6a与基带信号输入模块1的一个信号输出端1b连接，取模电路6用于对一种基带信号进行取模处理，得到综合基带信号模值，其中，综合基带信号模值为一种基带信号的模值。但是本申请实施例中，并不限定取模电路6的信号输入端6a与信号输入模块1连接的信号输出端1b的数量。
具体的，取模电路6将综合基带信号模值发送给第一存储器201和第二存储器203，第一存储器201根据综合基带信号模值找到第一乘法器202对应的参数的变化量，第一乘法器202用于对第Ni种基带信号的参数按照与第一乘法器202对应的参数的变化量进行改变得到第一分解信号。第二存储器203根据综合基带信号模值找到与第二乘法器204对应的参数的变化量，第二乘法器204用于对第Ni种基带信号的参数按照与第二乘法器204对应的参数的变化量进行改变得到第二分解信号。其中，与第一乘法器202对应的参数的变化量和与第二乘法器204对应的参数的变化量的差异，以实现第一分解信号和第二分解信号时两种振幅相同且相位相反的信号。
在一个实施例中，第一存储器201内包括控制单元，控制单元根据综合基带信号模值，发出选择信号，找到第一乘法器202对应的参数的变化量。第二存储器203内包括控制单元，控制单元根据综合基带信号模值，发出选择信号，找到第二乘法器204对应的参数的变化量。
可知的，双频功率放大器在饱和区时，可以对输入信号进行线性放大，放大倍数精准可控。如果双频功率放大器的线性度不高，会导致双频段功率放大器4输出的放大信号与输入信号的非线性失真。在本实施例中，对至少一种频率的基带信号进行放大并输出的信号处理装置，在保证信号处理装置对双频段功率放大器4输出的放大信号具有一定效率的基础上，为了进一步提高信号处理装置的线性度，本申请实施例还提供的如下技术方案：
图4是本申请实施例提供的又一种信号处理装置的结构示意图。图5是本申请实施例提供的又一种信号处理装置的结构示意图。在上述技术方案的基础上，参见图4和图5，基带信号输入模块1包括N个数字预失真单元10；取模电路6包括P个取模单元60，当P等于1时；信号处理装置还包括一个多路信号选择单元70，多路信号选择单元70的第一信号输入端70a与数字预失真单元10的信号输入端10a连接，多路信号选择单元70的第二信号输入端70b与数字预失真单元10的信号输出端10b连接，多路信号选择单元70的信号输出端70c与取模单元60的信号输入端60a连接，取模单元60用于根据基带信号得到综合基带信号的模值，取模单元60的信号输出端60b分别和第一存储器201的信号输入端201b和第二存储器203的信号输入端203b连接。
或者，当P大于1，且小于或等于N时；信号处理装置还包括P个多路信号选择单元70和第一信号合成单元71；多路信号选择单元70的第一信号输入端70a与数字预失真单元10的信号输入端10a连接，多路信号选择单元70的第二信号输入端70b与数字预失真单元10的信号输出端10b连接，多路信号选择单元70的信号输出端70c与取模单元60的信号输入端连接，取模单元60用于根据基带信号得到基带信号的模值；第一信号合成单元71的信号输入端71a与取模单元60的信号输出端60b连接，第一信号合成单元71用于将至少一种基带信号的模值进行求和处理，得到综合基带信号模值，第一信号合成单元71的信号输出端71b分别和第一存储器201的信号输入端201b和第二存储器203的信号输入端203b连接。
具体的，本实施例提供的信号处理装置，基带信号输入模块1采用N个数字预失真(Digital Predistortion,DPD)单元10对N种基带信号分别进行预失真处理，在保证信号处理装置对双频段功率放大器4输出的放大信号具有一定效率的基础上，为了进一步了提高信号处理装置的线性度。示例性的，第一信号合成单元71为加法器，但是本申请实施例对于第一合成单元71的具体器件选择并不限定与此。
需要说明的是，图4中的多路信号选择单元70可以选择进入数字预失真单元10之前的基带信号发送给取模单元60，也可以选择数字预失真单元10处理之后的基带信号发送给取模单元60。示例性的，图4中仅仅示出多路信号选择单元70与一个数字预失真单元10的信号输入端10a或者信 号输出端10b连接，也可以与两个或者多个数字预失真单元10的信号输入端10a或者信号输出端10b连接，本申请实施例对此不作限定。即多路信号选择单元70可以选择进入任何一个数字预失真单元10之前的基带信号发送给取模单元60，也可以选择任何一个数字预失真单元10处理之后的基带信号发送给取模单元60。
具体的，P的取值为1时，取模单元60根据一种基带信号进行取模处理，得到综合基带信号模值，第一存储器201根据综合基带信号模值找到第一乘法器202对应的参数的变化量，第一乘法器202用于对第Ni种基带信号的参数按照与第一乘法器202对应的参数的变化量进行改变得到第一分解信号。第二存储器203根据综合基带信号模值找到与第二乘法器204对应的参数的变化量，第二乘法器204用于对第Ni种基带信号的参数按照与第二乘法器204对应的参数的变化量进行改变得到第二分解信号。
图5示出的信号处理装置中，多路信号选择单元70和取模单元60的数量不再局限是一个，每个取模单元60根据一种基带信号进行取模处理，多个取模单元60可以得到多种基带信号的模值，第一信号合成单元71可以将多种基带信号的模值进行求和处理得到综合基带信号模值。第一存储器201根据综合基带信号模值找到第一乘法器202对应的参数的变化量，第一乘法器202用于对第Ni种基带信号的参数按照与第一乘法器202对应的参数的变化量进行改变得到第一分解信号。第二存储器203根据综合基带信号模值找到与第二乘法器204对应的参数的变化量，第二乘法器204用于对第Ni种基带信号的参数按照与第二乘法器204对应的参数的变化量进行改变得到第二分解信号。
为了根据双频段功率放大器4输出的放大信号的功率来调整信号分离模块2对N种基带信号的参数进行改变得到2N种分解信号的过程，本申请实施例还提供了如下技术方案：
图6是本申请实施例提供的又一种信号处理装置的结构示意图。图7是本申请实施例提供的又一种信号处理装置的结构示意图。在上述技术方案的基础上，参见图6和图7，信号处理装置还包括耦合器72、功率检测单元73和自适应参数提取单元74；耦合器72的信号输入端72a与双频段功率放大器4的信号输出端连接，耦合器72的第一信号输出端72b与天线连接；功率检测单元73的信号输入端73a与耦合器72的第二信号输出端72c连接，用于检测双频段功率放大器4输出的放大信号的功率；自适应参数提取单元74的信号输入端74a与功率检测单元73的信号输出端73b连接，自适应参数提取单元包括2*K1个信号输出端74b，第一存储器201的控制端201c与自适应参数提取单元74的信号输出端74b连接，第二存储器203的控制端203c与自适应参数提取单元74的信号输出端74b连接，自适应参数提取单元74用于根据双频段功率放大器4输出的放大信号的功率与预设功率的数值关系，调整第一存储器201的信号输出端201a输出的参数的变化量，以及第二存储器203的信号输出端203a输出的参数的变化量。
具体的，功率检测单元73用于检测双频段功率放大器4输出的放大信号的功率，自适应参数提取单元74用于根据双频段功率放大器4输出的放大信号的功率与预设功率的数值关系，发出调整信号，第一存储器201基于调整信号调整第一存储器201的信号输出端201a输出的参数的变化量；第二存储器203基于调整信号调整第二存储器203的信号输出端203a输出的参数的变化量，进而实现对第一信号分离单元20得到两种分解信号的参数的改变量的调整。上述技术方案实现了在保证双频段功率放大器4输出的放大信号的功率和预设功率相等的基础上，对至少一种频率的基带信号进行放大，提高了信号处理装置的功放效率。
下面具体细化第二信号分离单元21的结构。在上述技术方案的基础上，参见图4-图7，第二信号分离单元21包括第一振幅和相位调整器210以及第二振幅和相位调整器211，第一振幅和相位调整器210的信号输入端210a与基带信号输入模块1的信号输出端(即图中的数字预失真单元10的信号输出端10b)连接，第一振幅和相位调整器210用于对第Nj种基带信号的参数按照第一固有分改变量进行改变得到第三分解信号；第二振幅和相位调整器211的信号输入端211a与基带信号输入模块1的信号输出端连接，第二振幅和相位调整器211用于对第Nj种基带信号的参数按照第二固有分改变量进行改变得到第四分解信号。
具体的，第一振幅和相位调整器210按照基带信号的参数的固有改变量对第Nj种基带信号的 参数进行改变得到第三分解信号，第二振幅和相位调整器211用于对第Nj种基带信号的参数按照第二固有分改变量进行改变得到第四分解信号，这两种分解信号的参数可以相同，也可以不同。第一振幅和相位调整器210将第三分解信号通过第一振幅和相位调整器210的信号输出端210b输出，第二振幅和相位调整器211将第四分解信号通过第二振幅和相位调整器211的信号输出端211b输出。
为了实现信号同步输入到双频段功率放大器4，本申请实施例还提供了如下技术方案：
在上述技术方案的基础上，结合图1-图3，并参见图4-图7，该信号处理装置还包括时延控制模块，时延控制模块包括2N个时延控制单元80；时延控制单元80的信号输入端80a与信号分离模块2的信号输出端连接，或者，时延控制单元80的信号输入端与通道性能补偿单元50的信号输出端连接；时延控制单元80的信号输出端80b与信号调制模块3的信号输入端连接，时延控制单元80用于将分解信号同步输入至双频段功率放大器4的信号输入端。
具体的，至少一种频率的基带信号经过信号处理装置的处理到达双频段功率放大器4的信号输入端之前，可能会存在信号的不同步，本实施例提供的技术方案，时延控制单元80的设置可以保证合成模拟信号同步进入双频段功率放大器4，进而提高了信号处理装置的功放效率。
在一个实施例中，时延控制单元80可以通过常用时延控制电路，通过控制对于信号的采样点的时间间隔来实现不同信号的同步性。
需要说明的是，时延控制单元80的信号输入端80a直接与信号分离模块2的信号输出端连接的技术方案是针对图1a示出的方案的进一步改进。时延控制单元80的信号输入端80a直接与通道性能补偿单元50的信号输出端50b连接，针对图1b、图1c和图2示出的方案的进一步改进。
下面对于时延控制单元80的结构进行进一步细化。
图8为时延控制单元的结构示意图。在上述技术方案的基础上，结合图1-图7，并参见图8，时延控制单元80包括粗时延控制子单元801和精时延控制子单元802，粗时延控制子单元801的信号输入端801a与信号分离模块2的信号输出端连接，或者，粗时延控制子单元801的信号输入端801a与通道性能补偿单元50的信号输出端50b连接；精时延控制子单元802的信号输入端802a与粗时延控制子单元801的信号输出端801b连接，精时延控制子单元802的信号输出端802b与信号调制模块3的信号输入端连接，其中，粗时延控制子单元801对分解信号同步输入至双频段功率放大器的信号输入端的控制精确程度小于精时延控制子单元802对分解信号同步输入至双频段功率放大器4的信号输入端的控制精确程度。
需要说明的是，粗时延控制子单元801的信号输入端801a直接与信号分离模块2的信号输出端连接的技术方案是针对图1a示出的方案的进一步改进。粗时延控制子单元801的信号输入端801a直接与通道性能补偿单元50的信号输出端50b连接，针对图1b、图1c和图2示出的方案的进一步改进。
具体的，时延控制单元80可以通过常用时延控制电路，通过控制对于信号的采样点的时间间隔来实现不同信号的同步性。粗时延控制子单元801对于信号的采样点的时间间隔大于精时延控制子单元802对于信号的采样点的时间间隔，以实现粗时延控制子单元801对分解信号同步输入至双频段功率放大器的信号输入端的控制精确程度小于精时延控制子单元802对分解信号同步输入至双频段功率放大器4的信号输入端的控制精确程度。本实施例提供的技术方案，通过粗时延控制子单元801和精时延控制子单元802共同完成对分解信号的同步性进行控制，提高了控制精度，以及信号处理装置的功放效率。
下面进一步细化信号调制模块3的具体构成。
图9是本申请实施例提供的又一种信号处理装置的结构示意图。图10是本申请实施例提供的又一种信号处理装置的结构示意图。在上述技术方案的基础上，结合体1-图7，并参见图9和图10，N等于1时，信号调制模块3包括第一数字模拟转换(Digital-Analog Convertor，DAC)单元30和第二数字模拟转换单元31；第一数字模拟转换单元30的信号输入端30a作为信号调制模块3的信号输入端，第一数字模拟转换单元30的信号输出端30b作为信号调制模块3的信号输出端，第一数字模拟转换单元30用于将两种分解信号中的一种转换为模拟信号；第二数字模拟转换 单元31的信号输入端31a作为信号调制模块3的信号输入端，第二数字模拟转换单元31的信号输出端31b作为信号调制模块3的信号输出端，第二数字模拟转换单元31用于将两种分解信号中的另一种转换为模拟信号。
结合体1-图3，并参见图4-图7，N大于或等于2时，信号调制模块包括第一数字模拟转换单元30、第二数字模拟转换单元31、第二信号合成单元32和第三信号合成单元33；第二信号合成单元32的信号输入端32a作为信号调制模块3的信号输入端，第一数字模拟转换单元30的信号输入端30a与第二信号合成单元32的信号输出端32b连接，第二信号合成单元32的信号输出端32b作为信号调制模块3的信号输出端；第二信号合成单元32用于将2N种分解信号中的N种分解信号合成为第一合成信号；第三信号合成单元33的信号输入端33a作为信号调制模块3的信号输入端，第二数字模拟转换单元31的信号输入端31a与第三信号合成单元33的信号输出端33b连接，第三信号合成单元33的信号输出端33b作为信号调制模块3的信号输出端；第三信号合成单元33用于将2N种分解信号中的另外N种分解信号合成为第二合成信号；第一数字模拟转换单元30用于将第一合成信号转换为第一合成模拟信号；第二数字模拟转换单元31用于将第二合成信号转换为第二合成模拟信号。
示例性的，第二信号合成单元32和第三信号合成单元33为加法器，但是本申请实施例对于第二信号合成单元32和第三信号合成单元33的具体器件选择并不限定与此。
具体的，图9和图10示出的信号处理装置，基带信号为一种，第一数字模拟转换单元30用于将两种分解信号中的一种转换为模拟信号；第二数字模拟转换单元31用于将两种分解信号中的另一种转换为模拟信号。图4-图7示出的信号处理装置，第二信号合成单元32用于将2N种分解信号中的N种分解信号合成为第一合成信号，第三信号合成单元33用于将2N种分解信号中的另外N种分解信号合成为第二合成信号，第一数字模拟转换单元30用于将第一合成信号转换为第一合成模拟信号；第二数字模拟转换单元31用于将第二合成信号转换为第二合成模拟信号。上述技术方案实现了信号调制模块3用于将2N种分解信号转换为合成模拟信号，进而实现信号处理装置可以对至少一种频率的基带信号进行放大并将高功率的放大信号输出。需要说明的是，双频段功率放大器4是模拟器件，只能对模拟信号进行放大处理，因此，第一数字模拟转换单元30用于将第一合成信号转换为第一合成模拟信号，第二数字模拟转换单元31用于将第二合成信号转换为第二合成模拟信号，便于双频段功率放大器4的输入端输入第一合成模拟信号和第二合成模拟信号，之后对其进行放大，并输出。
为了将双频段功率放大器4输出的放大信号的频率和通过天线发射的频率相同，本申请实施例还提供了如下技术方案；
在上述技术方案的基础上，结合图1-图3，并参见图4-图7以及图9和图10，该信号处理装置还包括频率调节模块，频率调节模块包括2N个频率调节单元90，频率调节单元90的信号输入端90a与信号分离模块2的信号输出端连接，或者，频率调节单元90的信号输入端90a与通道性能补偿单元50的信号输出端50b连接；频率调节单元90的信号输出端90b与信号调制模块3的信号输入端连接，频率调节单元90用于将分解信号的频率调节至预设中频频率。
需要说明的是，频率调节模块包括2N个频率调节单元90，频率调节单元90的信号输入端90a直接与信号分离模块2的信号输出端连接的技术方案是针对图1a示出的方案的进一步改进。频率调节单元90的信号输入端90a直接与通道性能补偿单元50的信号输出端50b连接的技术方案是针对图1b、图1c和图2示出的方案的进一步改进。
具体的，频率调节单元90可以将分解信号的频率调高或者调低，将分解信号的频率和预设中频频率相同。
本申请实施例还提供了一种信号处理方法，该方法通过上述技术方案中的信号处理装置俩实现，本实施例提供的信号处理方法的实现原理和技术效果与上述实施例类似，此处不再赘述。
本领域普通技术人员可以理解，上文中所公开方法中的全部或某些步骤、系统、设备中的功能模块/单元可以被实施为软件、固件、硬件及其适当的组合。
在硬件实施方式中，在以上描述中提及的功能模块/单元之间的划分不一定对应于物理组件的 划分；例如，一个物理组件可以具有多个功能，或者一个功能或步骤可以由若干物理组件合作执行。某些物理组件或所有物理组件可以被实施为由处理器，如中央处理器、数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。这样的软件可以分布在计算机可读介质上，计算机可读介质可以包括计算机存储介质(或非暂时性介质)和通信介质(或暂时性介质)。如本领域普通技术人员公知的，术语计算机存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、程序模块或其他数据)的任何方法或技术中实施的易失性和非易失性、可移除和不可移除介质。计算机存储介质包括但不限于RAM、ROM、EEPROM、闪存或其他存储器技术、CD-ROM、数字多功能盘(DVD)或其他光盘存储、磁盒、磁带、磁盘存储或其他磁存储装置、或者可以用于存储期望的信息并且可以被计算机访问的任何其他的介质。此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、程序模块或者诸如载波或其他传输机制之类的调制数据信号中的其他数据，并且可包括任何信息递送介质。
以上参照附图说明了本申请的某些实施例，并非因此局限本申请的权利范围。本领域技术人员不脱离本申请的范围和实质内所作的任何修改、等同替换和改进，均应在本申请的权利范围之内。

Claims (11)

  1. 一种信号处理装置，其中包括基带信号输入模块、信号分离模块、信号调制模块和双频段功率放大器，其中：
    所述基带信号输入模块包括N个信号输入端和N个信号输出端，所述基带信号输入模块的N个所述信号输入端配置为输入N种基带信号，其中，N种所述基带信号的频率种类大于或等于1且小于或等于N，所述N为大于或等于1的整数；
    所述信号分离模块包括K1个第一信号分离单元和K2个第二信号分离单元，其中，所述K1为整数，所述K2为整数，且所述K1和所述K2的取值之和等于所述N的取值；
    所述K1大于或等于1，且所述K2大于或等于1时，所述第一信号分离单元的信号输入端与所述基带信号输入模块的信号输出端连接，所述第一信号分离单元配置为对第Ni种所述基带信号的参数按照综合基带信号模值确定的改变量进行改变得到两种振幅相同且相位相反的分解信号，其中所述综合基带信号模值为至少一种所述基带信号的模值之和；所述第二信号分离单元的信号输入端与所述基带信号输入模块的信号输出端连接，所述第二信号分离单元配置为对第Nj种所述基带信号的参数按照固有改变量进行改变得到两种分解信号；其中，所述Ni为大于或等于1且小于或等于N的整数，所述Nj为大于或等于1且小于或等于N的整数，所述参数包括振幅和/或相位；
    所述信号调制模块的信号输入端与所述信号分离模块的信号输出端连接，所述信号调制模块配置为将2N种所述分解信号转换为合成模拟信号；
    所述双频段功率放大器的信号输入端与所述信号调制模块的信号输出端连接，所述双频段功率放大器配置为放大两路所述合成模拟信号并输出；
    或者，所述K1为0或者所述K2为0时，所述信号处理装置还包括通道性能补偿模块，所述通道性能补偿模块包括2N个通道性能补偿单元，所述通道性能补偿单元的信号输入端与所述信号分离模块的信号输出端连接，所述通道性能补偿单元的信号输出端与所述信号调制模块的信号输入端连接，所述通道性能补偿单元配置为补偿分立器件对所述分解信号的参数产生的差异。
  2. 根据权利要求1所述的信号处理装置，其中，所述K1大于或等于1，且所述K2大于或等于1时，所述信号处理装置还包括所述通道性能补偿模块。
  3. 根据权利要求1所述的信号处理装置，其中，所述第一信号分离单元包括存储有第一查询表格的第一存储器、第一乘法器、存储有第二查询表格的第二存储器和第二乘法器，其中，所述第一查询表格包括M组所述参数的变化量，所述第二查询表格包括M组所述参数的变化量，所述M为大于或等于1的整数；
    所述第一乘法器的第一信号输入端与所述第一存储器的信号输出端连接，所述第一乘法器的第二信号输入端与所述基带信号输入模块的信号输出端连接，所述第一乘法器的信号输出端作为所述第一信号分离单元的信号输出端；所述第二乘法器的第一信号输入端与所述第二存储器的信号输出端连接，所述第二乘法器的第二信号输入端与所述基带信号输入模块的信号输出端连接，所述第二乘法器的信号输出端作为所述第一信号分离单元的信号输出端；
    所述信号处理装置还包括取模电路；所述取模电路的信号输入端与所述基带信号输入模块的至少一个信号输出端连接，所述取模电路配置为对至少一种所述基带信号进行取模处理，得到综合基带信号模值，其中，所述综合基带信号模值为至少一种所述基带信号的模值之和；
    所述取模电路的信号输出端分别与所述第一存储器的信号输入端和所述第二存储器的信号输入端连接，所述第一存储器配置为根据所述综合基带信号模值确定与所述第一乘法器对应的所述参数的变化量，所述第二存储器配置为根据所述基带信号模值确定与所述第二乘法器对应的所述参数的变化量；以及
    所述第一乘法器配置为对第Ni种所述基带信号的参数按照与所述第一乘法器对应的所述参数的变化量进行改变得到第一分解信号，所述第二乘法器配置为对第Ni种所述基带信号的参数按照与所述第二乘法器对应的所述参数的变化量进行改变得到第二分解信号。
  4. 根据权利要求3所述的信号处理装置，其中，所述基带信号输入模块包括N个数字预失真单元；
    所述取模电路包括P个取模单元，其中，
    当所述P等于1时；
    所述信号处理装置还包括一个多路信号选择单元，所述多路信号选择单元的第一信号输入端与所述数字预失真单元的信号输入端连接，所述多路选择单元的第二信号输入端与所述数字预失真单元的信号输出端连接，所述多路信号选择单元的信号输出端与所述取模单元的信号输入端连接，所述取模单元配置为根据所述基带信号得到所述综合基带信号的模值，所述取模单元的信号输出端分别和第一存储器的信号输入端和所述第二存储器的信号输入端连接；
    或者，当所述P大于1，且小于或等于N时；
    所述信号处理装置还包括P个多路信号选择单元和第一信号合成单元；
    所述多路信号选择单元的第一信号输入端与所述数字预失真单元的信号输入端连接，所述多路选择单元的第二信号输入端与所述数字预失真单元的信号输出端连接，所述多路信号选择单元的信号输出端与所述取模单元的信号输入端连接，所述取模单元配置为根据所述基带信号得到所述基带信号的模值；
    所述第一信号合成单元的信号输入端与所述取模单元的信号输出端连接，所述第一信号合成单元配置为将至少一种所述基带信号的模值进行求和处理，得到所述综合基带信号模值，所述第一信号合成单元的信号输出端分别和第一存储器的信号输入端和所述第二存储器的信号输入端连接。
  5. 根据权利要求3所述的信号处理装置，还包括耦合器、功率检测单元和自适应参数提取单元；
    所述耦合器的信号输入端与双频段功率放大器的信号输出端连接，所述耦合器的第一信号输出端与天线连接；
    所述功率检测单元的信号输入端与所述耦合器的第二信号输出端连接，配置为检测所述双频段功率放大器输出的放大信号的功率；以及
    所述自适应参数提取单元的信号输入端与所述功率检测单元的信号输出端连接，所述自适应参数提取单元包括2*K1个信号输出端，所述第一存储器的控制端与所述自适应参数提取单元的信号输出端连接，所述第二存储器的控制端与所述自适应参数提取单元的信号输出端连接，所述自适应参数提取单元配置为根据所述双频段功率放大器输出的放大信号的功率与预设功率的数值关系，调整所述第一存储器的信号输出端输出的所述参数的变化量，以及所述第二存储器的信号输出端输出的所述参数的变化量。
  6. 根据权利要求1所述的信号处理装置，其中，所述第二信号分离单元包括第一振幅和相位调整器以及第二振幅和相位调整器，所述第一振幅和相位调整器的信号输入端与所述基带信号输入模块的信号输出端连接，所述第一振幅和相位调整器配置为对第Nj种所述基带信号的参数按照第一固有分改变量进行改变得到第三分解信号；所述第二振幅和相位调整器的信号输入端与所述基带信号输入模块的信号输出端连接，所述第二振幅和相位调整器配置为对第Nj种所述基带信号的参数按照第二固有分改变量进行改变得到第四分解信号。
  7. 根据权利要求1所述的信号处理装置，还包括时延控制模块，所述时延控制模块包括2N个时延控制单元；
    所述时延控制单元的信号输入端与所述信号分离模块的信号输出端连接，或者，所述时延控制单元的信号输入端与所述通道性能补偿单元的信号输出端连接；所述时延控制单元的信号输出端与所述信号调制模块的信号输入端连接，所述时延控制单元配置为将所述分解信号同步输入至所述双频段功率放大器的信号输入端。
  8. 根据权利要求7所述的信号处理装置，其中，所述时延控制单元包括粗时延控制子单元和精时延控制子单元，所述粗时延控制子单元的信号输入端与所述信号分离模块的信号输出端连接，或者，所述粗时延控制子单元的信号输入端与所述通道性能补偿单元的信号输出端连接；所述精时延控制子单元的信号输入端与所述粗时延控制子单元的信号输出端连接，所述精时延控制子单元的 信号输出端与所述信号调制模块的信号输入端连接，其中，所述粗时延控制子单元对所述分解信号同步输入至所述双频段功率放大器的信号输入端的控制精确程度小于所述精时延控制子单元对所述分解信号同步输入至所述双频段功率放大器的信号输入端的控制精确程度。
  9. 根据权利要求1所述的信号处理装置，其中，所述N等于1时，所述信号调制模块包括第一数字模拟转换单元和第二数字模拟转换单元；
    所述第一数字模拟转换单元的信号输入端作为所述信号调制模块的信号输入端，所述第一数字模拟转换单元的信号输出端作为所述信号调制模块的信号输出端，所述第一数字模拟转换单元配置为将两种所述分解信号中的一种转换为模拟信号；所述第二数字模拟转换单元的信号输入端作为所述信号调制模块的信号输入端，所述第二数字模拟转换单元的信号输出端作为所述信号调制模块的信号输出端，所述第二数字模拟转换单元配置为将两种所述分解信号中的另一种转换为模拟信号；
    所述N大于或等于2时，所述信号调制模块包括第一数字模拟转换单元、第二数字模拟转换单元、第二信号合成单元和第三信号合成单元；
    所述第二信号合成单元的信号输入端作为所述信号调制模块的信号输入端，所述第一数字模拟转换单元的信号输入端与所述第二信号合成单元的信号输出端连接，所述第二信号合成单元的信号输出端作为所述信号调制模块的信号输出端；所述第二信号合成单元配置为将2N种所述分解信号中的N种分解信号合成为第一合成信号；
    所述第三信号合成单元的信号输入端作为所述信号调制模块的信号输入端，所述第二数字模拟转换单元的信号输入端与所述第三信号合成单元的信号输出端连接，所述第三信号合成单元的信号输出端作为所述信号调制模块的信号输出端；所述第三信号合成单元配置为将2N种所述分解信号中的另外N种分解信号合成为第二合成信号；
    所述第一数字模拟转换单元配置为将所述第一合成信号转换为第一合成模拟信号；以及
    所述第二数字模拟转换单元配置为将所述第二合成信号转换为第二合成模拟信号。
  10. 根据权利要求1所述的信号处理装置，还包括频率调节模块，所述频率调节模块包括2N个频率调节单元，所述频率调节单元的信号输入端与所述信号分离模块的信号输出端连接，或者，所述频率调节单元的信号输入端与所述通道性能补偿单元的信号输出端连接；所述频率调节单元的信号输出端与所述信号调制模块的信号输入端连接，所述频率调节单元配置为将述分解信号的频率调节至预设中频频率。
  11. 一种信号处理方法，通过根据权利要求1-10任一所述的信号处理装置实现。
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