WO2022161449A1 - Procédé de codage, procédé de décodage et dispositif de communication - Google Patents

Procédé de codage, procédé de décodage et dispositif de communication Download PDF

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WO2022161449A1
WO2022161449A1 PCT/CN2022/074480 CN2022074480W WO2022161449A1 WO 2022161449 A1 WO2022161449 A1 WO 2022161449A1 CN 2022074480 W CN2022074480 W CN 2022074480W WO 2022161449 A1 WO2022161449 A1 WO 2022161449A1
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codeword
matrix
code
code block
codeword matrix
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PCT/CN2022/074480
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English (en)
Chinese (zh)
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格里岑弗拉基米尔•维塔利耶维奇
李云龙
弗拉迪斯拉夫奥博连采夫
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华为技术有限公司
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Priority to CN202280007642.7A priority Critical patent/CN116491072A/zh
Publication of WO2022161449A1 publication Critical patent/WO2022161449A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes

Definitions

  • the present application relates to the field of communication technology, and more particularly, to an encoding method, a decoding method, and a communication device.
  • a coding method based on spatially coupled (SC) is currently known.
  • Spatial coupling is a way of designing a semi-infinite sequence of codeword symbols such that any symbol in the sequence of codeword symbols is contained in at least one finite subsequence that make up the codeword.
  • the component code is composed of the current information block and the historically generated information block through characteristic interleaving, and the information sequence can continuously form a new codeword through spatial coupling.
  • the present application provides an encoding method, a decoding method, and a communication device, in order to reduce the delay of encoding and decoding and speed up the convergence speed of decoding.
  • an encoding method is provided.
  • the method may be executed by the encoding end device, or may also be executed by a chip or a chip system or circuit configured in the encoding end device, which is not limited in this application.
  • the method may include: acquiring a bit sequence to be encoded; performing spatial coupling encoding on the bit sequence to be encoded to obtain an encoded codeword; wherein the codeword includes current code block bits and historical code block bits, current code block bits and historical code block bits The coupling relationship between the code block bits is unbalanced coupling.
  • a code block represents a part of a codeword matrix C with w rows and n columns of w ⁇ n, or a part of a symbol matrix C with w rows and n columns of w ⁇ n.
  • the unit of the codeword matrix C may be a codeword symbol. Therefore, the codeword matrix C may also be understood as a symbol sequence, and the symbol sequence constitutes a symbol matrix.
  • the historical code block and the current code block may be regarded as a relative meaning, and those skilled in the art should understand the meaning.
  • the currently encoded code block can be regarded as the current code block; the code block that has been coded before the current code block can be regarded as the historical code block.
  • the currently decoded code block may be regarded as the current code block; the code block that has been decoded before the current code block may be regarded as the historical code block.
  • Unbalanced spatial coupling means that there are two or more intersections between the current component code and the historical component code, or there are two or more intersections between the current code block and the historical code block.
  • the representation form of the coupling relationship can be a sub-matrix, or can also be a symbol (bit).
  • the coupling relationship between the current code block bits and the historical code block bits is designed to be unbalanced coupling, so that the current component code contains one or more symbols of the historical component code.
  • the current component code contains two or more symbols The symbol for the historical component code.
  • the time required for the unbalanced spatially coupled code to collect all the bits of the codeword is shorter than that of the balanced coupled code. Therefore, the same number of real codewords are transmitted, and the unbalanced coupling has a shorter delay. Since the delay for sending the same number of real code words is reduced, the occupied data buffer is also reduced accordingly. In addition, since the data buffer for sending the same number of real codewords becomes smaller, the power consumption caused by the data buffer is correspondingly reduced.
  • the real codeword part that is, the uncoupled part of the current component code.
  • the current component code includes a coupled part and a non-coupled part.
  • the coupled part is generally not sent, and the uncoupled part is sent.
  • the uncoupled part includes information bits and check bits, that is, the information and The check digit of the component code.
  • the parity bit is generally generated by the coupling part of the component code and the information bit.
  • a decoding method is provided.
  • the method may be executed by the decoding end device, or may also be executed by a chip or a chip system or circuit configured in the decoding end device, which is not limited in this application.
  • the method may include: receiving a codeword to be decoded; decoding the codeword; wherein, the codeword includes the current code block bits and the historical code block bits, and the coupling relationship between the current code block bits and the historical code block bits is: Unbalanced coupling.
  • the codeword may be a codeword encoded by unbalanced spatial coupling.
  • the component codes with a coupling relationship can help each other in decoding through iterative decoding, for example, a historical codeword that has been successfully decoded can help the decoding of the current codeword through the coupling relationship;
  • the decoding result of the current code block can also help the decoding of historical code blocks, so that the iterative decoding can be performed for many times. Due to the use of unbalanced spatial coupling, there are two or more intersections between the current component code and the historical component code. The same successfully decoded historical component code that is coupled with the current codeword can help the decoding of the current codeword more than the case where there is only one intersection. Therefore, the convergence speed of decoding can be accelerated during iterative decoding.
  • the codeword is a codeword matrix C with n columns and semi-infinite rows; the codeword matrix C includes an imaginary codeword matrix and a real codeword matrix,
  • the coupling relationship between the current code block bits and the historical code block bits is unbalanced coupling, including: the coupling relationship between the submatrix of the virtual codeword matrix and the submatrix of the real codeword matrix is an unbalanced coupling relationship.
  • the unit of the codeword matrix C may be a codeword symbol.
  • each row of the codeword matrix C may be defined as a component code.
  • the codeword matrix C is divided into two parts, A and B, by columns, A represents an imaginary codeword matrix, B represents a real codeword matrix, and (A, B) can be denoted as a zipper pair.
  • Z ⁇ [n] represents the codeword matrix C with n columns.
  • (A,B) can include the following features:
  • the sub-matrix of the virtual codeword matrix is obtained by coupling the sub-matrix of the historical real codeword matrix.
  • the row of the codeword matrix C is represented as wq+i
  • the column of the codeword matrix C is represented as ws+j
  • the submatrix T q of the codeword matrix C, s satisfies the following formula:
  • T q,s ⁇ c qw+i,ws+j ⁇ C ⁇ ;
  • T q,s represents the w ⁇ w submatrix of the qth row and the sth column of the codeword matrix C; s ⁇ [2L]; i,j ⁇ [w]; L and w are positive integers.
  • the submatrix T q s of the imaginary codeword matrix in the codeword matrix C satisfies the following formula:
  • ⁇ (q,s) represents the unbalanced coupling function
  • the superscript T represents the transposition
  • such coupling functions can be called periodic coupling functions.
  • ⁇ (q, s) corresponding to at least two s are the same.
  • the value of q is fixed, and the ⁇ (q, s) corresponding to at least two s are the same.
  • the coupling function can be independent of the number of rows.
  • the characteristics of the codeword matrix C include:
  • the row of the codeword matrix C is expressed as wq+i, the column is expressed as ws+j, q ⁇ Z, s ⁇ [2L], and i,j ⁇ [w];
  • T q,s represents the w ⁇ w sub-matrix of the q-th row and the s-th column;
  • ⁇ (q, s) is a positive integer; the relationship between ⁇ and s is not bijective for at least one q ⁇ Z.
  • the codeword includes a plurality of component codes, each component code consisting of one or more columns of a historical code block coupled with a row of the current code block.
  • one or more columns of the historical code block and the row of the current code block can be coupled to form a component code.
  • the codeword includes multiple code blocks
  • the multiple component codes include a first component code
  • at least two symbols in the first component code are from different symbols in the same code block.
  • Codeword submatrix
  • the symbols in the first component code include one or more first symbols, and a plurality of second symbols, the first symbols belong to the code block B i , the second symbols A symbol belongs to one or more code blocks B j , where i and j are positive integers and j is less than i.
  • the symbols in the first component code form a plurality of blocks, and the symbols in the first component code include:
  • f 1 , f 2 , f 3 are functions of outputting positive integers with (i, j, k) as variables; (i, j, k) represents the k-th w ⁇ w block in the code block B i
  • the jth column of ; (i,j) represents the rth row of the code block B i ; f 1 (i,j,1) ⁇ f 1 (i,j,2) ⁇ ... ⁇ f 1 (i,j,s )>0, 1 ⁇ f 2 (i,j,k) ⁇ w, 1 ⁇ f 3 (i,j,k) ⁇ s, k,w,s are all positive integers.
  • j is less than or equal to w, and k is less than or equal to s;
  • j is less than or equal to w, and k is less than or equal to s;
  • the codeword includes the following features:
  • the codeword includes a plurality of component codes
  • the component codes are any of the following: Reed-Solomon code RS code, BCH code, low density parity check code LDPC code.
  • the component code may be a non-binary BCH code.
  • an encoding method is provided.
  • the method may be executed by the encoding end device, or may also be executed by a chip or a chip system or circuit configured in the encoding end device, which is not limited in this application.
  • the method may include: acquiring a bit sequence to be encoded; performing spatial coupling encoding on the bit sequence to be encoded to obtain an encoded codeword; wherein the codeword is a codeword matrix C with n columns and semi-infinite rows;
  • the codeword matrix C is divided into two parts, A and B, by columns, where A is an imaginary codeword matrix, B is a real codeword matrix, and the coupling relationship between the codeword sub-matrices of A and B is unbalanced;
  • the codeword matrix C Features include:
  • the row of the codeword matrix C is expressed as wq+i, the column is expressed as ws+j, q ⁇ Z, s ⁇ [2L], and i,j ⁇ [w];
  • T q,s represents the w ⁇ w sub-matrix of the q-th row and the s-th column;
  • ⁇ (q, s) is a positive integer; the relationship between ⁇ and s is not bijective for at least one q ⁇ Z.
  • a decoding method is provided.
  • the method may be executed by the decoding end device, or may also be executed by a chip or a chip system or circuit configured in the decoding end device, which is not limited in this application.
  • the method may include: receiving a codeword to be decoded; decoding the codeword; wherein, the codeword is a codeword matrix C with n columns and semi-infinite rows; the codeword matrix C is divided into A by columns , B two parts, where A is an imaginary codeword matrix, B is a real codeword matrix, and the coupling relationship between the codeword sub-matrices of A and B is unbalanced; the characteristics of the codeword matrix C include:
  • the row of the codeword matrix C is expressed as wq+i, the column is expressed as ws+j, q ⁇ Z, s ⁇ [2L], and i,j ⁇ [w];
  • T q,s represents the w ⁇ w sub-matrix of the q-th row and the s-th column;
  • ⁇ (q, s) is a positive integer; the relationship between ⁇ and s is not bijective for at least one q ⁇ Z.
  • each row of the codeword matrix C may be defined as a component code.
  • an encoding method is provided.
  • the method may be executed by the encoding end device, or may also be executed by a chip or a chip system or circuit configured in the encoding end device, which is not limited in this application.
  • the method may include: acquiring a bit sequence to be encoded; performing spatial coupling encoding on the bit sequence to be encoded to obtain an encoded codeword; wherein the codeword structure is described as follows:
  • each row of the codeword matrix C may be defined as a component code.
  • a decoding method is provided.
  • the method may be executed by the decoding end device, or may also be executed by a chip or a chip system or circuit configured in the decoding end device, which is not limited in this application.
  • the method may include: receiving a codeword to be decoded; decoding the codeword; wherein the codeword structure is described as follows: mapping a data stream to a sequence of semi-infinite length code blocks; the sequence of semi-infinite length code blocks can be decomposed into multiple code blocks of w ⁇ m, w and m are positive integers; the symbols in the component code have one or more symbols belonging to the code block B i , and two or more symbols belong to one or more code blocks B j ; wherein, i and j is a positive integer, j is less than i; the component code is composed of data symbols and check symbols; the component code check symbols are composed of one or more symbols belonging to the code block B i and two or more symbols belonging to two or more The code block B j is generated; the code block B i or B j can be expressed as a w ⁇ m matrix; the code length of the component code is 2*m; each code block B i can be expressed as w ⁇ (s ⁇ w) Mat
  • the representation of the component code is: (if 1 (i,j,1), f 2 (i, j, 1), f 3 (i, j ,1)), (if 1 (i, j, 2), f 2 (i, j, 2), f 3 (i, j, 2)), ..., (if 1 (i, j, s), f2 ( i,j,s), f3 (i,j,s)) and row row(i,j).
  • the representation of the component code is: (if 1 (i,j,1), f 2 (i, j, 1), f 3 (i, j ,1)), (if 1 (i, j, 2), f 2 (i, j, 2), f 3 (i, j, 2)), ..., (if 1 (i, j, s), f2 ( i,j,s), f3 (i,j,s)) and row row(i,j).
  • a communication apparatus including each module or unit for performing the method in any of the possible implementation manners of the first aspect, the third aspect or the fifth aspect.
  • a wireless communication apparatus including each module or unit for performing the method in any of the possible implementation manners of the second aspect, the fourth aspect or the sixth aspect.
  • a communication device comprising a processor coupled with a memory, and configured to execute the method in any one of the possible implementations of the first aspect, the third aspect or the fifth aspect.
  • the communication device further includes a memory.
  • the communication device further includes a communication interface, and the processor is coupled to the communication interface.
  • the communication device further includes a communication interface, and the processor is coupled to the communication interface.
  • the communication device is a network device.
  • the communication interface may be a transceiver, or an input/output interface.
  • the communication device is a chip or a system of chips.
  • the communication interface may be an input/output interface, an interface circuit, an output circuit, an input circuit, a pin or a related circuit on the chip or a chip system.
  • the processor may also be embodied as a processing circuit or a logic circuit.
  • a communication device including a processor.
  • the processor is coupled to the memory and can be configured to execute instructions in the memory to implement the method in any of the possible implementation manners of the second aspect, the fourth aspect or the sixth aspect.
  • the communication device further includes a memory.
  • the communication device further includes a communication interface, and the processor is coupled to the communication interface.
  • the transceiver may be a transceiver circuit.
  • the input/output interface may be an input/output circuit.
  • the communication device is a terminal device.
  • the communication interface may be a transceiver, or an input/output interface.
  • the transceiver may be a transceiver circuit.
  • the input/output interface may be an input/output circuit.
  • the communication device is a chip or a system of chips.
  • the communication interface may be an input/output interface, an interface circuit, an output circuit, an input circuit, a pin or a related circuit on the chip or a chip system.
  • the processor may also be embodied as a processing circuit or a logic circuit.
  • a processor comprising: an input circuit, an output circuit and a processing circuit.
  • the processing circuit is configured to receive a signal through the input circuit and transmit a signal through the output circuit, so that any one of the first to sixth aspects, and any one of the first to sixth aspects The methods of one possible implementation are implemented.
  • the above-mentioned processor may be a chip
  • the input circuit may be an input pin
  • the output circuit may be an output pin
  • the processing circuit may be a transistor, a gate circuit, a flip-flop, and various logic circuits.
  • the input signal received by the input circuit may be received and input by, for example, but not limited to, a receiver
  • the signal output by the output circuit may be, for example, but not limited to, output to and transmitted by a transmitter
  • the circuit can be the same circuit that acts as an input circuit and an output circuit at different times.
  • the embodiments of the present application do not limit the specific implementation manners of the processor and various circuits.
  • a twelfth aspect provides a processing apparatus including a processor and a memory.
  • the processor is configured to read the instructions stored in the memory, and can receive signals through the receiver and transmit signals through the transmitter, so as to execute the first aspect to the sixth aspect and any possible implementation manner of the first aspect to the sixth aspect Methods.
  • processors there are one or more processors and one or more memories.
  • the memory may be integrated with the processor, or the memory may be provided separately from the processor.
  • the memory can be a non-transitory memory, such as a read only memory (ROM), which can be integrated with the processor on the same chip, or can be separately set in different On the chip, the embodiment of the present application does not limit the type of the memory and the setting manner of the memory and the processor.
  • ROM read only memory
  • the relevant data interaction process such as sending indication information, may be a process of outputting indication information from the processor, and receiving capability information may be a process of receiving input capability information by the processor.
  • the data output by the processing can be output to the transmitter, and the input data received by the processor can be from the receiver.
  • the transmitter and the receiver may be collectively referred to as a transceiver.
  • the processor in the twelfth aspect above may be a chip, and the processor may be implemented by hardware or software.
  • the processor When implemented by hardware, the processor may be a logic circuit, an integrated circuit, etc.; when implemented by software
  • the processor may be a general-purpose processor, which is implemented by reading software codes stored in a memory, and the memory may be integrated in the processor or located outside the processor and exist independently.
  • a thirteenth aspect provides a computer program product, the computer program product comprising: a computer program (also referred to as code, or instructions), which, when the computer program is executed, causes the computer to execute the above-mentioned first aspect to The sixth aspect and the method in any possible implementation manner of the first aspect to the sixth aspect.
  • a computer program also referred to as code, or instructions
  • a computer-readable medium stores a computer program (also referred to as code, or instruction) when it runs on a computer, causing the computer to execute the above-mentioned first aspect to The sixth aspect and the method in any possible implementation manner of the first aspect to the sixth aspect.
  • a computer program also referred to as code, or instruction
  • FIG. 1 is a schematic diagram of a wireless communication system 100 suitable for an embodiment of the present application.
  • FIG. 2 is a basic flowchart of communication using a wireless technology applicable to an embodiment of the present application.
  • FIG. 3 is a schematic block diagram of an encoding method provided according to an embodiment of the present application.
  • FIG. 4 shows a schematic diagram of an unbalanced spatially coupled codeword structure applicable to an embodiment of the present application.
  • Figure 5 shows a schematic diagram of a balanced spatially coupled codeword structure.
  • FIG. 6 is a schematic block diagram of a decoding method provided according to an embodiment of the present application.
  • FIG. 7 shows a schematic diagram of an unbalanced spatially coupled codeword structure applicable to yet another embodiment of the present application.
  • FIG. 8 shows a comparison between the decoding performance of the unbalanced spatially coupled code provided by the present application and the balanced spatially coupled code of the prior art.
  • FIG. 9 is a schematic diagram of an example of the communication device of the present application.
  • FIG. 10 is a schematic diagram of an example of a communication device of the present application.
  • FIG. 11 is a schematic diagram of an example of an encoder-side optical communication device of the present application.
  • FIG. 12 is a schematic diagram of an example of the optical communication device at the decoding end of the present application.
  • the wireless communication systems may include, but are not limited to: a wireless local access network (WLAN) system, a narrow band-internet of things, NB-IoT) system, 5th generation (5G) system or new radio (NR), long term evolution (LTE) system or communication system after 5G, etc.
  • WLAN wireless local access network
  • NB-IoT narrow band-internet of things
  • 5G 5th generation
  • NR new radio
  • LTE long term evolution
  • the technical solutions of the embodiments of the present application can also be applied to device (device to device, D2D) communication, machine to machine (machine to machine, M2M) communication, machine type communication (machine type communication, MTC), satellite communication and vehicle Communication in networked systems.
  • D2D device to device
  • M2M machine to machine
  • MTC machine type communication
  • satellite communication satellite communication and vehicle Communication in networked systems.
  • the technical solutions of the embodiments of the present application can be applied to application scenarios of 5G mobile communication systems, such as enhanced mobile broadband (eMBB), high reliability and low latency communication (ultra reliable low latency communication, URLLC), enhanced mobile broadband (eMBB), Massive machine type communication (eMTC), etc.
  • eMBB enhanced mobile broadband
  • URLLC ultra reliable low latency communication
  • eMBB enhanced mobile broadband
  • eMTC Massive machine type communication
  • FIG. 1 is a schematic diagram of a wireless communication system 100 suitable for an embodiment of the present application.
  • the wireless communication system 100 may include at least one network device, such as the network device 111 shown in FIG. 1 , and the wireless communication system 100 may also include at least one terminal device, such as the terminal device 121 shown in FIG. 1 . to the terminal device 123.
  • a network device (such as network device 111 as shown in FIG. 1 ) may wirelessly communicate with one or more end devices (such as end device 121 to end device 123 as shown in FIG. 1 ).
  • Wireless technology is used for communication between the network device and the terminal device in FIG. 1 .
  • a network device sends a signal
  • it is a sender
  • a network device receives a signal
  • it is a receiver
  • the terminal equipment sends a signal
  • it is the transmitting end
  • the terminal equipment receives the signal it is the receiving end.
  • Figure 2 is a basic flow chart of communication using wireless technology.
  • the source of the transmitting end is sent out on the channel after source coding, channel coding, rate matching and modulation in sequence.
  • the receiver After receiving the signal, the receiver obtains the sink after demodulation, rate matching, channel decoding and source decoding in sequence.
  • FIG. 2 is only an exemplary illustration for the convenience of understanding, and in actual communication, other processing steps or other deformation processing may also be included, which is not limited thereto.
  • Channel encoding and decoding is one of the core technologies in the field of wireless communication, and the improvement of its performance will directly improve network coverage and user transmission rate.
  • the original information is encoded by the encoder, transmitted through the channel, received by the decoder, and decoded. After decoding at the end, the original information is recovered.
  • the encoding end may also be called a sending end (or a sending device), and the decoding end may also be called a receiving end (or a receiving device) of information or data.
  • the transmitting end and the receiving end may perform wired communication, for example, optical communication, and the encoding scheme of the present application may be applied to the encoding process of wired communication.
  • the transmitting end and the receiving end may perform wireless communication, for example, it may be applied to an encoding process in a wireless communication system.
  • the solution provided in this application can be used for the encoding process of the sending device, and can also be used for the decoding process of the receiving device.
  • the sending device may be a network device, and the receiving device may be a terminal device.
  • the sending device may be a terminal device, and the receiving device may be a network device.
  • the sending device may be a terminal device, and the receiving device may be a terminal device.
  • the sending device may be a network device, and the receiving device may be a network device.
  • the specific forms of network equipment and terminal equipment are not strictly limited.
  • FEC forward error correction
  • Forward error correction is an error control method. It means that the signal is encoded in advance according to a certain algorithm before being sent to the transmission channel, and redundant codes with the characteristics of the signal itself are added. The technology of decoding the signal, so as to find out the error code generated in the transmission process and correct it.
  • a forward error correction code KP4 is defined in IEEE802.3. However, with the deterioration of channel conditions, KP4 has been difficult to meet the performance requirements. Considering factors such as power consumption and delay, KP4 can be considered to cascade a forward error correction code of an optical layer as an effective and compatible forward error correction code scheme.
  • GCC generalized concatenated code
  • the first encoding is outer code encoding relative to the second encoding
  • the second encoding is inner code encoding relative to the first encoding
  • the second encoding is outer code encoding relative to the third encoding
  • the third encoding is inner code encoding relative to the second encoding.
  • the outer code encoding is performed first, and the inner code encoding is performed later. The output of the outer code is used as the input of the inner code.
  • codeword For example, based on the codeword provided by the embodiment of the present application, it can be used as an inner code in a concatenated code, and can be used for interconnection between data centers.
  • the forward error correction code of the optical layer cascaded by KP4 needs to meet certain conditions.
  • the forward error correction code of the optical layer has high performance, low complexity, and certain anti-burst capability.
  • spatially coupled error correction codes ie KP4 cascaded spatially coupled error correction codes, may be used.
  • the spatially coupled error correction codes that meet the above conditions may include, but are not limited to: staircase codes, continuous interleaved BCH codes (CI-BCH codes), braided block codes, open front Error correction code (open forward error correction, oFEC) and so on.
  • each component code of the spatially coupled error correction code is composed of bits of the current code block and partial bits of one or more historical code blocks. When composed of bits from multiple historical code blocks. The number of bits belonging to each historical code block is equal.
  • the present application provides a solution, which can reduce the delay of encoding and decoding as much as possible and speed up the convergence speed of decoding.
  • FIG. 3 is a schematic diagram of an encoding method 300 provided by an embodiment of the present application.
  • Method 300 may include the following steps.
  • the code word includes the current code block bits and the historical code block bits, and the coupling relationship between the current code block bits and the historical code block bits is unbalanced coupling.
  • the representation form of the coupling relationship can be a sub-matrix, or can also be a symbol (bit).
  • a code block represents a part of a codeword matrix C with w rows and n columns of w ⁇ n, or a part of a symbol matrix C with w rows and n columns of w ⁇ n.
  • the unit of the codeword matrix C may be a codeword symbol. Therefore, the codeword matrix C may also be understood as a semi-infinite symbol sequence, and the symbol sequence constitutes a symbol matrix.
  • the historical code block and the current code block may be regarded as a relative meaning, and those skilled in the art should understand the meaning.
  • the currently encoded code block can be regarded as the current code block; the code block that has been coded before the current code block can be regarded as the historical code block.
  • the currently decoded code block may be regarded as the current code block; the code block that has been decoded before the current code block may be regarded as the historical code block. For example, taking the component code C(w(q-1)+i) and the component code C(w(q-4)+j) in FIG.
  • the component code C(w(q-1)+i) It can be regarded as the current component code
  • the component code C(w(q-4)+j) can be regarded as the historical component code.
  • the codeword includes a plurality of component codes.
  • the component codes are formed by interleaving and combining the characteristics based on the current information block and the information blocks generated in the history.
  • the component codes with the coupling relationship can help each other in decoding through iterative decoding.
  • the decoding result of the historical code block it can help the decoding of the current code block, or, the decoding result of the current code block can also help the decoding of the historical code block, so that the decoding can be iteratively decoded for many times, and the decoding accuracy can be improved. Rate.
  • Unbalanced spatial coupling means that there are two or more intersections between the current code block and the historical code block, or there are two or more intersections between the current component code and the historical component code. It should be understood that the unbalanced spatial coupling means that the current code block and the historical code block, or the current component code and the historical component code, may have 2 or more intersections, which are not limited to only 2 or more. intersection. For example, in some cases, there may also be an intersection.
  • Unbalanced space coupling can be understood as relative to balanced space coupling. For example, refer to FIGS. 4 and 5 .
  • the component code C(w(q-1)+i) is coupled with a matrix of historical codewords with four rows. Taking the component code C(w(q-4)+j) of a certain row as an example, in the unbalanced spatial coupling code shown in Figure 4, the component code C(w(q-1)+i) and the component code C( The number of intersections of w(q-4)+j) is 2.
  • the component code C(w(q-1)+i) is coupled to a matrix of historical codewords with seven rows. Taking the component code C(w(q-4)+j) of a certain row as an example, in the balanced spatial coupling code shown in Figure 5, the component code C(w(q-1)+i) and the component code C(w The number of intersections of (q-4)+j) is 1.
  • unbalanced spatial coupling is adopted, and the component codes of the same length are coupled with the historical codeword matrix with fewer rows.
  • the time required for the unbalanced spatially coupled code to receive all the bits of the component code is shorter than that of the balanced coupled code. Therefore, sending the same number of real codewords, the unbalanced coupling has a shorter delay. Since the delay for sending the same number of real code words is reduced, the occupied data buffer is also reduced accordingly. In addition, since the data buffer for sending the same number of real codewords becomes smaller, the power consumption caused by the data buffer is correspondingly reduced.
  • FIG. 6 is a schematic diagram of a decoding method 600 provided by an embodiment of the present application.
  • Method 600 may include the following steps.
  • the codeword includes the current code block bits and the historical code block bits, and the coupling relationship between the current code block bits and the historical code block bits is unbalanced coupling.
  • results of at least two current code blocks can be obtained based on the decoding results of historical code blocks, the decoding convergence speed is fast, and the decoding delay is short.
  • the codeword may be a codeword encoded by unbalanced spatial coupling.
  • component codes with coupling relationships can help each other in decoding through iterative decoding.
  • historical codewords that have been successfully decoded will help the decoding of the current codeword through the coupling relationship;
  • the decoding result of the code block can also help the historical code block decoding, so it can be iteratively decoded for many times. Due to the use of unbalanced spatial coupling, there are two or more intersections between the current component code and the historical component code.
  • the same successfully decoded historical component code that is coupled with the current codeword can help the decoding of the current codeword more than the case where there is only one intersection. Therefore, the convergence speed of decoding can be accelerated during iterative decoding.
  • the codeword provided by the embodiment of the present application is a semi-infinite-length unbalanced spatially coupled code.
  • the codeword generated by the coding method based on spatial coupling is a semi-infinitely long unbalanced spatially coupled code.
  • the codeword matrix is denoted as C
  • the codeword matrix C is a semi-infinite codeword sequence
  • the codeword sequence constitutes a codeword matrix
  • the number of rows of the codeword matrix is infinite
  • the number of columns of the codeword matrix is infinite.
  • n is a positive integer.
  • semi-infinite can be understood as the number of rows of the codeword matrix is not limited.
  • the unit of the codeword matrix may be the codeword symbol. Therefore, the codeword matrix C can also be understood as a semi-infinite symbol sequence, and the symbol sequence constitutes a symbol matrix, the number of rows of the symbol matrix is infinitely long, and the number of columns of the symbol matrix is n.
  • a symbol can be understood as a carrier of information or data. For example, in binary notation, one symbol is one bit; for another example, in hexadecimal notation, one symbol is one character. It should be understood that the relationship between symbols and bits is not limited, for example, a symbol may be one bit or multiple bits.
  • the position of the codeword symbol in the codeword matrix can be represented by (i, j).
  • (i,j) indicates that the codeword symbol is located in the ith row and the jth column of the codeword matrix.
  • Code character symbols are finite field elements.
  • a finite field means a field with a finite number of elements. The number of bits of a finite field element is related to the finite field to which it belongs. For example, a finite field GF(256) of order 256 has finite field elements of 8 bits.
  • the codeword matrix C may include an imaginary codeword matrix A and a real codeword matrix B.
  • (A,B) can be recorded as a zipper pair. in, (A,B) includes the following features:
  • Each row of the codeword matrix C can be defined as a component code.
  • the component code is RS(224, 218), where 218 is the information bit length, and 224 is the encoded codeword length.
  • the RS code is a Reed-Solomon (RS) code.
  • mapping ⁇ -1 :B ⁇ A for any a ⁇ A, b ⁇ B, we have Then ⁇ is bijective, and ⁇ -1 is called the inverse mapping of ⁇ .
  • a mapping ⁇ is causal if ⁇ 1 ( ⁇ (i,j)) ⁇ i.
  • ⁇ 1 is used to represent ⁇ 1 ( ⁇ (i, j)).
  • the coupling depth can also be defined, such as denoted as ⁇ .
  • the coupling depth ⁇ represents the difference between the maximum line numbers of the current component code and the historical component code.
  • the codeword structure provided by the embodiment of the present application is similar to the codeword structure of the tiled zipper code.
  • the rows and columns of the codeword matrix C can be expressed as wq+i and ws+j. where q ⁇ Z, s ⁇ [2L], and i,j ⁇ [w].
  • a w ⁇ w matrix T q,s is defined as a sub-matrix of the codeword matrix C. It should be understood that the sub-matrix is only a name for description, and does not limit the protection scope of the embodiments of the present application.
  • mapping relationship of the submatrix T q,s of the codeword matrix C of different rows can be: for s ⁇ [L], That is, for s ⁇ [L], a submatrix of the virtual codeword matrix can be defined
  • the sub-matrix of the virtual codeword matrix can be obtained by coupling the sub-matrix of the historical real codeword matrix.
  • ⁇ (q, s) may be called an inter-code block coupling function (or may also be called an inter-frame coupling function), and the value of ⁇ (q, s) may be a positive integer.
  • the q value is fixed, and the ⁇ (s) corresponding to at least two s are the same. That is, for a value of q, the corresponding ⁇ (s) of at least two s are the same.
  • ⁇ (q,s) ⁇ (s).
  • the period may be a fixed value ⁇ , for example, the period may be fixed to 1.
  • the coupling relationship between code blocks can be said to be balanced; otherwise, the coupling relationship is unbalanced. In this embodiment of the present application, the coupling relationship is unbalanced.
  • an embodiment of the present application provides an unbalanced spatial coupling function where the period of the coupling function between code blocks is 1, and the coupling function between code blocks is independent of the number of rows.
  • Tables 1 and 2 show two possible coupling functions ⁇ (s). It can be seen from Table 1 and Table 2 that the ⁇ (s) corresponding to at least two s are the same.
  • the unbalanced spatial coupling code provided based on the embodiment of the present application is shown in FIG. 4 .
  • the component code is RS(224,218,7) on the finite field GF(256)
  • the number of columns of the codeword matrix C is n, and the rows and columns of the codeword matrix C can be expressed as wq+i and ws+j, where q ⁇ Z, s ⁇ [2L], and i,j ⁇ [w].
  • the codeword matrix C includes a plurality of component codes, and each row of the codeword matrix C can be defined as a component code, that is, the codeword length of the component code is n.
  • the codeword matrix C is divided into units by w ⁇ w sub-matrix.
  • Each component code corresponds to multiple blocks, and the size of each block is w ⁇ w, that is, each block represents a w ⁇ w matrix.
  • the w ⁇ w matrix is a sub-matrix of the codeword matrix C, and the w ⁇ w matrix T q,s represents the w ⁇ w sub-matrix of the q-th row and the s-th column.
  • T q,s ⁇ c qw+i,ws+ j ⁇ C:i,j ⁇ [w] ⁇ .
  • each component code includes two parts, one part is in A and the other part is in B, and each part occupies L T q,s respectively.
  • the component code C(w(q-1)+i) is one row of the codeword matrix C.
  • the part of the component code C(w(q-1)+i) that belongs to the virtual codeword matrix A is represented by a dashed line
  • the real part of the component code C(w(q-1)+i) is represented by a thick solid line.
  • Part of the codeword matrix B The part of the component code C(w(q-1)+i) belonging to the virtual codeword matrix is distributed in the submatrix T q-1,s of the virtual codeword matrix A.
  • the part of the component code C(w(q-1)+i) belonging to the real codeword matrix is distributed in the submatrix T q-1,L+s of the real codeword matrix B, where s ⁇ [L].
  • the submatrix of the virtual codeword matrix A is obtained by mapping the submatrix of the real codeword matrix B.
  • the unbalanced spatially coupled code means that there may be two or more intersections between the historical component code and the current component code.
  • the component code C(w(q-4)+j) and the current component code as C(w(q-1)+i) have 2 intersections, which are C(w(q-4)+j, 8*w+i) and C(w(q-4) +j,9*w+i).
  • the original RS code length is the finite field length minus 1, that is, 2 m -1.
  • the primitive RS code polynomial can be expressed as:
  • the RS codeword described by the check matrix is a truncated RS code.
  • the truncated partial code polynomials are a 112 X 112 +...+a 127 X 127 and a 240 X 240 +...+a 254 X 254 parts.
  • the component code is an RS code, which is not limited thereto.
  • the unbalanced spatially coupled codeword can be encoded using a non-binary BCH code.
  • BCH code is taken from the abbreviation of Bose, Ray-Chaudhuri and Hocquenghem. It is a coding method that has been studied more in coding theory, especially in error correction codes.
  • BCH codes can be used for multi-level, cyclic, error-correcting, variable-length digital coding to correct for multiple random error patterns.
  • BCH codes can also be used for multi-level phase shift keying of prime order or power order of prime numbers.
  • the component code of the unbalanced spatially coupled code is a non-binary BCH [252, 245, 5] over a finite field GF(16).
  • Code blocks are 42x126 symbols.
  • component code is an example of RS code and non-binary BCH for exemplary description, which is not limited, and any form of component code may be used in the embodiments of the present application.
  • component code may also be other types of code words, such as BCH code, low density parity check code (low density parity check code, LDPC) and the like.
  • FIG. 4 is only an exemplary illustration, and is not limited thereto.
  • the blocks in FIG. 4 may also have other shapes.
  • the codeword structure provided by the embodiment of the present application is exemplified mainly based on the description method of the tiled zipper code. It should be understood that the above is only an exemplary description, which is not strictly limited.
  • the encoding end may use an unbalanced spatial coupling manner to encode finite-field data symbols (hereinafter referred to as data streams).
  • data streams finite-field data symbols
  • a code block which can represent a part of a symbol matrix C with w rows and n columns of w ⁇ n, for example, a code block can be represented as a w ⁇ m matrix, that is, a semi-infinite-length code block sequence can be decomposed into multiple w ⁇ m
  • Each code block may be composed of multiple symbols, and the multiple symbols in each code block may include data symbols, or may also include check symbols.
  • a symbol can be understood as a carrier of information or data, for example, a symbol is a bit in a binary symbol; for example, a symbol is a character in a hexadecimal symbol. It should be understood that the relationship between symbols and bits is not limited, for example, a symbol may be one bit or multiple bits.
  • one or more symbols belong to code block B i
  • two or more symbols belong to one or more code blocks B j .
  • i and j are integers and j is less than i.
  • the component codes may be codewords of different structures.
  • the number of symbols belonging to different code blocks B j in the component codes can be different.
  • the component code is composed of data symbols and check symbols, or the symbols in the component code include data symbols and check symbols.
  • the check symbols in the component code can be generated by one or more symbols belonging to code block B i and two or more symbols belonging to two or more code blocks B j .
  • the generated check symbols belong to the code block B i .
  • the above code block B i or B j can be represented as a w ⁇ m matrix.
  • the code length of the component code is 2*m.
  • the symbols of the component codes come from the columns of different code blocks.
  • An example is: (if 1 (i,j,1), f 2 (i, j, 1), f 3 (i, j, 1)), (if 1 (i, j, 2), f 2 (i,j,2), f3 (i,j, 2 )),...,(if1(i,j,s), f2 ( i,j,s), f3 (i,j,s) )) and row row(i,j).
  • f 1 , f 2 , and f 3 are functions that output positive integers with (i, j, k) as variables.
  • i, j, k, w, s are all positive integers.
  • the symbols of the component codes come from the columns of different code blocks.
  • f 1 , f 2 , f 3 are functions that output positive integers.
  • i, j, k, w, s are all positive integers. j is less than or equal to w, and k is less than or equal to s.
  • f 1 , f 2 , f 3 are functions that output positive integers.
  • i, j, k, w, s are all positive integers. j is less than or equal to w, and k is less than or equal to s.
  • the component code may be, but is not limited to: BCH code (eg, non-binary BCH code), RS code, and LDPC code.
  • the component code is composed of the column coupling of the historical code block and the row of the current code block.
  • the one-component code can be expressed as: B(20-f 1 (1), f 2 (j), f 3 (1)), B(20-f 1 (2), f 2 (j ), f 3 (2)), B(20-f 1 (3), f 2 (j), f 3 (3)), B(20-f 1 (4), f 2 (j), f 3 (4)), B(20-f 1 (5), f 2 (j), f 3 (5)), B(20-f 1 (6), f 2 (j), f 3 (6)) , B(20-f 1 (7), f 2 (j), f 3 (7)), B(20,j).
  • the codeword structure is introduced from different angles in combination with Mode 1 and Mode 2, respectively.
  • FIG. 8 shows a comparison between the decoding performance of the unbalanced spatially coupled code provided by the present application and the balanced spatially coupled code of the prior art. Specifically, FIG. 8 shows the simulation comparison of the unbalanced spatially coupled code and the balanced spatially coupled code under different decoding window lengths.
  • the abscissa is the bit error rate input by the FEC decoder
  • the ordinate is the bit error ratio (BER) after decoding by the FEC decoder.
  • BER bit error ratio
  • the decoding window lengths of the curves L1 and L2 are both 10, such as W10; the decoding window lengths of the curves L3 and L4 are both 20, such as W20; the curves L5 and The decoding window length of the curve L6 is all 40, such as W40.
  • the unbalanced spatially coupled code has a lower Post-correction bit error rate. Therefore, to achieve the same performance, the unbalanced spatially coupled code needs a smaller decoding window length. Therefore, the codeword based on unbalanced spatial coupling has faster decoding convergence speed and shorter decoding delay.
  • codewords based on unbalanced spatial coupling can achieve shorter buffering delays.
  • the unbalanced space coupling is adopted, and the component codes of the same length are coupled with the historical codeword matrix with fewer rows. Therefore, the same number of real codewords are sent and received, and the unbalanced coupling has a shorter delay. Further, since the delay of sending and receiving the same number of real codewords is reduced, the occupied data buffer will also be reduced accordingly. Therefore, based on the codewords with unbalanced spatial coupling, the encoding and decoding apparatus can occupy a smaller buffer, and The power consumption caused by the data cache is also reduced accordingly.
  • code block is mainly used as an example for exemplary description, and it should be understood that the “code block” may also be replaced by a “frame”.
  • the coupling function between code blocks can also be replaced by the coupling function between frames.
  • the methods and operations implemented by the encoding end device can also be implemented by components (such as chips or circuits) that can be used for the encoding end device, and the methods and operations implemented by the decoding end device, It can also be implemented by components (eg, chips or circuits) that can be used for decoding end devices.
  • FIG. 9 is a schematic block diagram of a communication apparatus provided by an embodiment of the present application.
  • the apparatus 900 includes a transceiver unit 910 and a processing unit 920 .
  • the transceiving unit 910 can receive information or data from the outside, and the transceiving unit 910 can transmit information or data to the outside, and the processing unit 920 is used for data processing, such as channel coding.
  • the apparatus 900 may further include a storage unit, where the storage unit may be used to store instructions or/or data, and the processing unit 920 may read the instructions or/or data in the storage unit.
  • the storage unit may be used to store instructions or/or data
  • the processing unit 920 may read the instructions or/or data in the storage unit.
  • the apparatus 900 can be used to perform the actions performed by the encoding end in the above method embodiments.
  • the apparatus 900 can be an encoder or a component that can be configured in the encoder, and the processing unit 920 is used to perform the above method implementation.
  • the apparatus 900 can be used to perform the actions performed by the decoding end in the above method embodiments.
  • the apparatus 900 can be a decoder or a component that can be configured in the decoder, and the processing unit 920 is used to perform the above method. Processing-related operations on the decoding side in the embodiment.
  • the communication apparatus 900 is configured to perform the actions performed by the encoding end device in the above method embodiments, the transceiver unit 910 is configured to: acquire the bit sequence to be encoded; the processing unit 920 is configured to: the bit sequence to be encoded Perform spatial coupling encoding to obtain an encoded codeword, wherein the codeword includes the current code block bits and the historical code block bits, and the coupling relationship between the current code block bits and the historical code block bits is unbalanced coupling.
  • the communication apparatus 900 may implement steps or processes corresponding to the encoding end device in the method 300 according to the embodiment of the present application, and the communication apparatus 900 may include a method for executing the encoding end device in the method 300 in FIG. 3 . unit. Moreover, each unit in the communication device 900 and the above-mentioned other operations and/or functions are respectively for realizing the corresponding flow of the method 300 in FIG. 3 .
  • the communication device 900 is configured to perform the actions performed by the decoding end device in the above method embodiments, the transceiver unit 910 is configured to: receive the codeword to be decoded; the processing unit 920 is configured to: Decoding is performed; wherein, the code word includes the current code block bits and the historical code block bits, and the coupling relationship between the current code block bits and the historical code block bits is unbalanced coupling.
  • the communication apparatus 900 may implement steps or processes corresponding to the decoding end device in the method 600 according to the embodiment of the present application, and the communication apparatus 900 may include a method for executing the decoding end device in the method 600 in FIG. 6 . unit. Moreover, each unit in the communication device 900 and the other operations and/or functions mentioned above are respectively for realizing the corresponding flow of the method 600 in FIG. 6 .
  • the codeword is a codeword matrix C with n columns and semi-infinite rows, and the codeword matrix C includes an imaginary codeword matrix and a real codeword matrix;
  • the coupling relationship is unbalanced coupling, including: the coupling relationship between the sub-matrix of the virtual codeword matrix and the sub-matrix of the real codeword matrix is an unbalanced coupling relationship.
  • a sub-matrix of an imaginary codeword matrix is coupled to a sub-matrix of a historical real codeword matrix.
  • the rows of the codeword matrix C are denoted wq+i
  • the columns of the codeword matrix C are denoted ws+j
  • T q,s ⁇ c qw+i,ws+j ⁇ C ⁇ ;
  • T q,s represents the w ⁇ w sub-matrix of the qth row and the sth column of the codeword matrix C; L and w are positive integers; s ⁇ [2L]; i,j ⁇ [w].
  • ⁇ (q,s) represents the unbalanced coupling function
  • the superscript T represents the transposition
  • the value of q is fixed, and ⁇ (q, s) corresponding to at least two s are the same.
  • the characteristics of the codeword matrix C include:
  • the row of the codeword matrix C is expressed as wq+i, the column is expressed as ws+j, q ⁇ Z, s ⁇ [2L], and i,j ⁇ [w];
  • T q,s represents the w ⁇ w sub-matrix of the q-th row and the s-th column;
  • ⁇ (q, s) is a positive integer; the relationship between ⁇ and s is not bijective for at least one q ⁇ Z.
  • a codeword includes a plurality of component codes, each component code consisting of one or more columns of a historical code block coupled with a row of a current code block.
  • the codeword includes a plurality of code blocks
  • the plurality of component codes includes a first component code
  • at least two symbols in the first component code are from different codeword sub-matrices of the same code block.
  • the symbols in the first component code include one or more first symbols, and a plurality of second symbols, the first symbols belong to code block B i , the second symbols belong to one or more code blocks B j , where i and j are positive integers, and j is less than i.
  • the symbols in the first component code form a plurality of blocks, and the first component code is represented as:
  • f 1 , f 2 , f 3 are functions of outputting positive integers with (i, j, k) as variables; (i, j, k) represents the k-th w ⁇ w block in the code block B i
  • the jth column of ; (i,j) represents the rth row of the code block B i ; f 1 (i,j,1) ⁇ f 1 (i,j,2) ⁇ ... ⁇ f 1 (i,j,s )>0, 1 ⁇ f 2 (i,j,k) ⁇ w, 1 ⁇ f 3 (i,j,k) ⁇ s, k,w,s are all positive integers.
  • a codeword includes the following characteristics:
  • the codeword includes a plurality of component codes
  • the component codes are any one of the following: Reed-Solomon code RS code, BCH code, low density parity check code LDPC code.
  • the processing unit 920 in the above embodiments may be implemented by at least one processor or processor-related circuits.
  • the transceiver unit 910 may be implemented by a transceiver or a transceiver-related circuit.
  • the transceiving unit 910 may also be referred to as a communication interface or a communication unit or an input-output unit.
  • the storage unit may be implemented by at least one memory.
  • the apparatus 900 in the above embodiment may be a communication device or a chip (eg, an encoding chip or a decoding chip) configured in the communication device.
  • a chip eg, an encoding chip or a decoding chip
  • an embodiment of the present application further provides a communication apparatus 1000 .
  • the communication device 1000 includes a processor 1010, the processor 1010 is coupled with a memory 1020, the memory 1020 is used for storing computer programs or instructions or/or data, and the processor 1010 is used for executing the computer programs or instructions and/or data stored in the memory 1020. , so that the methods in the above method embodiments are executed.
  • the communication apparatus 1000 includes one or more processors 1010 .
  • the communication apparatus 1000 may further include a memory 1020 .
  • the communication device 1000 may include one or more memories 1020 .
  • the memory 1020 may be integrated with the processor 1010, or provided separately.
  • the wireless communication apparatus 1000 may further include a transceiver 1030, and the transceiver 1030 is used for signal reception and/or transmission.
  • the processor 1010 is configured to control the transceiver 1030 to receive and/or transmit signals.
  • the communication apparatus 1000 is configured to implement the operations performed by the encoding end device in the above method embodiments.
  • the processor 1010 is configured to implement the processing-related operations performed by the encoding end device in the above method embodiments
  • the transceiver 1030 is configured to implement the transceiving-related operations performed by the encoding end device in the above method embodiments.
  • the communication apparatus 1000 is configured to implement the operations performed by the decoding end device in the above method embodiments.
  • the processor 1010 is configured to implement the processing-related operations performed by the decoding end device in the above method embodiments
  • the transceiver 1030 is configured to implement the transceiving-related operations performed by the decoding end device in the above method embodiments.
  • the encoding end device in the embodiment of the present application may also be an optical communication device.
  • FIG. 11 shows a schematic diagram of an example of an optical communication device at the encoding end of the present application.
  • the optical communication device at the encoding end may include an input interface, an FEC encoder, a memory, a modulator, and an optical interface.
  • the input interface is used to obtain the bit sequence to be encoded
  • the FEC encoder is used to perform the process of determining the codeword matrix of the present application
  • the memory can be used to store relevant information of the codeword matrix.
  • the decoding end device in the embodiment of the present application may also be an optical communication device.
  • FIG. 12 shows a schematic diagram of an example of the optical communication device at the decoding end of the present application.
  • the optical communication device at the encoding end may include an optical interface, a demodulator, an FEC decoder, and an output interface.
  • the optical interface is used to obtain the codeword sequence to be decoded, and the FEC decoder is used to perform the process of determining the codeword matrix of the present application.
  • Embodiments of the present application further provide a computer-readable storage medium, on which computer instructions for implementing the method executed by the encoding end device or the method executed by the decoding end device in the above method embodiments are stored.
  • the computer program when executed by a computer, the computer can implement the method executed by the encoding end device or the method executed by the decoding end device in the above method embodiments.
  • Embodiments of the present application further provide a computer program product including instructions, which, when executed by a computer, enable the computer to implement the method executed by the encoding end device or the method executed by the decoding end device in the above method embodiments.
  • An embodiment of the present application further provides a communication system, where the communication system includes the encoding end device and the decoding end device in the above embodiments.
  • the encoding end device or the decoding end device may include a hardware layer, an operating system layer running on the hardware layer, and an application layer running on the operating system layer.
  • the hardware layer may include hardware such as a central processing unit (CPU), a memory management unit (MMU), and memory (also called main memory).
  • the operating system of the operating system layer may be any one or more computer operating systems that implement business processing through processes, such as a Linux operating system, a Unix operating system, an Android operating system, an iOS operating system, or a Windows operating system.
  • the application layer may include applications such as browsers, address books, word processing software, and instant messaging software.
  • the embodiments of the present application do not specifically limit the specific structure of the execution body of the methods provided by the embodiments of the present application, as long as the program in which the codes of the methods provided by the embodiments of the present application are recorded can be executed to execute the methods according to the embodiments of the present application.
  • the execution body of the method provided by the embodiments of the present application may be an encoding end device or a decoding end device, or a functional module in the encoding end device or the decoding end device that can call and execute a program.
  • aspects or features of the present application may be implemented as methods, apparatus, or articles of manufacture using standard programming and/or engineering techniques.
  • article of manufacture as used herein may encompass a computer program accessible from any computer-readable device, carrier or media.
  • the computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server, data center, etc., which includes one or more available mediums integrated.
  • Useful media may include, but are not limited to, magnetic media or magnetic storage devices (eg, floppy disks, hard disks (eg, removable hard disks), magnetic tapes), optical media (eg, optical disks, compact discs) , CD), digital versatile disc (digital versatile disc, DVD), etc.), smart cards and flash memory devices (for example, erasable programmable read-only memory (EPROM), card, stick or key drive, etc. ), or semiconductor media (such as solid state disk (SSD), etc., U disk, read-only memory (ROM), random access memory (RAM), etc. that can store programs medium of code.
  • SSD solid state disk
  • Various storage media described herein may represent one or more devices and/or other machine-readable media for storing information.
  • the term "machine-readable medium” may include, but is not limited to, wireless channels and various other media capable of storing, containing, and/or carrying instructions and/or data.
  • processors mentioned in the embodiments of the present application may be a central processing unit (central processing unit, CPU), and may also be other general-purpose processors, digital signal processors (digital signal processors, DSP), application-specific integrated circuits ( application specific integrated circuit, ASIC), off-the-shelf programmable gate array (field programmable gate array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
  • the memory mentioned in the embodiments of the present application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically programmable Erase programmable read-only memory (electrically EPROM, EEPROM) or flash memory.
  • Volatile memory may be random access memory (RAM).
  • RAM can be used as an external cache.
  • RAM may include the following forms: static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM) , double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchronous link dynamic random access memory (synchlink DRAM, SLDRAM) and Direct memory bus random access memory (direct rambus RAM, DR RAM).
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • SDRAM synchronous dynamic random access memory
  • SDRAM double data rate synchronous dynamic random access memory
  • ESDRAM enhanced synchronous dynamic random access memory
  • SLDRAM synchronous link dynamic random access memory
  • Direct memory bus random access memory direct rambus RAM, DR RAM
  • the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components
  • the memory storage module
  • memory described herein is intended to include, but not be limited to, these and any other suitable types of memory.
  • the disclosed apparatus and method may be implemented in other manners.
  • the apparatus embodiments described above are only illustrative.
  • the division of the above-mentioned units is only a logical function division.
  • multiple units or components may be combined or may be Integration into another system, or some features can be ignored, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, which may be in electrical, mechanical or other forms.
  • the units described above as separate components may or may not be physically separated, and components shown as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to implement the solution provided in this application.
  • each functional unit in each embodiment of the present application may be integrated into one unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the computer program product includes one or more computer instructions.
  • the computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • the computer may be a personal computer, a server, or a network device or the like.
  • Computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, computer, server, or data center over a wire (e.g.
  • coaxial cable fiber optic, digital subscriber line (DSL)) or wireless (eg, infrared, wireless, microwave, etc.) to another website site, computer, server, or data center.
  • DSL digital subscriber line
  • wireless eg, infrared, wireless, microwave, etc.

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  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

La présente invention concerne un procédé de codage, un procédé de décodage et un dispositif de communication. Le procédé de codage peut consister à : acquérir une séquence de bits à coder ; effectuer un codage de couplage spatial sur ladite séquence de bits, de manière à obtenir un mot de code codé, le mot de code codé comprenant un bit de bloc de code actuel et un bit de bloc de code historique, et la relation de couplage entre le bit de bloc de code actuel et le bit de bloc de code historique étant une relation de couplage non équilibré. Grâce audit procédé, la relation de couplage entre le bit de bloc de code actuel et le bit de bloc de code historique est un couplage non équilibré, c'est-à-dire qu'il peut exister deux points d'intersection ou plus entre le bloc de code actuel et le bloc de code historique, si bien que le temps requis pour que le code de couplage spatial non équilibré collecte tous les bits du mot de code est plus court que celui d'un code de couplage équilibré. Ainsi, un couplage non équilibré a un retard plus court pour envoyer le même nombre de mots de code réels.
PCT/CN2022/074480 2021-01-29 2022-01-28 Procédé de codage, procédé de décodage et dispositif de communication WO2022161449A1 (fr)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2991231A1 (fr) * 2014-09-01 2016-03-02 Alcatel-Lucent Deutschland AG Codage multiniveau et décodage multi-étagé
CN107026709A (zh) * 2016-02-01 2017-08-08 中兴通讯股份有限公司 一种数据包编码处理方法及装置、基站及用户设备
CN107124188A (zh) * 2016-02-24 2017-09-01 华为技术有限公司 极化码的编码方法、译码方法、编码设备和译码设备
CN108292925A (zh) * 2015-11-02 2018-07-17 华为技术有限公司 通过使用m阶GEL码对数据进行编码/解码的方法与设备

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EP2991231A1 (fr) * 2014-09-01 2016-03-02 Alcatel-Lucent Deutschland AG Codage multiniveau et décodage multi-étagé
CN108292925A (zh) * 2015-11-02 2018-07-17 华为技术有限公司 通过使用m阶GEL码对数据进行编码/解码的方法与设备
CN107026709A (zh) * 2016-02-01 2017-08-08 中兴通讯股份有限公司 一种数据包编码处理方法及装置、基站及用户设备
CN107124188A (zh) * 2016-02-24 2017-09-01 华为技术有限公司 极化码的编码方法、译码方法、编码设备和译码设备

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