WO2022160703A1

WO2022160703A1 - Pooling method, and chip, device and storage medium

Info

Publication number: WO2022160703A1
Application number: PCT/CN2021/115667
Authority: WO
Inventors: 周军; 常亮; 周亮; 杨雨桐
Original assignee: 成都商汤科技有限公司; 电子科技大学
Priority date: 2021-01-29
Filing date: 2021-08-31
Publication date: 2022-08-04
Also published as: CN113052760A; CN112862667A

Abstract

Provided are a pooling method, and a chip, a device and a storage medium. The method may comprise: acquiring a target feature map; splitting the target feature map to obtain a plurality of feature sub-maps, wherein at least some pixel values, within the same pooling window, in the target feature map are respectively in different feature sub-maps, and pixel values, at the same positions, within pooling windows are in the same feature sub-map; and performing parallel processing on pixels, which belong to different pooling windows, in each feature sub-map, so as to obtain a pooling result corresponding to the target feature map.

Description

Pooling method, chip, device and storage medium

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority of the Chinese patent application filed on January 29, 2021 with the application number 202110127626.9 and the invention titled "A pooling method, chip, device and storage medium", the entire contents of which are by reference Incorporated in this disclosure.

technical field

The present application relates to computer technology, and in particular to a pooling method, chip, device and storage medium.

Background technique

Pooling refers to down-sampling the input feature map, reducing the number of features and simplifying the computational complexity of convolutional networks while maintaining the invariance of features in certain dimensions (eg, rotation, translation, scaling). . There are two types of pooling processing: first, average pooling, that is, averaging the eigenvalues within the pooling window; second, max pooling, that is, maximizing the eigenvalues within the pooling window. Pooling processing usually needs to rely on artificial intelligence chips (hereinafter referred to as AI chips). Currently, there is an urgent need for accelerated methods for pooling.

SUMMARY OF THE INVENTION

In view of this, the present application discloses at least one pooling method, and the method may include: acquiring a target feature map; splitting the above target feature map to obtain several sub-feature maps; wherein, the above target feature maps are in the same pooling At least some of the pixel values in the window are in different sub-feature maps respectively, and the pixel values in the same position in each pooling window are in the same sub-feature map; the pixels belonging to different pooling windows in each sub-feature map are processed in parallel to obtain the above The pooling result corresponding to the target feature map.

In some of the illustrated embodiments, the above-mentioned parallel processing of pixels belonging to different pooling windows in each sub-feature map to obtain a pooling result corresponding to the above-mentioned target feature map includes: It is loaded into the shift register array, and according to the pooling instruction, the pixel values in the same position in the above-mentioned several sub-feature maps are pooled in parallel to obtain the pooling result corresponding to the above-mentioned target feature map.

In some of the illustrated embodiments, the above-mentioned parallel processing of pixels belonging to different pooling windows in each sub-feature map to obtain a pooling result corresponding to the above-mentioned target feature map includes: according to the fact that each sub-feature map is in the same pooling window The position of the pixel value of the sub-feature map is determined, and the shift operation mode of the shift register array corresponding to each sub-feature map is determined; the above-mentioned sub-feature maps are respectively loaded into the shift register array, and for each sub-feature map, according to The shift operation mode of the shift register array determined by the sub-feature map performs a shift operation on the pixel values stored in the shift registers in the above-mentioned shift register array. Partial pooling results of different pooling windows; according to the partial pooling results of each sub-feature map corresponding to different pooling windows, determine the pooling results corresponding to the above target feature maps.

In some of the illustrated embodiments, the above-mentioned splitting the above-mentioned target feature map to obtain several sub-feature maps includes: determining the pixel values at odd-numbered rows and odd-numbered column positions in the above-mentioned target feature map as the first sub-feature map ; The pixel value in the odd row, the even column position in the above-mentioned target feature map is determined as the second sub-feature map; The pixel value in the even row, the odd column position in the above-mentioned target feature map is determined as the third sub-feature map; The pixel values in the even-numbered rows and even-numbered columns in the above target feature map are determined as the fourth sub-feature map.

In some of the illustrated embodiments, the pixel values respectively included in the several sub-feature maps are loaded into the shift register array, and the pixel values in the same position in the several sub-feature maps are pooled in parallel according to the pooling instruction processing to obtain a pooling result corresponding to the target feature map, including: moving each pixel value included in the first sub-feature map to at least part of the shift registers included in the shift register array; Each pixel value included in the feature map is respectively moved to the above-mentioned partial shift register, so that the calculation kernel corresponding to each shift register in the partial shift register pools the received two pixel values according to the above-mentioned pooling instruction. The first pooling processing result is obtained; the pixel values included in the third sub-feature map are respectively moved to the partial shift registers, so that the calculation corresponding to each shift register in the partial shift registers The kernel performs pooling processing on the above-mentioned first pooling processing result and the received pixel value according to the above-mentioned pooling instruction to obtain the second pooling processing result; each pixel value included in the above-mentioned fourth sub-feature map is respectively moved to the above-mentioned part In the shift register, so that the calculation kernel corresponding to each shift register in the partial shift register performs the pooling process on the above-mentioned second pooling processing result and the received pixel value according to the above-mentioned pooling instruction, and obtains the third. Pooling processing result; outputting a third pooling processing result obtained by performing pooling processing on the computing cores corresponding to each of the shift registers in the partial shift registers, and obtaining a pooling result corresponding to the above target feature map.

In some of the illustrated embodiments, the above-mentioned pooling processing includes maximum pooling processing; the above-mentioned pooling instruction includes comparing the maximum value between the two; the above-mentioned moving each pixel value included in the above-mentioned first sub-feature map to the above-mentioned At least part of the shift registers included in the shift register array includes: moving each pixel value included in the first sub-feature map to the first registers of at least part of the shift registers included in the shift register array; Each pixel value included in the above-mentioned second sub-feature map is respectively moved to the above-mentioned partial shift register, so that the calculation kernel corresponding to each of the shift registers in the partial shift register, according to the above-mentioned pooling instruction, The pixel values are pooled to obtain a first pooling result, which includes: moving each pixel value included in the second sub-feature map to the second register of the partial shift register, so that the partial shift register and the partial shift register are respectively moved. The computing kernel corresponding to each shift register in the bit register obtains the maximum value of the values stored in the first register and the second register according to the pooling instruction, and stores the maximum value as the result of the first pooling process. in the first register above.

In some of the illustrated embodiments, the pixel values included in the third sub-feature map are respectively moved to the partial shift registers, so that the calculation kernel corresponding to each shift register in the partial shift registers According to the above-mentioned pooling instruction, performing pooling processing on the above-mentioned first pooling processing result and the received pixel values to obtain a second pooling processing result, including: moving each pixel value included in the above-mentioned third sub-feature map to the above-mentioned In the second register of the partial shift register, so that the computing kernel corresponding to each shift register in the partial shift register obtains the value stored in the first register and the second register according to the pooling instruction. The maximum value is stored in the above-mentioned first register as the above-mentioned second pooling processing result; the above-mentioned each pixel value included in the above-mentioned fourth sub-feature map is respectively moved to the above-mentioned part of the shift register, so that the The computing kernel corresponding to each shift register in the partial shift registers performs pooling processing on the above-mentioned second pooling processing result and the received pixel value according to the above-mentioned pooling instruction to obtain a third pooling processing result, including: Each pixel value included in the above-mentioned fourth sub-feature map is respectively moved to the second register of the above-mentioned partial shift register, so that the calculation kernel corresponding to each of the shift registers in the partial shift register obtains according to the above-mentioned pooling instruction. The maximum value among the values stored in the first register and the second register is stored in the first register as the third pooling processing result.

In some of the illustrated embodiments, the above-mentioned output is the third pooling processing result obtained by performing pooling processing on the computing kernels corresponding to each of the shift registers in the partial shift registers, to obtain a pool corresponding to the above-mentioned target feature map. The pooling result includes: outputting the value stored in the first register of the partial shift register to obtain the pooling result corresponding to the target feature map.

In some of the illustrated embodiments, the above-mentioned parallel processing of pixels belonging to different pooling windows in each sub-feature map to obtain a pooling result corresponding to the above-mentioned target feature map includes: combining each pixel included in the above-mentioned first sub-feature map The values are respectively moved to at least part of the shift registers included in the above-mentioned shift register array; according to the above-mentioned pooling instruction, the pixel values in any four up, down, left, and right adjacent shift registers included in the above-mentioned shift register array are pooled. operation to obtain the first partial pooling processing result, and store the above-mentioned first partial pooling processing result in the target shift register at the preset position among the above-mentioned four adjacent shift registers; The pixel values included in the figure are respectively moved to the above-mentioned partial shift registers; according to the above-mentioned pooling instruction, the pixel values in any two up and down adjacent shift registers included in the above-mentioned shift register array are pooled to obtain The second part of the pooling processing result is stored in the above-mentioned target shift register; the pixel values included in the above-mentioned third sub-feature map are respectively moved to the above-mentioned partial shift register; according to the above The pooling instruction performs a pooling operation on the pixel values in any two left and right adjacent shift registers included in the above-mentioned shift register array to obtain a third part of the pooling processing result, and the above-mentioned third part of the pooling processing result Store to the above-mentioned target shift register; move each pixel value included in the above-mentioned fourth sub-feature map to the above-mentioned partial shift register respectively, and move the pixel values in each of the above-mentioned partial shift registers to the above-mentioned target Shift Register.

According to the first partial pooling processing result, the second partial pooling processing result, the third partial pooling processing result in each target shift register included in the above-mentioned shift register array, and the above-mentioned fourth sub-feature map, the above-mentioned target feature is obtained. The pooling result corresponding to the graph.

In the illustrated embodiment, the above-mentioned pooling processing includes maximum pooling processing; the above-mentioned pooling instruction includes comparing the maximum value between the two; the above-mentioned preset position includes any four adjacent shift registers in the upper, lower, left and right. the lower left corner position; the above-mentioned target shift register includes the shift register at the lower left corner position in the above-mentioned four adjacent shift registers; the above-mentioned each pixel value included in the above-mentioned first sub-feature map is respectively moved to the above-mentioned shift At least part of the shift registers included in the register array include: moving each pixel value included in the first sub-feature map to the first registers of at least part of the shift registers included in the shift register array; The first part of the pooling processing result is obtained, and the above-mentioned first part of the pooling processing result is stored in the In the target shift register in the preset position among the above-mentioned four adjacent shift registers, including: moving the numerical value in the first register of each first shift register in the above-mentioned partial shift registers to the first shift register. In the second register of the second shift register on the right side of the shift register; store the larger value of the first register and the second register in each second shift register into the first register of each second shift register ; Move the numerical value in the first register of the above-mentioned second shift registers to the second register of the third shift register below the second shift register; The larger value in the two registers is stored in the first register of each third shift register; the value in the first register in each of the third shift registers is moved to the target shift on the left of the third shift register In the second register of the register; the larger value in the first register and the second register in each target shift register is stored in the first register of each target shift register as the above-mentioned first partial pooling processing result.

In some of the illustrated embodiments, moving each pixel value included in the second sub-feature map to the partial shift register includes: moving each pixel value included in the second sub-feature map to the above-mentioned partial shift register. In the second register of the partial shift register; the above-mentioned pooling operation is performed on the pixel values in any two upper and lower adjacent shift registers included in the above-mentioned shift register array according to the above-mentioned pooling instruction, and the second partial pooling is obtained. processing the result, and storing the second partial pooling processing result in the target shift register, including: moving the value in the second register of each first shift register in the partial shift register to the first shift register In the third register of the target shift register below the register; the larger value in the second register and the third register in each target shift register is used as the result of the above-mentioned second part of the pooling processing, and is stored in each target shift register. in the second register.

In some of the illustrated embodiments, the above-mentioned moving each pixel value included in the third sub-feature map to the partial shift register includes: moving each pixel value included in the third sub-feature map to the above-mentioned In the third register of the partial shift register; the above-mentioned pooling operation is performed on the pixel values in any two left and right adjacent shift registers included in the above-mentioned shift register array according to the above-mentioned pooling instruction, so as to obtain a third partial pooling operation. processing results, and storing the above-mentioned third partial pooling processing results in the above-mentioned target shift register, including: moving the value in the third register of each first shift register in the above-mentioned partial shift register to the first shift register In the fourth register of the second shift register on the right side of the register; the larger value in the third register and the fourth register in each second shift register is used as the result of the third part of the pooling process, and is stored in each second shift register. In the third register of the shift register; move the third part of the pooling processing result in the third register of the second shift register to the third register of the first shift register to the left of the second shift register in; the third part of the pooling processing result in the third register of the first shift register is moved to the third register of the target shift register below the first shift register.

In some of the illustrated embodiments, moving each pixel value included in the fourth sub-feature map to the partial shift register includes: moving each pixel value included in the fourth sub-feature map to the aforementioned part In the fourth register of the shift register; the above-mentioned moving the pixel values in each of the shift registers in the above-mentioned partial shift registers to the above-mentioned target shift register includes: The values in the four registers are moved to the fourth register of the target shift register below the first shift register.

In some of the illustrated embodiments, the first partial pooling processing result, the second partial pooling processing result, the third partial pooling processing result and the above-mentioned first partial pooling processing result in each target shift register included in the above-mentioned shift register array The pixel values corresponding to the four sub-feature maps are obtained to obtain the pooling result corresponding to the above target feature map, including: storing the larger value in the first register and the second register in each target shift register into each target shift register in the first register of each target shift register; store the larger value of the first register in each target shift register and the third register in the first register of each target shift register; store the first register in each target shift register The larger value in the fourth register is stored in the first register of each target shift register; the value stored in the first register of each target shift register is output to obtain the pooling result corresponding to the above target feature map.

In some of the illustrated embodiments, a plurality of temporary registers are connected to the periphery of the above-mentioned shift register array; the above-mentioned temporary registers are used to store the pixel values that overflow the above-mentioned shift register array when performing a numerical value transfer operation.

In some of the illustrated embodiments, the number of pixels included in at least some of the sub-feature maps in the above-mentioned several sub-feature maps is consistent with the number of shift registers included in the above-mentioned shift register array.

The present application also proposes a pooling method, which may include: obtaining an original feature map; dividing the original feature map into several target feature maps; pooling each target feature map according to the pooling method shown in any of the foregoing embodiments After processing, the pooling results corresponding to each target feature map are obtained; the pooling results corresponding to each target feature map are output to obtain the pooling results corresponding to the above-mentioned original feature maps.

The application also proposes a chip, the chip may include a controller; the controller is used to obtain a target feature map; the target feature map is split to obtain several sub-feature maps; wherein, the target feature maps are in the same At least part of the pixel values in the pooling window are in different sub-feature maps, and the pixel values in the same position in each pooling window are in the same sub-feature map; the pixels belonging to different pooling windows in each sub-feature map are processed in parallel, The pooling result corresponding to the above target feature map is obtained.

In some of the illustrated embodiments, the above-mentioned controller is configured to: load the pixel values respectively included in the above-mentioned sub-feature maps into the shift register array; The values are pooled in parallel to obtain the pooling results corresponding to the above target feature maps.

In some of the illustrated embodiments, the above-mentioned controller is configured to: determine the shift operation mode of the shift register array corresponding to each sub-feature map according to the positions of the pixel values in the same pooling window in each sub-feature map ; Load the above-mentioned several sub-feature maps into the shift register array respectively, and for each sub-feature map, shift the shift register array in the above-mentioned shift register array according to the shift operation mode of the shift register array determined for the sub-feature map. Shift operation is performed on the pixel values stored in the register, and the partial pooling results corresponding to different pooling windows in the sub-feature map are obtained by parallel pooling processing according to the pooling instruction; the partial pooling results corresponding to different pooling windows are obtained according to each sub-feature map. , and determine the pooling result corresponding to the above target feature map.

In some of the illustrated embodiments, the controller is configured to: determine the pixel values in odd rows and odd columns in the target feature map as the first sub-feature map; The pixel value of the position is determined as the second sub-feature map; the pixel value in the even-numbered row and odd-numbered column position in the above-mentioned target feature map is determined as the third sub-feature map; The pixel value is determined as the fourth sub-feature map.

In some of the illustrated embodiments, the controller is configured to: move each pixel value included in the first sub-feature map to at least part of the shift registers included in the shift register array; The included pixel values are respectively moved to the above-mentioned partial shift registers, so that the calculation kernel corresponding to each shift register performs pooling processing on the received two pixel values according to the above-mentioned pooling instructions, and obtains the first pooling processing. Result: each pixel value included in the above-mentioned third sub-feature map is respectively moved to the above-mentioned partial shift registers, so that the calculation kernel corresponding to each of the shift registers in the partial shift registers can perform the above-mentioned pooling instruction according to the above-mentioned pooling instruction. The first pooling processing result and the received pixel values are pooled to obtain the second pooling processing result; the pixel values included in the fourth sub-feature map are respectively moved to the above-mentioned partial shift registers, so as to be consistent with all the pixel values. The computing kernel corresponding to each shift register in the partial shift registers performs pooling processing on the above-mentioned second pooling processing result and the received pixel value according to the above-mentioned pooling instruction to obtain the third pooling processing result; The calculation kernels corresponding to each shift register in the partial shift registers respectively perform pooling processing to obtain the third pooling processing result, and obtain the pooling result corresponding to the above-mentioned target feature map.

In some of the illustrated embodiments, the above-mentioned pooling processing includes maximum pooling processing; the above-mentioned pooling instruction includes comparing the maximum value between the two; the above-mentioned controller is configured to: combine the pixel values included in the above-mentioned first sub-feature map are respectively moved to the first registers of at least part of the shift registers included in the above-mentioned shift register array; and each pixel value included in the above-mentioned second sub-feature map is respectively moved to the second registers of the above-mentioned part of the shift registers, to Make the calculation kernel corresponding to each shift register in the partial shift register obtain the maximum value of the values stored in the first register and the second register according to the pooling instruction, and use the maximum value as the first A pooling result is stored in the above-mentioned first register.

In some of the illustrated embodiments, the controller is configured to: move each pixel value included in the third sub-feature map to the second register of the partial shift register, so as to be consistent with the partial shift register. The computing kernel corresponding to each shift register obtains the maximum value of the values stored in the first register and the second register according to the above-mentioned pooling instruction, and stores the above-mentioned maximum value as the result of the above-mentioned second pooling process in the above-mentioned No. In a register; and, moving each pixel value included in the fourth sub-characteristic map to the second register of the partial shift register, so that the calculation kernel corresponding to each shift register in the partial shift register According to the pooling instruction, the maximum value of the values stored in the first register and the second register is acquired, and the maximum value is stored in the first register as the third pooling processing result.

In some of the illustrated embodiments, the controller is configured to: output the value stored in the first register of the partial shift register to obtain a pooling result corresponding to the target feature map.

The present application also proposes a chip, the chip may include a controller; the controller is used to obtain an original feature map; the original feature map is divided into several target feature maps; Each target feature map is pooled to obtain the pooling result corresponding to each target feature map; the pooling result corresponding to each target feature map is output to obtain the pooling result corresponding to the above-mentioned original feature map.

The present application also provides an electronic device, including the chip shown in any of the foregoing embodiments.

The present application also provides a computer-readable storage medium on which a computer program is stored, and when the program is executed by the controller, any one of the pooling methods described above is implemented.

In the above solution, since at least part of the pixel values in the same pooling window in the target feature map are split into different sub-feature maps respectively, and the pixels belonging to different pooling windows in each sub-feature map are processed in parallel, The pooling result corresponding to the above target feature map is obtained, thus improving the chip pooling processing efficiency, reducing the computational burden of the chip, and reducing the difficulty of chip design.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not limiting of the present application.

Description of drawings

In order to more clearly illustrate the technical solutions in one or more embodiments of the present application or related technologies, the accompanying drawings required in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings in the following description The drawings are only some of the embodiments described in one or more embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without any creative effort.

FIG. 1 is a schematic structural diagram of a shift register array according to an embodiment of the application;

2 is a schematic structural diagram of a PE shown in an embodiment of the application;

FIG. 3 is a flowchart of a pooling method according to an embodiment of the present application;

4 is a schematic diagram of a splitting process of a target feature map shown in an embodiment of the application;

5 is a schematic diagram of a splitting process of a target feature map shown in an embodiment of the application;

FIG. 6 is a schematic diagram of a pooling window shown in an embodiment of the present application;

FIG. 7 is a schematic diagram of shifting pixel values of a first sub-feature map according to an embodiment of the present application;

FIG. 8 is a schematic diagram of transferring pixel values for a second sub-feature map according to an embodiment of the present application;

FIG. 9 is a schematic diagram of transferring pixel values for a third sub-feature map according to an embodiment of the present application;

FIG. 10 is a flowchart of a pooling method according to an embodiment of the present application.

Detailed ways

Exemplary embodiments will be described in detail below, examples of which are illustrated in the accompanying drawings. Where the following description refers to the drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the illustrative examples below are not intended to represent all implementations consistent with this application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as recited in the appended claims.

The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the application. As used in this application and the appended claims, the singular forms "a," "above," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the term "and/or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items. It should also be understood that the word "if", as used herein, can be interpreted as "at the time of" or "when" or "in response to determining", depending on the context.

The following first introduces the shift register array used by the AI chip.

Please refer to FIG. 1 , which is a schematic structural diagram of a shift register array shown in the present application.

The shift register array may include a plurality of shift registers arranged vertically and horizontally, and each shift register may uniquely correspond to a computing core (Processing Element, hereinafter referred to as PE), and each PE is used to perform operations according to the values in the shift register. As shown in FIG. 1 , it can be considered that the above-mentioned shift register array includes a plurality of PEs arranged vertically and horizontally. Data can be moved between any two adjacent PEs (shift registers corresponding to PEs); each row of PEs can obtain data from the corresponding RAM (Random Access Memory). Assume that the size of the above shift register array is 8*8; the size of the feature map that needs to be input is also 8*8. When performing the operation of inputting the feature map into the shift register array, the above-mentioned feature map may be split into 8 rows of pixel values by a controller (eg, an array controller, also referred to as a processor), and the 8 rows of pixel values are divided into 8 rows respectively. The pixel value is input into the RAM corresponding to each row of PE. Then, the above-mentioned controller can move the pixel values in each RAM to the corresponding shift registers according to the position sequence of each pixel value in the above-mentioned feature map through the data moving instruction, so as to complete the input shift of the feature map. operation of the register.

The above-mentioned PE can perform data operation on the data in the shift register in response to the instruction.

Please refer to FIG. 2 , which is a schematic structural diagram of a PE shown in this application. As shown in FIG. 2 , the PE corresponding to the above-mentioned shift register may include a register, and an ALU (arithmetic and logic unit, arithmetic logic unit). The above-mentioned register may be a register obtained by dividing the storage space of the above-mentioned shift register. In some examples, the above-mentioned shift register may be configured as several registers (for example, register 1 and register 2 shown in FIG. 2 ) that can move data between each other according to actual requirements. The above-mentioned PE can perform arithmetic processing on the data in the multiple registers according to the arithmetic instruction. The ALU user described above performs logical operations. For example, when the PE receives an operation instruction such as adding or subtracting a value or comparing the size, the above-mentioned ALU can perform a relevant operation on the value stored in the register.

In some examples, the above-mentioned shift register array in the embodiments of the present application includes a plurality of shift registers, where the shift registers correspond to respective PEs, and each shift register (or each PE) includes a plurality of registers (For example: the first register, the second register, the third register, the fourth register, etc., the number of registers per PE is not limited here).

This application proposes a pooling method. The method splits at least part of the pixel values in the same pooling window in the target feature map into different sub-feature maps respectively, and processes the pixels belonging to different pooling windows in each sub-feature map in parallel to obtain the above target feature The pooling result corresponding to the graph can improve the efficiency of chip pooling processing, reduce the computational burden of the chip, and reduce the difficulty of chip design.

Please refer to FIG. 3 , which is a flowchart of a pooling method shown in this application. As shown in FIG. 3 , the above-mentioned pooling method may include steps S302 to S306.

S302, acquiring a target feature map.

The above target feature map is a feature map that needs to be pooled. In some examples, the above target feature map may be a feature map that needs to be pooled after convolution processing. In some examples, the target feature map may be a target feature map obtained by performing convolution processing on each PE in the shift register array. It is understandable that, the above-mentioned target feature map may be stored in the RAM corresponding to each row of PE.

S304, splitting the target feature map to obtain several sub-feature maps; wherein, at least some pixel values in the same pooling window in the target feature map are respectively in different sub-feature maps, and each pooling window is in the same sub-feature map The pixel values of the positions are in the same sub-feature map.

The pooling process usually includes a pooling window of a preset size and a step size of a preset size set according to business requirements. Taking the pooling window as 2*2 and the step size as 2 as an example, when performing the pooling operation on the feature map, it can be understood as starting from the first pixel value in the upper left corner of the feature map, and taking the first pixel value as the upper left corner. The elements form a pooling window of size 2*2. Then, taking the maximum value for each pixel value included in the pooling window, the pooling operation in the pooling window is completed. After that, according to the step size of 2, slide two pixel values to the right of the first pixel value, and form a 2*2 pooling window. Then, the pooling operation is performed on the pixel values in the current pooling window. By analogy, after the pooling operation is performed on all pooling windows, the maximum pixel value output by each pooling window is combined to obtain the pooling result corresponding to the above feature map.

The pooling window may include several pixel values. Each pixel value can be in a different position of the pooling window. Take the pooling window as 2*2 as an example. The 4 pixel values in the pooling window can be located in the upper left corner, lower left corner, upper right corner and lower right corner of the pooling window, respectively. In some examples, when performing S304, according to the size of the preset pooling window and the position distribution rule of each pixel value, it is determined that at least some of the pixel values in the same pooling window in the target feature map that satisfy the above-mentioned target feature map are in different positions, respectively. The sub-feature map of , the splitting method under the condition that the pixel values in the same position in each pooling window are in the same sub-feature map. Then, the target feature map is split according to the determined splitting method to obtain several sub-feature maps. For example, when the pooling window is 2*2, it can be determined that each pixel value in the pooling window is located in odd rows, odd columns; odd rows, even columns; even rows, odd columns; even rows, even columns. Therefore, pixel values in odd rows and odd columns in the target feature map can be determined as the first sub-feature map; pixel values in odd rows and even columns in the target feature map can be determined as the second sub-feature Figure; the pixel value in the position of the even row and the odd column in the above target feature map is determined as the third sub-feature map; the pixel value in the position of the even row and the even column in the above target feature map is determined as the fourth sub-feature map.

In this way, the above target feature map can be split, and at least some pixel values in the same pooling window in the above target feature map are obtained in different sub-feature maps respectively, and the pixels in the same position in each pooling window are obtained. The split results with values in the same sub-feature map condition, and 4 sub-feature maps are obtained.

In some examples, the correspondence between pooling and splitting schemes may be maintained in advance. When splitting the target feature map, parameters such as the pooling window and step size of the pooling process can be determined first. Then, according to the determined parameters, the above-mentioned corresponding relationship is queried to obtain a corresponding splitting scheme, and the above-mentioned target feature map is split according to the above-mentioned splitting scheme.

After the splitting of the target feature map is completed, S306 can be executed to perform parallel processing on pixels belonging to different pooling windows in each sub-feature map to obtain the pooling result corresponding to the above target feature map.

In some examples, the pixel values respectively included in the above-mentioned several sub-feature maps can be loaded into the shift register array, and according to the pooling instruction, the pixel values in the same position in the above-mentioned several sub-feature maps can be pooled in parallel to obtain the same The pooling result corresponding to the above target feature map. The above-mentioned pooling instruction may include an instruction corresponding to the current pooling process. This instruction can be pre-generated. When the pooling process is max pooling, the above-mentioned pooling instruction can compare the maximum value between the two. When the pooling process is average pooling, the above-mentioned pooling instructions may be summation or average value. The above pooling result may include a pooling result obtained after the target feature map is pooled.

In some examples, when S306 is executed, the pixel values included in each sub-feature map may be sequentially moved to the shift registers included in the shift register array according to a preset moving method, so that the pixels in the same position in each sub-feature map are moved. Pixel values are moved into the same shift register. In the above-mentioned preset moving method, each pixel value is moved to the above-mentioned shift register array according to the order of each pixel value in the target feature map. The above-mentioned transfer method is not particularly limited in this application. It is understandable that the pixel values of each sub-feature map are transferred according to the same transfer method to ensure that the pixel values in the same position in each sub-feature map are transferred to the same shift register.

Then, the PE corresponding to each shift register can perform parallel pooling processing on the received pixel values according to the pooling instruction to obtain the pooling result corresponding to the above target feature map. For example, take the pooling process as max pooling. When each shift register receives a new pixel value, it can compare the newly received pixel value with the stored pixel value through its corresponding PE, obtain the maximum value, and cover the maximum value to the shift register. Therefore, after the input of each sub-feature map split from the target feature map is completed, the above-mentioned shift register can include the maximum pixel value in each pooling window. After that, output the maximum pixel value stored in the register array to obtain the pooling result for the above target feature map.

In the above example, in the target feature map split result, all pixel values included in the same pooling window are in different sub-feature maps. At this time, the pixel values respectively included in the above-mentioned sub-feature maps can be loaded into the shift register. In the array, according to the pooling instruction, the pixel values in the same position in the above-mentioned several sub-feature maps are pooled in parallel to obtain the pooling result corresponding to the above-mentioned target feature map, so that multiple PEs corresponding to the shift register array can be used. The pooling processing operations of each pooling window are performed in parallel, thereby improving the pooling processing efficiency, reducing the computational burden of the chip, and reducing the difficulty of chip design.

In some examples, when S306 is performed, the shift operation mode of the shift register array corresponding to each sub-feature map may be determined according to the positions of the pixel values in the same pooling window in each sub-feature map.

After the above-mentioned shift operation mode is determined, the above-mentioned several sub-feature maps can be loaded into the shift register array respectively, and for each sub-feature map, according to the shift operation mode of the shift register array determined for the sub-feature map The pixel values stored in the shift register array in the above-mentioned shift register array perform a shift operation, and then perform parallel pooling processing according to the pooling instruction to obtain partial pooling results corresponding to different pooling windows in the sub-feature map. The graphs correspond to partial pooling results of different pooling windows, and determine the pooling results corresponding to the above target feature graphs.

In the above example, in the target feature map split result, some pixel values in the same pooling window are in the same sub-feature map. At this time, the pixel values in the same pooling window in each sub-feature map can be pooled first. The partial pooling results corresponding to different pooling windows in each sub-feature map are obtained; then the partial pooling results corresponding to the same pooling window in each sub-feature map are pooled again to obtain the final pooling result. Multiple PEs corresponding to the shift register array can be used to perform the pooling processing operation of each pooling window in parallel, thereby improving the pooling processing efficiency, reducing the computational burden of the chip, and reducing the difficulty of chip design.

In some examples, in order to maximize the utilization of the PE corresponding to the shift register array and further improve the pooling efficiency, the number of pixels included in at least some of the sub-feature maps in the above-mentioned sub-feature maps is the same as the number of pixels included in the shift register array in the above-mentioned shift register array. The number is the same.

In some examples, when determining the splitting strategy, it can be determined according to the number of shift registers included in the shift register array, so as to ensure that each sub-feature map obtained by splitting the target feature map contains some sub-feature maps or The number of pixels included in all the sub-feature maps is the same as the number of the above-mentioned shift registers.

Therefore, all the PEs corresponding to the shift registers can be pooled in parallel, thereby maximizing the utilization of the PEs corresponding to the shift register array, further improving the pooling efficiency, reducing the computational burden of the chip, and reducing the difficulty of chip design.

Embodiments are described below with reference to specific scenarios.

Scenario 1: The size of the target feature map is 16*16, the size of the pooling window is 2*2, the step size is 2, the pooling process is maximum pooling process, and the pooling instruction includes comparing the maximum value between the two. The size of the shift register array included in the AI chip for pooling is 8*8.

When the pooling operation is performed by the AI chip, the above target feature map can be split to obtain four sub-feature maps. In some examples, pixel values in odd rows and odd columns in the target feature map may be determined as the first sub-feature map; pixel values in odd rows and even columns in the target feature map may be determined as the second sub-feature map sub-feature map; the pixel values in the even-numbered rows and odd-numbered columns in the above-mentioned target feature map are determined as the third sub-feature map; the pixel values in the even-numbered rows and even-numbered columns in the above-mentioned target feature map are determined as the fourth sub-feature picture.

Please refer to FIG. 4 , which is a schematic diagram of a splitting process of a target feature map shown in this application. As shown in Figure 4, the target feature map is 16*16. Among them, black squares indicate pixels in odd rows and columns in the target feature map; dark gray squares indicate pixels in odd rows and even columns in the target feature map; white squares indicate pixels in even rows and odd columns in the target feature map The light gray squares refer to the pixels in the even-numbered rows and even-numbered columns in the target feature map.

The target feature map is split according to the aforementioned splitting method to obtain the first to fourth sub-feature maps. The size of each sub-feature map is 8*8, which is consistent with the size of the above-mentioned shift register array. After the splitting is completed, each pixel value included in the above-mentioned first sub-feature map can be moved to at least part of the shift registers corresponding to the above-mentioned shift register array according to the preset moving method. In some examples, each pixel value included in the first sub-feature map may be moved to the first registers of at least part of the shift registers included in the shift register array according to a preset moving method. In some embodiments, each pixel value needs to be moved as a whole among the shift registers in the shift register array, then according to the moving direction and the moving step size, an idle shift can be reserved at a preset position in the shift register array Register in order to store the moved pixel value. Assuming that each pixel value needs to be moved to the right by one step as a whole, then at least the free shift register on the right adjacent to the pixel value of the rightmost column in each pixel value storage location needs to be reserved. , and other moving methods are the same, and will not be repeated here. In this way, all the pixel values included in the first sub-feature map can be transferred to the shift registers included in the shift register array.

Then, each pixel value included in the second sub-feature map can be respectively moved to the partial shift register according to the above-mentioned preset moving method, so that the computing kernel corresponding to the shift register can The received two pixel values are pooled to obtain a first pooling result. In some examples, each pixel value included in the second sub-feature map can be respectively moved to the second register of the partial shift register according to the above-mentioned preset moving method, so that each computing core can perform the pooling instruction according to the above-mentioned pooling instruction. , obtain the maximum value among the values stored in the first register and the second register, and store the maximum value in the first register as the result of the first pooling process. Therefore, the pixel values in the first sub-feature map and the second sub-feature map respectively in the same pooling window can be compared to obtain the maximum value and store it in the shift register.

Afterwards, each pixel value included in the above-mentioned third sub-feature map can be respectively moved to the above-mentioned partial shift registers according to the above-mentioned preset moving method, so that each computing kernel can process the above-mentioned first pooling process according to the above-mentioned pooling instruction The result is pooled with the received pixel value to obtain a second pooling result. In some examples, according to the above-mentioned preset moving method, each pixel value included in the above-mentioned third sub-feature map is respectively moved to the second register of the above-mentioned partial shift register, so that each computing core can be based on the above-mentioned pooling instruction, Obtain the maximum value among the values stored in the first register and the second register, and store the maximum value in the first register as the second pooling processing result. Therefore, the pixel values in the first sub-feature map, the second sub-feature map and the third sub-feature map respectively in the same pooling window can be compared to obtain the maximum value and store it in the shift register.

After that, each pixel value included in the above-mentioned fourth sub-feature map can be respectively moved to the above-mentioned partial shift register according to the above-mentioned preset moving method, so that each computing kernel can process the above-mentioned second pooling process according to the above-mentioned pooling instruction. The result is pooled with the received pixel value to obtain a third pooling result. In some examples, each pixel value included in the above-mentioned fourth sub-feature map is respectively moved to the second register of the above-mentioned partial shift register according to the above-mentioned preset moving method, so that each computing core can obtain the The maximum value among the values stored in the first register and the second register is stored in the first register as the third pooling processing result. In this way, the pixel values in the first sub-feature map, the second sub-feature map, the third sub-feature map and the fourth sub-feature map in the same pooling window can be compared, and the maximum value can be obtained and stored in the shift in the register.

Finally, the third pooling processing result obtained by performing pooling processing in each computing core can be outputted to obtain the pooling result corresponding to the above-mentioned target feature map. In some examples, the value stored in the first register of the partial shift register can be output to obtain the pooling result corresponding to the target feature map. In this way, the maximum pooling process for the above target feature map can be completed, and the corresponding pooling result can be obtained.

It should be noted that, the sequence in which each of the above sub-feature maps is input to the shift register is only for schematic illustration. Any input order can be used in practical applications.

When the pooling process is average pooling, the specific process may refer to the above-mentioned embodiment, only the pooling instructions are different, which will not be described in detail here.

Scenario 2: The size of the target feature map is 17*17, the size of the pooling window is 3*3, the step size is 2, the pooling process is the maximum pooling process, and the pooling command is the above-mentioned pooling command, including comparing the values between the two. maximum value. The size of the shift register array included in the AI chip for pooling is 9*9.

When the pooling operation is performed by the AI chip, the above target feature map can be split to obtain four sub-feature maps.

Please refer to FIG. 5 , which is a schematic diagram of a splitting process of a target feature map shown in the present application. As shown in Figure 5, the target feature map is 17*17. Among them, black squares indicate pixels in odd rows and columns in the target feature map; dark gray squares indicate pixels in odd rows and even columns in the target feature map; white squares indicate pixels in even rows and odd columns in the target feature map The light gray squares refer to the pixels in the even-numbered rows and even-numbered columns in the target feature map.

The target feature map is split according to the aforementioned splitting method to obtain the first to fourth sub-feature maps. The first sub-feature map is 9*9, the second sub-feature map is 9*8, the third sub-feature map is 8*9, and the fourth sub-feature map is 8*8. The size of the above-mentioned first sub-feature map is consistent with the size of the above-mentioned shift register array.

Please refer to FIG. 6, which is a schematic diagram of a pooling window shown in this application. Among them, the pooling window shown in FIG. 6 includes the pooling window when the pooling window size is 3*3 and the step size is 2 when the above target feature map is pooled. As shown in Figure 6, the dashed box represents a pooling window in the target feature map. The pooling window can include 4 black blocks, 2 dark gray blocks, 2 white blocks and 1 light gray block. When performing the pooling operation on the pooling window, according to the position of the pixel values in the same pooling window in each sub-feature map, for each pooling window, S61-S62 can be executed first, and it is determined that they are in the upper left corner respectively. , the maximum value among the four pixel values in the upper right corner, the lower left corner, and the lower right corner, that is, the first maximum value among the four adjacent pixel values in the upper, lower, left, and right corners corresponding to the pooling window. Then execute S63-S64 to determine the maximum value of the two pixel values in the first row, second column, and the third row, second column, that is, the pooling window corresponds to the upper and lower adjacent sub-feature maps in the second sub-feature map. The second largest of the two pixel values of . Then execute S65-S66 to determine the maximum value of the two pixel values in the first column of the second row and the third column of the second row, that is, the left and right adjacent pixels in the third sub-feature map corresponding to the pooling window are determined. The third largest of the two pixel values. Finally, determine the maximum value among the above-mentioned first maximum value, second maximum value, third maximum value and the pixel value in the middle (that is, the pixel value in the fourth sub-feature map corresponding to the pooling window), and set the The determined maximum value is taken as the result of max pooling for this pooling window.

In some examples, S61 can be executed to move each pixel value included in the first sub-feature map to at least part of the shift registers included in the shift register array according to a preset moving method. In some examples, each pixel value included in the first sub-feature map may be moved to the first registers of at least part of the shift registers included in the shift register array according to a preset moving method.

Then, S62 can be executed, and the computing kernel corresponding to the above-mentioned at least part of the shift registers can perform a pooling operation on the pixel values in any four adjacent shift registers included in the above-mentioned shift register array according to the above-mentioned pooling instruction , obtain the first partial pooling processing result, and store the first partial pooling processing result in the target shift register at the preset position among the four adjacent shift registers. In some examples, the above-mentioned preset position includes the position of the lower left corner of any four adjacent shift registers. It is understandable that, for the solution in which the above-mentioned preset positions are other positions, reference may be made to this embodiment.

The above-mentioned target shift register includes a shift register located at the lower left corner among the above-mentioned four adjacent shift registers. Please refer to FIG. 7 . FIG. 7 is a schematic diagram of transferring pixel values of the first sub-feature map according to the present application. It should be noted that any four adjacent shift registers in the shift register array can be regarded as a group of shift registers shown in FIG. 7 . Taking the second shift register in the group of shift registers shown in FIG. 7 as an example, in another group of shift registers, it may be the first shift register, or the third shift register or the target shift register. register. FIG. 7 only schematically illustrates the movement flow of pixel values in one group of shift registers, and the movement flow of pixel values in other groups of shift registers can be illustrated with reference to FIG. 7 , and will not be described in detail in this application. As shown in FIG. 7 (PE is not shown in FIG. 7 ), in a group of shift registers, the shift register at the upper left corner can be regarded as the first shift register, and the shift register to the right of the first shift register The register can be regarded as the second shift register, the shift register below the second shift register can be regarded as the third shift register, and the shift register to the left of the third shift register can be regarded as the above-mentioned target shift register .

In FIG. 7, S71, the value in the first register of each of the first shift registers in the above-mentioned partial shift registers can be moved to the second register of the second shift register to the right of the first shift register.

Then, each computing core can store the larger value in the first register and the second register in each second shift register into the first register in each second shift register.

S72, the value in the first register of the second shift registers can be moved to the second register of the third shift register below the second shift register.

Then, each computing core can store the larger value in the first register and the second register in each third shift register into the first register in each third shift register.

S73, the value in the first register of the third shift registers can be moved to the second register of the target shift register on the left side of the third shift register.

Then, each computing core can store the larger value in the first register and the second register in each target shift register as the above-mentioned first partial pooling processing result in the first register of each target shift register. In this way, the maximum value of the four pixel values in the upper left corner, upper right corner, lower left corner and lower right corner of the same pooling window can be determined, that is, among the four adjacent pixel values in the first sub-feature map. The first maximum value is stored in the aforementioned target shift register.

After that, S63 can be executed to move each pixel value included in the second sub-feature map to the partial shift register according to the preset moving method. In some examples, each pixel value included in the second sub-feature map can be respectively moved to the second register of the partial shift register according to the preset moving method.

Then, each computing core can execute S64, and according to the above-mentioned pooling instruction, perform a pooling operation on the pixel values in any two upper and lower adjacent shift registers included in the above-mentioned shift register array, to obtain a second partial pooling processing result , and store the above-mentioned second partial pooling processing result in the above-mentioned target shift register.

Please refer to FIG. 8 . FIG. 8 is a schematic diagram of transferring pixel values of the second sub-feature map according to the present application. It should be noted that any two adjacent shift registers in the shift register array can be regarded as a group of shift registers shown in FIG. 8 . FIG. 8 only schematically illustrates the movement flow of pixel values in one group of shift registers, and the movement flow of pixel values in other groups of shift registers can be illustrated with reference to FIG. 8 , and will not be described in detail in this application. As shown in FIG. 8 (the register is not shown in FIG. 8 ), the shift register at the upper position in a group of shift registers can be regarded as the first shift register, and the shift register below the first shift register can be regarded as the first shift register. Think of it as the above target shift register.

S81 , moving the value in the second register of each first shift register in the partial shift registers to the third register of the target shift register below the first shift register.

S82, each computing core may store the larger value in the second register and the third register in each target shift register as the result of the above-mentioned second partial pooling processing in the second register of each target shift register.

Therefore, the maximum value of the two pixel values in the first row, second column, and the third row and second column position in the same pooling window can be determined, that is, the two adjacent top and bottom in the second sub-feature map. The second largest of the pixel values is stored in the above-mentioned destination shift register.

After that, S65 can be executed, and each pixel value included in the third sub-feature map is respectively moved to the partial shift register according to the preset moving method. In some examples, each pixel value included in the third sub-feature map is respectively moved to the third register of the partial shift register according to the above-mentioned preset moving method.

Then, each computing core can execute S66, and according to the above-mentioned pooling instruction, perform a pooling operation on the pixel values in any two left and right adjacent shift registers included in the above-mentioned shift register array, and obtain a third partial pooling processing result , and store the above-mentioned third partial pooling processing result in the above-mentioned target shift register.

Please refer to FIG. 9. FIG. 9 is a schematic diagram of transferring pixel values of the third sub-feature map according to the present application. It should be noted that any two left and right adjacent shift registers in the shift register array can be regarded as a group of shift registers shown in FIG. 9 . FIG. 9 only schematically illustrates the movement flow of pixel values in one group of shift registers. The movement flow of pixel values in other groups of shift registers can be illustrated with reference to FIG. 9 , and will not be described in detail in this application. As shown in FIG. 9 (the register is not shown in FIG. 9 ), the shift register in the upper left corner of a group of shift registers can be regarded as the first shift register, and the shift register to the right of the first shift register The register can be regarded as the second shift register, the shift register below the second shift register can be regarded as the third shift register, and the shift register to the left of the third shift register can be regarded as the above-mentioned target shift register .

S91 , moving the values in the third registers of the first shift registers in the partial shift registers to the fourth register of the second shift registers to the right of the first shift register.

S92, each computing core may store the larger value in the third register and the fourth register in each second shift register as the above-mentioned third partial pooling processing result in the third register of each second shift register.

At this point, the maximum value of the two pixel values in the second row, the first column and the second row, the third column in the same pooling window, that is, the two adjacent pixel values on the left and right in the third sub-feature map. The third maximum value of is stored in the above-mentioned second shift register.

Afterwards, the above-mentioned third maximum value (the result of the third partial pooling process) can be moved to the above-mentioned target shift register. That is, S93 is executed, and the third part of the pooling processing result in the third register of the second shift register is moved to the third register of the first shift register on the left side of the second shift register. S94: Move the third part of the pooling processing result in the third register of the first shift register to the third register of the target shift register below the first shift register. Therefore, the maximum value of the two pixel values in the second row, the first column and the second row, the third column in the same pooling window, that is, the left and right adjacent pixel values in the third sub-feature map. The third maximum value is stored in the aforementioned target shift register. In some examples, when data is moved from the second shift register to the target shift register, the data can also be moved to the third shift register first, and then moved to the above-mentioned target shift register.

After that, S67 can be executed, and each pixel value included in the fourth sub-feature map is respectively moved to the partial shift register according to the above-mentioned preset moving method. In some examples, each pixel value included in the fourth sub-feature map can be respectively moved to the fourth register of the partial shift register according to the above-mentioned preset moving method.

Then, S68 can be executed to move the pixel values in each of the shift registers in the partial shift registers to the target shift register. In some examples, the values in the fourth register of each of the first shift registers in the above-mentioned partial shift registers may be moved to the fourth register of the target shift register below the first shift register. So far, the above target shift register includes the first part of the pooling processing result (the first maximum value), the second part of the pooling processing result (the second maximum value), and the third part of the pooling processing result (the third maximum value) ), and the pixel value in the middle of the pooling window (the pixel value corresponding to the fourth sub-feature map).

Finally, the first partial pooling processing result, the second partial pooling processing result, the third partial pooling processing result and the pixels corresponding to the fourth sub-feature map in each target shift register included in the shift register array can be Values are compared, and the maximum value among them is output to obtain the pooling result corresponding to the above target feature map. In some examples, each computing core may store the larger value of the first register and the second register of each target shift register into the first register of each target shift register.

Then, the larger value of the first register and the third register of each target shift register may be stored in the first register of each target shift register.

Afterwards, the larger value of the first register and the fourth register of each target shift register may be stored in the first register of each target shift register.

Finally, the value stored in the first register of each target shift register is output, and the pooling result corresponding to the above target feature map is obtained. In this way, the maximum value obtained by performing maximum pooling on each pooling window can be stored in the above target shift register, and by outputting the maximum value in each target shift register, the corresponding target feature map can be obtained. Pooling results. In some examples, in order to further improve the pooling efficiency, a plurality of temporary registers are connected to the periphery of the above-mentioned shift register. Wherein, the temporary register is used for storing the pixel value overflowing the shift register array when the numerical value transfer operation is performed. Therefore, in the process of data transfer, it is not necessary to store the pixel values of the overflow shift register array in RAM, but only the overflow pixel values need to be stored in the temporary register, thereby improving the data transfer efficiency and thus the pooling efficiency.

In some instances, the size of the feature map to be pooled may be larger than the size of the shift register array. This application proposes a pooling method. Please refer to FIG. 10. FIG. 10 is a method flowchart of a pooling method shown in this application. As shown in Figure 10, the above method may include:

S1002, obtain the original feature map.

S1004: Divide the above original feature map into several target feature maps.

S1006, performing pooling processing on each target feature map according to the pooling method shown in any of the foregoing embodiments, to obtain a pooling result corresponding to each target feature map.

S1008, output the pooling result corresponding to each target feature map, and obtain the pooling result corresponding to the above-mentioned original feature map.

In the above solution, the original feature map can be divided into several target feature maps first, and then each target feature map can be pooled according to the pooling method shown in any of the above embodiments, and the pooling result corresponding to each target feature map can be obtained. . Finally, the pooling result corresponding to each target feature map is output, and the pooling result corresponding to the original feature map above is obtained. Thus, efficient pooling of the above-mentioned original feature maps larger than the shift register array can be achieved.

The present application also proposes a chip. The above-mentioned chip may include a controller; the above-mentioned controller is used to obtain a target feature map; the above-mentioned target feature map is split to obtain several sub-feature maps; wherein, at least some of the pixels in the same pooling window in the above-mentioned target feature map The values are in different sub-feature maps, and the pixel values in the same position in each pooling window are in the same sub-feature map; the pixels belonging to different pooling windows in each sub-feature map are processed in parallel to obtain the pool corresponding to the above target feature map. result.

In some of the illustrated embodiments, the above-mentioned controller is configured to: load the pixel values respectively included in the above-mentioned several sub-feature maps into the shift register array, and, according to the pooling instruction, perform the processing for the pixels in the same position in the above-mentioned several sub-feature maps The values are pooled in parallel to obtain the pooling results corresponding to the above target feature maps.

In some of the illustrated embodiments, the controller is configured to: move each pixel value included in the first sub-feature map to at least part of the shift registers included in the shift register array; The included pixel values are respectively moved to the above-mentioned partial shift registers, so that the calculation kernel corresponding to each shift register performs pooling processing on the received two pixel values according to the above-mentioned pooling instructions, and obtains the first pooling processing. Result; each pixel value included in the above-mentioned third sub-feature map is respectively moved to the above-mentioned partial shift register, so that each computing kernel can pool the above-mentioned first pooling processing result and the received pixel value according to the above-mentioned pooling instruction. to obtain a second pooling result; move each pixel value included in the fourth sub-feature map to the above-mentioned partial shift register, so that each computing core performs the second pooling according to the above-mentioned pooling instruction. The processing result and the received pixel values are pooled to obtain a third pooling result; the third pooling result obtained by performing pooling on each computing core is output to obtain a pooling result corresponding to the above target feature map.

In some of the illustrated embodiments, the above-mentioned controller is configured to: output the value stored in the first register of the above-mentioned partial shift register, and obtain the pooling result corresponding to the above-mentioned target feature map.

In some of the illustrated embodiments, the controller is configured to: move each pixel value included in the first sub-feature map to at least part of the shift registers included in the shift register array; Perform a pooling operation on the pixel values in any four adjacent shift registers included in the above-mentioned shift register array to obtain a first partial pooling processing result, and store the above-mentioned first partial pooling processing result in the above-mentioned four upper, lower, and lower The left and right adjacent shift registers are located in the target shift register at the preset position; each pixel value included in the above-mentioned second sub-feature map is respectively moved to the above-mentioned partial shift register; according to the above-mentioned pooling instruction, the above-mentioned shift register is moved. Perform a pooling operation on the pixel values in any two up and down adjacent shift registers included in the bit register array to obtain a second partial pooling result, and store the second partial pooling result in the target shift register ; Each pixel value included in the above-mentioned third sub-feature map is moved into the above-mentioned partial shift register respectively; According to the above-mentioned pooling instruction, to the pixel in any two left and right adjacent shift registers included in the above-mentioned shift register array Perform a pooling operation on the values to obtain the third part of the pooling processing result, and store the above-mentioned third part of the pooling processing result in the above-mentioned target shift register; move each pixel value included in the above-mentioned fourth sub-feature map to the above-mentioned part respectively In the shift register, the pixel values in each shift register in the partial shift registers are transferred to the target shift register. According to the first partial pooling processing result, the second partial pooling processing result, the third partial pooling processing result in each target shift register included in the above-mentioned shift register array, and the above-mentioned fourth sub-feature map, the above-mentioned target feature is obtained. The pooling result corresponding to the graph.

In some of the illustrated embodiments, the above-mentioned pooling processing includes maximum pooling processing; the above-mentioned pooling instruction includes comparing the maximum value between the two; the above-mentioned preset position includes any four adjacent shift registers in the upper, lower, left and right. The above-mentioned target shift register includes the shift register at the lower-left corner position in the above-mentioned four adjacent shift registers; the above-mentioned controller is used for: respectively moved to the first register of at least part of the shift registers included in the above-mentioned shift register array; the above-mentioned controller is used for: moving the value in the first register of each first shift register in the above-mentioned partial shift register to the first register In the second register of the second shift register on the right side of the shift register; store the larger value of the first register and the second register in each second shift register into the first register of each second shift register ; Move the numerical value in the first register of the above-mentioned second shift registers to the second register of the third shift register below the second shift register; The larger value in the two registers is stored in the first register of each third shift register; the value in the first register in each of the third shift registers is moved to the target shift on the left of the third shift register In the second register of the register; the larger value in the first register and the second register in each target shift register is stored in the first register of each target shift register as the above-mentioned first partial pooling processing result.

In some of the illustrated embodiments, the above-mentioned controller is used for: moving each pixel value included in the above-mentioned second sub-feature map to the second register of the above-mentioned partial shift register; the above-mentioned controller is used for: shifting the above-mentioned part The value in the second register of each first shift register in the register is moved to the third register of the target shift register below the first shift register; the second register and the third register in each target shift register are moved. The larger value is stored in the second register of each target shift register as the result of the above-mentioned second partial pooling process.

In some of the illustrated embodiments, the above-mentioned controller is used for: moving each pixel value included in the above-mentioned third sub-feature map to the third register of the above-mentioned partial shift register; the above-mentioned controller is used for: shifting the above-mentioned part The value in the third register of each first shift register in the register is moved to the fourth register of the second shift register to the right of the first shift register; The larger value in the four registers is used as the result of the above-mentioned third part of the pooling processing, and is stored in the third register of each second shift register; the third part in the third register of the above-mentioned second shift register is pooled The result is moved to the third register of the first shift register on the left side of the second shift register; the third part of the pooling processing result in the third register of the first shift register is moved to the first shift register. in the third register of the destination shift register below the shift register.

In some of the illustrated embodiments, the above-mentioned controller is used for: moving each pixel value included in the above-mentioned fourth sub-feature map to the fourth register of the above-mentioned partial shift register; the above-mentioned controller is used for: shifting the above-mentioned part The value in the fourth register of each first shift register in the registers is moved to the fourth register of the target shift register below the first shift register.

In some of the illustrated embodiments, the above-mentioned controller is used to: store the larger value of the first register and the second register in each target shift register into the first register of each target shift register; store each target shift register The larger value in the first register and the third register in the shift register is stored in the first register of each target shift register; the larger value in the first register and the fourth register in each target shift register is stored Store the value in the first register of each target shift register; output the value stored in the first register of each target shift register, and obtain the pooling result corresponding to the above target feature map.

The present application also proposes a chip. The above-mentioned chip may include a controller; the above-mentioned controller is used to obtain an original feature map; the above-mentioned original feature map is divided into several target feature maps; and each target feature map is pooled according to the pooling method shown in any of the foregoing embodiments. , obtain the pooling result corresponding to each target feature map; output the pooling result corresponding to each target feature map, and obtain the pooling result corresponding to the above-mentioned original feature map.

The present application also provides an electronic device, which includes the chip shown in any of the foregoing embodiments. For example, the electronic device may be a smart terminal such as a mobile phone, or may be other devices that have a camera and can perform image processing. Exemplarily, when the electronic device performs pooling processing on the collected images, the chip of the embodiment of the present application may be used to perform the pooling task. Since the above chip has higher pooling processing efficiency and higher performance, the use of this chip can assist in improving the processing efficiency of the pooling task, thereby improving the performance of electronic equipment.

As will be appreciated by those skilled in the art, one or more embodiments of the present application may be provided as a method, system or computer program product. Accordingly, one or more embodiments of the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, one or more embodiments of the present application may employ a computer program implemented on one or more computer-usable storage media (including, but not limited to, disk storage, OxCD_00-ROM, optical storage, etc.) having computer-usable program code embodied therein form of the product.

"And/or" described in this application means at least one of the two, for example, "A and/or B" includes three schemes: A, B, and "A and B".

Each embodiment in this application is described in a progressive manner, and the same and similar parts between the various embodiments may be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the data processing device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for related parts, please refer to the partial description of the method embodiment.

The foregoing describes specific embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the acts or steps recited in the claims can be performed in an order different from that in the embodiments and still achieve desirable results. Additionally, the processes depicted in the figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

Embodiments of the subject matter and functional operations described in this application can be implemented in digital electronic circuits, in tangible embodiment of computer software or firmware, in computer hardware including the structures disclosed in this application and their structural equivalents, or in a combination of one or more. Embodiments of the subject matter described in this application may be implemented as one or more computer programs, ie, one or more of computer program instructions encoded on a tangible, non-transitory program carrier for execution by or to control the operation of a data processing chip. multiple units. Alternatively or additionally, the program instructions may be encoded on an artificially generated propagated signal, such as a machine-generated electrical, optical or electromagnetic signal, which is generated to encode and transmit information to a suitable receiver chip for interpretation by the data. Processing chip execution. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of these.

The processes and logic flows described in this application can be performed by one or more programmable computers executing one or more computer programs to perform corresponding functions by operating on input data and generating output. The processes and logic flows described above can also be performed by, and chips can also be implemented as, special purpose logic circuits, such as FPGAs (field programmable gate arrays) or ASICs (application specific integrated circuits).

Computers suitable for the execution of a computer program include, for example, general and/or special purpose microprocessors, or any other type of central processing unit. Typically, the central processing unit will receive instructions and data from read only memory and/or random access memory. The basic components of a computer include a central processing unit for implementing or executing instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include, or be operatively coupled to, one or more mass storage devices for storing data, such as magnetic, magneto-optical or optical disks, to receive data therefrom or to It transmits data, or both. However, the computer does not have to have such a device. Additionally, the computer may be embedded in another device, such as a mobile phone, personal digital assistant (PDA), mobile audio or video player, game console, global positioning system (GPS) receiver, or a universal serial bus (USB) ) flash drives for portable storage devices, to name a few.

Computer-readable media suitable for storage of computer program instructions and data include all forms of non-volatile memory, media, and memory devices including, for example, semiconductor memory devices (eg, EPROM, EEPROM, and flash memory devices), magnetic disks (eg, internal hard disks or memory devices). removable disk), magneto-optical disk and 0xCD_00ROM and DVD-ROM disks. The processor and memory may be supplemented by or incorporated in special purpose logic circuitry.

While this application contains many specific implementation details, these should not be construed as limiting the scope of any disclosure or what may be claimed, but rather are used primarily to describe features of particular disclosed specific embodiments. Certain features that are described herein in the context of multiple embodiments can also be implemented in combination in a single embodiment. On the other hand, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Furthermore, although features may function as above in certain combinations and are even originally claimed as such, one or more features from a claimed combination may in some instances be removed from the combination and claimed A combination of can point to a subcombination or a variation of a subcombination.

Similarly, although operations are depicted in the figures in a particular order, this should not be construed as requiring the operations to be performed in the particular order shown or sequentially, or that all illustrated operations be performed, to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of the various system elements and components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems may generally be integrated together in a single software product , or packaged into multiple software products.

Thus, specific embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results. Furthermore, the processes depicted in the figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some implementations, multitasking and parallel processing may be advantageous.

The above are only some embodiments of the present application, and are not intended to limit one or more embodiments of the present application. Any modifications, equivalent replacements, and improvements made within the spirit and principles of one or more embodiments of the present application etc., shall be included within the protection scope of one or more embodiments of the present application.

Claims

A pooling method including:

Get the target feature map;

Splitting the target feature map to obtain several sub-feature maps; wherein, at least part of the pixel values in the same pooling window in the target feature map are in different sub-feature maps, and each pooling window is in the same sub-feature map The pixel value of the position is in the same sub-feature map;

Pixels belonging to different pooling windows in each sub-feature map are processed in parallel to obtain a pooling result corresponding to the target feature map.
The method according to claim 1, wherein the parallel processing of pixels belonging to different pooling windows in each sub-feature map to obtain a pooling result corresponding to the target feature map, comprising:

Loading the pixel values respectively included in the sub-feature maps into the shift register array;

According to the pooling instruction, the pixel values in the same position in each of the sub-feature maps are pooled in parallel to obtain a pooling result corresponding to the target feature map.
The method according to claim 1, wherein the parallel processing of pixels belonging to different pooling windows in each sub-feature map to obtain a pooling result corresponding to the target feature map, comprising:

Determine the shift operation mode of the shift register array corresponding to each sub-feature map according to the position of the pixel value in the same pooling window in each sub-feature map;

Loading the several sub-feature maps into the shift register array respectively;

For each of the sub-feature maps, a shift operation is performed on the pixel values stored in the shift registers in the shift register array according to the shift operation mode of the shift register array determined for the sub-feature map. Instruct parallel pooling processing to obtain partial pooling results corresponding to different pooling windows in the sub-feature map;

According to the partial pooling results of each sub-feature map corresponding to different pooling windows, the pooling result corresponding to the target feature map is determined.
The method according to any one of claims 1-3, wherein the target feature map is split to obtain several sub-feature maps, including:

Determining the pixel values at odd-numbered rows and odd-numbered column positions in the target feature map as the first sub-feature map;

Determining the pixel values at odd-numbered rows and even-numbered column positions in the target feature map as the second sub-feature map;

Determining the pixel values in the even-numbered rows and odd-numbered column positions in the target feature map as the third sub-feature map;

The pixel values in the even-numbered rows and even-numbered columns in the target feature map are determined as the fourth sub-feature map.
The method according to claim 4, wherein the pixel values respectively included in the sub-feature maps are loaded into the shift register array, and according to a pooling instruction, the sub-feature maps in the same The pixel values of the positions are pooled in parallel to obtain the pooling results corresponding to the target feature map, including:

moving each pixel value included in the first sub-feature map to at least part of the shift registers included in the shift register array;

Move each pixel value included in the second sub-feature map to the partial shift register, so that the calculation kernel corresponding to each shift register in the partial shift register, according to the pooling instruction, The received two pixel values are pooled to obtain the first pooling result;

Move each pixel value included in the third sub-feature map to the partial shift register, so that the calculation kernel corresponding to each shift register in the partial shift register, according to the pooling instruction, The first pooling processing result and the received pixel value are subjected to pooling processing to obtain a second pooling processing result;

Move each pixel value included in the fourth sub-feature map to the partial shift register, so that the calculation kernel corresponding to each shift register in the partial shift register, according to the pooling instruction, The second pooling processing result and the received pixel value are subjected to pooling processing to obtain a third pooling processing result;

A third pooling processing result obtained by performing pooling processing on the computing kernels corresponding to each of the shift registers in the partial shift registers is output, and a pooling result corresponding to the target feature map is obtained.
The method according to claim 5, wherein the pooling process comprises a maximum pooling process; the pooling instruction comprises comparing the maximum value between the two;

The step of moving each pixel value included in the first sub-feature map to at least part of the shift registers included in the shift register array includes:

moving each pixel value included in the first sub-feature map to the first register of at least part of the shift registers included in the shift register array;

moving each pixel value included in the second sub-feature map to the partial shift register, so that the calculation kernel corresponding to each shift register in the partial shift register is based on the pooling instruction , perform pooling processing on the two received pixel values, and obtain the first pooling processing result, including:

Each pixel value included in the second sub-feature map is moved to the second register of the partial shift register, so that the calculation kernel corresponding to each shift register in the partial shift register is based on the pool. A pooling instruction to obtain the maximum value among the values stored in the first register and the second register, and store the maximum value in the first register as the first pooling processing result.
The method according to claim 6, wherein the moving each pixel value included in the third sub-feature map to the partial shift register respectively, so as to be different from the respective pixel values in the partial shift register. The computing kernel corresponding to the shift register performs pooling processing on the first pooling processing result and the received pixel value according to the pooling instruction to obtain a second pooling processing result, including:

Each pixel value included in the third sub-feature map is moved to the second register of the partial shift register, so that the calculation kernel corresponding to each shift register in the partial shift register is based on the pool. a pooling instruction, obtain the maximum value among the values stored in the first register and the second register, and store the maximum value in the first register as the second pooling processing result;

moving each pixel value included in the fourth sub-feature map to the partial shift register, so that the calculation kernel corresponding to each shift register in the partial shift register is based on the pooling instruction , and perform pooling processing on the second pooling processing result and the received pixel values to obtain a third pooling processing result, including:

Each pixel value included in the fourth sub-feature map is moved to the second register of the partial shift register, so that the calculation kernel corresponding to each shift register in the partial shift register is based on the pool. A pooling instruction is used to obtain the maximum value among the values stored in the first register and the second register, and store the maximum value in the first register as the third pooling processing result.
The method according to claim 7, wherein the third pooling processing result obtained by outputting the calculation kernel corresponding to each shift register in the partial shift registers is obtained by pooling processing respectively, and obtaining the same result as the Pooling results corresponding to the target feature map, including:

The value stored in the first register of the partial shift register is output to obtain a pooling result corresponding to the target feature map.
The method according to claim 4, wherein the parallel processing of pixels belonging to different pooling windows in each sub-feature map to obtain a pooling result corresponding to the target feature map, comprising:

moving each pixel value included in the first sub-feature map to at least part of the shift registers included in the shift register array;

According to the pooling instruction, a pooling operation is performed on the pixel values in any four adjacent shift registers included in the shift register array to obtain a first partial pooling result, and the first partial pooling result is obtained. The pooling processing result is stored in the target shift register in the preset position among the four adjacent shift registers;

moving each pixel value included in the second sub-feature map to the partial shift register;

According to the pooling instruction, a pooling operation is performed on the pixel values in any two vertically adjacent shift registers included in the shift register array to obtain a second partial pooling result, and the second partial pooling result is obtained. Partial pooling processing results are stored in the target shift register;

moving each pixel value included in the third sub-feature map to the partial shift register;

According to the pooling instruction, a pooling operation is performed on the pixel values in any two left and right adjacent shift registers included in the shift register array to obtain a third partial pooling result, and the third partial pooling result is obtained. Partial pooling processing results are stored in the target shift register;

moving each pixel value included in the fourth sub-feature map to the partial shift register respectively, and moving the pixel value in each shift register in the partial shift register to the target shift register;

According to the first partial pooling processing result, the second partial pooling processing result, the third partial pooling processing result and the fourth sub-feature map in each target shift register included in the shift register array, the corresponding result is obtained. The pooling result corresponding to the target feature map.
The method according to claim 9, wherein the pooling process includes maximum pooling process; the pooling instruction includes comparing the maximum value between the two; the preset position includes any four up, down, left and right the lower left corner position in the adjacent shift registers; the target shift register includes the shift register at the lower left corner position in the four adjacent shift registers;

Described moving each pixel value included in the first sub-feature map to at least part of the shift registers included in the shift register array, including:

moving each pixel value included in the first sub-feature map to the first register of at least part of the shift registers included in the shift register array;

The pooling operation is performed on the pixel values in any four adjacent shift registers included in the shift register array according to the pooling instruction to obtain a first partial pooling result, and the The first part of the pooling processing result is stored in the target shift register at the preset position among the four adjacent shift registers, including:

moving the value in the first register of each first shift register in the partial shift register to the second register of the second shift register on the right side of the first shift register;

storing the larger value in the first register and the second register in each second shift register into the first register in each second shift register;

moving the value in the first register of the second shift registers to the second register of the third shift register below the second shift register;

storing the larger value in the first register and the second register in each third shift register into the first register in each third shift register;

moving the value in the first register of the third shift registers to the second register of the target shift register on the left side of the third shift register;

The larger value in the first register and the second register in each target shift register is used as the first partial pooling processing result, and is stored in the first register of each target shift register.
The method according to claim 10, wherein the moving each pixel value included in the second sub-feature map to the partial shift register respectively comprises:

moving each pixel value included in the second sub-feature map to the second register of the partial shift register;

According to the pooling instruction, a pooling operation is performed on the pixel values in any two upper and lower adjacent shift registers included in the shift register array to obtain a second partial pooling result, and the The second part of the pooling processing result is stored in the target shift register, including:

moving the value in the second register of each first shift register in the partial shift register to the third register of the target shift register below the first shift register;

The larger value in the second register and the third register in each target shift register is used as the second partial pooling processing result, and is stored in the second register of each target shift register.
The method according to claim 11, wherein the moving each pixel value included in the third sub-feature map to the partial shift register respectively comprises:

moving each pixel value included in the third sub-feature map to the third register of the partial shift register;

The pooling operation is performed on the pixel values in any two left and right adjacent shift registers included in the shift register array according to the pooling instruction to obtain a third partial pooling result, and the The third part of the pooling processing result is stored in the target shift register, including:

moving the value in the third register of each first shift register in the partial shift register to the fourth register of the second shift register on the right side of the first shift register;

Taking the larger value of the third register and the fourth register in each second shift register as the third partial pooling processing result, and storing it in the third register of each second shift register;

moving the third part of the pooling processing result in the third register of the second shift register to the third register of the first shift register on the left side of the second shift register;

The third part of the pooling processing result in the third register of the first shift register is moved to the third register of the target shift register below the first shift register.
The method according to claim 12, wherein the moving each pixel value included in the fourth sub-feature map to the partial shift register respectively comprises:

moving each pixel value included in the fourth sub-feature map to the fourth register of the partial shift register;

The moving the pixel values in each shift register in the partial shift registers to the target shift register includes:

The value in the fourth register of each first shift register in the partial shift registers is moved to the fourth register of the target shift register below the first shift register.
The method according to claim 13, wherein, according to the first partial pooling processing result, the second partial pooling processing result and the third partial pooling processing result in each target shift register included in the shift register array The pooling result and the pixel value corresponding to the fourth sub-feature map are obtained, and the pooling result corresponding to the target feature map is obtained, including:

storing the larger value in the first register and the second register in each target shift register into the first register in each target shift register;

storing the larger value in the first register and the third register in each target shift register into the first register in each target shift register;

storing the larger value in the first register and the fourth register in each target shift register into the first register in each target shift register;

The value stored in the first register of each target shift register is output, and the pooling result corresponding to the target feature map is obtained.
The method according to any one of claims 9-14, wherein a plurality of temporary registers are connected to the periphery of the shift register array; and the temporary registers are used to store and overflow the shift register when performing a value moving operation. Array of pixel values.
The method according to any one of claims 1-15, wherein the number of pixels included in at least part of the sub-feature maps in each of the sub-feature maps is consistent with the number of shift registers included in the shift register array.
A pooling method including:

Get the original feature map;

dividing the original feature map into several target feature maps;

According to the pooling method according to any one of claims 1-16, each target feature map is pooled to obtain a pooling result corresponding to each target feature map;

The pooling result corresponding to each target feature map is output, and the pooling result corresponding to the original feature map is obtained.
A chip including a controller;

the controller, for acquiring the target feature map;

Splitting the target feature map to obtain several sub-feature maps; wherein, at least part of the pixel values in the same pooling window in the target feature map are in different sub-feature maps, and each pooling window is in the same sub-feature map The pixel value of the position is in the same sub-feature map;

Pixels belonging to different pooling windows in each sub-feature map are processed in parallel to obtain a pooling result corresponding to the target feature map.
The chip according to claim 18, wherein the controller is used for:

Loading the pixel values respectively included in the sub-feature maps into the shift register array;

According to the pooling instruction, the pixel values in the same position in each of the sub-feature maps are pooled in parallel to obtain a pooling result corresponding to the target feature map.
The chip according to claim 18, wherein the controller is used for:

Determine the shift operation mode of the shift register array corresponding to each sub-feature map according to the position of the pixel value in the same pooling window in each sub-feature map;

The several sub-feature maps are respectively loaded into the shift register array, and for each sub-feature map, the shift registers in the shift register array are shifted according to the shift operation mode of the shift register array determined for the sub-feature map. The pixel value stored in the bit register is subjected to a shift operation, and the partial pooling results corresponding to different pooling windows in the sub-feature map are obtained by parallel pooling processing according to the pooling instruction;

According to the partial pooling results of each sub-feature map corresponding to different pooling windows, the pooling result corresponding to the target feature map is determined.
The chip according to any one of claims 18-20, wherein the controller is used for:

Determining the pixel values at odd-numbered rows and odd-numbered column positions in the target feature map as the first sub-feature map;

Determining the pixel values at odd-numbered rows and even-numbered column positions in the target feature map as the second sub-feature map;

Determining the pixel values in the even-numbered rows and odd-numbered column positions in the target feature map as the third sub-feature map;

The pixel values in the even-numbered rows and even-numbered columns in the target feature map are determined as the fourth sub-feature map.
The chip according to claim 21, wherein the controller is used for:

moving each pixel value included in the first sub-feature map to at least part of the shift registers included in the shift register array;

Move each pixel value included in the second sub-feature map to the partial shift register, so that the calculation kernel corresponding to each shift register in the partial shift register, according to the pooling instruction, The received two pixel values are pooled to obtain the first pooling result;

Move each pixel value included in the third sub-feature map to the partial shift register, so that the calculation kernel corresponding to each shift register in the partial shift register, according to the pooling instruction, The first pooling processing result and the received pixel value are subjected to pooling processing to obtain a second pooling processing result;

Move each pixel value included in the fourth sub-feature map to the partial shift register, so that the calculation kernel corresponding to each shift register in the partial shift register, according to the pooling instruction, The second pooling processing result and the received pixel value are subjected to pooling processing to obtain a third pooling processing result;

A third pooling processing result obtained by performing pooling processing on the computing kernels corresponding to each of the shift registers in the partial shift registers is output, and a pooling result corresponding to the target feature map is obtained.
The chip according to claim 22, wherein the pooling process includes a maximum pooling process; the pooling instruction includes comparing the maximum value between the two; the controller is configured to:

moving each pixel value included in the first sub-feature map to a first register of at least a part of the shift registers included in the shift register array; and,

Each pixel value included in the second sub-feature map is moved to the second register of the partial shift register, so that the calculation kernel corresponding to each shift register in the partial shift register is based on the pool. A pooling instruction to obtain the maximum value among the values stored in the first register and the second register, and store the maximum value in the first register as the first pooling processing result.
The chip according to claim 23, wherein the controller is used for:

Each pixel value included in the third sub-feature map is moved to the second register of the partial shift register, so that the calculation kernel corresponding to each shift register in the partial shift register is based on the pool. a pooling instruction, obtain the maximum value among the values stored in the first register and the second register, and store the maximum value in the first register as the second pooling processing result; and,

Each pixel value included in the fourth sub-feature map is moved to the second register of the partial shift register, so that the calculation kernel corresponding to each shift register in the partial shift register is based on the pool. A pooling instruction is used to obtain the maximum value among the values stored in the first register and the second register, and store the maximum value in the first register as the third pooling processing result.
The chip of claim 24, wherein the controller is used to:

The value stored in the first register of the partial shift register is output to obtain a pooling result corresponding to the target feature map.
A chip including a controller;

the controller, for obtaining the original feature map;

dividing the original feature map into several target feature maps;

According to the pooling method according to any one of claims 1 to 16, each target feature map is pooled to obtain a pooling result corresponding to each target feature map;

The pooling result corresponding to each target feature map is output, and the pooling result corresponding to the original feature map is obtained.
An electronic device comprising the chip of any one of claims 18-25 or claim 26.
A computer-readable storage medium having a computer program stored thereon, the computer program implementing the method of any one of claims 1 to 17 when executed by a controller.