WO2022160410A1

WO2022160410A1 - Display panel and manufacturing method therefor

Info

Publication number: WO2022160410A1
Application number: PCT/CN2021/079205
Authority: WO
Inventors: 卢马才
Original assignee: 深圳市华星光电半导体显示技术有限公司
Priority date: 2021-01-28
Filing date: 2021-03-05
Publication date: 2022-08-04
Also published as: CN113658958B; CN113658958A

Abstract

The present invention provides a display panel and a manufacturing method therefor. The display panel comprises a substrate, a first metal layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second metal layer, a passivation layer, and a pixel electrode. According to the present invention, a second source-drain electrode layer and a first source-drain electrode layer share one metal film layer, and a conventional gate top ILD layer is removed, so that the use number of film layers and masks can be reduced.

Description

Display panel and method of making the same

technical field

The present invention relates to the field of display technology, and in particular, to a display panel and a manufacturing method thereof.

Background technique

As shown in Figure 1, OLED (Organic Light-Emitting Diode, organic electroluminescence display)/Micro LED is used as a current driving device, which requires large current passing capacity, good device stability, in-plane Vth uniformity and low leakage current and other characteristics. Top gate self-aligned oxide semiconductor thin film transistor (Top Gate IGZO TFT) has the characteristics of high mobility, small parasitic capacitance and low leakage current, and is more suitable as a current-driven display circuit. For bottom emission display substrates, the bottom of the driving thin film transistor is preferably provided with a light blocking layer. The light blocking layer can block the influence of ambient light on the characteristics of the thin film transistor. After the metal light blocking layer is connected to the source, the driving thin film transistor is affected. The output characteristic curve has a stabilizing effect.

technical problem

As shown in Figure 1 and Figure 2, in the prior art, a TG IGZO TFT with a light shielding layer requires at least 8 masks, and the process sequence is the light shielding layer (Line Shied Layer, LS), buffer layer (Buffer), semiconductor Layer (Indium Gallium Zinc Oxide, IGZO), gate insulating layer (Gate Insulator, GI) and gate (Gate Electrode, GE), insulating layer (Interlayer) Dielectric, ILD), source-drain metal electrodes (SE, DE), passivation layer (Passivation layer, PV1) and the pixel electrode (Pixel electrode, PE) This process requires 8 masks, the process is more complicated and the cost is higher. At the same time, with the development of displays, more and more self-luminous displays with top light emission have become the mainstream, and there are also new requirements for the shading of TFTs.

technical solutions

The present invention provides a display panel. By sharing a metal film layer with the first source-drain electrode layer and the second source-drain electrode layer, and removing the traditional gate top ILD layer, the film structure can be optimized, and the film and mask can be reduced. The number of diaphragms used.

The present invention provides a display panel, comprising: a substrate; a first metal layer disposed on the substrate, the first metal layer comprising: a first source-drain electrode layer and a second source-drain electrode layer, the first The source-drain electrode layer and the second source-drain electrode layer have a gap; the first insulating layer is arranged on the first metal layer and the substrate; the semiconductor layer is arranged on the first insulating layer and the On the first metal layer, the semiconductor layer includes a first semiconductor layer and a second semiconductor layer, the first semiconductor layer is connected to the first source-drain electrode layer, and the second semiconductor layer is connected to the second source-drain electrode a polar layer; a second insulating layer, arranged on the first metal layer and the semiconductor layer; a second metal layer, arranged on the second insulating layer, the second metal layer including the first gate layer and a second gate layer; a passivation layer, disposed on the second metal layer, the semiconductor layer and the substrate; and a pixel electrode, disposed on the passivation layer, and the pixel electrode is connected to the a first source-drain electrode layer.

Further, the first source-drain electrode layer and the second source-drain electrode layer are obtained by patterning the same metal layer.

Further, the first semiconductor layer and the second semiconductor layer are obtained by patterning the same active layer.

Further, the first gate layer and the second gate layer are obtained by patterning the same metal layer.

Further, the first source-drain electrode layer includes: a first source electrode and a first drain electrode, a first gap is formed between the first source electrode and the first drain electrode; the second source-drain electrode The layer includes a second source electrode and a second drain stage; there is a second gap between the second source electrode and the second drain stage, and the second source electrode is arranged between the second drain stage and the second drain stage There is a third gap between the first sources, the second source and the first source; the first semiconductor layer includes a first channel region, a first source connection region and a first a drain connection region, one end of the first source connection region is connected to one end of the first channel region, one end of the first drain connection region is connected to the other end of the first channel region, the The other end of the first source connection region is connected to the first source, and the other end of the first drain connection region is connected to the first drain; the second semiconductor layer includes a second channel region, a second Two source connection regions and a second drain connection region, one end of the second source connection region is connected to one end of the second channel region, and one end of the second drain connection region is connected to the second channel The other end of the channel region, the other end of the second source connection region is connected to the second source, and the other end of the second drain connection region is connected to the second drain.

Further, the first insulating layer includes: a first sub-insulating layer, extending on a part of the first source electrode and covering the first gap and part of the first drain; a second sub-insulating layer, is disposed on the substrate corresponding to the second gap, one end of the second sub-insulating layer and the second source electrode have a first interval, and the other end of the second sub-insulating layer and the second drain electrode The electrode has a second space; and a third sub-insulating layer is disposed in the third space and covers part of the first source-drain electrode layer and part of the second source electrode; the first channel region is disposed in the On the first sub-insulating layer, the first source connection region is extended and connected to the first source through the left side of the first sub-insulating layer, and the first drain connection region passes through the The right side of the first sub-insulating layer extends to the first drain; the second channel region is provided on the second sub-insulating layer, and the second source connection region passes through the second sub-insulating layer The left side of the insulating layer and the first spacer extend to the second source electrode; the second drain level connection extends to the second source through the right side of the second sub-insulating layer and the second spacer on the second drain.

Further, the second insulating layer includes: a first gate insulating layer disposed on the first semiconductor layer; a second gate insulating layer disposed on the second semiconductor layer; and a third gate an insulating layer, disposed on the first source electrode; the second metal layer further includes: an electrode layer; the first gate electrode layer is disposed on the first gate insulating layer; the second gate electrode layer is arranged on the second gate insulating layer; and the electrode layer is arranged on the third gate insulating layer, the electrode layer, the third gate insulating layer and the first source electrode A storage capacitor is formed.

Further, the display panel further comprises: a first metal line; a second metal line, the first metal line and the second metal line are respectively disposed on the passivation layer, the first metal line , the second metal line is arranged in the same layer as the pixel electrode; and the VDD power supply line is arranged in the first metal layer; wherein, one end of the first metal line penetrates through the passivation layer to connect the the first gate layer, the other end of the first metal line is connected to the second source and drain layers; one end of the second metal line is connected to the first semiconductor layer through the passivation layer, and the The other end of the second metal line is connected to the VDD power supply line.

Another object of the present invention is to provide a method for fabricating a display panel, including: providing a substrate; forming a first metal layer on the substrate, the first metal layer including: a first source-drain electrode layer and a second source a drain electrode layer, a gap is formed between the first source-drain electrode layer and the second source-drain electrode layer; a first insulating layer is formed on the first metal layer and the substrate; a semiconductor layer is formed on the On the first insulating layer and the first metal layer, the semiconductor layer includes a first semiconductor layer and a second semiconductor layer, the first semiconductor layer is connected to the first source-drain electrode layer, the second The semiconductor layer is connected to the second source-drain electrode layer; a second insulating layer is formed on the first metal layer and the semiconductor layer; a second metal layer is formed on the second insulating layer, and the first metal layer is formed on the second insulating layer. The two metal layers include a first gate layer and a second gate layer, the first gate layer is connected to the second gate layer; a passivation layer is formed on the second metal layer, the semiconductor layer and the on the substrate; and forming a pixel electrode on the passivation layer, and the pixel electrode is connected to the first source-drain electrode layer.

Further, in the step of forming a first metal layer on the substrate, it specifically includes the following steps: depositing a first metal material on the substrate, and patterning the first source through the same mask a drain electrode layer and the second source-drain electrode layer; the step of forming a semiconductor layer on the first insulating layer and the first metal layer specifically includes the following steps: depositing an active layer material on the first insulating layer and the first metal layer; the first semiconductor layer and the second semiconductor layer are obtained by patterning the same mask.

beneficial effect

The present invention provides a display panel and a manufacturing method thereof. By sharing a metal film layer with a first source-drain electrode layer and a second source-drain electrode layer, using the first source electrode as a light-shielding layer, and removing the traditional gate top The ILD layer can reduce the number of layers and masks used. The structure is beneficial to reduce the number of masks, reduce the size of thin film transistors, and stabilize device characteristics. The preparation method of the present invention only needs 6 photomask mask plate processes, which greatly reduces the preparation cost.

Description of drawings

The technical solutions and other beneficial effects of the present application will be apparent through the detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings.

1 is a cross-sectional view of a display panel in the prior art;

2 is a first cross-sectional view of a display panel provided by the present invention;

3 is a second cross-sectional view of the display panel provided by the present invention;

4 is a plan view of a display panel provided by the present invention;

5 is an equivalent circuit diagram of a display panel provided by the present invention;

FIG. 6 is a schematic diagram of step S1 of the manufacturing method of the display panel provided by the present invention;

FIG. 7 is a schematic diagram of step S2 of the manufacturing method of the display panel provided by the present invention;

FIG. 8 is a schematic diagram of step S3 of the manufacturing method of the display panel provided by the present invention;

FIG. 9 is a schematic diagram of step S4 of the manufacturing method of the display panel provided by the present invention;

10 is a schematic diagram of step S5 of the manufacturing method of the display panel provided by the present invention;

11 is a schematic diagram of step S6 of the method for manufacturing a display panel provided by the present invention;

12 is a schematic diagram of step S7 of the method for manufacturing a display panel provided by the present invention;

FIG. 13 is a schematic diagram of step S8 of the manufacturing method of the display panel provided by the present invention.

Embodiments of the present invention

Specific structural and functional details disclosed herein are merely representative and for purposes of describing example embodiments of the present application. The application may, however, be embodied in many alternative forms and should not be construed as limited only to the embodiments set forth herein.

In the description of this application, it should be understood that the terms "center", "lateral", "top", "bottom", "left", "right", "vertical", "horizontal", "top", The orientation or positional relationship indicated by "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying the indicated device. Or elements must have a particular orientation, be constructed and operate in a particular orientation, and therefore should not be construed as a limitation of the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature defined as "first" or "second" may expressly or implicitly include one or more of that feature. In the description of this application, unless stated otherwise, "plurality" means two or more. Additionally, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion.

As shown in FIG. 2, the present invention provides a display panel 100 including: a substrate 101, a first metal layer 110, a first insulating layer 104, a semiconductor layer 105, a second insulating layer 106, a second metal layer 107, a passivation layer layer 108 and pixel electrode 109 .

As shown in FIG. 2 and FIG. 7 , the first metal layer 110 is provided on the substrate 101 . The first metal layer 110 includes: a first source-drain electrode layer 102 and a second source-drain electrode layer 103 .

The first source-drain electrode layer 102 is spaced apart from the second source-drain electrode layer 103 . The first source-drain electrode layer 102 includes a first source electrode 1022 and a first drain electrode 1021 , and a first gap 201 is formed between the first source electrode 1022 and the first drain electrode 1021 . The second source-drain electrode layer 103 includes a second source electrode 1031 and a second drain stage 1032; there is a second gap 202 between the second source electrode 1031 and the second drain stage 1032, and the second The source electrode 1031 is disposed between the second drain stage 1032 and the first source-drain electrode layer 1021 , and there is a third gap 203 between the second source electrode 1031 and the first source-drain electrode layer 1021 .

In this embodiment, the first source electrode 1022 is used as a light shielding layer, and the first source-drain electrode layer 102 and the second source-drain electrode layer 103 are disposed in the same layer. The second source-drain electrode layer 103 and the first source-drain electrode layer 102 are formed by a mask. The materials used for the first source-drain electrode layer 102 and the second source-drain electrode layer 103 are the same, and the material includes Mo (molybdenum), CuNb (copper niobium compound) or TiAlTi (aluminum titanium compound). Further, the material can also be a laminated structure, and the laminated structure includes: Mo/Al (aluminum), Mo/Cu (copper), MoTi (molybdenum-titanium compound)/Cu, MoTi/Cu/MoTi, Ti/ Cu/Ti, Mo/Cu/IZO (indium zinc oxide), IZO/Cu/IZO or, Mo/Cu/ITO (indium tin oxide), Ni (nickel)/Cu/Ni, MoTiNi (molybdenum titanium nickel compound) /Cu/MoTiNi, MoNi (molybdenum-nickel compound)/Cu/MoNi, NiCr (chromium-nickel compound)/Cu/NiCr, TiNi (titanium-nickel compound)/Cu/TiNi or (titanium-chromium compound) TiCr/Cu/TiCr. The A/B structure of the present invention is a laminated structure, A represents the metal material used in one layer of the structure, B represents the metal material used in the other layer structure, and the upper and lower relationship between A and B is not limited.

As shown in FIG. 2 and FIG. 8 , the first insulating layer 104 is disposed on the first metal layer 110 and the substrate 101 . The first insulating layer 104 includes: a first sub-insulating layer 1041 , a second sub-insulating layer 1042 and a third sub-insulating layer 1043 .

The first sub-insulating layer 1041 extends on a part of the first source electrode 1022 and covers the first gap 201 and a part of the first drain 1021 . The second sub-insulating layer 1042 is disposed on the substrate 101 corresponding to the second gap 302. One end of the second sub-insulating layer 302 and the first source electrode 1031 have a first gap 304. The second sub-insulating layer 302 has a first gap 304. The other end of the insulating layer 1042 has a second gap 305 with the first drain electrode 1032 ; the third sub-insulating layer 1043 is disposed in the third gap 303 and covers part of the first source-drain electrode layer 1021 and part of the source electrode 1031. The film material of the first insulating layer 104 includes SiOx, SiNx, SiNOx and the like.

2, the semiconductor layer 105 is disposed on the first insulating layer 104 and the first metal layer 110, the semiconductor layer 105 includes a first semiconductor layer 1051 and a second semiconductor layer 1052, so The first semiconductor layer 1051 is connected to the first source-drain electrode layer 102 , and the second semiconductor layer 1052 is connected to the second source-drain electrode layer 103 . The first semiconductor layer 1051 includes a first channel region 1051-1, a first source connection region 1051-2 and a first drain connection region 1051-3, and one end of the first source connection region 1051-2 One end of the first channel region 1051-1 is connected, one end of the first drain connection region 1051-3 is connected to the other end of the first channel region 1051-1, and the first source connection region The other end of 1051-2 is connected to the first source electrode 1022, and the other end of the first drain connection region 1051-3 is connected to the first drain electrode 1021; the second semiconductor layer 1052 includes a second channel region 1052-1, a second source connection region 1052-2 and a second drain connection region 1052-3, one end of the second source connection region 1052-2 is connected to the second channel region 1052-1 One end of the second drain connection region 1052-3 is connected to the other end of the second channel region 1052-1, and the other end of the second source connection region 1052-2 is connected to the second source The other end of the second drain connection region 1052-3 is connected to the second drain 1032.

The first channel region 1051-1 is disposed on the first sub-insulating layer 1041, and the first source connection region 1051-2 extends to the first sub-insulating layer 1041 through the left side of the first sub-insulating layer 1041. On top of a source electrode 1022, the first drain level connection region 1051-3 extends to the top of the first drain electrode 1021 through the right side of the first sub-insulating layer 1041; the second channel region 1052 -1 is disposed on the second sub-insulating layer 1042, and the second source connecting region 1052-2 extends to the source through the left side of the second sub-insulating layer 1042 and the first spacer 304 1031 ; the second drain connection region 1052 - 3 extends to the second drain 1032 through the right side of the second sub-insulating layer 1042 and the second spacer 305 .

The materials of the semiconductor layer 105 include oxide semiconductors or other types of semiconductors, and the materials of the oxide semiconductors include IGZO (Indium Gallium Zinc Oxide), IGTO (Indium Gallium Titanium Oxide), IGZTO (Indium Gallium Zinc Titanium Oxide) compound), IGO (Indium Gallium Oxide), IZO (Indium Zinc Oxide) or AIZO (Aluminum Zinc Oxide).

The second insulating layer 106 is disposed on the first metal layer 102 and the semiconductor layer 105 . The second insulating layer 106 includes: a first gate insulating layer 1061 , a second gate insulating layer 1062 and a third gate insulating layer 1063 .

The first gate insulating layer 1061 is disposed on the first semiconductor layer 1051 ; the second gate insulating layer 1062 is disposed on the second semiconductor layer 1052 . The third gate insulating layer 1063 is disposed on the first source electrode 1022 .

The film material of the second insulating layer 106 includes SiOx (silicon oxide) or SiNx (silicon nitride). The second insulating layer 106 may also be a laminated structure, and the material of the laminated structure includes: Al2O3/SiNx/SiOx or SiOx/SiNx/SiOx.

The second metal layer 107 is disposed on the second insulating layer 106 , and the second metal layer 107 includes a first gate layer 1071 , a second gate layer 1072 and an electrode layer 1073 .

The first gate layer 1071 is disposed on the first gate insulating layer 1061; the second gate layer 1072 is disposed on the second gate insulating layer 1032; the electrode layer 1073 is disposed on the On the third gate insulating layer 1063, the electrode layer 1073, the third gate insulating layer 1063 and the first source electrode 1022 form a storage capacitor. The first gate layer 1071, the first semiconductor layer 1051 and the first source and drain layers 1021 constitute a driving thin film transistor. The second gate layer 1072, the second semiconductor layer 1052 and the second source and drain layers 103 constitute a switching thin film transistor.

The material of the second metal layer 107 includes Mo (molybdenum), CuNb (copper niobium compound) or TiAlTi (aluminum titanium compound). The gate layer 107 may be a stacked structure including: Mo/Al (aluminum), Mo/Cu (copper), MoTi (molybdenum titanium compound)/Cu, MoTi/Cu/MoTi, Ti /Cu/Ti, Mo/Cu/IZO (indium zinc oxide), IZO/Cu/IZO or, Mo/Cu/ITO (indium tin oxide), Ni (nickel)/Cu/Ni, MoTiNi (molybdenum titanium nickel compound )/Cu/MoTiNi, MoNi (molybdenum-nickel compound)/Cu/MoNi, NiCr (chromium-nickel compound)/Cu/NiCr, TiNi (titanium-nickel compound)/Cu/TiNi or (titanium-chromium compound) TiCr/Cu/TiCr.

The passivation layer 108 is disposed on the second metal layer 107 , the semiconductor layer 105 and the substrate 101 . The passivation layer 108 has a first through hole 1081 , a second through hole 1082 , a third through hole 1083 , a fourth through hole 1084 and a fifth through hole 1085 .

The first through hole 1081 extends downward to the upper surface of the first source electrode 1022 . The second through hole 1082 extends downward to the upper surface of the first gate sub-layer 1071 . The third through hole 1083 extends downward to the upper surface of the source electrode 1031 of the second source-drain electrode layer 103 and the passivation layer 108 . The fourth through hole 1084 extends downward to the upper surface of the first semiconductor layer 1052 , and the fifth through hole 1085 extends downward to the upper surface of the VDD power trace 121 .

The film material of the passivation layer 108 includes SiOx (silicon oxide), SiNx (silicon nitride) or SiNOx (silicon oxynitride). The passivation layer 108 may also be a laminated structure, and the material of the laminated structure includes: SiOx/SiNx.

The pixel electrode 109 is disposed on the passivation layer 108 , the pixel electrode 109 is connected to the first source electrode 1022 , and is connected to the first semiconductor layer 1051 of the driving thin film transistor through the first source electrode 1022 . The pixel electrode 109 is connected to the first source electrode 1022 through the first through hole 1081 .

The material of the pixel electrode 109 includes: ITO, IZO, or a metal-based film layer. The pixel electrode 109 may also be a laminated structure, and the laminated structure includes: Mo/Al (aluminum), Mo/Cu (copper), MoTi (molybdenum-titanium compound)/Cu, MoTi/Cu/MoTi, Ti/ Cu/Ti, Mo/Cu/IZO (indium zinc oxide), IZO/Cu/IZO or, Mo/Cu/ITO (indium tin oxide), Ni (nickel)/Cu/Ni, MoTiNi (molybdenum titanium nickel compound) /Cu/MoTiNi, MoNi (molybdenum-nickel compound)/Cu/MoNi, NiCr (chromium-nickel compound)/Cu/NiCr, TiNi (titanium-nickel compound)/Cu/TiNi or (titanium-chromium compound) TiCr/Cu/TiCr.

Referring to FIG. 2 and FIG. 3 at the same time, in one embodiment, the display panel 100 further includes: a first metal line 111 , a second metal line 114 and the VDD power supply line 121 .

The first metal line 111 and the second metal line 114 are respectively disposed on the passivation layer 108 , and the first metal line 111 and the second metal line 114 are disposed in the same layer as the pixel electrode 109 . . The first metal line 111 , the second metal line 114 and the pixel electrode 109 are formed by a mask process, and the materials thereof are all indium tin oxide. The VDD power trace 121 and the first source electrode 1022 are disposed on the substrate 101 at the same layer.

One end of the first metal line 111 is connected to the first gate layer 1071 through the second through hole 1082 . The other end of the first metal line 111 is connected to the source electrode 1031 through the third through hole 1083 , thereby completing the connection between the driving thin film transistor and the switching thin film transistor. One end of the second metal wire 114 is connected to the first semiconductor layer 1052 through the fourth through hole 1084 . , the other end of the second metal line 114 is connected to the VDD power supply line 121 through the fifth through hole 1085 .

The present invention provides a display panel 100. The display panel 100 is applied to a metal oxide thin film transistor with a top-gate self-aligned structure, and only needs 6 mask mask processes, and the sequential processes are the first metal layer (the first source A drain electrode layer (the first source electrode can be used as a light shielding layer and a second source and drain electrode layer), a first insulating layer, a semiconductor layer (the first semiconductor layer and the second semiconductor layer), the second insulating layer and the gate layer ( a first gate insulating layer and a first gate, a second gate insulating layer and a second gate), a passivation layer and a pixel electrode layer.

In the present invention, the first source-drain electrode layer 102 and the second source-drain electrode layer 103 share one metal film layer, and the traditional gate top ILD layer is removed. Through this structural optimization, the number of film layers and masks used can be reduced . The structure is beneficial to reduce the number of masks, reduce the size of thin film transistors, and stabilize device characteristics.

There are three connection modes of the semiconductor layer 105, the first gate layer 1071, and the source and drain layers of the present invention. The metal line 111 forms a connection; the second type is that the first semiconductor layer 1051 of the driving thin film transistor is directly connected to the first source-drain electrode layer 1021, and the third type is that the first semiconductor layer 1051 of the driving thin film transistor and the VDD trace through the second Metal wires 114 are connected.

As shown in FIG. 4 , specifically, the present invention provides a plan view of an embodiment in order to better understand the plane positional relationship between the pixel electrode 109 , the first metal line 111 and the second metal line 114 . Wherein, the first cross-sectional view of FIG. 2 is the cross-section at the dotted line AA' in the structure of FIG. 4 , and the second cross-sectional view of FIG. 3 is the cross-section at the dotted line of BB' in the structure of FIG. 4 .

As shown in FIG. 5 , which is an equivalent circuit diagram of the present invention, the circuit includes a switching thin film transistor T1 , a driving thin film transistor T2 , a sensing thin film transistor T3 and a capacitor C.

The gate of the switching thin film transistor T1 is connected to the gate voltage signal Vgate, the source of the switching thin film transistor T1 is connected to the data voltage signal Vdata, and the drain of the switching thin film transistor T1 is connected to the first end of the capacitor.

The gate of the driving thin film transistor T3 is connected to the drain of the switching thin film transistor T1, the drain of the driving thin film transistor T3 is connected to the high voltage source Vdd, and the source of the driving thin film transistor T3 is respectively connected to the capacitor C The second end of the light emitting diode and the first end of a light emitting diode, the second end of the light emitting diode is grounded.

The source of the sensing thin film transistor T3 is connected to the capacitor C, and the drain of the sensing thin film transistor T3 is connected to a sensing signal Sensing.

The present invention further provides a manufacturing method of a display panel, which is used to manufacture and form the display panel 100 of the present invention. The manufacturing method of the display panel includes the following steps S1-S8.

S1) As shown in FIG. 6 , a substrate 101 is provided.

S2) As shown in FIG. 7 , a first metal layer 110 is formed on the substrate 101 . The first metal layer 102 includes: a first source-drain electrode layer 102 and a second source-drain electrode layer 103 . The step S2 specifically includes: S201) depositing a first metal material on the substrate 101; S202) patterning the first source-drain electrode layer 102 and the second source-drain electrode layer 103 through the same mask . The first source-drain electrode layer 102 is spaced apart from the second source-drain electrode layer 103 . The first source-drain electrode layer 102 includes a first source electrode 1022 and a first drain electrode 1021 , and a first gap 201 is formed between the first source electrode 1022 and the first drain electrode 1021 . The second source-drain electrode layer 103 includes a second source electrode 1031 and a second drain stage 1032; there is a second gap 202 between the second source electrode 1031 and the second drain stage 1032, and the second The source electrode 1031 is disposed between the second drain stage 1032 and the first source-drain electrode layer 102 , and there is a third gap 203 between the second source electrode 1031 and the first source-drain electrode layer 102 . The first metal material includes Mo (molybdenum), CuNb (copper niobium compound), or TiAlTi (compound aluminum titanium). The first metal material can also be a laminated structure, and the laminated structure includes: Mo/Al (aluminum), Mo/Cu (copper), MoTi (molybdenum titanium compound)/Cu, MoTi/Cu/MoTi, Ti/Cu /Ti, Mo/Cu/IZO (indium zinc oxide), IZO/Cu/IZO or, Mo/Cu/ITO (indium tin oxide), Ni (nickel)/Cu/Ni, MoTiNi (molybdenum titanium nickel compound)/ Cu/MoTiNi, MoNi (molybdenum-nickel compound)/Cu/MoNi, NiCr (chromium-nickel compound)/Cu/NiCr, TiNi (titanium-nickel compound)/Cu/TiNi or (titanium-chromium compound) TiCr/Cu/TiCr.

S3) As shown in FIG. 8, a first insulating layer 104 is formed on the first metal layer 110 and the substrate 101. The first insulating layer 104 includes: a first sub-insulating layer 1041, a second sub-insulating layer 104 layer 1042 and a third sub-insulating layer 1043 . Specifically, step S3 specifically includes: S301) depositing a film layer material on the first metal layer 110 and the substrate 101; S302) patterning the first sub-insulation layer 1041, the The second sub-insulating layer 1042 and the third sub-insulating layer 1043 are formed. The first sub-insulating layer 1041 extends on a part of the first source electrode 1022 and covers the first gap 201 and a part of the first drain. The second sub-insulating layer 1042 is disposed on the substrate corresponding to the second gap 302. One end of the second sub-insulating layer 302 and the second source electrode 1031 have a first gap 304, and the second sub-insulating layer 302 has a first gap 304. The other end of the layer 1042 and the second drain 1032 have a second space 305; the third sub-insulating layer 1043 is disposed in the third space 303 and covers part of the first drain 1021 and part of the The second source electrode 1031 . The film material of the first insulating layer 104 includes SiOx, SiNx, SiNOx and the like.

S4) As shown in FIG. 9 , a semiconductor layer 105 is formed on the first insulating layer 104 and the first metal layer 102 , and the semiconductor layer 105 includes a first semiconductor layer 1051 and a second semiconductor layer 1052 . Specifically, step S4 includes: S401) depositing an active layer material on the first insulating layer 104 and the first metal layer 102; S402) patterning through the same mask to form the first semiconductor layer 1051 and the second semiconductor layer 1052 . The first semiconductor layer 1051 is connected to the first source-drain electrode layer 102 , and the second semiconductor layer 1052 is connected to the second source-drain electrode layer 103 . The first semiconductor layer 1051 includes a first channel region 1051-1, a first source connection region 1051-2 and a first drain connection region 1051-3, and the semiconductor material includes an oxide semiconductor or other types of semiconductors , the oxide semiconductor materials include IGZO (Indium Gallium Zinc Oxide), IGTO (Indium Gallium Titanium Oxide), IGZTO (Indium Gallium Zinc Titanium Oxide), IGO (Indium Gallium Oxide), IZO (Indium Zinc Oxide) compound) or AIZO (aluminum zinc oxide).

S5) As shown in FIG. 10, a second insulating layer 106 is formed on the first metal layer 102 and the semiconductor layer 105. The second insulating layer 106 includes: a first gate insulating layer 1061, a second A gate insulating layer 1062 and a third gate insulating layer 1063; a second metal layer 107 is formed on the second insulating layer 106, and the second metal layer 107 includes a first gate layer 1071 and a second gate layer 1072 and electrode layer 1073. Specifically, step S5 specifically includes: S501) depositing an insulating material on the first metal layer 102 and the semiconductor layer 105; S502) depositing a second metal material on the insulating material; S503) passing the same light After the mask is patterned, the first gate layer 1071 , the second gate layer 1072 and the electrode layer 1073 are formed; S504 ) according to the metal pattern of the second metal layer 107 , the first gate layer 1071 is formed after self-alignment patterning. The first gate insulating layer 1061 , the second gate insulating layer 1062 and the third gate insulating layer 1063 . S505 ) and perform metallization doping treatment on the semiconductor layer 105 according to the metal pattern of the second metal layer 107 to obtain a first channel region 1051-1, a first source connection region 1051-2, A first drain connection region 1051-3, a second channel region 1052-1, a second source connection region 1052-2, and a second drain connection region 1052-3, the first source connection region 1051-2 one end is connected to one end of the first channel region 1051-1, one end of the first drain connection region 1051-3 is connected to the other end of the first channel region 1051-1, the first source The other end of the connection region 1051-2 is connected to the first source 1022, and the other end of the first drain connection region 1051-3 is connected to the first drain 1021; the second source connection region 1052- One end of 2 is connected to one end of the second channel region 1052-1, one end of the second drain connection region 1052-3 is connected to the other end of the second channel region 1052-1, and the second source The other end of the electrode connection region 1052-2 is connected to the second source electrode 1031, and the other end of the second drain connection region 1052-3 is connected to the second drain electrode 1032. The first channel region 1051-1 is disposed on the first sub-insulating layer 1041, and the first source connection region 1051-2 extends to the first sub-insulating layer 1041 through the left side of the first sub-insulating layer 1041. On top of a source electrode 1022, the first drain level connection region 1051-3 extends to the top of the first drain electrode 1021 through the right side of the first sub-insulating layer 1041; the second channel region 1052 -1 is disposed on the second sub-insulating layer 1042, and the second source connecting region 1052-2 extends to the source through the left side of the second sub-insulating layer 1042 and the first spacer 304 1031 ; the second drain level connection region 1052 - 3 extends to the second drain electrode 1032 through the right side of the second sub-insulating layer 1042 and the second spacer 305 . The first gate insulating layer 1061 is disposed on the first semiconductor layer 1051 ; the second gate insulating layer 1062 is disposed on the second semiconductor layer 1052 . The third gate insulating layer 1063 is disposed on the first source electrode 1022 . The insulating material of the second insulating layer 106 includes SiOx (silicon oxide) or SiNx (silicon nitride). The insulating material of the second insulating layer 106 may also be a laminated structure, and the material of the laminated structure includes: Al2O3/SiNx/SiOx or SiOx/SiNx/SiOx. The first gate layer 1071 is disposed on the first gate insulating layer 1061; the second gate layer 1072 is disposed on the second gate insulating layer 1032; the electrode layer 1073 is disposed on the On the third gate insulating layer 1063, the electrode layer 1073, the third gate insulating layer 1063 and the first source electrode 1022 form a storage capacitor. The first gate layer 1071, the first semiconductor layer 1051 and the first source and drain layers 1021 constitute a driving thin film transistor. The second gate layer 1072, the second semiconductor layer 1052 and the second source and drain layers 103 constitute a switching thin film transistor. The second metal material includes Mo (molybdenum), CuNb (copper niobium compound) or TiAlTi (compound aluminum titanium). The second metal material can be a laminated structure, and the laminated structure includes: Mo/Al (aluminum), Mo/Cu (copper), MoTi (molybdenum-titanium compound)/Cu, MoTi/Cu/MoTi, Ti /Cu/Ti, Mo/Cu/IZO (indium zinc oxide), IZO/Cu/IZO or, Mo/Cu/ITO (indium tin oxide), Ni (nickel)/Cu/Ni, MoTiNi (molybdenum titanium nickel compound )/Cu/MoTiNi, MoNi (molybdenum-nickel compound)/Cu/MoNi, NiCr (chromium-nickel compound)/Cu/NiCr, TiNi (titanium-nickel compound)/Cu/TiNi or (titanium-chromium compound) TiCr/Cu/TiCr.

S6) As shown in FIG. 11 , a passivation layer 108 is formed on the second metal layer 107 , the semiconductor layer 105 and the substrate 101 . Specifically, step S7 specifically includes the following steps S601 to S602. S601 ) depositing a film material to form the passivation layer 108 on the second metal layer 107 , the semiconductor layer 105 and the substrate 101 . The film material of the passivation layer 108 includes SiOx (silicon oxide), SiNx (silicon nitride) or SiNOx (silicon oxynitride). The passivation layer 108 may also be a laminated structure, and the material of the laminated structure includes: SiOx/SiNx. S602 , continuing to refer to FIG. 11 , opening a first through hole 1081 , a second through hole 1082 , and a third through hole 1083 on the passivation layer 108 . The first through hole 1081 extends downward to the upper surface of the first source electrode 1022 . The second through hole 1082 extends downward to the upper surface of the first gate sub-layer 1071 . The third through hole 1083 extends downward to the upper surface of the source-drain electrode layer 103 .

S7) Referring to FIG. 12 , a pixel electrode 109 is formed on the passivation layer 108 , and the pixel electrode 109 is connected to the first source electrode 1022 . Specifically, step S8 includes: S701) depositing an electrode material on the passivation layer 108; S702) patterning the pixel electrode 109 and the first metal line 111 through the same mask. The pixel electrode 109 is connected to the first source electrode 1022 through the first through hole 1081 . One end of the first metal line 111 is connected to the first gate sub-layer 1071 through the second through hole 1082 , and the other end of the first metal line 111 is connected to the first gate sub-layer 1071 through the third through hole 1083 . Two source-drain electrode layers 103 . One end of the second metal wire 114 is connected to the first semiconductor layer 1052 through the fourth through hole 1084 .

The electrode material includes: ITO, IZO, or metal-based film layers. The pixel electrode 109 may also be a laminated structure, and the laminated structure includes: Mo/Al (aluminum), Mo/Cu (copper), MoTi (molybdenum-titanium compound)/Cu, MoTi/Cu/MoTi, Ti/ Cu/Ti, Mo/Cu/IZO (indium zinc oxide), IZO/Cu/IZO or, Mo/Cu/ITO (indium tin oxide), Ni (nickel)/Cu/Ni, MoTiNi (molybdenum titanium nickel compound) /Cu/MoTiNi, MoNi (molybdenum-nickel compound)/Cu/MoNi, NiCr (chromium-nickel compound)/Cu/NiCr, TiNi (titanium-nickel compound)/Cu/TiNi or (titanium-chromium compound) TiCr/Cu/TiCr.

S8) Referring to FIG. 13 , deposit a protective layer 131 on the substrate 101 .

The present invention provides a method for fabricating a display panel. When the display panel is applied to a metal oxide thin film transistor with a top-gate self-aligned structure, only 7 photomask mask steps are required, and the sequential steps are the first metal layer (the first source The drain electrode layer (the first source electrode serves as a light shielding layer) and the second source and drain electrode layer), the first insulating layer, the semiconductor layer (the first semiconductor layer and the second semiconductor layer), the second insulating layer and the gate layer (the first semiconductor layer and the second semiconductor layer) a gate insulating layer and a first gate, a second gate insulating layer and a second gate), a passivation layer and a pixel electrode layer.

In the present invention, the first source electrode is used as a light-shielding layer, and the traditional ILD layer on the top of the gate electrode is removed. Through this structural optimization, the number of film layers and masks used can be reduced. The structure is beneficial to reduce the number of masks, reduce the size of thin film transistors, and stabilize device characteristics.

The present invention further provides a display device including the display panel 100 according to an embodiment of the present invention.

To sum up, although the present application has disclosed the above-mentioned preferred embodiments, the above-mentioned preferred embodiments are not intended to limit the present application. Those of ordinary skill in the art, without departing from the spirit and scope of this application, can Therefore, the scope of protection of the present application is subject to the scope defined by the claims.

Claims

A display panel, comprising:

substrate;

a first metal layer, disposed on the substrate, the first metal layer includes: a first source-drain electrode layer and a second source-drain electrode layer, the first source-drain electrode layer and the second source-drain electrode layer the layer has a gap;

a first insulating layer, disposed on the first metal layer and the substrate;

a semiconductor layer, disposed on the first insulating layer and the first metal layer, the semiconductor layer includes a first semiconductor layer and a second semiconductor layer, the first semiconductor layer is connected to the first source-drain electrode layer , the second semiconductor layer is connected to the second source-drain electrode layer;

a second insulating layer, disposed on the first metal layer and the semiconductor layer;

a second metal layer, disposed on the second insulating layer, the second metal layer includes a first gate layer and a second gate layer;

a passivation layer disposed on the second metal layer, the semiconductor layer and the substrate; and

The pixel electrode is arranged on the passivation layer, and the pixel electrode is connected to the first source-drain electrode layer.
The display panel of claim 1, wherein,

The first source-drain electrode layer and the second source-drain electrode layer are obtained by patterning the same metal layer.
The display panel of claim 1, wherein,

The first semiconductor layer and the second semiconductor layer are obtained by patterning the same active layer.
The display panel of claim 1, wherein,

The first gate layer and the second gate layer are obtained by patterning the same metal layer.
The display panel of claim 1, wherein,

The first source-drain electrode layer includes: a first source electrode and a first drain electrode, and a first gap is formed between the first source electrode and the first drain electrode;

The second source-drain electrode layer includes a second source electrode and a second drain stage; a second gap is formed between the second source electrode and the second drain stage, and the second source electrode is arranged on the There is a third gap between the second drain and the first source, and between the second source and the first source;

The first semiconductor layer includes a first channel region, a first source connection region and a first drain connection region, one end of the first source connection region is connected to one end of the first channel region, the One end of the first drain connection region is connected to the other end of the first channel region, the other end of the first source connection region is connected to the first source, and the other end of the first drain connection region connecting the first drain;

The second semiconductor layer includes a second channel region, a second source connection region, and a second drain connection region, one end of the second source connection region is connected to one end of the second channel region, the One end of the second drain connection region is connected to the other end of the second channel region, the other end of the second source connection region is connected to the second source, and the other end of the second drain connection region connecting the second drain.
The display panel of claim 5, wherein,

The first insulating layer includes: a first sub-insulating layer, which is provided on a part of the first source electrode and extends and covers the first gap and a part of the first drain;

A second sub-insulating layer is disposed on the substrate corresponding to the second gap, one end of the second sub-insulating layer and the second source electrode have a first interval, and the other end of the second sub-insulating layer having a second interval with the second drain electrode; and a third sub-insulating layer disposed in the third gap and covering part of the first source-drain electrode layer and part of the second source electrode;

The first channel region is provided on the first sub-insulating layer, the first source connection region is extended and connected to the first source through the left side of the first sub-insulating layer, and the a first drain connection region extends to the first drain through the right side of the first sub-insulating layer;

The second channel region is disposed on the second sub-insulating layer, and the second source connection region extends to the second source through the left side of the second sub-insulating layer and the first spacer on the electrode; the second drain level connection extends to the second drain through the right side of the second sub-insulating layer and the second spacer.
The display panel of claim 6, wherein,

The second insulating layer includes:

a first gate insulating layer, disposed on the first semiconductor layer;

a second gate insulating layer disposed on the second semiconductor layer; and

a third gate insulating layer, disposed on the first source;

The second metal layer further includes: an electrode layer;

the first gate layer is disposed on the first gate insulating layer;

the second gate layer is disposed on the second gate insulating layer; and

The electrode layer is disposed on the third gate insulating layer, and the electrode layer, the third gate insulating layer and the first source form a storage capacitor.
The display panel of claim 1, further comprising:

the first metal wire;

second metal lines, the first metal lines and the second metal lines are respectively disposed on the passivation layer, the first metal lines, the second metal lines and the pixel electrodes are disposed in the same layer; as well as

VDD power supply wiring, arranged in the first metal layer;

Wherein, one end of the first metal wire is connected to the first gate electrode layer through the passivation layer, and the other end of the first metal wire is connected to the second source and drain layer;

One end of the second metal line is connected to the first semiconductor layer through the passivation layer, and the other end of the second metal line is connected to the VDD power supply line.
A preparation method of a display panel, comprising:

providing a substrate;

A first metal layer is formed on the substrate, the first metal layer includes: a first source-drain electrode layer and a second source-drain electrode layer, the first source-drain electrode layer and the second source-drain electrode layer the layer is provided with a gap;

forming a first insulating layer on the first metal layer and the substrate;

A semiconductor layer is formed on the first insulating layer and the first metal layer, the semiconductor layer includes a first semiconductor layer and a second semiconductor layer, and the first semiconductor layer is connected to the first source and drain electrodes layer, the second semiconductor layer is connected to the second source-drain electrode layer;

forming a second insulating layer on the first metal layer and the semiconductor layer; forming a second metal layer on the second insulating layer, the second metal layer including a first gate layer and a second a gate layer, the first gate layer is connected to the second gate layer;

forming a passivation layer on the second metal layer, the semiconductor layer and the substrate; and

A pixel electrode is formed on the passivation layer, and the pixel electrode is connected to the first source-drain electrode layer.
The preparation method of the display panel according to claim 9, wherein,

The step of forming a first metal layer on the substrate specifically includes the following steps:

depositing a first metal material on the substrate, and

The first source-drain electrode layer and the second source-drain electrode layer are obtained by patterning the same mask;

The step of forming a semiconductor layer on the first insulating layer and the first metal layer specifically includes the following steps:

depositing an active layer material on the first insulating layer and the first metal layer;

The first semiconductor layer and the second semiconductor layer are obtained by patterning the same mask.