WO2022160217A1 - 一种中断上报装置、方法及虚拟化系统 - Google Patents

一种中断上报装置、方法及虚拟化系统 Download PDF

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Publication number
WO2022160217A1
WO2022160217A1 PCT/CN2021/074257 CN2021074257W WO2022160217A1 WO 2022160217 A1 WO2022160217 A1 WO 2022160217A1 CN 2021074257 W CN2021074257 W CN 2021074257W WO 2022160217 A1 WO2022160217 A1 WO 2022160217A1
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interrupt
vpe
ppi
processor
message signal
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PCT/CN2021/074257
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English (en)
French (fr)
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贾艳磊
王静宜
程剑
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华为技术有限公司
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Priority to CN202180091958.4A priority Critical patent/CN116762061A/zh
Priority to PCT/CN2021/074257 priority patent/WO2022160217A1/zh
Publication of WO2022160217A1 publication Critical patent/WO2022160217A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines

Definitions

  • the present application relates to the field of virtualization technologies, and in particular, to an interrupt reporting device, method, and virtualization system.
  • Platform virtualization technology is a technology that hides the actual physical characteristics of a specific computing platform and provides users with an abstract, unified and simulated computing environment by using a virtual machine monitor (VMM). It is called a virtual machine (VM).
  • the operating system running in the VM may be called a guest operating system (guest operation system, guest OS).
  • guest operation system guest OS
  • the hardware layer of the platform virtualization environment may include: a processor and a generic interrupt controller (generic interrupt controller, GIC), the processor runs a VMM and a guest OS, the GIC and the VMM and There is a physical interface and a virtual interface between the guest OS.
  • the processor includes a core (core), and the core includes a processing engine (processing engine, PE) and a timer (timer).
  • the interrupt generated by the timer is taken over by the VMM, and the VMM needs to complete the processing and forwarding of the interrupt.
  • the timer in the core when the processor is in the guest OS state, the timer in the core generates an interrupt, the GIC will receive the interrupt, and report the interrupt to the VMM through the physical interface, and the processor needs to switch from the guest OS state to the VMM state; after the VMM receives the interrupt, it needs to process the interrupt to a certain extent, and finally report the interrupt to the guest OS through the virtual interface.
  • the processor needs to switch from the VMM state to the guest OS again. state.
  • the path of the interrupt reporting is shown by 1 to 5.
  • the processor when the GIC reports the interrupt to the VMM, the processor needs to switch from the guest OS state to the VMM state, and after the VMM forwards the interrupt, the processor also needs to switch back from the VMM state.
  • the guest OS state that is, the processor needs to switch between the VMM state and the guest OS state twice, which will cause the interrupt processing rate to be slow and affect the performance of the timer in the guest OS state.
  • the present application provides an interrupt reporting device, method and virtualization system, which can be used to directly report interrupts from the hardware layer to the guest operating system without forwarding by the VMM, thereby improving the interrupt processing rate and ensuring the guest OS The performance of the timer in the state.
  • an interrupt reporting device which is applied in a virtualized system, where the virtualized system includes a processor, and the device includes: a message interrupt generator, configured to, when a private peripheral interrupt PPI is acquired, send the PPI to the It is converted into a message signal interrupt, and the PPI can be generated by a timer in the core of the processor; the interrupt conversion service component is used to determine the virtual processing engine vPE according to the message signal interrupt; the interrupt controller is used to determine the virtual processing engine vPE according to the vPE; The message signal interrupt is reported to the guest operating system running on the processor.
  • a message interrupt generator configured to, when a private peripheral interrupt PPI is acquired, send the PPI to the It is converted into a message signal interrupt, and the PPI can be generated by a timer in the core of the processor
  • the interrupt conversion service component is used to determine the virtual processing engine vPE according to the message signal interrupt
  • the interrupt controller is used to determine the virtual processing engine vPE according to the vPE
  • the message signal interrupt is reported to
  • the message interrupt generator can convert the PPI into a message signal interrupt when acquiring the PPI, and the interrupt conversion service component can determine the processing according to the message signal interrupt.
  • the vPE used to run the guest operating system in the processor, so that the interrupt controller can directly report the message signal interrupt to the guest operating system according to the vPE.
  • the processor does not need to be in the VMM state and the guest OS state. Switch between them, thereby improving the processing rate of PPI and ensuring the performance of the timer in the guest OS state.
  • the processing rate of the PPI can be greatly improved.
  • the message signal interrupt includes an interrupt vector
  • the interrupt conversion service component is configured to: determine a vPE corresponding to the interrupt vector according to a first preset relationship, that is, determine a vPE for running the interrupt vector
  • the first preset relationship is used to indicate the corresponding relationship between multiple interrupt vectors and multiple vPEs
  • the multiple interrupt vectors include the interrupt vector.
  • the first preset relationship may include the multiple interrupt vectors. interrupt vectors, and an identifier of a vPE corresponding to each interrupt vector in the multiple interrupt vectors, where the identifier of the vPE can be used to determine the corresponding vPE.
  • the interrupt conversion service component may determine the vPE corresponding to the interrupt vector according to the first preset relationship, that is, determine the vPE for running the guest operating system, so that the interrupt controller can The vPE directly reports the message signal interruption to the guest operating system, thereby improving the processing rate of the PPI.
  • the interrupt controller includes multiple redistributors, and the multiple redistributors may correspond to different cores in the processor; Among the multiple redistributors, the redistributor corresponding to the vPE is determined, that is, the redistributor corresponding to the core in which the vPE is located is determined; the redistributor is used to interrupt and report the message signal to the interface corresponding to the vPE.
  • the interface In the guest operating system, the interface may be a virtual interface.
  • the interrupt conversion service component may determine the redistributor corresponding to the core where the vPE is located, so that the redistributor directly reports the message signal interrupt to the guest operating system.
  • the interrupt conversion service component is further configured to: determine the redistributor corresponding to the vPE according to a second preset relationship, where the second preset relationship is used to indicate a plurality of vPEs
  • the corresponding relationship with the multiple redistributors, the multiple vPEs include the vPEs, for example, the second preset relationship may be the identifiers of the multiple vPEs and the identifiers of the multiple vPEs.
  • the identifier of each vPE The identifier of the corresponding redistributor.
  • the identifier of the redistributor can be used to determine the corresponding redistributor.
  • the processor includes a first processor core, the first processor core includes a processing engine PE, and the vPE is a virtual vPE of the PE.
  • the first processor core further includes a timer, and the PPI is an interrupt generated by the timer, that is, the PPI is an interrupt generated by a timer in the first processor core .
  • the processor further includes a second processor core, the second processor core includes a timer, and the PPI is an interrupt generated by the timer, that is, the PPI is different from the first An interrupt generated by a timer in another core of the processor core.
  • the PPI when the timer in the processor core generates a PPI interrupt, the PPI can be directly processed from the message interrupt generator, the interrupt conversion service component and the interrupt controller after a series of processes.
  • the interrupt controller reports to the guest operating system, thereby greatly improving the processing efficiency of the PPI generated by the timer.
  • the message interrupt generator is configured to: determine interrupt information according to an interrupt generation identifier corresponding to the PPI, where the interrupt generation identifier is an identifier of the timer, for example, the interrupt generation identifier may be is the interrupt number of the timer; according to the interrupt information, the PPI is converted into a message signal interrupt.
  • the interrupt information can include an interrupt vector and a specified address, and the message interrupt generator can write the interrupt vector as data to the specified address.
  • the PPI is converted into a message signal interrupt.
  • the message interrupt generator is configured to: determine the interrupt information corresponding to the interrupt generation identifier according to interrupt configuration information, where the interrupt configuration information is used to indicate multiple interrupt generation identifiers and multiple interrupt generation identifiers. Correspondence between pieces of interrupt information, the multiple interrupt generation identifiers include the interrupt generation identifiers. In the above possible implementation manners, a simple and effective manner of determining the interrupt information corresponding to the interrupt generation identifier is provided.
  • an interrupt reporting method is provided, applied in a virtualization system, the virtualization system includes a processor, a message interrupt generator, an interrupt conversion service component and an interrupt controller, and the method includes: the message interrupt generator is in When the private peripheral interrupt PPI is obtained, the PPI is converted into a message signal interrupt, and the PPI can be generated by a timer in the core of the processor; the interrupt conversion service component determines the virtual processing engine vPE according to the message signal interrupt; the The interrupt controller reports the message signal interrupt to the guest operating system running on the processor according to the vPE.
  • the message signal interrupt includes an interrupt vector
  • the interrupt conversion service component determines the vPE according to the message signal interrupt, including: the interrupt conversion service component determines according to the first preset relationship with the The vPE corresponding to the interrupt vector, that is, the vPE used to run the guest operating system is determined, and the first preset relationship is used to indicate the corresponding relationship between multiple interrupt vectors and multiple vPEs, and the multiple interrupt vectors include the interrupt vector,
  • the first preset relationship may include the multiple interrupt vectors and the identifier of the vPE corresponding to each interrupt vector in the multiple interrupt vectors, and the identifier of the vPE may be used to determine the corresponding vPE.
  • the interrupt controller includes multiple redistributors, and the multiple redistributors may correspond to different cores in the processor, and the method further includes: the interrupt conversion service component from the The redistributor corresponding to the vPE is determined among the multiple redistributors, that is, the redistributor corresponding to the core where the vPE is located is determined; correspondingly, the interrupt controller reports the message signal interrupt to the client operation according to the vPE
  • the system includes: the redistributor reports the message signal interruption to the guest operating system according to the interface corresponding to the vPE.
  • the method further includes: the interrupt conversion service component determines the redistributor corresponding to the vPE according to a second preset relationship, where the second preset relationship is used to indicate a plurality of The correspondence between the vPE and the multiple redistributors, the multiple vPEs include the vPE, for example, the second preset relationship may be the identifiers of the multiple vPEs and the identifier of each vPE in the identifiers of the multiple vPEs The identifier of the corresponding redistributor. The identifier of the redistributor can be used to determine the corresponding redistributor.
  • the processor includes a first processor core, the first processor core includes a processing engine PE, and the vPE is a virtual vPE of the PE.
  • the first processor core further includes a timer, and the PPI is an interrupt generated by the timer, that is, the PPI is an interrupt generated by a timer in the first processor core .
  • the processor further includes a second processor core, the second processor core includes a timer, and the PPI is an interrupt generated by the timer, that is, the PPI is different from the first An interrupt generated by a timer in another core of the processor core.
  • the PPI can be directly reported from the interrupt controller to the guest operating system after a series of processing by the message interrupt generator, the interrupt conversion service component and the interrupt controller, thereby greatly improving the PPI generated by the timer. processing efficiency.
  • the message interrupt generator converts the PPI into a message signal interrupt, including: determining interrupt information according to an interrupt generation identifier corresponding to the PPI, and the interrupt generation identifier is the timer.
  • the identifier for example, the interrupt generation identifier can be the interrupt number of the timer; according to the interrupt information, the PPI is converted into a message signal interrupt, for example, the interrupt information can include an interrupt vector and a specified address, and the message interrupt generator can The interrupt vector is written into the register corresponding to the specified address as data to convert the PPI into a message signal interrupt.
  • the message interrupt generator determines the interrupt information according to the interrupt generation identifier corresponding to the PPI, including: determining the interrupt information corresponding to the interrupt generation identifier according to the interrupt configuration information, the interrupt The configuration information is used to indicate the correspondence between multiple interrupt generation identifiers and multiple interrupt information, and the multiple interrupt generation identifiers include the interrupt generation identifier.
  • a third aspect provides a virtualization system, where the virtualization system includes a processor running a guest operating system, and the interrupt reporting apparatus provided by the first aspect or any possible implementation manner of the first aspect.
  • any interrupt reporting method and virtualization system provided above include all the contents of the virtualization device provided above. Therefore, the beneficial effects that can be achieved can refer to the interrupt provided above. The beneficial effects in the reporting device will not be repeated here.
  • Fig. 1 is a kind of schematic diagram of interrupt reporting
  • FIG. 2 is a schematic structural diagram of a virtualization system according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another virtualization system provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a hardware layer provided by an embodiment of the present application.
  • FIG. 5 is a schematic flowchart of an interruption reporting method provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of an interruption reporting apparatus provided by an embodiment of the present application.
  • At least one means one or more
  • plural means two or more.
  • And/or which describes the association relationship of the associated objects, indicates that there can be three kinds of relationships, for example, A and/or B, which can indicate: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A, B can be singular or plural.
  • At least one item(s) below or similar expressions thereof refer to any combination of these items, including any combination of single item(s) or plural items(s).
  • At least one (a) of a, b, or c may represent: a, b, c, a and b, a and c, b and c, or a, b and c, where a, b, c can be single or multiple.
  • words such as “first” and “second” are used to distinguish objects with similar names or functions or functions. Those skilled in the art can understand that words such as “first” and “second” do not The quantity and execution order are not limited.
  • Interrupts are hardware or software generated signals and events. Once an interrupt occurs, the processor will immediately abort the current execution and respond to the interrupt request. Hardware interrupts are physical signals sent from the device to the processor. Once the device meets certain conditions, it notifies the processor and asks for immediate action.
  • a software interrupt is a signal generated by software running on the processor, and it mostly occurs in special circumstances, such as executing a system call, trap instruction, or other interrupt-generating instructions provided by the system.
  • Interrupt category 1) Private peripheral interrupt (PPI): This is an interrupt private to each processor core, and the PPI will be sent to the specified processor or the specified core of the processor. It is mainly aimed at the scenario where the timer of the processor core generates an interrupt. Therefore, the interrupt category in this application mainly refers to PPI; 2) Shared peripheral interrupt (SPI): It is a common external device interrupt, and also It can be called a shared interrupt and can be handled by multiple processors or cores, not limited to a specific processor; 3) Software-generated interrupt (SGI): software can trigger an interrupt by writing the GICD_SGIR register.
  • PPI Private peripheral interrupt
  • SPI Shared peripheral interrupt
  • SGI Software-generated interrupt
  • LPI Locality-specific peripheral interrupt
  • GIC Generic interrupt controller
  • ARM Generic interrupt controller
  • GIC can be divided into the following parts: 1) Distributor: used to manage SPI interrupts and send SPI interrupts to redistributors. Since this application is mainly aimed at PPI interrupts, this application describes the solution in this application. 2) Redistributor (redistributor): used to manage PPI, SGI and LPI, and send these interrupts to the processor interface (interface), such as the CPU interface.
  • the main functions of the redistributor include enabling and disabling SGI and PPI, setting the priority of SGI and PPI, setting each PPI as level-triggered or edge-triggered, assigning each SGI and PPI to an interrupt group, controlling Status and power management support of SGI and PPI, etc.; 3) Processor interface (for example, CPU interface): used to transmit interrupts to the processor core (core), responsible for shielding low-priority interrupts (relative to the priority of the interrupt being processed) level), allowing high-priority interrupts to preempt the processor.
  • Processor interface for example, CPU interface
  • Interrupt translation service (ITS) component It is mainly used to receive interrupts from peripherals, and convert these interrupts into LP interrupt identifiers and send them to the corresponding redistributor.
  • the ITS component is currently mainly used to implement LPI interrupts.
  • the peripheral initiates the LPI interrupt by writing the GITS_TRANSLATER register.
  • the ITS component will obtain two pieces of information: the event ID (event ID), the value is stored in the GITS_TRANSLATER register, indicating the event type of the peripheral sending the interrupt; the device ID (device ID), Indicates which peripheral initiated the LPI interrupt.
  • ITS obtains the LPI interrupt number through a series of look-up tables according to the event identifier and device identifier, and then uses the LPI interrupt number to look up the table to obtain the target processor of the interrupt.
  • a message based interrupt generator is a device that detects and samples level interrupts, and converts level interrupts to message signal interrupts (MSI). For example, when the message interrupt generator samples a level interrupt, it can convert the level interrupt into a message signal interrupt by writing a specific message to a specific address (for example, a specific register).
  • MSI message signal interrupt
  • a message signal interrupt also known as a message interrupt, is an interrupt generated by a message interrupt generator by writing a specific message to a specific address.
  • the technical solutions provided by the embodiments of the present application mainly relate to interrupt processing in the platform virtualization technology.
  • the platform virtualization technology is a method of hiding the actual physical characteristics of a specific computing platform by using a virtual machine monitor (VMM).
  • VMM virtual machine monitor
  • VM virtual machine
  • This paper takes the virtualization system shown in FIG. 2 as an example to illustrate the structure of the virtualization system based on the platform virtualization technology. As shown in FIG.
  • the virtualization system includes: a hardware layer, a virtual machine monitor (VMM) running on the hardware layer, and a plurality of virtual machines (virtual machines, VM), each running in the VM
  • the operating system can be called a guest operating system (guest operating system, guest OS).
  • Hardware layer The entire hardware platform that runs as a virtualized environment can include multiple hardware resources such as processor, memory, disk, network interface controller (NIC), and peripherals.
  • the processor may be a central processing unit (CPU), an artificial intelligence (artificial intelligence, AI) processor, and/or a network processor, and the like.
  • the memory may include random access memory and/or read only memory, among others.
  • the peripheral device is an abbreviation of an external device, and may include an input device, a display device, and/or a printing device, and the like.
  • the VMM may also be called a hypervisor, and as a management layer, the VMM can be used to: complete the management and allocation of hardware resources; present a virtual hardware platform for multiple VMs; and perform scheduling and isolation of multiple VMs.
  • the virtual hardware platform provides various hardware resources, such as virtual processors, virtual memory, virtual disks, virtual network cards, and virtual peripherals, to multiple VMs on it. Multiple VMs run on a virtual platform for which the VMM is prepared.
  • the processor in the hardware layer may have two working modes, EL1 and EL2, the EL1 mode is used to run the guest OS, and the EL2 mode is used to run the VMM. That is, when the processor works in the EL1 mode, the processor is used to run the guest OS, which can also be called the guest OS state; when the processor works in the EL2 mode, the processor is used to run the VMM. , which can also be referred to as the processor in the VMM state.
  • the processor may be a multi-core processor such as a dual-core, quad-core or octa-core, and each core (core) in the multi-core processor may run one or more VMs, so that each core may run a One or more guest OS.
  • the multi-core processor may include core 0 and core 1, the multiple guest OSs include guest OS0 and guest OS1, guest OS0 runs on core 0, and guest OS1 runs on core 1.
  • each core in the multi-core processor may include a processing engine (PE) and a timer (timer).
  • PE processing engine
  • timer timer
  • the PE in the core can be called a virtual processing engine (vPE) for the guest OS
  • the timer in the core can be called a virtual processing engine (vPE) for the guest OS.
  • Virtual timer virtual timer
  • the timer in each core can have the following functions: used to measure the elapsed time in real time; used to measure the virtual time elapsed on a certain VM; used for timing, triggering an event at regular intervals, and forward timing and countdown, etc.; provide system counter (system counter) function.
  • the hardware layer may further include a message interrupt generator MBIG, an interrupt conversion service ITS component, and an interrupt controller.
  • the interrupt controller may be a general interrupt controller GIC. This GIC will be described as an example.
  • the GIC may include a distributor and multiple redistributors, the multiple redistributors may correspond one-to-one with multiple cores in the multi-core processor, and each core has a processor interface with the GIC, and the processing Device interfaces (represented as interfaces in the figure) may include physical interfaces and virtual interfaces.
  • the GIC includes four redistributors and are denoted as RD1 to RD4 respectively
  • the multi-core processor includes four cores and are denoted as C1 to C4 respectively
  • RD1 to RD4 are in one-to-one correspondence with C1 to C4, for example, RD1 Corresponding to C1, RD2 corresponds to C2, RD3 corresponds to C3, RD4 corresponds to C4 as an example for description.
  • the MBIG can be used to convert PPI (for example, an interrupt generated by a timer, the interrupt can also be called a level interrupt) into a message signal interrupt MSI, and the MSI can carry interrupt information; the ITS component can be used to provide interrupts for interrupts.
  • PPI for example, an interrupt generated by a timer, the interrupt can also be called a level interrupt
  • MSI can carry interrupt information
  • the ITS component can be used to provide interrupts for interrupts.
  • Directed services such as forwarding interrupts to the corresponding redistributor in the GIC according to the MSI
  • the ITS is transparent (or non-existent) to the guest OS; the redistributor can be used to forward received interrupts through virtual
  • the interface is reported to the corresponding guest OS, and the guest OS handles the interrupt.
  • FIG. 3 only shows a part of the structure of the hardware layer related to the present application.
  • the hardware layer of the virtualization system includes: a processor, an MBIG, an ITS component and a GIC, and the core of the processor includes a PE and a timer.
  • a VMM and a guest OS run on the processor, a physical interface and a virtual interface are provided between the GIC, the VMM and the guest OS, and the GIC includes a redistributor corresponding to the core of the processor.
  • FIG. 4 is a virtual vPE of PE, and for the guest OS, the PE is a vPE; the virtual (virtual, v) timer (v timer for short) is a virtual timer of the timer, and for the guest OS Timers are virtual timers.
  • 1 to 5 in FIG. 4 show an interrupt reporting path of a timer in the core. For the corresponding reporting method, refer to the related description of the interrupt reporting method provided in this document.
  • the interrupt reporting method provided by this embodiment of the present application can be applied to any of the virtualization systems provided above, and the method can be used to report PPI.
  • PPI is an interrupt private to the core of the processor and needs to be reported to a designated processing on the specified core of the processor or processor.
  • the processor when the processor is in the guest OS state, from the software level, the PPI of the processor needs to be reported to the guest OS running on the processor, and the guest OS processes the PPI.
  • the processor includes one or more core processors
  • the PPI of the processor includes the PPI of the one or more core processors, so the PPI of a certain core needs to be reported to the guest OS running on the core.
  • the interrupt reporting method provided by the embodiment of the present application can directly report the generated PPI to the guest OS when the processor is in the guest OS state, and the processor does not need to switch between the VMM state and the guest OS state, thereby improving the The interrupt processing rate is guaranteed, and the performance of the timer in the guest OS state is also guaranteed.
  • FIG. 5 is a schematic flowchart of an interrupt reporting method provided by an embodiment of the present application.
  • the method can be applied to a virtualization system, and the virtualization system can be the virtualization system provided above.
  • the method includes the following steps .
  • the PPI may be PPI generated by different peripherals corresponding to the core of the processor, and the present application mainly takes the PPI generated by the timer in the core of the processor as an example for description.
  • the processor may include one or more cores, timers in the one or more cores may be used to generate the PPI, and one or more guest OSs may run on the one or more cores.
  • the first core of the processor includes a first PE and a first timer, a first guest OS runs on the first PE, and the PPI is generated by the first timer.
  • the MBIG can be used to detect and sample the interrupt pins of one or more timers included in the core of the processor, and the one or more timers include the first timer, so that when the first timer generates the In the case of PPI, the MBIG can obtain the PPI through the interrupt pin of the first timer, and the form of the PPI can be a level interrupt. After that, the MBIG can determine the first interrupt information according to the first interrupt generation identifier corresponding to the PPI, and convert the PPI into a message signal interrupt according to the first interrupt information, and the first interrupt generation identifier can be the first timing for generating the PPI device identification.
  • the process of determining the first interrupt information by the MBIG according to the first interrupt generation identifier corresponding to the PPI may be: determining the first interrupt information corresponding to the first interrupt generation identifier according to the interrupt configuration information, where the interrupt configuration information is used to indicate Correspondence between multiple interrupt generation identifiers and multiple interrupt information, where the multiple interrupt generation identifiers include a first interrupt generation identifier.
  • the multiple interrupt generation identifiers may be interrupt numbers of multiple timers included in the processor, so the first interrupt generation identifier may be the interrupt number of the first timer.
  • the interrupt number of each timer in the plurality of timers may be the interrupt pin identifier of the timer, so that the interrupt number of the first timer may be the interrupt pin identifier of the first timer .
  • each interrupt information in the plurality of interrupt information may include an interrupt vector and a designated address
  • the first interrupt information may include a first interrupt vector and a first designated address
  • the first interrupt vector may be used to identify the PPI interrupt
  • the first interrupt vector may be used to identify the PPI interrupt.
  • a specified address may be the address of a particular register.
  • the MBIG may be based on the interrupt index of the first timer.
  • a pin identifier, first interrupt information corresponding to the interrupt pin identifier of the first timer is obtained from the interrupt configuration information, and the first interrupt information includes a first interrupt vector and a first designated address.
  • the MBIG can write the first interrupt vector as data into the interrupt generation register corresponding to the first designated address to generate the message signal interrupt of the PPI, that is, convert the PPI into a message signal interrupt.
  • the interrupt configuration information may be pre-configured.
  • the VMM in the virtualization system may determine the interrupt configuration information in advance, and configure the interrupt configuration information to the MBIG, which is not performed in this embodiment of the present application. specific restrictions.
  • S202 The ITS component interrupts and determines the first vPE according to the message signal.
  • the processor may include one or more cores, and each core includes one PE, so that the processor may include one or more PEs, and each PE may virtualize one or more vPEs, so that the processor may Include multiple vPEs, each of which can be used to run a guest OS.
  • the first vPE may be the vPE of the above-mentioned first PE, and the first vPE may be used to run the first guest OS.
  • the message signal interrupt may include a first interrupt vector
  • the ITS component may determine a first vPE corresponding to the first interrupt vector according to a first preset relationship, and the first preset relationship is used to indicate that the multiple interrupt vectors are related to Correspondence between multiple vPEs, where the multiple interrupt vectors include the first interrupt vector.
  • the first preset relationship may include an identifier of a vPE corresponding to each interrupt vector in the plurality of interrupt vectors, and the identifier of one vPE may be used to indicate the vPE, so that the ITS component obtains the identifier of the first vPE. identification, that is, determining the first vPE corresponding to the first interrupt vector.
  • the ITS component may include a translator, and the translator can be used to capture the message signal interrupt generated by the MBIG write interrupt generation register, so that the MBIG writes the first interrupt vector into the first specified address corresponding to the
  • the translator in the ITS component can capture the message signal interrupt; the ITS component can query the first preset relationship according to the first interrupt information in the message signal interrupt to start from the first preset relationship.
  • the identifier of the vPE corresponding to the first interrupt vector ie, the identifier of the first vPE
  • the ITS component can send the identifier of the first vPE to the GIC, so that the GIC can determine the first vPE according to the identifier of the first vPE.
  • the first preset relationship may be preset, for example, the first preset relationship is preset by the VMM and configured to the ITS component, which is not specifically limited in this embodiment of the present application.
  • the GIC includes a plurality of redistributors (as shown in FIG. 3 ), and the plurality of redistributors are in one-to-one correspondence with the plurality of cores of the processor.
  • the ITS component may also determine The first redistributor corresponding to the first vPE, the first redistributor is the redistributor corresponding to the first core, and the first vPE is the vPE of the first PE in the first core, so the first vPE also corresponds to the first redistributor.
  • Distributor may also determine The first redistributor corresponding to the first vPE, the first redistributor is the redistributor corresponding to the first core, and the first vPE is the vPE of the first PE in the first core, so the first vPE also corresponds to the first redistributor.
  • the ITS component may determine the first redistributor corresponding to the first vPE according to a second preset correspondence, and the second preset correspondence is used to indicate the correspondence between multiple vPEs and multiple redistributors,
  • the plurality of vPEs include a first vPE.
  • the second preset correspondence may include the identifiers of the multiple vPEs, and the identifiers of the redistributors corresponding to the identifiers of each vPE, and the identifiers of one redistributor may be used to indicate the redistributor, Therefore, the ITS component can obtain the identifier of the redistributor corresponding to the identifier of the first vPE from the second preset correspondence according to the identifier of the first vPE, and the identifier of the corresponding redistributor is the identifier of the first redistributor. , that is, the first redistributor corresponding to the first vPE is determined. Afterwards, the ITS component may send the identity of the first vPE to the first redistributor in the GIC.
  • the ITS component may also send the configuration information of the PPI to the GIC, for example, the configuration information may include the priority of the PPI and the enable state of the PPI, and the like.
  • the ITS component may also send the list information of the PPIs to be processed together with configuration information and the like to the GIC.
  • the other PPIs to be processed include one or more PPIs that need to be distributed by the first redistributor, the ITS component can send the list information and configuration information of the corresponding PPIs to be processed to the first redistributor together. . This embodiment of the present application does not specifically limit this.
  • S203 The GIC reports the message signal interruption to the first guest OS according to the first vPE.
  • the interrupt controller may directly report the message signal interrupt to the first guest OS through the virtual interface, thus completing the reporting of the PPI.
  • the first guest OS can process the message signal interrupt, that is, the first guest OS can process the PPI. For example, when the priority of the PPI is higher than the priority of the task currently executed by the first guest OS, the first guest OS can suspend the task and transfer to process the PPI.
  • the GIC includes multiple redistributors, the first vPE corresponds to the first redistributor in the multiple redistributors, and the first redistributor can interrupt the message signal through the virtual interface corresponding to the first vPE. Report directly to the first guest OS.
  • the first redistributor when the ITS component sends the configuration information of the PPI to the first redistributor, if the enable state in the configuration information is valid (or in an active state (active)), the first redistributor can Report the message signal interruption to the first guest OS. If the enable state in the configuration information is invalid, the first redistributor may not report the message signal interruption. Further, when the ITS component sends the list information and configuration information of the PPIs to be processed to the first redistributor, for each PPI to be processed in the list information, the first redistributor can Select to report or not to report the enabled state of the processing PPI.
  • the first redistributor may further process the multiple to-be-processed PPIs in sequence according to the order of the priorities of the multiple to-be-processed PPIs.
  • the interrupt reporting method provided by the embodiment of the present application can be used to report the PPI of one core to the guest OS running on the core, and can also be used to report the PPI of one core to the guest running on another core.
  • OS can be used to report the PPI of one core to the guest OS running on the core, and can also be used to report the PPI of one core to the guest running on another core.
  • the PPI generated by the timer in the core 1 (or the first processor core) can be reported to the guest OS running on the vPE in the core 1 (or the first processor core) through the method of the present application;
  • the PPI generated by the timer in the core 2 (or the second processor core) can be reported to the guest OS running on the vPE in the core 1 (or the first processor core) through the method of the present application.
  • the embodiment does not specifically limit this.
  • the MBIG can convert the PPI into a message signal interrupt when acquiring the PPI, and the ITS component can determine the PPI used in the processor according to the message signal interrupt.
  • the GIC can directly report the message signal interruption to the first guest OS according to the first vPE.
  • the processor does not need to perform between the VMM state and the guest OS state. Switching, thereby improving the processing rate of PPI, and also ensuring the performance of the timer in the guest OS state. Especially for the PPI generated by the timer in the core, the processing rate of the PPI can be greatly improved.
  • the virtualization system includes corresponding hardware structures and/or software modules for executing each function.
  • the present application can be implemented in hardware or in the form of a combination of hardware and computer software, in conjunction with the devices and algorithm steps of each example described in the embodiments disclosed herein. Whether a function is performed by hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Skilled artisans may implement the described functionality using different methods for each particular application, but such implementations should not be considered beyond the scope of the present invention.
  • the virtualization system may be divided into functional modules according to the foregoing method examples.
  • each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module.
  • the above-mentioned integrated modules can be implemented in the form of hardware, and can also be implemented in the form of software function modules. It should be noted that, the division of modules in the embodiments of the present application is schematic, and is only a logical function division, and there may be other division manners in actual implementation.
  • FIG. 6 shows a possible schematic structural diagram of the interrupt reporting device involved in the above embodiment, and the device may include: a message interrupt generator 301, an interrupt conversion service Component 302 and interrupt controller 303, which may include multiple redistributors.
  • the message interrupt generator 301 can be used to support the device to perform S201 in the above method embodiments;
  • the interrupt conversion service component 302 can be used to support the device to perform S202 in the above method embodiments;
  • the interrupt controller 303 can be used to support the device to perform the above method embodiments.
  • S203 in the method embodiment.
  • a virtualization system in another embodiment, includes a processor running a guest operating system, and the interrupt reporting device provided above; wherein, the interrupt reporting device can use in performing the steps in the interrupt reporting method provided above.
  • the core of the processor may include a processing engine PE and a timer, and the interrupt reporting device may report the interrupt generated by the timer to the guest operating system on the processor through the method provided above.
  • the message interrupt generator can convert the PPI into a message signal interrupt when acquiring the PPI, and the interrupt conversion service component can determine according to the message signal interrupt
  • the processor is used to run the vPE of the guest operating system, so that the interrupt controller can directly report the message signal interrupt to the guest operating system according to the vPE.
  • the processor does not need to be in the VMM state and the guest OS Switch between states, thereby improving the processing rate of PPI and ensuring the performance of the timer in the guest OS state.
  • the processing rate of the PPI can be greatly improved.
  • the disclosed apparatus, virtualization system and method may be implemented in other manners.
  • the embodiments of the interrupt reporting apparatus described above are only illustrative.
  • the division of the modules or units is only a functional division. In actual implementation, there may be other divisions, such as multiple divisions. Units or components may be combined or may be integrated into another device, or some features may be omitted, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place, or may be distributed to multiple different places . Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

Abstract

本申请提供一种中断上报装置、方法及虚拟化系统，涉及虚拟化技术领域，用于提高了中断的处理速率。该装置应用于包括处理器的虚拟化系统中，包括：消息中断发生器，用于在获取到PPI时，将该PPI转换为消息信号中断；中断转换服务组件，用于根据该消息信号中断确定vPE；中断控制器，用于根据该vPE将该消息信号中断上报给该处理器上运行的客户操作系统。这样，该PPI可直接从中断控制器上报至该客户操作系统，而无需经过VMM的转发，进而提高了PPI中断的处理速率。

Description

一种中断上报装置、方法及虚拟化系统 技术领域
本申请涉及虚拟化技术领域，尤其涉及一种中断上报装置、方法及虚拟化系统。
背景技术
平台虚拟化技术是一种通过使用虚拟机监控器(virtual machine monitor，VMM)，隐藏特定计算平台的实际物理特性，为用户提供抽象的、统一的、模拟的计算环境的技术，该计算环境可以称为虚拟机(virtual machine，VM)。其中，VM中运行的操作系统可以称为客户操作系统(guest operation system，guest OS)。如图1所示，该平台虚拟化环境的硬件层中可以包括：处理器和通用中断控制器(generic interrupt controller，GIC)，该处理器上运行有VMM和guest OS，该GIC与该VMM和该guest OS之间存在物理接口和虚拟接口。另外，该处理器中包括核(core)，该核中包括处理引擎(processing engine，PE)和定时器(timer)。
现有技术中，在图1所示的平台虚拟化环境下，定时器产生的中断由VMM接管，VMM需要完成对该中断的处理和转发。具体的，当该处理器处于guest OS状态，该核中的定时器产生中断，该GIC会接收到该中断，并将该中断通过物理接口上报至该VMM，该处理器需要从guest OS状态切换至VMM状态；该VMM在接收到该中断之后，需要对该中断进行一定的处理，并最终将该中断通过虚拟接口上报至该guest OS，此时该处理器需要从VMM状态再切换回guest OS状态。图1中通过①至⑤表示出了该中断上报的路径。
上述技术方案中，该GIC在向该VMM上报该中断时，该处理器需要从guest OS状态切换至VMM状态，在该VMM将该中断转发之后，该处理器还需要从该VMM状态再切换回该guest OS状态，即该处理器需要在该VMM状态和该guest OS状态之间进行两次切换，这样会导致该中断的处理速率较慢，同时会影响guest OS状态下该定时器的性能。
发明内容
本申请提供一种中断上报装置、方法及虚拟化系统，可用于将中断从硬件层直接上报至客户操作系统，而无需经过VMM的转发，进而提高了中断的处理速率，同时也保证了guest OS状态下定时器的性能。
为达到上述目的，本申请采用如下技术方案：
第一方面，提供一种中断上报装置，应用于虚拟化系统中，该虚拟化系统包括处理器，该装置包括：消息中断发生器，用于在获取到私有外设中断PPI时，将该PPI转换为消息信号中断，该PPI可以由该处理器的核中的定时器产生；中断转换服务组件，用于根据该消息信号中断确定虚拟处理引擎vPE；中断控制器，用于根据该vPE将该消息信号中断上报给该处理器上运行的客户操作系统。
上述技术方案中，对于虚拟化系统中产生的PPI，该消息中断发生器可以在获取到该PPI时，将该PPI转换为消息信号中断，该中断转换服务组件可以根据该消息信号中断确定该处理器中用于运行该客户操作系统的vPE，从而该中断控制器可以根据该vPE将该消息信号中断直接上报给该客户操作系统，在此过程中该处理器无需在VMM状态与guest  OS状态之间进行切换，从而提高了PPI的处理速率、同时也保证了guest OS状态下定时器的性能。尤其是对于核中的定时器产生的PPI，能够大大提高该PPI的处理速率。
在第一方面的一种可能的实现方式中，该消息信号中断包括中断向量，该中断转换服务组件用于：根据第一预设关系确定与该中断向量对应的vPE，即确定用于运行该客户操作系统的vPE，第一预设关系用于指示多个中断向量与多个vPE之间的对应关系，该多个中断向量包括该中断向量，比如，第一预设关系中可以包括该多个中断向量、以及该多个中断向量中每个中断向量对应的vPE的标识，该vPE的标识可以用于确定对应的vPE。上述可能的实现方式中，该中断转换服务组件可以根据第一预设关系确定与该中断向量对应的vPE，即确定了用于运行该客户操作系统的vPE，从而使得该中断控制器可以根据该vPE直接将该消息信号中断上报给该客户操作系统，进而提高了该PPI的处理速率。
在第一方面的一种可能的实现方式中，该中断控制器包括多个重分发器，该多个重分发器可以对应处理器中不同的核；该中断转换服务组件，还用于从该多个重分发器中确定与该vPE对应的重分发器，即确定该vPE所在的核对应的重分发器；该重分发器，用于通过与该vPE对应的接口将该消息信号中断上报给该客户操作系统，该接口可以为虚拟接口。上述可能的实现方式中，中断转换服务组件可以通过确定该vPE所在的核对应的重分发器，从而使得该重分发器直接将该消息信号中断上报给该客户操作系统。
在第一方面的一种可能的实现方式中，该中断转换服务组件还用于：根据第二预设关系确定与该vPE对应的该重分发器，第二预设关系用于指示多个vPE与该多个重分发器之间的对应关系，该多个vPE包括所述vPE，比如，第二预设关系可以该多个vPE的标识、以及该多个vPE的标识中每个vPE的标识对应的重分发器的标识，重分发器的标识可用于确定对应的重分发器。上述可能的实现方式中，提供了一种简单有效的确定该vPE对应的该重分发器的方式。
在第一方面的一种可能的实现方式中，该处理器包括第一处理器核，第一处理器核包括处理引擎PE，该vPE是该PE虚拟的vPE。
在第一方面的一种可能的实现方式中，该第一处理器核中还包括定时器，该PPI是该定时器产生的中断，即PPI是第一处理器核中的定时器产生的中断。
在第一方面的一种可能的实现方式中，该处理器还包括第二处理器核，第二处理器核包括定时器，该PPI是该定时器产生的中断，即PPI是不同于第一处理器核的另一个核中的定时器产生的中断。
上述可能的实现方式中，当处理器核中的定时器产生PPI中断时，该PPI可以依次经过该消息中断发生器、该中断转换服务组件和该中断控制器的一系列处理后，直接从该中断控制器上报至该客户操作系统，从而大大提高了定时器产生的PPI的处理效率。
在第一方面的一种可能的实现方式中，该消息中断发生器用于：根据该PPI对应的中断产生标识确定中断信息，该中断产生标识为该定时器的标识，比如，该中断产生标识可以为该定时器的中断号；根据该中断信息将该PPI转换为消息信号中断，比如，该中断信息可以包括中断向量和指定地址，消息中断发生器可以将该中断向量作为数据写入该指定地址对应的寄存器中以将该PPI转换为消息信号中断。上述可能的实现方式中，提供了一种简单有效的将该PPI转换为消息信号中断的方式。
在第一方面的一种可能的实现方式中，该消息中断发生器用于：根据中断配置信息确 定与该中断产生标识对应的该中断信息，该中断配置信息用于指示多个中断产生标识与多个中断信息之间的对应关系，该多个中断产生标识包括所述中断产生标识。上述可能的实现方式中，提供了一种简单有效的确定与该中断产生标识对应的该中断信息的方式。
第二方面，提供一种中断上报方法，应用于虚拟化系统中，该虚拟化系统包括处理器、消息中断发生器、中断转换服务组件和中断控制器，该方法包括：该消息中断发生器在获取到私有外设中断PPI时，将该PPI转换为消息信号中断，该PPI可以由该处理器的核中的定时器产生；该中断转换服务组件根据该消息信号中断确定虚拟处理引擎vPE；该中断控制器根据该vPE将该消息信号中断上报给该处理器上运行的客户操作系统。
在第二方面的一种可能的实现方式中，该消息信号中断包括中断向量，该中断转换服务组件根据该消息信号中断确定vPE，包括：该中断转换服务组件根据第一预设关系确定与该中断向量对应的vPE，即确定用于运行该客户操作系统的vPE，第一预设关系用于指示多个中断向量与多个vPE之间的对应关系，该多个中断向量包括该中断向量，比如，第一预设关系中可以包括该多个中断向量、以及该多个中断向量中每个中断向量对应的vPE的标识，该vPE的标识可以用于确定对应的vPE。
在第二方面的一种可能的实现方式中，该中断控制器包括多个重分发器，该多个重分发器可以对应处理器中不同的核，该方法还包括：该中断转换服务组件从该多个重分发器中确定与该vPE对应的重分发器，即确定该vPE所在的核对应的重分发器；相应的，该中断控制器根据该vPE将该消息信号中断上报给该客户操作系统，包括：该重分发器根据与该vPE对应的接口将该消息信号中断上报给该客户操作系统。
在第二方面的一种可能的实现方式中，该方法还包括：该中断转换服务组件根据第二预设关系确定与该vPE对应的该重分发器，第二预设关系用于指示多个vPE与该多个重分发器之间的对应关系，该多个vPE包括该vPE，比如，第二预设关系可以该多个vPE的标识、以及该多个vPE的标识中每个vPE的标识对应的重分发器的标识，重分发器的标识可用于确定对应的重分发器。
在第二方面的一种可能的实现方式中，该处理器包括第一处理器核，第一处理器核包括处理引擎PE，该vPE是该PE虚拟的vPE。
在第二方面的一种可能的实现方式中，该第一处理器核中还包括定时器，该PPI是该定时器产生的中断，即PPI是第一处理器核中的定时器产生的中断。
在第二方面的一种可能的实现方式中，该处理器还包括第二处理器核，第二处理器核包括定时器，该PPI是该定时器产生的中断，即PPI是不同于第一处理器核的另一个核中的定时器产生的中断。
这样该PPI可以依次经过该消息中断发生器、该中断转换服务组件和该中断控制器的一系列处理后，直接从该中断控制器上报至该客户操作系统，从而大大提高了定时器产生的PPI的处理效率。
在第二方面的一种可能的实现方式中，该消息中断发生器将该PPI转换为消息信号中断，包括：根据该PPI对应的中断产生标识确定中断信息，该中断产生标识为该定时器的标识，比如，该中断产生标识可以为该定时器的中断号；根据该中断信息将该PPI转换为消息信号中断，比如，该中断信息可以包括中断向量和指定地址，消息中断发生器可以将该中断向量作为数据写入该指定地址对应的寄存器中以将该PPI转换为消息信号中断。
在第二方面的一种可能的实现方式中，该消息中断发生器根据该PPI对应的中断产生标识确定中断信息，包括：根据中断配置信息确定与该中断产生标识对应的该中断信息，该中断配置信息用于指示多个中断产生标识与多个中断信息之间的对应关系，该多个中断产生标识包括该中断产生标识。
第三方面，提供一种虚拟化系统，该虚拟化系统包括运行有客户操作系统的处理器、以及上述第一方面或者第一方面的任一种可能的实现方式所提供的中断上报装置。
可以理解地，上述提供的任一种中断上报方法和虚拟化系统等均包含了上文所提供的虚拟化装置的所有内容，因此，其所能达到的有益效果可参考上文所提供的中断上报装置中的有益效果，此处不再赘述。
附图说明
图1为一种中断上报的示意图；
图2为本申请实施例提供的一种虚拟化系统的结构示意图；
图3为本申请实施例提供的另一种虚拟化系统的结构示意图；
图4为本申请实施例提供的一种硬件层的结构示意图；
图5为本申请实施例提供的一种中断上报方法的流程示意图；
图6为本申请实施例提供的一种中断上报装置的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例进行描述。
本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b，或c中的至少一项(个)，可以表示：a，b，c，a和b，a和c，b和c，或a、b和c，其中a，b，c可以是单个，也可以是多个。另外，本申请的实施例采用了“第一”、“第二”等字样对名称或功能或作用类似的对象进行区分，本领域技术人员可以理解“第一”、“第二”等字样并不对数量和执行次序进行限定。
本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
首先，对本申请中的部分用语进行解释说明，以便于本领域技术人员理解。
中断：中断是硬件或软件生成的信号(signal)和事件(event)。一旦中断发生，处理器会立即中止现在的执行并响应中断请求。硬件中断就是从设备发送给处理器的物理信号(physical signal)。一旦设备满足特定条件，它就会通知处理器并要求立刻处理。软件中断是由运行在处理器上的软件生成的信号，且它多发生在特殊情况，比如执行系统调用(system call)、陷阱(trap)指令或系统提供的其他中断生成指令。
中断类别：1)私有外设中断(private peripheral interrupt，PPI)：这是每个处理器核所私有的中断，PPI会被送达到指定处理器或者处理器的指定核上，由于本申请的方案主要是针对处理器核的定时器产生中断的场景，因此，本申请的中断类别主要是指PPI；2) 共享外设中断(shared peripheral interrupt，SPI)：是一种公用的外部设备中断，也可以称为共享中断，可以由多个处理器或者核(core)处理，不限定特定的处理器；3)软件触发的中断(software generated interrupt，SGI)：软件可以通过写GICD_SGIR寄存器来触发一个中断事件，一般用于核间通信；4)局部特定外设中断(locality-specific peripheral interrupt，LPI)，是GICv3中的新特性，LPI在很多方面与其他类型的中断不同，LPI始终是基于消息的中断，LPI的配置保存在表中而不是寄存器。
通用中断控制器(generic interrupt controller，GIC)：是ARM公司提供的一个通用的中断控制器，主要用于接收中断信号，并经过一定处理后分发给对应的处理器进行处理。GIC可以分为如下几部分：1)分发器(distributor)：用于管理SPI中断，并且将SPI中断发送给重分发器(redistributor)，由于本申请主要针对PPI中断，因此本申请在描述本方案时不对GIC中的分发器做过多描述；2)重分发器(redistributor)：用于管理PPI、SGI和LPI，将这些中断发送给处理器接口(interface)，比如CPU接口。具体地，重分发器的主要功能包括启用和禁用SGI和PPI、设置SGI和PPI的优先级、将每个PPI设置为电平触发或边缘触发、将每个SGI和PPI分配给中断组、控制SGI和PPI的状态和电源管理支持等；3)处理器接口(比如，CPU接口)：用于传输中断给处理器核(core)，负责屏蔽低优先级中断(相对于正在处理的中断的优先级)，让高优先级的中断抢占处理器。
中断转换服务(interrupt translation service，ITS)组件：主要用于负责接收来自外设的中断，并将这些中断转化为LP中断标识发送到相应的重分发器，ITS组件目前主要用于实现LPI中断。外设通过写GITS_TRANSLATER寄存器发起LPI中断，此时ITS组件会获得两个信息：事件标识(event ID)，值保存在GITS_TRANSLATER寄存器中，表示外设发送中断的事件类型；设备标识(device ID)，表示哪一个外设发起LPI中断。ITS根据事件标识和设备标识，通过一系列查表，得到LPI中断号，再使用LPI中断号查表，得到该中断的目标处理器。
消息中断发生器(message based interrupt generator，MBIG)是一种用于检测和采样电平中断，以及将电平中断转换为消息信号中断(message signal interrupt，MSI)的设备。比如，消息中断发生器在采样到电平中断时，可以通过写一个特定消息到特定地址(比如，特定寄存器)，以将该电平中断转换为消息信号中断。消息信号中断(message signal interrupt，MSI)，也可以称为消息中断，是消息中断发生器通过写一个特定消息到特定地址而产生的中断。
本申请实施例提供的技术方案主要涉及平台虚拟化技术中的中断处理，该平台虚拟化技术是一种通过使用虚拟机监控器(virtual machine monitor，VMM)，隐藏特定计算平台的实际物理特性，为用户提供抽象的、统一的、模拟的计算环境的技术，该计算环境可以称为虚拟机(virtual machine，VM)。本文以图2所示的虚拟化系统为例，对基于平台虚拟化技术的虚拟化系统的结构进行举例说明。如图2所示，该虚拟化系统包括：硬件层、运行在该硬件层上的虚拟机监控器(virtual machine monitor，VMM)和多个虚拟机(virtual machine，VM)，每个VM中运行的操作系统可以称为客户操作系统(guest operation system，guest OS)。
硬件层：作为虚拟化环境运行的整个硬件平台，具体可以包括处理器、内存(memory)、磁盘(disk)、网络接口卡(network interface controller，NIC)和外设等多个硬件资源。 示例性的，该处理器可以为中央处理器(central processing unit，CPU)、人工智能(artificial intelligence，AI)处理器和/或网络处理器等。该内存可以包括随机存取存储器和/或只读存储器等。该外设是外部设备的简称，可以包括输入设备、显示设备和/或打印设备等。
VMM也可以称为超级监控器(hypervisor)，VMM作为管理层可用于：完成硬件资源的管理和分配；为多个VM呈现一个虚拟硬件平台；以及执行多个VM的调度和隔离。虚拟硬件平台对其上的多个VM提供各种硬件资源，比如虚拟处理器、虚拟内存、虚拟磁盘、虚拟网卡和虚拟外设等。多个VM运行在VMM为其准备的虚拟平台中。
具体的，该硬件层中的处理器可以具有EL1和EL2两个工作模式，EL1模式用于运行guest OS，EL2模式用于运行VMM。也即是，当该处理器工作在EL1模式时，该处理器用于运行guest OS，也可以称为该处理器为guest OS状态；当该处理器工作在EL2模式时，该处理器用于运行VMM，也可以称为该处理器为VMM状态。
进一步的，该处理器可以为双核、四核或者八核等多核处理器，该多核处理器中的每个核(core)上可以运行有一个或者多个VM，从而每个核上可以运行有一个或者多个guest OS。比如，该多核处理器可以包括核0和核1，该多个guest OS包括guest OS0和guest OS1，guest OS0运行在核0上，guest OS1运行在核1上。此外，该多核处理器中的每个核可以包括处理引擎(processing engine，PE)和定时器(timer)。当处理器工作在guest OS状态下时，核中的PE对于guest OS而言可以称为虚拟处理引擎(virtual processing engine，vPE)，核中的定时器(timer)对于guest OS而言可以称为虚拟定时器(virtual timer)。其中，每个核中的定时器可以具有以下功能：用于实时测量流逝的时间；用于测量某个VM上流逝的虚拟时间；用于定时、每隔一段时间触发一个事件、以及正向计时和倒计时等；提供系统计数器(system counter)功能。
在本申请实施例中，如图3所示，该硬件层中还可以包括消息中断发生器MBIG、中断转换服务ITS组件和中断控制器，该中断控制器可以为通用中断控制器GIC，下面以该GIC为例进行说明。其中，该GIC可以包括分发器和多个重分发器，该多个重分发器与多核处理器中的多个核可以一一对应，每个核与该GIC之间具有处理器接口，该处理器接口(图中表示为接口)可以包括物理接口和虚拟接口。图3中以该GIC包括四个重分发器且分别表示为RD1至RD4，该多核处理器包括四个核且分别表示为C1至C4，RD1至RD4与C1至C4一一对应，比如，RD1对应C1、RD2对应C2、RD3对应C3、RD4对应C4为例进行说明。其中，该MBIG可用于将PPI(比如，定时器产生的中断，该中断也可以称为电平中断)转换为消息信号中断MSI，该MSI中可以承载中断信息；ITS组件可用于为中断提供重定向服务，比如，根据该MSI将中断转发该GIC中对应的重分发器上，该ITS对于guest OS而言是透明的(或不存在的)；该重分发器可用于将接收的中断通过虚拟接口上报至对应的guest OS，由该guest OS处理该中断。需要说明的是，图3中仅示出了硬件层中与本申请相关的部分结构。
为便于理解，以该处理器的一个核上运行的一个guest OS为例，对该虚拟化系统的结构进行举例说明。如图4所示，该虚拟化系统的硬件层包括：处理器、MBIG、ITS组件和GIC，该处理器的核包括PE和定时器。其中，该处理器上运行有VMM和guest OS，该GIC与该VMM和该guest OS之间具有物理接口和虚拟接口，该GIC中包括与该处理器的核对应的重分发器。另外，图4中的vPE是PE虚拟的vPE，对于guest OS而言PE是vPE； 虚拟(virtual，v)定时器(简称v定时器)是定时器虚拟的虚拟定时器，对于guest OS而言定时器是虚拟定时器。图4中的①至⑤示出了一种核中定时器的中断的上报路径，对应的上报方法参见本文提供的中断上报方法的相关描述。
本申请实施例提供的中断上报方法可以应用于上文所提供的任一种虚拟化系统中，该方法可用于PPI的上报，PPI是处理器的核所私有的中断，需要被上报至指定处理器或者处理器的指定核上。在该虚拟化系统中，当该处理器处于guest OS状态下时，从软件层面而言，该处理器的PPI需要被上报至该处理器上运行的guest OS，由该guest OS处理该PPI。进一步的，当该处理器包括一个或者多个核处理器，该处理器的PPI包括这一个或者多个核处理器的PPI，从而某一核的PPI需要上报至该核上运行的guest OS。本申请实施例提供的中断上报方法可以在该处理器处于guest OS状态下时，直接将产生的PPI上报至guest OS，且该处理器无需在VMM状态于guest OS状态之间进行切换，从而提高了中断的处理速率、同时也保证了guest OS状态下定时器的性能。
图5为本申请实施例提供的一种中断上报方法的流程示意图，该方法可以应用于虚拟化系统中，该虚拟化系统可以为上文所提供的虚拟化系统，该方法包括以下几个步骤。
S201：MBIG在获取到PPI时，将该PPI转换为消息信号中断。
其中，该PPI可以是处理器的核对应的不同外设产生的PPI，本申请主要以该PPI是该处理器的核中的定时器产生的PPI为例进行说明。该处理器可以包括一个或者多个核，这一个或者多个核中的定时器均可以用于产生该PPI，这一个或者多个核上可以运行有一个或者多个guest OS。为便于描述，下文中以该处理器的第一核包括第一PE和第一定时器，第一PE上运行有第一guest OS，由第一定时器产生该PPI为例进行说明。
具体的，该MBIG可用于检测和采样该处理器的核中包括的一个或者多个定时器的中断引脚，这一个或者多个定时器包括第一定时器，从而当第一定时器产生该PPI时，该MBIG可以通过第一定时器的中断引脚获取到该PPI，该PPI的形式可以是电平中断。之后，该MBIG可以根据该PPI对应的第一中断产生标识确定第一中断信息，并根据第一中断信息将该PPI转换为消息信号中断，第一中断产生标识可以为产生该PPI的第一定时器的标识。
可选的，该MBIG根据该PPI对应的第一中断产生标识确定第一中断信息的过程可以为：根据中断配置信息确定第一中断产生标识对应的第一中断信息，该中断配置信息用于指示多个中断产生标识与多个中断信息之间的对应关系，该多个中断产生标识包括第一中断产生标识。
其中，该多个中断产生标识可以为该处理器中包括的多个定时器的中断号，从而第一中断产生标识可以为第一定时器的中断号。在一种示例中，该多个定时器中的每个定时器的中断号可以为该定时器的中断引脚标识，从而第一定时器的中断号可以为第一定时器的中断引脚标识。
另外，该多个中断信息中的每个中断信息可以包括中断向量和指定地址，第一中断信息可以包括第一中断向量和第一指定地址，第一中断向量可以用于标识该PPI中断，第一指定地址可以是特定寄存器的地址。在该中断配置信息中，该多个中断产生标识与该多个中断信息之间可以是一一对应的关系。
在一种可能实施例中，当该中断配置信息用于指示该多个定时器的中断引脚标识与该 多个中断信息之间的对应关系时，该MBIG可以根据第一定时器的中断引脚标识，从该中断配置信息中获取与第一定时器的中断引脚标识对应的第一中断信息，第一中断信息包括第一中断向量和第一指定地址。之后，该MBIG可以将第一中断向量作为数据写入第一指定地址对应的中断生成寄存器中，以产生该PPI的消息信号中断，即将该PPI转换为消息信号中断。
需要说明的是，该中断配置信息可以是事先配置的，比如，该虚拟化系统中的VMM可以事先确定该中断配置信息，并将该中断配置信息配置给该MBIG，本申请实施例对此不作具体限制。
S202：ITS组件根据该消息信号中断确定第一vPE。
其中，该处理器可以包括一个或者多个核，每个核中包括一个PE，从而该处理器可以包括一个或者多个PE，每个PE可以虚拟出一个或者多个vPE，从而该处理器可以包括多个vPE，该多个vPE中的每个vPE可以用于运行一个guest OS。第一vPE可以是上述第一PE的vPE，第一vPE可以用于运行第一guest OS。
另外，该消息信号中断中可以包括第一中断向量，该ITS组件可以根据第一预设关系中确定第一中断向量对应的第一vPE，第一预设关系用于指示该多个中断向量与多个vPE之间的对应关系，该多个中断向量包括第一中断向量。在一种示例中，第一预设关系可以包括该多个中断向量中每个中断向量对应的vPE的标识，一个vPE的标识可以用于指示该vPE，从而该ITS组件获取到第一vPE的标识，即确定第一中断向量对应的第一vPE。
具体的，该ITS组件中可以包括翻译器(translator)，该翻译器可用于捕捉该MBIG写中断生成寄存器所产生的消息信号中断，从而在该MBIG将第一中断向量写入第一指定地址对应的中断生成寄存器产生消息信号中断时，该ITS组件中的翻译器可以捕捉到该消息信号中断；该ITS组件可以根据该消息信号中断中的第一中断信息查询第一预设关系，以从第一预设关系中获取第一中断向量对应的vPE的标识(即第一vPE的标识)。之后，该ITS组件可以向GIC发送第一vPE的标识，以使该GIC可以根据第一vPE的标识确定第一vPE。
需要说明的是，第一预设关系可以是事先设置的，比如，第一预设关系由VMM事先设置并配置给该ITS组件，本申请实施例对此不作具体限制。
进一步的，该GIC包括多个重分发器(如图3所示)，该多个重分发器与该处理器的多个核一一对应，该ITS组件在确定第一vPE时，还可以确定第一vPE对应的第一重分发器，第一重分发器为第一核对应的重分发器，第一vPE是第一核中的第一PE的vPE，从而第一vPE也对应第一重分发器。具体的，该ITS组件可以根据第二预设对应关系确定第一vPE对应的第一重分发器，第二预设对应关系用于指示多个vPE与多个重分发器之间的对应关系，该多个vPE包括第一vPE。在一种示例中，第二预设对应关系可以包括该多个vPE的标识，以及每个vPE的标识对应的重分发器的标识，一个重分发器的标识可以用于指示该重分发器，从而该ITS组件可以根据第一vPE的标识，从第二预设对应关系中获取第一vPE的标识对应的重分发器的标识，该对应的重分发器的标识就是第一重分发器的标识，即确定第一vPE对应的第一重分发器。之后，该ITS组件可以将第一vPE的标识发送给该GIC中的第一重分发器。
可选的，该ITS组件还可以将该PPI的配置信息发送给该GIC，比如，该配置信息可 以包括该PPI的优先级和该PPI的使能状态等。此外，当该虚拟化系统中还包括其他待处理PPI时，该ITS组件还可以将待处理PPI的列表信息和配置信息等一起发送给该GIC。进一步的，若该其他待处理PPI中包括需要第一重分发器分发的一个或者多个PPI时，该ITS组件可以将对应的待处理PPI的列表信息和配置信息一起发送给第一重分发器。本申请实施例对此不作具体限制。
S203：该GIC根据第一vPE将该消息信号中断上报给第一guest OS。
在该ITS组件确定第一vPE之后，该中断控制器可以通过虚拟接口将该消息信号中断直接上报给第一guest OS，这样就完成了该PPI的上报。当第一guest OS接收到该消息信号中断时，第一guest OS可以处理该消息信号中断，即第一guest OS可以处理该PPI。比如，当该PPI的优先级高于第一guest OS当前执行的任务的优先级时，第一guest OS可以暂停该任务并转去处理该PPI。
进一步的，该GIC包括多个重分发器，第一vPE对应该多个重分发器中的第一重分发器，可以由第一重分发器通过第一vPE对应的虚拟接口将该消息信号中断直接上报给第一guest OS。
可选的，当该ITS组件将该PPI的配置信息发送给第一重分发器时，若该配置信息中的使能状态为有效(或处于活跃状态(active))，第一重分发器可以向第一guest OS上报该消息信号中断，若该配置信息中的使能状态为无效，第一重分发器可以不上报该消息信号中断。进一步的，当该ITS组件将待处理PPI的列表信息和配置信息等均发送给第一重分发器时，对于列表信息中的每个待处理PPI，第一重分发器均可以根据每个待处理PPI的使能状态选择上报或者不上报该PPI。当多个待处理PPI的优先级不同时，第一重分发器还可以按照该多个待处理PPI的优先级的顺序，依次处理该多个待处理PPI。
需要说明的是，本申请实施例提供的中断上报方法，可用于将一个核的PPI上报给该核上运行的guest OS，也可以用于将一个核的PPI上报给另一个核上运行的guest OS。示例性的，核1(或称第一处理器核)中的定时器产生的PPI可以通过本申请的方法上报至核1(或称第一处理器核)中的vPE上运行的guest OS；或者，核2(或称第二处理器核)中的定时器产生的PPI可以通过本申请的方法上报至核1(或称第一处理器核)中的vPE上运行的guest OS，本申请实施例对此不作具体限制。
在本申请实施例中，对于虚拟化系统中产生的PPI，该MBIG可以在获取到该PPI时，将该PPI转换为消息信号中断，该ITS组件可以根据该消息信号中断确定该处理器中用于运行第一guest OS的第一vPE，从而该GIC可以根据第一vPE将该消息信号中断直接上报给第一guest OS，在此过程中该处理器无需在VMM状态与guest OS状态之间进行切换，从而提高了PPI的处理速率、同时也保证了guest OS状态下定时器的性能。尤其是对于核中的定时器产生的PPI，能够大大提高该PPI的处理速率。
上述主要从虚拟化系统的角度对本申请实施例提供的方案进行了介绍。可以理解的是，该虚拟化系统为了实现上述功能，其包含了执行各个功能相应的硬件结构和/或软件模块。本领域技术人员应该很容易意识到，结合本文中所公开的实施例描述的各示例的设备及算法步骤，本申请能够以硬件或硬件和计算机软件的结合形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种 实现不应认为超出本发明的范围。
本申请实施例可以根据上述方法示例对该虚拟化系统进行功能模块的划分，例如，可以对应各个功能划分各个功能模块，也可以将两个或两个以上的功能集成在一个处理模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。需要说明的是，本申请实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。
在采用对应各个功能划分各个功能模块的情况下，图6示出了上述实施例中所涉及的中断上报装置的一种可能的结构示意图，该装置可以包括：消息中断发生器301、中断转换服务组件302和中断控制器303，该中断控制器303可以包括多个重分发器。其中，消息中断发生器301可用于支持该装置执行上述方法实施例中S201；中断转换服务组件302可用于支持该装置执行上述方法实施例中的S202；中断控制器303可用于支持该装置执行上述方法实施例中的S203。
需要说明的是，上述方法实施例涉及的各步骤的所有相关内容均可以援引到对应功能模块的功能描述，在此不再赘述。
在本申请的另一实施例中，还提供一种虚拟化系统，该虚拟化系统包括运行有客户操作系统的处理器、以及上文所提供的中断上报装置；其中，该中断上报装置可以用于执行上文所提供的中断上报方法中的步骤。可选的，该处理器的核中可以包括处理引擎PE和定时器，该中断上报装置可以通过上文所提供的方法将该定时器产生的中断上报至该处理器上的客户操作系统。
在本申请实施例中，对于虚拟化系统中产生的PPI，该消息中断发生器可以在获取到该PPI时，将该PPI转换为消息信号中断，该中断转换服务组件可以根据该消息信号中断确定该处理器中用于运行该客户操作系统的vPE，从而该中断控制器可以根据该vPE将该消息信号中断直接上报给该客户操作系统，在此过程中该处理器无需在VMM状态与guest OS状态之间进行切换，从而提高了PPI的处理速率、同时也保证了guest OS状态下定时器的性能。尤其是对于核中的定时器产生的PPI，能够大大提高该PPI的处理速率。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置、虚拟化系统和方法，可以通过其它的方式实现。例如，以上所描述的中断上报装置的实施例仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种功能性的划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个装置，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是一个物理单元或多个物理单元，即可以位于一个地方，或者也可以分布到多个不同地方。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
最后应说明的是：以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种中断上报装置，其特征在于，应用于虚拟化系统中，所述虚拟化系统包括处理器，所述装置包括：
    消息中断发生器，用于在获取到私有外设中断PPI时，将所述PPI转换为消息信号中断；
    中断转换服务组件，用于根据所述消息信号中断确定虚拟处理引擎vPE；
    中断控制器，用于根据所述vPE将所述消息信号中断上报给所述处理器上运行的客户操作系统。
  2. 根据权利要求1所述的装置，其特征在于，所述消息信号中断包括中断向量，所述中断转换服务组件用于：
    根据第一预设关系确定与所述中断向量对应的所述vPE，所述第一预设关系用于指示多个中断向量与多个vPE之间的对应关系，所述多个中断向量包括所述中断向量。
  3. 根据权利要求1或2所述的装置，其特征在于，所述中断控制器包括多个重分发器；
    所述中断转换服务组件，还用于从所述多个重分发器中确定与所述vPE对应的重分发器；
    所述重分发器，用于通过与所述vPE对应的接口将所述消息信号中断上报给所述客户操作系统。
  4. 根据权利要求3所述的装置，其特征在于，所述中断转换服务组件还用于：
    根据第二预设关系确定与所述vPE对应的所述重分发器，所述第二预设关系用于指示多个vPE与所述多个重分发器之间的对应关系，所述多个vPE包括所述vPE。
  5. 根据权利要求1-4任一所述的装置，其特征在于，所述处理器包括第一处理器核，所述第一处理器核包括处理引擎PE，所述vPE是所述PE虚拟的vPE。
  6. 根据权利要求5所述的装置，其特征在于，所述第一处理器核中还包括定时器，所述PPI是所述定时器产生的中断。
  7. 根据权利要求5所述的装置，其特征在于，所述处理器还包括第二处理器核，所述第二处理器核包括定时器，所述PPI是所述定时器产生的中断。
  8. 根据权利要求6或7所述的装置，其特征在于，所述消息中断发生器用于：
    根据所述PPI对应的中断产生标识确定中断信息，所述中断产生标识为所述定时器的标识；
    根据所述中断信息将所述PPI转换为消息信号中断。
  9. 根据权利要求8所述的装置，其特征在于，所述消息中断发生器用于：
    根据中断配置信息确定与所述中断产生标识对应的所述中断信息，所述中断配置信息用于指示多个中断产生标识与多个中断信息之间的对应关系，所述多个中断产生标识包括所述中断产生标识。
  10. 一种中断上报方法，其特征在于，应用于虚拟化系统中，所述虚拟化系统包括处理器、消息中断发生器、中断转换服务组件和中断控制器，所述方法包括：
    所述消息中断发生器在获取到私有外设中断PPI时，将所述PPI转换为消息信号中断；
    所述中断转换服务组件根据所述消息信号中断确定虚拟处理引擎vPE；
    所述中断控制器根据所述vPE将所述消息信号中断上报给所述处理器上运行的客户操作系统。
  11. 根据权利要求10所述的方法，其特征在于，所述消息信号中断包括中断向量，所述中断转换服务组件根据所述消息信号中断确定vPE，包括：
    所述中断转换服务组件根据第一预设关系确定与所述中断向量对应的所述vPE，所述第一预设关系用于指示多个中断向量与多个vPE之间的对应关系，所述多个中断向量包括所述中断向量。
  12. 根据权利要求10或11所述的方法，其特征在于，所述中断控制器包括多个重分发器，所述方法还包括：
    所述中断转换服务组件从所述多个重分发器中确定与所述vPE对应的重分发器；
    相应的，所述中断控制器根据所述vPE将所述消息信号中断上报给所述客户操作系统，包括：
    所述重分发器根据与所述vPE对应的接口将所述消息信号中断上报给所述客户操作系统。
  13. 根据权利要求12所述的方法，其特征在于，所述方法还包括：
    所述中断转换服务组件根据第二预设关系确定与所述vPE对应的所述重分发器，所述第二预设关系用于指示多个vPE与所述多个重分发器之间的对应关系，所述多个vPE包括所述vPE。
  14. 根据权利要求10-13任一所述的方法，其特征在于，所述处理器包括第一处理器核，所述第一处理器核包括处理引擎PE，所述vPE是所述PE虚拟的vPE。
  15. 根据权利要求14所述的方法，其特征在于，所述第一处理器包括处理器核，所述处理器核还包括定时器，所述PPI是所述定时器产生的中断。
  16. 根据权利要求14所述的方法，其特征在于，所述处理器还包括第二处理器核，所述第二处理器核包括定时器，所述PPI是所述定时器产生的中断。
  17. 根据权利要求15或16所述的方法，其特征在于，所述消息中断发生器将所述PPI转换为消息信号中断，包括：
    根据所述PPI对应的中断产生标识确定中断信息，所述中断产生标识为所述定时器的标识；
    根据所述中断信息将所述PPI转换为消息信号中断。
  18. 根据权利要求17所述的方法，其特征在于，所述消息中断发生器根据所述PPI对应的中断产生标识确定中断信息，包括：
    根据中断配置信息确定与所述中断产生标识对应的所述中断信息，所述中断配置信息用于指示多个中断产生标识与多个中断信息之间的对应关系，所述多个中断产生标识包括所述中断产生标识。
  19. 一种虚拟化系统，其特征在于，所述虚拟化系统包括运行有客户操作系统的处理器、以及包括权利要求1-9任一项所述的中断上报装置。
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CN101004726A (zh) * 2005-12-30 2007-07-25 英特尔公司 直接传送中断到虚拟处理器
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