WO2022151985A1 - 基于虚拟内存的数据存储方法、装置、设备及存储介质 - Google Patents

基于虚拟内存的数据存储方法、装置、设备及存储介质 Download PDF

Info

Publication number
WO2022151985A1
WO2022151985A1 PCT/CN2021/143003 CN2021143003W WO2022151985A1 WO 2022151985 A1 WO2022151985 A1 WO 2022151985A1 CN 2021143003 W CN2021143003 W CN 2021143003W WO 2022151985 A1 WO2022151985 A1 WO 2022151985A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
memory
address
physical address
virtual memory
Prior art date
Application number
PCT/CN2021/143003
Other languages
English (en)
French (fr)
Inventor
刘同强
王朝辉
周玉龙
Original Assignee
苏州浪潮智能科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 苏州浪潮智能科技有限公司 filed Critical 苏州浪潮智能科技有限公司
Publication of WO2022151985A1 publication Critical patent/WO2022151985A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G06F9/5077—Logical partitioning of resources; Management or configuration of virtualized resources

Definitions

  • the present application relates to the field of computer memory management, and more particularly, to a virtual memory-based data storage method, apparatus, device, and storage medium.
  • Virtual memory is a specific technique for computer memory management. It makes the application think that it has contiguous available memory, when in fact it is usually divided into multiple physical memory fragments, and some are temporarily stored on external disk storage for data exchange when needed. At present, most operating systems use virtual memory technology, such as: “virtual memory” of Windows system, "swap space” of Linux, etc. However, traditional virtual memory uses disks as virtual memory media, resulting in the problems of occupying a large amount of disk space and slow access speed.
  • the purpose of this application is to provide a data storage method, device, device and storage medium based on virtual memory, so as to reduce the disk space occupied by the virtual memory and improve the access speed of the virtual memory.
  • the present application provides a virtual memory-based data storage method, comprising:
  • the first logical address is within the virtual memory range, determining a first physical address corresponding to the first logical address through an address mapping mechanism, where the first physical address is the physical address of the extended board memory;
  • the target data is stored in the extended board memory by using the first physical address.
  • the data storage method further includes:
  • the target data is compressed by a lossless compression algorithm to obtain compressed data
  • using the first physical address to store the target data in the extended on-board memory includes: using the first physical address to store the compressed data in the extended on-board memory.
  • the method further includes:
  • the capacity of the compressed data is smaller than the capacity of the target data, use the first physical address to store the compressed data in the extended board memory, if the capacity of the compressed data is not less than the capacity of the target data capacity, and using the first physical address to store the target data in the extended board memory.
  • the method further includes:
  • the remaining capacity of the virtual memory is updated according to the capacity of the compressed data or the target data.
  • the data storage method further includes:
  • the step of determining the first physical address corresponding to the first logical address through the address mapping mechanism is performed;
  • a second physical address corresponding to the first logical address is determined through an address mapping mechanism, and the target data is stored to a location based on the second physical address.
  • Disk the second physical address is the physical address of the disk.
  • the data storage method further includes:
  • a third physical address corresponding to the second logical address is determined through an address mapping mechanism, a recycling operation is performed on the data stored under the third physical address, and a The remaining capacity of virtual memory is updated.
  • the data storage method further includes:
  • the fourth physical address corresponding to the third logical address and the capacity of the data to be read are determined through an address mapping mechanism, and based on the fourth physical address and the to-be-read data Fetch the capacity of the data to perform the data read operation.
  • the present application further provides a virtual memory-based data storage device, comprising:
  • a data determination module configured to determine target data to be stored corresponding to the memory allocation operation when it is detected that the operating system performs the memory allocation operation
  • a first logical address determination module configured to determine a first logical address allocated by the operating system corresponding to the memory allocation operation when it is detected that the operating system performs the memory allocation operation
  • a first physical address determination module configured to determine a first physical address corresponding to the first logical address through an address mapping mechanism when the first logical address is within the virtual memory range, where the first physical address is an extension The physical address of the board memory;
  • the first data storage module is used for storing the target data in the extended board memory by using the first physical address.
  • the application further provides an electronic device, comprising:
  • the processor is configured to implement the steps of the above virtual memory-based data storage method when executing the computer program.
  • the present application further provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned virtual memory-based data storage method are implemented. .
  • a virtual memory-based data storage method includes: if it is detected that an operating system performs an allocation memory operation, determining target data to be stored corresponding to the memory allocation operation and the operation The first logical address allocated by the system; if the first logical address is within the virtual memory range, the first physical address corresponding to the first logical address is determined through the address mapping mechanism, and the first physical address is the physical address of the extended board memory ; Use the first physical address to store the target data in the extended board memory.
  • FIG. 1 is a schematic flowchart of a virtual memory-based data storage method disclosed in an embodiment of the present application
  • FIG. 2 is a schematic flowchart of another virtual memory-based data storage method disclosed in an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a data storage system disclosed in an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a virtual memory-based data storage device disclosed in an embodiment of the present application.
  • FIG. 5 is a schematic diagram of an electronic device disclosed in an embodiment of the present application.
  • Step 1 The central processing unit accesses the logical address of the main memory, decomposes the logical address into a group number a and an intra-group address b, and performs address conversion on the group number a, that is, the logical group number a is used as an index, and the address conversion table is checked, to determine whether the set of information is stored in main memory.
  • Step 2 If the group number a is already in the main memory, go to step 4; if the group number a is not in the main memory, check whether there is a free area in the main memory, if there is no free area in the main memory, then Transfer a temporarily unused group out to auxiliary storage (disk), so that this group of information can be transferred into main memory.
  • auxiliary storage disk
  • Step 3 Read the desired group from the auxiliary storage and send it to the free area of the main memory, and then register the idle physical group number a and logical group number a in the address conversion table.
  • Step 4 Read out the physical group number a corresponding to the logical group number a from the address conversion table.
  • Step 5 Obtain the physical address from the physical group number a and the byte address b in the group.
  • Step 6 Access necessary information from the main memory according to the physical address.
  • the existing solution uses a disk as a virtual memory medium, which will occupy disk space.
  • the access speed is slow and the efficiency is low. Therefore, the embodiments of the present application disclose a data storage method, device, device and storage medium based on virtual memory, so as to reduce the disk space occupied by the virtual memory and improve the access speed of the virtual memory.
  • FIG. 1 a schematic flowchart of a virtual memory-based data storage method provided by an embodiment of the present application; the data storage method includes:
  • the operating system when the operating system stores the target data in the virtual memory, it needs to perform a memory allocation operation, so as to allocate a logical address to the target data to be stored.
  • the logical address allocated by the operating system to the target data is called the first logical address, to distinguish it from other logical addresses.
  • the solution can detect the operation, thereby obtaining the target data to be stored and the first logical address.
  • a system patch can be set in the operating system, and the system patch is used to detect the corresponding logical address and forward data when the operating system performs an operation of allocating memory, performing an operation of reclaiming memory, and performing an operation of reading memory. Therefore, in this solution, after the operating system performs the memory allocation operation, the system patch will detect the first logical address and the target data.
  • the system patch After the system patch detects the first logical address, it also needs to determine whether the first logical address is within the virtual memory range. If the first logical address is not within the virtual memory range, it means that it does not need to be stored in the virtual memory. , if the first logical address is within the virtual memory range, it means that the target data needs to be stored in the virtual memory. At this time, the corresponding physical address needs to be allocated for the target data. In order to distinguish, the physical address allocated for the target data will be is called the first physical address.
  • This scheme mainly uses the address mapping mechanism to determine the first physical address corresponding to the target data, and in order to reduce the virtual memory occupied disk space and improve the virtual memory access speed, it is specifically necessary to use an extended memory board to replace the disk. Therefore, this scheme
  • the first physical address allocated by the address mapping mechanism in the target data is the physical address of the board memory, so that the target data can be stored in the extended board memory without occupying disk space and improving the access speed.
  • the address mapping mechanism allocates the corresponding first physical address to the first logical address, the mapping relationship between the first logical address and the first physical address also needs to be saved, so that data can be searched through the mapping relationship later.
  • the extended board memory is used as the storage medium of the virtual memory, and the data is directly stored in the board memory, thereby avoiding occupying disk space and improving the access speed.
  • FIG. 2 a schematic flowchart of another virtual memory-based data storage method provided by an embodiment of the present application; the data storage method includes:
  • the system patch when it detects that the first logical address is within the virtual memory range, it can forward the target data to a lossless compression algorithm, and use the lossless compression algorithm to compress the target data. Compression is performed to obtain compressed data; the lossless compression algorithm may adopt a general lossless compression or a collection of multiple lossless compression algorithms, specifically: LZ77 algorithm, LZSS algorithm, compression algorithm based on Huffman coding principle, and so on. Referring to FIG.
  • a schematic structural diagram of a data storage system provided in an embodiment of the present application includes a system patch, a compression algorithm, and an address mapping mechanism, wherein after the system patch detects the first logical address of the target data, the target data is sent to The compression algorithm obtains the compressed data, and sends the compressed data and size to the address mapping mechanism, which allocates and stores physical addresses through the address mapping mechanism.
  • the present application also needs to update the remaining capacity of the virtual memory according to the capacity of the compressed data or target data.
  • the capacity of the compressed data or the size of the target data can be fed back to the system patch through a lossless compression algorithm, and the remaining memory space of the virtual operating system and the virtual memory size parameters can be updated through the system patch.
  • the operating system operates the memory data in the unit of page (4K).
  • the data is compressed in the unit of page, and the compressed data is stored correspondingly according to the storage order when stored, and the starting address plus the compression size is used to store the corresponding storage.
  • the memory management of the memory board adopts the minimum memory read unit as the management granularity.
  • this solution also needs to determine whether the remaining capacity of the virtual memory is greater than the capacity of the target data; If the remaining capacity of the memory is greater than the capacity of the target data, then perform the step of determining the first physical address corresponding to the first logical address through the address mapping mechanism; if the remaining capacity of the virtual memory is not greater than the capacity of the target data, then determine through the address mapping mechanism A second physical address corresponding to the first logical address, and the target data is stored to the disk based on the second physical address.
  • the remaining capacity of the virtual memory is greater than the capacity of the target data, it means that there is still space left in the memory of the board to store the target data, and the subsequent steps of allocating the first logical address and data storage can be continued; if the virtual memory The remaining capacity of the target data is not greater than the capacity of the target data, indicating that the target data cannot be stored in the on-board memory. At this time, the physical address of the disk can be allocated to the target data to store the target data to the disk to avoid the problem of storage failure.
  • this solution detects that the operating system performs a memory recovery operation or a data read operation, it also needs to perform corresponding management operations on the data, including:
  • the present application also needs to determine the second logical address corresponding to the reclaiming memory operation; if the second logical address is within the virtual memory range, then determine the relationship with the second logical address through the address mapping mechanism. For the third physical address corresponding to the address, a recovery operation is performed on the data stored under the third physical address, and the remaining capacity of the virtual memory is updated.
  • the system patch when the operating system performs the reclaiming memory operation, after the system patch detects the allocated second logical address, if the address range is within the virtual memory range, the system patch needs to forward the second logical address to the address mapping mechanism.
  • the address mapping mechanism determines the third physical address corresponding to the second logical address according to the mapping relationship between the logical address and the physical address, so as to perform a recycling operation on the data stored in the third physical address. After performing the recycling operation, the system The patch also needs to update the virtual operating system memory remaining space and virtual memory size parameters.
  • the present application also needs to determine the third logical address corresponding to the data read operation; if the third logical address is within the virtual memory range, then the address mapping mechanism is used to determine and the third logical address.
  • the data read operation is performed based on the fourth physical address corresponding to the three logical addresses and the capacity of the data to be read.
  • the system patch in this application also needs to detect the allocated third logical address. If the address range is within the virtual memory range, the system patch will forward the address to the address map.
  • the address mapping mechanism obtains the fourth physical address and size corresponding to the third logical address through retrieval, and reads the data.
  • the physical address obtained by the address mapping mechanism is the physical address of the on-board memory, and the corresponding physical address is executed in the on-board memory. If the data is stored in the disk, the physical address obtained by the address mapping mechanism is the physical address of the disk, and the corresponding data recovery or data read operation is performed in the disk.
  • the solution detects that the operation performed by the operating system is a CPU-based memory access operation, and of course it can also be a memory access operation of processors in other fields, which is not specifically limited here.
  • this scheme discloses a data storage method based on virtual memory.
  • the storage medium of virtual memory is the board memory, and the method of compressing the data and storing it in the board memory through this scheme, and Compared with the traditional way of using a disk as a virtual memory medium, the disk space occupied by the data is reduced, the disk access request is reduced, and the data access efficiency is improved.
  • the data storage device, device, and medium provided by the embodiments of the present application.
  • the data storage device, device, and medium described below may refer to each other with the data storage method described above.
  • FIG. 4 a schematic structural diagram of a virtual memory-based data storage device provided by an embodiment of the present application; the device includes:
  • the data determination module 100 is configured to determine target data to be stored corresponding to the memory allocation operation when it is detected that the operating system performs the memory allocation operation;
  • the first logical address determination module 200 is configured to determine the first logical address allocated by the operating system corresponding to the memory allocation operation when it is detected that the operating system performs the memory allocation operation;
  • a first physical address determination module 300 configured to determine a first physical address corresponding to the first logical address through an address mapping mechanism when the first logical address is within the virtual memory range, where the first physical address is The physical address of the extended board memory;
  • the first data storage module 400 is configured to use the first physical address to store the target data in the extended board memory.
  • the device also includes:
  • a compression module configured to compress the target data through a lossless compression algorithm to obtain compressed data when the first logical address is within the virtual memory range;
  • the first data storage module is specifically configured to: use the first physical address to store the compressed data in the extended board memory.
  • the device also includes:
  • a first judgment module for judging whether the capacity of the compressed data is less than the capacity of the target data
  • the first data storage module is specifically configured to: when the capacity of the compressed data is smaller than the capacity of the target data, use the first physical address to store the compressed data in the extended board memory; When the capacity of the compressed data is not less than the capacity of the target data, the target data is stored in the extended board memory by using the first physical address.
  • the device also includes:
  • the updating module is configured to update the remaining capacity of the virtual memory according to the capacity of the compressed data or the target data after storing the compressed data or the target data in the expanded board memory.
  • the device also includes:
  • the second judging module is used to judge whether the remaining capacity of the virtual memory is greater than the capacity of the target data; if the remaining capacity of the virtual memory is greater than the capacity of the target data, the first physical address determining module is triggered; The remaining capacity is not greater than the capacity of the target data, then trigger the second physical address determination module;
  • a second physical address determination module configured to determine a second physical address corresponding to the first logical address through an address mapping mechanism; the second physical address is the physical address of the disk;
  • a second data storage module configured to store the target data to a disk based on the second physical address.
  • the device also includes:
  • a second logical address determining module configured to determine a second logical address corresponding to the reclaiming memory operation when it is detected that the operating system performs the reclaiming memory operation
  • a data recycling module configured to determine a third physical address corresponding to the second logical address through an address mapping mechanism when the second logical address is in the virtual memory range, Perform a reclamation operation and update the remaining capacity of virtual memory.
  • the device also includes:
  • a third logical address determination module configured to determine a third logical address corresponding to the data read operation when it is detected that the operating system performs the data read operation
  • a data reading module configured to determine a fourth physical address corresponding to the third logical address and the capacity of the data to be read through an address mapping mechanism when the third logical address is within the virtual memory range, and based on the The fourth physical address and the capacity of the data to be read perform a data read operation.
  • FIG. 5 it is a schematic diagram of an electronic device disclosed in an embodiment of the application, and the device includes:
  • memory 11 for storing computer programs
  • the processor 12 is configured to implement the steps of the virtual memory-based data storage method described in any of the foregoing method embodiments when executing the computer program.
  • the device may be a PC (Personal Computer, personal computer), or may be a terminal device such as a smart phone, a tablet computer, a palmtop computer, and a portable computer.
  • PC Personal Computer
  • terminal device such as a smart phone, a tablet computer, a palmtop computer, and a portable computer.
  • the device may include a memory 11 , a processor 12 and a bus 13 .
  • the memory 11 includes at least one type of readable storage medium, including flash memory, hard disk, multimedia card, card-type memory (eg, SD or DX memory, etc.), magnetic memory, magnetic disk, optical disk, and the like.
  • the memory 11 may in some embodiments be an internal storage unit of the device, such as a hard disk of the device. In other embodiments, the memory 11 may also be an external storage device of the device, such as a plug-in hard disk equipped on the device, a Smart Media Card (SMC), a Secure Digital (SD) card, and a flash memory card. (Flash Card) etc. Further, the memory 11 may also include both an internal storage unit of the device and an external storage device.
  • the memory 11 can be used not only to store application software installed in the device and various types of data, such as program codes for executing data storage methods, etc., but also to temporarily store data that has been output or will be output.
  • the processor 12 may be a central processing unit (Central Processing Unit, CPU), controller, microcontroller, microprocessor or other data processing chip in some embodiments, for running the program code or processing stored in the memory 11 Data, such as program code that executes data storage methods, etc.
  • CPU Central Processing Unit
  • controller microcontroller
  • microprocessor or other data processing chip in some embodiments, for running the program code or processing stored in the memory 11 Data, such as program code that executes data storage methods, etc.
  • the bus 13 may be a peripheral component interconnect (PCI for short) bus or an extended industry standard architecture (EISA for short) bus or the like.
  • PCI peripheral component interconnect
  • EISA extended industry standard architecture
  • the bus can be divided into address bus, data bus, control bus and so on. For ease of presentation, only one thick line is used in FIG. 5, but it does not mean that there is only one bus or one type of bus.
  • the device may also include a network interface 14, and the network interface 14 may optionally include a wired interface and/or a wireless interface (such as a WI-FI interface, a Bluetooth interface, etc.), which is usually used between the device and other electronic devices Establish a communication connection.
  • a network interface 14 may optionally include a wired interface and/or a wireless interface (such as a WI-FI interface, a Bluetooth interface, etc.), which is usually used between the device and other electronic devices Establish a communication connection.
  • the device may further include a user interface 15, the user interface 15 may include a display, an input unit such as a keyboard, and the optional user interface 15 may also include a standard wired interface and a wireless interface.
  • the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, an OLED (Organic Light-Emitting Diode, organic light-emitting diode) touch device, and the like.
  • the display may also be appropriately referred to as a display screen or a display unit, for displaying information processed in the device and for displaying a visual user interface.
  • FIG. 5 only shows the device with components 11 to 15. Those skilled in the art can understand that the structure shown in FIG. 5 does not constitute a limitation to the device, and may include fewer or more components than those shown. Either some components are combined, or different component arrangements.
  • the embodiments of the present application further disclose a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the virtual memory-based storage medium described in any of the foregoing method embodiments is implemented.
  • the steps of the data storage method are not limited to, but not limited to, but not limited to, but not limited to, but not limited to, but not limited to, but not limited to, but not limited to a computer program.
  • the storage medium may include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other various storage media that can store program codes medium.
  • U disk mobile hard disk
  • read-only memory Read-Only Memory
  • RAM random access memory
  • magnetic disk or optical disk and other various storage media that can store program codes medium.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

本申请公开了一种基于虚拟内存的数据存储方法、装置、设备及存储介质；本方案包括：若检测到操作系统执行分配内存操作，则确定与分配内存操作对应的待存储的目标数据以及操作系统分配的第一逻辑地址；若第一逻辑地址在虚拟内存范围内，则通过地址映射机制确定与第一逻辑地址对应的第一物理地址，第一物理地址为扩展的板卡内存的物理地址；利用第一物理地址将目标数据存储至扩展的板卡内存。可见，本方案基于虚拟内存进行数据存储时，使用扩展的板卡内存作为虚拟内存的存储介质，直接将数据存储至板卡内存中，从而避免占用磁盘空间，提高访问速度。

Description

基于虚拟内存的数据存储方法、装置、设备及存储介质
本申请要求在2021年01月18日提交中国专利局、申请号为202110063607.4、发明名称为“基于虚拟内存的数据存储方法、装置、设备及存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机内存管理领域，更具体地说，涉及一种基于虚拟内存的数据存储方法、装置、设备及存储介质。
背景技术
虚拟内存是计算机内存管理的一种特定技术。它使得应用程序认为它拥有连续的可用的内存，而实际上，它通常是被分隔成多个物理内存碎片，还有部分暂时存储在外部磁盘存储器上，在需要时进行数据交换。目前，大多数操作系统都使用了虚拟内存技术，例如：Windows系统的“虚拟内存”，Linux的“交换空间”等。但是，传统的虚拟内存均使用磁盘作为虚拟内存介质，导致出现占用大量磁盘空间、访问速度慢的问题。
发明内容
本申请的目的在于提供一种基于虚拟内存的数据存储方法、装置、设备及存储介质，以减少虚拟内存占用磁盘空间，提高虚拟内存访问速度。
为实现上述目的，本申请提供一种基于虚拟内存的数据存储方法，包括：
若检测到操作系统执行分配内存操作，则确定与所述分配内存操作对应的待存储的目标数据以及所述操作系统分配的第一逻辑地址；
若所述第一逻辑地址在虚拟内存范围内，则通过地址映射机制确定与所述第一逻辑地址对应的第一物理地址，所述第一物理地址为扩展的板卡内存的物理地址；
利用所述第一物理地址将所述目标数据存储至扩展的板卡内存。
其中，若第一逻辑地址在虚拟内存范围内，则该数据存储方法还包括：
通过无损压缩算法对所述目标数据进行压缩，得到压缩数据；
相应的，所述利用所述第一物理地址将所述目标数据存储至扩展的板卡内存包括：利用所述第一物理地址将所述压缩数据存储至扩展的板卡内存。
其中，所述通过地址映射机制确定与所述第一逻辑地址对应的第一物理地址之后，还包括：
判断所述压缩数据的容量是否小于所述目标数据的容量；
若所述压缩数据的容量小于所述目标数据的容量，则利用所述第一物理地址将所述压缩数据存储至扩展的板卡内存，若所述压缩数据的容量不小于所述目标数据的容量，利用所述第一物理地址将所述目标数据存储至扩展的板卡内存。
其中，将所述压缩数据或目标数据存储至扩展的板卡内存之后，还包括：
根据所述压缩数据或目标数据的容量对虚拟内存的剩余容量进行更新。
其中，若第一逻辑地址在虚拟内存范围内，则所述数据存储方法还包括：
判断虚拟内存的剩余容量是否大于所述目标数据的容量；
若虚拟内存的剩余容量大于所述目标数据的容量，则执行所述通过地址映射机制确定与所述第一逻辑地址对应的第一物理地址的步骤；
若虚拟内存的剩余容量不大于所述目标数据的容量，则通过地址映射机制确定与所述第一逻辑地址对应的第二物理地址，并基于所述第二物理地址将所述目标数据存储至磁盘；所述第二物理地址为磁盘的物理地址。
其中，所述数据存储方法还包括：
若检测到操作系统执行回收内存操作，则确定与所述回收内存操作对应的第二逻辑地址；
若所述第二逻辑地址在虚拟内存范围内，则通过地址映射机制确定与所述第二逻辑地址对应的第三物理地址，对所述第三物理地址下存储的数据执行回收操作，并对虚拟内存的剩余容量进行更新。
其中，所述数据存储方法还包括：
若检测到操作系统执行数据读取操作，则确定与所述数据读取操作对应的第三逻辑地址；
若所述第三逻辑地址在虚拟内存范围内，则通过地址映射机制确定与所述第三逻辑地址对应的第四物理地址及待读取数据的容量，基于所述第四物理地址及待读取数据的容量执行数据读取操作。
为实现上述目的，本申请进一步提供一种基于虚拟内存的数据存储装置，包括：
数据确定模块，用于在检测到操作系统执行分配内存操作时，确定与所述分配内存操作对应的待存储的目标数据；
第一逻辑地址确定模块，用于在检测到操作系统执行分配内存操作时，确定与所述分配内存操作对应的所述操作系统分配的第一逻辑地址；
第一物理地址确定模块，用于在所述第一逻辑地址在虚拟内存范围内时，通过地址映射机制确定与所述第一逻辑地址对应的第一物理地址，所述第一物理地址为扩展的板卡内存的物理地址；
第一数据存储模块，用于利用所述第一物理地址将所述目标数据存储至扩展的板卡内存。
为实现上述目的，本申请进一步提供一种电子设备，包括：
存储器，用于存储计算机程序；
处理器，用于执行所述计算机程序时实现上述基于虚拟内存的数据存储方法的步骤。
为实现上述目的，本申请进一步提供一种计算机可读存储介质，所述计算机可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现上述基于虚拟内存的数据存储方法的步骤。
通过以上方案可知，本申请实施例提供的一种基于虚拟内存的数据存储方法，包括：若检测到操作系统执行分配内存操作，则确定与所述分配内存操作对应的待存储的目标数据以及操作系统分配的第一逻辑地址；若第一逻辑地址在虚拟内存范围内，则通过地址映射机制确定与第一逻辑地址对应的第一物理地址，第一物理地址为扩展的板卡内存的物理地址；利用第一物理地址将目标数据存储至扩展的板卡内存。
可见，本方案基于虚拟内存进行数据存储时，使用扩展的板卡内存作为虚拟内存的存储介质，直接将数据存储至板卡内存中，从而避免占用磁盘空 间，提高访问速度；本申请还公开了一种基于虚拟内存的数据存储装置、设备及存储介质，同样能实现上述技术效果。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例公开的一种基于虚拟内存的数据存储方法流程示意图；
图2为本申请实施例公开的另一种基于虚拟内存的数据存储方法流程示意图；
图3为本申请实施例公开的数据存储系统结构示意图；
图4为本申请实施例公开的一种基于虚拟内存的数据存储装置结构示意图；
图5为本申请实施例公开的一种电子设备示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明的是，虚拟存储器是由硬件和操作系统自动实现存储信息调度和管理，它的工作过程包括6个步骤：
步骤1、中央处理器访问主存的逻辑地址，将该逻辑地址分解成组号a和组内地址b，并对组号a进行地址变换，即将逻辑组号a作为索引，查地址变换表，以确定该组信息是否存放在主存内。
步骤2、如该组号a已在主存内，则转而执行步骤4；如果该组号a不在主存内，则检查主存中是否有空闲区，如果主存中没有空闲区，便将某个暂时不用的组调出送往辅存(磁盘)，以便将这组信息调入主存。
步骤3、从辅存读出所要的组，并送到主存空闲区，然后将该空闲的物理组号a和逻辑组号a登录在地址变换表中。
步骤4、从地址变换表读出与逻辑组号a对应的物理组号a。
步骤5、从物理组号a和组内字节地址b得到物理地址。
步骤6、根据物理地址从主存中存取必要的信息。
并且，现有方案使用磁盘作为虚拟内存介质，会占用磁盘空间，在向磁盘发送访问请求时，访问速度慢，效率偏低。因此，本申请实施例公开了一种基于虚拟内存的数据存储方法、装置、设备及存储介质，以减少虚拟内存占用磁盘空间，提高虚拟内存访问速度。
参见图1，本申请实施例提供的一种基于虚拟内存的数据存储方法流程示意图；该数据存储方法包括：
S101、若检测到操作系统执行分配内存操作，则确定与分配内存操作对应的待存储的目标数据以及操作系统分配的第一逻辑地址；
具体的，操作系统在向虚拟内存存储目标数据时，需要执行分配内存操作，从而为待存储的目标数据分配逻辑地址，在本方案中，将操作系统分配给目标数据的逻辑地址称为第一逻辑地址，以与其他逻辑地址区分。
并且，操作系统执行分配内存操作时，本方案即可检测出该操作，从而获得待存储的目标数据及第一逻辑地址。本方案可在操作系统中设置系统补丁，该系统补丁用于在操作系统执行分配内存操作、执行回收内存操作、执行读取内存操作时，检测对应的逻辑地址及进行数据的转发。因此在本方案中，操作系统执行分配内存操作后，系统补丁即会检测出该第一逻辑地址及目标数据。
S102、若第一逻辑地址在虚拟内存范围内，则通过地址映射机制确定与第一逻辑地址对应的第一物理地址，该第一物理地址为扩展的板卡内存的物理地址；
S103、利用第一物理地址将目标数据存储至扩展的板卡内存。
需要说明的是，系统补丁检测出第一逻辑地址之后，还需要判断该第一逻辑地址是否在虚拟内存范围内，如果第一逻辑地址不在该虚拟内存范围内，则说明不需要存储至虚拟内存，如果第一逻辑地址在该虚拟内存范围内，说明需要将目标数据存储至虚拟内存，此时，便需要为目标数据分配对应的物理地址，在此为了区分，将为目标数据分配的物理地址称为第一物理地址。
本方案主要通过地址映射机制来确定与目标数据对应的第一物理地址，并且，为了减少虚拟内存占用磁盘空间，提高虚拟内存访问速度，具体需要采用扩展内存板卡方式代替磁盘，因此，本方案中的地址映射机制为目标数据分配的第一物理地址为板卡内存的物理地址，以便将目标数据存储至扩展的板卡内存，不占用磁盘空间，提高访问速度。地址映射机制为第一逻辑地址分配对应的第一物理地址后，还需要保存第一逻辑地址和第一物理地址之间的映射关系，以便后续通过该映射关系查找数据。
综上可见，本方案基于虚拟内存进行数据存储时，使用扩展的板卡内存作为虚拟内存的存储介质，直接将数据存储至板卡内存中，从而避免占用磁盘空间，提高访问速度。
参见图2，本申请实施例提供的另一种基于虚拟内存的数据存储方法流程示意图；该数据存储方法包括：
S201、若检测到操作系统执行分配内存操作，则确定与分配内存操作对应的待存储的目标数据以及操作系统分配的第一逻辑地址；
S202、若第一逻辑地址在虚拟内存范围内，通过无损压缩算法对所述目标数据进行压缩，得到压缩数据；
S203、通过地址映射机制确定与第一逻辑地址对应的第一物理地址，该第一物理地址为扩展的板卡内存的物理地址；
S204、判断所述压缩数据的容量是否小于所述目标数据的容量；
若所述压缩数据的容量小于所述目标数据的容量，则执行S205；若所述压缩数据的容量不小于所述目标数据的容量，则执行S206；
S205、利用第一物理地址将压缩数据存储至扩展的板卡内存；
S206、利用第一物理地址将目标数据存储至扩展的板卡内存。
需要说明的是，本申请为了减少数据存储时所占用的容量，系统补丁检测到第一逻辑地址在虚拟内存范围内时，可将该目标数据转发给无损压缩算法，通过无损压缩算法对目标数据进行压缩，得到压缩数据；该无损压缩算法可采用一种通用无损压缩或者多种无损压缩算法的集合，具体可以为：LZ77算法、LZSS算法、基于哈夫曼编码原理的压缩算法等等。参见图3，为本申请实施例提供的数据存储系统结构示意图，该系统包括系统补丁、压缩算法和地址映射机制，其中，系统补丁检测出目标数据的第一逻辑地址后，将目标数据发送给压缩算法得到压缩数据，并将压缩数据及大小发送给地址映射机制，通过地址映射机制进行物理地址的分配及存储。
可以理解的是，对目标数据压缩后，若压缩后的数据大于压缩前的目标数据，则可以直接存储数据较小的目标数据，若压缩后的数据小于压缩前的目标数据，则可存储数据较小的压缩数据。并且，将压缩数据或目标数据存储至扩展的板卡内存之后，本申请还需要根据压缩数据或目标数据的容量对虚拟内存的剩余容量进行更新。在更新容量时，具体可通过无损压缩算法将压缩数据的大小或目标数据的大小反馈给系统补丁，通过系统补丁更新虚拟操作系统内存剩余空间及虚拟内存大小参数。其中，在本方案中，操作系统是以页为单位(4K)操作内存数据，本方案以页为单位压缩数据，压缩数据在存储时按照存储顺序对应存储，采用起始地址加压缩大小对应存储，内存板卡的内存管理采用内存最小读取单位为管理粒度。
具体来说，本方案为了避免因板卡内存满而出现存储失败的问题，若第一逻辑地址在虚拟内存范围内，本方案还需要判断虚拟内存的剩余容量是否大于目标数据的容量；若虚拟内存的剩余容量大于目标数据的容量，则执行通过地址映射机制确定与第一逻辑地址对应的第一物理地址的步骤；若虚拟内存的剩余容量不大于目标数据的容量，则通过地址映射机制确定与第一逻辑地址对应的第二物理地址，并基于第二物理地址将目标数据存储至磁盘。也即：若虚拟内存的剩余容量大于目标数据的容量，则说明板卡内存中还有剩余空间来存储该目标数据，则可继续执行后续分配第一逻辑地址及数据存储的步骤；若虚拟内存的剩余容量不大于目标数据的容量，说明目标数据不能存储至板卡内存，此时便可为该目标数据分配磁盘的物理地址，以将该目标数据存储至磁盘，避免出现存储失败的问题。
进一步，本方案检测到操作系统执行回收内存操作或者执行数据读取操作时，同样需要对数据执行对应的管理操作，分别包括：
1)若检测到操作系统执行回收内存操作，则本申请还需要确定与回收内存操作对应的第二逻辑地址；若第二逻辑地址在虚拟内存范围内，则通过地址映射机制确定与第二逻辑地址对应的第三物理地址，对第三物理地址下存储的数据执行回收操作，并对虚拟内存的剩余容量进行更新。
具体来说，操作系统执行回收内存操作时，系统补丁检测到分配的第二逻辑地址后，若该地址范围在虚拟内存范围内，则系统补丁需要将该第二逻辑地址转发给地址映射机制，地址映射机制根据逻辑地址与物理地址之间的映射关系，确定与该第二逻辑地址对应的第三物理地址，从而对第三物理地址内存储的数据执行回收操作，在执行回收操作后，系统补丁还需要更新虚拟操作系统内存剩余空间及虚拟内存大小参数。
2)若检测到操作系统执行数据读取操作，则本申请还需要确定与数据读取操作对应的第三逻辑地址；若第三逻辑地址在虚拟内存范围内，则通过地址映射机制确定与第三逻辑地址对应的第四物理地址及待读取数据的容量，基于第四物理地址及待读取数据的容量执行数据读取操作。
具体来说，操作系统执行读取内存操作时，本申请中的系统补丁还需要检测出分配的第三逻辑地址，如果该地址范围在虚拟内存范围内，系统补丁会将该地址转发给地址映射机制，地址映射机制通过检索得到与该第三逻辑地址对应的第四物理地址及大小，进行数据的读取。
需要说明的是，在进行数据回收或数据读取时，若该数据存储在板卡内存中，则经地址映射机制得到的物理地址为板卡内存的物理地址，并在板卡内存中执行对应的数据回收或者数据读取操作；若该数据存储在磁盘中，则经地址映射机制得到的物理地址为磁盘的物理地址，并在磁盘中执行对应的数据回收或者数据读取操作。并且，本方案检测到操作系统执行的操作为基于CPU的访存操作，当然也可以为其他领域的处理器的访存操作，在此并不具体限定。
综上所述，本方案公开了一种基于虚拟内存的数据存储方法，在本方法中，虚拟内存的存储介质为板卡内存，通过本方案将数据压缩后存储至板卡 内存的方式，与传统使用磁盘作为虚拟内存介质的方式相比，减少了数据占用的磁盘空间，减少了磁盘访问请求，提高数据访问效率。
下面对本申请实施例提供的数据存储装置、设备及介质进行介绍，下文描述的数据存储装置、设备及介质与上文描述的数据存储方法可以相互参照。
参见图4，本申请实施例提供的一种基于虚拟内存的数据存储装置结构示意图；该装置包括：
数据确定模块100，用于在检测到操作系统执行分配内存操作时，确定与所述分配内存操作对应的待存储的目标数据；
第一逻辑地址确定模块200，用于在检测到操作系统执行分配内存操作时，确定与所述分配内存操作对应的所述操作系统分配的第一逻辑地址；
第一物理地址确定模块300，用于在所述第一逻辑地址在虚拟内存范围内时，通过地址映射机制确定与所述第一逻辑地址对应的第一物理地址，所述第一物理地址为扩展的板卡内存的物理地址；
第一数据存储模块400，用于利用所述第一物理地址将所述目标数据存储至扩展的板卡内存。
其中，所述装置还包括：
压缩模块，用于在所述第一逻辑地址在虚拟内存范围内时，通过无损压缩算法对所述目标数据进行压缩，得到压缩数据；
所述第一数据存储模块，具体用于：利用所述第一物理地址将所述压缩数据存储至扩展的板卡内存。
其中，所述装置还包括：
第一判断模块，用于判断所述压缩数据的容量是否小于所述目标数据的容量；
所述第一数据存储模块具体用于：在所述压缩数据的容量小于所述目标数据的容量时，利用所述第一物理地址将所述压缩数据存储至扩展的板卡内存；在所述压缩数据的容量不小于所述目标数据的容量时，利用所述第一物理地址将所述目标数据存储至扩展的板卡内存。
其中，所述装置还包括：
更新模块，用于将所述压缩数据或目标数据存储至扩展的板卡内存之后，根据所述压缩数据或目标数据的容量对虚拟内存的剩余容量进行更新。
其中，所述装置还包括：
第二判断模块，用于判断虚拟内存的剩余容量是否大于所述目标数据的容量；若虚拟内存的剩余容量大于所述目标数据的容量，则触发所述第一物理地址确定模块；若虚拟内存的剩余容量不大于所述目标数据的容量，则触发第二物理地址确定模块；
第二物理地址确定模块，用于通过地址映射机制确定与所述第一逻辑地址对应的第二物理地址；所述第二物理地址为磁盘的物理地址；
第二数据存储模块，用于基于所述第二物理地址将所述目标数据存储至磁盘。
其中，所述装置还包括：
第二逻辑地址确定模块，用于在检测到操作系统执行回收内存操作时，确定与所述回收内存操作对应的第二逻辑地址；
数据回收模块，用于在所述第二逻辑地址在虚拟内存范围内时，通过地址映射机制确定与所述第二逻辑地址对应的第三物理地址，对所述第三物理地址下存储的数据执行回收操作，并对虚拟内存的剩余容量进行更新。
其中，所述装置还包括：
第三逻辑地址确定模块，用于在检测到操作系统执行数据读取操作时，确定与所述数据读取操作对应的第三逻辑地址；
数据读取模块，用于在所述第三逻辑地址在虚拟内存范围内时，通过地址映射机制确定与所述第三逻辑地址对应的第四物理地址及待读取数据的容量，基于所述第四物理地址及待读取数据的容量执行数据读取操作。
参见图5，为本申请实施例公开的一种电子设备示意图，该设备包括：
存储器11，用于存储计算机程序；
处理器12，用于执行所述计算机程序时实现上述任意方法实施例所述的基于虚拟内存的数据存储方法的步骤。
在本实施例中，设备可以是PC(Personal Computer，个人电脑)，也可以是智能手机、平板电脑、掌上电脑、便携计算机等终端设备。
该设备可以包括存储器11、处理器12和总线13。
其中，存储器11至少包括一种类型的可读存储介质，所述可读存储介质包括闪存、硬盘、多媒体卡、卡型存储器(例如，SD或DX存储器等)、磁性存储器、磁盘、光盘等。存储器11在一些实施例中可以是设备的内部存储单元，例如该设备的硬盘。存储器11在另一些实施例中也可以是设备的外部存储设备，例如设备上配备的插接式硬盘，智能存储卡(Smart Media Card,SMC)，安全数字(Secure Digital,SD)卡，闪存卡(Flash Card)等。进一步地，存储器11还可以既包括设备的内部存储单元也包括外部存储设备。存储器11不仅可以用于存储安装于设备的应用软件及各类数据，例如执行数据存储方法的程序代码等，还可以用于暂时地存储已经输出或者将要输出的数据。
处理器12在一些实施例中可以是一中央处理器(Central Processing Unit,CPU)、控制器、微控制器、微处理器或其他数据处理芯片，用于运行存储器11中存储的程序代码或处理数据，例如执行数据存储方法的程序代码等。
该总线13可以是外设部件互连标准(peripheral component interconnect，简称PCI)总线或扩展工业标准结构(extended industry standard architecture，简称EISA)总线等。该总线可以分为地址总线、数据总线、控制总线等。为便于表示，图5中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
进一步地，设备还可以包括网络接口14，网络接口14可选的可以包括有线接口和/或无线接口(如WI-FI接口、蓝牙接口等)，通常用于在该设备与其他电子设备之间建立通信连接。
可选地，该设备还可以包括用户接口15，用户接口15可以包括显示器(Display)、输入单元比如键盘(Keyboard)，可选的用户接口15还可以包括标准的有线接口、无线接口。可选地，在一些实施例中，显示器可以是LED显示器、液晶显示器、触控式液晶显示器以及OLED(Organic Light-Emitting Diode，有机发光二极管)触摸器等。其中，显示器也可以适当的称为显示屏或显示单元，用于显示在设备中处理的信息以及用于显示可视化的用户界面。
图5仅示出了具有组件11至15的设备，本领域技术人员可以理解的是，图5示出的结构并不构成对设备的限定，可以包括比图示更少或者更多的部件，或者组合某些部件，或者不同的部件布置。
本申请实施例还公开了一种计算机可读存储介质，所述计算机可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现上述任意方法实施例所述的基于虚拟内存的数据存储方法的步骤。
其中，该存储介质可以包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本申请。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本申请的精神或范围的情况下，在其它实施例中实现。因此，本申请将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (10)

  1. 一种基于虚拟内存的数据存储方法，其特征在于，包括：
    若检测到操作系统执行分配内存操作，则确定与所述分配内存操作对应的待存储的目标数据以及所述操作系统分配的第一逻辑地址；
    若所述第一逻辑地址在虚拟内存范围内，则通过地址映射机制确定与所述第一逻辑地址对应的第一物理地址，所述第一物理地址为扩展的板卡内存的物理地址；
    利用所述第一物理地址将所述目标数据存储至扩展的板卡内存。
  2. 根据权利要求1所述的数据存储方法，其特征在于，若所述第一逻辑地址在虚拟内存范围内，则所述数据存储方法还包括：
    通过无损压缩算法对所述目标数据进行压缩，得到压缩数据；
    相应的，所述利用所述第一物理地址将所述目标数据存储至扩展的板卡内存包括：利用所述第一物理地址将所述压缩数据存储至扩展的板卡内存。
  3. 根据权利要求2所述的数据存储方法，其特征在于，所述通过地址映射机制确定与所述第一逻辑地址对应的第一物理地址之后，还包括：
    判断所述压缩数据的容量是否小于所述目标数据的容量；
    若所述压缩数据的容量小于所述目标数据的容量，则利用所述第一物理地址将所述压缩数据存储至扩展的板卡内存，若所述压缩数据的容量不小于所述目标数据的容量，利用所述第一物理地址将所述目标数据存储至扩展的板卡内存。
  4. 根据权利要求3所述的数据存储方法，其特征在于，将所述压缩数据或所述目标数据存储至扩展的板卡内存之后，还包括：
    根据所述压缩数据或所述目标数据的容量对虚拟内存的剩余容量进行更新。
  5. 根据权利要求1所述的数据存储方法，其特征在于，若所述第一逻辑地址在虚拟内存范围内，则所述数据存储方法还包括：
    判断虚拟内存的剩余容量是否大于所述目标数据的容量；
    若虚拟内存的剩余容量大于所述目标数据的容量，则执行所述通过地址映射机制确定与所述第一逻辑地址对应的第一物理地址的步骤；
    若虚拟内存的剩余容量不大于所述目标数据的容量，则通过地址映射机制确定与所述第一逻辑地址对应的第二物理地址，并基于所述第二物理地址将所述目标数据存储至磁盘；所述第二物理地址为磁盘的物理地址。
  6. 根据权利要求1至5中任意一项所述的数据存储方法，其特征在于，所述数据存储方法还包括：
    若检测到操作系统执行回收内存操作，则确定与所述回收内存操作对应的第二逻辑地址；
    若所述第二逻辑地址在虚拟内存范围内，则通过地址映射机制确定与所述第二逻辑地址对应的第三物理地址，对所述第三物理地址下存储的数据执行回收操作，并对虚拟内存的剩余容量进行更新。
  7. 根据权利要求1至5中任意一项所述的数据存储方法，其特征在于，所述数据存储方法还包括：
    若检测到操作系统执行数据读取操作，则确定与所述数据读取操作对应的第三逻辑地址；
    若所述第三逻辑地址在虚拟内存范围内，则通过地址映射机制确定与所述第三逻辑地址对应的第四物理地址及待读取数据的容量，基于所述第四物理地址及待读取数据的容量执行数据读取操作。
  8. 一种基于虚拟内存的数据存储装置，其特征在于，包括：
    数据确定模块，用于在检测到操作系统执行分配内存操作时，确定与所述分配内存操作对应的待存储的目标数据；
    第一逻辑地址确定模块，用于在检测到操作系统执行分配内存操作时，确定与所述分配内存操作对应的所述操作系统分配的第一逻辑地址；
    第一物理地址确定模块，用于在所述第一逻辑地址在虚拟内存范围内时，通过地址映射机制确定与所述第一逻辑地址对应的第一物理地址，所述第一物理地址为扩展的板卡内存的物理地址；
    第一数据存储模块，用于利用所述第一物理地址将所述目标数据存储至扩展的板卡内存。
  9. 一种电子设备，其特征在于，包括：
    存储器，用于存储计算机程序；
    处理器，用于执行所述计算机程序时实现如权利要求1至7任一项所述的基于虚拟内存的数据存储方法的步骤。
  10. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现如权利要求1至7任一项所述的基于虚拟内存的数据存储方法的步骤。
PCT/CN2021/143003 2021-01-18 2021-12-30 基于虚拟内存的数据存储方法、装置、设备及存储介质 WO2022151985A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110063607.4A CN112764925A (zh) 2021-01-18 2021-01-18 基于虚拟内存的数据存储方法、装置、设备及存储介质
CN202110063607.4 2021-01-18

Publications (1)

Publication Number Publication Date
WO2022151985A1 true WO2022151985A1 (zh) 2022-07-21

Family

ID=75702811

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/143003 WO2022151985A1 (zh) 2021-01-18 2021-12-30 基于虚拟内存的数据存储方法、装置、设备及存储介质

Country Status (2)

Country Link
CN (1) CN112764925A (zh)
WO (1) WO2022151985A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112764925A (zh) * 2021-01-18 2021-05-07 苏州浪潮智能科技有限公司 基于虚拟内存的数据存储方法、装置、设备及存储介质
CN113625953B (zh) * 2021-06-30 2023-08-22 苏州浪潮智能科技有限公司 一种数据处理方法、装置、设备及存储介质
CN115794669A (zh) * 2021-09-11 2023-03-14 华为技术有限公司 一种扩展内存的方法、装置及相关设备

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108197038A (zh) * 2018-02-01 2018-06-22 深圳市风云实业有限公司 一种Linux数据传输方法、装置和用户终端
CN110737608A (zh) * 2018-07-03 2020-01-31 阿里巴巴集团控股有限公司 一种数据操作方法、装置及系统
US20200065254A1 (en) * 2018-08-21 2020-02-27 International Business Machines Corporation Storage management for deployment of virtual machine
CN110955488A (zh) * 2019-09-10 2020-04-03 中兴通讯股份有限公司 一种持久性内存的虚拟化方法及系统
CN111414248A (zh) * 2019-01-04 2020-07-14 阿里巴巴集团控股有限公司 内存管理方法、装置及计算设备
CN111984610A (zh) * 2020-09-27 2020-11-24 苏州浪潮智能科技有限公司 数据压缩方法、装置及计算机可读存储介质
CN112162818A (zh) * 2020-09-16 2021-01-01 Oppo（重庆）智能科技有限公司 一种虚拟内存分配方法、装置、电子设备及存储介质
CN112764925A (zh) * 2021-01-18 2021-05-07 苏州浪潮智能科技有限公司 基于虚拟内存的数据存储方法、装置、设备及存储介质

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102169459B (zh) * 2010-11-29 2013-04-24 北京握奇数据系统有限公司 一种访问数据的方法、装置和智能卡

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108197038A (zh) * 2018-02-01 2018-06-22 深圳市风云实业有限公司 一种Linux数据传输方法、装置和用户终端
CN110737608A (zh) * 2018-07-03 2020-01-31 阿里巴巴集团控股有限公司 一种数据操作方法、装置及系统
US20200065254A1 (en) * 2018-08-21 2020-02-27 International Business Machines Corporation Storage management for deployment of virtual machine
CN111414248A (zh) * 2019-01-04 2020-07-14 阿里巴巴集团控股有限公司 内存管理方法、装置及计算设备
CN110955488A (zh) * 2019-09-10 2020-04-03 中兴通讯股份有限公司 一种持久性内存的虚拟化方法及系统
CN112162818A (zh) * 2020-09-16 2021-01-01 Oppo（重庆）智能科技有限公司 一种虚拟内存分配方法、装置、电子设备及存储介质
CN111984610A (zh) * 2020-09-27 2020-11-24 苏州浪潮智能科技有限公司 数据压缩方法、装置及计算机可读存储介质
CN112764925A (zh) * 2021-01-18 2021-05-07 苏州浪潮智能科技有限公司 基于虚拟内存的数据存储方法、装置、设备及存储介质

Also Published As

Publication number Publication date
CN112764925A (zh) 2021-05-07

Similar Documents

Publication Publication Date Title
WO2022151985A1 (zh) 基于虚拟内存的数据存储方法、装置、设备及存储介质
US11531625B2 (en) Memory management method and apparatus
CN111352861B (zh) 内存压缩方法、装置及电子设备
US20170177497A1 (en) Compressed caching of a logical-to-physical address table for nand-type flash memory
US20160253104A1 (en) Techniques for automatically freeing space in a log-structured storage system
US9977598B2 (en) Electronic device and a method for managing memory space thereof
CN111625191A (zh) 一种数据读写方法、装置及电子设备和存储介质
US11132291B2 (en) System and method of FPGA-executed flash translation layer in multiple solid state drives
EP3163451B1 (en) Memory management method and device, and memory controller
US20140122803A1 (en) Information processing apparatus and method thereof
US20200225882A1 (en) System and method for compaction-less key-value store for improving storage capacity, write amplification, and i/o performance
WO2015180598A1 (zh) 对存储设备的访问信息处理方法和装置、系统
US8499138B2 (en) Demand-based memory management of non-pagable data storage
CN111240601A (zh) 一种分区空间的超级块确定方法、装置、设备及存储介质
WO2024099448A1 (zh) 内存释放、内存恢复方法、装置、计算机设备及存储介质
CN110554837A (zh) 易疲劳存储介质的智能交换
US11928359B2 (en) Memory swapping method and apparatus
CN115543532A (zh) 缺页异常的处理方法、装置、电子设备以及存储介质
CN111338981A (zh) 一种内存防碎片方法、系统及储存介质
CN111881065B (zh) 数据重删操作的物理地址处理方法、装置、设备及介质
KR20220024206A (ko) 하드웨어 기반 메모리 압축
EP4134829A1 (en) Page swapping method, storage system, and electronic device
US11354233B2 (en) Method and system for facilitating fast crash recovery in a storage device
CN113625953B (zh) 一种数据处理方法、装置、设备及存储介质
US10846023B2 (en) Storage device and storage area management method for reducing garbage collection processing

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21919172

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21919172

Country of ref document: EP

Kind code of ref document: A1