WO2022149813A1 - Display device - Google Patents

Display device Download PDF

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Publication number
WO2022149813A1
WO2022149813A1 PCT/KR2022/000020 KR2022000020W WO2022149813A1 WO 2022149813 A1 WO2022149813 A1 WO 2022149813A1 KR 2022000020 W KR2022000020 W KR 2022000020W WO 2022149813 A1 WO2022149813 A1 WO 2022149813A1
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WO
WIPO (PCT)
Prior art keywords
electrode
disposed
light emitting
pattern
bank
Prior art date
Application number
PCT/KR2022/000020
Other languages
French (fr)
Korean (ko)
Inventor
박노경
이현욱
Original Assignee
삼성디스플레이 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 삼성디스플레이 주식회사 filed Critical 삼성디스플레이 주식회사
Priority to EP22736791.9A priority Critical patent/EP4276902A1/en
Priority to CN202280007143.8A priority patent/CN116349015A/en
Publication of WO2022149813A1 publication Critical patent/WO2022149813A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present invention relates to a display device.
  • OLED organic light emitting display
  • LCD liquid crystal display
  • a device for displaying an image of a display device includes a display panel such as an organic light emitting display panel or a liquid crystal display panel.
  • the light emitting display panel may include a light emitting device.
  • a light emitting diode LED
  • OLED organic light emitting diode
  • An object of the present invention is to provide a display device in which peeling of an insulating layer disposed on light emitting devices is prevented.
  • a display device provides a light emitting area, a sub area spaced apart from the light emitting area in a first direction, a first electrode disposed in the light emitting area and extending in the first direction, and the second A second electrode spaced apart from the first electrode in a second direction crossing the first direction and extending in the first direction, a first insulating layer disposed on the first electrode and the second electrode, and the first insulating layer a plurality of light emitting devices disposed on the upper surface and at least one end of both ends disposed on the first electrode or the second electrode, a first pattern disposed on the plurality of light emitting devices and extending in the first direction a second insulating layer including a portion and a first base portion disposed in the sub-region, a first connection electrode disposed on the first electrode and in contact with the light emitting device, and disposed on the second electrode to emit the light and a second connection electrode in contact with the device, wherein the first pattern portion is disposed from the light emitting region to the sub region
  • a first bank including a plurality of bank parts extending in the first direction from the light emitting area, and a second bank disposed to surround the light emitting area and the sub area, wherein the second insulating layer comprises the It is disposed on the second bank and may further include a second base part connected to the first base part and the first pattern part.
  • the first connection electrode and the second connection electrode are respectively disposed over the light emitting region and the sub region, and the first pattern portion extends between the first connection electrode and the second connection electrode in the first direction. It may be connected to the first base part.
  • the first connection electrode and the second connection electrode may contact both sides of the first pattern portion, respectively, and a width of the first pattern portion may be smaller than a length of the plurality of light emitting devices.
  • the plurality of light emitting devices are first light emitting devices disposed on the first electrode and the third electrode a device and a second light emitting device disposed on the third electrode and the second electrode, wherein the first pattern portion of the second insulating layer is disposed on the first light emitting devices and the second insulating layer
  • the layer may further include a second pattern portion disposed on the second light emitting devices, and a first support pattern portion disposed on the third electrode.
  • the second insulating layer has a shape extending in the second direction, a first bridge part connected to the first pattern part and the second base part, and extending in the second direction, the second pattern part and the first and a second bridge part connected to the support pattern part, wherein widths of the first bridge part and the second bridge part measured in the first direction are measured in the second direction of the first pattern part and the second pattern part may be larger than the specified width.
  • the first support pattern part may extend in the first direction on the third electrode, and a width measured in the second direction may be greater than a width measured in the first direction of the first bridge part and the second bridge part. have.
  • Each of the plurality of bank parts of the first bank has a length extending in the first direction longer than the light emitting area, and a portion of the second bank disposed between the light emitting area and the sub area is the plurality of bank parts. and overlapping in the thickness direction, and the second base portion may not be disposed on a portion of the second bank that overlaps the bank portions.
  • the plurality of light emitting devices include the first A first light emitting element disposed on the first electrode and the third electrode and in contact with the first connection electrode and the third connection electrode, the second connection electrode and the second electrode disposed on the second electrode and the fourth electrode a second light emitting element in contact with a fifth connection electrode, a third light emitting element disposed on the first electrode and the third electrode and contacting the third connection electrode and the fourth connection electrode, and the second electrode;
  • a fourth light emitting device disposed on the fourth electrode and in contact with the fourth connection electrode and the fifth connection electrode may be included.
  • the first pattern portion of the second insulating layer is disposed on the first light emitting devices, and the second insulating layer is disposed on the second pattern portion and the third light emitting devices disposed on the second light emitting devices.
  • a third pattern portion disposed on the , a fourth pattern portion disposed on the fourth light emitting devices, a first support pattern portion partially overlapping the second electrode and the third electrode and extending in the first direction; and a plurality of bridge parts having a shape extending in the second direction and connected to any one of the first support pattern part and the first to fourth pattern parts.
  • the plurality of bridge parts includes a second bridge part connecting the second pattern part and the first support pattern part, a third bridge part connecting the third pattern part and the first support pattern part, and the fourth pattern part; A fourth bridge part connecting the first support pattern part may be included.
  • the second insulating layer further includes a second support pattern part and a third support pattern part extending in the first direction in the light emitting area and spaced apart from each other in the second direction with the first support pattern part interposed therebetween,
  • the plurality of bridge parts includes a first bridge part connected to the first pattern part and the second support pattern part, a fifth bridge part connected to the fourth pattern part and the third support pattern part, and the third pattern part; It may include a sixth bridge part connected to the second support pattern part.
  • a width of the first pattern portion of the second insulating layer measured in the second direction may be smaller than a thickness of the first pattern portion.
  • a display device includes a plurality of electrodes extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a first electrode, the first electrode, and the first electrode A second electrode spaced apart in two directions, a third electrode disposed between the first electrode and the second electrode, and a fourth electrode spaced apart from the second electrode in the second direction, on the plurality of electrodes a first insulating layer, both ends of which are disposed on the first electrode and the third electrode, and a plurality of first light emitting devices arranged in the first direction, and both ends of the second electrode and the fourth electrode a plurality of second light emitting elements arranged on an electrode and arranged in the first direction, and a first pattern part disposed on the first light emitting elements and extending in the first direction, on the second light emitting elements a second insulating layer including a second pattern part disposed on the ridge and extending in the first direction, and a first support pattern part partially disposed on the second electrode and the third electrode
  • a first width measured in the second direction of the first pattern portion and the second pattern portion is smaller than lengths of the plurality of first light emitting elements and the plurality of second light emitting elements, respectively, and A second width measured in the first direction is greater than the first widths of the first pattern part and the second pattern part, and a third width measured in the second direction of the first support pattern part is the plurality of bridge parts. may be greater than the second width measured in the first direction.
  • a thickness of the first pattern part and the second pattern part may be greater than the first width of the first pattern part and the second pattern part.
  • a first bank overlapping the plurality of electrodes and including a plurality of bank portions extending in the first direction, a light emitting region in which the plurality of first light emitting devices and the plurality of second light emitting devices are disposed and a second bank surrounding the sub-region spaced apart from the light-emitting region in the first direction, wherein the second insulating layer includes a first base portion disposed in the sub-region, and a second bank disposed on the second bank. It further includes a second base part, wherein the first pattern part and the second pattern part each extend from the light emitting area to the sub area to be connected to the first base part.
  • the second insulating layer may further include a first bridge part having a shape extending in the second direction and connected to the first pattern part and the second base part.
  • the second insulating layer includes a third pattern portion spaced apart from the first pattern portion in the first direction, a fourth pattern portion spaced apart from the second pattern portion in the first direction, and the first direction and further comprising a second support pattern portion and a third support pattern portion spaced apart from each other in the second direction with the first support pattern portion interposed therebetween, wherein the plurality of bridge portions include the first pattern portion and the second support pattern portion A first bridge part connected to the second support pattern part, a second bridge part connected to the second pattern part and the first support pattern part, a third bridge part connected to the third pattern part and the first support pattern part, and It may include a fourth bridge part connected to the fourth pattern part and the first support pattern part.
  • the plurality of bridge parts may further include a fifth bridge part connected to the fourth pattern part and the third support pattern part, and a sixth bridge part connected to the third pattern part and the second support pattern part.
  • the display device may have a structure that prevents peeling of the insulating layer for fixing the light emitting elements even if the line width is thin compared to the length.
  • the insulating layer may include a pattern part for fixing the light emitting devices, support pattern parts having a width greater than that of the pattern part and connected thereto, and a bridge part.
  • the display device may have a structure to prevent a portion disposed on the light emitting device from being peeled off during a subsequent process after the formation of the insulating layer, and the light emitting device and a portion of the insulating layer may be peeled off or separated in the subsequent process It can be used to prevent others as foreign bodies.
  • FIG. 1 is a schematic plan view of a display device according to an exemplary embodiment.
  • FIG. 2 is a plan view illustrating one pixel of a display device according to an exemplary embodiment.
  • FIG. 3 is a plan view illustrating a relative arrangement of a first bank and a second bank, a plurality of electrodes, and a second insulating layer disposed in one pixel of FIG. 2 .
  • FIG. 4 is a plan view illustrating a relative arrangement of a first bank and a second bank, a plurality of connection electrodes, and a second insulating layer disposed in one pixel of FIG. 2 .
  • FIG. 5 is a cross-sectional view taken along line Q1-Q1' of FIG. 2 .
  • FIG. 6 is a cross-sectional view taken along the line Q2-Q2' of FIG.
  • FIG. 7 is an enlarged view of a portion A1 of FIG. 2 .
  • FIG. 8 is a schematic diagram of a light emitting device according to an embodiment.
  • FIG. 9 is a plan view illustrating one sub-pixel of a display device according to another exemplary embodiment.
  • FIG. 10 is a cross-sectional view taken along line Q3-Q3' of FIG. 9 .
  • FIG. 11 is an enlarged view of a portion A2 of FIG. 9 .
  • FIG. 12 is a plan view illustrating one sub-pixel of a display device according to another exemplary embodiment.
  • FIG. 13 is a plan view illustrating a relative arrangement of a first bank and a second bank, a plurality of connection electrodes, and a second insulating layer disposed in one sub-pixel of FIG. 12 .
  • FIG. 14 is a cross-sectional view taken along line Q4-Q4' of FIG. 12 .
  • FIG. 15 is an enlarged view of a portion A3 of FIG. 12 .
  • FIG. 16 is an enlarged view of a portion A4 of FIG. 12 .
  • FIG. 17 is an enlarged view of a portion A5 of FIG. 12 .
  • FIG. 18 is a plan view illustrating one sub-pixel of a display device according to another exemplary embodiment.
  • FIG. 19 is a cross-sectional view taken along line Q5-Q5' of FIG. 18 .
  • 20 is a plan view illustrating one sub-pixel of a display device according to another exemplary embodiment.
  • 21 is a cross-sectional view taken along line Q6-Q6' of FIG. 20;
  • FIG. 22 is a cross-sectional view taken along line Q7-Q7' of FIG. 20 .
  • FIG. 23 is a plan view illustrating one sub-pixel of a display device according to another exemplary embodiment.
  • FIG. 24 is an enlarged view of a portion A6 of FIG. 23 .
  • FIG. 25 is an enlarged view of a portion A7 of FIG. 23 .
  • 26 is a cross-sectional view taken along line Q8-Q8' of FIG. 24 and line Q9-Q9' of FIG. 25;
  • Elements or layers are referred to as “on” of another element or layer, including cases in which another layer or other element is interposed immediately on or in the middle of another element.
  • those referred to as “Below”, “Left” and “Right” refer to cases where they are interposed immediately adjacent to other elements or interposed other layers or other materials in the middle.
  • Like reference numerals refer to like elements throughout.
  • FIG. 1 is a schematic plan view of a display device according to an exemplary embodiment.
  • the display device 10 displays a moving image or a still image.
  • the display device 10 may refer to any electronic device that provides a display screen.
  • An electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation system, a game machine, a digital camera, a camcorder, etc. may be included in the display device 10 .
  • the display device 10 includes a display panel that provides a display screen.
  • the display panel include an inorganic light emitting diode display panel, an organic light emitting display panel, a quantum dot light emitting display panel, a plasma display panel, a field emission display panel, and the like.
  • an inorganic light emitting diode display panel is applied is exemplified as an example of the display panel, but the present invention is not limited thereto, and the same technical idea may be applied to other display panels if applicable.
  • the shape of the display device 10 may be variously modified.
  • the display device 10 may have a shape such as a long rectangle, a long rectangle, a square, a rectangle with rounded corners (vertices), other polygons, or a circle.
  • the shape of the display area DPA of the display device 10 may also be similar to the overall shape of the display device 10 .
  • FIG. 1 a display device 10 having a rectangular shape having a long length in the second direction DR2 is illustrated.
  • the display device 10 may include a display area DPA and a non-display area NDA surrounding the display area DPA along an edge or a periphery of the display area DPA.
  • the display area DPA is an area in which a screen can be displayed
  • the non-display area NDA is an area in which a screen is not displayed.
  • the display area DPA may be referred to as an active area
  • the non-display area NDA may also be referred to as a non-active area.
  • the display area DPA may generally occupy the center of the display device 10 .
  • the display area DPA may include a plurality of pixels PX.
  • the plurality of pixels PX may be arranged in a matrix direction.
  • the shape of each pixel PX may be a rectangular shape or a square shape in plan view, but is not limited thereto, and each side may have a rhombus shape inclined with respect to one direction.
  • Each pixel PX may be arranged in a stripe type or a PENTILE TM type.
  • each of the pixels PX may include one or more light emitting devices emitting light of a specific wavelength band to display a specific color.
  • a non-display area NDA may be disposed around the display area DPA.
  • the non-display area NDA may completely or partially surround the display area DPA.
  • the display area DPA may have a rectangular shape, and the non-display area NDA may be disposed adjacent to four sides of the display area DPA.
  • the non-display area NDA may constitute a bezel of the display device 10 .
  • Wires or circuit drivers included in the display device 10 may be disposed in each of the non-display areas NDA, or external devices may be mounted thereon.
  • FIG. 2 is a plan view illustrating one pixel of a display device according to an exemplary embodiment.
  • a portion of another pixel PX adjacent thereto in the first direction DR1 is also illustrated.
  • each of the plurality of pixels PX of the display device 10 may include a plurality of sub-pixels SPXn, where n is 1 to 3 .
  • one pixel PX may include a first sub-pixel SPX1 , a second sub-pixel SPX2 , and a third sub-pixel SPX3 .
  • the first sub-pixel SPX1 emits light of a first color
  • the second sub-pixel SPX2 emits light of a second color
  • the third sub-pixel SPX3 emits light of a third color.
  • the first color may be blue
  • the second color may be green
  • the third color may be red.
  • each of the sub-pixels SPXn may emit light of the same color.
  • each of the sub-pixels SPXn may emit blue light.
  • one pixel PX includes three sub-pixels SPXn in FIG. 2
  • the present invention is not limited thereto, and the pixel PX may include a larger number of sub-pixels SPXn. .
  • Each of the sub-pixels SPXn of the display device 10 may include an emission area EMA and a non-emission area.
  • the light emitting area EMA may be an area in which the light emitting device ED is disposed and light of a specific wavelength band is emitted.
  • the non-emission area may be an area in which the light emitting device ED is not disposed and light emitted from the light emitting device ED does not reach and is not emitted.
  • the light emitting area may include a region in which the light emitting device ED is disposed, and an area adjacent to the light emitting device ED, in which light emitted from the light emitting device ED is emitted.
  • the light emitting area EMA is not limited thereto, and the light emitting area EMA may also include an area in which light emitted from the light emitting device ED is reflected or refracted by other members to be emitted.
  • the plurality of light emitting devices ED may be disposed in each sub-pixel SPXn, and may form a light emitting area including an area in which they are disposed and an area adjacent thereto.
  • each of the emission areas EMA of each sub-pixel SPXn may have a different area according to a color or wavelength band of light emitted from the light-emitting device ED disposed in the corresponding sub-pixel.
  • Each sub-pixel SPXn may further include a sub-area SA disposed in the non-emission area.
  • the sub-area SA may be disposed below the light-emitting area EMA, which is the other side of the first direction DR1 , and may be disposed between the light-emitting areas EMA of the sub-pixels SPXn adjacent in the first direction DR1 .
  • the plurality of light-emitting areas EMA and sub-areas SA are repeatedly arranged in the second direction DR2 , and the light-emitting area EMA and the sub-area SA are arranged in the first direction DR1 . Can be arranged alternately.
  • the present invention is not limited thereto, and the emission areas EMA and the sub-areas SA of the plurality of pixels PX may have a different arrangement from that of FIG. 2 . Since the light emitting device ED is not disposed in the sub area SA, no light is emitted, but a portion of the electrode RME disposed in each sub pixel SPXn may be disposed. The electrodes RME disposed in different sub-pixels SPXn may be disposed to be separated from each other in the separation portion ROP of the sub-area SA.
  • a second bank BNL2 is disposed between the emission areas EMA and the sub areas SA.
  • the second bank BNL2 may be disposed in a grid pattern on the entire surface of the display area DPA, including portions extending in the first and second directions DR1 and DR2 in a plan view.
  • the second bank BNL2 is disposed across the boundary of each sub-pixel SPXn to distinguish neighboring sub-pixels SPXn.
  • the second bank BNL2 is disposed to surround the emission area EMA disposed in each sub-pixel SPXn to distinguish them.
  • the distance between the light emitting areas EMA, between the sub areas SA, and between the foot and the foot area EMA and the sub area SA may vary according to the width of the second bank BNL2 .
  • FIG. 3 is a plan view illustrating a relative arrangement of a first bank and a second bank, a plurality of electrodes, and a second insulating layer disposed in one pixel of FIG. 2 .
  • FIG. 4 is a plan view illustrating a relative arrangement of a first bank and a second bank, a plurality of connection electrodes, and a second insulating layer disposed in one pixel of FIG. 2 .
  • FIG. 5 is a cross-sectional view taken along line Q1-Q1' of FIG. 2 .
  • 6 is a cross-sectional view taken along the line Q2-Q2' of FIG.
  • FIG. 7 is an enlarged view of a portion A1 of FIG. 2 .
  • FIG. 3 and 4 illustrate only some layers among a plurality of layers disposed in one pixel PX by omitting some of the layers.
  • FIG. 5 shows a cross-section crossing both ends of the light emitting device ED disposed in the first sub-pixel SPX1
  • FIG. 6 is a separation disposed in the sub-area SA of the first sub-pixel SPX1 .
  • a cross-section across the portion ROP is shown.
  • 7 is an enlarged view of a portion between the light emitting area EMA and the sub area SA.
  • the display device 10 includes a first substrate SUB, a semiconductor layer disposed on the first substrate SUB, a plurality of conductive layers, and a plurality of insulating layers. layers may be included.
  • the semiconductor layer, the conductive layer, and the insulating layer may constitute the circuit layer CCL and the display element layer of the display device 10 , respectively.
  • the first substrate SUB may be an insulating substrate.
  • the first substrate SUB may be made of an insulating material such as glass, quartz, or polymer resin.
  • the first substrate SUB may be a rigid substrate, but may also be a flexible substrate capable of bending, folding, rolling, or the like.
  • the first conductive layer may be disposed on the first substrate SUB.
  • the first conductive layer includes a lower metal layer BML, and the lower metal layer BML is formed in a thickness direction (eg, a third direction (eg, a third direction) of the active layer ACT1 of the first transistor T1 and the first substrate SUB. DR3))).
  • the lower metal layer BML may include a light-blocking material to prevent light from being incident on the active layer ACT1 of the first transistor. However, in some embodiments, the lower metal layer BML may be omitted.
  • the buffer layer BL may be disposed on the lower metal layer BML and the first substrate SUB.
  • the buffer layer BL is formed on the first substrate SUB to protect the transistors of the pixel PX from moisture penetrating through the first substrate SUB, which is vulnerable to moisture permeation, and may perform a surface planarization function.
  • the semiconductor layer is disposed on the buffer layer BL.
  • the semiconductor layer may include the active layer ACT1 of the first transistor T1 .
  • the active layer ACT1 may be disposed to partially overlap the gate electrode G1 of the second conductive layer to be described later in the third direction DR3 .
  • the semiconductor layer may include polycrystalline silicon, single crystal silicon, an oxide semiconductor, or the like. In another embodiment, the semiconductor layer may include polycrystalline silicon.
  • the oxide semiconductor may be an oxide semiconductor containing indium (In).
  • the oxide semiconductor may include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), and indium zinc tin oxide (Indium Zinc Tin Oxide).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • IGO indium gallium oxide
  • IGO indium zinc tin oxide
  • IZTO Indium Gallium Tin Oxide
  • IGTO Indium Gallium Tin Oxide
  • IGZO Indium Gallium Zinc Oxide
  • IGZTO Indium Gallium Zinc Tin Oxide
  • FIG. 5 illustrates that one first transistor T1 is disposed in the sub-pixel SPXn of the display device 10 , but the present invention is not limited thereto, and the display device 10 may include a larger number of transistors. have.
  • the first gate insulating layer GI is disposed on the semiconductor layer and the buffer layer BL.
  • the first gate insulating layer GI may serve as a gate insulating layer of the first transistor T1 .
  • the second conductive layer is disposed on the first gate insulating layer GI.
  • the second conductive layer may include the gate electrode G1 of the first transistor T1 .
  • the gate electrode G1 may be disposed to overlap the channel region of the active layer ACT1 in the third direction DR3 that is the thickness direction of the first substrate SUB.
  • the first interlayer insulating layer IL1 is disposed on the second conductive layer and the first gate insulating layer GI.
  • the first interlayer insulating layer IL1 may function as an insulating layer between the second conductive layer and other layers disposed thereon and may protect the second conductive layer.
  • the third conductive layer is disposed on the first interlayer insulating layer IL1.
  • the third conductive layer may include a first voltage line VL1 , a second voltage line VL2 , and a plurality of conductive patterns CDP1 and CDP2 .
  • a high potential voltage (or a first power voltage) transmitted to the first electrode RME1 is applied to the first voltage line VL1
  • a low voltage transmitted to the second electrode RME2 is applied to the second voltage line VL2
  • a potential voltage (or a second power supply voltage) may be applied.
  • the first voltage line VL1 may be partially in contact with the active layer ACT1 of the first transistor T1 through a contact hole penetrating the first interlayer insulating layer IL1 and the first gate insulating layer GI. have.
  • the first voltage line VL1 may serve as the first drain electrode D1 of the first transistor T1 .
  • the second voltage line VL2 may be directly connected to a second electrode RME2 to be described later.
  • the first conductive pattern CDP1 may contact the active layer ACT1 of the first transistor T1 through a contact hole penetrating the first interlayer insulating layer IL1 and the first gate insulating layer GI. Also, the first conductive pattern CDP1 may contact the lower metal layer BML through another contact hole penetrating the first interlayer insulating layer IL1 , the first gate insulating layer GI, and the buffer layer GL. have.
  • the first conductive pattern CDP1 may serve as the first source electrode S1 of the first transistor T1 .
  • the second conductive pattern CDP2 may be connected to a first electrode RME1 to be described later. Also, the second conductive pattern CDP2 may be electrically connected to the first transistor T1 through the first conductive pattern CDP1 .
  • the first conductive pattern CDP1 and the second conductive pattern CDP2 are exemplified to be separated from each other, but in some embodiments, the second conductive pattern CDP2 is formed between the first conductive pattern CDP1 and the second conductive pattern CDP1 They may be integrated to form one pattern.
  • the first transistor T1 may transfer the first power voltage applied from the first voltage line VL1 to the first electrode RME1 .
  • the second conductive pattern CDP2 is a conductive layer different from the first conductive pattern CDP1 , for example, a fourth conductive layer disposed on the third conductive layer with the third conductive layer and some insulating layers interposed therebetween.
  • the first voltage line VL1 and the second voltage line VL2 may also be formed of a fourth conductive layer instead of the third conductive layer, and the first voltage line VL1 may be formed of the first voltage line VL1 through a different conductive pattern. It may be electrically connected to the drain electrode D1 of the transistor T1.
  • the above-described buffer layer BL, the first gate insulating layer GI, and the first interlayer insulating layer IL1 may be formed of a plurality of inorganic layers alternately stacked.
  • the buffer layer BL, the first gate insulating layer GI, and the first interlayer insulating layer IL1 may include silicon oxide (Silicon Oxide, SiO x ), silicon nitride (SiN x ), and silicon acid.
  • Nitride (Silicon Oxynitride, SiO x N y ) It may be formed as a double layer in which an inorganic layer including at least one of them is stacked, or a multilayer in which these are alternately stacked.
  • the buffer layer BL, the first gate insulating layer GI, and the first interlayer insulating layer IL1 may be formed of one inorganic layer including the above-described insulating material.
  • the first interlayer insulating layer IL1 may be made of an organic insulating material such as polyimide (PI).
  • the second conductive layer and the third conductive layer include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may be formed as a single layer or multiple layers made of any one or an alloy thereof. However, the present invention is not limited thereto.
  • the via layer VIA is disposed on the third conductive layer.
  • the via layer VIA may include an organic insulating material, for example, an organic insulating material such as polyimide (PI), and may perform a surface planarization function.
  • PI polyimide
  • the first bank BNL1 may be directly disposed on the via layer VIA.
  • the first banks BNL1 are disposed in the emission area EMA of the sub-pixel SPXn, have a shape extending in the first direction DR1 , and may be spaced apart from each other in the second direction DR2 .
  • the first bank BNL1 includes the first bank part BN1 disposed on the left side of the second direction DR2 with respect to the center of the light emitting area EMA, and the center of the light emitting area EMA. It may include a second bank unit BN2 disposed on the right side, which is the other side of the second direction DR2 based on .
  • Each of the bank units BN1 and BN2 of the first bank BNL1 may have the same width, but is not limited thereto, and some of the bank units BN1 and BN2 may have different widths from the other bank units BN1 and BN2.
  • Each of the bank parts BN1 and BN2 of the first bank BNL1 has a length extending in the first direction DR1 is greater than a length of the light emitting area EMA surrounded by the second bank BNL2 in the first direction DR1 . can be small
  • the first bank BNL1 may form an island-shaped pattern extending in one direction with a narrow width in the emission area EMA of each sub-pixel SPXn on the entire surface of the display area DPA.
  • a plurality of light emitting devices ED may be disposed between the bank portions BN1 and BN2 spaced apart from each other.
  • the first bank BNL1 may have a structure in which at least a portion protrudes from the top surface of the via layer VIA.
  • the protruding portion of the first bank BNL1 may have an inclined or curved side surface.
  • each configuration of the first bank BNL1 may have a semicircle or semielliptical shape with a curved outer surface in cross-sectional view.
  • the first bank BNL1 may include an organic insulating material such as polyimide (PI), but is not limited thereto.
  • the plurality of electrodes RME are disposed in each sub-pixel SPXn in a shape extending in one direction.
  • the plurality of electrodes RME may extend in the first direction DR1 to cover the light emitting area EMA and the sub area SA of the sub pixel SPXn, and they may be spaced apart from each other in the second direction DR2 . and can be placed.
  • the display device 10 includes a first electrode RME1 and a second electrode RME2 disposed in each sub-pixel SPXn.
  • the first electrode RME1 is disposed on the left side with respect to the center of the emission area EMA, and the second electrode RME2 is spaced apart from the first electrode RME1 in the second direction DR2 to form the emission area EMA. is placed to the right of the center of the
  • a part of the first electrode RME1 may be disposed on the first bank part BN1
  • a part of the second electrode RME2 may be disposed on the second bank part BN2
  • the plurality of electrodes RME may be disposed on at least inclined side surfaces of each of the bank units BN1 and BN2.
  • a width measured in the second direction DR2 of the plurality of electrodes RME may be smaller than a width measured in the second direction DR2 of the bank parts BN1 and BN2.
  • Each of the electrodes RME may be disposed to cover at least one side surface of the first bank BNL1 to reflect light emitted from the light emitting device ED.
  • an interval between the plurality of electrodes RME in the second direction DR2 may be narrower than an interval between the bank portions BN1 and BN2 .
  • At least a portion of each of the electrodes RME may be directly disposed on the via layer VIA so that they may be disposed on the same plane.
  • first electrode RME1 and the second electrode RME2 have a first electrode contact hole CTD and a second electrode contact hole formed in portions overlapping the second bank BNL2 and the third direction DR3, respectively.
  • CTS may be connected to the third conductive layer.
  • the first electrode RME1 may contact the second electrode pattern CDP2 through the first electrode contact hole CTD penetrating the via layer VIA thereunder.
  • the second electrode RME2 may contact the second voltage line VL2 through the second electrode contact hole CTS penetrating the via layer VIA thereunder.
  • the first electrode RME1 is electrically connected to the first transistor T1 through the second electrode pattern CDP2 and the first electrode pattern CDP1 so that a first power voltage is applied
  • the second electrode RME2 is The second power voltage may be applied by being electrically connected to the second voltage line VL2 .
  • 5 illustrates that the first electrode contact hole CTD and the second electrode contact hole CTS are disposed under the second bank BNL2, but the present invention is not limited thereto.
  • Each of the electrode contact holes CTD and CTS may be disposed in the emission area EMA or the sub area SA.
  • the electrodes RME disposed in different sub-pixels SPXn adjacent in the first direction DR1 may be spaced apart from each other in the separation portion ROP of the sub-region SA.
  • the electrode RME may be disposed as one electrode line extending in the first direction DR1 , and may be formed by disposing the light emitting devices ED and then separating the electrode line in a subsequent process.
  • the electrode line may be utilized to generate an electric field in the sub-pixel SPXn to align the light emitting device ED during the manufacturing process of the display device 10 .
  • the electrode line may be separated from the separation part ROP to form a plurality of electrodes RME spaced apart from each other in the first direction DR1 .
  • the process of separating the electrode line may be performed after the process of forming the second insulating layer PAS2 to be described later, and as shown in FIG. 6 , the second insulating layer PAS2 is disposed in the separating part ROP as shown in FIG. 6 . it may not be
  • the second insulating layer PAS2 may be used as a mask pattern in a process of separating the electrode lines.
  • the plurality of electrodes RME may be electrically connected to the light emitting device ED.
  • Each of the electrodes RME may be connected to the light emitting device ED through connection electrodes CNE (CNE1, CNE2), which will be described later, and may transmit an electric signal applied from a lower conductive layer to the light emitting device ED.
  • Each of the plurality of electrodes RME may include a conductive material having high reflectivity.
  • the electrode RME is a material with high reflectivity and includes a metal such as silver (Ag), copper (Cu), aluminum (Al), or the like, or includes aluminum (Al), nickel (Ni), lanthanum (La), etc. It may be an alloy containing.
  • the electrode RME may reflect light emitted from the light emitting device ED and traveling to the side surface of the first bank BNL1 in an upper direction of each sub-pixel SPXn.
  • each electrode RME may further include a transparent conductive material.
  • each electrode RME may include a material such as ITO, IZO, ITZO, or the like.
  • each of the electrodes RME may have a structure in which one or more layers of a transparent conductive material and a metal layer having high reflectivity are stacked, or may be formed as a single layer including them.
  • each electrode RME may have a stacked structure such as ITO/Ag/ITO/, ITO/Ag/IZO, or ITO/Ag/ITZO/IZO.
  • the first insulating layer PAS1 is disposed on the via layer VIA, the first banks BNL1 , and the plurality of electrodes RME.
  • the first insulating layer PAS1 may be disposed on the via layer VIA to cover the plurality of electrodes RME and the first bank BNL1 .
  • the first insulating layer PAS1 may not be disposed in the separation portion ROP in which the electrodes RME adjacent to each other in the first direction DR1 in the sub area SA are spaced apart from each other.
  • the first insulating layer PAS1 may protect the plurality of electrodes RME and at the same time insulate the different electrodes RME from each other.
  • the first insulating layer PAS1 may prevent the light emitting device ED disposed thereon from being damaged by direct contact with other members.
  • a step may be formed such that a portion of the upper surface of the first insulating layer PAS1 is recessed between the electrodes RME spaced apart in the second direction DR2 .
  • the light emitting device ED may be disposed on the upper surface of the first insulating layer PAS1 having a step, and a space may be formed between the light emitting device ED and the first insulating layer PAS1 .
  • the first insulating layer PAS1 may include a plurality of contact portions CT1 and CT2 exposing a portion of the top surface of each electrode RME.
  • the plurality of contact portions CT1 and CT2 may pass through the first insulating layer PAS1 , and connection electrodes CNE, which will be described later, may contact the electrode RME exposed through the contact portions CT1 and CT2 .
  • the second bank BNL2 may be disposed on the first insulating layer PAS1 .
  • the second bank BNL2 may be disposed in a grid pattern including portions extending in the first direction DR1 and the second direction DR2 in a plan view, and may be disposed across the boundary of each sub-pixel SPXn. The neighboring sub-pixels SPXn may be distinguished.
  • the second bank BNL2 is disposed to surround the light emitting area EMA and the sub area SA, and regions divided by the second bank BNL2 and opened are the light emitting area EMA and the sub area SA, respectively. ) can be
  • the second bank BNL2 may have a predetermined height, and in some embodiments, a top surface of the second bank BNL2 may be higher than that of the first bank BNL1 , and the thickness thereof may be greater than that of the first bank BNL1 . and the second bank BNL2 may be equal to or larger than the second bank BNL2.
  • the second bank BNL2 may prevent ink from overflowing into the adjacent sub-pixel SPXn in an inkjet printing process during a manufacturing process of the display device 10 .
  • the second bank BNL2 may prevent inks in which different light emitting devices ED are dispersed in different sub-pixels SPXn from being mixed with each other.
  • the second bank BNL2 may include polyimide like the first bank BNL1 , but is not limited thereto.
  • the plurality of light emitting devices ED may be disposed on the first insulating layer PAS1 .
  • the light emitting device ED may include a plurality of layers disposed in a direction parallel to the top surface of the first substrate SUB.
  • the light emitting device ED of the display device 10 is disposed so that one extended direction is parallel to the top surface of the first substrate SUB, and a plurality of semiconductor layers included in the light emitting device ED are formed on the first substrate SUB. may be sequentially disposed along a direction parallel to the upper surface of the .
  • the present invention is not limited thereto.
  • the plurality of layers may be disposed in a direction perpendicular to the first substrate SUB.
  • the plurality of light emitting devices ED may be disposed on electrodes RME spaced apart from each other in the second direction DR2 between different bank parts BN1 and BN2 .
  • the light emitting devices ED may be disposed to be spaced apart from each other along the first direction DR1 in which the respective electrodes RME extend, and may be aligned substantially parallel to each other.
  • the light emitting device ED may have a shape extending in one direction, and the extended length may be longer than the shortest distance between the electrodes RME spaced apart in the second direction DR2 .
  • At least one end of the light emitting devices ED may be disposed on any one of the electrodes RME different from each other, or both ends of the light emitting devices ED may be disposed on different electrodes RME.
  • a direction in which each of the electrodes RME extends and a direction in which the light emitting device ED extends may be disposed to be substantially perpendicular to each other.
  • the present invention is not limited thereto, and the light emitting device ED may be disposed obliquely in a direction in which the respective electrodes RME extend.
  • the light emitting devices ED disposed in each sub-pixel SPXn may include a plurality of semiconductor layers, and may emit light of different wavelength bands according to materials of the semiconductor layers.
  • the present invention is not limited thereto, and the light emitting devices ED disposed in each sub-pixel SPXn may include a semiconductor layer of the same material to emit light of the same color.
  • the light emitting device ED may include semiconductor layers doped with different conductivity types and may be oriented so that one end thereof faces a specific direction by an electric field generated on the electrode RME. In the light emitting devices ED, a first end and a second end opposite to the one semiconductor layer may be defined.
  • a portion disposed on the first electrode RME1 may be a first end portion of the light emitting device ED, and a portion disposed on the second electrode RME2 may be a second end portion.
  • the display device 10 includes a greater number of electrodes RME, directions in which the first ends of the light emitting devices ED disposed on different electrodes RME may be different from each other.
  • the light emitting devices ED may be electrically connected to each other by contacting the connection electrodes CNE: CNE1 and CNE2. Since a portion of the semiconductor layer is exposed on the one end surface of the light emitting device ED, the exposed semiconductor layer may contact the connection electrode CNE. Each of the light emitting devices ED may be electrically connected to the conductive layers under the electrode RME and the via layer VIA through the connection electrodes CNE, and an electric signal may be applied to emit light in a specific wavelength band. .
  • the second insulating layer PAS2 may be disposed on the plurality of light emitting devices ED, the second bank BNL2 and the sub-region SA.
  • the second insulating layer PAS2 extends in the first direction DR1 and includes the first pattern portion PT1 disposed on the plurality of light emitting devices ED.
  • the first pattern part PT1 is disposed between the first bank part BN1 and the second bank part BN2 to partially surround the outer surface of the light emitting device ED, both sides of the light emitting device ED, or Both ends may not be covered.
  • the first pattern part PT1 may form a linear or island-shaped pattern in each sub-pixel SPXn in a plan view.
  • the first pattern portion PT1 of the second insulating layer PAS2 may protect the light emitting device ED and fix the light emitting devices ED in the manufacturing process of the display device 10 . Also, the first pattern portion PT1 may be disposed to fill a space between the light emitting device ED and the first insulating layer PAS1 thereunder.
  • the first pattern portion PT1 of the second insulating layer PAS2 may be formed by patterning an organic insulating material disposed entirely on the sub-pixel SPXn to expose both ends of the light emitting device ED.
  • the first direction DR1 is compared to the width measured in the second direction DR2 . can be long.
  • the thickness of the second insulating layer PAS2 eg, the thickness of the first pattern portion PT1
  • the first pattern portion PT1 having such a shape may be easily peeled off in a subsequent process.
  • the second insulating layer PAS2 has a larger width and includes a portion connected to the first pattern portion PT1. Peeling of (PT1) can be prevented.
  • the second insulating layer PAS2 may include a first base part BP1 disposed on the sub area SA and a second base part BP2 disposed on the second bank BNL2.
  • the first pattern part PT1 disposed in the emission area EMA may extend in the first direction DR1 to be connected to the first base part BP1 or the second base part BP2 .
  • the first base part BP1 may be disposed on the entire surface of the sub-region SA except for a portion of the sub-region SA in which the separation part ROP and connection electrodes CNE, which will be described later, are located.
  • the separation part ROP after forming the second insulating layer PAS2 , a process of separating the electrodes RME thereunder is performed, so that the first base part BP1 may not be disposed.
  • the connection electrodes CNE are disposed in a portion where the second insulating layer PAS2 is not disposed and are disposed over the side surface of the second insulating layer PAS2 , the first base part BP1 is connected to the connection electrode CNE. and may not overlap in the thickness direction of the first substrate SUB.
  • the second base part BP2 is disposed on the second bank BNL2 . Similar to the second bank BNL2 , the second base part BP2 includes a portion extending in the first direction DR1 , a portion extending in the second direction DR2 , and a portion protruding in the second direction DR2 . may include The second base part BP2 extends in the first direction DR1 between sub-pixels SPXn adjacent in the second direction DR2 and between sub-pixels SPXn adjacent in the first direction DR1 . may extend in the second direction DR2.
  • the second base part BP2 is protruded in the second direction DR2. It may be disposed on the second bank BNL2 . Since the connection electrodes CNE are disposed on the second bank BNL2 between the emission area EMA and the sub area SA of each sub-pixel SPXn, the second base part BP2 is connected to each connection electrode CNE. ) may protrude from a portion extending in the first direction DR1 to be disposed on the second bank BNL2 . At the boundary of the sub-region SA surrounded by the second bank BNL2 , the first base part BP1 and the second base part BP2 may be connected to each other in contact with each other.
  • Each of the first base part BP1 and the second base part BP2 may have the same thickness as the first pattern part PT1 , and a width measured in the second direction DR2 may be greater than that.
  • the first pattern part PT1 has a width shorter than the length of the light emitting element ED, but the first base part BP1 and the second base part BP2 have a width greater than or equal to that of the second bank BNL2. It may be the same as the area surrounded by the two banks BNL2.
  • the first base part BP1 and the second base part BP2 may be firmly disposed on the first insulating layer PAS1 and the second bank BNL2 without being peeled off. .
  • the first pattern part PT1 may extend in the first direction DR1 to extend beyond the second bank BNL2 to the first base part BP1 .
  • One side of the first pattern part PT1 in the first direction DR1 is connected to the second base part BP2 disposed on the second bank BNL2 , and the other side of the first pattern part DR1 is a sub area SA. may be extended to be connected to the first base part BP1.
  • the one side of the first pattern portion PT1 may be disposed at the boundary of the sub-pixel SPXn of the second base portion BP2 and may be connected to a portion extending in the second direction DR2 .
  • the first base part BP1 may have a connection pattern part CNP disposed between the connection electrodes CNE and connected to the first pattern part PT1 , and the first pattern part PT1 may have a first base part. It is connected to the BP1 and the second base part BP2 and may be supported by the base parts BP1 and BP2 so as not to be peeled off during a subsequent process.
  • the display device 10 may have a structure in which the second insulating layer PAS2 prevents peeling of the first pattern portion PT1 fixing the light emitting device ED, and in a subsequent process, the light emitting device ED and the second insulating layer PAS2 are formed. 1 It is possible to prevent a problem that the pattern part PT1 is separated and remains as a foreign material.
  • the first pattern portion PT1 , the first base portion BP1 , and the second base portion BP2 of the second insulating layer PAS2 are separately referred to, but these may be integrated into one.
  • each part of the second insulating layer PAS2 is divided according to an arrangement position and a connection relationship with other members, they may be formed in the same process to constitute one second insulating layer PAS2 .
  • connection electrodes CNE; CNE1 and CNE2 may be disposed on the plurality of electrodes RME and the light emitting devices ED. Also, the connection electrodes CNE are partially disposed on the side surface of the first pattern part PT1 of the second insulating layer PAS2, and are formed with the other connection electrode CNE and the first pattern part PT1 interposed therebetween. They may be spaced apart in two directions DR2. A portion of each of the connection electrodes CNE disposed on a side surface of the first pattern portion PT1 may have a height lower than a height of the first pattern portion PT1 , and the first pattern portion of the second insulating layer PAS2 . Connection electrodes CNE may not be disposed on the upper surface of PT1.
  • connection electrodes CNE In other portions of the second insulating layer PAS2 , for example, in the first base portion BP1 and the second base portion BP2 , also in contact with the connection electrodes CNE, from the side surface of each base portion BP1 and BP2 . It may be in contact with the connection electrodes CNE. That is, in an embodiment, the plurality of connection electrodes CNE may not overlap the second insulating layer PAS2 in the thickness direction.
  • the plurality of connection electrodes CNE may be formed to form a first connection electrode CNE1 and a second connection electrode CNE2 spaced apart from each other through a process of removing the material of the connection electrodes disposed on the second insulating layer PAS2. Also, the connection electrodes CNE may not be disposed on the second insulating layer PAS2 .
  • connection electrodes CNE may contact the light emitting element ED and the electrodes RME, respectively.
  • the connection electrode CNE may directly contact the semiconductor layer exposed on both end surfaces of the light emitting element ED, and the electrode RME through the contact portions CT1 and CT2 penetrating the first insulating layer PAS1. may be in contact with at least one of them. Both ends of the light emitting device ED may be electrically connected to the electrode RME through the plurality of connection electrodes CNE1 and CNE2 .
  • the first connection electrode CNE1 may have a shape extending in the first direction DR1 and may be disposed on the first electrode RME1 .
  • a portion of the first connection electrode CNE1 disposed on the first bank part BN1 overlaps the first electrode RME1 , and extends in the first direction DR1 therefrom to cross the second bank BNL2 . It may be disposed up to the sub area SA.
  • the first connection electrode CNE1 includes an extension having a large width in the second direction DR2 in the sub-region SA, and the extension connects the first contact portion CT1 exposing the top surface of the first electrode RME1. through the first electrode RME1.
  • the first connection electrode CNE1 is in contact with the first end of the light emitting devices ED and the first electrode RME1 to receive an electrical signal (eg, a first voltage line VL1 ) applied from the first transistor T1 . applied) to the light emitting device ED.
  • an electrical signal eg, a first voltage line VL1
  • VL1 first voltage line
  • the second connection electrode CNE2 may have a shape extending in the first direction DR1 and may be disposed on the second electrode RME2 .
  • a portion of the second connection electrode CNE2 disposed on the second bank part BN2 overlaps the second electrode RME2 , and extends in the first direction DR1 therefrom to cross the second bank BNL2 . It may be disposed up to the sub area SA.
  • the second connection electrode CNE2 includes an extension having a large width in the second direction DR2 in the sub area SA, and the extension connects the second contact portion CT2 exposing the top surface of the second electrode RME2 . through the second electrode RME2 .
  • the second connection electrode CNE2 may contact the second end of the light emitting devices ED and the second electrode RME2 to transmit an electrical signal applied from the second voltage line VL2 to the light emitting device ED.
  • the plurality of contact portions CT1 and CT2 do not overlap with the light emitting devices ED in the second direction DR2 in the region where the plurality of light emitting devices ED are disposed and in the first direction DR1 . may be formed spaced apart from each other. 4 and 7 , it is exemplified that the plurality of contact portions CT1 and CT2 are disposed in the sub area SA, but the present invention is not limited thereto, and the plurality of contact portions CT1 and CT2 emit light in the light emitting area EMA. It may be formed in a portion where the elements ED are not disposed.
  • the first connection electrode CNE1 and the second connection electrode CNE2 may be disposed to be spaced apart from each other in the second direction DR2 in a plan view.
  • the first connection electrode CNE1 and the second connection electrode CNE2 are disposed not to directly contact each other, and an electrical signal applied to each connection electrode CNE may flow through the light emitting device ED.
  • the first connection electrode CNE1 and the second connection electrode CNE2 are disposed on substantially the same layer.
  • the present invention is not limited thereto, and in some embodiments, the first connection electrode CNE1 and the second connection electrode CNE2 may be disposed on different layers, and another insulating layer may be further disposed between them.
  • connection electrodes CNE may include a conductive material.
  • it may include ITO, IZO, ITZO, aluminum (Al), and the like.
  • the connection electrode CNE may include a transparent conductive material, and light emitted from the light emitting device ED may pass through the connection electrode CNE and travel toward the electrodes RME.
  • the present invention is not limited thereto.
  • another insulating layer may be further disposed on the second insulating layer PAS2 and the plurality of connection electrodes CNE.
  • the insulating layer may serve to protect members disposed on the first substrate SUB from an external environment.
  • the above-described first insulating layer PAS1 may include an inorganic insulating material or an organic insulating material
  • the second insulating layer PAS2 may include an organic insulating material.
  • the present invention is not limited thereto.
  • FIG. 8 is a schematic diagram of a light emitting device according to an embodiment.
  • the light emitting device ED may be a light emitting diode, for example, the light emitting device ED has a size of nanometers to micrometers. and may be an inorganic light emitting diode made of an inorganic material.
  • the light emitting device ED may be aligned between the two electrodes in which polarities are formed when an electric field is formed in a specific direction between the two electrodes facing each other.
  • the light emitting device ED may have a shape extending in one direction.
  • the light emitting device ED may have a shape such as a cylinder, a rod, a wire, or a tube.
  • the shape of the light emitting element (ED) is not limited thereto, and the light emitting element ( ED) may have various forms.
  • the light emitting device ED may include a semiconductor layer doped with an arbitrary conductivity type (eg, p-type or n-type) impurity.
  • the semiconductor layer may emit an electric signal applied from an external power source to emit light in a specific wavelength band.
  • the light emitting device ED may include a first semiconductor layer 31 , a second semiconductor layer 32 , a light emitting layer 36 , an electrode layer 37 , and an insulating layer 38 .
  • the first semiconductor layer 31 may be an n-type semiconductor.
  • the first semiconductor layer 31 may include a semiconductor material having a chemical formula of AlxGayIn1-x-yN (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x+y ⁇ 1).
  • the first semiconductor layer 31 may be any one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with n-type.
  • the n-type dopant doped in the first semiconductor layer 31 may be Si, Ge, Sn, Se, or the like.
  • the second semiconductor layer 32 is disposed on the first semiconductor layer 31 with the light emitting layer 36 interposed therebetween.
  • the second semiconductor layer 32 may be a p-type semiconductor, and the second semiconductor layer 32 is composed of AlxGayIn1-x-yN (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x+y ⁇ 1). and a semiconductor material having a chemical formula.
  • the second semiconductor layer 32 may be any one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with p-type.
  • the p-type dopant doped in the second semiconductor layer 32 may be Mg, Zn, Ca, Ba, or the like.
  • the drawing shows that the first semiconductor layer 31 and the second semiconductor layer 32 are configured as one layer, the present invention is not limited thereto.
  • the first semiconductor layer 31 and the second semiconductor layer 32 may further include a larger number of layers, for example, a clad layer or a TSBR (Tensile strain barrier reducing) layer. may be
  • the light emitting layer 36 is disposed between the first semiconductor layer 31 and the second semiconductor layer 32 .
  • the light emitting layer 36 may include a material having a single or multiple quantum well structure.
  • the light emitting layer 36 may include a material having a multi-quantum well structure, it may have a structure in which a plurality of quantum layers and a well layer are alternately stacked.
  • the light emitting layer 36 may emit light by combining electron-hole pairs according to an electric signal applied through the first semiconductor layer 31 and the second semiconductor layer 32 .
  • the emission layer 36 may include a material such as AlGaN or AlGaInN.
  • the quantum layer may include a material such as AlGaN or AlGaInN
  • the well layer may include a material such as GaN or AlInN.
  • the light emitting layer 36 may have a structure in which a type of semiconductor material having a large band gap energy and a semiconductor material having a small band gap energy are alternately stacked with each other, and groups 3 to 5 are different according to the wavelength band of the emitted light. It may also include semiconductor materials.
  • the light emitted by the light emitting layer 36 is not limited to light of a blue wavelength band, and in some cases, light of a red and green wavelength band may be emitted.
  • the electrode layer 37 may be an ohmic connection electrode. However, the present invention is not limited thereto, and may be a Schottky connection electrode.
  • the light emitting device ED may include at least one electrode layer 37 .
  • the light emitting device ED may include one or more electrode layers 37 , but the present invention is not limited thereto and the electrode layers 37 may be omitted.
  • the electrode layer 37 may reduce resistance between the light emitting element ED and the electrode or the connection electrode when the light emitting element ED is electrically connected to an electrode or a connection electrode in the display device 10 .
  • the electrode layer 37 may include a conductive metal.
  • the electrode layer 37 may include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), ITO, IZO, and ITZO.
  • the insulating film 38 is disposed so as to surround the outer surfaces of the plurality of semiconductor layers and the electrode layers described above.
  • the insulating layer 38 may be disposed to surround at least the outer surface of the light emitting layer 36 , and both ends of the light emitting device ED in the longitudinal direction may be exposed.
  • the insulating layer 38 may be formed to have a round top surface in cross-section in a region adjacent to at least one end of the light emitting device ED.
  • the insulating layer 38 is formed of materials having insulating properties, for example, silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide ( AlO x ) and the like.
  • silicon oxide (SiO x ) silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide ( AlO x ) and the like.
  • the insulating film 38 is formed as a single layer, but the present invention is not limited thereto, and in some embodiments, the insulating film 38 may be formed in a multi-layered structure in which a plurality of layers are stacked.
  • the insulating layer 38 may function to protect the members.
  • the insulating layer 38 may prevent an electrical short that may occur in the light emitting layer 36 when it is in direct contact with an electrode through which an electrical signal is transmitted to the light emitting device ED.
  • the insulating layer 38 may prevent a decrease in the luminous efficiency of the light emitting device ED.
  • the outer surface of the insulating film 38 may be surface-treated.
  • the light emitting device ED may be sprayed onto the electrode in a state of being dispersed in a predetermined ink to be aligned.
  • the surface of the insulating layer 38 may be treated with hydrophobicity or hydrophilicity.
  • the display device 10 may have a structure in which the second insulating layer PAS2 prevents peeling of the first pattern portion PT1 disposed on the light emitting devices ED.
  • the structure and shape of the second insulating layer PAS2 may be variously modified according to the number of electrodes RME disposed in each of the sub-pixels SPXn.
  • various embodiments of the display device 10 will be described with further reference to other drawings.
  • FIG. 9 is a plan view illustrating one sub-pixel of a display device according to another exemplary embodiment.
  • FIG. 10 is a cross-sectional view taken along line Q3-Q3' of FIG. 9 .
  • 11 is an enlarged view of a portion A2 of FIG. 9 .
  • the display device 10_1 may include a larger number of electrodes RME_1 for each sub-pixel SPXn, and is disposed in each sub-pixel SPXn.
  • the number of light emitting devices ED may increase.
  • the second insulating layer PAS2_1 further includes, in addition to the plurality of pattern parts PT1 and PT2 , other pattern parts SP1 connected to each of the pattern parts PT1 and PT2 to prevent peeling thereof. can do.
  • the first bank BNL1_1 may further include a third bank unit BN3 having a width different from that of the first bank unit BN1 and the second bank unit BN2 .
  • the third bank part BN3 may be disposed between the first bank part BN1 and the second bank part BN2 and may have a shape extending in the first direction DR1 .
  • the first bank part BN1 , the second bank part BN2 , and the third bank part BN3 have the same length extending in the first direction DR1 , but have a width measured in the second direction DR2 .
  • the third bank unit BN3 may be larger than other bank units.
  • the third bank unit BN3 may be disposed to be spaced apart from the first bank unit BN1 and the second bank units BN2 in the second direction DR2 .
  • the third bank part BN3 may have a width greater than that of the first bank part BN1 so that a third electrode RME3 to be described later may be disposed.
  • the light emitting devices ED may be respectively disposed between the first bank unit BN1 and the third bank unit BN3 and between the second bank unit BN2 and the third bank unit BN3 .
  • the first electrode RME1 may be disposed on the first bank part BN1
  • the second electrode RME2 may be disposed on the second bank part BN2 .
  • a description thereof is the same as described above with reference to FIGS. 2 and 3 .
  • the third electrode RME3 is disposed on the third bank part BN3 .
  • the third electrode RME3 may extend in the first direction DR1 between the first electrode RME1 and the second electrode RME2 to cover the emission area EMA and the sub area SA.
  • the width of the third electrode RME3 may be greater than that of the first electrode RME1 and the second electrode RME2 , and may be greater than the width of the third bank part BN3 .
  • the third electrode RME3 is disposed to cover both side surfaces of the third bank unit BN3 , and may face the first electrode RME1 and the second electrode RME2 respectively in the second direction DR2 to face each other. have.
  • the third electrode RME3 may be connected to the third conductive layer under the via layer VIA similarly to the first electrode RME1 .
  • the third electrode RME3 may be connected to the second voltage line VL2 through the second electrode contact hole CTS formed in a portion overlapping the second bank BNL2 in the thickness direction.
  • the second electrode RME2 may not be connected to the third conductive layer.
  • the second electrode RME2 may be connected to the second connection electrode CNE2 , and an electrical signal flowing along the light emitting devices ED may be applied thereto. As will be described later, the second electrode RME2 and the second connection electrode CNE2 may provide electrical connection paths between different light emitting devices ED.
  • the light emitting devices ED may be disposed between the first bank part BN1 and the third bank part BN3 and between the third bank part BN3 and the second bank part BN2 .
  • the first light emitting device ED1 disposed between the first bank part BN1 and the third bank part BN3 has a first end disposed on the first electrode RME1 and a second end disposed on the third electrode ( RME1 ). may be disposed on one side of the RME3).
  • the second light emitting device ED2 disposed between the third bank part BN3 and the second bank part BN2 has a first end disposed on the second electrode RME2 and a second end disposed on the third electrode ( RME2 ). may be disposed on the other side of RME3).
  • the first light emitting device ED1 and the second light emitting device ED2 may have a direction opposite to that of the first end thereof.
  • the second insulating layer PAS2_1 includes a first pattern part PT1 and a second pattern part disposed on each of the light emitting devices ED between the bank parts BN1 , BN2 , and BN3 of the first bank BNL1 . (PT2).
  • the first pattern part PT1 and the second pattern part PT2 may each extend in the first direction DR1 to cover the first light emitting devices ED1 and the second light emitting devices ED2 . These may be fixed while enclosing the plurality of light emitting devices ED.
  • the first pattern part PT1 and the second pattern part PT2 may have a smaller width compared to the length and thickness, and the second insulating layer PAS2_1 may be formed of It may have a structure capable of preventing peeling.
  • the second insulating layer PAS2_1 includes a first support pattern part SP1 connected to at least some of the plurality of pattern parts PT1 and PT2 and the pattern parts PT1 and PT2 as first
  • a plurality of bridge parts BR1 and BR2 connected to the support pattern part SP1 or the second base part BP2 may be further included.
  • the first pattern part PT1 extends in the first direction DR1 , so that one side of the first direction DR1 is connected to a part extending in the second direction DR2 of the second base part BP2 , the first direction (DR1) The other side may be connected to the first base portion (BP1).
  • the first pattern part PT1 may be connected to the second base part BP2 through the first bridge part BR1 .
  • the first bridge part BR1 may have a shape extending in the second direction DR2 , and may be connected to a portion of the second base part BP2 extending in the first direction DR1 and the first pattern part PT1 . have.
  • the first bridge part BR1 may be disposed to be spaced apart from one end disposed in the light emitting area EMA among both ends of the first connection electrode CNE1 in the first direction DR1 .
  • the first bridge part BR1 may be disposed in contact with the one end of the first connection electrode CNE1 according to process conditions when the first connection electrode CNE1 is formed.
  • the first pattern part PT1 is formed by the first bridge part BR1 extending in the second direction DR2 in addition to the base parts BP1 and BP2 positioned on both sides of the first direction DR1 . It can be supported so as not to be peeled off during a subsequent process.
  • the second pattern part PT2 may also extend in the first direction DR1 , and the other side of the second pattern part PT2 may be connected to the first base part BP1 .
  • the first connection part CN_B1 of the third connection electrode CNE3 is disposed on one side of the first direction DR1 , it may not be directly connected to the second base part BP2 .
  • the second pattern part PT2 may be connected to the first support pattern part SP1 disposed between the first pattern part PT1 and have a structure in which peeling is prevented.
  • the first support pattern part SP1 may be disposed to extend in the first direction DR1 on the third bank part BN3 and the third electrode RME3 .
  • the first support pattern part SP1 is disposed between the first extension part CN_E1 and the second connection electrode CNE2 of the third connection electrode CNE3, and they are respectively disposed on the side surface of the first support pattern part SP1 and the second connection electrode CNE2. can be spaced apart.
  • both sides of the first support pattern part SP1 also have the first extension part CN_E1 and the second connection electrode CNE2 according to the forming process conditions of the connection electrodes CNE_1 .
  • a connection pattern portion disposed on the second bank BNL2 is positioned on the other side of the first pattern portion PT1 and the first support pattern portion SP1 in the first direction DR1, and through this, the first base portion BP1 and can be connected
  • the second bridge part BR2 has a shape extending in the second direction DR2 , and may be connected to the first support pattern part SP1 and the second pattern part PT2 .
  • the second bridge part BR2 includes one end disposed in the emission area EMA among both ends of the second connection electrode CNE2 in the first direction DR1 and the first connection part CN_B1 of the third connection electrode CNE3 . may be disposed to be spaced apart from each other. Alternatively, the second bridge part BR2 may contact the second connection electrode CNE2 and the first connection part CN_B1 .
  • the first pattern portion PT1 includes a second bridge portion BR2 and a first portion extending in the second direction DR2 in addition to the first base portion BP1 located on the other side of the first direction DR1 . It may be supported so as not to be peeled off during a subsequent process by the support pattern part SP1 .
  • the first support pattern part SP1 and the plurality of bridge parts BR1 and BR2 are disposed in the light emitting area EMA.
  • the first support pattern part SP1 and the plurality of bridge parts BR1 and BR2 are formed in the respective pattern parts PT1 and PT2 even in a narrow space within the emission area EMA.
  • ) can be wider than 11 , according to an exemplary embodiment, the width W3 measured in the second direction DR2 of the first support pattern part SP1 and the first direction DR1 of the bridge parts BR1 and BR2 .
  • the first width W1 of the pattern portions PT1 and PT2 may be greater than the width W1 of the pattern portions PT1 and PT2, respectively.
  • the first width W1 of each of the pattern portions PT1 and PT2 may be smaller than the length of the light emitting device ED.
  • the second width W2 of the bridge portions BR1 and BR2 may be greater than the first width W1 of the pattern portions PT1 and PT2 and the length of the light emitting devices ED.
  • the length of the bridge parts BR1 and BR2 extending in the second direction DR2 is shorter than the length of the pattern parts PT1 and PT2 in the first direction DR1 , the first of the bridge parts BR1 and BR2 .
  • a difference between a width in the direction DR1 and a length in the second direction DR2 may be smaller than that of the pattern portions PT1 and PT2 . Accordingly, the bridge parts BR1 and BR2 may withstand a subsequent process without being peeled off from the pattern parts PT1 and PT2 , and the pattern parts PT1 and PT2 may also be fixed.
  • the first support pattern part SP1 extends in the first direction DR1 similarly to the pattern parts PT1 and PT2 , it has a larger width W3 to prevent separation of the pattern parts PT1 and PT2 .
  • the third width W3 of the first support pattern part SP1 may be greater than the second width W2 of the bridge parts BR1 and BR2 .
  • the display device 10_1 may include a larger number of electrodes RME_1 and connection electrodes CNE_1 .
  • the second insulating layer PAS2_1 includes more pattern parts PT1 and PT2 , and includes the first support pattern part SP1 and the plurality of bridge parts BR1 and BR2 , and includes the pattern part PT1 . , PT2) can be prevented from peeling.
  • the plurality of connection electrodes CNE_1 includes a first connection electrode CNE1 disposed on the first electrode RME1 , a second connection electrode CNE2 disposed on the other side of the third electrode RME3 , and a third A third connection electrode CNE3 disposed over one side of the electrode RME3 and the second electrode RME2 may be included.
  • the first connection electrode CNE1 may contact the first electrode RME1 and the first end of the first light emitting device ED1 .
  • the first connection electrode CNE1 may contact the first electrode RME1 through the first contact portion CT1 penetrating the first insulating layer PAS1 .
  • the second connection electrode CNE2 may contact the third electrode RME3 and the second end of the second light emitting device ED2 .
  • the second connection electrode CNE2 may contact the third electrode RME3 through the third contact portion CT3 penetrating the first insulating layer PAS1 .
  • the first connection electrode CNE1 and the second connection electrode CNE2 may extend in the first direction DR1 and extend from the emission area EMA to the sub area SA.
  • the third connection electrode CNE3 is disposed on one side of the third electrode RME3 and is disposed on the first extension CN_E1 and the second electrode RME2 extending in the first direction DR1 to form the first It may include a second extension part CN_E2 extending in the direction DR1 , and a first connection part CN_B1 connecting the first extension part CN_E1 and the second extension part CN_E2 .
  • the first extension CN_E1 and the second extension CN_E2 of the third connection electrode CNE3 may be spaced apart from each other in the second direction DR2 with the second connection electrode CNE2 interposed therebetween.
  • the first extension part CN_E1 may face the first connection electrode CNE1 and spaced apart and face the second extension part CN_E2 to face the second connection electrode CNE2.
  • the first extension CN_E1 may contact the second end of the first light emitting element ED1
  • the second extension CN_E2 may contact the first end of the second light emitting element ED2 .
  • the first connection part CN_B1 may have a shape extending in the second direction DR2 from the sub area SA, and may connect the first extension part CN_E1 and the second extension part CN_E2 to each other.
  • the first connection part CN_B1 is disposed between the first support pattern part SP1 and the second base part BP2 of the second insulating layer PAS2_1 and may be spaced apart from side surfaces thereof.
  • the second extension part CN_E2 of the second connection electrode CNE3 is disposed to extend to the sub-region SA and passes through the third contact part CT3 penetrating the first insulating layer PAS1 to the third electrode ( RME3) (shown in FIG. 12).
  • a first end of the first light emitting device ED1 is electrically connected to the first electrode RME1 through a first connection electrode CNE1, and a second end of the second light emitting device ED2 has a second connection electrode ( It may be electrically connected to the third electrode RME3 through CNE2 .
  • the second end of the first light emitting element ED1 and the first end of the second light emitting element ED2 may be connected to each other in series through the third connection electrode CNE3 .
  • the light emitting devices EDs ED1 and ED2 having different positions with respect to the third bank unit BN3 may have a series connection structure.
  • the display device 10_1 includes a larger number of light emitting devices ED for each sub-pixel SPXn and may form a series connection therebetween. The amount of light emitted per sugar may be increased.
  • FIG. 12 is a plan view illustrating one sub-pixel of a display device according to another exemplary embodiment.
  • 13 is a plan view illustrating a relative arrangement of a first bank and a second bank, a plurality of connection electrodes, and a second insulating layer disposed in one sub-pixel of FIG. 12 .
  • 14 is a cross-sectional view taken along line Q4-Q4' of FIG. 12 .
  • the display device 10_2 may include a larger number of electrodes RME_2 for each sub-pixel SPXn.
  • the second insulating layer PAS2_2 may further include a greater number of pattern portions PT1 , PT2 , PT3 , and PT4 and bridge portions BR1 , BR2 , BR3 , BR4 , and BR5 .
  • each electrode RME_2 ; RME1 , RME2 , RME3 , and RME4 are disposed for each sub-pixel SPXn, and light emitting devices ED; ED1 , ED2 , ED3, ED4 and ED5 disposed between them are disposed.
  • ) may include five connection electrodes (CNE_2; CNE1, CNE2, CNE3, CNE4, CNE5) for a series connection configuration.
  • the plurality of light emitting devices ED may be connected in series with each other according to the connection electrodes CNE_2 connected to both ends.
  • the second insulating layer PAS2_2 may include a plurality of pattern portions PT1 , PT2 , PT3 , and PT4 for fixing each light emitting device ED, and may have a structure to prevent separation thereof.
  • overlapping content will be omitted and the differences will be mainly described.
  • a third electrode RME3_2 , a second electrode RME2_2 , and a fourth electrode RME4_2 are sequentially disposed along the second direction DR2 with respect to the first electrode RME1_2 .
  • Each of the electrodes RME_2 may extend in the first direction DR1 and may be disposed over the emission area EMA and the sub area SA.
  • the first electrode RME1 is disposed on the first bank part BN1
  • the third electrode RME3 is disposed on one side of the third bank part BN3
  • the second electrode RME2 may be disposed on the other side of the third bank part BN3
  • the fourth electrode RME4 may be disposed on the second bank part BN2 .
  • Each of the electrodes RME_2 is spaced apart from each other in the second direction DR2 , the first electrode RME1 and the third electrode RME3 face each other, and the second electrode RME2 and the fourth electrode RME4 connect to each other. can oppose
  • the first electrode RME1 and the second electrode RME2 have a first electrode contact hole CTD and a second electrode contact hole CTS passing through the via layer VIA at portions overlapping the second bank BNL2, respectively. ) may be directly connected to the third conductive layer.
  • the third electrode RME3 and the fourth electrode RME4 may not be directly connected to the third conductive layer.
  • the third electrode RME3 and the fourth electrode RME4 are respectively connected to the third connection electrode CNE3 and the fifth connection electrode CNE5 , and electric signals flowing along the light emitting devices ED may be applied thereto.
  • the third electrode RME3 and the fourth electrode RME4 together with the third connection electrode CNE3 and the fifth connection electrode CNE5 provide electrical connection paths between different light emitting devices ED. can
  • the first light emitting devices ED1 and the third light emitting devices ED3 are disposed between the first bank part BN1 and the third bank part BN3, and the third bank part BN3 ) and the second bank unit BN2 , the second light emitting devices ED2 and the fourth light emitting devices ED4 may be disposed.
  • the first light emitting elements ED1 and the second light emitting elements ED2 are disposed adjacent to the sub area SA of the corresponding sub pixel SPXn in the light emitting area EMA of each sub pixel SPXn, and the third The light emitting devices ED3 and the fourth light emitting devices ED4 may be disposed adjacent to the sub area SA of the other sub pixel SPXn in the light emitting area EMA of each sub pixel SPXn. That is, the first light emitting elements ED1 and the second light emitting elements ED2 are disposed below the other side of the first direction DR1 in the light emitting area EMA, and the third light emitting elements ED3 and the fourth light emitting element ED3 are provided.
  • the devices ED4 may be disposed on one side of the light emitting area EMA in the first direction DR1 .
  • each of the light emitting devices ED is not classified according to a position disposed in the light emitting area EMA, but may be classified according to a connection relationship with the connection electrode CNE_2 to be described later.
  • Each of the light emitting devices ED may have different connecting electrodes CNE_2 contacting both ends according to the arrangement structure of the connecting electrodes CNE_2 , and different light emitting devices ED according to the type of the contacting connecting electrodes CNE_2 . ) can be distinguished.
  • the first light emitting device ED1 and the third light emitting device ED3 may have a first end disposed on the first electrode RME1 and a second end disposed on the third electrode RME3 .
  • the second light emitting device ED2 and the fourth light emitting device ED4 may have a first end disposed on the fourth electrode RME4 and a second end disposed on the second electrode RME2 .
  • the first light emitting device ED1 and the third light emitting device ED3 may have a different direction from that of the second light emitting device ED2 and the fourth light emitting device ED4 .
  • the plurality of connection electrodes CNE_2 includes a plurality of electrodes ( A third connection electrode CNE3 , a fourth connection electrode CNE4 , and a fifth connection electrode CNE5 disposed across the RME_2s may be further included.
  • each of the first connection electrode CNE1 and the second connection electrode CNE2 may have a relatively short length extending in the first direction DR1 .
  • the first connection electrode CNE1 and the second connection electrode CNE2 may be disposed below the center of the emission area EMA.
  • the first connection electrode CNE1 and the second connection electrode CNE2 are disposed over the light emitting area EMA and the sub area SA of the corresponding sub pixel SPXn, and are first contacts formed in the sub area SA, respectively.
  • the first electrode RME1 and the second electrode RME2 may be in contact with the portion CT1 and the second contact portion CT2 .
  • the third connection electrode CNE3 includes a first extension portion CN_E1 disposed on the third electrode RME3 , a second extension portion CN_E2 disposed on the first electrode RME1 , and a first extension portion ( A first connection part CN_B1 connecting the CN_E1 and the second extension part CN_E2 may be included.
  • the first extension part CN_E1 is spaced apart from the first connection electrode CNE1 in the second direction DR2
  • the second extension part CN_E2 faces the first connection electrode CNE1 in the first direction DR1 . can be spaced apart.
  • the first extension part CN_E1 may be disposed below the emission area EMA of the corresponding sub-pixel SPXn, and the second extension part CN_E2 may be disposed above the emission area EMA.
  • the first extension part CN_E1 may be disposed over the emission area EMA and the sub area SA and may be connected to the third electrode RME3 through the third contact part CT3 formed in the sub area SA.
  • the first connection part CN_B1 may be disposed across the first electrode RME1 and the third electrode RME3 from the center of the emission area EMA.
  • the third connection electrode CNE3 may generally have a shape extending in the first direction DR1 , and may have a shape that is bent in the second direction DR2 and then extends again in the first direction DR1 .
  • the fourth connection electrode CNE4 includes a third extension portion CN_E3 disposed on the third electrode RME3 , a fourth extension portion CN_E4 disposed on the fourth electrode RME4 , and a third extension portion ( A second connection part CN_B2 connecting the CN_E3 and the fourth extension part CN_E4 may be included.
  • the third extension part CN_E3 is spaced apart from the second extension part CN_E2 of the third connection electrode CNE3 in the second direction DR2 and faces, and the fourth extension part CN_E4 is a fifth connection electrode (to be described later) It may be spaced apart from the sixth extension CN_E6 of the CNE5 in the first direction DR1 .
  • the third extension part CN_E3 and the fourth extension part CN_E4 are respectively disposed above the light emitting area EMA, and the second connection part CN_B2 includes the third electrode RME3, the second electrode RME2, and the second electrode RME2. It may be disposed across the four electrodes RME4.
  • the fourth connection electrode CNE4 may be disposed to surround the fifth extension part CN_E5 of the fifth connection electrode CNE5 in a plan view.
  • the fifth connection electrode CNE5 is a fifth extension CN_E5 disposed on the second electrode RME2 , a sixth extension CN_E6 disposed on the fourth electrode RME4 , and a fifth extension CN_E5 . ) and a third connection part CN_B3 connecting the sixth extension part CN_E6.
  • the fifth extension part CN_E5 includes the fourth extension part CN_E4 and the second connection part CN_E4 of the fourth connection electrode CNE4.
  • the sixth extension part CN_E6 may be spaced apart from each other in the direction DR2, and the sixth extension part CN_E6 may be spaced apart from the second connection electrode CNE2 in the second direction DR2.
  • the fifth extension part CN_E5 has a corresponding sub-pixel SPXn ) of the light emitting area EMA
  • the sixth extension CN_E6 may be disposed below the light emitting area EMA
  • the sixth extension CN_E6 includes the light emitting area EMA and the sub area It is disposed over SA and may be connected to the fourth electrode RME4 through a fourth contact portion CT4 formed in the sub area SA.
  • the third connection portion CN_B3 is adjacent to the center of the light emitting area EMA. Thus, it may be disposed across the second electrode RME2 and the fourth electrode RME4.
  • the fifth connection electrode CNE5_2 has a shape that generally extends in the first direction DR1, and extends in the second direction DR2. After being bent, it may have a shape extending in the first direction DR1 again.
  • the first connection electrode CNE1 and the second connection electrode CNE2 are first type connection electrodes in contact with the first electrode RME1 and the second electrode RME2 directly connected to the third conductive layer, respectively, and the third connection electrode
  • the electrode CNE3 and the fifth connection electrode CNE5 are a second type connection electrode in contact with the third electrode RME3 and the fourth electrode RME4 that are not directly connected to the third conductive layer, and the fourth connection electrode CNE4 may be a third type connection electrode that does not contact the electrodes RME_2 .
  • the plurality of light emitting devices ED may be divided into different light emitting devices ED according to the connection electrode CNE_2 having both ends in contact.
  • the first light emitting element ED1 may have a first end in contact with the first connection electrode CNE1 , and a second end in contact with the first extension CN_E1 of the third connection electrode CNE3 .
  • the second light emitting device ED2 may have a first end in contact with the sixth extension CN_E6 of the fifth connection electrode CNE5 , and a second end in contact with the second connection electrode CNE2 .
  • the third light emitting element ED3 has a first end in contact with the second extension CN_E2 of the third connection electrode CNE3 and a second end of the third extension CN_E3 of the fourth connection electrode CNE4.
  • the fourth light emitting element ED4 has a first end in contact with the fourth extension CN_E4 of the fourth connection electrode CNE4 and a second end of the fifth extension CN_E5 of the fifth connection electrode CNE5. can be contacted with
  • the first end of the first light emitting element ED1 is electrically connected to the first electrode RME1 directly connected to the third conductive layer, and the second end of the second light emitting element ED2 is also directly connected to the third conductive layer. It may be electrically connected to the second electrode RME2 .
  • the first light emitting element ED1 and the third light emitting element ED3 are electrically connected to each other through a third connection electrode CNE3 , and the third light emitting element ED3 and the fourth light emitting element ED4 are connected to a fourth connection Through the electrode CNE4 , the fourth light emitting element ED4 and the second light emitting element ED2 may be electrically connected through the fifth connection electrode CNE5 .
  • the first light emitting device ED1 , the third light emitting device ED3 , the fourth light emitting device ED4 , and the second light emitting device ED2 may be connected in series to each other through the plurality of connection electrodes CNE_2 .
  • the display device 10_2 according to the present exemplary embodiment may include a larger number of light emitting devices ED for each sub-pixel SPXn and form a series connection therebetween, so that the amount of light per unit area may be further increased. .
  • the second insulating layer PAS2_2 has a larger number of pattern portions PT1 , PT2 , and PT3 . , PT4) may be included.
  • the second insulating layer PAS2_2 has a structure capable of preventing separation of each of the pattern portions PT1, PT2, PT3, and PT4, and has a larger number of the bridge portions BR1, BR2, BR3, BR4, BR5. ) may include
  • any one of the first pattern parts PT1_2 is connected to the pattern part disposed on the second sub-bank SBL2 , and they may be surrounded by connection electrodes.
  • 17 is an enlarged view of a portion A5 of FIG. 12 . 15 to 17 illustrate portions in which different pattern portions PT1 , PT2 , PT3 , and PT4 of the second insulating layer PAS2_2 are connected to the base portions BP1 and BP2 or the bridge portion.
  • the second insulating layer PAS2_2 includes a first pattern part PT1 and a second light emitting device disposed on the first light emitting devices ED1.
  • a pattern part PT4 may be included.
  • the first pattern part PT1 and the third pattern part PT3 are disposed between the first bank part BN1 and the third bank part BN3, respectively, and the first connection part CN_B1 of the third connection electrode CNE3 ) may be disposed to be spaced apart from each other in the first direction DR1 .
  • the first pattern part PT1 and the third pattern part PT3 may be disposed in contact with the first connection part CN_B1, respectively.
  • the other side of the first pattern part PT1 in the first direction DR1 crosses the second bank BNL2 and is connected to the first base part BP1 , and is connected to the third pattern part PT3 in the first direction DR1 .
  • the side may be connected to the second base part BP2 disposed on the second bank BNL2 .
  • the second pattern part PT2 and the fourth pattern part PT4 are respectively disposed between the third bank part BN3 and the second bank part BN2 , and the third connection part CN_B3 of the fifth connection electrode CNE5 . ) may be disposed to be spaced apart from each other in the first direction DR1 .
  • the second pattern part PT2 and the fourth pattern part PT4 may be disposed in contact with the third connection part CN_B3, respectively.
  • the other side of the second pattern part PT2 in the first direction DR1 crosses the second bank BNL2 and is connected to the first base part BP1
  • one side of the fourth pattern part PT4 in the first direction DR1 crosses the second bank BNL2 .
  • the side may be connected to the second base part BP2 disposed on the second bank BNL2 .
  • the first support pattern part SP1 is disposed on the third bank part BN3 similarly to the embodiment of FIG. 9 .
  • the first support pattern part SP1 may partially overlap the second electrode RME2 and the third electrode RME3, respectively.
  • the first support pattern part SP1 may extend in the first direction DR1 to be connected to the connection pattern part CNP of the first base part BP1 disposed in the sub area SA.
  • the second insulating layer PAS2_2 may include a plurality of bridge parts connecting each of the pattern parts PT1 , PT2 , PT3 , and PT4 to the second base part BP2 or the first support pattern part SP1 .
  • the first bridge part BR1 may be connected to a portion extending in the first direction DR1 among the first pattern part PT1 and the second base part BP2 .
  • the first bridge part BR1 may be disposed between the first connection electrode CNE1 and the second extension part CN_E2 of the third connection electrode CNE3 to extend in the second direction DR2 .
  • the first bridge part BR1 may be disposed to be spaced apart from the first connection electrode CNE1 and the third connection electrode CNE3 .
  • the second bridge part BR2 may be connected to the second pattern part PT2 and the first support pattern part SP1 .
  • the second bridge part BR2 may be disposed between the second connection electrode CNE2 and the fifth extension part CN_E5 of the fifth connection electrode CNE5 to extend in the second direction DR2 .
  • the second bridge part BR2 may be disposed to be spaced apart from the second connection electrode CNE2 and the fifth connection electrode CNE5 .
  • the third bridge part BR3 may be connected to the third pattern part PT3 and the first support pattern part SP1 .
  • the third bridge part BR3 is disposed between the first extension part CN_E1 of the third connection electrode CNE3 and the third extension part CN_E3 of the fourth connection electrode CNE4 in the second direction DR2 . It may have an elongated shape.
  • the third bridge part BR3 may be disposed to be spaced apart from the third connection electrode CNE3 and the fourth connection electrode CNE4 .
  • the fourth bridge part BR4 may be connected to the fourth pattern part PT4 and the first support pattern part SP1 .
  • the fourth bridge part BR4 is disposed between the second connection part CN_B2 of the fourth connection electrode CNE4 and the fifth extension part CN_E5 of the fifth connection electrode CNE5 and extends in the second direction DR2 . may have a given shape.
  • the fourth bridge part BR4 may be disposed to be spaced apart from the fourth connection electrode CNE4 and the fifth connection electrode CNE5 .
  • the fifth bridge part BR5 may be connected to a portion extending in the first direction DR1 among the fourth pattern part PT4 and the second base part BP2 .
  • the fifth bridge part BR5 is disposed between the fourth extension part CN_E4 of the fourth connection electrode CNE4 and the sixth extension part CN_E6 of the fifth connection electrode CNE5 in the second direction DR2 . It may have an elongated shape.
  • the fifth bridge part BR5 may be disposed to be spaced apart from the fourth connection electrode CNE4 and the fifth connection electrode CNE5 .
  • the second insulating layer PAS2_2 is disposed to not overlap the connection electrodes CNE_2 in the thickness direction.
  • the pattern portions PT1 , PT2 , PT3 , and PT4 of the second insulating layer PAS2_2 and the bridge portions BR1 , BR2 , BR3 , BR4 , and BR5 may be connected to each other so as not to be separated.
  • the plurality of bridge parts BR1 , BR2 , BR3 , BR4 , and BR5 may be disposed to contact side surfaces of the adjacent connection electrodes CNE_2 according to manufacturing process conditions of the connection electrodes CNE_2 .
  • the second insulating layer PAS2_2 includes more pattern portions as a larger number of electrodes RME_2 are disposed in each sub-pixel SPXn, and more pattern portions are added to have a structure in which they are not peeled off. It may include a number of bridge parts.
  • the plurality of bridge portions have a shape extending in the second direction DR2 , and include portions extending in the first direction DR1 of the second base portion BP2 and can be connected
  • the second insulating layer PAS2 may be formed on the second base portion (BP2) may be omitted.
  • the pattern disposed in the light emitting area EMA is connected to each of the pattern parts through the bridge part, and separation of the pattern parts can be prevented.
  • FIG. 18 is a plan view illustrating one sub-pixel of a display device according to another exemplary embodiment. 19 is a cross-sectional view taken along line Q5-Q5' of FIG. 18 .
  • the second insulating layer PAS2_3 has the second base part BP2 omitted, and a larger number of the support pattern parts SP1 and SP2 is provided. , SP3) may be included.
  • a plurality of bridge parts connecting each of the pattern parts PT1 , PT2 , PT3 , and PT4 to the second base part BP2 may be respectively connected to any one of the plurality of support pattern parts SP1 , SP2 , and SP3 .
  • This embodiment is different from the embodiment of FIG. 12 in that the second base part BP2 of the second insulating layer PAS2_3 is replaced with a plurality of support pattern parts SP1 , SP2 , and SP3 .
  • overlapping content will be omitted and the differences will be mainly described.
  • the second insulating layer PAS2_3 is spaced apart from the first support pattern part SP1 in the second direction DR2 in addition to the second support pattern part SP2 disposed in the emission area EMA. and a third support pattern part SP3. While the first support pattern part SP1 is disposed on the third bank part BN3 , the second support pattern part SP2 is disposed on a part of the first bank part BN1 , and the third support pattern part SP3 may be disposed on a portion of the second bank unit BN2 .
  • Each of the second support pattern part SP2 and the third support pattern part SP3 has a third width W3 equal to that of the first support pattern part SP1 and extends in the first direction DR1 , and includes the first support pattern part SP1 . They may be spaced apart from each other in the second direction DR2 with the pattern part SP1 interposed therebetween.
  • the second support pattern part SP2 may partially overlap the first bank part BN1 and the first electrode RME1 .
  • the second support pattern part SP2 may be disposed to be spaced apart from or in contact with the second extension part CN_E2 of the first connection electrode CNE1 and the third connection electrode CNE3 , and may be disposed in contact with the first pattern part through the bridge parts. It may be connected to the PT1 and the third pattern part PT3 .
  • the first pattern part PT1 may be connected to the second support pattern part SP2 via the first bridge part BR1
  • the third pattern part PT3 may be connected to the second support pattern part SP2 via the sixth bridge part BR6 , respectively.
  • the first pattern part PT1 may be connected to the first base part BP1 beyond the second bank BNL2 , and at the same time may be connected to the first bridge part BR1 and the second support pattern part SP2 .
  • the third pattern part PT3 is formed with the first support pattern part SP1 and the second support pattern part SP1 through the third bridge part BR3 and the sixth bridge part BR6, respectively. 2 may be connected to the support pattern part SP2.
  • the third support pattern part SP3 may partially overlap the second bank part BN2 and the fourth electrode RME4 .
  • the third support pattern part SP3 may be disposed to be spaced apart from or in contact with the fourth extension part CN_E4 of the fourth connection electrode CNE4 and the sixth extension part CN_E6 of the fifth connection electrode CNE5, It may be connected to the fourth pattern part PT4 through the fifth bridge part BR5 .
  • the display device 10_3 As the second base portion BP2 in which the second insulating layer PAS2_3 is disposed on the second bank BNL2 is omitted, the inner region of the sub-pixel SPXn and the sub-pixel SPXn are omitted. There is an advantage in that the step difference between the boundary regions between the pixels SPXn is reduced.
  • 20 is a plan view illustrating one sub-pixel of a display device according to another exemplary embodiment.
  • 21 is a cross-sectional view taken along line Q6-Q6' of FIG. 20;
  • 22 is a cross-sectional view taken along line Q7-Q7' of FIG. 20 .
  • 21 illustrates a cross-section crossing the emission area EMA of one sub-pixel SPXn, and
  • FIG. 22 illustrates a cross-section crossing the separation portion ROP of the sub-area SA.
  • the display device 10_4 is disposed between the pattern portions PT1 , PT2 , PT3 , and PT4 of the second insulating layer PAS2_4 and the light emitting device ED.
  • a third insulating layer PAS3_4 may be further included.
  • the third insulating layer PAS3_4 may be formed before the second insulating layer PAS2_4 to fix the light emitting devices ED, and the second insulating layer PAS2_4 may separate the plurality of electrodes RME. It may be formed after the process of separating from the part ROP. Accordingly, the first base part BP1 of the second insulating layer PAS2_4 may be disposed on the entire surface of the sub-region SA including the separation part ROP.
  • the third insulating layer PAS3_4 may be disposed under the pattern portions PT1 , PT2 , PT3 , and PT4 of the second insulating layer PAS2_4 to have substantially the same shape.
  • the third insulating layer PAS3_4 may have a shape extending in the first direction DR1 between the respective bank parts BN1 , BN2 and BN3 , and may include a plurality of light emitting devices ED. can be covered Both side surfaces of the third insulating layer PAS3_4 may be parallel to both side surfaces of the pattern portions PT1 , PT2 , PT3 , and PT4 of the second insulating layer PAS2_4 , respectively.
  • the third insulating layer PAS3_4 may be formed by forming an insulating material to cover the plurality of light emitting devices ED and then patterning it in the same process as the second insulating layer PAS2_4 . Accordingly, the pattern shape of the third insulating layer PAS3_4 on a plane and cross-sectional view may be substantially the same as that of the second insulating layer PAS2_4 .
  • the third insulating layer PAS3_4 may include an inorganic insulating material unlike the second insulating layer PAS2_4 .
  • the third insulating layer PAS3_4 may be made of a material closer to the first insulating layer PAS1 than the second insulating layer PAS2_4 , and may surround the light emitting devices ED to fix and protect them.
  • the electrodes RME of the other sub-pixels SPXn adjacent in the first direction DR1 may be spaced apart from each other in the separation portion ROP.
  • the electrodes spaced apart from each other in the first direction DR1 may be formed as one electrode line and separated from each other after the alignment process of the light emitting devices ED.
  • the process of separating the electrode lines may be performed after the third insulating layer PAS3_4 is formed, and the second insulating layer PAS2_4 may be formed after the separating process.
  • the first insulating layer PAS1 and the third insulating layer PAS3_4 are not disposed in the separation portion ROP of the sub-region SA, and the electrodes RME are spaced apart from each other to form the exposed via layer VIA.
  • the first base part BP1 of the second insulating layer PAS2_4 may cover it.
  • the third insulating layer PAS3_4 may be used as a mask pattern in a process of separating the electrode lines.
  • the first base part BP1 covers the separation part ROP of the sub-region SA, a step difference due to the first base part BP1 in the sub-region SA may be reduced.
  • the first base part BP1 is disposed to cover all of the sub-regions SA except for a region where the plurality of connection electrodes CNE and the contact parts CT1 , CT2 , CT3 , and CT4 are formed.
  • the first base portion BP1 covers the separation portion ROP adjacent to the contact portions CT1 , CT2 , CT3 , and CT4 , thereby reducing a step formed at a location other than the contact portion. Accordingly, when the connection electrodes CNE are formed on the contact portions, there is an advantage in that a material residue is prevented from remaining due to a step formed in the separation portion ROP adjacent thereto.
  • each of the bank portions BN1 , BN2 , and BN3 of the first bank BNL1 may have a length measured in the first direction DR1 shorter than the emission area EMA.
  • each of the bank parts BN1 , BN2 , and BN3 has a length in the first direction DR1 longer than the emission area EMA and extends in the second direction DR2 of the second bank BNL2 . You can also nest parts.
  • FIG. 23 is a plan view illustrating one sub-pixel of a display device according to another exemplary embodiment.
  • 24 is an enlarged view of a portion A6 of FIG. 23 .
  • 25 is an enlarged view of a portion A7 of FIG. 23 .
  • 26 is a cross-sectional view taken along line Q8-Q8' of FIG. 24 and line Q9-Q9' of FIG. 25;
  • FIG. 24 shows a portion of the second bank BNL2 and the first bank BNL1 positioned above the light emitting area EMA
  • FIG. 25 shows the second bank BNL2 and the second bank BNL2 positioned below the light emitting area EMA.
  • a portion of the first banks BNL1 is shown.
  • the plurality of bank portions BN1 , BN2 , and BN3 of the first bank BNL1_5 are arranged in the first direction DR1 rather than the emission area EMA. ) may be longer.
  • a portion of the second bank BNL2 extending in the second direction DR2 may partially overlap each of the bank portions BN1 , BN2 , and BN3 , and the overlapping portion may overlap the top surface of the via layer VIA.
  • the height measured as a reference may be higher than other parts.
  • the connection electrodes CNE may extend in the first direction DR1 from the bank parts BN1 , BN2 , and BN3 to be disposed over the sub-region SA.
  • connection electrodes CNE are disposed in the light emitting area EMA.
  • a step difference between the portion and the second bank BNL2 may be reduced. This may prevent a material residue from remaining on the second bank BNL2 in the process of forming the connection electrodes CNE.
  • the second insulating layer PAS2_5 includes a second base part BP2 disposed on the second bank BNL2 , and the second base part BP2 is the bank parts BN1 and BN2 of the first bank BNL1 . , BN3 , and the second bank BNL2 overlap at the same time, the step difference may increase.
  • the second base portion BP2 of the second insulating layer PAS2_5 is formed at a portion where the bank portions BN1 , BN2 , BN3 of the first bank BNL1 and the second bank BNL2 overlap. may not be placed.

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Abstract

Disclosed is a display device. The display device comprises: a light emitting region; a sub region spaced apart from the light emitting region in a first direction; a first electrode extending in the first direction; a second electrode spaced apart from the first electrode and extending in the first direction; a first insulating layer disposed on the first electrode and the second electrode; light emitting elements having at least one end disposed on the first electrode or the second electrode; a second insulating layer including a first pattern part, which is disposed on the light emitting elements and extends in the first direction, and a first base part disposed in the sub region; a first connection electrode disposed on the first electrode and in contact with the light emitting element; and a second connection electrode disposed on the second electrode and in contact with the light emitting element, wherein the first pattern part spans the sub region and the light emitting region and is connected to the first base part.

Description

표시 장치display device
본 발명은 표시 장치에 관한 것이다.The present invention relates to a display device.
표시 장치는 멀티미디어의 발달과 함께 그 중요성이 증대되고 있다. 이에 부응하여 유기발광 표시 장치(Organic Light Emitting Display, OLED), 액정 표시 장치(Liquid Crystal Display, LCD) 등과 같은 여러 종류의 표시 장치가 사용되고 있다. The importance of the display device is increasing with the development of multimedia. In response to this, various types of display devices such as an organic light emitting display (OLED) and a liquid crystal display (LCD) are being used.
표시 장치의 화상을 표시하는 장치로서 유기 발광 표시 패널이나 액정 표시 패널과 같은 표시 패널을 포함한다. 그 중, 발광 표시 패널로써, 발광 소자를 포함할 수 있는데, 예를 들어 발광 다이오드(Light Emitting Diode, LED)의 경우, 유기물을 형광 물질로 이용하는 유기 발광 다이오드(OLED), 무기물을 형광물질로 이용하는 무기 발광 다이오드 등이 있다.A device for displaying an image of a display device includes a display panel such as an organic light emitting display panel or a liquid crystal display panel. Among them, the light emitting display panel may include a light emitting device. For example, in the case of a light emitting diode (LED), an organic light emitting diode (OLED) using an organic material as a fluorescent material and an inorganic material as a fluorescent material may be included. and inorganic light emitting diodes.
본 발명이 해결하고자 하는 과제는 발광 소자들 상에 배치된 절연층의 박리가 방지된 표시 장치를 제공하는 것이다.SUMMARY OF THE INVENTION An object of the present invention is to provide a display device in which peeling of an insulating layer disposed on light emitting devices is prevented.
본 발명의 과제들은 이상에서 언급한 과제로 제한되지 않으며, 언급되지 않은 또 다른 기술적 과제들은 아래의 기재로부터 당업자에게 명확하게 이해될 수 있을 것이다.The problems of the present invention are not limited to the problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.
상기 과제를 해결하기 위한 일 실시예에 따른 표시 장치는 발광 영역 및 상기 발광 영역의 제1 방향으로 이격된 서브 영역, 상기 발광 영역에 배치되어 상기 제1 방향으로 연장된 제1 전극, 및 상기 제1 전극과 상기 제1 방향과 교차하는 제2 방향으로 이격되고 상기 제1 방향으로 연장된 제2 전극, 상기 제1 전극 및 상기 제2 전극 상에 배치된 제1 절연층, 상기 제1 절연층 상에 배치되고 양 단부 중 적어도 일 단부가 상기 제1 전극 또는 상기 제2 전극 상에 배치된 복수의 발광 소자들, 상기 복수의 발광 소자들 상에 배치되어 상기 제1 방향으로 연장된 제1 패턴부 및 상기 서브 영역에 배치된 제1 베이스부를 포함하는 제2 절연층, 및 상기 제1 전극 상에 배치되어 상기 발광 소자와 접촉하는 제1 연결 전극, 및 상기 제2 전극 상에 배치되어 상기 발광 소자의 접촉하는 제2 연결 전극을 포함하고, 상기 제1 패턴부는 상기 발광 영역으로부터 상기 서브 영역에 걸쳐 배치되어 상기 제1 베이스부와 연결된다.A display device according to an exemplary embodiment provides a light emitting area, a sub area spaced apart from the light emitting area in a first direction, a first electrode disposed in the light emitting area and extending in the first direction, and the second A second electrode spaced apart from the first electrode in a second direction crossing the first direction and extending in the first direction, a first insulating layer disposed on the first electrode and the second electrode, and the first insulating layer a plurality of light emitting devices disposed on the upper surface and at least one end of both ends disposed on the first electrode or the second electrode, a first pattern disposed on the plurality of light emitting devices and extending in the first direction a second insulating layer including a portion and a first base portion disposed in the sub-region, a first connection electrode disposed on the first electrode and in contact with the light emitting device, and disposed on the second electrode to emit the light and a second connection electrode in contact with the device, wherein the first pattern portion is disposed from the light emitting region to the sub region to be connected to the first base portion.
상기 발광 영역에서 상기 제1 방향으로 연장된 복수의 뱅크부들을 포함하는 제1 뱅크, 및 상기 발광 영역과 상기 서브 영역을 둘러싸도록 배치된 제2 뱅크를 더 포함하고, 상기 제2 절연층은 상기 제2 뱅크 상에 배치되어 상기 제1 베이스부 및 상기 제1 패턴부와 연결된 제2 베이스부를 더 포함할 수 있다.A first bank including a plurality of bank parts extending in the first direction from the light emitting area, and a second bank disposed to surround the light emitting area and the sub area, wherein the second insulating layer comprises the It is disposed on the second bank and may further include a second base part connected to the first base part and the first pattern part.
상기 제1 연결 전극 및 상기 제2 연결 전극은 각각 상기 발광 영역과 상기 서브 영역에 걸쳐 배치되고, 상기 제1 패턴부는 상기 제1 연결 전극과 상기 제2 연결 전극 사이에서 상기 제1 방향으로 연장되어 상기 제1 베이스부와 연결될 수 있다.The first connection electrode and the second connection electrode are respectively disposed over the light emitting region and the sub region, and the first pattern portion extends between the first connection electrode and the second connection electrode in the first direction. It may be connected to the first base part.
상기 제1 연결 전극 및 상기 제2 연결 전극은 각각 상기 제1 패턴부의 양 측과 접촉하고, 상기 제1 패턴부의 폭은 상기 복수의 발광 소자의 길이보다 작을 수 있다.The first connection electrode and the second connection electrode may contact both sides of the first pattern portion, respectively, and a width of the first pattern portion may be smaller than a length of the plurality of light emitting devices.
상기 제1 전극과 상기 제2 전극 사이에 배치되어 상기 제1 방향으로 연장된 제3 전극을 더 포함하고, 상기 복수의 발광 소자는 상기 제1 전극과 상기 제3 전극 상에 배치된 제1 발광 소자, 및 상기 제3 전극과 상기 제2 전극 상에 배치된 제2 발광 소자를 포함하며, 상기 제2 절연층의 상기 제1 패턴부는 상기 제1 발광 소자들 상에 배치되고, 상기 제2 절연층은 상기 제2 발광 소자들 상에 배치된 제2 패턴부, 및 상기 제3 전극 상에 배치된 제1 지지 패턴부를 더 포함할 수 있다.and a third electrode disposed between the first electrode and the second electrode and extending in the first direction, wherein the plurality of light emitting devices are first light emitting devices disposed on the first electrode and the third electrode a device and a second light emitting device disposed on the third electrode and the second electrode, wherein the first pattern portion of the second insulating layer is disposed on the first light emitting devices and the second insulating layer The layer may further include a second pattern portion disposed on the second light emitting devices, and a first support pattern portion disposed on the third electrode.
상기 제2 절연층은 상기 제2 방향으로 연장된 형상을 갖고 상기 제1 패턴부와 상기 제2 베이스부에 연결된 제1 브릿지부, 및 상기 제2 방향으로 연장되고 상기 제2 패턴부와 제1 지지 패턴부에 연결된 제2 브릿지부를 더 포함하고, 상기 제1 브릿지부 및 상기 제2 브릿지부의 상기 제1 방향으로 측정된 폭은 상기 제1 패턴부와 상기 제2 패턴부의 상기 제2 방향으로 측정된 폭보다 클 수 있다.The second insulating layer has a shape extending in the second direction, a first bridge part connected to the first pattern part and the second base part, and extending in the second direction, the second pattern part and the first and a second bridge part connected to the support pattern part, wherein widths of the first bridge part and the second bridge part measured in the first direction are measured in the second direction of the first pattern part and the second pattern part may be larger than the specified width.
상기 제1 지지 패턴부는 상기 제3 전극 상에서 상기 제1 방향으로 연장되고, 상기 제2 방향으로 측정된 폭이 상기 제1 브릿지부 및 상기 제2 브릿지부의 상기 제1 방향으로 측정된 폭보다 클 수 있다.The first support pattern part may extend in the first direction on the third electrode, and a width measured in the second direction may be greater than a width measured in the first direction of the first bridge part and the second bridge part. have.
상기 제1 뱅크의 상기 복수의 뱅크부들은 각각 상기 제1 방향으로 연장된 길이가 상기 발광 영역보다 길고, 상기 제2 뱅크 중 상기 발광 영역과 상기 서브 영역 사이에 배치된 부분은 상기 복수의 뱅크부들과 두께 방향으로 중첩하고, 상기 제2 베이스부는 상기 제2 뱅크 중 상기 뱅크부들과 중첩된 부분 상에는 배치되지 않을 수 있다.Each of the plurality of bank parts of the first bank has a length extending in the first direction longer than the light emitting area, and a portion of the second bank disposed between the light emitting area and the sub area is the plurality of bank parts. and overlapping in the thickness direction, and the second base portion may not be disposed on a portion of the second bank that overlaps the bank portions.
상기 제1 전극과 상기 제2 전극 사이에 배치된 제3 전극, 상기 제2 전극과 상기 제2 방향으로 이격된 제4 전극, 상기 제1 전극과 상기 제3 전극에 걸쳐 배치된 제3 연결 전극, 상기 제3 전극과 상기 제4 전극에 걸쳐 배치된 제4 연결 전극, 및 상기 제4 전극과 상기 제2 전극에 걸쳐 배치된 제5 연결 전극을 더 포함하고, 상기 복수의 발광 소자는 상기 제1 전극과 상기 제3 전극 상에 배치되어 상기 제1 연결 전극 및 상기 제3 연결 전극에 접촉하는 제1 발광 소자, 상기 제2 전극과 상기 제4 전극 상에 배치되어 상기 제2 연결 전극 및 상기 제5 연결 전극과 접촉하는 제2 발광 소자, 상기 제1 전극과 상기 제3 전극 상에 배치되어 상기 제3 연결 전극 및 상기 제4 연결 전극에 접촉하는 제3 발광 소자, 및 상기 제2 전극과 상기 제4 전극 상에 배치되어 상기 제4 연결 전극 및 상기 제5 연결 전극과 접촉하는 제4 발광 소자를 포함할 수 있다.A third electrode disposed between the first electrode and the second electrode, a fourth electrode spaced apart from the second electrode in the second direction, and a third connection electrode disposed over the first electrode and the third electrode , a fourth connection electrode disposed over the third electrode and the fourth electrode, and a fifth connection electrode disposed over the fourth electrode and the second electrode, wherein the plurality of light emitting devices include the first A first light emitting element disposed on the first electrode and the third electrode and in contact with the first connection electrode and the third connection electrode, the second connection electrode and the second electrode disposed on the second electrode and the fourth electrode a second light emitting element in contact with a fifth connection electrode, a third light emitting element disposed on the first electrode and the third electrode and contacting the third connection electrode and the fourth connection electrode, and the second electrode; A fourth light emitting device disposed on the fourth electrode and in contact with the fourth connection electrode and the fifth connection electrode may be included.
상기 제2 절연층의 상기 제1 패턴부는 상기 제1 발광 소자들 상에 배치되고, 상기 제2 절연층은 상기 제2 발광 소자들 상에 배치된 제2 패턴부, 상기 제3 발광 소자들 상에 배치된 제3 패턴부, 상기 제4 발광 소자들 상에 배치된 제4 패턴부, 상기 제2 전극과 상기 제3 전극에 부분적으로 중첩하며 상기 제1 방향으로 연장된 제1 지지 패턴부, 및 상기 제2 방향으로 연장된 형상을 갖고 상기 제1 지지 패턴부와 상기 제1 내지 제4 패턴부들 중 어느 하나와 연결된 복수의 브릿지부들을 더 포함할 수 있다.The first pattern portion of the second insulating layer is disposed on the first light emitting devices, and the second insulating layer is disposed on the second pattern portion and the third light emitting devices disposed on the second light emitting devices. a third pattern portion disposed on the , a fourth pattern portion disposed on the fourth light emitting devices, a first support pattern portion partially overlapping the second electrode and the third electrode and extending in the first direction; and a plurality of bridge parts having a shape extending in the second direction and connected to any one of the first support pattern part and the first to fourth pattern parts.
상기 복수의 브릿지부는 상기 제2 패턴부와 상기 제1 지지 패턴부를 연결하는 제2 브릿지부, 상기 제3 패턴부와 상기 제1 지지 패턴부를 연결하는 제3 브릿지부, 및 상기 제4 패턴부와 상기 제1 지지 패턴부를 연결하는 제4 브릿지부를 포함할 수 있다.The plurality of bridge parts includes a second bridge part connecting the second pattern part and the first support pattern part, a third bridge part connecting the third pattern part and the first support pattern part, and the fourth pattern part; A fourth bridge part connecting the first support pattern part may be included.
상기 제2 절연층은 상기 발광 영역 내에서 상기 제1 방향으로 연장되고 상기 제1 지지 패턴부를 사이에 두고 서로 상기 제2 방향으로 이격된 제2 지지 패턴부 및 제3 지지 패턴부를 더 포함하고, 상기 복수의 브릿지부는 상기 제1 패턴부 및 상기 제2 지지 패턴부와 연결된 제1 브릿지부, 상기 제4 패턴부 및 상기 제3 지지 패턴부와 연결된 제5 브릿지부, 및 상기 제3 패턴부 및 상기 제2 지지 패턴부와 연결된 제6 브릿지부를 포함할 수 있다.The second insulating layer further includes a second support pattern part and a third support pattern part extending in the first direction in the light emitting area and spaced apart from each other in the second direction with the first support pattern part interposed therebetween, The plurality of bridge parts includes a first bridge part connected to the first pattern part and the second support pattern part, a fifth bridge part connected to the fourth pattern part and the third support pattern part, and the third pattern part; It may include a sixth bridge part connected to the second support pattern part.
상기 제2 절연층의 상기 제1 패턴부는 상기 제2 방향으로 측정된 폭이 상기 제1 패턴부의 두께보다 작을 수 있다.A width of the first pattern portion of the second insulating layer measured in the second direction may be smaller than a thickness of the first pattern portion.
상기 과제를 해결하기 위한 일 실시예에 따른 표시 장치는 제1 방향으로 연장되고 서로 상기 제1 방향과 교차하는 제2 방향으로 이격된 복수의 전극들로서, 제1 전극, 상기 제1 전극과 상기 제2 방향으로 이격된 제2 전극, 상기 제1 전극과 상기 제2 전극 사이에 배치된 제3 전극, 및 상기 제2 전극과 상기 제2 방향으로 이격된 제4 전극, 상기 복수의 전극들 상에 배치된 제1 절연층, 양 단부가 상기 제1 전극 및 상기 제3 전극 상에 배치되어 상기 제1 방향으로 배열된 복수의 제1 발광 소자들, 및 양 단부가 상기 제2 전극 및 상기 제4 전극 상에 배치된 상기 제1 방향으로 배열된 복수의 제2 발광 소자들, 및 상기 제1 발광 소자들 상에 배치되어 상기 제1 방향으로 연장된 제1 패턴부, 상기 제2 발광 소자들 상에 배치되어 상기 제1 방향으로 연장된 제2 패턴부, 및 상기 제2 전극과 상기 제3 전극 상에 부분적으로 배치되고 상기 제1 방향으로 연장된 제1 지지 패턴부를 포함하는 제2 절연층을 포함하고, 상기 제2 절연층은 상기 제2 방향으로 연장된 형상을 갖고 상기 제1 패턴부 및 상기 제2 패턴부 중 적어도 어느 하나 및 상기 제1 지지 패턴부에 연결된 복수의 브릿지부들을 포함한다.A display device according to an exemplary embodiment includes a plurality of electrodes extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a first electrode, the first electrode, and the first electrode A second electrode spaced apart in two directions, a third electrode disposed between the first electrode and the second electrode, and a fourth electrode spaced apart from the second electrode in the second direction, on the plurality of electrodes a first insulating layer, both ends of which are disposed on the first electrode and the third electrode, and a plurality of first light emitting devices arranged in the first direction, and both ends of the second electrode and the fourth electrode a plurality of second light emitting elements arranged on an electrode and arranged in the first direction, and a first pattern part disposed on the first light emitting elements and extending in the first direction, on the second light emitting elements a second insulating layer including a second pattern part disposed on the ridge and extending in the first direction, and a first support pattern part partially disposed on the second electrode and the third electrode and extending in the first direction wherein the second insulating layer has a shape extending in the second direction and includes at least one of the first pattern part and the second pattern part, and a plurality of bridge parts connected to the first support pattern part .
상기 제1 패턴부 및 상기 제2 패턴부의 상기 제2 방향으로 측정된 제1 폭은 각각 상기 복수의 제1 발광 소자 및 상기 복수의 제2 발광 소자의 길이보다 작고, 상기 복수의 브릿지부들의 상기 제1 방향으로 측정된 제2 폭은 상기 제1 패턴부 및 상기 제2 패턴부의 상기 제1 폭보다 크고, 상기 제1 지지 패턴부의 상기 제2 방향으로 측정된 제3 폭은 상기 복수의 브릿지부들의 상기 제1 방향으로 측정된 상기 제2 폭보다 클 수 있다.A first width measured in the second direction of the first pattern portion and the second pattern portion is smaller than lengths of the plurality of first light emitting elements and the plurality of second light emitting elements, respectively, and A second width measured in the first direction is greater than the first widths of the first pattern part and the second pattern part, and a third width measured in the second direction of the first support pattern part is the plurality of bridge parts. may be greater than the second width measured in the first direction.
상기 제1 패턴부 및 상기 제2 패턴부의 두께는 상기 제1 패턴부 및 상기 제2 패턴부의 상기 제1 폭보다 클 수 있다.A thickness of the first pattern part and the second pattern part may be greater than the first width of the first pattern part and the second pattern part.
상기 복수의 전극들과 중첩하며 상기 제1 방향으로 연장된 복수의 뱅크부들을 포함하는 제1 뱅크, 및 상기 복수의 제1 발광 소자들 및 상기 복수의 제2 발광 소자들이 배치된 발광 영역과 상기 발광 영역으로부터 상기 제1 방향으로 이격된 서브 영역을 둘러싸는 제2 뱅크를 더 포함하고, 상기 제2 절연층은 상기 서브 영역에 배치된 제1 베이스부, 및 상기 제2 뱅크 상에 배치된 제2 베이스부를 더 포함하며, 상기 제1 패턴부 및 상기 제2 패턴부는 각각 상기 발광 영역으로부터 상기 서브 영역에 연장되어 상기 제1 베이스부와 연결될 수 있다.A first bank overlapping the plurality of electrodes and including a plurality of bank portions extending in the first direction, a light emitting region in which the plurality of first light emitting devices and the plurality of second light emitting devices are disposed and a second bank surrounding the sub-region spaced apart from the light-emitting region in the first direction, wherein the second insulating layer includes a first base portion disposed in the sub-region, and a second bank disposed on the second bank. It further includes a second base part, wherein the first pattern part and the second pattern part each extend from the light emitting area to the sub area to be connected to the first base part.
상기 제2 절연층은 상기 제2 방향으로 연장된 형상을 갖고 상기 제1 패턴부 및 상기 제2 베이스부와 연결된 제1 브릿지부를 더 포함할 수 있다.The second insulating layer may further include a first bridge part having a shape extending in the second direction and connected to the first pattern part and the second base part.
상기 제2 절연층은 상기 제1 패턴부와 상기 제1 방향으로 이격되어 위치하는 제3 패턴부, 상기 제2 패턴부와 상기 제1 방향으로 이격되어 위치하는 제4 패턴부, 및 상기 제1 방향으로 연장되고, 상기 제1 지지 패턴부를 사이에 두고 서로 상기 제2 방향으로 이격된 제2 지지 패턴부와 제3 지지 패턴부를 더 포함하고, 상기 복수의 브릿지부는 상기 제1 패턴부 및 상기 제2 지지 패턴부와 연결된 제1 브릿지부, 상기 제2 패턴부 및 상기 제1 지지 패턴부와 연결된 제2 브릿지부, 상기 제3 패턴부 및 상기 제1 지지 패턴부와 연결된 제3 브릿지부, 및 상기 제4 패턴부 및 상기 제1 지지 패턴부와 연결된 제4 브릿지부를 포함할 수 있다.The second insulating layer includes a third pattern portion spaced apart from the first pattern portion in the first direction, a fourth pattern portion spaced apart from the second pattern portion in the first direction, and the first direction and further comprising a second support pattern portion and a third support pattern portion spaced apart from each other in the second direction with the first support pattern portion interposed therebetween, wherein the plurality of bridge portions include the first pattern portion and the second support pattern portion A first bridge part connected to the second support pattern part, a second bridge part connected to the second pattern part and the first support pattern part, a third bridge part connected to the third pattern part and the first support pattern part, and It may include a fourth bridge part connected to the fourth pattern part and the first support pattern part.
상기 복수의 브릿지부는 상기 제4 패턴부와 상기 제3 지지 패턴부와 연결된 제5 브릿지부, 및 상기 제3 패턴부와 상기 제2 지지 패턴부와 연결된 제6 브릿지부를 더 포함할 수 있다.The plurality of bridge parts may further include a fifth bridge part connected to the fourth pattern part and the third support pattern part, and a sixth bridge part connected to the third pattern part and the second support pattern part.
기타 실시예의 구체적인 사항들은 상세한 설명 및 도면들에 포함되어 있다.The details of other embodiments are included in the detailed description and drawings.
일 실시예에 따른 표시 장치는 발광 소자들을 고정시키는 절연층이 길이 대비 얇은 선폭을 갖더라도 이의 박리를 방지하는 구조를 가질 수 있다. 상기 절연층은 발광 소자들을 고정하는 패턴부와, 상기 패턴부보다 큰 폭을 갖고 연결된 지지 패턴부들 및 브릿지부를 포함할 수 있다. 표시 장치는 상기 절연층의 형성 이후에 후속 공정이 진행되는 동안 발광 소자 상에 배치된 부분이 박리되는 것을 방지하는 구조를 가질 수 있고, 이후 공정에서 발광 소자 및 상기 절연층의 일부분이 박리 또는 이탈되어 이물로 남을 방지할 수 있다.The display device according to an exemplary embodiment may have a structure that prevents peeling of the insulating layer for fixing the light emitting elements even if the line width is thin compared to the length. The insulating layer may include a pattern part for fixing the light emitting devices, support pattern parts having a width greater than that of the pattern part and connected thereto, and a bridge part. The display device may have a structure to prevent a portion disposed on the light emitting device from being peeled off during a subsequent process after the formation of the insulating layer, and the light emitting device and a portion of the insulating layer may be peeled off or separated in the subsequent process It can be used to prevent others as foreign bodies.
실시예들에 따른 효과는 이상에서 예시된 내용에 의해 제한되지 않으며, 더욱 다양한 효과들이 본 명세서 내에 포함되어 있다.Effects according to the embodiments are not limited by the contents exemplified above, and more various effects are included in the present specification.
도 1은 일 실시예에 따른 표시 장치의 개략적인 평면도이다.1 is a schematic plan view of a display device according to an exemplary embodiment.
도 2는 일 실시예에 따른 표시 장치의 일 화소를 나타내는 평면도이다.2 is a plan view illustrating one pixel of a display device according to an exemplary embodiment.
도 3은 도 2의 일 화소에 배치된 제1 뱅크와 제2 뱅크, 복수의 전극들 및 제2 절연층의 상대적인 배치를 나타내는 평면도이다.FIG. 3 is a plan view illustrating a relative arrangement of a first bank and a second bank, a plurality of electrodes, and a second insulating layer disposed in one pixel of FIG. 2 .
도 4는 도 2의 일 화소에 배치된 제1 뱅크와 제2 뱅크, 복수의 연결 전극들 및 제2 절연층의 상대적인 배치를 나타내는 평면도이다.FIG. 4 is a plan view illustrating a relative arrangement of a first bank and a second bank, a plurality of connection electrodes, and a second insulating layer disposed in one pixel of FIG. 2 .
도 5는 도 2의 Q1-Q1'선을 따라 자른 단면도이다.FIG. 5 is a cross-sectional view taken along line Q1-Q1' of FIG. 2 .
도 6은 도 2의 Q2-Q2'선을 따라 자른 단면도이다.6 is a cross-sectional view taken along the line Q2-Q2' of FIG.
도 7은 도 2의 A1부분의 확대도이다.FIG. 7 is an enlarged view of a portion A1 of FIG. 2 .
도 8은 일 실시예에 따른 발광 소자의 개략도이다.8 is a schematic diagram of a light emitting device according to an embodiment.
도 9는 다른 실시예에 따른 표시 장치의 일 서브 화소를 나타내는 평면도이다.9 is a plan view illustrating one sub-pixel of a display device according to another exemplary embodiment.
도 10은 도 9의 Q3-Q3'선을 따라 자른 단면도이다. FIG. 10 is a cross-sectional view taken along line Q3-Q3' of FIG. 9 .
도 11은 도 9의 A2부분의 확대도이다.11 is an enlarged view of a portion A2 of FIG. 9 .
도 12는 다른 실시예에 따른 표시 장치의 일 서브 화소를 나타내는 평면도이다.12 is a plan view illustrating one sub-pixel of a display device according to another exemplary embodiment.
도 13은 도 12의 일 서브 화소에 배치된 제1 뱅크와 제2 뱅크, 복수의 연결 전극들 및 제2 절연층의 상대적인 배치를 나타내는 평면도이다.13 is a plan view illustrating a relative arrangement of a first bank and a second bank, a plurality of connection electrodes, and a second insulating layer disposed in one sub-pixel of FIG. 12 .
도 14는 도 12의 Q4-Q4'선을 따라 자른 단면도이다. 14 is a cross-sectional view taken along line Q4-Q4' of FIG. 12 .
도 15는 도 12의 A3부분의 확대도이다.15 is an enlarged view of a portion A3 of FIG. 12 .
도 16은 도 12의 A4부분의 확대도이다.16 is an enlarged view of a portion A4 of FIG. 12 .
도 17은 도 12의 A5부분의 확대도이다.17 is an enlarged view of a portion A5 of FIG. 12 .
도 18은 다른 실시예에 따른 표시 장치의 일 서브 화소를 나타내는 평면도이다.18 is a plan view illustrating one sub-pixel of a display device according to another exemplary embodiment.
도 19는은 도 18의 Q5-Q5'선을 따라 자른 단면도이다. 19 is a cross-sectional view taken along line Q5-Q5' of FIG. 18 .
도 20은 다른 실시예에 따른 표시 장치의 일 서브 화소를 나타내는 평면도이다.20 is a plan view illustrating one sub-pixel of a display device according to another exemplary embodiment.
도 21은 도 20의 Q6-Q6'선을 따라 자른 단면도이다. 21 is a cross-sectional view taken along line Q6-Q6' of FIG. 20;
도 22는 도 20의 Q7-Q7'선을 따라 자른 단면도이다. 22 is a cross-sectional view taken along line Q7-Q7' of FIG. 20 .
도 23은 다른 실시예에 따른 표시 장치의 일 서브 화소를 나타내는 평면도이다.23 is a plan view illustrating one sub-pixel of a display device according to another exemplary embodiment.
도 24는 도 23의 A6부분의 확대도이다.24 is an enlarged view of a portion A6 of FIG. 23 .
도 25는 도 23의 A7부분의 확대도이다.25 is an enlarged view of a portion A7 of FIG. 23 .
도 26은 도 24의 Q8-Q8'선, 및 도 25의 Q9-Q9'선을 따라 자른 단면도이다.26 is a cross-sectional view taken along line Q8-Q8' of FIG. 24 and line Q9-Q9' of FIG. 25;
본 발명의 이점 및 특징, 그리고 그것들을 달성하는 방법은 첨부되는 도면과 함께 상세하게 후술되어 있는 실시예들을 참조하면 명확해질 것이다. 그러나 본 발명은 이하에서 개시되는 실시예들에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시예들은 본 발명의 개시가 완전하도록 하며, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이며, 본 발명은 청구항의 범주에 의해 정의될 뿐이다. Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims.
소자(Elements) 또는 층이 다른 소자 또는 층의 "상(On)"으로 지칭되는 것은 다른 소자 바로 위에 또는 중간에 다른 층 또는 다른 소자를 개재한 경우를 모두 포함한다. 이와 마찬가지로, "하(Below)", "좌(Left)" 및 "우(Right)"로 지칭되는 것들은 다른 소자와 바로 인접하게 개재된 경우 또는 중간에 다른 층 또는 다른 소재를 개재한 경우를 모두 포함한다. 명세서 전체에 걸쳐 동일 참조 부호는 동일 구성 요소를 지칭한다.Elements or layers are referred to as “on” of another element or layer, including cases in which another layer or other element is interposed immediately on or in the middle of another element. Likewise, those referred to as “Below”, “Left” and “Right” refer to cases where they are interposed immediately adjacent to other elements or interposed other layers or other materials in the middle. include Like reference numerals refer to like elements throughout.
비록 제1, 제2 등이 다양한 구성요소들을 서술하기 위해서 사용되나, 이들 구성요소들은 이들 용어에 의해 제한되지 않음은 물론이다. 이들 용어들은 단지 하나의 구성요소를 다른 구성요소와 구별하기 위하여 사용하는 것이다. 따라서, 이하에서 언급되는 제1 구성요소는 본 발명의 기술적 사상 내에서 제2 구성요소일 수도 있음은 물론이다.Although the first, second, etc. are used to describe various elements, these elements are not limited by these terms, of course. These terms are only used to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may be the second component within the spirit of the present invention.
이하, 첨부된 도면을 참고로 하여 실시예들에 대해 설명한다. Hereinafter, embodiments will be described with reference to the accompanying drawings.
도 1은 일 실시예에 따른 표시 장치의 개략적인 평면도이다. 1 is a schematic plan view of a display device according to an exemplary embodiment.
도 1을 참조하면, 표시 장치(10)는 동영상이나 정지영상을 표시한다. 표시 장치(10)는 표시 화면을 제공하는 모든 전자 장치를 지칭할 수 있다. 예를 들어, 표시 화면을 제공하는 텔레비전, 노트북, 모니터, 광고판, 사물 인터넷, 모바일 폰, 스마트 폰, 태블릿 PC(Personal Computer), 전자 시계, 스마트 워치, 워치 폰, 헤드 마운트 디스플레이, 이동 통신 단말기, 전자 수첩, 전자 책, PMP(Portable Multimedia Player), 내비게이션, 게임기, 디지털 카메라, 캠코더 등이 표시 장치(10)에 포함될 수 있다. Referring to FIG. 1 , the display device 10 displays a moving image or a still image. The display device 10 may refer to any electronic device that provides a display screen. For example, televisions, laptops, monitors, billboards, Internet of Things, mobile phones, smart phones, tablet PCs (Personal Computers), electronic watches, smart watches, watch phones, head mounted displays, mobile communication terminals, An electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation system, a game machine, a digital camera, a camcorder, etc. may be included in the display device 10 .
표시 장치(10)는 표시 화면을 제공하는 표시 패널을 포함한다. 표시 패널의 예로는 무기 발광 다이오드 표시 패널, 유기발광 표시 패널, 양자점 발광 표시 패널, 플라즈마 표시 패널, 전계방출 표시 패널 등을 들 수 있다. 이하에서는 표시 패널의 일 예로서, 무기 발광 다이오드 표시 패널이 적용된 경우를 예시하지만, 그에 제한되는 것은 아니며, 동일한 기술적 사상이 적용 가능하다면 다른 표시 패널에도 적용될 수 있다. The display device 10 includes a display panel that provides a display screen. Examples of the display panel include an inorganic light emitting diode display panel, an organic light emitting display panel, a quantum dot light emitting display panel, a plasma display panel, a field emission display panel, and the like. Hereinafter, a case in which an inorganic light emitting diode display panel is applied is exemplified as an example of the display panel, but the present invention is not limited thereto, and the same technical idea may be applied to other display panels if applicable.
표시 장치(10)의 형상은 다양하게 변형될 수 있다. 예를 들어, 표시 장치(10)는 가로가 긴 직사각형, 세로가 긴 직사각형, 정사각형, 코너부(꼭지점)가 둥근 사각형, 기타 다각형, 원형 등의 형상을 가질 수 있다. 표시 장치(10)의 표시 영역(DPA)의 형상 또한 표시 장치(10)의 전반적인 형상과 유사할 수 있다. 도 1에서는 제2 방향(DR2)의 길이가 긴 직사각형 형상의 표시 장치(10)가 예시되어 있다. The shape of the display device 10 may be variously modified. For example, the display device 10 may have a shape such as a long rectangle, a long rectangle, a square, a rectangle with rounded corners (vertices), other polygons, or a circle. The shape of the display area DPA of the display device 10 may also be similar to the overall shape of the display device 10 . In FIG. 1 , a display device 10 having a rectangular shape having a long length in the second direction DR2 is illustrated.
표시 장치(10)는 표시 영역(DPA)과 표시 영역(DPA)의 가장자리 또는 주변을 따라 표시 영역(DPA)을 둘러싸는 비표시 영역(NDA)을 포함할 수 있다. 표시 영역(DPA)은 화면이 표시될 수 있는 영역이고, 비표시 영역(NDA)은 화면이 표시되지 않는 영역이다. 표시 영역(DPA)은 활성 영역으로, 비표시 영역(NDA)은 비활성 영역으로도 지칭될 수 있다. 표시 영역(DPA)은 대체로 표시 장치(10)의 중앙을 차지할 수 있다. The display device 10 may include a display area DPA and a non-display area NDA surrounding the display area DPA along an edge or a periphery of the display area DPA. The display area DPA is an area in which a screen can be displayed, and the non-display area NDA is an area in which a screen is not displayed. The display area DPA may be referred to as an active area, and the non-display area NDA may also be referred to as a non-active area. The display area DPA may generally occupy the center of the display device 10 .
표시 영역(DPA)은 복수의 화소(PX)를 포함할 수 있다. 복수의 화소(PX)는 행렬 방향으로 배열될 수 있다. 각 화소(PX)의 형상은 평면상 직사각형 또는 정사각형일 수 있지만, 이에 제한되는 것은 아니고 각 변이 일 방향에 대해 기울어진 마름모 형상일 수도 있다. 각 화소(PX)는 스트라이프 타입 또는 PENTILETM 타입으로 배열될 수 있다. 또한, 화소(PX)들 각각은 특정 파장대의 광을 방출하는 발광 소자를 하나 이상 포함하여 특정 색을 표시할 수 있다. The display area DPA may include a plurality of pixels PX. The plurality of pixels PX may be arranged in a matrix direction. The shape of each pixel PX may be a rectangular shape or a square shape in plan view, but is not limited thereto, and each side may have a rhombus shape inclined with respect to one direction. Each pixel PX may be arranged in a stripe type or a PENTILE TM type. In addition, each of the pixels PX may include one or more light emitting devices emitting light of a specific wavelength band to display a specific color.
표시 영역(DPA)의 주변에는 비표시 영역(NDA)이 배치될 수 있다. 비표시 영역(NDA)은 표시 영역(DPA)을 전부 또는 부분적으로 둘러쌀 수 있다. 표시 영역(DPA)은 직사각형 형상이고, 비표시 영역(NDA)은 표시 영역(DPA)의 4변에 인접하도록 배치될 수 있다. 비표시 영역(NDA)은 표시 장치(10)의 베젤을 구성할 수 있다. 각 비표시 영역(NDA)들에는 표시 장치(10)에 포함되는 배선들 또는 회로 구동부들이 배치되거나, 외부 장치들이 실장될 수 있다.A non-display area NDA may be disposed around the display area DPA. The non-display area NDA may completely or partially surround the display area DPA. The display area DPA may have a rectangular shape, and the non-display area NDA may be disposed adjacent to four sides of the display area DPA. The non-display area NDA may constitute a bezel of the display device 10 . Wires or circuit drivers included in the display device 10 may be disposed in each of the non-display areas NDA, or external devices may be mounted thereon.
도 2는 일 실시예에 따른 표시 장치의 일 화소를 나타내는 평면도이다. 도 2에서는 하나의 화소(PX)에 더하여 이와 제1 방향(DR1)으로 이웃한 다른 화소(PX)의 일부분이 함께 도시되어 있다.2 is a plan view illustrating one pixel of a display device according to an exemplary embodiment. In FIG. 2 , in addition to one pixel PX, a portion of another pixel PX adjacent thereto in the first direction DR1 is also illustrated.
도 2를 참조하면, 표시 장치(10)의 복수의 화소(PX)들을 각각은 복수의 서브 화소(SPXn, n은 1 내지 3)를 포함할 수 있다. 예를 들어, 하나의 화소(PX)는 제1 서브 화소(SPX1), 제2 서브 화소(SPX2) 및 제3 서브 화소(SPX3)를 포함할 수 있다. 제1 서브 화소(SPX1)는 제1 색의 광을 발광하고, 제2 서브 화소(SPX2)는 제2 색의 광을 발광하며, 제3 서브 화소(SPX3)는 제3 색의 광을 발광할 수 있다. 일 예로, 제1 색은 청색, 제2 색은 녹색, 제3 색은 적색일 수 있다. 다만, 이에 제한되지 않고, 각 서브 화소(SPXn)들은 동일한 색의 광을 발광할 수도 있다. 일 실시예에서, 각 서브 화소(SPXn)들은 청색의 광을 발광할 수 있다. 또한, 도 2에서는 하나의 화소(PX)가 3개의 서브 화소(SPXn)들을 포함하는 것을 예시하였으나, 이에 제한되지 않고, 화소(PX)는 더 많은 수의 서브 화소(SPXn)들을 포함할 수 있다.Referring to FIG. 2 , each of the plurality of pixels PX of the display device 10 may include a plurality of sub-pixels SPXn, where n is 1 to 3 . For example, one pixel PX may include a first sub-pixel SPX1 , a second sub-pixel SPX2 , and a third sub-pixel SPX3 . The first sub-pixel SPX1 emits light of a first color, the second sub-pixel SPX2 emits light of a second color, and the third sub-pixel SPX3 emits light of a third color. can For example, the first color may be blue, the second color may be green, and the third color may be red. However, the present invention is not limited thereto, and each of the sub-pixels SPXn may emit light of the same color. In an embodiment, each of the sub-pixels SPXn may emit blue light. Also, although one pixel PX includes three sub-pixels SPXn in FIG. 2 , the present invention is not limited thereto, and the pixel PX may include a larger number of sub-pixels SPXn. .
표시 장치(10)의 각 서브 화소(SPXn)들은 발광 영역(EMA) 및 비발광 영역을 포함할 수 있다. 발광 영역(EMA)은 발광 소자(ED)가 배치되어 특정 파장대의 광이 출사되는 영역일 수 있다. 비발광 영역은 발광 소자(ED)가 배치되지 않고, 발광 소자(ED)에서 방출된 광들이 도달하지 않아 출사되지 않는 영역일 수 있다. Each of the sub-pixels SPXn of the display device 10 may include an emission area EMA and a non-emission area. The light emitting area EMA may be an area in which the light emitting device ED is disposed and light of a specific wavelength band is emitted. The non-emission area may be an area in which the light emitting device ED is not disposed and light emitted from the light emitting device ED does not reach and is not emitted.
발광 영역은 발광 소자(ED)가 배치된 영역을 포함하여, 발광 소자(ED)와 인접한 영역으로 발광 소자(ED)에서 방출된 광들이 출사되는 영역을 포함할 수 있다. 이에 제한되지 않고, 발광 영역(EMA)은 발광 소자(ED)에서 방출된 광이 다른 부재에 의해 반사되거나 굴절되어 출사되는 영역도 포함할 수 있다. 복수의 발광 소자(ED)들은 각 서브 화소(SPXn)에 배치되고, 이들이 배치된 영역과 이에 인접한 영역을 포함하여 발광 영역을 형성할 수 있다. The light emitting area may include a region in which the light emitting device ED is disposed, and an area adjacent to the light emitting device ED, in which light emitted from the light emitting device ED is emitted. The light emitting area EMA is not limited thereto, and the light emitting area EMA may also include an area in which light emitted from the light emitting device ED is reflected or refracted by other members to be emitted. The plurality of light emitting devices ED may be disposed in each sub-pixel SPXn, and may form a light emitting area including an area in which they are disposed and an area adjacent thereto.
도 2에서는 각 서브 화소(SPXn)의 발광 영역(EMA)들이 서로 균일한 면적을 갖는 것이 예시되어 있으나, 이에 제한되지 않는다. 몇몇 실시예에서, 각 서브 화소(SPXn)의 각 발광 영역(EMA)들은 해당 서브 화소에 배치된 발광 소자(ED)에서 방출된 광의 색 또는 파장대에 따라 서로 다른 면적을 가질 수도 있다.2 illustrates that the emission areas EMA of each sub-pixel SPXn have a uniform area, but is not limited thereto. In some embodiments, each of the emission areas EMA of each sub-pixel SPXn may have a different area according to a color or wavelength band of light emitted from the light-emitting device ED disposed in the corresponding sub-pixel.
각 서브 화소(SPXn)는 비발광 영역에 배치된 서브 영역(SA)을 더 포함할 수 있다. 서브 영역(SA)은 발광 영역(EMA)의 제1 방향(DR1) 타 측인 하측에 배치되어 제1 방향(DR1)으로 이웃하는 서브 화소(SPXn)들의 발광 영역(EMA)들 사이에 배치될 수 있다. 예를 들어, 복수의 발광 영역(EMA)들과 서브 영역(SA)들은 각각 제2 방향(DR2)으로 반복 배열되되, 발광 영역(EMA)과 서브 영역(SA)은 제1 방향(DR1)으로 교대 배열될 수 있다. 다만, 이에 제한되지 않고, 복수의 화소(PX)들에서 발광 영역(EMA)들과 서브 영역(SA)들은 도 2와 다른 배열을 가질 수도 있다. 서브 영역(SA)에는 발광 소자(ED)가 배치되지 않아 광이 출사되지 않으나, 각 서브 화소(SPXn)에 배치된 전극(RME) 일부가 배치될 수 있다. 서로 다른 서브 화소(SPXn)에 배치되는 전극(RME)들은 서브 영역(SA)의 분리부(ROP) 서로 분리되어 배치될 수 있다.Each sub-pixel SPXn may further include a sub-area SA disposed in the non-emission area. The sub-area SA may be disposed below the light-emitting area EMA, which is the other side of the first direction DR1 , and may be disposed between the light-emitting areas EMA of the sub-pixels SPXn adjacent in the first direction DR1 . have. For example, the plurality of light-emitting areas EMA and sub-areas SA are repeatedly arranged in the second direction DR2 , and the light-emitting area EMA and the sub-area SA are arranged in the first direction DR1 . Can be arranged alternately. However, the present invention is not limited thereto, and the emission areas EMA and the sub-areas SA of the plurality of pixels PX may have a different arrangement from that of FIG. 2 . Since the light emitting device ED is not disposed in the sub area SA, no light is emitted, but a portion of the electrode RME disposed in each sub pixel SPXn may be disposed. The electrodes RME disposed in different sub-pixels SPXn may be disposed to be separated from each other in the separation portion ROP of the sub-area SA.
발광 영역(EMA)들 및 서브 영역(SA)들 사이에는 제2 뱅크(BNL2)가 배치된다. 제2 뱅크(BNL2)는 평면상 제1 방향(DR1) 및 제2 방향(DR2)으로 연장된 부분을 포함하여 표시 영역(DPA) 전면에서 격자형 패턴으로 배치될 수 있다. 제2 뱅크(BNL2)는 각 서브 화소(SPXn)들의 경계에 걸쳐 배치되어 이웃하는 서브 화소(SPXn)들을 구분할 수 있다. 또한, 제2 뱅크(BNL2)는 서브 화소(SPXn)마다 배치된 발광 영역(EMA)을 둘러싸도록 배치되어 이들을 구분할 수 있다. 발광 영역(EMA)들 사이, 서브 영역(SA)들 사이, 및 발과 영역(EMA)과 서브 영역(SA) 사이의 간격은 제2 뱅크(BNL2)의 폭에 따라 달라질 수 있다. A second bank BNL2 is disposed between the emission areas EMA and the sub areas SA. The second bank BNL2 may be disposed in a grid pattern on the entire surface of the display area DPA, including portions extending in the first and second directions DR1 and DR2 in a plan view. The second bank BNL2 is disposed across the boundary of each sub-pixel SPXn to distinguish neighboring sub-pixels SPXn. Also, the second bank BNL2 is disposed to surround the emission area EMA disposed in each sub-pixel SPXn to distinguish them. The distance between the light emitting areas EMA, between the sub areas SA, and between the foot and the foot area EMA and the sub area SA may vary according to the width of the second bank BNL2 .
도 3은 도 2의 일 화소에 배치된 제1 뱅크와 제2 뱅크, 복수의 전극들 및 제2 절연층의 상대적인 배치를 나타내는 평면도이다. 도 4는 도 2의 일 화소에 배치된 제1 뱅크와 제2 뱅크, 복수의 연결 전극들 및 제2 절연층의 상대적인 배치를 나타내는 평면도이다. 도 5는 도 2의 Q1-Q1'선을 따라 자른 단면도이다. 도 6은 도 2의 Q2-Q2'선을 따라 자른 단면도이다. 도 7은 도 2의 A1부분의 확대도이다.FIG. 3 is a plan view illustrating a relative arrangement of a first bank and a second bank, a plurality of electrodes, and a second insulating layer disposed in one pixel of FIG. 2 . FIG. 4 is a plan view illustrating a relative arrangement of a first bank and a second bank, a plurality of connection electrodes, and a second insulating layer disposed in one pixel of FIG. 2 . FIG. 5 is a cross-sectional view taken along line Q1-Q1' of FIG. 2 . 6 is a cross-sectional view taken along the line Q2-Q2' of FIG. FIG. 7 is an enlarged view of a portion A1 of FIG. 2 .
도 3 및 도 4는 일 화소(PX)에 배치된 복수의 층들 중, 일부를 생략하여 몇몇 층들만을 도시하고 있다. 도 5는 제1 서브 화소(SPX1)에 배치된 발광 소자(ED)의 양 단부를 가로지르는 단면을 도시하고 있고, 도 6은 제1 서브 화소(SPX1)의 서브 영역(SA)에 배치된 분리부(ROP)를 가로지르는 단면을 도시하고 있다. 도 7은 발광 영역(EMA)과 서브 영역(SA) 사이 부분을 확대하여 도시하고 있다. 3 and 4 illustrate only some layers among a plurality of layers disposed in one pixel PX by omitting some of the layers. FIG. 5 shows a cross-section crossing both ends of the light emitting device ED disposed in the first sub-pixel SPX1 , and FIG. 6 is a separation disposed in the sub-area SA of the first sub-pixel SPX1 . A cross-section across the portion ROP is shown. 7 is an enlarged view of a portion between the light emitting area EMA and the sub area SA.
도 2에 결부하여 도 3 내지 도 7을 참조하면, 표시 장치(10)는 제1 기판(SUB), 및 제1 기판(SUB) 상에 배치되는 반도체층, 복수의 도전층, 및 복수의 절연층들을 포함할 수 있다. 상기 반도체층, 도전층 및 절연층들은 각각 표시 장치(10)의 회로층(CCL)과 표시 소자층을 구성할 수 있다.3 to 7 in conjunction with FIG. 2 , the display device 10 includes a first substrate SUB, a semiconductor layer disposed on the first substrate SUB, a plurality of conductive layers, and a plurality of insulating layers. layers may be included. The semiconductor layer, the conductive layer, and the insulating layer may constitute the circuit layer CCL and the display element layer of the display device 10 , respectively.
예를 들어, 제1 기판(SUB)은 절연 기판일 수 있다. 제1 기판(SUB)은 유리, 석영, 또는 고분자 수지 등의 절연 물질로 이루어질 수 있다. 또한, 제1 기판(SUB)은 리지드(Rigid) 기판일 수 있지만, 벤딩(Bending), 폴딩(Folding), 롤링(Rolling) 등이 가능한 플렉시블(Flexible) 기판일 수도 있다.For example, the first substrate SUB may be an insulating substrate. The first substrate SUB may be made of an insulating material such as glass, quartz, or polymer resin. In addition, the first substrate SUB may be a rigid substrate, but may also be a flexible substrate capable of bending, folding, rolling, or the like.
제1 도전층은 제1 기판(SUB) 상에 배치될 수 있다. 제1 도전층은 하부 금속층(BML)을 포함하고, 하부 금속층(BML)은 제1 트랜지스터(T1)의 액티브층(ACT1)과 제1 기판(SUB)의 두께 방향(예를 들어 제3 방향(DR3))으로 중첩하도록 배치된다. 하부 금속층(BML)은 광을 차단하는 재료를 포함하여, 제1 트랜지스터의 액티브층(ACT1)에 광이 입사되는 것을 방지할 수 있다. 다만, 몇몇 실시예에서, 하부 금속층(BML)은 생략될 수 있다. The first conductive layer may be disposed on the first substrate SUB. The first conductive layer includes a lower metal layer BML, and the lower metal layer BML is formed in a thickness direction (eg, a third direction (eg, a third direction) of the active layer ACT1 of the first transistor T1 and the first substrate SUB. DR3))). The lower metal layer BML may include a light-blocking material to prevent light from being incident on the active layer ACT1 of the first transistor. However, in some embodiments, the lower metal layer BML may be omitted.
버퍼층(BL)은 하부 금속층(BML) 및 제1 기판(SUB) 상에 배치될 수 있다. 버퍼층(BL)은 투습에 취약한 제1 기판(SUB)을 통해 침투하는 수분으로부터 화소(PX)의 트랜지스터들을 보호하기 위해 제1 기판(SUB) 상에 형성되며, 표면 평탄화 기능을 수행할 수 있다. The buffer layer BL may be disposed on the lower metal layer BML and the first substrate SUB. The buffer layer BL is formed on the first substrate SUB to protect the transistors of the pixel PX from moisture penetrating through the first substrate SUB, which is vulnerable to moisture permeation, and may perform a surface planarization function.
반도체층은 버퍼층(BL) 상에 배치된다. 반도체층은 제1 트랜지스터(T1)의 액티브층(ACT1)을 포함할 수 있다. 액티브층(ACT1)은 후술하는 제2 도전층의 게이트 전극(G1)과 부분적으로 제3 방향(DR3)으로 중첩하도록 배치될 수 있다. The semiconductor layer is disposed on the buffer layer BL. The semiconductor layer may include the active layer ACT1 of the first transistor T1 . The active layer ACT1 may be disposed to partially overlap the gate electrode G1 of the second conductive layer to be described later in the third direction DR3 .
반도체층은 다결정 실리콘, 단결정 실리콘, 산화물 반도체 등을 포함할 수 있다. 다른 실시예에서, 반도체층은 다결정 실리콘을 포함할 수도 있다. 상기 산화물 반도체는 인듐(In)을 함유하는 산화물 반도체일 수 있다. 예를 들어, 상기 산화물 반도체는 인듐 주석 산화물(Indium Tin Oxide, ITO), 인듐 아연 산화물(Indium Zinc Oxide, IZO), 인듐 갈륨 산화물(Indium Gallium Oxide, IGO), 인듐 아연 주석 산화물(Indium Zinc Tin Oxide, IZTO), 인듐 갈륨 주석 산화물(Indium Gallium Tin Oxide, IGTO), 인듐 갈륨 아연 산화물(Indium Gallium Zinc Oxide, IGZO), 인듐 갈륨 아연 주석 산화물(Indium Gallium Zinc Tin Oxide, IGZTO) 중 적어도 하나일 수 있다.The semiconductor layer may include polycrystalline silicon, single crystal silicon, an oxide semiconductor, or the like. In another embodiment, the semiconductor layer may include polycrystalline silicon. The oxide semiconductor may be an oxide semiconductor containing indium (In). For example, the oxide semiconductor may include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), and indium zinc tin oxide (Indium Zinc Tin Oxide). , IZTO), Indium Gallium Tin Oxide (IGTO), Indium Gallium Zinc Oxide (IGZO), Indium Gallium Zinc Tin Oxide (IGZTO) may be at least one .
도 5에서는 표시 장치(10)의 서브 화소(SPXn)에 하나의 제1 트랜지스터(T1)가 배치된 것을 예시하고 있으나, 이에 제한되지 않고 표시 장치(10)는 더 많은 수의 트랜지스터들을 포함할 수 있다. 5 illustrates that one first transistor T1 is disposed in the sub-pixel SPXn of the display device 10 , but the present invention is not limited thereto, and the display device 10 may include a larger number of transistors. have.
제1 게이트 절연층(GI)은 반도체층 및 버퍼층(BL)상에 배치된다. 제1 게이트 절연층(GI)은 제1 트랜지스터(T1)의 게이트 절연막의 역할을 할 수 있다. The first gate insulating layer GI is disposed on the semiconductor layer and the buffer layer BL. The first gate insulating layer GI may serve as a gate insulating layer of the first transistor T1 .
제2 도전층은 제1 게이트 절연층(GI) 상에 배치된다. 제2 도전층은 제1 트랜지스터(T1)의 게이트 전극(G1)을 포함할 수 있다. 게이트 전극(G1)은 액티브층(ACT1)의 채널 영역과 제1 기판(SUB)의 두께 방향인 제3 방향(DR3)으로 중첩하도록 배치될 수 있다. The second conductive layer is disposed on the first gate insulating layer GI. The second conductive layer may include the gate electrode G1 of the first transistor T1 . The gate electrode G1 may be disposed to overlap the channel region of the active layer ACT1 in the third direction DR3 that is the thickness direction of the first substrate SUB.
제1 층간 절연층(IL1)은 제2 도전층 및 제1 게이트 절연층(GI) 상에 배치된다. 제1 층간 절연층(IL1)은 제2 도전층과 그 상에 배치되는 다른 층들 사이에서 절연막의 기능을 수행하며 제2 도전층을 보호할 수 있다. The first interlayer insulating layer IL1 is disposed on the second conductive layer and the first gate insulating layer GI. The first interlayer insulating layer IL1 may function as an insulating layer between the second conductive layer and other layers disposed thereon and may protect the second conductive layer.
제3 도전층은 제1 층간 절연층(IL1) 상에 배치된다. 제3 도전층은 제1 전압 배선(VL1)과 제2 전압 배선(VL2), 및 복수의 도전 패턴(CDP1, CDP2)들을 포함할 수 있다. The third conductive layer is disposed on the first interlayer insulating layer IL1. The third conductive layer may include a first voltage line VL1 , a second voltage line VL2 , and a plurality of conductive patterns CDP1 and CDP2 .
제1 전압 배선(VL1)은 제1 전극(RME1)에 전달되는 고전위 전압(또는, 제1 전원 전압)이 인가되고, 제2 전압 배선(VL2)은 제2 전극(RME2)에 전달되는 저전위 전압(또는, 제2 전원 전압)이 인가될 수 있다. 제1 전압 배선(VL1)은 일부분이 제1 층간 절연층(IL1)과 제1 게이트 절연층(GI)을 관통하는 컨택홀을 통해 제1 트랜지스터(T1)의 액티브층(ACT1)과 접촉할 수 있다. 제1 전압 배선(VL1)은 제1 트랜지스터(T1)의 제1 드레인 전극(D1)의 역할을 할 수 있다. 제2 전압 배선(VL2)은 후술하는 제2 전극(RME2)과 직접 연결될 수 있다.A high potential voltage (or a first power voltage) transmitted to the first electrode RME1 is applied to the first voltage line VL1 , and a low voltage transmitted to the second electrode RME2 is applied to the second voltage line VL2 . A potential voltage (or a second power supply voltage) may be applied. The first voltage line VL1 may be partially in contact with the active layer ACT1 of the first transistor T1 through a contact hole penetrating the first interlayer insulating layer IL1 and the first gate insulating layer GI. have. The first voltage line VL1 may serve as the first drain electrode D1 of the first transistor T1 . The second voltage line VL2 may be directly connected to a second electrode RME2 to be described later.
제1 도전 패턴(CDP1)은 제1 층간 절연층(IL1)과 제1 게이트 절연층(GI)을 관통하는 컨택홀을 통해 제1 트랜지스터(T1)의 액티브층(ACT1)과 접촉할 수 있다. 또한, 제1 도전 패턴(CDP1)은 제1 층간 절연층(IL1), 제1 게이트 절연층(GI), 및 버퍼층(GL)을 관통하는 다른 컨택홀을 통해 하부 금속층(BML)과 접촉할 수 있다. 제1 도전 패턴(CDP1)은 제1 트랜지스터(T1)의 제1 소스 전극(S1)의 역할을 할 수 있다. The first conductive pattern CDP1 may contact the active layer ACT1 of the first transistor T1 through a contact hole penetrating the first interlayer insulating layer IL1 and the first gate insulating layer GI. Also, the first conductive pattern CDP1 may contact the lower metal layer BML through another contact hole penetrating the first interlayer insulating layer IL1 , the first gate insulating layer GI, and the buffer layer GL. have. The first conductive pattern CDP1 may serve as the first source electrode S1 of the first transistor T1 .
제2 도전 패턴(CDP2)은 후술하는 제1 전극(RME1)과 연결될 수 있다. 또한, 제2 도전 패턴(CDP2)은 제1 도전 패턴(CDP1)을 통해 제1 트랜지스터(T1)와 전기적으로 연결될 수 있다. 도 5에서는 제1 도전 패턴(CDP1)과 제2 도전 패턴(CDP2)이 서로 분리되어 배치된 것으로 예시되어 있으나, 몇몇 실시예에서, 제2 도전 패턴(CDP2)은 제1 도전 패턴(CDP1)과 일체화되어 하나의 패턴을 형성할 수도 있다. 제1 트랜지스터(T1)는 제1 전압 배선(VL1)으로부터 인가되는 제1 전원 전압을 제1 전극(RME1)으로 전달할 수 있다.The second conductive pattern CDP2 may be connected to a first electrode RME1 to be described later. Also, the second conductive pattern CDP2 may be electrically connected to the first transistor T1 through the first conductive pattern CDP1 . In FIG. 5 , the first conductive pattern CDP1 and the second conductive pattern CDP2 are exemplified to be separated from each other, but in some embodiments, the second conductive pattern CDP2 is formed between the first conductive pattern CDP1 and the second conductive pattern CDP1 They may be integrated to form one pattern. The first transistor T1 may transfer the first power voltage applied from the first voltage line VL1 to the first electrode RME1 .
한편, 도면에서는 제1 도전 패턴(CDP1)과 제2 도전 패턴(CDP2)이 동일한 층에 형성된 것이 예시되어 있으나, 이에 제한되지 않는다. 몇몇 실시예에서, 제2 도전 패턴(CDP2)은 제1 도전 패턴(CDP1)과 다른 도전층, 예컨대 제3 도전층과 몇몇 절연층을 사이에 두고 제3 도전층 상에 배치된 제4 도전층으로 형성될 수도 있다. 이 경우, 제1 전압 배선(VL1) 및 제2 전압 배선(VL2)도 제3 도전층이 아닌 제4 도전층으로 형성될 수 있고, 제1 전압 배선(VL1)은 다른 도전 패턴을 통해 제1 트랜지스터(T1)의 드레인 전극(D1)과 전기적으로 연결될 수 있다. Meanwhile, although it is illustrated that the first conductive pattern CDP1 and the second conductive pattern CDP2 are formed on the same layer in the drawings, the present invention is not limited thereto. In some embodiments, the second conductive pattern CDP2 is a conductive layer different from the first conductive pattern CDP1 , for example, a fourth conductive layer disposed on the third conductive layer with the third conductive layer and some insulating layers interposed therebetween. may be formed as In this case, the first voltage line VL1 and the second voltage line VL2 may also be formed of a fourth conductive layer instead of the third conductive layer, and the first voltage line VL1 may be formed of the first voltage line VL1 through a different conductive pattern. It may be electrically connected to the drain electrode D1 of the transistor T1.
상술한 버퍼층(BL), 제1 게이트 절연층(GI), 및 제1 층간 절연층(IL1)은 교번하여 적층된 복수의 무기층들로 이루어질 수 있다. 예를 들어, 버퍼층(BL), 제1 게이트 절연층(GI), 및 제1 층간 절연층(IL1)은 실리콘 산화물(Silicon Oxide, SiOx), 실리콘 질화물(Silicon Nitride, SiNx), 실리콘 산질화물(Silicon Oxynitride, SiOxNy) 중 적어도 어느 하나를 포함하는 무기층이 적층된 이중층, 또는 이들이 교번하여 적층된 다중층으로 형성될 수 있다. 다만, 이에 제한되지 않으며 버퍼층(BL), 제1 게이트 절연층(GI), 및 제1 층간 절연층(IL1)은 상술한 절연성 재료를 포함하여 하나의 무기층으로 이루어질 수도 있다. 또한, 몇몇 실시예에서, 제1 층간 절연층(IL1)은 폴리이미드(Polyimide, PI)와 같은 유기 절연 물질로 이루어질 수도 있다.The above-described buffer layer BL, the first gate insulating layer GI, and the first interlayer insulating layer IL1 may be formed of a plurality of inorganic layers alternately stacked. For example, the buffer layer BL, the first gate insulating layer GI, and the first interlayer insulating layer IL1 may include silicon oxide (Silicon Oxide, SiO x ), silicon nitride (SiN x ), and silicon acid. Nitride (Silicon Oxynitride, SiO x N y ) It may be formed as a double layer in which an inorganic layer including at least one of them is stacked, or a multilayer in which these are alternately stacked. However, the present invention is not limited thereto, and the buffer layer BL, the first gate insulating layer GI, and the first interlayer insulating layer IL1 may be formed of one inorganic layer including the above-described insulating material. Also, in some embodiments, the first interlayer insulating layer IL1 may be made of an organic insulating material such as polyimide (PI).
제2 도전층, 및 제3 도전층은 몰리브덴(Mo), 알루미늄(Al), 크롬(Cr), 금(Au), 티타늄(Ti), 니켈(Ni), 네오디뮴(Nd) 및 구리(Cu) 중 어느 하나 또는 이들의 합금으로 이루어진 단일층 또는 다중층으로 형성될 수 있다. 다만, 이에 제한되는 것은 아니다.The second conductive layer and the third conductive layer include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may be formed as a single layer or multiple layers made of any one or an alloy thereof. However, the present invention is not limited thereto.
비아층(VIA)은 제3 도전층 상에 배치된다. 비아층(VIA)은 유기 절연 물질, 예를 들어 폴리이미드(PI)와 같은 유기 절연 물질을 포함하여, 표면 평탄화 기능을 수행할 수 있다.The via layer VIA is disposed on the third conductive layer. The via layer VIA may include an organic insulating material, for example, an organic insulating material such as polyimide (PI), and may perform a surface planarization function.
비아층(VIA) 상에는 표시 소자층으로서, 복수의 전극(RME; RME1, RME2)들과 복수의 제1 뱅크(BNL1)들 및 제2 뱅크(BNL2), 복수의 발광 소자(ED)들과 복수의 연결 전극(CNE; CNE1, CNE2)들이 배치된다. 또한, 비아층(VIA) 상에는 복수의 절연층(PAS1, PAS2)들이 배치될 수 있다.As a display element layer on the via layer VIA, a plurality of electrodes RME; RME1 and RME2; a plurality of first banks BNL1 and a second bank BNL2; and a plurality of light emitting devices ED and a plurality of connection electrodes CNE; CNE1, CNE2 of Also, a plurality of insulating layers PAS1 and PAS2 may be disposed on the via layer VIA.
제1 뱅크(BNL1)는 비아층(VIA) 상에 직접 배치될 수 있다. 제1 뱅크(BNL1)들은 서브 화소(SPXn)의 발광 영역(EMA) 내에 배치되고, 제1 방향(DR1)으로 연장된 형상을 갖고 서로 제2 방향(DR2)으로 이격될 수 있다. 예를 들어, 제1 뱅크(BNL1)는 발광 영역(EMA)의 중심을 기준으로 제2 방향(DR2)의 일 측인 좌측에 배치된 제1 뱅크부(BN1), 및 발광 영역(EMA)의 중심을 기준으로 제2 방향(DR2)의 타 측인 우측에 배치된 제2 뱅크부(BN2)를 포함할 수 있다.The first bank BNL1 may be directly disposed on the via layer VIA. The first banks BNL1 are disposed in the emission area EMA of the sub-pixel SPXn, have a shape extending in the first direction DR1 , and may be spaced apart from each other in the second direction DR2 . For example, the first bank BNL1 includes the first bank part BN1 disposed on the left side of the second direction DR2 with respect to the center of the light emitting area EMA, and the center of the light emitting area EMA. It may include a second bank unit BN2 disposed on the right side, which is the other side of the second direction DR2 based on .
제1 뱅크(BNL1)의 각 뱅크부(BN1, BN2)들은 서로 동일한 폭을 가질 수 있으나, 이에 제한되지 않고 몇몇 뱅크부(BN1, BN2)들은 다른 뱅크부(BN1, BN2)들과 다른 폭을 가질 수도 있다. 제1 뱅크(BNL1)의 각 뱅크부(BN1, BN2)들은 제1 방향(DR1)으로 연장된 길이가 제2 뱅크(BNL2)에 의해 둘러싸인 발광 영역(EMA)의 제1 방향(DR1) 길이보다 작을 수 있다. 제1 뱅크(BNL1)는 표시 영역(DPA) 전면에서 각 서브 화소(SPXn)의 발광 영역(EMA) 내에서 좁은 폭을 갖고 일 방향으로 연장된 섬형의 패턴을 형성할 수 있다. 서로 이격된 뱅크부(BN1, BN2)들 사이에는 복수의 발광 소자(ED)들이 배치될 수 있다.Each of the bank units BN1 and BN2 of the first bank BNL1 may have the same width, but is not limited thereto, and some of the bank units BN1 and BN2 may have different widths from the other bank units BN1 and BN2. may have Each of the bank parts BN1 and BN2 of the first bank BNL1 has a length extending in the first direction DR1 is greater than a length of the light emitting area EMA surrounded by the second bank BNL2 in the first direction DR1 . can be small The first bank BNL1 may form an island-shaped pattern extending in one direction with a narrow width in the emission area EMA of each sub-pixel SPXn on the entire surface of the display area DPA. A plurality of light emitting devices ED may be disposed between the bank portions BN1 and BN2 spaced apart from each other.
제1 뱅크(BNL1)는 비아층(VIA)의 상면을 기준으로 적어도 일부가 돌출된 구조를 가질 수 있다. 제1 뱅크(BNL1)의 돌출된 부분은 경사지거나 곡률진 측면을 가질 수 있다. 도면에 예시된 바와 달리, 제1 뱅크(BNL1)의 각 구성들은 단면도 상 외면이 곡률진 반원 또는 반타원의 형상을 가질 수도 있다. 제1 뱅크(BNL1)는 폴리이미드(Polyimide, PI)와 같은 유기 절연 물질을 포함할 수 있으나, 이에 제한되지 않는다.The first bank BNL1 may have a structure in which at least a portion protrudes from the top surface of the via layer VIA. The protruding portion of the first bank BNL1 may have an inclined or curved side surface. Unlike illustrated in the drawing, each configuration of the first bank BNL1 may have a semicircle or semielliptical shape with a curved outer surface in cross-sectional view. The first bank BNL1 may include an organic insulating material such as polyimide (PI), but is not limited thereto.
복수의 전극(RME)들은 일 방향으로 연장된 형상으로 각 서브 화소(SPXn)마다 배치된다. 복수의 전극(RME)들은 제1 방향(DR1)으로 연장되어 서브 화소(SPXn)의 발광 영역(EMA)과 서브 영역(SA)에 걸쳐 배치될 수 있으며, 이들은 서로 제2 방향(DR2)으로 이격되어 배치될 수 있다. 표시 장치(10)는 각 서브 화소(SPXn)에 배치된 제1 전극(RME1) 및 제2 전극(RME2)을 포함한다. 제1 전극(RME1)은 발광 영역(EMA)의 중심을 기준으로 좌측에 배치되고, 제2 전극(RME2)은 제1 전극(RME1)과 제2 방향(DR2)으로 이격되어 발광 영역(EMA)의 중심을 기준으로 우측에 배치된다. The plurality of electrodes RME are disposed in each sub-pixel SPXn in a shape extending in one direction. The plurality of electrodes RME may extend in the first direction DR1 to cover the light emitting area EMA and the sub area SA of the sub pixel SPXn, and they may be spaced apart from each other in the second direction DR2 . and can be placed. The display device 10 includes a first electrode RME1 and a second electrode RME2 disposed in each sub-pixel SPXn. The first electrode RME1 is disposed on the left side with respect to the center of the emission area EMA, and the second electrode RME2 is spaced apart from the first electrode RME1 in the second direction DR2 to form the emission area EMA. is placed to the right of the center of the
제1 전극(RME1)은 일부분이 제1 뱅크부(BN1) 상에 배치되고, 제2 전극(RME2)은 일부분이 제2 뱅크부(BN2) 상에 배치될 수 있다. 복수의 전극(RME)들은 적어도 각 뱅크부(BN1, BN2)의 경사진 측면 상에 배치될 수 있다. 일 실시예에서, 복수의 전극(RME)들의 제2 방향(DR2)으로 측정된 폭은 뱅크부(BN1, BN2)의 제2 방향(DR2)으로 측정된 폭보다 작을 수 있다. 각 전극(RME)들은 적어도 제1 뱅크(BNL1)의 일 측면은 덮도록 배치되어 발광 소자(ED)에서 방출된 광을 반사시킬 수 있다. 또한, 복수의 전극(RME)들이 제2 방향(DR2)으로 이격된 간격은 뱅크부(BN1, BN2)들 사이의 간격보다 좁을 수 있다. 각 전극(RME)들은 적어도 일부 영역이 비아층(VIA) 상에 직접 배치되어 이들은 동일 평면 상에 배치될 수 있다.A part of the first electrode RME1 may be disposed on the first bank part BN1 , and a part of the second electrode RME2 may be disposed on the second bank part BN2 . The plurality of electrodes RME may be disposed on at least inclined side surfaces of each of the bank units BN1 and BN2. In an embodiment, a width measured in the second direction DR2 of the plurality of electrodes RME may be smaller than a width measured in the second direction DR2 of the bank parts BN1 and BN2. Each of the electrodes RME may be disposed to cover at least one side surface of the first bank BNL1 to reflect light emitted from the light emitting device ED. Also, an interval between the plurality of electrodes RME in the second direction DR2 may be narrower than an interval between the bank portions BN1 and BN2 . At least a portion of each of the electrodes RME may be directly disposed on the via layer VIA so that they may be disposed on the same plane.
또한, 제1 전극(RME1)과 제2 전극(RME2)은 각각 제2 뱅크(BNL2)와 제3 방향(DR3)으로 중첩하는 부분에 형성된 제1 전극 컨택홀(CTD) 및 제2 전극 컨택홀(CTS)을 통해 제3 도전층과 연결될 수 있다. 제1 전극(RME1)은 그 하부의 비아층(VIA)을 관통하는 제1 전극 컨택홀(CTD)을 통해 제2 전극 패턴(CDP2)과 접촉할 수 있다. 제2 전극(RME2)은 그 하부의 비아층(VIA)을 관통하는 제2 전극 컨택홀(CTS)을 통해 제2 전압 배선(VL2)과 접촉할 수 있다. 제1 전극(RME1)은 제2 전극 패턴(CDP2) 및 제1 전극 패턴(CDP1)을 통해 제1 트랜지스터(T1)와 전기적으로 연결되어 제1 전원 전압이 인가되고, 제2 전극(RME2)은 제2 전압 배선(VL2)과 전기적으로 연결되어 제2 전원 전압이 인가될 수 있다. 도 5에서는 제1 전극 컨택홀(CTD)과 제2 전극 컨택홀(CTS)이 제2 뱅크(BNL2)의 하부에 배치된 것이 예시되어 있으나, 이에 제한되지 않는다. 각 전극 컨택홀(CTD, CTS)들은 발광 영역(EMA) 또는 서브 영역(SA)에 배치될 수도 있다.In addition, the first electrode RME1 and the second electrode RME2 have a first electrode contact hole CTD and a second electrode contact hole formed in portions overlapping the second bank BNL2 and the third direction DR3, respectively. (CTS) may be connected to the third conductive layer. The first electrode RME1 may contact the second electrode pattern CDP2 through the first electrode contact hole CTD penetrating the via layer VIA thereunder. The second electrode RME2 may contact the second voltage line VL2 through the second electrode contact hole CTS penetrating the via layer VIA thereunder. The first electrode RME1 is electrically connected to the first transistor T1 through the second electrode pattern CDP2 and the first electrode pattern CDP1 so that a first power voltage is applied, and the second electrode RME2 is The second power voltage may be applied by being electrically connected to the second voltage line VL2 . 5 illustrates that the first electrode contact hole CTD and the second electrode contact hole CTS are disposed under the second bank BNL2, but the present invention is not limited thereto. Each of the electrode contact holes CTD and CTS may be disposed in the emission area EMA or the sub area SA.
제1 방향(DR1)으로 이웃한 서로 다른 서브 화소(SPXn)에 배치된 전극(RME)들은 서브 영역(SA)의 분리부(ROP)에서 서로 이격될 수 있다. 이러한 전극(RME)의 배치는 제1 방향(DR1)으로 연장된 하나의 전극 라인으로 형성되었다가 발광 소자(ED)들을 배치한 뒤 후속 공정에서 상기 전극 라인을 분리함으로써 형성될 수 있다. 전극 라인은 표시 장치(10)의 제조 공정 중 발광 소자(ED)를 정렬하기 위해 서브 화소(SPXn) 내에 전계를 생성하는 데에 활용될 수 있다. The electrodes RME disposed in different sub-pixels SPXn adjacent in the first direction DR1 may be spaced apart from each other in the separation portion ROP of the sub-region SA. The electrode RME may be disposed as one electrode line extending in the first direction DR1 , and may be formed by disposing the light emitting devices ED and then separating the electrode line in a subsequent process. The electrode line may be utilized to generate an electric field in the sub-pixel SPXn to align the light emitting device ED during the manufacturing process of the display device 10 .
발광 소자(ED)들을 정렬시킨 뒤 전극 라인을 분리부(ROP)에서 분리하여 서로 제1 방향(DR1)으로 이격된 복수의 전극(RME)들을 형성할 수 있다. 상기 전극 라인을 분리하는 공정은 후술하는 제2 절연층(PAS2)을 형성하는 공정 이후에 수행될 수 있고, 도 6에 도시된 바와 같이 분리부(ROP)에서는 제2 절연층(PAS2)이 배치되지 않을 수 있다. 제2 절연층(PAS2)은 전극 라인을 분리하는 공정에서 마스크 패턴으로 활용될 수 있다. After aligning the light emitting devices ED, the electrode line may be separated from the separation part ROP to form a plurality of electrodes RME spaced apart from each other in the first direction DR1 . The process of separating the electrode line may be performed after the process of forming the second insulating layer PAS2 to be described later, and as shown in FIG. 6 , the second insulating layer PAS2 is disposed in the separating part ROP as shown in FIG. 6 . it may not be The second insulating layer PAS2 may be used as a mask pattern in a process of separating the electrode lines.
복수의 전극(RME)들은 발광 소자(ED)와 전기적으로 연결될 수 있다. 각 전극(RME)들은 후술하는 연결 전극(CNE; CNE1, CNE2)을 통해 발광 소자(ED)와 연결될 수 있고, 하부의 도전층으로부터 인가되는 전기 신호를 발광 소자(ED)에 전달할 수 있다. The plurality of electrodes RME may be electrically connected to the light emitting device ED. Each of the electrodes RME may be connected to the light emitting device ED through connection electrodes CNE (CNE1, CNE2), which will be described later, and may transmit an electric signal applied from a lower conductive layer to the light emitting device ED.
복수의 전극(RME)들 각각은 반사율이 높은 전도성 물질을 포함할 수 있다. 예를 들어, 전극(RME)은 반사율이 높은 물질로 은(Ag), 구리(Cu), 알루미늄(Al) 등과 같은 금속을 포함하거나, 알루미늄(Al), 니켈(Ni), 란타늄(La) 등을 포함하는 합금일 수 있다. 전극(RME)은 발광 소자(ED)에서 방출되어 제1 뱅크(BNL1)의 측면으로 진행하는 광을 각 서브 화소(SPXn)의 상부 방향으로 반사시킬 수 있다. Each of the plurality of electrodes RME may include a conductive material having high reflectivity. For example, the electrode RME is a material with high reflectivity and includes a metal such as silver (Ag), copper (Cu), aluminum (Al), or the like, or includes aluminum (Al), nickel (Ni), lanthanum (La), etc. It may be an alloy containing. The electrode RME may reflect light emitted from the light emitting device ED and traveling to the side surface of the first bank BNL1 in an upper direction of each sub-pixel SPXn.
다만, 이에 제한되지 않고 각 전극(RME)은 투명성 전도성 물질을 더 포함할 수 있다. 예를 들어, 각 전극(RME)은 ITO, IZO, ITZO 등과 같은 물질을 포함할 수 있다. 몇몇 실시예에서 각 전극(RME)들은 투명성 전도성 물질과 반사율이 높은 금속층이 각각 한층 이상 적층된 구조를 이루거나, 이들을 포함하여 하나의 층으로 형성될 수도 있다. 예를 들어, 각 전극(RME)은 ITO/Ag/ITO/, ITO/Ag/IZO, 또는 ITO/Ag/ITZO/IZO 등의 적층 구조를 가질 수 있다. However, the present invention is not limited thereto, and each electrode RME may further include a transparent conductive material. For example, each electrode RME may include a material such as ITO, IZO, ITZO, or the like. In some embodiments, each of the electrodes RME may have a structure in which one or more layers of a transparent conductive material and a metal layer having high reflectivity are stacked, or may be formed as a single layer including them. For example, each electrode RME may have a stacked structure such as ITO/Ag/ITO/, ITO/Ag/IZO, or ITO/Ag/ITZO/IZO.
제1 절연층(PAS1)은 비아층(VIA), 제1 뱅크(BNL1)들 및 복수의 전극(RME)들 상에 배치된다. 제1 절연층(PAS1)은 비아층(VIA) 상에서 복수의 전극(RME)들과 제1 뱅크(BNL1)를 덮도록 배치될 수 있다. 또한, 제1 절연층(PAS1)은 서브 영역(SA)에서 제1 방향(DR1)으로 이웃한 전극(RME)들이 이격된 분리부(ROP)에도 배치되지 않을 수 있다. 제1 절연층(PAS1)은 복수의 전극(RME)들을 보호함과 동시에 서로 다른 전극(RME)들을 상호 절연시킬 수 있다. 또한, 제1 절연층(PAS1)은 그 상에 배치되는 발광 소자(ED)가 다른 부재들과 직접 접촉하여 손상되는 것을 방지할 수도 있다. The first insulating layer PAS1 is disposed on the via layer VIA, the first banks BNL1 , and the plurality of electrodes RME. The first insulating layer PAS1 may be disposed on the via layer VIA to cover the plurality of electrodes RME and the first bank BNL1 . Also, the first insulating layer PAS1 may not be disposed in the separation portion ROP in which the electrodes RME adjacent to each other in the first direction DR1 in the sub area SA are spaced apart from each other. The first insulating layer PAS1 may protect the plurality of electrodes RME and at the same time insulate the different electrodes RME from each other. Also, the first insulating layer PAS1 may prevent the light emitting device ED disposed thereon from being damaged by direct contact with other members.
예시적인 실시예에서, 제1 절연층(PAS1)은 제2 방향(DR2)으로 이격된 전극(RME) 사이에서 상면의 일부가 함몰되도록 단차가 형성될 수 있다. 제1 절연층(PAS1)의 단차가 형성된 상면에는 발광 소자(ED)가 배치되고, 발광 소자(ED)와 제1 절연층(PAS1) 사이에는 공간이 형성될 수도 있다. In an exemplary embodiment, a step may be formed such that a portion of the upper surface of the first insulating layer PAS1 is recessed between the electrodes RME spaced apart in the second direction DR2 . The light emitting device ED may be disposed on the upper surface of the first insulating layer PAS1 having a step, and a space may be formed between the light emitting device ED and the first insulating layer PAS1 .
제1 절연층(PAS1)은 각 전극(RME)들의 상면 일부를 노출하는 복수의 컨택부(CT1, CT2)들을 포함할 수 있다. 복수의 컨택부(CT1, CT2)들은 제1 절연층(PAS1)을 관통하며, 후술하는 연결 전극(CNE)들은 컨택부(CT1, CT2)들을 통해 노출된 전극(RME)과 접촉할 수 있다. The first insulating layer PAS1 may include a plurality of contact portions CT1 and CT2 exposing a portion of the top surface of each electrode RME. The plurality of contact portions CT1 and CT2 may pass through the first insulating layer PAS1 , and connection electrodes CNE, which will be described later, may contact the electrode RME exposed through the contact portions CT1 and CT2 .
제2 뱅크(BNL2)는 제1 절연층(PAS1) 상에 배치될 수 있다. 제2 뱅크(BNL2)는 평면도 상 제1 방향(DR1) 및 제2 방향(DR2)으로 연장된 부분을 포함하여 격자형 패턴으로 배치될 수 있고, 각 서브 화소(SPXn)들의 경계에 걸쳐 배치되어 이웃하는 서브 화소(SPXn)들을 구분할 수 있다. 또한, 제2 뱅크(BNL2)는 발광 영역(EMA) 및 서브 영역(SA)을 둘러싸도록 배치되며, 제2 뱅크(BNL2)가 구획하며 개구하는 영역이 각각 발광 영역(EMA)과 서브 영역(SA)일 수 있다.The second bank BNL2 may be disposed on the first insulating layer PAS1 . The second bank BNL2 may be disposed in a grid pattern including portions extending in the first direction DR1 and the second direction DR2 in a plan view, and may be disposed across the boundary of each sub-pixel SPXn. The neighboring sub-pixels SPXn may be distinguished. In addition, the second bank BNL2 is disposed to surround the light emitting area EMA and the sub area SA, and regions divided by the second bank BNL2 and opened are the light emitting area EMA and the sub area SA, respectively. ) can be
제2 뱅크(BNL2)는 일정 높이를 가질 수 있고, 몇몇 실시예에서, 제2 뱅크(BNL2)는 상면의 높이가 제1 뱅크(BNL1)보다 높을 수 있고, 그 두께는 제1 뱅크(BNL1) 및 제2 뱅크(BNL2)와 같거나 더 클 수 있다. 제2 뱅크(BNL2)는 표시 장치(10)의 제조 공정 중 잉크젯 프린팅 공정에서 잉크가 인접한 서브 화소(SPXn)로 넘치는 것을 방지할 수 있다. 제2 뱅크(BNL2)는 다른 서브 화소(SPXn)마다 다른 발광 소자(ED)들이 분산된 잉크가 서로 혼합되는 것을 방지할 수 있다. 제2 뱅크(BNL2)는 제1 뱅크(BNL1)와 같이 폴리이미드를 포함할 수 있으나, 이에 제한되는 것은 아니다.The second bank BNL2 may have a predetermined height, and in some embodiments, a top surface of the second bank BNL2 may be higher than that of the first bank BNL1 , and the thickness thereof may be greater than that of the first bank BNL1 . and the second bank BNL2 may be equal to or larger than the second bank BNL2. The second bank BNL2 may prevent ink from overflowing into the adjacent sub-pixel SPXn in an inkjet printing process during a manufacturing process of the display device 10 . The second bank BNL2 may prevent inks in which different light emitting devices ED are dispersed in different sub-pixels SPXn from being mixed with each other. The second bank BNL2 may include polyimide like the first bank BNL1 , but is not limited thereto.
복수의 발광 소자(ED)들은 제1 절연층(PAS1) 상에 배치될 수 있다. 발광 소자(ED)는 제1 기판(SUB)의 상면에 평행한 방향으로 배치된 복수의 층들을 포함할 수 있다. 표시 장치(10)의 발광 소자(ED)는 연장된 일 방향이 제1 기판(SUB)의 상면과 평행하도록 배치되고, 발광 소자(ED)에 포함된 복수의 반도체층들은 제1 기판(SUB)의 상면과 평행한 방향을 따라 순차적으로 배치될 수 있다. 다만, 이에 제한되지 않는다. 경우에 따라서는 발광 소자(ED)가 다른 구조를 갖는 경우, 복수의 층들은 제1 기판(SUB)에 수직한 방향으로 배치될 수도 있다. The plurality of light emitting devices ED may be disposed on the first insulating layer PAS1 . The light emitting device ED may include a plurality of layers disposed in a direction parallel to the top surface of the first substrate SUB. The light emitting device ED of the display device 10 is disposed so that one extended direction is parallel to the top surface of the first substrate SUB, and a plurality of semiconductor layers included in the light emitting device ED are formed on the first substrate SUB. may be sequentially disposed along a direction parallel to the upper surface of the . However, the present invention is not limited thereto. In some cases, when the light emitting device ED has a different structure, the plurality of layers may be disposed in a direction perpendicular to the first substrate SUB.
복수의 발광 소자(ED)들은 서로 다른 뱅크부(BN1, BN2)들 사이에서, 제2 방향(DR2)으로 이격된 전극(RME)들 상에 배치될 수 있다. 발광 소자(ED)들은 각 전극(RME)들이 연장된 제1 방향(DR1)을 따라 서로 이격되어 배치되며 실질적으로 상호 평행하게 정렬될 수 있다. 발광 소자(ED)는 일 방향으로 연장된 형상을 가질 수 있고, 연장된 길이가 제2 방향(DR2)으로 이격된 전극(RME)들 사이의 최단 간격보다 길 수 있다. 발광 소자(ED)들은 적어도 일 단부가 서로 다른 전극(RME)들 중 어느 하나 상에 배치되거나, 양 단부가 각각 서로 다른 전극(RME)들 상에 놓이도록 배치될 수 있다. 각 전극(RME)들이 연장된 방향과 발광 소자(ED)가 연장된 방향은 실질적으로 수직을 이루도록 배치될 수 있다. 다만, 이에 제한되지 않으며, 발광 소자(ED)는 각 전극(RME)들이 연장된 방향에 비스듬히 배치될 수도 있다.The plurality of light emitting devices ED may be disposed on electrodes RME spaced apart from each other in the second direction DR2 between different bank parts BN1 and BN2 . The light emitting devices ED may be disposed to be spaced apart from each other along the first direction DR1 in which the respective electrodes RME extend, and may be aligned substantially parallel to each other. The light emitting device ED may have a shape extending in one direction, and the extended length may be longer than the shortest distance between the electrodes RME spaced apart in the second direction DR2 . At least one end of the light emitting devices ED may be disposed on any one of the electrodes RME different from each other, or both ends of the light emitting devices ED may be disposed on different electrodes RME. A direction in which each of the electrodes RME extends and a direction in which the light emitting device ED extends may be disposed to be substantially perpendicular to each other. However, the present invention is not limited thereto, and the light emitting device ED may be disposed obliquely in a direction in which the respective electrodes RME extend.
각 서브 화소(SPXn)에 배치된 발광 소자(ED)들은 복수의 반도체층을 포함하고, 상기 반도체층이 이루는 재료에 따라 서로 다른 파장대의 광을 방출할 수 있다. 다만, 이에 제한되지 않고, 각 서브 화소(SPXn)에 배치된 발광 소자(ED)들은 동일한 재료의 반도체층을 포함하여 동일한 색의 광을 방출할 수 있다. 또한, 발광 소자(ED)는 서로 다른 도전형으로 도핑된 반도체층들을 포함하여 전극(RME) 상에 생성되는 전계에 의해 일 단부가 특정 방향을 향하도록 배향될 수 있다. 발광 소자(ED)들은 어느 한 반도체층을 기준으로 제1 단부와 그 반대편 제2 단부가 정의될 수 있다. 예를 들어, 발광 소자(ED)는 제1 전극(RME1) 상에 배치된 부분이 제1 단부이고, 제2 전극(RME2) 상에 배치된 부분은 제2 단부일 수 있다. 표시 장치(10)가 더 많은 수의 전극(RME)들을 포함하는 실시예에서, 서로 다른 전극(RME)들 상에 배치된 발광 소자(ED)들은 제1 단부가 향하는 방향이 서로 다를 수 있다. The light emitting devices ED disposed in each sub-pixel SPXn may include a plurality of semiconductor layers, and may emit light of different wavelength bands according to materials of the semiconductor layers. However, the present invention is not limited thereto, and the light emitting devices ED disposed in each sub-pixel SPXn may include a semiconductor layer of the same material to emit light of the same color. In addition, the light emitting device ED may include semiconductor layers doped with different conductivity types and may be oriented so that one end thereof faces a specific direction by an electric field generated on the electrode RME. In the light emitting devices ED, a first end and a second end opposite to the one semiconductor layer may be defined. For example, a portion disposed on the first electrode RME1 may be a first end portion of the light emitting device ED, and a portion disposed on the second electrode RME2 may be a second end portion. In an embodiment in which the display device 10 includes a greater number of electrodes RME, directions in which the first ends of the light emitting devices ED disposed on different electrodes RME may be different from each other.
발광 소자(ED)들은 연결 전극(CNE: CNE1, CNE2)들과 접촉하여 전기적으로 연결될 수 있다. 발광 소자(ED)는 연장된 일 방향측 단부면에는 반도체층 일부가 노출되기 때문에, 상기 노출된 반도체층은 연결 전극(CNE)과 접촉할 수 있다. 각 발광 소자(ED)들은 연결 전극(CNE)들을 통해 전극(RME) 및 비아층(VIA) 하부의 도전층들과 전기적으로 연결될 수 있고, 전기 신호가 인가되어 특정 파장대의 광을 방출할 수 있다.The light emitting devices ED may be electrically connected to each other by contacting the connection electrodes CNE: CNE1 and CNE2. Since a portion of the semiconductor layer is exposed on the one end surface of the light emitting device ED, the exposed semiconductor layer may contact the connection electrode CNE. Each of the light emitting devices ED may be electrically connected to the conductive layers under the electrode RME and the via layer VIA through the connection electrodes CNE, and an electric signal may be applied to emit light in a specific wavelength band. .
제2 절연층(PAS2)은 복수의 발광 소자(ED)들, 제2 뱅크(BNL2) 및 서브 영역(SA)에 배치될 수 있다. 제2 절연층(PAS2)은 제1 방향(DR1)으로 연장되어 복수의 발광 소자(ED)들 상에 배치된 제1 패턴부(PT1)를 포함한다. 제1 패턴부(PT1)는 제1 뱅크부(BN1)와 제2 뱅크부(BN2) 사이에서 발광 소자(ED)의 외면을 부분적으로 감싸도록 배치되며, 발광 소자(ED)의 양 측, 또는 양 단부는 덮지 않을 수 있다. 제1 패턴부(PT1)는 평면도상 각 서브 화소(SPXn) 내에서 선형 또는 섬형 패턴을 형성할 수 있다. 제2 절연층(PAS2)의 제1 패턴부(PT1)는 발광 소자(ED)를 보호함과 동시에 표시 장치(10)의 제조 공정에서 발광 소자(ED)들을 고정시킬 수 있다. 또한, 제1 패턴부(PT1)는 발광 소자(ED)와 그 하부의 제1 절연층(PAS1) 사이의 공간을 채우도록 배치될 수도 있다.The second insulating layer PAS2 may be disposed on the plurality of light emitting devices ED, the second bank BNL2 and the sub-region SA. The second insulating layer PAS2 extends in the first direction DR1 and includes the first pattern portion PT1 disposed on the plurality of light emitting devices ED. The first pattern part PT1 is disposed between the first bank part BN1 and the second bank part BN2 to partially surround the outer surface of the light emitting device ED, both sides of the light emitting device ED, or Both ends may not be covered. The first pattern part PT1 may form a linear or island-shaped pattern in each sub-pixel SPXn in a plan view. The first pattern portion PT1 of the second insulating layer PAS2 may protect the light emitting device ED and fix the light emitting devices ED in the manufacturing process of the display device 10 . Also, the first pattern portion PT1 may be disposed to fill a space between the light emitting device ED and the first insulating layer PAS1 thereunder.
제2 절연층(PAS2)의 제1 패턴부(PT1)는 서브 화소(SPXn)에 전면적으로 배치된 유기 절연 물질이 발광 소자(ED)의 양 단부를 노출하도록 패터닝되어 형성된 것일 수 있다. 제1 패턴부(PT1)는 발광 소자(ED)의 양 측은 노출하면서 제1 방향(DR1)으로 연장된 형상을 가짐에 따라, 제2 방향(DR2)으로 측정된 폭 대비 제1 방향(DR1)의 길이가 길 수 있다. 또한, 후술할 바와 같이 제2 절연층(PAS2)은 유기 절연 물질을 포함하여 그 두께(예를 들어 제1 패턴부(PT1)의 두께)도 제2 방향(DR2)으로 측정된 폭보다 클 수 있다. 이러한 형상의 제1 패턴부(PT1)는 후속 공정에서 쉽게 박리될 수 있는데, 제2 절연층(PAS2)은 더 큰 폭을 갖고 제1 패턴부(PT1)와 연결된 부분을 포함하여 제1 패턴부(PT1)의 박리를 방지할 수 있다. The first pattern portion PT1 of the second insulating layer PAS2 may be formed by patterning an organic insulating material disposed entirely on the sub-pixel SPXn to expose both ends of the light emitting device ED. As the first pattern portion PT1 has a shape extending in the first direction DR1 while exposing both sides of the light emitting device ED, the first direction DR1 is compared to the width measured in the second direction DR2 . can be long. Also, as will be described later, the thickness of the second insulating layer PAS2 (eg, the thickness of the first pattern portion PT1 ) may be greater than the width measured in the second direction DR2 including the organic insulating material. have. The first pattern portion PT1 having such a shape may be easily peeled off in a subsequent process. The second insulating layer PAS2 has a larger width and includes a portion connected to the first pattern portion PT1. Peeling of (PT1) can be prevented.
일 실시예에 따르면, 제2 절연층(PAS2)은 서브 영역(SA)에 배치된 제1 베이스부(BP1)와 제2 뱅크(BNL2) 상에 배치된 제2 베이스부(BP2)를 포함할 수 있다. 발광 영역(EMA)에 배치된 제1 패턴부(PT1)는 제1 방향(DR1)으로 연장되어 제1 베이스부(BP1) 또는 제2 베이스부(BP2)와 연결될 수 있다. According to an embodiment, the second insulating layer PAS2 may include a first base part BP1 disposed on the sub area SA and a second base part BP2 disposed on the second bank BNL2. can The first pattern part PT1 disposed in the emission area EMA may extend in the first direction DR1 to be connected to the first base part BP1 or the second base part BP2 .
제1 베이스부(BP1)는 서브 영역(SA) 중 분리부(ROP)와 후술하는 연결 전극(CNE)들이 위치한 부분을 제외하고 서브 영역(SA) 전면에 배치될 수 있다. 분리부(ROP)에서는 제2 절연층(PAS2)을 형성한 뒤, 그 하부의 전극(RME)들을 분리하는 공정이 수행되므로 제1 베이스부(BP1)가 배치되지 않을 수 있다. 또한, 연결 전극(CNE)들은 제2 절연층(PAS2)이 배치되지 않는 부분에 배치되고 제2 절연층(PAS2)의 측면에 걸쳐 배치되므로, 제1 베이스부(BP1)는 연결 전극(CNE)과 제1 기판(SUB)의 두께 방향으로 중첩하지 않을 수 있다. The first base part BP1 may be disposed on the entire surface of the sub-region SA except for a portion of the sub-region SA in which the separation part ROP and connection electrodes CNE, which will be described later, are located. In the separation part ROP, after forming the second insulating layer PAS2 , a process of separating the electrodes RME thereunder is performed, so that the first base part BP1 may not be disposed. In addition, since the connection electrodes CNE are disposed in a portion where the second insulating layer PAS2 is not disposed and are disposed over the side surface of the second insulating layer PAS2 , the first base part BP1 is connected to the connection electrode CNE. and may not overlap in the thickness direction of the first substrate SUB.
제2 베이스부(BP2)는 제2 뱅크(BNL2) 상에 배치된다. 제2 베이스부(BP2)는 제2 뱅크(BNL2)와 유사하게 제1 방향(DR1)으로 연장된 부분과 제2 방향(DR2)으로 연장된 부분 및 제2 방향(DR2)으로 돌출된 부분을 포함할 수 있다. 제2 베이스부(BP2)는 제2 방향(DR2)으로 이웃한 서브 화소(SPXn)들 사이에서 제1 방향(DR1)으로 연장되고, 제1 방향(DR1)으로 이웃한 서브 화소(SPXn) 사이에서 제2 방향(DR2)으로 연장될 수 있다. 각 서브 화소(SPXn)의 발광 영역(EMA)과 서브 영역(SA) 사이에는 제2 베이스부(BP2)의 제1 방향(DR1)으로 연장된 부분에서 일부분이 제2 방향(DR2)으로 돌출되어 제2 뱅크(BNL2) 상에 배치될 수 있다. 각 서브 화소(SPXn)의 발광 영역(EMA)과 서브 영역(SA) 사이에는 연결 전극(CNE)들이 제2 뱅크(BNL2) 상에 배치되므로, 제2 베이스부(BP2)는 각 연결 전극(CNE)들과 중첩하지 않도록 제1 방향(DR1)으로 연장된 부분에서 일부분이 돌출되어 제2 뱅크(BNL2) 상에 배치될 수 있다. 제2 뱅크(BNL2)가 둘러싸는 서브 영역(SA)의 경계에서, 제1 베이스부(BP1)와 제2 베이스부(BP2)는 서로 맞닿아 연결될 수 있다.The second base part BP2 is disposed on the second bank BNL2 . Similar to the second bank BNL2 , the second base part BP2 includes a portion extending in the first direction DR1 , a portion extending in the second direction DR2 , and a portion protruding in the second direction DR2 . may include The second base part BP2 extends in the first direction DR1 between sub-pixels SPXn adjacent in the second direction DR2 and between sub-pixels SPXn adjacent in the first direction DR1 . may extend in the second direction DR2. Between the emission area EMA and the sub area SA of each sub-pixel SPXn, a portion of the second base part BP2 extending in the first direction DR1 is protruded in the second direction DR2. It may be disposed on the second bank BNL2 . Since the connection electrodes CNE are disposed on the second bank BNL2 between the emission area EMA and the sub area SA of each sub-pixel SPXn, the second base part BP2 is connected to each connection electrode CNE. ) may protrude from a portion extending in the first direction DR1 to be disposed on the second bank BNL2 . At the boundary of the sub-region SA surrounded by the second bank BNL2 , the first base part BP1 and the second base part BP2 may be connected to each other in contact with each other.
제1 베이스부(BP1)와 제2 베이스부(BP2)는 각각 제1 패턴부(PT1)와 동일한 두께를 갖고, 그보다 제2 방향(DR2)으로 측정된 폭이 더 클 수 있다. 제1 패턴부(PT1)는 발광 소자(ED)의 길이보다 짧은 폭을 가지나, 제1 베이스부(BP1) 및 제2 베이스부(BP2)는 그 폭이 제2 뱅크(BNL2)보다 크거나 제2 뱅크(BNL2)가 둘러싸는 영역과 동일할 수 있다. 제1 패턴부(PT1) 대비 제1 베이스부(BP1) 및 제2 베이스부(BP2)는 박리되지 않고 제1 절연층(PAS1), 및 제2 뱅크(BNL2) 상에 견고하게 배치될 수 있다. Each of the first base part BP1 and the second base part BP2 may have the same thickness as the first pattern part PT1 , and a width measured in the second direction DR2 may be greater than that. The first pattern part PT1 has a width shorter than the length of the light emitting element ED, but the first base part BP1 and the second base part BP2 have a width greater than or equal to that of the second bank BNL2. It may be the same as the area surrounded by the two banks BNL2. Compared to the first pattern part PT1 , the first base part BP1 and the second base part BP2 may be firmly disposed on the first insulating layer PAS1 and the second bank BNL2 without being peeled off. .
도 7에 도시된 바와 같이, 제1 패턴부(PT1)는 제1 방향(DR1)으로 연장되어 제2 뱅크(BNL2)를 넘어 제1 베이스부(BP1)까지 연장될 수 있다. 제1 패턴부(PT1)의 제1 방향(DR1) 일 측은 제2 뱅크(BNL2) 상에 배치된 제2 베이스부(BP2)와 연결되고, 제1 방향(DR1) 타 측은 서브 영역(SA)까지 연장되어 제1 베이스부(BP1)와 연결될 수 있다. 제1 패턴부(PT1)의 상기 일 측은 제2 베이스부(BP2) 중 서브 화소(SPXn)의 경계에 배치되어 제2 방향(DR2)으로 연장된 부분과 연결될 수 있다. 제1 베이스부(BP1)는 연결 전극(CNE)들 사이에 배치되어 제1 패턴부(PT1)와 연결된 연결 패턴부(CNP)를 가질 수 있고, 제1 패턴부(PT1)는 제1 베이스부(BP1) 및 제2 베이스부(BP2)와 연결되어 후속 공정이 진행되는 동안 박리되지 않도록 베이스부(BP1, BP2)들에 의해 지지될 수 있다. 표시 장치(10)는 제2 절연층(PAS2)이 발광 소자(ED)를 고정하는 제1 패턴부(PT1)의 박리를 방지하는 구조를 가질 수 있고, 이후 공정에서 발광 소자(ED) 및 제1 패턴부(PT1)가 이탈되어 이물로 남는 문제를 방지할 수 있다.7 , the first pattern part PT1 may extend in the first direction DR1 to extend beyond the second bank BNL2 to the first base part BP1 . One side of the first pattern part PT1 in the first direction DR1 is connected to the second base part BP2 disposed on the second bank BNL2 , and the other side of the first pattern part DR1 is a sub area SA. may be extended to be connected to the first base part BP1. The one side of the first pattern portion PT1 may be disposed at the boundary of the sub-pixel SPXn of the second base portion BP2 and may be connected to a portion extending in the second direction DR2 . The first base part BP1 may have a connection pattern part CNP disposed between the connection electrodes CNE and connected to the first pattern part PT1 , and the first pattern part PT1 may have a first base part. It is connected to the BP1 and the second base part BP2 and may be supported by the base parts BP1 and BP2 so as not to be peeled off during a subsequent process. The display device 10 may have a structure in which the second insulating layer PAS2 prevents peeling of the first pattern portion PT1 fixing the light emitting device ED, and in a subsequent process, the light emitting device ED and the second insulating layer PAS2 are formed. 1 It is possible to prevent a problem that the pattern part PT1 is separated and remains as a foreign material.
한편, 도면에서는 제2 절연층(PAS2)의 제1 패턴부(PT1), 제1 베이스부(BP1) 및 제2 베이스부(BP2)를 구분하여 지칭하였으나, 이들은 하나로 일체화된 부분일 수 있다. 제2 절연층(PAS2)의 각 부분들은 배치된 위치, 및 다른 부재와의 연결 관계에 따라 구분된 것이지만, 이들은 동일한 공정에서 형성되어 하나의 제2 절연층(PAS2)을 구성하는 것일 수 있다. Meanwhile, in the drawings, the first pattern portion PT1 , the first base portion BP1 , and the second base portion BP2 of the second insulating layer PAS2 are separately referred to, but these may be integrated into one. Although each part of the second insulating layer PAS2 is divided according to an arrangement position and a connection relationship with other members, they may be formed in the same process to constitute one second insulating layer PAS2 .
복수의 연결 전극(CNE; CNE1, CNE2)들은 복수의 전극(RME)들, 및 발광 소자(ED)들 상에 배치될 수 있다. 또한, 연결 전극(CNE)들은 부분적으로 제2 절연층(PAS2)의 제1 패턴부(PT1) 측면에 걸쳐 배치되며, 다른 연결 전극(CNE)과 제1 패턴부(PT1)를 사이에 두고 제2 방향(DR2)으로 이격될 수 있다. 각 연결 전극(CNE)들 중 제1 패턴부(PT1) 측면에 배치된 부분은 그 높이가 제1 패턴부(PT1)의 높이보다 낮을 수 있고, 제2 절연층(PAS2)의 제1 패턴부(PT1)는 상면에 연결 전극(CNE)들이 배치되지 않을 수 있다. 제2 절연층(PAS2)의 다른 부분들, 예컨대 제1 베이스부(BP1) 및 제2 베이스부(BP2)에서도 연결 전극(CNE)들과 맞닿는 부분은 각 베이스부(BP1, BP2)의 측면에서 연결 전극(CNE)들과 접촉할 수 있다. 즉, 일 실시예에서 복수의 연결 전극(CNE)들은 제2 절연층(PAS2)과 두께 방향으로 중첩하지 않을 수 있다. 복수의 연결 전극(CNE)들은 제2 절연층(PAS2) 상부에 배치되는 연결 전극들의 재료를 제거하는 공정을 통해 서로 이격된 제1 연결 전극(CNE1)과 제2 연결 전극(CNE2)을 형성될 수 있고, 제2 절연층(PAS2) 상에는 연결 전극(CNE)들이 배치되지 않을 수 있다. The plurality of connection electrodes CNE; CNE1 and CNE2 may be disposed on the plurality of electrodes RME and the light emitting devices ED. Also, the connection electrodes CNE are partially disposed on the side surface of the first pattern part PT1 of the second insulating layer PAS2, and are formed with the other connection electrode CNE and the first pattern part PT1 interposed therebetween. They may be spaced apart in two directions DR2. A portion of each of the connection electrodes CNE disposed on a side surface of the first pattern portion PT1 may have a height lower than a height of the first pattern portion PT1 , and the first pattern portion of the second insulating layer PAS2 . Connection electrodes CNE may not be disposed on the upper surface of PT1. In other portions of the second insulating layer PAS2 , for example, in the first base portion BP1 and the second base portion BP2 , also in contact with the connection electrodes CNE, from the side surface of each base portion BP1 and BP2 . It may be in contact with the connection electrodes CNE. That is, in an embodiment, the plurality of connection electrodes CNE may not overlap the second insulating layer PAS2 in the thickness direction. The plurality of connection electrodes CNE may be formed to form a first connection electrode CNE1 and a second connection electrode CNE2 spaced apart from each other through a process of removing the material of the connection electrodes disposed on the second insulating layer PAS2. Also, the connection electrodes CNE may not be disposed on the second insulating layer PAS2 .
복수의 연결 전극(CNE)들은 각각 발광 소자(ED) 및 전극(RME)들과 접촉할 수 있다. 연결 전극(CNE)은 발광 소자(ED)의 양 단부면에 노출된 반도체층과 직접 접촉할 수 있고, 제1 절연층(PAS1)을 관통하는 컨택부(CT1, CT2)를 통해 전극(RME)들 중 적어도 어느 하나와 접촉할 수 있다. 발광 소자(ED)의 양 단부는 복수의 연결 전극(CNE1, CNE2)들을 통해 전극(RME)과 전기적으로 연결될 수 있다. The plurality of connection electrodes CNE may contact the light emitting element ED and the electrodes RME, respectively. The connection electrode CNE may directly contact the semiconductor layer exposed on both end surfaces of the light emitting element ED, and the electrode RME through the contact portions CT1 and CT2 penetrating the first insulating layer PAS1. may be in contact with at least one of them. Both ends of the light emitting device ED may be electrically connected to the electrode RME through the plurality of connection electrodes CNE1 and CNE2 .
제1 연결 전극(CNE1)은 제1 방향(DR1)으로 연장된 형상을 갖고 제1 전극(RME1) 상에 배치될 수 있다. 제1 연결 전극(CNE1) 중 제1 뱅크부(BN1) 상에 배치된 부분은 제1 전극(RME1)과 중첩하고, 이로부터 제1 방향(DR1)으로 연장되어 제2 뱅크(BNL2)를 넘어 서브 영역(SA)까지 배치될 수 있다. 제1 연결 전극(CNE1)은 서브 영역(SA)에서 제2 방향(DR2) 폭이 큰 확장부를 포함하고, 상기 확장부는 제1 전극(RME1)의 상면을 노출하는 제1 컨택부(CT1)를 통해 제1 전극(RME1)과 접촉할 수 있다. 제1 연결 전극(CNE1)은 발광 소자(ED)들의 제1 단부 및 제1 전극(RME1)과 접촉하여 제1 트랜지스터(T1)로부터 인가된 전기 신호(예를 들어, 제1 전압 배선(VL1)으로부터 인가된)를 발광 소자(ED)에 전달할 수 있다. The first connection electrode CNE1 may have a shape extending in the first direction DR1 and may be disposed on the first electrode RME1 . A portion of the first connection electrode CNE1 disposed on the first bank part BN1 overlaps the first electrode RME1 , and extends in the first direction DR1 therefrom to cross the second bank BNL2 . It may be disposed up to the sub area SA. The first connection electrode CNE1 includes an extension having a large width in the second direction DR2 in the sub-region SA, and the extension connects the first contact portion CT1 exposing the top surface of the first electrode RME1. through the first electrode RME1. The first connection electrode CNE1 is in contact with the first end of the light emitting devices ED and the first electrode RME1 to receive an electrical signal (eg, a first voltage line VL1 ) applied from the first transistor T1 . applied) to the light emitting device ED.
제2 연결 전극(CNE2)은 제1 방향(DR1)으로 연장된 형상을 갖고 제2 전극(RME2) 상에 배치될 수 있다. 제2 연결 전극(CNE2) 중 제2 뱅크부(BN2) 상에 배치된 부분은 제2 전극(RME2)과 중첩하고, 이로부터 제1 방향(DR1)으로 연장되어 제2 뱅크(BNL2)를 넘어 서브 영역(SA)까지 배치될 수 있다. 제2 연결 전극(CNE2)은 서브 영역(SA)에서 제2 방향(DR2) 폭이 큰 확장부를 포함하고, 상기 확장부는 제2 전극(RME2)의 상면을 노출하는 제2 컨택부(CT2)를 통해 제2 전극(RME2)과 접촉할 수 있다. 제2 연결 전극(CNE2)은 발광 소자(ED)들의 제2 단부 및 제2 전극(RME2)과 접촉하여 제2 전압 배선(VL2)으로부터 인가된 전기 신호를 발광 소자(ED)에 전달할 수 있다. The second connection electrode CNE2 may have a shape extending in the first direction DR1 and may be disposed on the second electrode RME2 . A portion of the second connection electrode CNE2 disposed on the second bank part BN2 overlaps the second electrode RME2 , and extends in the first direction DR1 therefrom to cross the second bank BNL2 . It may be disposed up to the sub area SA. The second connection electrode CNE2 includes an extension having a large width in the second direction DR2 in the sub area SA, and the extension connects the second contact portion CT2 exposing the top surface of the second electrode RME2 . through the second electrode RME2 . The second connection electrode CNE2 may contact the second end of the light emitting devices ED and the second electrode RME2 to transmit an electrical signal applied from the second voltage line VL2 to the light emitting device ED.
일 실시예에서, 복수의 컨택부(CT1, CT2)들은 발광 소자(ED)들과 제2 방향(DR2)으로 중첩하지 않도록 복수의 발광 소자(ED)들이 배치되는 영역과 제1 방향(DR1)으로 이격되어 형성될 수 있다. 도 4 및 도 7에서는 복수의 컨택부(CT1, CT2)들이 서브 영역(SA)에 배치된 것이 예시되어 있으나, 이에 제한되지 않고 복수의 컨택부(CT1, CT2)들은 발광 영역(EMA) 중 발광 소자(ED)들이 배치되지 않는 부분에 형성될 수 있다. In an embodiment, the plurality of contact portions CT1 and CT2 do not overlap with the light emitting devices ED in the second direction DR2 in the region where the plurality of light emitting devices ED are disposed and in the first direction DR1 . may be formed spaced apart from each other. 4 and 7 , it is exemplified that the plurality of contact portions CT1 and CT2 are disposed in the sub area SA, but the present invention is not limited thereto, and the plurality of contact portions CT1 and CT2 emit light in the light emitting area EMA. It may be formed in a portion where the elements ED are not disposed.
제1 연결 전극(CNE1)과 제2 연결 전극(CNE2)은 평면도 상 서로 제2 방향(DR2)으로 이격되어 배치될 수 있다. 제1 연결 전극(CNE1)과 제2 연결 전극(CNE2)은 서로 직접 접촉하지 않도록 배치되고, 각 연결 전극(CNE)에 인가된 전기 신호는 발광 소자(ED)를 통해 흐를 수 있다. 한편, 도면에서는 제1 연결 전극(CNE1)과 제2 연결 전극(CNE2)이 실질적으로 동일한 층에 배치된 것이 예시되어 있다. 다만, 이에 제한되지 않으며, 몇몇 실시예에서, 제1 연결 전극(CNE1)과 제2 연결 전극(CNE2)은 서로 다른 층에 배치될 수 있고, 이들 사이에는 다른 절연층이 더 배치될 수 있다. The first connection electrode CNE1 and the second connection electrode CNE2 may be disposed to be spaced apart from each other in the second direction DR2 in a plan view. The first connection electrode CNE1 and the second connection electrode CNE2 are disposed not to directly contact each other, and an electrical signal applied to each connection electrode CNE may flow through the light emitting device ED. Meanwhile, in the drawings, it is exemplified that the first connection electrode CNE1 and the second connection electrode CNE2 are disposed on substantially the same layer. However, the present invention is not limited thereto, and in some embodiments, the first connection electrode CNE1 and the second connection electrode CNE2 may be disposed on different layers, and another insulating layer may be further disposed between them.
연결 전극(CNE)들은 전도성 물질을 포함할 수 있다. 예를 들어, ITO, IZO, ITZO, 알루미늄(Al) 등을 포함할 수 있다. 일 예로, 연결 전극(CNE)은 투명성 전도성 물질을 포함하고, 발광 소자(ED)에서 방출된 광은 연결 전극(CNE)을 투과하여 전극(RME)들을 향해 진행할 수 있다. 다만, 이에 제한되는 것은 아니다.The connection electrodes CNE may include a conductive material. For example, it may include ITO, IZO, ITZO, aluminum (Al), and the like. For example, the connection electrode CNE may include a transparent conductive material, and light emitted from the light emitting device ED may pass through the connection electrode CNE and travel toward the electrodes RME. However, the present invention is not limited thereto.
몇몇 실시예에서, 제2 절연층(PAS2), 및 복수의 연결 전극(CNE)들 상에는 다른 절연층이 더 배치될 수 있다. 상기 절연층은 제1 기판(SUB) 상에 배치된 부재들을 외부 환경에 대하여 보호하는 기능을 할 수 있다. In some embodiments, another insulating layer may be further disposed on the second insulating layer PAS2 and the plurality of connection electrodes CNE. The insulating layer may serve to protect members disposed on the first substrate SUB from an external environment.
상술한 제1 절연층(PAS1)은 무기물 절연성 물질 또는 유기물 절연성 물질을 포함하고, 제2 절연층(PAS2)은 유기물 절연성 물질을 포함할 수 있다. 다만, 이에 제한되는 것은 아니다. The above-described first insulating layer PAS1 may include an inorganic insulating material or an organic insulating material, and the second insulating layer PAS2 may include an organic insulating material. However, the present invention is not limited thereto.
도 8은 일 실시예에 따른 발광 소자의 개략도이다. 8 is a schematic diagram of a light emitting device according to an embodiment.
도 8을 참조하면, 발광 소자(ED)는 발광 다이오드(Light Emitting diode)일 수 있으며, 예를 들어 발광 소자(ED)는 나노 미터(Nano-meter) 내지 마이크로 미터(Micro-meter) 단위의 크기를 가지고, 무기물로 이루어진 무기 발광 다이오드일 수 있다. 발광 소자(ED)는 서로 대향하는 두 전극들 사이에 특정 방향으로 전계를 형성하면 극성이 형성되는 상기 두 전극 사이에 정렬될 수 있다. Referring to FIG. 8 , the light emitting device ED may be a light emitting diode, for example, the light emitting device ED has a size of nanometers to micrometers. and may be an inorganic light emitting diode made of an inorganic material. The light emitting device ED may be aligned between the two electrodes in which polarities are formed when an electric field is formed in a specific direction between the two electrodes facing each other.
일 실시예에 따른 발광 소자(ED)는 일 방향으로 연장된 형상을 가질 수 있다. 발광 소자(ED)는 원통, 로드(Rod), 와이어(Wire), 튜브(Tube) 등의 형상을 가질 수 있다. 다만, 발광 소자(ED)의 형태가 이에 제한되는 것은 아니며, 정육면체, 직육면체, 육각기둥형 등 다각기둥의 형상을 갖거나, 일 방향으로 연장되되 외면이 부분적으로 경사진 형상을 갖는 등 발광 소자(ED)는 다양한 형태를 가질 수 있다. The light emitting device ED according to an embodiment may have a shape extending in one direction. The light emitting device ED may have a shape such as a cylinder, a rod, a wire, or a tube. However, the shape of the light emitting element (ED) is not limited thereto, and the light emitting element ( ED) may have various forms.
발광 소자(ED)는 임의의 도전형(예컨대, p형 또는 n형) 불순물로 도핑된 반도체층을 포함할 수 있다. 반도체층은 외부의 전원으로부터 인가되는 전기 신호가 전달되어 특정 파장대의 광을 방출할 수 있다. 발광 소자(ED)는 제1 반도체층(31), 제2 반도체층(32), 발광층(36), 전극층(37) 및 절연막(38)을 포함할 수 있다. The light emitting device ED may include a semiconductor layer doped with an arbitrary conductivity type (eg, p-type or n-type) impurity. The semiconductor layer may emit an electric signal applied from an external power source to emit light in a specific wavelength band. The light emitting device ED may include a first semiconductor layer 31 , a second semiconductor layer 32 , a light emitting layer 36 , an electrode layer 37 , and an insulating layer 38 .
제1 반도체층(31)은 n형 반도체일 수 있다. 제1 반도체층(31)은 AlxGayIn1-x-yN(0≤x≤1,0≤y≤1, 0≤x+y≤1)의 화학식을 갖는 반도체 재료를 포함할 수 있다. 예를 들어, 제1 반도체층(31)은 n형으로 도핑된 AlGaInN, GaN, AlGaN, InGaN, AlN 및 InN 중에서 어느 하나 이상일 수 있다. 제1 반도체층(31)에 도핑된 n형 도펀트는 Si, Ge, Sn, Se 등일 수 있다. The first semiconductor layer 31 may be an n-type semiconductor. The first semiconductor layer 31 may include a semiconductor material having a chemical formula of AlxGayIn1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the first semiconductor layer 31 may be any one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with n-type. The n-type dopant doped in the first semiconductor layer 31 may be Si, Ge, Sn, Se, or the like.
제2 반도체층(32)은 발광층(36)을 사이에 두고 제1 반도체층(31) 상에 배치된다. 제2 반도체층(32)은 p형 반도체일 수 있으며, 제2 반도체층(32)은 AlxGayIn1-x-yN(0≤x≤1,0≤y≤1, 0≤x+y≤1)의 화학식을 갖는 반도체 재료를 포함할 수 있다. 예를 들어, 제2 반도체층(32)은 p형으로 도핑된 AlGaInN, GaN, AlGaN, InGaN, AlN 및 InN 중에서 어느 하나 이상일 수 있다. 제2 반도체층(32)에 도핑된 p형 도펀트는 Mg, Zn, Ca, Ba 등일 수 있다. The second semiconductor layer 32 is disposed on the first semiconductor layer 31 with the light emitting layer 36 interposed therebetween. The second semiconductor layer 32 may be a p-type semiconductor, and the second semiconductor layer 32 is composed of AlxGayIn1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1). and a semiconductor material having a chemical formula. For example, the second semiconductor layer 32 may be any one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with p-type. The p-type dopant doped in the second semiconductor layer 32 may be Mg, Zn, Ca, Ba, or the like.
한편, 도면에서는 제1 반도체층(31)과 제2 반도체층(32)이 하나의 층으로 구성된 것을 도시하고 있으나, 이에 제한되는 것은 아니다. 발광층(36)의 물질에 따라 제1 반도체층(31)과 제2 반도체층(32)은 더 많은 수의 층, 예컨대 클래드층(Clad layer) 또는 TSBR(Tensile strain barrier reducing)층을 더 포함할 수도 있다. Meanwhile, although the drawing shows that the first semiconductor layer 31 and the second semiconductor layer 32 are configured as one layer, the present invention is not limited thereto. Depending on the material of the light emitting layer 36, the first semiconductor layer 31 and the second semiconductor layer 32 may further include a larger number of layers, for example, a clad layer or a TSBR (Tensile strain barrier reducing) layer. may be
발광층(36)은 제1 반도체층(31)과 제2 반도체층(32) 사이에 배치된다. 발광층(36)은 단일 또는 다중 양자 우물 구조의 물질을 포함할 수 있다. 발광층(36)이 다중 양자 우물 구조의 물질을 포함하는 경우, 양자층(Quantum layer)과 우물층(Well layer)이 서로 교번적으로 복수 개 적층된 구조일 수도 있다. 발광층(36)은 제1 반도체층(31) 및 제2 반도체층(32)을 통해 인가되는 전기 신호에 따라 전자-정공 쌍의 결합에 의해 광을 발광할 수 있다. 발광층(36)은 AlGaN, AlGaInN 등의 물질을 포함할 수 있다. 예를 들어, 발광층(36)이 다중 양자 우물 구조로 양자층과 우물층이 교번적으로 적층된 구조인 경우, 양자층은 AlGaN 또는 AlGaInN, 우물층은 GaN 또는 AlInN 등과 같은 물질을 포함할 수 있다. The light emitting layer 36 is disposed between the first semiconductor layer 31 and the second semiconductor layer 32 . The light emitting layer 36 may include a material having a single or multiple quantum well structure. When the light emitting layer 36 includes a material having a multi-quantum well structure, it may have a structure in which a plurality of quantum layers and a well layer are alternately stacked. The light emitting layer 36 may emit light by combining electron-hole pairs according to an electric signal applied through the first semiconductor layer 31 and the second semiconductor layer 32 . The emission layer 36 may include a material such as AlGaN or AlGaInN. For example, when the light emitting layer 36 has a multi-quantum well structure in which quantum layers and well layers are alternately stacked, the quantum layer may include a material such as AlGaN or AlGaInN, and the well layer may include a material such as GaN or AlInN. .
발광층(36)은 밴드갭(Band gap) 에너지가 큰 종류의 반도체 물질과 밴드갭 에너지가 작은 반도체 물질들이 서로 교번적으로 적층된 구조일 수도 있고, 발광하는 광의 파장대에 따라 다른 3족 내지 5족 반도체 물질들을 포함할 수도 있다. 발광층(36)이 방출하는 광은 청색 파장대의 광으로 제한되지 않고, 경우에 따라 적색, 녹색 파장대의 광을 방출할 수도 있다. The light emitting layer 36 may have a structure in which a type of semiconductor material having a large band gap energy and a semiconductor material having a small band gap energy are alternately stacked with each other, and groups 3 to 5 are different according to the wavelength band of the emitted light. It may also include semiconductor materials. The light emitted by the light emitting layer 36 is not limited to light of a blue wavelength band, and in some cases, light of a red and green wavelength band may be emitted.
전극층(37)은 오믹(Ohmic) 연결 전극일 수 있다. 다만, 이에 제한되지 않고, 쇼트키(Schottky) 연결 전극일 수도 있다. 발광 소자(ED)는 적어도 하나의 전극층(37)을 포함할 수 있다. 발광 소자(ED)는 하나 이상의 전극층(37)을 포함할 수 있으나, 이에 제한되지 않고 전극층(37)은 생략될 수도 있다. The electrode layer 37 may be an ohmic connection electrode. However, the present invention is not limited thereto, and may be a Schottky connection electrode. The light emitting device ED may include at least one electrode layer 37 . The light emitting device ED may include one or more electrode layers 37 , but the present invention is not limited thereto and the electrode layers 37 may be omitted.
전극층(37)은 표시 장치(10)에서 발광 소자(ED)가 전극 또는 연결 전극과 전기적으로 연결될 때, 발광 소자(ED)와 전극 또는 연결 전극 사이의 저항을 감소시킬 수 있다. 전극층(37)은 전도성이 있는 금속을 포함할 수 있다. 예를 들어, 전극층(37)은 알루미늄(Al), 티타늄(Ti), 인듐(In), 금(Au), 은(Ag), ITO, IZO 및 ITZO 중에서 적어도 어느 하나를 포함할 수 있다. The electrode layer 37 may reduce resistance between the light emitting element ED and the electrode or the connection electrode when the light emitting element ED is electrically connected to an electrode or a connection electrode in the display device 10 . The electrode layer 37 may include a conductive metal. For example, the electrode layer 37 may include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), ITO, IZO, and ITZO.
절연막(38)은 상술한 복수의 반도체층 및 전극층의 외면을 둘러싸도록 배치된다. 예를 들어, 절연막(38)은 적어도 발광층(36)의 외면을 둘러싸도록 배치되되, 발광 소자(ED)의 길이방향의 양 단부는 노출되도록 형성될 수 있다. 또한, 절연막(38)은 발광 소자(ED)의 적어도 일 단부와 인접한 영역에서 단면상 상면이 라운드지게 형성될 수도 있다. The insulating film 38 is disposed so as to surround the outer surfaces of the plurality of semiconductor layers and the electrode layers described above. For example, the insulating layer 38 may be disposed to surround at least the outer surface of the light emitting layer 36 , and both ends of the light emitting device ED in the longitudinal direction may be exposed. In addition, the insulating layer 38 may be formed to have a round top surface in cross-section in a region adjacent to at least one end of the light emitting device ED.
절연막(38)은 절연특성을 가진 물질들, 예를 들어, 실리콘 산화물(SiOx), 실리콘 질화물(SiNx), 실리콘 산질화물 (SiOxNy), 질화알루미늄(AlNx), 산화알루미늄(AlOx) 등을 포함할 수 있다. 도면에서는 절연막(38)이 단일층으로 형성된 것이 예시되어 있으나 이에 제한되지 않으며, 몇몇 실시예에서 절연막(38)은 복수의 층이 적층된 다중층 구조로 형성될 수도 있다.The insulating layer 38 is formed of materials having insulating properties, for example, silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide ( AlO x ) and the like. In the drawings, it is illustrated that the insulating film 38 is formed as a single layer, but the present invention is not limited thereto, and in some embodiments, the insulating film 38 may be formed in a multi-layered structure in which a plurality of layers are stacked.
절연막(38)은 상기 부재들을 보호하는 기능을 수행할 수 있다. 절연막(38)은 발광 소자(ED)에 전기 신호가 전달되는 전극과 직접 접촉하는 경우 발광층(36)에 발생할 수 있는 전기적 단락을 방지할 수 있다. 또한, 절연막(38)은 발광 소자(ED)의 발광 효율의 저하를 방지할 수 있다.The insulating layer 38 may function to protect the members. The insulating layer 38 may prevent an electrical short that may occur in the light emitting layer 36 when it is in direct contact with an electrode through which an electrical signal is transmitted to the light emitting device ED. In addition, the insulating layer 38 may prevent a decrease in the luminous efficiency of the light emitting device ED.
또한, 절연막(38)은 외면이 표면처리될 수 있다. 발광 소자(ED)는 소정의 잉크 내에서 분산된 상태로 전극 상에 분사되어 정렬될 수 있다. 여기서, 발광 소자(ED)가 잉크 내에서 인접한 다른 발광 소자(ED)와 응집되지 않고 분산된 상태를 유지하기 위해, 절연막(38)은 표면이 소수성 또는 친수성 처리될 수 있다. In addition, the outer surface of the insulating film 38 may be surface-treated. The light emitting device ED may be sprayed onto the electrode in a state of being dispersed in a predetermined ink to be aligned. Here, in order to maintain the light emitting device ED in a dispersed state without agglomeration with other light emitting devices ED adjacent in the ink, the surface of the insulating layer 38 may be treated with hydrophobicity or hydrophilicity.
일 실시예에 따른 표시 장치(10)는 제2 절연층(PAS2)이 발광 소자(ED)들 상에서 배치된 제1 패턴부(PT1)의 박리를 방지하는 구조를 가질 수 있다. 제2 절연층(PAS2)의 구조 및 형상은 각 서브 화소(SPXn)들에 배치된 전극(RME)들의 개수에 따라 다양하게 변형될 수 있다. 이하, 다른 도면들을 더 참조하여 표시 장치(10)의 다양한 실시예들에 대하여 설명하기로 한다.The display device 10 according to an exemplary embodiment may have a structure in which the second insulating layer PAS2 prevents peeling of the first pattern portion PT1 disposed on the light emitting devices ED. The structure and shape of the second insulating layer PAS2 may be variously modified according to the number of electrodes RME disposed in each of the sub-pixels SPXn. Hereinafter, various embodiments of the display device 10 will be described with further reference to other drawings.
도 9는 다른 실시예에 따른 표시 장치의 일 서브 화소를 나타내는 평면도이다. 도 10은 도 9의 Q3-Q3'선을 따라 자른 단면도이다. 도 11은 도 9의 A2부분의 확대도이다.9 is a plan view illustrating one sub-pixel of a display device according to another exemplary embodiment. FIG. 10 is a cross-sectional view taken along line Q3-Q3' of FIG. 9 . 11 is an enlarged view of a portion A2 of FIG. 9 .
도 9 내지 도 11을 참조하면, 일 실시예에 따른 표시 장치(10_1)는 각 서브 화소(SPXn)마다 더 많은 수의 전극(RME_1)들을 포함할 수 있고, 각 서브 화소(SPXn)에 배치되는 발광 소자(ED)들의 개수가 증가할 수 있다. 그에 따라, 제2 절연층(PAS2_1)은 복수의 패턴부(PT1, PT2)들에 더하여, 이들의 박리를 방지하기 위해 각 패턴부(PT1, PT2)와 연결된 다른 패턴부(SP1)들을 더 포함할 수 있다. 9 to 11 , the display device 10_1 according to an exemplary embodiment may include a larger number of electrodes RME_1 for each sub-pixel SPXn, and is disposed in each sub-pixel SPXn. The number of light emitting devices ED may increase. Accordingly, the second insulating layer PAS2_1 further includes, in addition to the plurality of pattern parts PT1 and PT2 , other pattern parts SP1 connected to each of the pattern parts PT1 and PT2 to prevent peeling thereof. can do.
제1 뱅크(BNL1_1)는 제1 뱅크부(BN1) 및 제2 뱅크부(BN2)에 더하여 이들과 다른 폭을 갖는 제3 뱅크부(BN3)를 더 포함할 수 있다. 제3 뱅크부(BN3)는 제1 뱅크부(BN1) 및 제2 뱅크부(BN2) 사이에 배치되고, 제1 방향(DR1)으로 연장된 형상을 가질 수 있다. 제1 뱅크부(BN1), 제2 뱅크부(BN2) 및 제3 뱅크부(BN3)는 각각 제1 방향(DR1)으로 연장된 길이는 서로 동일하되, 제2 방향(DR2)으로 측정된 폭은 제3 뱅크부(BN3)가 다른 뱅크부들보다 클 수 있다. The first bank BNL1_1 may further include a third bank unit BN3 having a width different from that of the first bank unit BN1 and the second bank unit BN2 . The third bank part BN3 may be disposed between the first bank part BN1 and the second bank part BN2 and may have a shape extending in the first direction DR1 . The first bank part BN1 , the second bank part BN2 , and the third bank part BN3 have the same length extending in the first direction DR1 , but have a width measured in the second direction DR2 . The third bank unit BN3 may be larger than other bank units.
제3 뱅크부(BN3)는 제1 뱅크부(BN1) 및 제2 뱅크부(BN2)들과 제2 방향(DR2)으로 이격되어 배치될 수 있다. 제3 뱅크부(BN3)는 후술하는 제3 전극(RME3)이 배치될 수 있도록 제1 뱅크부(BN1)보다 큰 폭을 가질 수 있다. 제1 뱅크부(BN1)와 제3 뱅크부(BN3) 사이, 및 제2 뱅크부(BN2)와 제3 뱅크부(BN3) 사이에는 각각 발광 소자(ED)들이 배치될 수 있다. The third bank unit BN3 may be disposed to be spaced apart from the first bank unit BN1 and the second bank units BN2 in the second direction DR2 . The third bank part BN3 may have a width greater than that of the first bank part BN1 so that a third electrode RME3 to be described later may be disposed. The light emitting devices ED may be respectively disposed between the first bank unit BN1 and the third bank unit BN3 and between the second bank unit BN2 and the third bank unit BN3 .
제1 전극(RME1)은 제1 뱅크부(BN1) 상에 배치되고, 제2 전극(RME2)은 제2 뱅크부(BN2) 상에 배치될 수 있다. 이에 대한 설명은 도 2 및 도 3을 참조하여 상술한 바와 동일하다.The first electrode RME1 may be disposed on the first bank part BN1 , and the second electrode RME2 may be disposed on the second bank part BN2 . A description thereof is the same as described above with reference to FIGS. 2 and 3 .
제3 전극(RME3)은 제3 뱅크부(BN3) 상에 배치된다. 제3 전극(RME3)은 제1 전극(RME1)과 제2 전극(RME2) 사이에서 제1 방향(DR1)으로 연장되어 발광 영역(EMA) 및 서브 영역(SA)에 걸쳐 배치될 수 있다. 몇몇 실시예에서, 제3 전극(RME3)의 폭은 제1 전극(RME1) 및 제2 전극(RME2)보다 크고, 제3 뱅크부(BN3)의 폭보다 클 수 있다. 제3 전극(RME3)은 제3 뱅크부(BN3)의 양 측면을 덮도록 배치되며, 각각 제1 전극(RME1) 및 제2 전극(RME2)과 제2 방향(DR2)으로 이격되어 대향할 수 있다.The third electrode RME3 is disposed on the third bank part BN3 . The third electrode RME3 may extend in the first direction DR1 between the first electrode RME1 and the second electrode RME2 to cover the emission area EMA and the sub area SA. In some embodiments, the width of the third electrode RME3 may be greater than that of the first electrode RME1 and the second electrode RME2 , and may be greater than the width of the third bank part BN3 . The third electrode RME3 is disposed to cover both side surfaces of the third bank unit BN3 , and may face the first electrode RME1 and the second electrode RME2 respectively in the second direction DR2 to face each other. have.
제3 전극(RME3)은 제1 전극(RME1)과 유사하게 비아층(VIA) 하부의 제3 도전층과 연결될 수 있다. 제3 전극(RME3)은 제2 뱅크(BNL2)와 두께 방향으로 중첩하는 부분에 형성된 제2 전극 컨택홀(CTS)을 통해 제2 전압 배선(VL2)과 연결될 수 있다. 다만, 제2 전극(RME2)은 제1 전극(RME1) 및 제3 전극(RME3)과 달리 제3 도전층과 연결되지 않을 수 있다. 제2 전극(RME2)은 제2 연결 전극(CNE2)과 연결되고, 발광 소자(ED)들을 따라 흐르는 전기 신호가 인가될 수 있다. 후술할 바와 같이, 제2 전극(RME2)은 제2 연결 전극(CNE2)과 함께 서로 다른 발광 소자(ED)들의 전기적 연결 경로를 제공할 수 있다. The third electrode RME3 may be connected to the third conductive layer under the via layer VIA similarly to the first electrode RME1 . The third electrode RME3 may be connected to the second voltage line VL2 through the second electrode contact hole CTS formed in a portion overlapping the second bank BNL2 in the thickness direction. However, unlike the first electrode RME1 and the third electrode RME3 , the second electrode RME2 may not be connected to the third conductive layer. The second electrode RME2 may be connected to the second connection electrode CNE2 , and an electrical signal flowing along the light emitting devices ED may be applied thereto. As will be described later, the second electrode RME2 and the second connection electrode CNE2 may provide electrical connection paths between different light emitting devices ED.
발광 소자(ED)들은 제1 뱅크부(BN1)와 제3 뱅크부(BN3) 사이, 및 제3 뱅크부(BN3)와 제2 뱅크부(BN2) 사이에 배치될 수 있다. 제1 뱅크부(BN1)와 제3 뱅크부(BN3) 사이에 배치된 제1 발광 소자(ED1)는 제1 단부가 제1 전극(RME1) 상에 배치되고, 제2 단부가 제3 전극(RME3)의 일 측 상에 배치될 수 있다. 제3 뱅크부(BN3)와 제2 뱅크부(BN2) 사이에 배치된 제2 발광 소자(ED2)는 제1 단부가 제2 전극(RME2) 상에 배치되고, 제2 단부가 제3 전극(RME3)의 타 측 상에 배치될 수 있다. 일 실시예에서 제1 발광 소자(ED1)와 제2 발광 소자(ED2)는 제1 단부가 향하는 방향이 서로 반대 방향일 수 있다. The light emitting devices ED may be disposed between the first bank part BN1 and the third bank part BN3 and between the third bank part BN3 and the second bank part BN2 . The first light emitting device ED1 disposed between the first bank part BN1 and the third bank part BN3 has a first end disposed on the first electrode RME1 and a second end disposed on the third electrode ( RME1 ). may be disposed on one side of the RME3). The second light emitting device ED2 disposed between the third bank part BN3 and the second bank part BN2 has a first end disposed on the second electrode RME2 and a second end disposed on the third electrode ( RME2 ). may be disposed on the other side of RME3). In an embodiment, the first light emitting device ED1 and the second light emitting device ED2 may have a direction opposite to that of the first end thereof.
제2 절연층(PAS2_1)은 제1 뱅크(BNL1)의 뱅크부(BN1, BN2, BN3)들 사이에서 각 발광 소자(ED)들 상에 배치된 제1 패턴부(PT1)와 제2 패턴부(PT2)를 포함할 수 있다. 제1 패턴부(PT1) 및 제2 패턴부(PT2)는 각각 제1 방향(DR1)으로 연장되어 제1 발광 소자(ED1)들 및 제2 발광 소자(ED2)들을 덮을 수 있다. 이들은 복수의 발광 소자(ED)들을 감싸면서 고정시킬 수 있다.The second insulating layer PAS2_1 includes a first pattern part PT1 and a second pattern part disposed on each of the light emitting devices ED between the bank parts BN1 , BN2 , and BN3 of the first bank BNL1 . (PT2). The first pattern part PT1 and the second pattern part PT2 may each extend in the first direction DR1 to cover the first light emitting devices ED1 and the second light emitting devices ED2 . These may be fixed while enclosing the plurality of light emitting devices ED.
도 2 내지 도 7을 참조하여 상술한 바와 같이, 제1 패턴부(PT1)와 제2 패턴부(PT2)는 길이 및 두께 대비 얇은 폭을 가질 수 있고, 제2 절연층(PAS2_1)은 이들의 박리를 방지할 수 있는 구조를 가질 수 있다. 일 실시예에 따르면, 제2 절연층(PAS2_1)은 복수의 패턴부(PT1, PT2)들 중 적어도 일부와 연결되는 제1 지지 패턴부(SP1)와, 패턴부(PT1, PT2)들을 제1 지지 패턴부(SP1) 또는 제2 베이스부(BP2)와 연결시키는 복수의 브릿지부(BR1, BR2)들을 더 포함할 수 있다. As described above with reference to FIGS. 2 to 7 , the first pattern part PT1 and the second pattern part PT2 may have a smaller width compared to the length and thickness, and the second insulating layer PAS2_1 may be formed of It may have a structure capable of preventing peeling. According to an exemplary embodiment, the second insulating layer PAS2_1 includes a first support pattern part SP1 connected to at least some of the plurality of pattern parts PT1 and PT2 and the pattern parts PT1 and PT2 as first A plurality of bridge parts BR1 and BR2 connected to the support pattern part SP1 or the second base part BP2 may be further included.
제1 패턴부(PT1)는 제1 방향(DR1)으로 연장되어 제1 방향(DR1) 일 측은 제2 베이스부(BP2)의 제2 방향(DR2)으로 연장된 부분과 연결되고, 제1 방향(DR1) 타 측은 제1 베이스부(BP1)와 연결될 수 있다. 이에 더하여, 제1 패턴부(PT1)는 제1 브릿지부(BR1)를 통해 제2 베이스부(BP2)와 연결될 수 있다. 제1 브릿지부(BR1)는 제2 방향(DR2)으로 연장된 형상을 갖고, 제2 베이스부(BP2) 중 제1 방향(DR1)으로 연장된 부분과 제1 패턴부(PT1)에 연결될 수 있다. 제1 브릿지부(BR1)는 제1 연결 전극(CNE1)의 제1 방향(DR1) 양 단부 중 발광 영역(EMA) 내에 배치된 일 단부와 이격되어 배치될 수 있다. 또는, 제1 연결 전극(CNE1)의 형성 시 공정 조건에 따라 제1 브릿지부(BR1)는 제1 연결 전극(CNE1)의 상기 일 단부와 맞닿아 배치될 수도 있다. 제1 패턴부(PT1)는 제1 방향(DR1)의 양 측에 위치한 베이스부(BP1, BP2)들에 더하여, 제2 방향(DR2)으로 연장되어 배치된 제1 브릿지부(BR1)에 의해 후속 공정이 진행되는 동안 박리되지 않도록 지지될 수 있다. The first pattern part PT1 extends in the first direction DR1 , so that one side of the first direction DR1 is connected to a part extending in the second direction DR2 of the second base part BP2 , the first direction (DR1) The other side may be connected to the first base portion (BP1). In addition, the first pattern part PT1 may be connected to the second base part BP2 through the first bridge part BR1 . The first bridge part BR1 may have a shape extending in the second direction DR2 , and may be connected to a portion of the second base part BP2 extending in the first direction DR1 and the first pattern part PT1 . have. The first bridge part BR1 may be disposed to be spaced apart from one end disposed in the light emitting area EMA among both ends of the first connection electrode CNE1 in the first direction DR1 . Alternatively, the first bridge part BR1 may be disposed in contact with the one end of the first connection electrode CNE1 according to process conditions when the first connection electrode CNE1 is formed. The first pattern part PT1 is formed by the first bridge part BR1 extending in the second direction DR2 in addition to the base parts BP1 and BP2 positioned on both sides of the first direction DR1 . It can be supported so as not to be peeled off during a subsequent process.
제2 패턴부(PT2)도 제1 방향(DR1)으로 연장되어 제1 방향(DR1) 타 측은 제1 베이스부(BP1)와 연결될 수 있다. 다만, 제1 방향(DR1) 일 측에는 제3 연결 전극(CNE3)의 제1 연결부(CN_B1)가 배치되므로, 제2 베이스부(BP2)와 직접 연결되지 못할 수 있다. 제2 패턴부(PT2)는 제1 패턴부(PT1)와의 사이에 배치된 제1 지지 패턴부(SP1)와 연결되어 박리가 방지되는 구조를 가질 수 있다. The second pattern part PT2 may also extend in the first direction DR1 , and the other side of the second pattern part PT2 may be connected to the first base part BP1 . However, since the first connection part CN_B1 of the third connection electrode CNE3 is disposed on one side of the first direction DR1 , it may not be directly connected to the second base part BP2 . The second pattern part PT2 may be connected to the first support pattern part SP1 disposed between the first pattern part PT1 and have a structure in which peeling is prevented.
제1 지지 패턴부(SP1)는 제3 뱅크부(BN3) 및 제3 전극(RME3) 상에서 제1 방향(DR1)으로 연장되어 배치될 수 있다. 제1 지지 패턴부(SP1)는 제3 연결 전극(CNE3)의 제1 연장부(CN_E1)와 제2 연결 전극(CNE2) 사이에 배치되며, 이들은 각각 제1 지지 패턴부(SP1)의 측면과 이격될 수 있다. 다만, 제1 브릿지부(BR1)와 유사하게, 제1 지지 패턴부(SP1)도 연결 전극(CNE_1)들의 형성 공정 조건에 따라 양 측면이 제1 연장부(CN_E1) 및 제2 연결 전극(CNE2)과 접촉할 수 있다. 제1 지지 패턴부(SP1)의 제1 방향(DR1) 일 측은 제1 연결부(CN_B1)와 이격되어 배치되고, 제1 방향(DR1) 타 측은 서브 영역(SA)까지 연장되어 제1 베이스부(BP1)와 연결될 수 있다. 제1 패턴부(PT1)와 제1 지지 패턴부(SP1)의 제1 방향(DR1) 타 측에는 제2 뱅크(BNL2) 상에 배치된 연결 패턴부가 위치하고, 이를 통해 제1 베이스부(BP1)와 연결될 수 있다. The first support pattern part SP1 may be disposed to extend in the first direction DR1 on the third bank part BN3 and the third electrode RME3 . The first support pattern part SP1 is disposed between the first extension part CN_E1 and the second connection electrode CNE2 of the third connection electrode CNE3, and they are respectively disposed on the side surface of the first support pattern part SP1 and the second connection electrode CNE2. can be spaced apart. However, similarly to the first bridge part BR1 , both sides of the first support pattern part SP1 also have the first extension part CN_E1 and the second connection electrode CNE2 according to the forming process conditions of the connection electrodes CNE_1 . ) can be in contact with One side of the first support pattern part SP1 in the first direction DR1 is disposed to be spaced apart from the first connection part CN_B1, and the other side of the first support pattern part SP1 extends to the sub-region SA to the first base part ( BP1) can be linked. A connection pattern portion disposed on the second bank BNL2 is positioned on the other side of the first pattern portion PT1 and the first support pattern portion SP1 in the first direction DR1, and through this, the first base portion BP1 and can be connected
제2 브릿지부(BR2)는 제2 방향(DR2)으로 연장된 형상을 갖고, 제1 지지 패턴부(SP1) 및 제2 패턴부(PT2)에 연결될 수 있다. 제2 브릿지부(BR2)는 제2 연결 전극(CNE2)의 제1 방향(DR1) 양 단부 중 발광 영역(EMA) 내에 배치된 일 단부와 제3 연결 전극(CNE3)의 제1 연결부(CN_B1)에 각각 이격되어 배치될 수 있다. 또는 제2 브릿지부(BR2)는 제2 연결 전극(CNE2) 및 제1 연결부(CN_B1)와 접촉할 수 있다. 제1 패턴부(PT1)는 제1 방향(DR1)의 타 측에 위치한 제1 베이스부(BP1)에 더하여, 제2 방향(DR2)으로 연장되어 배치된 제2 브릿지부(BR2) 및 제1 지지 패턴부(SP1)에 의해 후속 공정이 진행되는 동안 박리되지 않도록 지지될 수 있다.The second bridge part BR2 has a shape extending in the second direction DR2 , and may be connected to the first support pattern part SP1 and the second pattern part PT2 . The second bridge part BR2 includes one end disposed in the emission area EMA among both ends of the second connection electrode CNE2 in the first direction DR1 and the first connection part CN_B1 of the third connection electrode CNE3 . may be disposed to be spaced apart from each other. Alternatively, the second bridge part BR2 may contact the second connection electrode CNE2 and the first connection part CN_B1 . The first pattern portion PT1 includes a second bridge portion BR2 and a first portion extending in the second direction DR2 in addition to the first base portion BP1 located on the other side of the first direction DR1 . It may be supported so as not to be peeled off during a subsequent process by the support pattern part SP1 .
제1 지지 패턴부(SP1) 및 복수의 브릿지부(BR1, BR2)들은 베이스부(BP1, BP2)들과 달리 발광 영역(EMA) 내에 배치된다. 각 패턴부(PT1, PT2)들의 박리를 방지하기 위해서, 제1 지지 패턴부(SP1) 및 복수의 브릿지부(BR1, BR2)들은 발광 영역(EMA) 내의 좁은 공간 내에서도 각 패턴부(PT1, PT2)들보다 넓은 폭을 가질 수 있다. 도 11에 도시된 바와 같이, 일 실시예에 따르면 제1 지지 패턴부(SP1)의 제2 방향(DR2)으로 측정된 폭(W3), 및 브릿지부(BR1, BR2)들의 제1 방향(DR1)으로 측정된 폭(W2)은 각각 패턴부(PT1, PT2)들의 폭(W1)보다 클 수 있다. 각 패턴부(PT1, PT2)들의 제1 폭(W1)은 발광 소자(ED)의 길이보다 작을 수 있다. 반면, 브릿지부(BR1, BR2)들의 제2 폭(W2)은 패턴부(PT1, PT2)들의 제1 폭(W1), 및 발광 소자(ED)들의 길이보다 더 클 수 있다. 또한, 브릿지부(BR1, BR2)들은 제2 방향(DR2)으로 연장된 길이가 패턴부(PT1, PT2)들의 제1 방향(DR1) 길이보다 짧으므로, 브릿지부(BR1, BR2)의 제1 방향(DR1) 폭과 제2 방향(DR2) 길이의 차이가 패턴부(PT1, PT2)들보다 작을 수 있다. 이에 따라, 브릿지부(BR1, BR2)들은 패턴부(PT1, PT2)들보다 후속 공정에서 박리되지 않고 견딜 수 있고, 패턴부(PT1, PT2)들도 고정시킬 수 있다.Unlike the base parts BP1 and BP2 , the first support pattern part SP1 and the plurality of bridge parts BR1 and BR2 are disposed in the light emitting area EMA. In order to prevent separation of each of the pattern parts PT1 and PT2 , the first support pattern part SP1 and the plurality of bridge parts BR1 and BR2 are formed in the respective pattern parts PT1 and PT2 even in a narrow space within the emission area EMA. ) can be wider than 11 , according to an exemplary embodiment, the width W3 measured in the second direction DR2 of the first support pattern part SP1 and the first direction DR1 of the bridge parts BR1 and BR2 . ) may be greater than the width W1 of the pattern portions PT1 and PT2, respectively. The first width W1 of each of the pattern portions PT1 and PT2 may be smaller than the length of the light emitting device ED. On the other hand, the second width W2 of the bridge portions BR1 and BR2 may be greater than the first width W1 of the pattern portions PT1 and PT2 and the length of the light emitting devices ED. In addition, since the length of the bridge parts BR1 and BR2 extending in the second direction DR2 is shorter than the length of the pattern parts PT1 and PT2 in the first direction DR1 , the first of the bridge parts BR1 and BR2 . A difference between a width in the direction DR1 and a length in the second direction DR2 may be smaller than that of the pattern portions PT1 and PT2 . Accordingly, the bridge parts BR1 and BR2 may withstand a subsequent process without being peeled off from the pattern parts PT1 and PT2 , and the pattern parts PT1 and PT2 may also be fixed.
제1 지지 패턴부(SP1)는 패턴부(PT1, PT2)들과 유사하게 제1 방향(DR1)으로 연장되므로, 패턴부(PT1, PT2)들의 박리를 방지하기 위해 더 큰 폭(W3)을 가질 수 있다. 일 실시예에 따르면, 제1 지지 패턴부(SP1)의 제3 폭(W3)은 브릿지부(BR1, BR2)들의 제2 폭(W2)보다 클 수 있다. 일 실시예에 따른 표시 장치(10_1)는 더 많은 수의 전극(RME_1)들 및 연결 전극(CNE_1)들을 포함할 수 있다. 그에 대응하여, 제2 절연층(PAS2_1)은 더 많은 패턴부(PT1, PT2)들을 포함하고, 제1 지지 패턴부(SP1) 및 복수의 브릿지부(BR1, BR2)를 포함하여 패턴부(PT1, PT2)들의 박리를 방지할 수 있다.Since the first support pattern part SP1 extends in the first direction DR1 similarly to the pattern parts PT1 and PT2 , it has a larger width W3 to prevent separation of the pattern parts PT1 and PT2 . can have According to an exemplary embodiment, the third width W3 of the first support pattern part SP1 may be greater than the second width W2 of the bridge parts BR1 and BR2 . The display device 10_1 according to an exemplary embodiment may include a larger number of electrodes RME_1 and connection electrodes CNE_1 . Correspondingly, the second insulating layer PAS2_1 includes more pattern parts PT1 and PT2 , and includes the first support pattern part SP1 and the plurality of bridge parts BR1 and BR2 , and includes the pattern part PT1 . , PT2) can be prevented from peeling.
복수의 연결 전극(CNE_1)은 제1 전극(RME1) 상에 배치된 제1 연결 전극(CNE1), 제3 전극(RME3)의 타 측 상에 배치된 제2 연결 전극(CNE2), 및 제3 전극(RME3)의 일 측과 제2 전극(RME2) 상에 걸쳐 배치된 제3 연결 전극(CNE3)을 포함할 수 있다. The plurality of connection electrodes CNE_1 includes a first connection electrode CNE1 disposed on the first electrode RME1 , a second connection electrode CNE2 disposed on the other side of the third electrode RME3 , and a third A third connection electrode CNE3 disposed over one side of the electrode RME3 and the second electrode RME2 may be included.
제1 연결 전극(CNE1)은 제1 전극(RME1) 및 제1 발광 소자(ED1)의 제1 단부와 접촉할 수 있다. 제1 연결 전극(CNE1)은 제1 절연층(PAS1)을 관통하는 제1 컨택부(CT1)를 통해 제1 전극(RME1)과 접촉할 수 있다. 제2 연결 전극(CNE2)은 제3 전극(RME3) 및 제2 발광 소자(ED2)의 제2 단부와 접촉할 수 있다. 제2 연결 전극(CNE2)은 제1 절연층(PAS1)을 관통하는 제3 컨택부(CT3)를 통해 제3 전극(RME3)과 접촉할 수 있다. 제1 연결 전극(CNE1)과 제2 연결 전극(CNE2)은 제1 방향(DR1)으로 연장된 형상을 갖고, 발광 영역(EMA)으로부터 서브 영역(SA)까지 연장되어 배치될 수 있다. The first connection electrode CNE1 may contact the first electrode RME1 and the first end of the first light emitting device ED1 . The first connection electrode CNE1 may contact the first electrode RME1 through the first contact portion CT1 penetrating the first insulating layer PAS1 . The second connection electrode CNE2 may contact the third electrode RME3 and the second end of the second light emitting device ED2 . The second connection electrode CNE2 may contact the third electrode RME3 through the third contact portion CT3 penetrating the first insulating layer PAS1 . The first connection electrode CNE1 and the second connection electrode CNE2 may extend in the first direction DR1 and extend from the emission area EMA to the sub area SA.
제3 연결 전극(CNE3)은 제3 전극(RME3)의 일 측 상에 배치되어 제1 방향(DR1)으로 연장된 제1 연장부(CN_E1), 제2 전극(RME2) 상에 배치되어 제1 방향(DR1)으로 연장된 제2 연장부(CN_E2), 및 제1 연장부(CN_E1)와 제2 연장부(CN_E2)를 연결하는 제1 연결부(CN_B1)를 포함할 수 있다. 제3 연결 전극(CNE3)의 제1 연장부(CN_E1)와 제2 연장부(CN_E2)는 제2 연결 전극(CNE2)을 사이에 두고 서로 제2 방향(DR2)으로 이격될 수 있다. 제1 연장부(CN_E1)는 제1 연결 전극(CNE1)과 이격 대향하고, 제2 연장부(CN_E2)는 제2 연결 전극(CNE2)과 이격 대향할 수 있다. 제1 연장부(CN_E1)는 제1 발광 소자(ED1)의 제2 단부와 접촉하고, 제2 연장부(CN_E2)는 제2 발광 소자(ED2)의 제1 단부와 접촉할 수 있다. The third connection electrode CNE3 is disposed on one side of the third electrode RME3 and is disposed on the first extension CN_E1 and the second electrode RME2 extending in the first direction DR1 to form the first It may include a second extension part CN_E2 extending in the direction DR1 , and a first connection part CN_B1 connecting the first extension part CN_E1 and the second extension part CN_E2 . The first extension CN_E1 and the second extension CN_E2 of the third connection electrode CNE3 may be spaced apart from each other in the second direction DR2 with the second connection electrode CNE2 interposed therebetween. The first extension part CN_E1 may face the first connection electrode CNE1 and spaced apart and face the second extension part CN_E2 to face the second connection electrode CNE2. The first extension CN_E1 may contact the second end of the first light emitting element ED1 , and the second extension CN_E2 may contact the first end of the second light emitting element ED2 .
제1 연결부(CN_B1)는 서브 영역(SA)에서 제2 방향(DR2)으로 연장된 형상을 갖고, 제1 연장부(CN_E1) 및 제2 연장부(CN_E2)를 서로 연결할 수 있다. 제1 연결부(CN_B1)는 제2 절연층(PAS2_1)의 제1 지지 패턴부(SP1)와 제2 베이스부(BP2) 사이에 배치되며, 이들의 측면과 각각 이격될 수 있다. 제2 연결 전극(CNE3)의 제2 연장부(CN_E2)는 서브 영역(SA)까지 연장되어 배치되고, 제1 절연층(PAS1)을 관통하는 제3 컨택부(CT3)를 통해 제3 전극(RME3)과 연결될 수 있다(도 12에 도시). The first connection part CN_B1 may have a shape extending in the second direction DR2 from the sub area SA, and may connect the first extension part CN_E1 and the second extension part CN_E2 to each other. The first connection part CN_B1 is disposed between the first support pattern part SP1 and the second base part BP2 of the second insulating layer PAS2_1 and may be spaced apart from side surfaces thereof. The second extension part CN_E2 of the second connection electrode CNE3 is disposed to extend to the sub-region SA and passes through the third contact part CT3 penetrating the first insulating layer PAS1 to the third electrode ( RME3) (shown in FIG. 12).
제1 발광 소자(ED1)의 제1 단부는 제1 연결 전극(CNE1)을 통해 제1 전극(RME1)과 전기적으로 연결되고, 제2 발광 소자(ED2)의 제2 단부는 제2 연결 전극(CNE2)을 통해 제3 전극(RME3)과 전기적으로 연결될 수 있다. 제1 발광 소자(ED1)의 제2 단부와 제2 발광 소자(ED2)의 제1 단부는 서로 제3 연결 전극(CNE3)을 통해 직렬로 연결될 수 있다. 복수의 발광 소자(ED)들은 각각 병렬 연결 구조에 더하여, 제3 뱅크부(BN3)를 기준으로 배치된 위치가 다른 발광 소자(ED; ED1, ED2)들은 직렬 연결 구조를 가질 수 있다. 도 2의 실시예와 달리, 본 실시예에 따른 표시 장치(10_1)는 각 서브 화소(SPXn)마다 더 많은 수의 발광 소자(ED)들을 포함하며 이들의 직렬 연결을 구성할 수 있어, 단위 면적 당 발광량이 증가할 수 있다. A first end of the first light emitting device ED1 is electrically connected to the first electrode RME1 through a first connection electrode CNE1, and a second end of the second light emitting device ED2 has a second connection electrode ( It may be electrically connected to the third electrode RME3 through CNE2 . The second end of the first light emitting element ED1 and the first end of the second light emitting element ED2 may be connected to each other in series through the third connection electrode CNE3 . In addition to the parallel connection structure of each of the plurality of light emitting devices ED, the light emitting devices EDs ED1 and ED2 having different positions with respect to the third bank unit BN3 may have a series connection structure. Unlike the exemplary embodiment of FIG. 2 , the display device 10_1 according to the present exemplary embodiment includes a larger number of light emitting devices ED for each sub-pixel SPXn and may form a series connection therebetween. The amount of light emitted per sugar may be increased.
도 12는 다른 실시예에 따른 표시 장치의 일 서브 화소를 나타내는 평면도이다. 도 13은 도 12의 일 서브 화소에 배치된 제1 뱅크와 제2 뱅크, 복수의 연결 전극들 및 제2 절연층의 상대적인 배치를 나타내는 평면도이다. 도 14는 도 12의 Q4-Q4'선을 따라 자른 단면도이다. 12 is a plan view illustrating one sub-pixel of a display device according to another exemplary embodiment. 13 is a plan view illustrating a relative arrangement of a first bank and a second bank, a plurality of connection electrodes, and a second insulating layer disposed in one sub-pixel of FIG. 12 . 14 is a cross-sectional view taken along line Q4-Q4' of FIG. 12 .
도 12 내지 도 14를 참조하면, 일 실시예에 따른 표시 장치(10_2)는 각 서브 화소(SPXn)마다 더 많은 수의 전극(RME_2)들을 포함할 수 있다. 또한, 제2 절연층(PAS2_2)도 더 많은 수의 패턴부(PT1, PT2, PT3, PT4)들과 브릿지부(BR1, BR2, BR3, BR4, BR5)들을 더 포함할 수 있다. 표시 장치(10_2)는 각 서브 화소(SPXn)마다 4개의 전극(RME_2; RME1, RME2, RME3, RME4)들이 배치되고, 이들 사이에 배치된 발광 소자(ED; ED1, ED2, ED3, ED4, ED5)들의 직렬 연결 구성을 위한 5개의 연결 전극(CNE_2; CNE1, CNE2, CNE3, CNE4, CNE5)들을 포함할 수 있다. 복수의 발광 소자(ED)들은 양 단부에 연결된 연결 전극(CNE_2)들에 따라 서로 직렬로 연결될 수 있다. 제2 절연층(PAS2_2)은 각 발광 소자(ED)들을 고정시키는 복수의 패턴부(PT1, PT2, PT3, PT4)들을 포함하며 이들의 박리를 방지하는 구조를 가질 수 있다. 이하, 중복된 내용은 생략하고 차이점을 중심으로 설명하기로 한다.12 to 14 , the display device 10_2 according to an exemplary embodiment may include a larger number of electrodes RME_2 for each sub-pixel SPXn. Also, the second insulating layer PAS2_2 may further include a greater number of pattern portions PT1 , PT2 , PT3 , and PT4 and bridge portions BR1 , BR2 , BR3 , BR4 , and BR5 . In the display device 10_2 , four electrodes RME_2 ; RME1 , RME2 , RME3 , and RME4 are disposed for each sub-pixel SPXn, and light emitting devices ED; ED1 , ED2 , ED3, ED4 and ED5 disposed between them are disposed. ) may include five connection electrodes (CNE_2; CNE1, CNE2, CNE3, CNE4, CNE5) for a series connection configuration. The plurality of light emitting devices ED may be connected in series with each other according to the connection electrodes CNE_2 connected to both ends. The second insulating layer PAS2_2 may include a plurality of pattern portions PT1 , PT2 , PT3 , and PT4 for fixing each light emitting device ED, and may have a structure to prevent separation thereof. Hereinafter, overlapping content will be omitted and the differences will be mainly described.
복수의 전극(RME_2)들은 제1 전극(RME1_2)을 기준으로 제2 방향(DR2)을 따라 제3 전극(RME3_2), 제2 전극(RME2_2) 및 제4 전극(RME4_2)이 순차적으로 배치된다. 각 전극(RME_2)들은 제1 방향(DR1)으로 연장되어 발광 영역(EMA) 및 서브 영역(SA)에 걸쳐 배치될 수 있다.In the plurality of electrodes RME_2 , a third electrode RME3_2 , a second electrode RME2_2 , and a fourth electrode RME4_2 are sequentially disposed along the second direction DR2 with respect to the first electrode RME1_2 . Each of the electrodes RME_2 may extend in the first direction DR1 and may be disposed over the emission area EMA and the sub area SA.
제1 전극(RME1)은 제1 뱅크부(BN1) 상에 배치되고, 제3 전극(RME3)은 제3 뱅크부(BN3)의 일 측 상에 배치된다. 제2 전극(RME2)은 제3 뱅크부(BN3)의 타 측 상에 배치되고, 제4 전극(RME4)은 제2 뱅크부(BN2) 상에 배치될 수 있다. 각 전극(RME_2)들은 서로 제2 방향(DR2)으로 이격되면서, 제1 전극(RME1)과 제3 전극(RME3)이 서로 대향하고, 제2 전극(RME2)과 제4 전극(RME4)이 서로 대향할 수 있다. The first electrode RME1 is disposed on the first bank part BN1 , and the third electrode RME3 is disposed on one side of the third bank part BN3 . The second electrode RME2 may be disposed on the other side of the third bank part BN3 , and the fourth electrode RME4 may be disposed on the second bank part BN2 . Each of the electrodes RME_2 is spaced apart from each other in the second direction DR2 , the first electrode RME1 and the third electrode RME3 face each other, and the second electrode RME2 and the fourth electrode RME4 connect to each other. can oppose
제1 전극(RME1)과 제2 전극(RME2)은 각각 제2 뱅크(BNL2)와 중첩하는 부분에서 비아층(VIA)을 관통하는 제1 전극 컨택홀(CTD) 및 제2 전극 컨택홀(CTS)을 통해 제3 도전층과 직접 연결될 수 있다. 반면, 제3 전극(RME3)과 제4 전극(RME4)은 제3 도전층과 직접 연결되지 않을 수 있다. 제3 전극(RME3)과 제4 전극(RME4)은 각각 제3 연결 전극(CNE3) 및 제5 연결 전극(CNE5)과 연결되고, 발광 소자(ED)들을 따라 흐르는 전기 신호가 인가될 수 있다. 후술할 바와 같이, 제3 전극(RME3)과 제4 전극(RME4)은 제3 연결 전극(CNE3) 및 제5 연결 전극(CNE5)과 함께 서로 다른 발광 소자(ED)들의 전기적 연결 경로를 제공할 수 있다. The first electrode RME1 and the second electrode RME2 have a first electrode contact hole CTD and a second electrode contact hole CTS passing through the via layer VIA at portions overlapping the second bank BNL2, respectively. ) may be directly connected to the third conductive layer. On the other hand, the third electrode RME3 and the fourth electrode RME4 may not be directly connected to the third conductive layer. The third electrode RME3 and the fourth electrode RME4 are respectively connected to the third connection electrode CNE3 and the fifth connection electrode CNE5 , and electric signals flowing along the light emitting devices ED may be applied thereto. As will be described later, the third electrode RME3 and the fourth electrode RME4 together with the third connection electrode CNE3 and the fifth connection electrode CNE5 provide electrical connection paths between different light emitting devices ED. can
발광 소자(ED)들 중 제1 뱅크부(BN1)와 제3 뱅크부(BN3) 사이에는 제1 발광 소자(ED1)들 및 제3 발광 소자(ED3)들이 배치되고, 제3 뱅크부(BN3)와 제2 뱅크부(BN2) 사이에는 제2 발광 소자(ED2)들과 제4 발광 소자(ED4)들이 배치될 수 있다. 제1 발광 소자(ED1)들 및 제2 발광 소자(ED2)들은 각 서브 화소(SPXn)의 발광 영역(EMA)에서 해당 서브 화소(SPXn)의 서브 영역(SA)에 인접하여 배치되고, 제3 발광 소자(ED3)들 및 제4 발광 소자(ED4)들은 각 서브 화소(SPXn)의 발광 영역(EMA)에서 다른 서브 화소(SPXn)의 서브 영역(SA)에 인접하여 배치될 수 있다. 즉, 제1 발광 소자(ED1)들 및 제2 발광 소자(ED2)들은 발광 영역(EMA)에서 제1 방향(DR1) 타 측인 하측에 배치되고, 제3 발광 소자(ED3)들 및 제4 발광 소자(ED4)들은 발광 영역(EMA)에서 제1 방향(DR1) 일 측인 상측에 배치될 수 있다. Among the light emitting devices ED, the first light emitting devices ED1 and the third light emitting devices ED3 are disposed between the first bank part BN1 and the third bank part BN3, and the third bank part BN3 ) and the second bank unit BN2 , the second light emitting devices ED2 and the fourth light emitting devices ED4 may be disposed. The first light emitting elements ED1 and the second light emitting elements ED2 are disposed adjacent to the sub area SA of the corresponding sub pixel SPXn in the light emitting area EMA of each sub pixel SPXn, and the third The light emitting devices ED3 and the fourth light emitting devices ED4 may be disposed adjacent to the sub area SA of the other sub pixel SPXn in the light emitting area EMA of each sub pixel SPXn. That is, the first light emitting elements ED1 and the second light emitting elements ED2 are disposed below the other side of the first direction DR1 in the light emitting area EMA, and the third light emitting elements ED3 and the fourth light emitting element ED3 are provided. The devices ED4 may be disposed on one side of the light emitting area EMA in the first direction DR1 .
다만, 각 발광 소자(ED)들은 발광 영역(EMA)에서 배치된 위치에 따라 구분되는 것이 아니며, 후술하는 연결 전극(CNE_2)과의 연결 관계에 따라 구분된 것일 수 있다. 각 발광 소자(ED)들은 연결 전극(CNE_2)들의 배치 구조에 따라 양 단부가 접촉하는 연결 전극(CNE_2)이 서로 다를 수 있고, 접촉하는 연결 전극(CNE_2)의 종류에 따라 서로 다른 발광 소자(ED)들로 구분될 수 있다. However, each of the light emitting devices ED is not classified according to a position disposed in the light emitting area EMA, but may be classified according to a connection relationship with the connection electrode CNE_2 to be described later. Each of the light emitting devices ED may have different connecting electrodes CNE_2 contacting both ends according to the arrangement structure of the connecting electrodes CNE_2 , and different light emitting devices ED according to the type of the contacting connecting electrodes CNE_2 . ) can be distinguished.
제1 발광 소자(ED1) 및 제3 발광 소자(ED3)는 제1 단부가 제1 전극(RME1) 상에 배치되고 제2 단부가 제3 전극(RME3) 상에 배치될 수 있다. 제2 발광 소자(ED2) 및 제4 발광 소자(ED4)는 제1 단부가 제4 전극(RME4) 상에 배치되고 제2 단부가 제2 전극(RME2) 상에 배치될 수 있다. 제1 발광 소자(ED1) 및 제3 발광 소자(ED3)는 제2 발광 소자(ED2) 및 제4 발광 소자(ED4)와 제1 단부가 향하는 방향이 서로 다를 수 있다. The first light emitting device ED1 and the third light emitting device ED3 may have a first end disposed on the first electrode RME1 and a second end disposed on the third electrode RME3 . The second light emitting device ED2 and the fourth light emitting device ED4 may have a first end disposed on the fourth electrode RME4 and a second end disposed on the second electrode RME2 . The first light emitting device ED1 and the third light emitting device ED3 may have a different direction from that of the second light emitting device ED2 and the fourth light emitting device ED4 .
복수의 연결 전극(CNE_2)은 제1 전극(RME1) 상에 배치된 제1 연결 전극(CNE1) 및 제2 전극(RME2) 상에 배치된 제2 연결 전극(CNE2)에 더하여, 복수의 전극(RME_2)들에 걸쳐 배치된 제3 연결 전극(CNE3), 제4 연결 전극(CNE4) 및 제5 연결 전극(CNE5)을 더 포함할 수 있다. In addition to the first connection electrode CNE1 disposed on the first electrode RME1 and the second connection electrode CNE2 disposed on the second electrode RME2, the plurality of connection electrodes CNE_2 includes a plurality of electrodes ( A third connection electrode CNE3 , a fourth connection electrode CNE4 , and a fifth connection electrode CNE5 disposed across the RME_2s may be further included.
도 2 및 도 9의 실시예와 달리, 제1 연결 전극(CNE1)과 제2 연결 전극(CNE2)은 각각 제1 방향(DR1)으로 연장된 길이가 비교적 짧을 수 있다. 제1 연결 전극(CNE1)과 제2 연결 전극(CNE2)은 발광 영역(EMA)의 중심을 기준으로 하측에 배치될 수 있다. 제1 연결 전극(CNE1)과 제2 연결 전극(CNE2)은 발광 영역(EMA)과 해당 서브 화소(SPXn)의 서브 영역(SA)에 걸쳐 배치되고, 각각 서브 영역(SA)에 형성된 제1 컨택부(CT1) 및 제2 컨택부(CT2)를 통해 제1 전극(RME1) 및 제2 전극(RME2)과 접촉할 수 있다.2 and 9 , each of the first connection electrode CNE1 and the second connection electrode CNE2 may have a relatively short length extending in the first direction DR1 . The first connection electrode CNE1 and the second connection electrode CNE2 may be disposed below the center of the emission area EMA. The first connection electrode CNE1 and the second connection electrode CNE2 are disposed over the light emitting area EMA and the sub area SA of the corresponding sub pixel SPXn, and are first contacts formed in the sub area SA, respectively. The first electrode RME1 and the second electrode RME2 may be in contact with the portion CT1 and the second contact portion CT2 .
제3 연결 전극(CNE3)은 제3 전극(RME3) 상에 배치된 제1 연장부(CN_E1), 제1 전극(RME1) 상에 배치된 제2 연장부(CN_E2), 및 제1 연장부(CN_E1)와 제2 연장부(CN_E2)를 연결하는 제1 연결부(CN_B1)를 포함할 수 있다. 제1 연장부(CN_E1)는 제1 연결 전극(CNE1)과 제2 방향(DR2)으로 이격 대향하고, 제2 연장부(CN_E2)는 제1 연결 전극(CNE1)과 제1 방향(DR1)으로 이격될 수 있다. 제1 연장부(CN_E1)는 해당 서브 화소(SPXn)의 발광 영역(EMA) 중 하측에 배치되며, 제2 연장부(CN_E2)는 발광 영역(EMA)의 상측에 배치될 수 있다. 제1 연장부(CN_E1)는 발광 영역(EMA) 및 서브 영역(SA)에 걸쳐 배치되어 서브 영역(SA)에 형성된 제3 컨택부(CT3)를 통해 제3 전극(RME3)과 연결될 수 있다. 제1 연결부(CN_B1)는 발광 영역(EMA)의 중심부에서 제1 전극(RME1) 및 제3 전극(RME3)에 걸쳐 배치될 수 있다. 제3 연결 전극(CNE3)은 대체로 제1 방향(DR1)으로 연장된 형상을 갖되, 제2 방향(DR2)으로 절곡되었다가 다시 제1 방향(DR1)으로 연장된 형상을 가질 수 있다. The third connection electrode CNE3 includes a first extension portion CN_E1 disposed on the third electrode RME3 , a second extension portion CN_E2 disposed on the first electrode RME1 , and a first extension portion ( A first connection part CN_B1 connecting the CN_E1 and the second extension part CN_E2 may be included. The first extension part CN_E1 is spaced apart from the first connection electrode CNE1 in the second direction DR2 , and the second extension part CN_E2 faces the first connection electrode CNE1 in the first direction DR1 . can be spaced apart. The first extension part CN_E1 may be disposed below the emission area EMA of the corresponding sub-pixel SPXn, and the second extension part CN_E2 may be disposed above the emission area EMA. The first extension part CN_E1 may be disposed over the emission area EMA and the sub area SA and may be connected to the third electrode RME3 through the third contact part CT3 formed in the sub area SA. The first connection part CN_B1 may be disposed across the first electrode RME1 and the third electrode RME3 from the center of the emission area EMA. The third connection electrode CNE3 may generally have a shape extending in the first direction DR1 , and may have a shape that is bent in the second direction DR2 and then extends again in the first direction DR1 .
제4 연결 전극(CNE4)은 제3 전극(RME3) 상에 배치된 제3 연장부(CN_E3), 제4 전극(RME4) 상에 배치된 제4 연장부(CN_E4), 및 제3 연장부(CN_E3)와 제4 연장부(CN_E4)를 연결하는 제2 연결부(CN_B2)를 포함할 수 있다. 제3 연장부(CN_E3)는 제3 연결 전극(CNE3)의 제2 연장부(CN_E2)와 제2 방향(DR2)으로 이격 대향하고, 제4 연장부(CN_E4)는 후술하는 제5 연결 전극(CNE5)의 제6 연장부(CN_E6)와 제1 방향(DR1)으로 이격될 수 있다. 제3 연장부(CN_E3) 및 제4 연장부(CN_E4)는 각각 발광 영역(EMA)의 상측에 배치되고, 제2 연결부(CN_B2)는 제3 전극(RME3), 제2 전극(RME2) 및 제4 전극(RME4)에 걸쳐 배치될 수 있다. 제4 연결 전극(CNE4)은 평면도 상 제5 연결 전극(CNE5)의 제5 연장부(CN_E5)를 둘러싸는 형상으로 배치될 수 있다. The fourth connection electrode CNE4 includes a third extension portion CN_E3 disposed on the third electrode RME3 , a fourth extension portion CN_E4 disposed on the fourth electrode RME4 , and a third extension portion ( A second connection part CN_B2 connecting the CN_E3 and the fourth extension part CN_E4 may be included. The third extension part CN_E3 is spaced apart from the second extension part CN_E2 of the third connection electrode CNE3 in the second direction DR2 and faces, and the fourth extension part CN_E4 is a fifth connection electrode (to be described later) It may be spaced apart from the sixth extension CN_E6 of the CNE5 in the first direction DR1 . The third extension part CN_E3 and the fourth extension part CN_E4 are respectively disposed above the light emitting area EMA, and the second connection part CN_B2 includes the third electrode RME3, the second electrode RME2, and the second electrode RME2. It may be disposed across the four electrodes RME4. The fourth connection electrode CNE4 may be disposed to surround the fifth extension part CN_E5 of the fifth connection electrode CNE5 in a plan view.
제5 연결 전극(CNE5은 제2 전극(RME2) 상에 배치된 제5 연장부(CN_E5), 제4 전극(RME4) 상에 배치된 제6 연장부(CN_E6), 및 제5 연장부(CN_E5)와 제6 연장부(CN_E6)를 연결하는 제3 연결부(CN_B3)를 포함할 수 있다. 제5 연장부(CN_E5)는 제4 연결 전극(CNE4)의 제4 연장부(CN_E4)와 제2 방향(DR2)으로 이격 대향하며, 제6 연장부(CN_E6)는 제2 연결 전극(CNE2)과 제2 방향(DR2)으로 이격될 수 있다. 제5 연장부(CN_E5)는 해당 서브 화소(SPXn)의 발광 영역(EMA) 중 상측에 배치되며, 제6 연장부(CN_E6)는 발광 영역(EMA)의 하측에 배치될 수 있다. 제6 연장부(CN_E6)는 발광 영역(EMA) 및 서브 영역(SA)에 걸쳐 배치되어 서브 영역(SA)에 형성된 제4 컨택부(CT4)를 통해 제4 전극(RME4)과 연결될 수 있다. 제3 연결부(CN_B3)는 발광 영역(EMA)의 중심에 인접하여 제2 전극(RME2) 및 제4 전극(RME4)에 걸쳐 배치될 수 있다. 제5 연결 전극(CNE5_2)은 대체로 제1 방향(DR1)으로 연장된 형상을 갖되, 제2 방향(DR2)으로 절곡되었다가 다시 제1 방향(DR1)으로 연장된 형상을 가질 수 있다. The fifth connection electrode CNE5 is a fifth extension CN_E5 disposed on the second electrode RME2 , a sixth extension CN_E6 disposed on the fourth electrode RME4 , and a fifth extension CN_E5 . ) and a third connection part CN_B3 connecting the sixth extension part CN_E6. The fifth extension part CN_E5 includes the fourth extension part CN_E4 and the second connection part CN_E4 of the fourth connection electrode CNE4. The sixth extension part CN_E6 may be spaced apart from each other in the direction DR2, and the sixth extension part CN_E6 may be spaced apart from the second connection electrode CNE2 in the second direction DR2. The fifth extension part CN_E5 has a corresponding sub-pixel SPXn ) of the light emitting area EMA, the sixth extension CN_E6 may be disposed below the light emitting area EMA, and the sixth extension CN_E6 includes the light emitting area EMA and the sub area It is disposed over SA and may be connected to the fourth electrode RME4 through a fourth contact portion CT4 formed in the sub area SA. The third connection portion CN_B3 is adjacent to the center of the light emitting area EMA. Thus, it may be disposed across the second electrode RME2 and the fourth electrode RME4. The fifth connection electrode CNE5_2 has a shape that generally extends in the first direction DR1, and extends in the second direction DR2. After being bent, it may have a shape extending in the first direction DR1 again.
제1 연결 전극(CNE1)과 제2 연결 전극(CNE2)은 각각 제3 도전층과 직접 연결된 제1 전극(RME1) 및 제2 전극(RME2)과 접촉하는 제1 타입 연결 전극이고, 제3 연결 전극(CNE3), 및 제5 연결 전극(CNE5)은 제3 도전층과 직접 연결되지 않는 제3 전극(RME3) 및 제4 전극(RME4)과 접촉하는 제2 타입 연결 전극이며, 제4 연결 전극(CNE4)은 전극(RME_2)들과 접촉하지 않는 제3 타입 연결 전극일 수 있다.The first connection electrode CNE1 and the second connection electrode CNE2 are first type connection electrodes in contact with the first electrode RME1 and the second electrode RME2 directly connected to the third conductive layer, respectively, and the third connection electrode The electrode CNE3 and the fifth connection electrode CNE5 are a second type connection electrode in contact with the third electrode RME3 and the fourth electrode RME4 that are not directly connected to the third conductive layer, and the fourth connection electrode CNE4 may be a third type connection electrode that does not contact the electrodes RME_2 .
상술한 바와 같이, 연결 전극(CNE_2)들의 배치 구조에 대응하여 복수의 발광 소자(ED)들은 양 단부가 접촉하는 연결 전극(CNE_2)에 따라 서로 다른 발광 소자(ED)들로 구분될 수 있다. As described above, corresponding to the arrangement structure of the connection electrodes CNE_2 , the plurality of light emitting devices ED may be divided into different light emitting devices ED according to the connection electrode CNE_2 having both ends in contact.
제1 발광 소자(ED1)는 제1 단부가 제1 연결 전극(CNE1)과 접촉하고, 제2 단부는 제3 연결 전극(CNE3)의 제1 연장부(CN_E1)와 접촉할 수 있다. 제2 발광 소자(ED2)는 제1 단부가 제5 연결 전극(CNE5)의 제6 연장부(CN_E6)와 접촉하고, 제2 단부는 제2 연결 전극(CNE2)과 접촉할 수 있다. 제3 발광 소자(ED3)는 제1 단부가 제3 연결 전극(CNE3)의 제2 연장부(CN_E2)와 접촉하고, 제2 단부는 제4 연결 전극(CNE4)의 제3 연장부(CN_E3)와 접촉할 수 있다. 제4 발광 소자(ED4)는 제1 단부가 제4 연결 전극(CNE4)의 제4 연장부(CN_E4)와 접촉하고, 제2 단부는 제5 연결 전극(CNE5)의 제5 연장부(CN_E5)와 접촉할 수 있다.The first light emitting element ED1 may have a first end in contact with the first connection electrode CNE1 , and a second end in contact with the first extension CN_E1 of the third connection electrode CNE3 . The second light emitting device ED2 may have a first end in contact with the sixth extension CN_E6 of the fifth connection electrode CNE5 , and a second end in contact with the second connection electrode CNE2 . The third light emitting element ED3 has a first end in contact with the second extension CN_E2 of the third connection electrode CNE3 and a second end of the third extension CN_E3 of the fourth connection electrode CNE4. can be contacted with The fourth light emitting element ED4 has a first end in contact with the fourth extension CN_E4 of the fourth connection electrode CNE4 and a second end of the fifth extension CN_E5 of the fifth connection electrode CNE5. can be contacted with
제1 발광 소자(ED1)의 제1 단부는 제3 도전층과 직접 연결된 제1 전극(RME1)과 전기적으로 연결되고, 제2 발광 소자(ED2)의 제2 단부도 제3 도전층과 직접 연결된 제2 전극(RME2)과 전기적으로 연결될 수 있다. 제1 발광 소자(ED1)와 제3 발광 소자(ED3)는 제3 연결 전극(CNE3)을 통해 서로 전기적으로 연결되고, 제3 발광 소자(ED3)와 제4 발광 소자(ED4)는 제4 연결 전극(CNE4)을 통해, 제4 발광 소자(ED4)와 제2 발광 소자(ED2)는 제5 연결 전극(CNE5)을 통해 전기적으로 연결될 수 있다. 제1 발광 소자(ED1), 제3 발광 소자(ED3), 제4 발광 소자(ED4) 및 제2 발광 소자(ED2)는 복수의 연결 전극(CNE_2)들을 통해 서로 직렬로 연결될 수 있다. 본 실시예에 따른 표시 장치(10_2)는 각 서브 화소(SPXn)마다 더 많은 수의 발광 소자(ED)들을 포함하며 이들의 직렬 연결을 구성할 수 있어, 단위 면적 당 발광량이 더욱 증가할 수 있다. The first end of the first light emitting element ED1 is electrically connected to the first electrode RME1 directly connected to the third conductive layer, and the second end of the second light emitting element ED2 is also directly connected to the third conductive layer. It may be electrically connected to the second electrode RME2 . The first light emitting element ED1 and the third light emitting element ED3 are electrically connected to each other through a third connection electrode CNE3 , and the third light emitting element ED3 and the fourth light emitting element ED4 are connected to a fourth connection Through the electrode CNE4 , the fourth light emitting element ED4 and the second light emitting element ED2 may be electrically connected through the fifth connection electrode CNE5 . The first light emitting device ED1 , the third light emitting device ED3 , the fourth light emitting device ED4 , and the second light emitting device ED2 may be connected in series to each other through the plurality of connection electrodes CNE_2 . The display device 10_2 according to the present exemplary embodiment may include a larger number of light emitting devices ED for each sub-pixel SPXn and form a series connection therebetween, so that the amount of light per unit area may be further increased. .
각 서브 화소(SPXn)에 배치된 복수의 발광 소자(ED)들이 서로 다른 발광 소자(ED)들로 구분됨에 따라, 제2 절연층(PAS2_2)은 더 많은 수의 패턴부(PT1, PT2, PT3, PT4)들을 포함할 수 있다. 그에 대응하여, 제2 절연층(PAS2_2)은 각 패턴부(PT1, PT2, PT3, PT4)들의 박리를 방지할 수 있는 구조로, 더 많은 수의 브릿지부(BR1, BR2, BR3, BR4, BR5)들을 포함할 수 있다.As the plurality of light emitting devices ED disposed in each sub-pixel SPXn are divided into different light emitting devices ED, the second insulating layer PAS2_2 has a larger number of pattern portions PT1 , PT2 , and PT3 . , PT4) may be included. Correspondingly, the second insulating layer PAS2_2 has a structure capable of preventing separation of each of the pattern portions PT1, PT2, PT3, and PT4, and has a larger number of the bridge portions BR1, BR2, BR3, BR4, BR5. ) may include
도 15를 참조하면, 제1 패턴부(PT1_2) 중 어느 하나는 제2 서브 뱅크(SBL2) 상에 배치된 패턴부와 연결되며, 이들은 연결 전극들에 의해 둘러싸일 수 있다. 도 17은 도 12의 A5부분의 확대도이다. 도 15 내지 도 17에서는 제2 절연층(PAS2_2)의 서로 다른 패턴부(PT1, PT2, PT3, PT4)들이 베이스부(BP1, BP2) 또는 브릿지부와 연결된 부분을 도시하고 있다. Referring to FIG. 15 , any one of the first pattern parts PT1_2 is connected to the pattern part disposed on the second sub-bank SBL2 , and they may be surrounded by connection electrodes. 17 is an enlarged view of a portion A5 of FIG. 12 . 15 to 17 illustrate portions in which different pattern portions PT1 , PT2 , PT3 , and PT4 of the second insulating layer PAS2_2 are connected to the base portions BP1 and BP2 or the bridge portion.
도 12 내지 도 14에 결부하여 도 15 내지 도 17을 참조하면, 제2 절연층(PAS2_2)은 제1 발광 소자(ED1)들 상에 배치된 제1 패턴부(PT1), 제2 발광 소자(ED2)들 상에 배치된 제2 패턴부(PT2), 제3 발광 소자(ED3)들 상에 배치된 제3 패턴부(PT3), 및 제4 발광 소자(ED4)들 상에 배치된 제4 패턴부(PT4)를 포함할 수 있다. Referring to FIGS. 15 to 17 in conjunction with FIGS. 12 to 14 , the second insulating layer PAS2_2 includes a first pattern part PT1 and a second light emitting device disposed on the first light emitting devices ED1. The second pattern part PT2 disposed on the ED2 , the third pattern part PT3 disposed on the third light emitting devices ED3 , and the fourth pattern part PT3 disposed on the fourth light emitting devices ED4 . A pattern part PT4 may be included.
제1 패턴부(PT1)와 제3 패턴부(PT3)는 각각 제1 뱅크부(BN1) 및 제3 뱅크부(BN3) 사이에 배치되고, 제3 연결 전극(CNE3)의 제1 연결부(CN_B1)를 사이에 두고 서로 제1 방향(DR1)으로 이격되어 위치할 수 있다. 제1 패턴부(PT1)와 제3 패턴부(PT3)는 각각 제1 연결부(CN_B1)와 맞닿아 배치될 수 있다. 제1 패턴부(PT1)의 제1 방향(DR1) 타 측은 제2 뱅크(BNL2)를 넘어 제1 베이스부(BP1)와 연결되고, 제3 패턴부(PT3)의 제1 방향(DR1) 일 측은 제2 뱅크(BNL2) 상에 배치된 제2 베이스부(BP2)와 연결될 수 있다. The first pattern part PT1 and the third pattern part PT3 are disposed between the first bank part BN1 and the third bank part BN3, respectively, and the first connection part CN_B1 of the third connection electrode CNE3 ) may be disposed to be spaced apart from each other in the first direction DR1 . The first pattern part PT1 and the third pattern part PT3 may be disposed in contact with the first connection part CN_B1, respectively. The other side of the first pattern part PT1 in the first direction DR1 crosses the second bank BNL2 and is connected to the first base part BP1 , and is connected to the third pattern part PT3 in the first direction DR1 . The side may be connected to the second base part BP2 disposed on the second bank BNL2 .
제2 패턴부(PT2)와 제4 패턴부(PT4)는 각각 제3 뱅크부(BN3) 및 제2 뱅크부(BN2) 사이에 배치되고, 제5 연결 전극(CNE5)의 제3 연결부(CN_B3)를 사이에 두고 서로 제1 방향(DR1)으로 이격되어 위치할 수 있다. 제2 패턴부(PT2)와 제4 패턴부(PT4)는 각각 제3 연결부(CN_B3)와 맞닿아 배치될 수 있다. 제2 패턴부(PT2)의 제1 방향(DR1) 타 측은 제2 뱅크(BNL2)를 넘어 제1 베이스부(BP1)와 연결되고, 제4 패턴부(PT4)의 제1 방향(DR1) 일 측은 제2 뱅크(BNL2) 상에 배치된 제2 베이스부(BP2)와 연결될 수 있다.The second pattern part PT2 and the fourth pattern part PT4 are respectively disposed between the third bank part BN3 and the second bank part BN2 , and the third connection part CN_B3 of the fifth connection electrode CNE5 . ) may be disposed to be spaced apart from each other in the first direction DR1 . The second pattern part PT2 and the fourth pattern part PT4 may be disposed in contact with the third connection part CN_B3, respectively. The other side of the second pattern part PT2 in the first direction DR1 crosses the second bank BNL2 and is connected to the first base part BP1 , and one side of the fourth pattern part PT4 in the first direction DR1 crosses the second bank BNL2 . The side may be connected to the second base part BP2 disposed on the second bank BNL2 .
제1 지지 패턴부(SP1)는 도 9의 실시예와 유사하게 제3 뱅크부(BN3) 상에 배치된다. 제1 지지 패턴부(SP1)는 제2 전극(RME2) 및 제3 전극(RME3)과 각각 부분적으로 중첩할 수 있다. 제1 지지 패턴부(SP1)는 제1 방향(DR1)으로 연장되어 서브 영역(SA)에 배치된 제1 베이스부(BP1)의 연결 패턴부(CNP)와 연결될 수 있다.The first support pattern part SP1 is disposed on the third bank part BN3 similarly to the embodiment of FIG. 9 . The first support pattern part SP1 may partially overlap the second electrode RME2 and the third electrode RME3, respectively. The first support pattern part SP1 may extend in the first direction DR1 to be connected to the connection pattern part CNP of the first base part BP1 disposed in the sub area SA.
제2 절연층(PAS2_2)은 각 패턴부(PT1, PT2, PT3, PT4)들을 제2 베이스부(BP2) 또는 제1 지지 패턴부(SP1)와 연결하는 복수의 브릿지부들을 포함할 수 있다. The second insulating layer PAS2_2 may include a plurality of bridge parts connecting each of the pattern parts PT1 , PT2 , PT3 , and PT4 to the second base part BP2 or the first support pattern part SP1 .
제1 브릿지부(BR1)는 제1 패턴부(PT1) 및 제2 베이스부(BP2) 중 제1 방향(DR1)으로 연장된 부분과 연결될 수 있다. 제1 브릿지부(BR1)는 제1 연결 전극(CNE1)과 제3 연결 전극(CNE3)의 제2 연장부(CN_E2) 사이에 배치되어 제2 방향(DR2)으로 연장된 형상을 가질 수 있다. 제1 브릿지부(BR1)는 제1 연결 전극(CNE1) 및 제3 연결 전극(CNE3)과 이격되어 배치될 수 있다. 제2 브릿지부(BR2)는 제2 패턴부(PT2) 및 제1 지지 패턴부(SP1)와 연결될 수 있다. 제2 브릿지부(BR2)는 제2 연결 전극(CNE2)과 제5 연결 전극(CNE5)의 제5 연장부(CN_E5) 사이에 배치되어 제2 방향(DR2)으로 연장된 형상을 가질 수 있다. 제2 브릿지부(BR2)는 제2 연결 전극(CNE2) 및 제5 연결 전극(CNE5)과 이격되어 배치될 수 있다.The first bridge part BR1 may be connected to a portion extending in the first direction DR1 among the first pattern part PT1 and the second base part BP2 . The first bridge part BR1 may be disposed between the first connection electrode CNE1 and the second extension part CN_E2 of the third connection electrode CNE3 to extend in the second direction DR2 . The first bridge part BR1 may be disposed to be spaced apart from the first connection electrode CNE1 and the third connection electrode CNE3 . The second bridge part BR2 may be connected to the second pattern part PT2 and the first support pattern part SP1 . The second bridge part BR2 may be disposed between the second connection electrode CNE2 and the fifth extension part CN_E5 of the fifth connection electrode CNE5 to extend in the second direction DR2 . The second bridge part BR2 may be disposed to be spaced apart from the second connection electrode CNE2 and the fifth connection electrode CNE5 .
제3 브릿지부(BR3)는 제3 패턴부(PT3) 및 제1 지지 패턴부(SP1)와 연결될 수 있다. 제3 브릿지부(BR3)는 제3 연결 전극(CNE3)의 제1 연장부(CN_E1)와 제4 연결 전극(CNE4)의 제3 연장부(CN_E3) 사이에 배치되어 제2 방향(DR2)으로 연장된 형상을 가질 수 있다. 제3 브릿지부(BR3)는 제3 연결 전극(CNE3) 및 제4 연결 전극(CNE4)과 이격되어 배치될 수 있다. 제4 브릿지부(BR4)는 제4 패턴부(PT4) 및 제1 지지 패턴부(SP1)와 연결될 수 있다. 제4 브릿지부(BR4)는 제4 연결 전극(CNE4)의 제2 연결부(CN_B2)와 제5 연결 전극(CNE5)의 제5 연장부(CN_E5) 사이에 배치되어 제2 방향(DR2)으로 연장된 형상을 가질 수 있다. 제4 브릿지부(BR4)는 제4 연결 전극(CNE4) 및 제5 연결 전극(CNE5)과 이격되어 배치될 수 있다.The third bridge part BR3 may be connected to the third pattern part PT3 and the first support pattern part SP1 . The third bridge part BR3 is disposed between the first extension part CN_E1 of the third connection electrode CNE3 and the third extension part CN_E3 of the fourth connection electrode CNE4 in the second direction DR2 . It may have an elongated shape. The third bridge part BR3 may be disposed to be spaced apart from the third connection electrode CNE3 and the fourth connection electrode CNE4 . The fourth bridge part BR4 may be connected to the fourth pattern part PT4 and the first support pattern part SP1 . The fourth bridge part BR4 is disposed between the second connection part CN_B2 of the fourth connection electrode CNE4 and the fifth extension part CN_E5 of the fifth connection electrode CNE5 and extends in the second direction DR2 . may have a given shape. The fourth bridge part BR4 may be disposed to be spaced apart from the fourth connection electrode CNE4 and the fifth connection electrode CNE5 .
제5 브릿지부(BR5)는 제4 패턴부(PT4) 및 제2 베이스부(BP2) 중 제1 방향(DR1)으로 연장된 부분과 연결될 수 있다. 제5 브릿지부(BR5)는 제4 연결 전극(CNE4)의 제4 연장부(CN_E4)와 제5 연결 전극(CNE5)의 제6 연장부(CN_E6) 사이에 배치되어 제2 방향(DR2)으로 연장된 형상을 가질 수 있다. 제5 브릿지부(BR5)는 제4 연결 전극(CNE4) 및 제5 연결 전극(CNE5)과 이격되어 배치될 수 있다.The fifth bridge part BR5 may be connected to a portion extending in the first direction DR1 among the fourth pattern part PT4 and the second base part BP2 . The fifth bridge part BR5 is disposed between the fourth extension part CN_E4 of the fourth connection electrode CNE4 and the sixth extension part CN_E6 of the fifth connection electrode CNE5 in the second direction DR2 . It may have an elongated shape. The fifth bridge part BR5 may be disposed to be spaced apart from the fourth connection electrode CNE4 and the fifth connection electrode CNE5 .
상술한 바와 같이, 제2 절연층(PAS2_2)은 연결 전극(CNE_2)들과 두께 방향으로 비중첩하도록 배치된다. 제2 절연층(PAS2_2)의 패턴부(PT1, PT2, PT3, PT4)들 및 브릿지부(BR1, BR2, BR3, BR4, BR5)들은 서로 연결되어 박리되지 않는 구조를 가질 수 있다. 또한, 상술한 바와 같이 복수의 브릿지부(BR1, BR2, BR3, BR4, BR5)들은 연결 전극(CNE_2)들의 제조 공정 조건에 따라, 인접한 연결 전극(CNE_2)들의 측면과 접촉하도록 배치될 수도 있다.As described above, the second insulating layer PAS2_2 is disposed to not overlap the connection electrodes CNE_2 in the thickness direction. The pattern portions PT1 , PT2 , PT3 , and PT4 of the second insulating layer PAS2_2 and the bridge portions BR1 , BR2 , BR3 , BR4 , and BR5 may be connected to each other so as not to be separated. Also, as described above, the plurality of bridge parts BR1 , BR2 , BR3 , BR4 , and BR5 may be disposed to contact side surfaces of the adjacent connection electrodes CNE_2 according to manufacturing process conditions of the connection electrodes CNE_2 .
본 실시예에 따른 제2 절연층(PAS2_2)은 각 서브 화소(SPXn)마다 더 많은 수의 전극(RME_2)들이 배치됨에 따라 더 많은 패턴부들을 포함하고, 이들이 박리되지 않는 구조를 갖기 위해 더 많은 수의 브릿지부들을 포함할 수 있다. The second insulating layer PAS2_2 according to the present exemplary embodiment includes more pattern portions as a larger number of electrodes RME_2 are disposed in each sub-pixel SPXn, and more pattern portions are added to have a structure in which they are not peeled off. It may include a number of bridge parts.
한편, 복수의 패턴부들의 박리를 방지하는 구조로서, 복수의 브릿지부들은 제2 방향(DR2)으로 연장된 형상을 갖고 제2 베이스부(BP2)의 제1 방향(DR1)으로 연장된 부분과 연결될 수 있다. 몇몇 실시예에서, 발광 영역(EMA) 내에 제2 베이스부(BP2)의 제1 방향(DR1)으로 연장된 부분과 유사한 패턴이 배치될 수 있다면, 제2 절연층(PAS2)은 제2 베이스부(BP2)가 생략될 수도 있다. 이 경우, 발광 영역(EMA)에 배치된 상기 패턴이 브릿지부를 통해 각 패턴부들과 연결되고, 패턴부들의 박리를 방지할 수 있다.Meanwhile, as a structure to prevent separation of the plurality of pattern portions, the plurality of bridge portions have a shape extending in the second direction DR2 , and include portions extending in the first direction DR1 of the second base portion BP2 and can be connected In some embodiments, if a pattern similar to a portion extending in the first direction DR1 of the second base portion BP2 may be disposed in the light emitting area EMA, the second insulating layer PAS2 may be formed on the second base portion (BP2) may be omitted. In this case, the pattern disposed in the light emitting area EMA is connected to each of the pattern parts through the bridge part, and separation of the pattern parts can be prevented.
도 18은 다른 실시예에 따른 표시 장치의 일 서브 화소를 나타내는 평면도이다. 도 19는 도 18의 Q5-Q5'선을 따라 자른 단면도이다. 18 is a plan view illustrating one sub-pixel of a display device according to another exemplary embodiment. 19 is a cross-sectional view taken along line Q5-Q5' of FIG. 18 .
도 18 및 도 19을 참조하면, 일 실시예에 따른 표시 장치(10_3)는 제2 절연층(PAS2_3)이 제2 베이스부(BP2)가 생략되고, 더 많은 수의 지지 패턴부(SP1, SP2, SP3)들을 포함할 수 있다. 각 패턴부(PT1, PT2, PT3, PT4)들을 제2 베이스부(BP2)와 연결하는 복수의 브릿지부들은 각각 복수의 지지 패턴부(SP1, SP2, SP3)들 중 어느 하나와 연결될 수 있다. 본 실시예는 제2 절연층(PAS2_3)의 제2 베이스부(BP2)가 복수의 지지 패턴부(SP1, SP2, SP3)들로 대체된 점에서 도 12의 실시예와 차이가 있다. 이하, 중복된 내용은 생략하고 차이점을 중심으로 설명하기로 한다.18 and 19 , in the display device 10_3 according to an exemplary embodiment, the second insulating layer PAS2_3 has the second base part BP2 omitted, and a larger number of the support pattern parts SP1 and SP2 is provided. , SP3) may be included. A plurality of bridge parts connecting each of the pattern parts PT1 , PT2 , PT3 , and PT4 to the second base part BP2 may be respectively connected to any one of the plurality of support pattern parts SP1 , SP2 , and SP3 . This embodiment is different from the embodiment of FIG. 12 in that the second base part BP2 of the second insulating layer PAS2_3 is replaced with a plurality of support pattern parts SP1 , SP2 , and SP3 . Hereinafter, overlapping content will be omitted and the differences will be mainly described.
일 실시예에 따르면, 제2 절연층(PAS2_3)은 제1 지지 패턴부(SP1)에 더하여 이와 제2 방향(DR2)으로 이격되어 발광 영역(EMA) 내에 배치된 제2 지지 패턴부(SP2) 및 제3 지지 패턴부(SP3)를 더 포함할 수 있다. 제1 지지 패턴부(SP1)가 제3 뱅크부(BN3) 상에 배치된 반면, 제2 지지 패턴부(SP2)는 제1 뱅크부(BN1) 중 일부분 상에 배치되고, 제3 지지 패턴부(SP3)는 제2 뱅크부(BN2) 중 일부분 상에 배치될 수 있다. 제2 지지 패턴부(SP2)와 제3 지지 패턴부(SP3)는 각각 제1 지지 패턴부(SP1)와 동일한 제3 폭(W3)을 갖고 제1 방향(DR1)으로 연장되며, 제1 지지 패턴부(SP1)를 사이에 두고 서로 제2 방향(DR2)으로 이격될 수 있다.According to an embodiment, the second insulating layer PAS2_3 is spaced apart from the first support pattern part SP1 in the second direction DR2 in addition to the second support pattern part SP2 disposed in the emission area EMA. and a third support pattern part SP3. While the first support pattern part SP1 is disposed on the third bank part BN3 , the second support pattern part SP2 is disposed on a part of the first bank part BN1 , and the third support pattern part SP3 may be disposed on a portion of the second bank unit BN2 . Each of the second support pattern part SP2 and the third support pattern part SP3 has a third width W3 equal to that of the first support pattern part SP1 and extends in the first direction DR1 , and includes the first support pattern part SP1 . They may be spaced apart from each other in the second direction DR2 with the pattern part SP1 interposed therebetween.
제2 지지 패턴부(SP2)는 제1 뱅크부(BN1) 및 제1 전극(RME1)과 부분적으로 중첩할 수 있다. 제2 지지 패턴부(SP2)는 제1 연결 전극(CNE1) 및 제3 연결 전극(CNE3)의 제2 연장부(CN_E2)와 이격되거나 맞닿아 배치될 수 있고, 브릿지부들을 통해 제1 패턴부(PT1) 및 제3 패턴부(PT3)와 연결될 수 있다. 예를 들어, 제1 패턴부(PT1)는 제1 브릿지부(BR1)를 통해, 제3 패턴부(PT3)는 제6 브릿지부(BR6)를 통해 각각 제2 지지 패턴부(SP2)와 연결될 수 있다. 제1 패턴부(PT1)는 제2 뱅크(BNL2)를 넘어 제1 베이스부(BP1)와 연결되며, 이와 동시에 제1 브릿지부(BR1) 및 제2 지지 패턴부(SP2)와 연결될 수 있다. 반면, 제2 베이스부(BP2)가 생략됨에 따라, 제3 패턴부(PT3)는 제3 브릿지부(BR3)와 제6 브릿지부(BR6)를 통해 각각 제1 지지 패턴부(SP1) 및 제2 지지 패턴부(SP2)와 연결될 수 있다. The second support pattern part SP2 may partially overlap the first bank part BN1 and the first electrode RME1 . The second support pattern part SP2 may be disposed to be spaced apart from or in contact with the second extension part CN_E2 of the first connection electrode CNE1 and the third connection electrode CNE3 , and may be disposed in contact with the first pattern part through the bridge parts. It may be connected to the PT1 and the third pattern part PT3 . For example, the first pattern part PT1 may be connected to the second support pattern part SP2 via the first bridge part BR1 , and the third pattern part PT3 may be connected to the second support pattern part SP2 via the sixth bridge part BR6 , respectively. can The first pattern part PT1 may be connected to the first base part BP1 beyond the second bank BNL2 , and at the same time may be connected to the first bridge part BR1 and the second support pattern part SP2 . On the other hand, as the second base part BP2 is omitted, the third pattern part PT3 is formed with the first support pattern part SP1 and the second support pattern part SP1 through the third bridge part BR3 and the sixth bridge part BR6, respectively. 2 may be connected to the support pattern part SP2.
제3 지지 패턴부(SP3)는 제2 뱅크부(BN2) 및 제4 전극(RME4)과 부분적으로 중첩할 수 있다. 제3 지지 패턴부(SP3)는 제4 연결 전극(CNE4)의 제4 연장부(CN_E4) 및 제5 연결 전극(CNE5)의 제6 연장부(CN_E6)와 이격되거나 맞닿아 배치될 수 있고, 제5 브릿지부(BR5)를 통해 제4 패턴부(PT4)와 연결될 수 있다. The third support pattern part SP3 may partially overlap the second bank part BN2 and the fourth electrode RME4 . The third support pattern part SP3 may be disposed to be spaced apart from or in contact with the fourth extension part CN_E4 of the fourth connection electrode CNE4 and the sixth extension part CN_E6 of the fifth connection electrode CNE5, It may be connected to the fourth pattern part PT4 through the fifth bridge part BR5 .
본 실시예에 따른 표시 장치(10_3)는 제2 절연층(PAS2_3)이 제2 뱅크(BNL2) 상에 배치된 제2 베이스부(BP2)가 생략됨에 따라, 서브 화소(SPXn) 내측 영역과 서브 화소(SPXn)들 사이의 경계 영역 간 단차가 줄어드는 이점이 있다. In the display device 10_3 according to the present exemplary embodiment, as the second base portion BP2 in which the second insulating layer PAS2_3 is disposed on the second bank BNL2 is omitted, the inner region of the sub-pixel SPXn and the sub-pixel SPXn are omitted. There is an advantage in that the step difference between the boundary regions between the pixels SPXn is reduced.
도 20은 다른 실시예에 따른 표시 장치의 일 서브 화소를 나타내는 평면도이다. 도 21은 도 20의 Q6-Q6'선을 따라 자른 단면도이다. 도 22는 도 20의 Q7-Q7'선을 따라 자른 단면도이다. 도 21은 일 서브 화소(SPXn)의 발광 영역(EMA)을 가로지르는 단면을 도시하고, 도 22는 서브 영역(SA)의 분리부(ROP)를 가로지르는 단면을 도시하고 있다.20 is a plan view illustrating one sub-pixel of a display device according to another exemplary embodiment. 21 is a cross-sectional view taken along line Q6-Q6' of FIG. 20; 22 is a cross-sectional view taken along line Q7-Q7' of FIG. 20 . 21 illustrates a cross-section crossing the emission area EMA of one sub-pixel SPXn, and FIG. 22 illustrates a cross-section crossing the separation portion ROP of the sub-area SA.
도 20 내지 도 22를 참조하면, 일 실시예에 따른 표시 장치(10_4)는 제2 절연층(PAS2_4)의 패턴부(PT1, PT2, PT3, PT4)들과 발광 소자(ED) 사이에 배치된 제3 절연층(PAS3_4)을 더 포함할 수 있다. 제3 절연층(PAS3_4)은 제2 절연층(PAS2_4) 보다 먼저 형성되어 발광 소자(ED)들을 고정하는 기능을 수행할 수 있고, 제2 절연층(PAS2_4)은 복수의 전극(RME)들을 분리부(ROP)에서 분리하는 공정 이후에 형성될 수 있다. 그에 따라, 제2 절연층(PAS2_4)의 제1 베이스부(BP1)는 분리부(ROP)를 포함한 서브 영역(SA) 전면에 배치될 수 있다.20 to 22 , the display device 10_4 according to an exemplary embodiment is disposed between the pattern portions PT1 , PT2 , PT3 , and PT4 of the second insulating layer PAS2_4 and the light emitting device ED. A third insulating layer PAS3_4 may be further included. The third insulating layer PAS3_4 may be formed before the second insulating layer PAS2_4 to fix the light emitting devices ED, and the second insulating layer PAS2_4 may separate the plurality of electrodes RME. It may be formed after the process of separating from the part ROP. Accordingly, the first base part BP1 of the second insulating layer PAS2_4 may be disposed on the entire surface of the sub-region SA including the separation part ROP.
제3 절연층(PAS3_4)은 제2 절연층(PAS2_4)의 패턴부(PT1, PT2, PT3, PT4)들 하부에 배치되어 실질적으로 동일한 형상을 가질 수 있다. 도면에 도시되지 않았으나, 제3 절연층(PAS3_4)은 각 뱅크부(BN1, BN2, BN3)들 사이에서 제1 방향(DR1)으로 연장된 형상을 가질 수 있고, 복수의 발광 소자(ED)들을 덮을 수 있다. 제3 절연층(PAS3_4)의 양 측면은 각각 제2 절연층(PAS2_4)의 패턴부(PT1, PT2, PT3, PT4)의 양 측면과 나란할 수 있다. 제3 절연층(PAS3_4)은 절연 물질이 복수의 발광 소자(ED)들을 덮도록 형성되었다가 제2 절연층(PAS2_4)과 동일한 공정에서 패터닝되어 형성될 수 있다. 그에 따라, 제3 절연층(PAS3_4)의 평면 및 단면도 상 패턴 형상은 실질적으로 제2 절연층(PAS2_4)과 동일할 수 있다.The third insulating layer PAS3_4 may be disposed under the pattern portions PT1 , PT2 , PT3 , and PT4 of the second insulating layer PAS2_4 to have substantially the same shape. Although not shown in the drawing, the third insulating layer PAS3_4 may have a shape extending in the first direction DR1 between the respective bank parts BN1 , BN2 and BN3 , and may include a plurality of light emitting devices ED. can be covered Both side surfaces of the third insulating layer PAS3_4 may be parallel to both side surfaces of the pattern portions PT1 , PT2 , PT3 , and PT4 of the second insulating layer PAS2_4 , respectively. The third insulating layer PAS3_4 may be formed by forming an insulating material to cover the plurality of light emitting devices ED and then patterning it in the same process as the second insulating layer PAS2_4 . Accordingly, the pattern shape of the third insulating layer PAS3_4 on a plane and cross-sectional view may be substantially the same as that of the second insulating layer PAS2_4 .
일 실시예에서, 제3 절연층(PAS3_4)은 제2 절연층(PAS2_4)과 달리 무기 절연 물질을 포함할 수 있다. 제3 절연층(PAS3_4)은 제2 절연층(PAS2_4)보다 제1 절연층(PAS1)에 가까운 재료로 이루어질 수 있고, 발광 소자(ED)들을 감싸며 이들을 고정하고 보호할 수 있다. In an embodiment, the third insulating layer PAS3_4 may include an inorganic insulating material unlike the second insulating layer PAS2_4 . The third insulating layer PAS3_4 may be made of a material closer to the first insulating layer PAS1 than the second insulating layer PAS2_4 , and may surround the light emitting devices ED to fix and protect them.
반면, 서브 영역(SA)에서는 제1 방향(DR1)으로 이웃한 다른 서브 화소(SPXn)의 전극(RME)들이 분리부(ROP)에서 서로 이격될 수 있다. 제1 방향(DR1)으로 이격된 전극들은 하나의 전극 라인으로 형성되었다가 발광 소자(ED)들의 정렬 공정 이후에 서로 분리되어 형성될 수 있다. 상기 전극 라인을 분리하는 공정은 제3 절연층(PAS3_4)을 형성한 뒤에 수행되고, 제2 절연층(PAS2_4)은 분리 공정 이후에 형성될 수 있다. 그에 따라, 서브 영역(SA)의 분리부(ROP)에서는 제1 절연층(PAS1)과 제3 절연층(PAS3_4)이 배치되지 않고, 전극(RME)들이 이격되어 노출된 비아층(VIA)은 제2 절연층(PAS2_4)의 제1 베이스부(BP1)가 덮을 수 있다. 제3 절연층(PAS3_4)은 전극 라인들을 분리하는 공정에서 마스크 패턴으로 활용될 수 있다. On the other hand, in the sub-region SA, the electrodes RME of the other sub-pixels SPXn adjacent in the first direction DR1 may be spaced apart from each other in the separation portion ROP. The electrodes spaced apart from each other in the first direction DR1 may be formed as one electrode line and separated from each other after the alignment process of the light emitting devices ED. The process of separating the electrode lines may be performed after the third insulating layer PAS3_4 is formed, and the second insulating layer PAS2_4 may be formed after the separating process. Accordingly, the first insulating layer PAS1 and the third insulating layer PAS3_4 are not disposed in the separation portion ROP of the sub-region SA, and the electrodes RME are spaced apart from each other to form the exposed via layer VIA. The first base part BP1 of the second insulating layer PAS2_4 may cover it. The third insulating layer PAS3_4 may be used as a mask pattern in a process of separating the electrode lines.
서브 영역(SA)의 분리부(ROP)를 제1 베이스부(BP1)가 덮음으로써, 서브 영역(SA) 내에서 제1 베이스부(BP1)에 의한 단차가 줄어들 수 있다. 제1 베이스부(BP1)는 복수의 연결 전극(CNE)들과 컨택부(CT1, CT2, CT3, CT4)들이 형성되는 영역을 제외하고 서브 영역(SA)을 모두 덮도록 배치된다. 예를 들어, 제1 베이스부(BP1)는 컨택부(CT1, CT2, CT3, CT4)들과 인접한 분리부(ROP)를 덮음으로써, 컨택부 이외의 위치에 형성되는 단차를 줄일 수 있다. 그에 따라, 연결 전극(CNE)들이 컨택부들 상에 형성될 때, 그와 인접한 분리부(ROP)에 형성된 단차에 의해 재료의 잔사가 남는 것이 방지되는 이점이 있다. As the first base part BP1 covers the separation part ROP of the sub-region SA, a step difference due to the first base part BP1 in the sub-region SA may be reduced. The first base part BP1 is disposed to cover all of the sub-regions SA except for a region where the plurality of connection electrodes CNE and the contact parts CT1 , CT2 , CT3 , and CT4 are formed. For example, the first base portion BP1 covers the separation portion ROP adjacent to the contact portions CT1 , CT2 , CT3 , and CT4 , thereby reducing a step formed at a location other than the contact portion. Accordingly, when the connection electrodes CNE are formed on the contact portions, there is an advantage in that a material residue is prevented from remaining due to a step formed in the separation portion ROP adjacent thereto.
한편, 상술한 실시예들에서 제1 뱅크(BNL1)의 각 뱅크부(BN1, BN2, BN3)들은 제1 방향(DR1)으로 측정된 길이가 발광 영역(EMA)보다 짧을 수 있다. 다만, 몇몇 실시예에서 각 뱅크부(BN1, BN2, BN3)들은 제1 방향(DR1)의 길이가 발광 영역(EMA)보다 길고, 제2 뱅크(BNL2)의 제2 방향(DR2)으로 연장된 부분과 중첩할 수도 있다. Meanwhile, in the above-described embodiments, each of the bank portions BN1 , BN2 , and BN3 of the first bank BNL1 may have a length measured in the first direction DR1 shorter than the emission area EMA. However, in some embodiments, each of the bank parts BN1 , BN2 , and BN3 has a length in the first direction DR1 longer than the emission area EMA and extends in the second direction DR2 of the second bank BNL2 . You can also nest parts.
도 23은 다른 실시예에 따른 표시 장치의 일 서브 화소를 나타내는 평면도이다. 도 24는 도 23의 A6부분의 확대도이다. 도 25는 도 23의 A7부분의 확대도이다. 도 26은 도 24의 Q8-Q8'선, 및 도 25의 Q9-Q9'선을 따라 자른 단면도이다. 도 24는 발광 영역(EMA)의 상측에 위치한 제2 뱅크(BNL2)와 제1 뱅크(BNL1)들의 일부분을 도시하고, 도 25는 발광 영역(EMA)의 하측에 위치한 제2 뱅크(BNL2)와 제1 뱅크(BNL1)들의 일부분을 도시하고 있다.23 is a plan view illustrating one sub-pixel of a display device according to another exemplary embodiment. 24 is an enlarged view of a portion A6 of FIG. 23 . 25 is an enlarged view of a portion A7 of FIG. 23 . 26 is a cross-sectional view taken along line Q8-Q8' of FIG. 24 and line Q9-Q9' of FIG. 25; FIG. 24 shows a portion of the second bank BNL2 and the first bank BNL1 positioned above the light emitting area EMA, and FIG. 25 shows the second bank BNL2 and the second bank BNL2 positioned below the light emitting area EMA. A portion of the first banks BNL1 is shown.
도 23 내지 도 26을 참조하면, 일 실시예에 따른 표시 장치(10_5)는 제1 뱅크(BNL1_5)의 복수의 뱅크부(BN1, BN2, BN3)들이 발광 영역(EMA)보다 제1 방향(DR1)으로 연장된 길이가 더 길 수 있다. 제2 뱅크(BNL2) 중 제2 방향(DR2)으로 연장된 부분은 각 뱅크부(BN1, BN2, BN3)들과 부분적으로 중첩할 수 있고, 이들이 중첩된 부분은 비아층(VIA)의 상면을 기준으로 측정된 높이가 다른 부분들보다 높을 수 있다. 연결 전극(CNE)들은 뱅크부(BN1, BN2, BN3) 상에서부터 제1 방향(DR1)으로 연장되어 서브 영역(SA)에 걸쳐 배치될 수 있다. 발광 영역(EMA)과 서브 영역(SA) 사이에서 뱅크부(BN1, BN2, BN3)들이 제2 뱅크(BNL2)와 부분적으로 중첩함에 따라, 발광 영역(EMA) 중 연결 전극(CNE)들이 배치된 부분과 제2 뱅크(BNL2) 사이의 단차가 줄어들 수 있다. 이는 연결 전극(CNE)들의 형성 공정에서 제2 뱅크(BNL2) 상에 재료의 잔사가 남는 것을 방지할 수 있다. 23 to 26 , in the display device 10_5 according to an exemplary embodiment, the plurality of bank portions BN1 , BN2 , and BN3 of the first bank BNL1_5 are arranged in the first direction DR1 rather than the emission area EMA. ) may be longer. A portion of the second bank BNL2 extending in the second direction DR2 may partially overlap each of the bank portions BN1 , BN2 , and BN3 , and the overlapping portion may overlap the top surface of the via layer VIA. The height measured as a reference may be higher than other parts. The connection electrodes CNE may extend in the first direction DR1 from the bank parts BN1 , BN2 , and BN3 to be disposed over the sub-region SA. As the bank portions BN1 , BN2 , and BN3 partially overlap the second bank BNL2 between the light emitting area EMA and the sub area SA, the connection electrodes CNE are disposed in the light emitting area EMA. A step difference between the portion and the second bank BNL2 may be reduced. This may prevent a material residue from remaining on the second bank BNL2 in the process of forming the connection electrodes CNE.
다만, 제1 뱅크(BNL1)의 뱅크부(BN1, BN2, BN3)들과 제2 뱅크(BNL2)가 중첩된 부분은 다른 부분들 대비 높게 형성될 수 있고, 이들 사이의 단차가 매우 커질 수 있다. 제2 절연층(PAS2_5)은 제2 뱅크(BNL2) 상에 배치되는 제2 베이스부(BP2)를 포함하는데, 제2 베이스부(BP2)가 제1 뱅크(BNL1)의 뱅크부(BN1, BN2, BN3)들 및 제2 뱅크(BNL2)와 동시에 중첩하는 경우, 그 단차 차이는 더 커질 수 있다. 이를 방지하기 위해, 제2 절연층(PAS2_5)의 제2 베이스부(BP2)는 제1 뱅크(BNL1)의 뱅크부(BN1, BN2, BN3)들 및 제2 뱅크(BNL2)가 중첩하는 부분에는 배치되지 않을 수 있다. However, a portion in which the bank portions BN1 , BN2 , BN3 of the first bank BNL1 and the second bank BNL2 overlap may be formed to be higher than other portions, and a step difference between them may be very large. . The second insulating layer PAS2_5 includes a second base part BP2 disposed on the second bank BNL2 , and the second base part BP2 is the bank parts BN1 and BN2 of the first bank BNL1 . , BN3 , and the second bank BNL2 overlap at the same time, the step difference may increase. In order to prevent this, the second base portion BP2 of the second insulating layer PAS2_5 is formed at a portion where the bank portions BN1 , BN2 , BN3 of the first bank BNL1 and the second bank BNL2 overlap. may not be placed.
이상 첨부된 도면을 참조하여 본 발명의 실시예들을 설명하였지만, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자는 본 발명의 그 기술적 사상이나 필수적인 특징을 변경하지 않고서 다른 구체적인 형태로 실시될 수 있다는 것을 이해할 수 있을 것이다. 그러므로 이상에서 기술한 실시예들은 모든 면에서 예시적인 것이며 한정적이 아닌 것으로 이해해야만 한다.Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those of ordinary skill in the art to which the present invention pertains may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. you will be able to understand Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

Claims (20)

  1. 발광 영역 및 상기 발광 영역의 제1 방향으로 이격된 서브 영역; a light emitting region and a sub region spaced apart from each other in a first direction;
    상기 발광 영역에 배치되어 상기 제1 방향으로 연장된 제1 전극, 및 상기 제1 전극과 상기 제1 방향과 교차하는 제2 방향으로 이격되고 상기 제1 방향으로 연장된 제2 전극; a first electrode disposed in the light emitting area and extending in the first direction, and a second electrode spaced apart from the first electrode in a second direction crossing the first direction and extending in the first direction;
    상기 제1 전극 및 상기 제2 전극 상에 배치된 제1 절연층; a first insulating layer disposed on the first electrode and the second electrode;
    상기 제1 절연층 상에 배치되고 양 단부 중 적어도 일 단부가 상기 제1 전극 또는 상기 제2 전극 상에 배치된 복수의 발광 소자들; a plurality of light emitting devices disposed on the first insulating layer and having at least one end of both ends disposed on the first electrode or the second electrode;
    상기 복수의 발광 소자들 상에 배치되어 상기 제1 방향으로 연장된 제1 패턴부 및 상기 서브 영역에 배치된 제1 베이스부를 포함하는 제2 절연층; 및 a second insulating layer disposed on the plurality of light emitting devices and including a first pattern portion extending in the first direction and a first base portion disposed in the sub region; and
    상기 제1 전극 상에 배치되어 상기 발광 소자와 접촉하는 제1 연결 전극, 및 상기 제2 전극 상에 배치되어 상기 발광 소자의 접촉하는 제2 연결 전극을 포함하고, a first connection electrode disposed on the first electrode to contact the light emitting device, and a second connection electrode disposed on the second electrode to contact the light emitting device,
    상기 제1 패턴부는 상기 발광 영역으로부터 상기 서브 영역에 걸쳐 배치되어 상기 제1 베이스부와 연결된 표시 장치.The first pattern part is disposed over the sub-region from the light-emitting region and is connected to the first base part.
  2. 제1 항에 있어서, The method of claim 1,
    상기 발광 영역에서 상기 제1 방향으로 연장된 복수의 뱅크부들을 포함하는 제1 뱅크, 및 상기 발광 영역과 상기 서브 영역을 둘러싸도록 배치된 제2 뱅크를 더 포함하고, A first bank including a plurality of bank portions extending in the first direction from the light emitting area, and a second bank disposed to surround the light emitting area and the sub area,
    상기 제2 절연층은 상기 제2 뱅크 상에 배치되어 상기 제1 베이스부 및 상기 제1 패턴부와 연결된 제2 베이스부를 더 포함하는 표시 장치.and the second insulating layer is disposed on the second bank and further includes a second base part connected to the first base part and the first pattern part.
  3. 제2 항에 있어서, 3. The method of claim 2,
    상기 제1 연결 전극 및 상기 제2 연결 전극은 각각 상기 발광 영역과 상기 서브 영역에 걸쳐 배치되고, The first connection electrode and the second connection electrode are respectively disposed over the light emitting region and the sub region,
    상기 제1 패턴부는 상기 제1 연결 전극과 상기 제2 연결 전극 사이에서 상기 제1 방향으로 연장되어 상기 제1 베이스부와 연결된 표시 장치.The first pattern portion extends in the first direction between the first connection electrode and the second connection electrode and is connected to the first base portion.
  4. 제3 항에 있어서, 4. The method of claim 3,
    상기 제1 연결 전극 및 상기 제2 연결 전극은 각각 상기 제1 패턴부의 양 측과 접촉하고, 상기 제1 패턴부의 폭은 상기 복수의 발광 소자의 길이보다 작은 표시 장치.The first connection electrode and the second connection electrode contact both sides of the first pattern portion, respectively, and a width of the first pattern portion is smaller than a length of the plurality of light emitting devices.
  5. 제2 항에 있어서, 3. The method of claim 2,
    상기 제1 전극과 상기 제2 전극 사이에 배치되어 상기 제1 방향으로 연장된 제3 전극을 더 포함하고, and a third electrode disposed between the first electrode and the second electrode and extending in the first direction,
    상기 복수의 발광 소자는 상기 제1 전극과 상기 제3 전극 상에 배치된 제1 발광 소자, 및 상기 제3 전극과 상기 제2 전극 상에 배치된 제2 발광 소자를 포함하며, The plurality of light emitting devices includes a first light emitting device disposed on the first electrode and the third electrode, and a second light emitting device disposed on the third electrode and the second electrode,
    상기 제2 절연층의 상기 제1 패턴부는 상기 제1 발광 소자들 상에 배치되고, The first pattern portion of the second insulating layer is disposed on the first light emitting devices,
    상기 제2 절연층은 상기 제2 발광 소자들 상에 배치된 제2 패턴부, 및 상기 제3 전극 상에 배치된 제1 지지 패턴부를 더 포함하는 표시 장치.The second insulating layer may further include a second pattern portion disposed on the second light emitting devices and a first support pattern portion disposed on the third electrode.
  6. 제5 항에 있어서, 6. The method of claim 5,
    상기 제2 절연층은 상기 제2 방향으로 연장된 형상을 갖고 상기 제1 패턴부와 상기 제2 베이스부에 연결된 제1 브릿지부, 및 상기 제2 방향으로 연장되고 상기 제2 패턴부와 제1 지지 패턴부에 연결된 제2 브릿지부를 더 포함하고, The second insulating layer has a shape extending in the second direction, a first bridge part connected to the first pattern part and the second base part, and extending in the second direction, the second pattern part and the first Further comprising a second bridge part connected to the support pattern part,
    상기 제1 브릿지부 및 상기 제2 브릿지부의 상기 제1 방향으로 측정된 폭은 상기 제1 패턴부와 상기 제2 패턴부의 상기 제2 방향으로 측정된 폭보다 큰 표시 장치.Widths of the first bridge part and the second bridge part measured in the first direction are greater than widths of the first pattern part and the second pattern part measured in the second direction.
  7. 제6 항에 있어서, 7. The method of claim 6,
    상기 제1 지지 패턴부는 상기 제3 전극 상에서 상기 제1 방향으로 연장되고, 상기 제2 방향으로 측정된 폭이 상기 제1 브릿지부 및 상기 제2 브릿지부의 상기 제1 방향으로 측정된 폭보다 큰 표시 장치.The first support pattern part extends in the first direction on the third electrode, and a width measured in the second direction is greater than a width measured in the first direction of the first bridge part and the second bridge part Device.
  8. 제2 항에 있어서, 3. The method of claim 2,
    상기 제1 뱅크의 상기 복수의 뱅크부들은 각각 상기 제1 방향으로 연장된 길이가 상기 발광 영역보다 길고, Each of the plurality of bank parts of the first bank has a length extending in the first direction longer than the light emitting area,
    상기 제2 뱅크 중 상기 발광 영역과 상기 서브 영역 사이에 배치된 부분은 상기 복수의 뱅크부들과 두께 방향으로 중첩하고, a portion of the second bank disposed between the light emitting region and the sub region overlaps the plurality of bank portions in a thickness direction;
    상기 제2 베이스부는 상기 제2 뱅크 중 상기 뱅크부들과 중첩된 부분 상에는 배치되지 않는 표시 장치.The second base portion is not disposed on a portion of the second bank that overlaps the bank portions.
  9. 제1 항에 있어서, The method of claim 1,
    상기 제1 전극과 상기 제2 전극 사이에 배치된 제3 전극; a third electrode disposed between the first electrode and the second electrode;
    상기 제2 전극과 상기 제2 방향으로 이격된 제4 전극; a fourth electrode spaced apart from the second electrode in the second direction;
    상기 제1 전극과 상기 제3 전극에 걸쳐 배치된 제3 연결 전극; a third connection electrode disposed over the first electrode and the third electrode;
    상기 제3 전극과 상기 제4 전극에 걸쳐 배치된 제4 연결 전극; 및 a fourth connection electrode disposed over the third electrode and the fourth electrode; and
    상기 제4 전극과 상기 제2 전극에 걸쳐 배치된 제5 연결 전극을 더 포함하고, Further comprising a fifth connection electrode disposed over the fourth electrode and the second electrode,
    상기 복수의 발광 소자는 상기 제1 전극과 상기 제3 전극 상에 배치되어 상기 제1 연결 전극 및 상기 제3 연결 전극에 접촉하는 제1 발광 소자; The plurality of light emitting devices may include: a first light emitting device disposed on the first electrode and the third electrode and contacting the first connection electrode and the third connection electrode;
    상기 제2 전극과 상기 제4 전극 상에 배치되어 상기 제2 연결 전극 및 상기 제5 연결 전극과 접촉하는 제2 발광 소자; 상기 제1 전극과 상기 제3 전극 상에 배치되어 상기 제3 연결 전극 및 상기 제4 연결 전극에 접촉하는 제3 발광 소자; 및 a second light emitting device disposed on the second electrode and the fourth electrode and in contact with the second connection electrode and the fifth connection electrode; a third light emitting device disposed on the first electrode and the third electrode and contacting the third connection electrode and the fourth connection electrode; and
    상기 제2 전극과 상기 제4 전극 상에 배치되어 상기 제4 연결 전극 및 상기 제5 연결 전극과 접촉하는 제4 발광 소자를 포함하는 표시 장치.and a fourth light emitting element disposed on the second electrode and the fourth electrode and in contact with the fourth connection electrode and the fifth connection electrode.
  10. 제9 항에 있어서, 10. The method of claim 9,
    상기 제2 절연층의 상기 제1 패턴부는 상기 제1 발광 소자들 상에 배치되고, The first pattern portion of the second insulating layer is disposed on the first light emitting devices,
    상기 제2 절연층은 상기 제2 발광 소자들 상에 배치된 제2 패턴부; The second insulating layer may include a second pattern portion disposed on the second light emitting devices;
    상기 제3 발광 소자들 상에 배치된 제3 패턴부; a third pattern portion disposed on the third light emitting devices;
    상기 제4 발광 소자들 상에 배치된 제4 패턴부; a fourth pattern portion disposed on the fourth light emitting devices;
    상기 제2 전극과 상기 제3 전극에 부분적으로 중첩하며 상기 제1 방향으로 연장된 제1 지지 패턴부, 및 a first support pattern part partially overlapping the second electrode and the third electrode and extending in the first direction; and
    상기 제2 방향으로 연장된 형상을 갖고 상기 제1 지지 패턴부와 상기 제1 내지 제4 패턴부들 중 어느 하나와 연결된 복수의 브릿지부들을 더 포함하는 표시 장치.The display device further includes a plurality of bridge parts having a shape extending in the second direction and connected to any one of the first support pattern part and the first to fourth pattern parts.
  11. 제10 항에 있어서, 11. The method of claim 10,
    상기 복수의 브릿지부는 상기 제2 패턴부와 상기 제1 지지 패턴부를 연결하는 제2 브릿지부; The plurality of bridge parts may include: a second bridge part connecting the second pattern part and the first support pattern part;
    상기 제3 패턴부와 상기 제1 지지 패턴부를 연결하는 제3 브릿지부; 및 a third bridge part connecting the third pattern part and the first support pattern part; and
    상기 제4 패턴부와 상기 제1 지지 패턴부를 연결하는 제4 브릿지부를 포함하는 표시 장치.and a fourth bridge part connecting the fourth pattern part and the first support pattern part.
  12. 제10 항에 있어서, 11. The method of claim 10,
    상기 제2 절연층은 상기 발광 영역 내에서 상기 제1 방향으로 연장되고 상기 제1 지지 패턴부를 사이에 두고 서로 상기 제2 방향으로 이격된 제2 지지 패턴부 및 제3 지지 패턴부를 더 포함하고, The second insulating layer further includes a second support pattern portion and a third support pattern portion extending in the first direction in the light emitting region and spaced apart from each other in the second direction with the first support pattern portion interposed therebetween,
    상기 복수의 브릿지부는 상기 제1 패턴부 및 상기 제2 지지 패턴부와 연결된 제1 브릿지부; The plurality of bridge parts may include: a first bridge part connected to the first pattern part and the second support pattern part;
    상기 제4 패턴부 및 상기 제3 지지 패턴부와 연결된 제5 브릿지부; 및 a fifth bridge part connected to the fourth pattern part and the third support pattern part; and
    상기 제3 패턴부 및 상기 제2 지지 패턴부와 연결된 제6 브릿지부를 포함하는 표시 장치.and a sixth bridge part connected to the third pattern part and the second support pattern part.
  13. 제1 항에 있어서, The method of claim 1,
    상기 제2 절연층의 상기 제1 패턴부는 상기 제2 방향으로 측정된 폭이 상기 제1 패턴부의 두께보다 작은 표시 장치.A width of the first pattern portion of the second insulating layer measured in the second direction is smaller than a thickness of the first pattern portion.
  14. 제1 방향으로 연장되고 서로 상기 제1 방향과 교차하는 제2 방향으로 이격된 복수의 전극들로서, 제1 전극, 상기 제1 전극과 상기 제2 방향으로 이격된 제2 전극, 상기 제1 전극과 상기 제2 전극 사이에 배치된 제3 전극, 및 상기 제2 전극과 상기 제2 방향으로 이격된 제4 전극; A plurality of electrodes extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a first electrode, a second electrode spaced apart from the first electrode in the second direction, the first electrode and a third electrode disposed between the second electrodes, and a fourth electrode spaced apart from the second electrode in the second direction;
    상기 복수의 전극들 상에 배치된 제1 절연층; a first insulating layer disposed on the plurality of electrodes;
    양 단부가 상기 제1 전극 및 상기 제3 전극 상에 배치되어 상기 제1 방향으로 배열된 복수의 제1 발광 소자들, 및 양 단부가 상기 제2 전극 및 상기 제4 전극 상에 배치된 상기 제1 방향으로 배열된 복수의 제2 발광 소자들; 및a plurality of first light emitting devices having both ends disposed on the first electrode and the third electrode and arranged in the first direction, and the second electrode having both ends disposed on the second electrode and the fourth electrode a plurality of second light emitting elements arranged in one direction; and
    상기 제1 발광 소자들 상에 배치되어 상기 제1 방향으로 연장된 제1 패턴부, 상기 제2 발광 소자들 상에 배치되어 상기 제1 방향으로 연장된 제2 패턴부, 및 상기 제2 전극과 상기 제3 전극 상에 부분적으로 배치되고 상기 제1 방향으로 연장된 제1 지지 패턴부를 포함하는 제2 절연층을 포함하고, a first pattern part disposed on the first light emitting devices and extending in the first direction, a second pattern part disposed on the second light emitting devices and extending in the first direction, and the second electrode; a second insulating layer partially disposed on the third electrode and including a first support pattern part extending in the first direction;
    상기 제2 절연층은 상기 제2 방향으로 연장된 형상을 갖고 상기 제1 패턴부 및 상기 제2 패턴부 중 적어도 어느 하나 및 상기 제1 지지 패턴부에 연결된 복수의 브릿지부들을 포함하는 표시 장치.The second insulating layer has a shape extending in the second direction and includes at least one of the first pattern part and the second pattern part, and a plurality of bridge parts connected to the first support pattern part.
  15. 제14 항에 있어서, 15. The method of claim 14,
    상기 제1 패턴부 및 상기 제2 패턴부의 상기 제2 방향으로 측정된 제1 폭은 각각 상기 복수의 제1 발광 소자 및 상기 복수의 제2 발광 소자의 길이보다 작고, A first width measured in the second direction of the first pattern portion and the second pattern portion is smaller than lengths of the plurality of first light emitting elements and the plurality of second light emitting elements, respectively,
    상기 복수의 브릿지부들의 상기 제1 방향으로 측정된 제2 폭은 상기 제1 패턴부 및 상기 제2 패턴부의 상기 제1 폭보다 크고, A second width of the plurality of bridge portions measured in the first direction is greater than the first width of the first pattern portion and the second pattern portion,
    상기 제1 지지 패턴부의 상기 제2 방향으로 측정된 제3 폭은 상기 복수의 브릿지부들의 상기 제1 방향으로 측정된 상기 제2 폭보다 큰 표시 장치.A third width of the first support pattern part measured in the second direction is greater than the second width of the plurality of bridge parts measured in the first direction.
  16. 제15 항에 있어서, 16. The method of claim 15,
    상기 제1 패턴부 및 상기 제2 패턴부의 두께는 상기 제1 패턴부 및 상기 제2 패턴부의 상기 제1 폭보다 큰 표시 장치.The thickness of the first pattern part and the second pattern part is greater than the first width of the first pattern part and the second pattern part.
  17. 제14 항에 있어서, 15. The method of claim 14,
    상기 복수의 전극들과 중첩하며 상기 제1 방향으로 연장된 복수의 뱅크부들을 포함하는 제1 뱅크, 및 a first bank overlapping the plurality of electrodes and including a plurality of bank portions extending in the first direction; and
    상기 복수의 제1 발광 소자들 및 상기 복수의 제2 발광 소자들이 배치된 발광 영역과 상기 발광 영역으로부터 상기 제1 방향으로 이격된 서브 영역을 둘러싸는 제2 뱅크를 더 포함하고, A second bank surrounding a light emitting area in which the plurality of first light emitting elements and the plurality of second light emitting elements are disposed and a sub area spaced apart from the light emitting area in the first direction,
    상기 제2 절연층은 상기 서브 영역에 배치된 제1 베이스부, 및 상기 제2 뱅크 상에 배치된 제2 베이스부를 더 포함하며, The second insulating layer further includes a first base portion disposed in the sub-region, and a second base portion disposed on the second bank,
    상기 제1 패턴부 및 상기 제2 패턴부는 각각 상기 발광 영역으로부터 상기 서브 영역에 연장되어 상기 제1 베이스부와 연결된 표시 장치.The first pattern part and the second pattern part each extend from the light emitting area to the sub area and are connected to the first base part.
  18. 제17 항에 있어서, 18. The method of claim 17,
    상기 제2 절연층은 상기 제2 방향으로 연장된 형상을 갖고 상기 제1 패턴부 및 상기 제2 베이스부와 연결된 제1 브릿지부를 더 포함하는 표시 장치.The second insulating layer may further include a first bridge part having a shape extending in the second direction and connected to the first pattern part and the second base part.
  19. 제14 항에 있어서, 15. The method of claim 14,
    상기 제2 절연층은 상기 제1 패턴부와 상기 제1 방향으로 이격되어 위치하는 제3 패턴부; The second insulating layer may include a third pattern portion spaced apart from the first pattern portion in the first direction;
    상기 제2 패턴부와 상기 제1 방향으로 이격되어 위치하는 제4 패턴부; 및 a fourth pattern portion spaced apart from the second pattern portion in the first direction; and
    상기 제1 방향으로 연장되고, 상기 제1 지지 패턴부를 사이에 두고 서로 상기 제2 방향으로 이격된 제2 지지 패턴부와 제3 지지 패턴부를 더 포함하고, It further includes a second support pattern portion and a third support pattern portion extending in the first direction and spaced apart from each other in the second direction with the first support pattern portion interposed therebetween,
    상기 복수의 브릿지부는 상기 제1 패턴부 및 상기 제2 지지 패턴부와 연결된 제1 브릿지부; The plurality of bridge parts may include: a first bridge part connected to the first pattern part and the second support pattern part;
    상기 제2 패턴부 및 상기 제1 지지 패턴부와 연결된 제2 브릿지부; a second bridge part connected to the second pattern part and the first support pattern part;
    상기 제3 패턴부 및 상기 제1 지지 패턴부와 연결된 제3 브릿지부; 및 a third bridge part connected to the third pattern part and the first support pattern part; and
    상기 제4 패턴부 및 상기 제1 지지 패턴부와 연결된 제4 브릿지부를 포함하는 표시 장치.and a fourth bridge part connected to the fourth pattern part and the first support pattern part.
  20. 제19 항에 있어서, 20. The method of claim 19,
    상기 복수의 브릿지부는 상기 제4 패턴부와 상기 제3 지지 패턴부와 연결된 제5 브릿지부; 및 The plurality of bridge parts may include: a fifth bridge part connected to the fourth pattern part and the third support pattern part; and
    상기 제3 패턴부와 상기 제2 지지 패턴부와 연결된 제6 브릿지부를 더 포함하는 표시 장치.The display device further comprising a sixth bridge part connected to the third pattern part and the second support pattern part.
PCT/KR2022/000020 2021-01-08 2022-01-03 Display device WO2022149813A1 (en)

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KR20200138479A (en) * 2019-05-29 2020-12-10 삼성디스플레이 주식회사 Display device

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