WO2022142856A1 - 一种led调光电路 - Google Patents

一种led调光电路 Download PDF

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Publication number
WO2022142856A1
WO2022142856A1 PCT/CN2021/132133 CN2021132133W WO2022142856A1 WO 2022142856 A1 WO2022142856 A1 WO 2022142856A1 CN 2021132133 W CN2021132133 W CN 2021132133W WO 2022142856 A1 WO2022142856 A1 WO 2022142856A1
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level
low
capacitor
terminal
signal
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PCT/CN2021/132133
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English (en)
French (fr)
Inventor
刘军
李国成
吴泉清
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华润微集成电路(无锡)有限公司
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Priority to EP21913598.5A priority Critical patent/EP4110016B1/en
Publication of WO2022142856A1 publication Critical patent/WO2022142856A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/10—Controlling the intensity of the light
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/32—Pulse-control circuits
    • H05B45/325—Pulse-width modulation [PWM]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/32—Pulse-control circuits
    • H05B45/33—Pulse-amplitude modulation [PAM]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/32—Pulse-control circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/50—Circuit arrangements for operating light-emitting diodes [LED] responsive to malfunctions or undesirable behaviour of LEDs; responsive to LED life; Protective circuits
    • H05B45/59—Circuit arrangements for operating light-emitting diodes [LED] responsive to malfunctions or undesirable behaviour of LEDs; responsive to LED life; Protective circuits for reducing or suppressing flicker or glow effects
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection

Definitions

  • the invention belongs to the field of integrated circuit design, in particular to an LED dimming circuit.
  • one is analog dimming, that is, by adjusting the reference voltage to adjust the LED output current to achieve dimming (as shown in Figure 1a);
  • the advantage is that it can be done No stroboscopic output, the disadvantage is that the dimming depth is relatively small, usually only about 3%, because the reference voltage will be very small if the dimming depth is smaller, and the chip accuracy will not meet the requirements at this time, and the LED output current is too small. Color cast will occur.
  • PWM dimming that is, the PWM dimming signal is used to adjust the LED output current to achieve dimming (as shown in Figure 1b); this dimming method also has some problems, and the LED output current follows the PWM dimming signal. If the frequency of the PWM dimming signal is too low, the human eye can see flickering, but if the frequency of the PWM dimming signal is relatively high in order to avoid flickering, the minimum on-time of the PWM dimming signal will be affected by the change.
  • the above dimming method still has defects.
  • the frequency of the PWM dimming signal cannot be too low, otherwise there will still be stroboscopic flicker.
  • the dimming frequency needs to be Greater than 3kHz is a safe range for the human eye, so the dimming frequency range is limited;
  • a PWM signal with an analog signal must be output, which has relatively high requirements on the microcontroller.
  • the amplitude and duty cycle of the PWM dimming signal are All of them will have an impact on the LED output current, so the requirements for the preparation of the PWM dimming signal are relatively high.
  • the purpose of the present invention is to provide an LED dimming circuit to solve the limitation of the dimming frequency of the existing dimming method combining analog dimming and PWM dimming, and the The single-chip microcomputer that generates the dimming signal requires higher requirements.
  • the LED dimming circuit includes:
  • the low-level voltage generation module is used to count the low-level in the period of the low-frequency PWM signal according to the high-frequency clock signal to obtain the low-level time, and then convert the low-level time to obtain the low-level voltage ;
  • the high-level voltage generation module is used to count the high-level in the period of the low-frequency PWM signal according to the high-frequency clock signal to obtain the high-level time, and then convert the high-level time to obtain the high-level voltage ;
  • the reference voltage generation module is connected to the output end of the low-level voltage generation module and the output end of the high-level voltage generation module, and is used for charging the capacitor through a constant current to obtain a capacitor terminal voltage, and according to the A high-frequency switching signal is obtained from the comparison result of the capacitor terminal voltage and the high-level voltage.
  • the sum of the low-level voltage and the high-level voltage is compared with the capacitor terminal voltage, and control is performed according to the comparison result.
  • the period of the high-frequency switching signal then, under the control of the high-frequency switching signal, the capacitor is charged and discharged based on the reference voltage to generate a reference voltage only related to the duty cycle of the low-frequency PWM signal;
  • a dimming signal generating module connected to the output end of the reference voltage generating module, for outputting the reference voltage as a dimming signal when the reference voltage is greater than a set voltage; when the reference voltage is less than the set voltage
  • a new PWM signal whose value is the set voltage and whose frequency is independent of the low-frequency PWM signal is output as the dimming signal, wherein the average value of the new PWM signal is the same as the reference voltage.
  • the low-level voltage generating module includes:
  • a rising edge detection unit configured to generate a low-level counting end signal when the rising edge of the low-frequency PWM signal arrives
  • the first counter whose clock input terminal is connected to the high-frequency clock signal, and whose reset terminal is connected to the output terminal of the rising edge detection unit, is used to perform a periodical period on the low-frequency PWM signal according to the high-frequency clock signal.
  • the low-level counting is performed, and when the low-level counting end signal is valid, a reset operation is performed to complete the low-level counting, and at the same time, the next high-level counting is started;
  • a first digital-to-analog converter connected to the output end of the first counter, for performing digital-to-analog conversion on the low-level time output by the first counter;
  • a low-level voltage latching unit connected to the output end of the first digital-to-analog converter, for latching the output of the first digital-to-analog converter when the low-level counting end signal is valid to obtain the low-level voltage
  • the high-level voltage generating module includes:
  • a falling edge detection unit configured to generate a high-level counting end signal when the falling edge of the low-frequency PWM signal arrives
  • the second counter whose clock input terminal is connected to the high-frequency clock signal, and whose reset terminal is connected to the output terminal of the falling edge detection unit, is used to perform a periodical period on the low-frequency PWM signal according to the high-frequency clock signal.
  • high-level counting and when the high-level counting end signal is valid, a reset operation is performed to complete the high-level counting, and simultaneously start the next low-level counting;
  • a second digital-to-analog converter connected to the output end of the second counter, for performing digital-to-analog conversion on the high level time output by the second counter
  • a high-level voltage latch unit connected to the output end of the second digital-to-analog converter, for latching the output of the second digital-to-analog converter when the high-level counting end signal is valid to obtain the high-level voltage
  • the first counter is the same as the second counter
  • the first digital-to-analog converter is the same as the second digital-to-analog converter
  • the low-level voltage generation module and the high-level voltage generation module share a counter and a digital-to-analog converter; at this time, the reset terminal of the counter is connected to the rising edge through the first adder.
  • the output end of the detection unit and the output end of the falling edge detection unit, the output end of the counter is connected to the input end of the digital-to-analog converter, and the output end of the digital-to-analog converter is connected to the low level
  • the low-level voltage latching unit includes: a first switch and a first capacitor, the control end of the first switch is connected to the output end of the rising edge detection unit, and the first switch of the first switch is connected to the output end of the rising edge detection unit.
  • a connection end is connected to the output end of the digital-to-analog converter, the second connection end of the first switch is connected to one end of the first capacitor, and serves as the output end of the low-level voltage generating module, so The other end of the first capacitor is grounded;
  • the high-level voltage latching unit includes: a second switch and a second capacitor, the control end of the second switch is connected to the output end of the falling edge detection unit, and the first connection end of the second switch is connected to At the output end of the digital-to-analog converter, the second connection end of the second switch is connected to one end of the second capacitor, and serves as the output end of the high-level voltage generating module, the second capacitor the other end is grounded.
  • the LED dimming circuit further includes:
  • the low-level voltage clearing module is connected to both ends of the first capacitor, and is used to reset the latched voltage in the first capacitor when the low-frequency PWM signal is high and the counter overflows.
  • the low-level voltage performs a clearing operation
  • a high-level voltage clearing module is connected to both ends of the second capacitor, and is used to reset the latched voltage in the second capacitor when the low-frequency PWM signal is low and the counter overflows.
  • the high-level voltage performs a clearing operation.
  • the low-level voltage clearing module includes:
  • a high-level detection unit for generating a high-level detection signal when the low-frequency PWM signal is at a high level
  • the first AND gate one input end of which is connected to the output end of the high-level detection unit, and the other input end of which is connected to the counting overflow end of the counter, is used for when the high-level detection signal is valid and all When the counter overflows, a low-level voltage clearing drive signal is generated;
  • a first MOS transistor the gate terminal of which is connected to the output terminal of the first AND gate, the drain terminal of which is connected to one end of the first capacitor, and the source terminal of which is connected to the other end of the first capacitor, used for The low-level voltage clearing drive signal is turned on when valid, so as to perform a zero-clearing operation on the low-level voltage latched in the first capacitor;
  • the high-level voltage clearing module includes:
  • a low-level detection unit configured to generate a low-level detection signal when the low-frequency PWM signal is at a low level
  • the second AND gate one input terminal of which is connected to the output terminal of the low-level detection unit, and the other input terminal of which is connected to the counting overflow terminal of the counter, used for when the low-level detection signal is valid and all When the counter overflows, a high-level voltage clearing drive signal is generated;
  • the second MOS transistor has its gate terminal connected to the output terminal of the second AND gate, its drain terminal connected to one end of the second capacitor, and its source terminal connected to the other end of the second capacitor for
  • the high-level voltage clearing drive signal is turned on when valid, so as to perform a clearing operation on the high-level voltage latched in the second capacitor.
  • the low-level voltage generating module further includes:
  • a low-level auxiliary transmission unit connected between the digital-to-analog converter and the first capacitor, for transmitting the output of the digital-to-analog converter to the digital-to-analog converter when the low-level detection signal is valid the first capacitor;
  • the high-level voltage generating module further includes:
  • a high-level auxiliary transmission unit connected between the digital-to-analog converter and the second capacitor, for transmitting the output of the digital-to-analog converter to the said high-level detection signal when the high-level detection signal is valid second capacitor.
  • the low-level auxiliary transmission unit includes: a third switch and a first diode, the control terminal of the third switch is connected to the output terminal of the low-level detection unit, and the third switch The first connection end of the switch is connected to the output end of the digital-to-analog converter, the second connection end of the third switch is connected to the positive end of the first diode, and the negative end of the first diode connected to one end of the first capacitor;
  • the high-level auxiliary transmission unit includes: a fourth switch and a second diode, the control terminal of the fourth switch is connected to the output terminal of the high-level detection unit, and the first connection of the fourth switch The terminal is connected to the output terminal of the digital-to-analog converter, the second connection terminal of the fourth switch is connected to the positive terminal of the second diode, and the negative terminal of the second diode is connected to the one end of the second capacitor.
  • the reference voltage generating module includes:
  • a low-level voltage buffer unit connected to the output end of the low-level voltage generating module, for buffering the low-level voltage
  • a high-level voltage buffer unit connected to the output end of the high-level voltage generating module, for buffering the high-level voltage
  • a constant current source and a third capacitor the current input terminal of the constant current source is connected to the power supply voltage, the current output terminal of the constant current source is connected to one end of the third capacitor, and the other end of the third capacitor is grounded , for charging the third capacitor with a constant current provided by the constant current source, so as to generate a capacitor terminal voltage at one end of the third capacitor;
  • the first comparator whose non-inverting input terminal is connected to one end of the third capacitor, and whose inverting input terminal is connected to the output terminal of the high-level voltage buffer unit, is used for comparing the capacitor terminal voltage and the high-level voltage buffer unit. comparing the level voltages and obtaining the high-frequency switching signal according to the comparison result;
  • a second comparator whose non-inverting input terminal is connected to one end of the third capacitor, and whose inverting input terminal is connected to the output terminal of the low-level voltage buffer unit and the high-level voltage buffer through a second adder
  • the output terminal of the unit is used to compare the capacitor terminal voltage and the sum of the low-level voltage and the high-level voltage, and the capacitor terminal voltage is not less than the low-level voltage and the high-level voltage
  • a discharge drive signal is generated when the sum of the high-level voltages is generated;
  • the gate terminal of the third MOS transistor is connected to the output terminal of the second comparator, the drain terminal is connected to one end of the third capacitor, and the source terminal is connected to the other terminal of the third capacitor.
  • the discharge driving signal is turned on when it is valid, so as to discharge the third capacitor, and start the next cycle after the discharge ends, so as to control the cycle of the high-frequency switching signal;
  • the reference voltage generating unit is connected to the output end of the first comparator, and is used for generating the reference voltage by charging and discharging a capacitor based on the reference voltage under the control of the high-frequency switching signal.
  • the reference voltage generating unit includes: a first resistor, a second resistor, a fifth switch, a fourth capacitor and an operational amplifier, one end of the first resistor is connected to the reference voltage, and the first resistor
  • the other end of the fifth switch is connected to the first connection end of the fifth switch and one end of the second resistor, the control end of the fifth switch is connected to the output end of the first comparator, and the control end of the fifth switch is connected to the output end of the first comparator.
  • the second connection end is grounded, the other end of the second resistor is connected to one end of the fourth capacitor and the non-inverting input end of the operational amplifier, the other end of the fourth capacitor is grounded, and the inverting phase of the operational amplifier
  • the input terminal is connected to the output terminal and serves as the output terminal of the reference voltage generating module.
  • the dimming signal generating module includes:
  • a switch control signal generating unit configured to generate an analog output switch control signal when the reference voltage is greater than the set voltage, and when the reference voltage is less than the set voltage, according to the high level of the low-frequency PWM signal
  • the counting and cycle counter counts the high-frequency clock signal to generate a PWM output switch control signal
  • an output control unit connected to the output end of the reference voltage generation module and the output end of the switch control signal generation unit, for outputting a switch control signal in the analog when the reference voltage is greater than the set voltage Under the control of the PWM output switch, the reference voltage is output as the dimming signal; when the reference voltage is less than the set voltage, a new PWM signal is output as the dimming signal under the control of the PWM output switch control signal.
  • the switch control signal generating unit includes:
  • a register for latching the high-level count in the high-level voltage generating module when the falling edge of the low-frequency PWM signal arrives;
  • a cycle counter the clock input terminal of which is connected to the high-frequency clock signal, and is used to cycle count the high-frequency clock signal
  • XOR gate one input end is connected to the output end of the register, and the other input end is connected to the output end of the loop counter, used for the high level count latched in the register and the loop counter generating a clock trigger signal when the count of the high frequency clock signal by the counter is consistent;
  • the third AND gate one input end of which is connected to the counting overflow end of the loop counter through the first inverter, and the other input end of which is connected to the control signal output end of the output control unit, used for A set trigger signal is generated when the voltage is greater than the set voltage or the cycle counter overflows;
  • the output end of the switch control signal generating unit is used to generate a switch on signal when the set trigger signal is valid, and generate a switch off signal when the clock trigger signal is valid.
  • the output control unit includes: a second inverter, a third comparator, a sixth switch, a seventh switch and an eighth switch, and the non-inverting input end of the third comparator is connected to the reference voltage
  • the output end of the generation module and the first connection end of the sixth switch, the inverting input end of the third comparator is connected to the first connection end of the seventh switch, and connected to the set voltage
  • the output end of the third comparator is connected to the input end of the second inverter and the control end of the sixth switch
  • the output end of the second inverter is connected to the control end of the seventh switch
  • the second connection end of the sixth switch is connected to the second connection end of the seventh switch and the first connection end of the eighth switch, so
  • the control end of the eighth switch is connected to the output end of the switch control signal generating unit, and the second connection end of the eighth switch serves as the dimming signal output end of the dimming signal generating module.
  • an LED dimming circuit of the present invention has the following beneficial effects:
  • the LED dimming circuit of the present invention can output an analog signal only related to the duty cycle of the input low-frequency PWM signal as a dimming signal when the reference voltage is greater than the set voltage, and when the reference voltage is less than the set voltage, The output frequency is Amplitude decreases to The new PWM signal is used as the dimming signal, and the average value of the new PWM signal is the same as the reference voltage, so as to control the external dimming current.
  • the dimming signal of the present invention is only related to the duty cycle of the input low-frequency PWM signal, thereby reducing the requirements for the single-chip microcomputer that generates the dimming signal.
  • the present invention outputs an analog signal as a dimming signal when dimming a large current, and does not need to use a large capacitor in the process of converting a low-frequency PWM signal to an analog signal, so that the output analog signal can respond instantly to the input low-frequency PWM signal, and can Integrated inside the chip to simplify peripheral circuits.
  • the dimming current is small, the output frequency is Amplitude decreases to
  • the new PWM signal is used as the dimming signal, and the average value of the new PWM signal is the same as the reference voltage, so as to reduce the programming requirements for the input low-frequency PWM signal; at the same time, the frequency of the new PWM signal is the same as that of the input low-frequency PWM signal. It is irrelevant.
  • the frequency of the new PWM signal can be made higher than the frequency that the human eye can see the flicker, so as to avoid the limitation of the dimming frequency and realize the output without stroboscopic, and The reduction in the amplitude of the new PWM signal can reduce the generation of audible noise.
  • FIG. 2 is a circuit structure diagram of the LED dimming circuit according to the present invention.
  • FIG. 3 is a waveform diagram of each signal when the LED dimming circuit according to the present invention generates a reference voltage.
  • FIG. 4 is a waveform diagram of each signal of the LED dimming circuit according to the present invention when the dimming ratio is high.
  • this embodiment provides an LED dimming circuit, and the LED dimming circuit includes:
  • the low-level voltage generating module 100 is configured to perform low-level counting on the low-frequency PWM signal in a period according to the high-frequency clock signal CLK to obtain the low-level time Toff, and then perform conversion processing on the low-level time Toff to obtain Low-level voltage VToff;
  • the high-level voltage generating module 200 is configured to perform high-level counting on the low-frequency PWM signal in a period according to the high-frequency clock signal CLK to obtain the high-level time Ton, and then perform conversion processing on the high-level time Ton to obtain High level voltage VTon;
  • the reference voltage generation module 500 is connected to the output end of the low-level voltage generation module 100 and the output end of the high-level voltage generation module 200, and is used for charging the capacitor through a constant current to obtain a capacitor terminal voltage, and A high-frequency switching signal is obtained according to the comparison result between the capacitor terminal voltage and the high-level voltage VTon.
  • the sum of the low-level voltage and the high-level voltage is compared with the capacitor terminal voltage, and the period of the high-frequency switching signal is controlled according to the comparison result; then, under the control of the high-frequency switching signal , the capacitor is charged and discharged based on the reference voltage Vref to generate a reference voltage Vref_out1 only related to the duty cycle of the low-frequency PWM signal;
  • the dimming signal generating module 600 is connected to the output end of the reference voltage generating module 500, and is used for outputting the reference voltage Vref_out1 as a dimming signal when the reference voltage Vref_out1 is greater than the set voltage Vref_min; When the voltage Vref_out1 is lower than the set voltage Vref_min, a new PWM signal whose value is the set voltage and whose frequency is independent of the low frequency PWM signal is output as the dimming signal, wherein the average value of the new PWM signal It is the same as the reference voltage Vref_out1.
  • the low-level voltage generating module 100 includes:
  • a rising edge detection unit 101 configured to generate a low-level counting end signal when the rising edge of the low-frequency PWM signal arrives;
  • the first counter whose clock input terminal is connected to the high-frequency clock signal CLK, and whose reset terminal is connected to the output terminal of the rising edge detection unit 101, is used for analyzing the low-frequency PWM signal according to the high-frequency clock signal CLK. Perform low-level counting in the cycle, and perform a reset operation when the low-level counting end signal is valid to complete the low-level counting, and simultaneously start the next high-level counting;
  • a first digital-to-analog converter connected to the output end of the first counter, for performing digital-to-analog conversion on the low-level time Toff output by the first counter;
  • the low-level voltage latch unit 102 is connected to the output end of the first digital-to-analog converter, and is used for locking the output of the first digital-to-analog converter when the low-level counting end signal is valid stored to obtain the low-level voltage VToff;
  • the high-level voltage generating module 200 includes:
  • the falling edge detection unit 201 is used to generate a high level counting end signal when the falling edge of the low frequency PWM signal arrives;
  • the second counter whose clock input terminal is connected to the high-frequency clock signal CLK, and whose reset terminal is connected to the output terminal of the falling edge detection unit 201, is used for analyzing the low-frequency PWM signal according to the high-frequency clock signal CLK. Perform high-level counting in the cycle, and perform a reset operation when the high-level counting end signal is valid to complete the high-level counting, and simultaneously start the next low-level counting;
  • a second digital-to-analog converter connected to the output end of the second counter, for performing digital-to-analog conversion on the high-level time Ton output by the second counter;
  • the high-level voltage latch unit 202 is connected to the output end of the second digital-to-analog converter, and is used for locking the output of the second digital-to-analog converter when the high-level counting end signal is valid stored to obtain the high-level voltage VTon;
  • the first counter is the same as the second counter
  • the first digital-to-analog converter is the same as the second digital-to-analog converter. It should be noted that “the first counter is the same as the second counter, and the first digital-to-analog converter is the same as the second digital-to-analog converter” mentioned here means that the structures and parameters of the two devices are identical.
  • the low-level voltage generation module 100 and the high-level voltage generation module 200 share a counter Counter1 and a digital-to-analog converter DAC; at this time, the reset terminal of the counter Counter1 passes through the An adder ADD1 is connected to the output end of the rising edge detection unit 101 and the output end of the falling edge detection unit 201 , the output end of the counter Counter1 is connected to the input end of the digital-to-analog converter DAC, the The output terminal of the digital-to-analog converter DAC is connected to the input terminal of the low-level voltage latch unit 102 and the input terminal of the high-level voltage latch unit 202 (specifically, as shown in FIG. 2 ).
  • the rising edge detection unit 101 is any existing circuit that can realize the rising edge detection of the PWM signal
  • the falling edge detection unit 201 is any existing circuit that can realize the falling edge detection of the PWM signal. This example does not limit its specific circuit composition.
  • the low-level voltage latch unit 102 includes: a first switch S1 and a first capacitor C1 , and the control end of the first switch S1 is connected to the rising edge detection unit 101 . output end, the first connection end of the first switch S1 is connected to the output end of the digital-to-analog converter DAC, the second connection end of the first switch S1 is connected to one end of the first capacitor C1, and As the output end of the low-level voltage generating module 100, the other end of the first capacitor C1 is grounded;
  • the high-level voltage latching unit 202 includes: a second switch S2 and a second capacitor C2, the first The control terminal of the second switch S2 is connected to the output terminal of the falling edge detection unit 201, the first connection terminal of the second switch S2 is connected to the output terminal of the digital-to-analog converter DAC, and the The second connection end is connected to one end of the second capacitor C2 and serves as the output end of the high-level voltage generating module 200 , and
  • counter1 is used to count the low level of the low-frequency PWM signal through the high-frequency clock signal CLK, and then the digital-to-analog converter DAC is used to perform digital-to-analog conversion on the output of the counter.
  • the edge is used as a trigger signal to trigger the reset terminal of the counter Counter1 to end low-level counting, and at the same time, the rising edge of the low-frequency PWM signal is used as a switch control signal to control the first switch S1 to be turned on to latch the output of the digital-to-analog converter DAC. into the first capacitor C1 to obtain a low-level voltage VToff.
  • the counter1 counts the high level of the low-frequency PWM signal through the high-frequency clock signal CLK, and then the digital-to-analog converter DAC is used to perform digital-to-analog conversion on the output of the counter Counter1; among them, the falling edge of the low-frequency PWM signal is used.
  • the reset terminal of the counter Counter1 is triggered to end high-level counting, and at the same time, the falling edge of the low-frequency PWM signal is used as a switch control signal to control the second switch S2 to be turned on, so as to latch the output of the digital-to-analog converter DAC to In the second capacitor C2, a high-level voltage VTon is obtained.
  • the LED dimming circuit further includes:
  • the low-level voltage clearing module 300 is connected to both ends of the first capacitor C1, and is used for performing a reset on the first capacitor C1 when the low-frequency PWM signal is at a high level and the counter Counter1 overflows.
  • the low-level voltage VToff latched in the middle is cleared;
  • the high-level voltage clearing module 400 is connected to both ends of the second capacitor C2, and is used for performing a reset on the second capacitor C2 when the low-frequency PWM signal is at a low level and the counter Counter1 overflows.
  • the high-level voltage VTon latched in the middle performs a clearing operation.
  • the low-level voltage clearing module 300 includes:
  • a high-level detection unit 301 configured to generate a high-level detection signal when the low-frequency PWM signal is at a high level
  • the first AND gate AND1 one input terminal of which is connected to the output terminal of the high-level detection unit 301, and the other input terminal of which is connected to the counting overflow terminal of the counter Counter1, is used to detect the signal at the high-level Valid and the counter1 generates a low-level voltage clearing drive signal when the counter overflows;
  • the gate terminal of the first MOS transistor M1 is connected to the output terminal of the first AND gate AND1, its drain terminal is connected to one end of the first capacitor C1, and its source terminal is connected to the other terminal of the first capacitor C1 , for conducting when the low-level voltage clearing drive signal is valid, so as to perform a clearing operation on the low-level voltage VToff latched in the first capacitor C1;
  • the high-level voltage clearing module 400 includes:
  • a low-level detection unit 401 configured to generate a low-level detection signal when the low-frequency PWM signal is at a low level
  • the second AND gate AND2 one input terminal of which is connected to the output terminal of the low-level detection unit 401, and the other input terminal of which is connected to the counting overflow terminal of the counter Counter1 for detecting the signal at the low-level Valid and the counter1 generates a high-level voltage clearing drive signal when the counter overflows;
  • the gate terminal of the second MOS transistor M2 is connected to the output terminal of the second AND gate AND2, its drain terminal is connected to one end of the second capacitor C2, and its source terminal is connected to the other terminal of the second capacitor C2 , which is used to turn on when the high-level voltage clearing drive signal is valid, so as to perform a clearing operation on the high-level voltage VTon latched in the second capacitor C2.
  • the frequency of the high frequency clock signal CLK and the number of bits of the counter Counter1 determine the maximum length of time that the counter Counter1 counts the high and low levels of the low frequency PWM signal
  • the count overflow signal generated by the counting overflow terminal of the counter Counter1 and the high-level detection signal generated by the high-level detection unit 301 pass through the first AND gate AND1 and The first MOS transistor M1 clears the low-level voltage VToff latched in the first capacitor C1; when the low-level count time of the low-frequency PWM signal by the counter Counter1 exceeds T_max, the count overflow signal generated by the counter overflow end of the counter Counter1 Together with the low-level detection signal generated by the low-level detection unit 401, the high-level voltage VTon latched in the second capacitor C2 is cleared through the second AND gate AND2 and the second MOS transistor M2; this prevents the circuit from starting or When turned off, because the
  • the high-level detection unit 301 is any existing circuit that can realize the high-level detection of the PWM signal
  • the low-level detection unit 401 is any existing circuit that can realize the PWM signal detection.
  • a circuit for low-level detection of a signal the specific circuit composition of which is not limited in this example.
  • the low-level voltage generating module 100 further includes:
  • the low-level auxiliary transmission unit 103 is connected between the digital-to-analog converter DAC and the first capacitor C1, and is used for transferring the output of the digital-to-analog converter DAC when the low-level detection signal is valid transfer to the first capacitor C1;
  • the high-level voltage generating module 200 further includes:
  • the high-level auxiliary transmission unit 203 is connected between the digital-to-analog converter DAC and the second capacitor C2, and is used for transferring the output of the digital-to-analog converter DAC when the high-level detection signal is valid transferred to the second capacitor C2.
  • the low-level auxiliary transmission unit 103 includes: a third switch S3 and a first diode D1, and the control end of the third switch S3 is connected to the low-level detection unit 401, the first connection end of the third switch S3 is connected to the output end of the digital-to-analog converter DAC, and the second connection end of the third switch S3 is connected to the first diode D1
  • the positive terminal of the first diode D1 is connected to one end of the first capacitor C1;
  • the high-level auxiliary transmission unit 203 includes: a fourth switch S4 and a second diode D2, so The control end of the fourth switch S4 is connected to the output end of the high level detection unit 301, the first connection end of the fourth switch S4 is connected to the output end of the digital-to-analog converter DAC, the fourth The second connection terminal of the switch S4 is connected to the positive terminal of the second diode D2, and the negative terminal of the second diode D2 is connected to one
  • the low-level detection signal generated by the low-level detection unit 401 is used to control the third switch S3 to be turned on, so as to control the first switch S1 to be turned on even if there is no rising edge of the low-frequency PWM signal as the switch control signal
  • the output of the digital-to-analog converter DAC can also be latched into the first capacitor C1 through the first diode D1; similarly, the fourth switch S4 is controlled to be turned on by using the high-level detection signal generated by the high-level detection unit 301 , so that the output of the digital-to-analog converter DAC can be latched into the second capacitor C2 through the second diode D2 even if there is no falling edge of the low-frequency PWM signal as the switch control signal to control the second switch S2 to be turned on.
  • the reference voltage generating module 500 includes:
  • a low-level voltage buffer unit 501 connected to the output end of the low-level voltage generating module 100, for buffering the low-level voltage VToff;
  • a high-level voltage buffer unit 502 connected to the output end of the high-level voltage generating module 200, for buffering the high-level voltage VTon;
  • a constant current source I1 and a third capacitor C3 the current input terminal of the constant current source I1 is connected to the power supply voltage Vdd, the current output terminal of the constant current source I1 is connected to one end of the third capacitor C3, the The other end of the three capacitors C3 is grounded for charging the third capacitor C3 through the constant current provided by the constant current source I1, so as to generate a capacitor terminal voltage VC3 at one end of the third capacitor C3;
  • the non-inverting input terminal of the first comparator CMP1 is connected to one end of the third capacitor C3, and the inverting input terminal of the first comparator CMP1 is connected to the output terminal of the high-level voltage buffer unit 502, and is used for comparing the capacitor terminal voltage VC3 and the high-level voltage VTon is compared and the high-frequency switching signal is obtained according to the comparison result;
  • the non-inverting input end of the second comparator CMP2 is connected to one end of the third capacitor C3, and the inverting input end of the second comparator CMP2 is connected to the output end of the low-level voltage buffer unit 501 and the high-level voltage buffer unit 501 through the second adder ADD2.
  • the output terminal of the level voltage buffer unit 502 is used to compare the capacitor terminal voltage VC3 and the sum of the low level voltage VToff and the high level voltage VTon, and the capacitor terminal voltage VC3 is not less than A discharge driving signal is generated when the low-level voltage VToff and the high-level voltage VTon are summed;
  • the gate terminal of the third MOS transistor M3 is connected to the output terminal of the second comparator CMP2, its drain terminal is connected to one end of the third capacitor C3, and its source terminal is connected to the other terminal of the third capacitor C3 , which is used to turn on when the discharge driving signal is valid, so as to discharge the third capacitor C3, and start the next cycle after the discharge ends, so as to control the cycle of the high-frequency switching signal;
  • the reference voltage generating unit 503 is connected to the output end of the first comparator CMP1, and is configured to perform capacitor charging and discharging based on the reference voltage Vref under the control of the high-frequency switching signal to generate the reference voltage Vref_out1.
  • the low-level voltage buffer unit 501 and the high-level voltage buffer unit 502 are any existing circuits that can implement a voltage buffer function, and the specific circuit composition thereof is not limited in this example.
  • the reference voltage generating unit 503 includes: a first resistor R1, a second resistor R2, a fifth switch S5, a fourth capacitor C4 and an operational amplifier OP, and one end of the first resistor R1 Connect to the reference voltage Vref, the other end of the first resistor R1 is connected to the first connection end of the fifth switch S5 and one end of the second resistor R2, and the control end of the fifth switch S5 is connected to At the output end of the first comparator CMP1, the second connection end of the fifth switch S5 is grounded, and the other end of the second resistor R2 is connected to one end of the fourth capacitor C4 and the operational amplifier OP The non-inverting input end of the fourth capacitor C4 is grounded, and the inverting input end of the operational amplifier OP is connected to its output end and serves as the output end of the reference voltage generating module 500 .
  • the low-level voltage VToff and the high-level voltage VTon work together to obtain a high-frequency switch through the constant current source I1, the third capacitor C3, the first comparator CMP1, the second comparator CMP2 and the third MOS transistor M3.
  • the first comparator CMP1 compares the capacitor terminal voltage and the high-level voltage to control the fifth switch S5, so as to determine the high level of the high-frequency switch signal, and the second comparator CMP2 is used to control the fifth switch S5.
  • the third MOS transistor M3 is controlled by the comparison result of the sum of the low-level voltage and the high-level voltage and the capacitor terminal voltage, thereby determining the period of the high-frequency switching signal; then the fifth switch S5 is controlled by the high-frequency switching signal It is turned on or off to obtain an approximate DC reference voltage Vref_out1 at one end of the fourth capacitor C4, and the isolated output of the reference voltage Vref_out1 is realized through the operational amplifier OP.
  • the constant current source I1 and the third capacitor C3 determine the minimum switching signal frequency of the reference voltage generating module 500 When the capacitor terminal voltage is less than the high level voltage, that is, VC3 ⁇ VTon, the first comparator CMP1 outputs a low level to control the fifth switch S5 to be turned off.
  • the reference voltage Vref passes through the pair of the first resistor R1 and the second resistor R2.
  • the fourth capacitor C4 is charged, and the charging time
  • the first comparator CMP1 outputs a high level to control the fifth switch S5 to be turned on
  • the fourth capacitor C4 is discharged to the ground through the second resistor R2 and the fifth switch S5;
  • the second comparator CMP2 outputs a high level to control the conduction of the third MOS transistor M3, discharges the third capacitor C3, and restarts a new cycle after the discharge ends, with a new cycle time Therefore Since the time constant of the second resistor R2 and the fourth capacitor C4 is much larger than the period T
  • the dimming signal generating module 600 includes:
  • a switch control signal generating unit 601 is configured to generate an analog output switch control signal when the reference voltage Vref_out1 is greater than the set voltage Vref_min, and when the reference voltage Vref_out1 is less than the set voltage Vref_min, according to the low frequency PWM
  • the high-level count of the signal and the cycle counter count the high-frequency clock signal to generate a PWM output switch control signal;
  • the output control unit 602 is connected to the output end of the reference voltage generation module 500 and the output end of the switch control signal generation unit 601 , and is used for, when the reference voltage Vref_out1 is greater than the set voltage Vref_min, The reference voltage Vref_out1 is output as a dimming signal under the control of the analog output switch control signal; when the reference voltage Vref_out1 is less than the set voltage Vref_min, a new PWM signal is output under the control of the PWM output switch control signal as the dimming signal.
  • the switch control signal generating unit 601 includes:
  • a register Reg used for latching the high-level count in the high-level voltage generating module when the falling edge of the low-frequency PWM signal arrives;
  • a cycle counter Counter2 the clock input terminal of which is connected to the high-frequency clock signal CLK, and is used to cycle count the high-frequency clock signal CLK;
  • XOR gate XOR one input end of which is connected to the output end of the register Reg, and the other input end of which is connected to the output end of the loop counter Counter2, for counting the high level latched in the register Reg
  • a clock trigger signal is generated when the cycle counter Counter2 counts the high-frequency clock signal CLK consistent;
  • the third AND gate AND3 has one input terminal connected to the counting overflow terminal of the loop counter Counter2 through the first inverter I1, and the other input terminal connected to the control signal output terminal of the output control unit 602 for use in A set trigger signal is generated when the reference voltage Vref_out1 is greater than the set voltage Vref_min or the cycle counter Counter2 overflows;
  • D flip-flop DFF its clock input end is connected to the output end of the XOR gate XOR, its data end is connected to a low level, its set end is connected to the output end of the third AND gate AND1, and its output end As the output end of the switch control signal generating unit 601, it is used to generate a switch-on signal when the set trigger signal is valid, and generate a switch-off signal when the clock trigger signal is valid.
  • the output control unit 602 includes: a second inverter I2 , a third comparator CMP3 , a sixth switch S6 , a seventh switch S7 and an eighth switch S8 , the third comparator
  • the non-inverting input end of the comparator CMP3 is connected to the output end of the reference voltage generating module 500 and the first connection end of the sixth switch S6, and the inverting input end of the third comparator CMP3 is connected to the seventh switch
  • the first connection end of S7 is connected to the set voltage Vref_min
  • the output end of the third comparator CMP3 is connected to the input end of the second inverter I2 and the control end of the sixth switch S6
  • the output terminal of the second inverter I2 is connected to the control terminal of the seventh switch S7, and is used as the control signal output terminal of the output control unit 602
  • the second connection terminal of the sixth switch S6 is connected to At the second connection end of the seventh switch S7 and the first connection end of the
  • the set voltage is set When Vref_out1>Vref_min, the third comparator CMP3 outputs a high level to control the sixth switch S6 to be turned on and the seventh switch S7 to be turned off.
  • the high level is connected to the second inverter I2 and the third AND gate AND3
  • Vref_out1 ⁇ Vref_min the third comparator CMP3 outputs a low level to control the sixth switch S6 to be turned off and the seventh switch S7 to be turned on.
  • the cycle counter Counter2 generates a count overflow signal of one cycle and passes through the first inverter.
  • the level count is latched in the register Ref.
  • the XOR gate XOR When the count of the loop counter Counter2 is consistent with the high-level count latched in the register Reg, the XOR gate XOR outputs a low-level clock trigger signal to trigger the D flip-flop, making D
  • the resolution is the minimum dimming ratio of (specifically shown in Figure 4).
  • the LED dimming circuit of the present invention has the following beneficial effects: the LED dimming circuit of the present invention can realize that when the reference voltage is greater than the set voltage, the output is only equal to the input low-frequency PWM signal.
  • the analog signal related to the empty ratio is used as the dimming signal.
  • the output frequency is Amplitude decreases to
  • the new PWM signal is used as the dimming signal, and the average value of the new PWM signal is the same as the reference voltage, so as to control the external dimming current.
  • the dimming signal of the present invention is only related to the duty ratio of the input low-frequency PWM signal, thereby reducing the requirements for the single-chip microcomputer that generates the dimming signal.
  • the present invention outputs an analog signal as a dimming signal when dimming a large current, and does not need to use a large capacitor in the process of converting a low-frequency PWM signal to an analog signal, so that the output analog signal can respond instantly to the input low-frequency PWM signal, and can Integrated inside the chip to simplify peripheral circuits.
  • the dimming current is small, the output frequency is Amplitude decreases to
  • the new PWM signal is used as the dimming signal, and the average value of the new PWM signal is the same as the reference voltage, so as to reduce the programming requirements for the input low-frequency PWM signal; at the same time, the frequency of the new PWM signal is the same as that of the input low-frequency PWM signal. It is irrelevant.
  • the frequency of the new PWM signal can be made higher than the frequency that the human eye can see the flicker, so as to avoid the limitation of the dimming frequency and realize the output without stroboscopic, and
  • the reduction in the amplitude of the new PWM signal can reduce the generation of audible noise.
  • the present invention in the case of parallel connection of multiple LED lamps, as long as the sampling frequencies of the high-frequency clock signals are consistent, even when the dimming is adjusted to a small brightness, the dimming consistency of the multiple lamps will be very good. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

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Abstract

提供一LED调光电路，包括低电平电压产生模块（100）、高电平电压产生模块（200）、基准电压产生模块（500）及调光信号产生模块（600），通过对低频PWM信号的高、低电平进行计数以得到相对于时间的高、低电平电压，再通过恒流源与电容转换成高频开关信号，并以此得到一仅与低频PWM信号占空比相关的直流基准电压；在基准电压大于设定电压时输出该基准电压作为调光信号；在基准电压小于设定电压时，输出一幅值为设定电压且频率与低频PWM信号无关的新PWM信号作为调光信号，新PWM信号的平均值与基准电压相同。提供的LED调光电路，解决了现有模拟调光与PWM调光相结合的调光方式存在的调光频率受限且对产生调光信号的单片机要求较高的问题。

Description

一种LED调光电路 技术领域
本发明属于集成电路设计领域，特别是涉及一种LED调光电路。
背景技术
在LED照明的应用中，通常有两种调光方式：一种是模拟调光，即通过调节基准电压来调节LED输出电流从而实现调光(具体如图1a所示)；其优点是可以做到输出无频闪，缺点是调光深度比较小，通常只有3％左右，因为调光深度再小的话基准电压就会很小，此时芯片精度会无法达到要求，另外LED输出电流过小时还会产生色偏。另一种是PWM调光，即通过PWM调光信号来调节LED输出电流从而实现调光(具体如图1b所示)；此种调光方式也存在一些问题，LED输出电流跟随PWM调光信号在变化，如果PWM调光信号的频率过低，会导致人眼能够看到闪烁，但如果为了避免闪烁，使PWM调光信号的频率比较高，那么PWM调光信号的最小导通时间会受限制(例如1kHz做0.1％调光深度，最小导通时间需要为1uS)，通常给出调光信号的单片机无法做到这么小的时间输出，并且，由于LED输出电流是从0-100％的变化，在电路中容易产生音频噪声，影响使用者的感受。
为了解决上述两种调光方式存在的缺点，现有提出了一种将模拟调光与PWM调光相结合的调光方式(具体如图1c所示)，在输出小电流的时候一方面减小占空比，另一方面减小基准电压来得到比较低的LED输出电流；例如基准做到10％，PWM占空比做到1％，输出电流就可以做到0.1％，此时1kHz的最小占空比只要10uS，单片机就可以满足要求，并且小电流时的变化幅度不再是0-100％，而是0-10％，相对可以减小输出电流纹波并且减少噪声的产生。
但是上述这种调光方式仍然存在缺陷，首先是PWM调光信号的频率仍然不能太低，否则仍然会有频闪，根据IEEE-STD-1789的标准，调制指数为100％时调光频率需要大于3kHz才属于对人眼比较安全的范围，因此调光频率范围受限；其次要输出一个带模拟信号的PWM信号，对单片机的要求比较高，同时PWM调光信号的幅值和占空比都会对LED输出电流产生影响，从而对PWM调光信号的编制要求比较高。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种LED调光电路，用以解决现有模拟调光与PWM调光相结合的调光方式存在的调光频率受限且对产生调光信号的单片机要求较高的问题。
为实现上述目的及其他相关目的，本发明提供一种LED调光电路，所述LED调光电路包括：
低电平电压产生模块，用于根据高频时钟信号对低频PWM信号进行周期内的低电平计数以得到低电平时间，之后对所述低电平时间进行转换处理以得到低电平电压；
高电平电压产生模块，用于根据高频时钟信号对低频PWM信号进行周期内的高电平计数以得到高电平时间，之后对所述高电平时间进行转换处理以得到高电平电压；
基准电压产生模块，连接于所述低电平电压产生模块的输出端及所述高电平电压产生模块的输出端，用于通过恒定电流对电容充电以得到一电容端电压，并根据所述电容端电压和所述高电平电压的比较结果得到一高频开关信号，同时将所述低电平电压与所述高电平电压之和与所述电容端电压进行比较，根据比较结果控制所述高频开关信号的周期；之后在所述高频开关信号的控制下，基于参考电压进行电容充放电以产生一仅与所述低频PWM信号占空比相关的基准电压；
调光信号产生模块，连接于所述基准电压产生模块的输出端，用于在所述基准电压大于设定电压时，输出所述基准电压作为调光信号；在所述基准电压小于所述设定电压时，输出一幅值为所述设定电压且频率与所述低频PWM信号无关的新PWM信号作为所述调光信号，其中所述新PWM信号的平均值与所述基准电压相同。
可选地，所述低电平电压产生模块包括：
上升沿检测单元，用于在所述低频PWM信号的上升沿到来时产生一低电平计数结束信号；
第一计数器，其时钟输入端接入所述高频时钟信号，其复位端连接于所述上升沿检测单元的输出端，用于根据所述高频时钟信号对所述低频PWM信号进行周期内的低电平计数，并在所述低电平计数结束信号有效时进行复位操作以完成低电平计数，同时开始下一次的高电平计数；
第一数模转换器，连接于所述第一计数器的输出端，用于对所述第一计数器输出的低电平时间进行数模转换；
低电平电压锁存单元，连接于所述第一数模转换器的输出端，用于在所述低电平计数结束信号有效时，对所述第一数模转换器的输出进行锁存以得到所述低电平电压；
所述高电平电压产生模块包括：
下降沿检测单元，用于在所述低频PWM信号的下降沿到来时产生一高电平计数结束信号；
第二计数器，其时钟输入端接入所述高频时钟信号，其复位端连接于所述下降沿检测单元的输出端，用于根据所述高频时钟信号对所述低频PWM信号进行周期内的高电平计数，并在所述高电平计数结束信号有效时进行复位操作以完成高电平计数，同时开始下一次的低电平计数；
第二数模转换器，连接于所述第二计数器的输出端，用于对所述第二计数器输出的高电平时间进行数模转换；
高电平电压锁存单元，连接于所述第二数模转换器的输出端，用于在所述高电平计数结束信号有效时，对所述第二数模转换器的输出进行锁存以得到所述高电平电压；
其中，所述第一计数器与所述第二计数器相同，所述第一数模转换器与所述第二数模转换器相同。
可选地，所述低电平电压产生模块与所述高电平电压产生模块共用一个计数器及数模转换器；此时，所述计数器的复位端通过第一加法器连接于所述上升沿检测单元的输出端及所述下降沿检测单元的输出端，所述计数器的输出端连接于所述数模转换器的输入端，所述数模转换器的输出端连接于所述低电平电压锁存单元的输入端及所述高电平电压锁存单元的输入端。
可选地，所述低电平电压锁存单元包括：第一开关及第一电容，所述第一开关的控制端连接于所述上升沿检测单元的输出端，所述第一开关的第一连接端连接于所述数模转换器的输出端，所述第一开关的第二连接端连接于所述第一电容的一端，并作为所述低电平电压产生模块的输出端，所述第一电容的另一端接地；
所述高电平电压锁存单元包括：第二开关及第二电容，所述第二开关的控制端连接于所述下降沿检测单元的输出端，所述第二开关的第一连接端连接于所述数模转换器的输出端，所述第二开关的第二连接端连接于所述第二电容的一端，并作为所述高电平电压产生模块的输出端，所述第二电容的另一端接地。
可选地，所述LED调光电路还包括：
低电平电压清零模块，连接于所述第一电容的两端，用于在所述低频PWM信号为高电平且所述计数器发生计数溢出时，对所述第一电容中锁存的所述低电平电压进行清零操作；
高电平电压清零模块，连接于所述第二电容的两端，用于在所述低频PWM信号为低电平且所述计数器发生计数溢出时，对所述第二电容中锁存的所述高电平电压进行清零操 作。
可选地，所述低电平电压清零模块包括：
高电平检测单元，用于在所述低频PWM信号为高电平时产生高电平检测信号；
第一与门，其一输入端连接于所述高电平检测单元的输出端，其另一输入端连接于所述计数器的计数溢出端，用于在所述高电平检测信号有效且所述计数器发生计数溢出时产生低电平电压清零驱动信号；
第一MOS管，其栅极端连接于所述第一与门的输出端，其漏极端连接于所述第一电容的一端，其源极端连接于所述第一电容的另一端，用于在所述低电平电压清零驱动信号有效时导通，以对所述第一电容中锁存的所述低电平电压进行清零操作；
所述高电平电压清零模块包括：
低电平检测单元，用于在所述低频PWM信号为低电平时产生低电平检测信号；
第二与门，其一输入端连接于所述低电平检测单元的输出端，其另一输入端连接于所述计数器的计数溢出端，用于在所述低电平检测信号有效且所述计数器发生计数溢出时产生高电平电压清零驱动信号；
第二MOS管，其栅极端连接于所述第二与门的输出端，其漏极端连接于所述第二电容的一端，其源极端连接于所述第二电容的另一端，用于在所述高电平电压清零驱动信号有效时导通，以对所述第二电容中锁存的所述高电平电压进行清零操作。
可选地，所述低电平电压产生模块还包括：
低电平辅助传输单元，连接于所述数模转换器及所述第一电容之间，用于在所述低电平检测信号有效时，将所述数模转换器的输出传输至所述第一电容；
所述高电平电压产生模块还包括：
高电平辅助传输单元，连接于所述数模转换器及所述第二电容之间，用于在所述高电平检测信号有效时，将所述数模转换器的输出传输至所述第二电容。
可选地，所述低电平辅助传输单元包括：第三开关及第一二极管，所述第三开关的控制端连接于所述低电平检测单元的输出端，所述第三开关的第一连接端连接于所述数模转换器的输出端，所述第三开关的第二连接端连接于所述第一二极管的正极端，所述第一二极管的负极端连接于所述第一电容的一端；
所述高电平辅助传输单元包括：第四开关及第二二极管，所述第四开关的控制端连接于所述高电平检测单元的输出端，所述第四开关的第一连接端连接于所述数模转换器的输出端，所述第四开关的第二连接端连接于所述第二二极管的正极端，所述第二二极管的负极端连接于所述第二电容的一端。
可选地，所述基准电压产生模块包括：
低电平电压缓存单元，连接于所述低电平电压产生模块的输出端，用于缓存所述低电平电压；
高电平电压缓存单元，连接于所述高电平电压产生模块的输出端，用于缓存所述高电平电压；
恒流源及第三电容，所述恒流源的电流输入端接入电源电压，所述恒流源的电流输出端连接于所述第三电容的一端，所述第三电容的另一端接地，用于通过所述恒流源提供的恒定电流对所述第三电容充电，以在所述第三电容的一端产生电容端电压；
第一比较器，其同相输入端连接于所述第三电容的一端，其反相输入端连接于所述高电平电压缓存单元的输出端，用于对所述电容端电压及所述高电平电压进行比较并根据比较结果得到所述高频开关信号；
第二比较器，其同相输入端连接于所述第三电容的一端，其反相输入端通过第二加法器连接于所述低电平电压缓存单元的输出端及所述高电平电压缓存单元的输出端，用于对所述电容端电压及所述低电平电压与所述高电平电压之和进行比较，并在所述电容端电压不小于所述低电平电压与所述高电平电压之和时产生放电驱动信号；
第三MOS管，其栅极端连接于所述第二比较器的输出端，其漏极端连接于所述第三电容的一端，其源极端连接于所述第三电容的另一端，用于在所述放电驱动信号有效时导通，以对所述第三电容进行放电操作，并在放电结束后开始下一周期，以此控制所述高频开关信号的周期；
基准电压产生单元，连接于所述第一比较器的输出端，用于在所述高频开关信号的控制下，基于所述参考电压进行电容充放电以产生所述基准电压。
可选地，所述基准电压产生单元包括：第一电阻、第二电阻、第五开关、第四电容及运算放大器，所述第一电阻的一端接入所述参考电压，所述第一电阻的另一端连接于所述第五开关的第一连接端及所述第二电阻的一端，所述第五开关的控制端连接于所述第一比较器的输出端，所述第五开关的第二连接端接地，所述第二电阻的另一端连接于所述第四电容的一端及所述运算放大器的同相输入端，所述第四电容的另一端接地，所述运算放大器的反相输入端连接于其输出端，并作为所述基准电压产生模块的输出端。
可选地，所述调光信号产生模块包括：
开关控制信号产生单元，用于在所述基准电压大于所述设定电压时产生模拟输出开关控制信号，在所述基准电压小于所述设定电压时，根据所述低频PWM信号的高电平计数及循环计数器对所述高频时钟信号的计数产生PWM输出开关控制信号；
输出控制单元，连接于所述基准电压产生模块的输出端及所述开关控制信号产生单元的输出端，用于在所述基准电压大于所述设定电压时，在所述模拟输出开关控制信号的控制下输出所述基准电压作为调光信号；在所述基准电压小于所述设定电压时，在所述PWM输出开关控制信号的控制下输出新PWM信号作为所述调光信号。
可选地，所述开关控制信号产生单元包括：
寄存器，用于在所述低频PWM信号的下降沿到来时，锁存所述高电平电压产生模块中的高电平计数；
循环计数器，其时钟输入端接入所述高频时钟信号，用于对所述高频时钟信号进行循环计数；
异或门，其一输入端连接于所述寄存器的输出端，其另一输入端连接于所述循环计数器的输出端，用于在所述寄存器中锁存的高电平计数与所述循环计数器对所述高频时钟信号的计数一致时产生时钟触发信号；
第三与门，其一输入端通过第一反相器连接于所述循环计数器的计数溢出端，其另一输入端连接于所述输出控制单元的控制信号输出端，用于在所述基准电压大于所述设定电压或所述循环计数器发生计数溢出时产生置位触发信号；
D触发器，其时钟输入端连接于所述异或门的输出端，其数据端接入低电平，其置位端连接于所述第三与门的输出端，其输出端作为所述开关控制信号产生单元的输出端，用于在所述置位触发信号有效时产生开关导通信号，在所述时钟触发信号有效时产生开关断开信号。
可选地，所述输出控制单元包括：第二反相器、第三比较器、第六开关、第七开关及第八开关，所述第三比较器的同相输入端连接于所述基准电压产生模块的输出端及所述第六开关的第一连接端，所述第三比较器的反相输入端连接于所述第七开关的第一连接端，并接入所述设定电压，所述第三比较器的输出端连接于所述第二反相器的输入端及所述第六开关的控制端，所述第二反相器的输出端连接于所述第七开关的控制端，并作为所述输出控制单元的控制信号输出端，所述第六开关的第二连接端连接于所述第七开关的第二连接端及所述第八开关的第一连接端，所述第八开关的控制端连接于所述开关控制信号产生单元的输出端，所述第八开关的第二连接端作为所述调光信号产生模块的调光信号输出端。
如上所述，本发明的一种LED调光电路，具有以下有益效果：
本发明所述LED调光电路，可实现在基准电压大于设定电压时，输出一仅与输入的低频PWM信号占空比相关的模拟信号作为调光信号，在基准电压小于设定电压时，输出一 频率为
Figure PCTCN2021132133-appb-000001
幅值减小至
Figure PCTCN2021132133-appb-000002
的新PWM信号作为调光信号，且该新PWM信号的平均值与基准电压相同，以此来控制外部调光电流。
本发明所述调光信号仅与输入的低频PWM信号的占空比相关，从而降低对产生调光信号的单片机的要求。
本发明在调光大电流时输出模拟信号作为调光信号，在低频PWM信号到模拟信号的转换过程中无需使用大电容，从而使得输出的模拟信号对输入的低频PWM信号可以即时响应，并且可以集成在芯片内部以简化外围电路。在调光小电流时输出频率为
Figure PCTCN2021132133-appb-000003
幅值减小至
Figure PCTCN2021132133-appb-000004
的新PWM信号作为调光信号，且该新PWM信号的平均值与基准电压相同，以此降低对输入的低频PWX信号的编制要求；同时该新PWM信号的频率与输入的低频PWM信号的频率无关，可以通过选择合适的高频时钟信号频率及循环计数器位数，使得该新PWM信号的频率高于人眼能够看到闪烁的频率，避免调光频率受限，实现输出无频闪，并且该新PWM信号的幅值的减小可以减少音频噪声的产生。
本发明对于多个LED灯并联的情况，只要高频时钟信号的采样频率一致，即使调光到小亮度时，多灯调光一致性也会很好。
附图说明
图1中(a)显示为现有模拟调光方式中LED输出电流随调光信号的波形变化，(b)显示为现有PWM调光方式中LED输出电流随调光信号的波形变化，(c)显示为现有模拟调光与PWM调光相结合的调光方式中LED输出电流随调光信号的波形变化。
图2显示为本发明所述LED调光电路的电路结构图。
图3显示为本发明所述LED调光电路产生基准电压时各信号的波形图。
图4显示为本发明所述LED调光电路在高调光比时各信号的波形图。
元件标号说明
100                   低电平电压产生模块
101                   上升沿检测单元
102                   低电平电压锁存单元
103                   低电平辅助传输单元
200                    高电平电压产生模块
201                    下降沿检测单元
202                    高电平电压锁存单元
203                    高电平辅助传输单元
300                    低电平电压清零模块
301                    高电平检测单元
400                    高电平电压清零模块
401                    低电平检测单元
500                    基准电压产生模块
501                    低电平电压缓存单元
502                    高电平电压缓存单元
503                    基准电压产生单元
600                    调光信号产生模块
601                    开关控制信号产生单元
602                    输出控制单元
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图2至图4。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，虽图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的形态、数量及比例可为一种随意的改变，且其组件布局形态也可能更为复杂。
如图2所示，本实施例提供一种LED调光电路，所述LED调光电路包括：
低电平电压产生模块100，用于根据高频时钟信号CLK对低频PWM信号进行周期内的低电平计数以得到低电平时间Toff，之后对所述低电平时间Toff进行转换处理以得到低电平电压VToff；
高电平电压产生模块200，用于根据高频时钟信号CLK对低频PWM信号进行周期内的高电平计数以得到高电平时间Ton，之后对所述高电平时间Ton进行转换处理以得到高 电平电压VTon；
基准电压产生模块500，连接于所述低电平电压产生模块100的输出端及所述高电平电压产生模块200的输出端，用于通过恒定电流对电容充电以得到一电容端电压，并根据所述电容端电压和所述高电平电压VTon的比较结果得到一高频开关信号。同时将所述低电平电压与所述高电平电压之和与所述电容端电压进行比较，根据比较结果控制所述高频开关信号的周期；之后在所述高频开关信号的控制下，基于参考电压Vref进行电容充放电以产生一仅与所述低频PWM信号占空比相关的基准电压Vref_out1；
调光信号产生模块600，连接于所述基准电压产生模块500的输出端，用于在所述基准电压Vref_out1大于设定电压Vref_min时，输出所述基准电压Vref_out1作为调光信号；在所述基准电压Vref_out1小于所述设定电压Vref_min时，输出一幅值为所述设定电压且频率与所述低频PWM信号无关的新PWM信号作为所述调光信号，其中所述新PWM信号的平均值与所述基准电压Vref_out1相同。
作为示例，如图2所示，所述低电平电压产生模块100包括：
上升沿检测单元101，用于在所述低频PWM信号的上升沿到来时产生一低电平计数结束信号；
第一计数器，其时钟输入端接入所述高频时钟信号CLK，其复位端连接于所述上升沿检测单元101的输出端，用于根据所述高频时钟信号CLK对所述低频PWM信号进行周期内的低电平计数，并在所述低电平计数结束信号有效时进行复位操作以完成低电平计数，同时开始下一次的高电平计数；
第一数模转换器，连接于所述第一计数器的输出端，用于对所述第一计数器输出的低电平时间Toff进行数模转换；
低电平电压锁存单元102，连接于所述第一数模转换器的输出端，用于在所述低电平计数结束信号有效时，对所述第一数模转换器的输出进行锁存以得到所述低电平电压VToff；
所述高电平电压产生模块200包括：
下降沿检测单元201，用于在所述低频PWM信号的下降沿到来时产生一高电平计数结束信号；
第二计数器，其时钟输入端接入所述高频时钟信号CLK，其复位端连接于所述下降沿检测单元201的输出端，用于根据所述高频时钟信号CLK对所述低频PWM信号进行周期内的高电平计数，并在所述高电平计数结束信号有效时进行复位操作以完成高电平计数，同时开始下一次的低电平计数；
第二数模转换器，连接于所述第二计数器的输出端，用于对所述第二计数器输出的高电平时间Ton进行数模转换；
高电平电压锁存单元202，连接于所述第二数模转换器的输出端，用于在所述高电平计数结束信号有效时，对所述第二数模转换器的输出进行锁存以得到所述高电平电压VTon；
其中，所述第一计数器与所述第二计数器相同，所述第一数模转换器与所述第二数模转换器相同。需要注意的是，此处所述“第一计数器与第二计数器相同，第一数模转换器与第二数模转换器相同”是指两器件的结构、参数完全相同。
可选地，本示例中，所述低电平电压产生模块100与所述高电平电压产生模块200共用一个计数器Counter1及数模转换器DAC；此时，所述计数器Counter1的复位端通过第一加法器ADD1连接于所述上升沿检测单元101的输出端及所述下降沿检测单元201的输出端，所述计数器Counter1的输出端连接于所述数模转换器DAC的输入端，所述数模转换器DAC的输出端连接于所述低电平电压锁存单元102的输入端及所述高电平电压锁存单元202的输入端(具体如图2所示)。
具体的，所述上升沿检测单元101为现有任一种可实现对PWM信号进行上升沿检测的电路，所述下降沿检测单元201为现有任一种可实现对PWM信号进行下降沿检测的电路，本示例对其具体电路组成不做限定。
具体的，如图2所示，所述低电平电压锁存单元102包括：第一开关S1及第一电容C1，所述第一开关S1的控制端连接于所述上升沿检测单元101的输出端，所述第一开关S1的第一连接端连接于所述数模转换器DAC的输出端，所述第一开关S1的第二连接端连接于所述第一电容C1的一端，并作为所述低电平电压产生模块100的输出端，所述第一电容C1的另一端接地；所述高电平电压锁存单元202包括：第二开关S2及第二电容C2，所述第二开关S2的控制端连接于所述下降沿检测单元201的输出端，所述第二开关S2的第一连接端连接于所述数模转换器DAC的输出端，所述第二开关S2的第二连接端连接于所述第二电容C2的一端，并作为所述高电平电压产生模块200的输出端，所述第二电容C2的另一端接地。
本示例中，利用计数器Counter1通过高频时钟信号CLK对低频PWM信号的低电平进行计数，之后再通过数模转换器DAC对计数器Counter1的输出进行数模转换；其中，以低频PWM信号的上升沿作为触发信号来触发计数器Counter1的复位端以结束低电平计数，同时以低频PWM信号的上升沿作为开关控制信号来控制第一开关S1导通，以将数模转换器DAC的输出锁存至第一电容C1中，从而得到低电平电压VToff。同理，利用计数 器Counter1通过高频时钟信号CLK对低频PWM信号的高电平进行计数，之后再通过数模转换器DAC对计数器Counter1的输出进行数模转换；其中，以低频PWM信号的下降沿作为触发信号来触发计数器Counter1的复位端以结束高电平计数，同时以低频PWM信号的下降沿作为开关控制信号来控制第二开关S2导通，以将数模转换器DAC的输出锁存至第二电容C2中，从而得到高电平电压VTon。
作为示例，如图2所示，所述LED调光电路还包括：
低电平电压清零模块300，连接于所述第一电容C1的两端，用于在所述低频PWM信号为高电平且所述计数器Counter1发生计数溢出时，对所述第一电容C1中锁存的所述低电平电压VToff进行清零操作；
高电平电压清零模块400，连接于所述第二电容C2的两端，用于在所述低频PWM信号为低电平且所述计数器Counter1发生计数溢出时，对所述第二电容C2中锁存的所述高电平电压VTon进行清零操作。
具体的，如图2所示，所述低电平电压清零模块300包括：
高电平检测单元301，用于在所述低频PWM信号为高电平时产生高电平检测信号；
第一与门AND1，其一输入端连接于所述高电平检测单元301的输出端，其另一输入端连接于所述计数器Counter1的计数溢出端，用于在所述高电平检测信号有效且所述计数器Counter1发生计数溢出时产生低电平电压清零驱动信号；
第一MOS管M1，其栅极端连接于所述第一与门AND1的输出端，其漏极端连接于所述第一电容C1的一端，其源极端连接于所述第一电容C1的另一端，用于在所述低电平电压清零驱动信号有效时导通，以对所述第一电容C1中锁存的所述低电平电压VToff进行清零操作；
所述高电平电压清零模块400包括：
低电平检测单元401，用于在所述低频PWM信号为低电平时产生低电平检测信号；
第二与门AND2，其一输入端连接于所述低电平检测单元401的输出端，其另一输入端连接于所述计数器Counter1的计数溢出端，用于在所述低电平检测信号有效且所述计数器Counter1发生计数溢出时产生高电平电压清零驱动信号；
第二MOS管M2，其栅极端连接于所述第二与门AND2的输出端，其漏极端连接于所述第二电容C2的一端，其源极端连接于所述第二电容C2的另一端，用于在所述高电平电压清零驱动信号有效时导通，以对所述第二电容C2中锁存的所述高电平电压VTon进行清零操作。
本示例中，高频时钟信号CLK的频率和计数器Counter1的位数决定了计数器Counter1 对低频PWM信号进行高、低电平计数的最大时间长度
Figure PCTCN2021132133-appb-000005
当计数器Counter1对低频PWM信号的高电平计数时间超过T_max时，计数器Counter1的计数溢出端产生的计数溢出信号与高电平检测单元301产生的高电平检测信号一起通过第一与门AND1及第一MOS管M1将第一电容C1中锁存的低电平电压VToff清零；当计数器Counter1对低频PWM信号的低电平计数时间超过T_max时，计数器Counter1的计数溢出端产生的计数溢出信号与低电平检测单元401产生的低电平检测信号一起通过第二与门AND2及第二MOS管M2将第二电容C2中锁存的高电平电压VTon清零；以此防止电路启动或关断时，因低频PWM信号只有一个上升沿或下降沿，从而导致输出卡在VTon_max+VToff_max的状态。需要注意的是，所述高电平检测单元301为现有任一种可实现对PWM信号进行高电平检测的电路，所述低电平检测单元401为现有任一种可实现对PWM信号进行低电平检测的电路，本示例对其具体电路组成不做限定。
作为示例，如图2所示，所述低电平电压产生模块100还包括：
低电平辅助传输单元103，连接于所述数模转换器DAC及所述第一电容C1之间，用于在所述低电平检测信号有效时，将所述数模转换器DAC的输出传输至所述第一电容C1；
所述高电平电压产生模块200还包括：
高电平辅助传输单元203，连接于所述数模转换器DAC及所述第二电容C2之间，用于在所述高电平检测信号有效时，将所述数模转换器DAC的输出传输至所述第二电容C2。
具体的，如图2所示，所述低电平辅助传输单元103包括：第三开关S3及第一二极管D1，所述第三开关S3的控制端连接于所述低电平检测单元401的输出端，所述第三开关S3的第一连接端连接于所述数模转换器DAC的输出端，所述第三开关S3的第二连接端连接于所述第一二极管D1的正极端，所述第一二极管D1的负极端连接于所述第一电容C1的一端；所述高电平辅助传输单元203包括：第四开关S4及第二二极管D2，所述第四开关S4的控制端连接于所述高电平检测单元301的输出端，所述第四开关S4的第一连接端连接于所述数模转换器DAC的输出端，所述第四开关S4的第二连接端连接于所述第二二极管D2的正极端，所述第二二极管D2的负极端连接于所述第二电容C2的一端。
本示例中，利用低电平检测单元401产生的低电平检测信号来控制第三开关S3导通，以实现即使没有低频PWM信号的上升沿作为开关控制信号来控制第一开关S1导通，数模转换器DAC的输出也能通过第一二极管D1锁存至第一电容C1中；同理，利用高电平检测单元301产生的高电平检测信号来控制第四开关S4导通，以实现即使没有低频PWM信号的下降沿作为开关控制信号来控制第二开关S2导通，数模转换器DAC的输出也能通过 第二二极管D2锁存至第二电容C2中。
作为示例，如图2所示，所述基准电压产生模块500包括：
低电平电压缓存单元501，连接于所述低电平电压产生模块100的输出端，用于缓存所述低电平电压VToff；
高电平电压缓存单元502，连接于所述高电平电压产生模块200的输出端，用于缓存所述高电平电压VTon；
恒流源I1及第三电容C3，所述恒流源I1的电流输入端接入电源电压Vdd，所述恒流源I1的电流输出端连接于所述第三电容C3的一端，所述第三电容C3的另一端接地，用于通过所述恒流源I1提供的恒定电流对所述第三电容C3充电，以在所述第三电容C3的一端产生电容端电压VC3；
第一比较器CMP1，其同相输入端连接于所述第三电容C3的一端，其反相输入端连接于所述高电平电压缓存单元502的输出端，用于对所述电容端电压VC3及所述高电平电压VTon进行比较并根据比较结果得到所述高频开关信号；
第二比较器CMP2，其同相输入端连接于所述第三电容C3的一端，其反相输入端通过第二加法器ADD2连接于所述低电平电压缓存单元501的输出端及所述高电平电压缓存单元502的输出端，用于对所述电容端电压VC3及所述低电平电压VToff与所述高电平电压VTon之和进行比较，并在所述电容端电压VC3不小于所述低电平电压VToff与所述高电平电压VTon之和时产生放电驱动信号；
第三MOS管M3，其栅极端连接于所述第二比较器CMP2的输出端，其漏极端连接于所述第三电容C3的一端，其源极端连接于所述第三电容C3的另一端，用于在所述放电驱动信号有效时导通，以对所述第三电容C3进行放电操作，并在放电结束后开始下一周期，以此控制所述高频开关信号的周期；
基准电压产生单元503，连接于所述第一比较器CMP1的输出端，用于在所述高频开关信号的控制下，基于所述参考电压Vref进行电容充放电以产生所述基准电压Vref_out1。
具体的，所述低电平电压缓存单元501及所述高电平电压缓存单元502为现有任一种可实现电压缓存功能的电路，本示例对其具体电路组成不做限定。
具体的，如图2所示，所述基准电压产生单元503包括：第一电阻R1、第二电阻R2、第五开关S5、第四电容C4及运算放大器OP，所述第一电阻R1的一端接入所述参考电压Vref，所述第一电阻R1的另一端连接于所述第五开关S5的第一连接端及所述第二电阻R2的一端，所述第五开关S5的控制端连接于所述第一比较器CMP1的输出端，所述第五开关S5的第二连接端接地，所述第二电阻R2的另一端连接于所述第四电容C4的一端及所 述运算放大器OP的同相输入端，所述第四电容C4的另一端接地，所述运算放大器OP的反相输入端连接于其输出端，并作为所述基准电压产生模块500的输出端。
本示例中，低电平电压VToff和高电平电压VTon通过恒流源I1、第三电容C3、第一比较器CMP1、第二比较器CMP2及第三MOS管M3共同作用得到一个高频开关信号，其中，利用第一比较器CMP1对电容端电压和高电平电压的比较结果来控制第五开关S5，以此决定了该高频开关信号的高电平，利用第二比较器CMP2对低电平电压与高电平电压之和与电容端电压的比较结果来控制第三MOS管M3，以此决定了该高频开关信号的周期；之后通过该高频开关信号控制第五开关S5导通或断开，以在第四电容C4的一端得到一近似直流的基准电压Vref_out1，并通过运算放大器OP实现该基准电压Vref_out1的隔离输出。具体为：恒流源I1与第三电容C3决定了基准电压产生模块500的最低开关信号频率
Figure PCTCN2021132133-appb-000006
当电容端电压小于高电平电压，即VC3<VTon时，第一比较器CMP1输出低电平以控制第五开关S5断开，此时参考电压Vref通过第一电阻R1、第二电阻R2对第四电容C4充电，充电时间
Figure PCTCN2021132133-appb-000007
当电容端电压大于高电平电压且小于低电平电压与高电平电压之和，即VTon<VC3<VTon+VToff时，第一比较器CMP1输出高电平以控制第五开关S5导通，此时第四电容C4通过第二电阻R2及第五开关S5放电到地；当电容端电压等于低电平电压与高电平电压之和，即VC3＝VTon+VToff时，第二比较器CMP2输出高电平以控制第三MOS管M3导通，对第三电容C3放电，并在放电结束后重新开始一个新的周期，新的周期时间
Figure PCTCN2021132133-appb-000008
由此可得
Figure PCTCN2021132133-appb-000009
由于第二电阻R2及第四电容C4的时间常数远大于该高频开关信号的周期Tnew，因此经过第二电阻R2及第四电容C4滤波后近似输出一个直流电压作为系统的基准电压来控制外部调光电流，且该基准电压Vref_out1与输入的低频PWM信号的频率无关，仅与输入的低频PWM信号的占空比相关，从而实现了低频PWM信号到模拟信号的调光转换(具体如图3所示)。
作为示例，如图2所示，所述调光信号产生模块600包括：
开关控制信号产生单元601，用于在所述基准电压Vref_out1大于所述设定电压Vref_min时产生模拟输出开关控制信号，在所述基准电压Vref_out1小于所述设定电压Vref_min时，根据所述低频PWM信号的高电平计数及循环计数器对所述高频时钟信号的计数产生PWM输出开关控制信号；
输出控制单元602，连接于所述基准电压产生模块500的输出端及所述开关控制信号产生单元601的输出端，用于在所述基准电压Vref_out1大于所述设定电压Vref_min时，在所述模拟输出开关控制信号的控制下输出所述基准电压Vref_out1作为调光信号；在所述基准电压Vref_out1小于所述设定电压Vref_min时，在所述PWM输出开关控制信号的控制下输出新PWM信号作为所述调光信号。
具体的，如图2所示，所述开关控制信号产生单元601包括：
寄存器Reg，用于在所述低频PWM信号的下降沿到来时，锁存所述高电平电压产生模块中的高电平计数；
循环计数器Counter2，其时钟输入端接入所述高频时钟信号CLK，用于对所述高频时钟信号CLK进行循环计数；
异或门XOR，其一输入端连接于所述寄存器Reg的输出端，其另一输入端连接于所述循环计数器Counter2的输出端，用于在所述寄存器Reg中锁存的高电平计数与所述循环计数器Counter2对所述高频时钟信号CLK的计数一致时产生时钟触发信号；
第三与门AND3，其一输入端通过第一反相器I1连接于所述循环计数器Counter2的计数溢出端，其另一输入端连接于所述输出控制单元602的控制信号输出端，用于在所述基准电压Vref_out1大于所述设定电压Vref_min或所述循环计数器Counter2发生计数溢出时产生置位触发信号；
D触发器DFF，其时钟输入端连接于所述异或门XOR的输出端，其数据端接入低电平，其置位端连接于所述第三与门AND1的输出端，其输出端作为所述开关控制信号产生单元601的输出端，用于在所述置位触发信号有效时产生开关导通信号，在所述时钟触发信号有效时产生开关断开信号。
具体的，如图2所示，所述输出控制单元602包括：第二反相器I2、第三比较器CMP3、第六开关S6、第七开关S7及第八开关S8，所述第三比较器CMP3的同相输入端连接于所述基准电压产生模块500的输出端及所述第六开关S6的第一连接端，所述第三比较器CMP3的反相输入端连接于所述第七开关S7的第一连接端，并接入所述设定电压Vref_min，所述第三比较器CMP3的输出端连接于所述第二反相器I2的输入端及所述第六开关S6的控制端，所述第二反相器I2的输出端连接于所述第七开关S7的控制端，并作为所述输出控制单元602的控制信号输出端，所述第六开关S6的第二连接端连接于所述第七开关S7的第二连接端及所述第八开关S8的第一连接端，所述第八开关S8的控制端连接于所述开关控制信号产生单元601的输出端，所述第八开关S8的第二连接端作为所述调光信号产生模块600的调光信号输出端。
本示例中，设定所述设定电压
Figure PCTCN2021132133-appb-000010
当Vref_out1>Vref_min时，第三比较器CMP3输出高电平以控制第六开关S6导通、第七开关S7断开，同时该高电平经第二反相器I2及第三与门AND3将D触发器DFF置位，以使D触发器DFF输出高电平控制第八开关S8导通，从而使Vref_out2＝Vref_out1。当Vref_out1<Vref_min时，第三比较器CMP3输出低电平以控制第六开关S6断开、第七开关S7导通，此时循环计数器Counter2产生一个周期的计数溢出信号并经过第一反相器I1及第三与门AND3将D触发器DFF置位，以使D触发器DFF输出高电平控制第八开关S8导通，从而使Vref_out2＝Vref_min；利用输入的低频PWM信号的下降沿将高电平计数锁存在寄存器Ref中，当循环计数器Counter2的计数与寄存器Reg中锁存的高电平计数一致时，异或门XOR输出一低电平的时钟触发信号以触发D触发器，使D触发器输出低电平以控制第八开关S8断开，此时Vref_out2＝0；可见，在Vref_out1<Vref_min时，可以得到一个新PWM信号作为调光信号输出，其中，该新PWM信号的频率为
Figure PCTCN2021132133-appb-000011
其占空比为
Figure PCTCN2021132133-appb-000012
并且此时的调光幅值为
Figure PCTCN2021132133-appb-000013
输出电流比例为
Figure PCTCN2021132133-appb-000014
分辨率即最小调光比为
Figure PCTCN2021132133-appb-000015
(具体如图4所示)。
综上所述，本发明的一种LED调光电路，具有以下有益效果：本发明所述LED调光电路，可实现在基准电压大于设定电压时，输出一仅与输入的低频PWM信号占空比相关的模拟信号作为调光信号，在基准电压小于设定电压时，输出一频率为
Figure PCTCN2021132133-appb-000016
幅值减小至
Figure PCTCN2021132133-appb-000017
的新PWM信号作为调光信号，且该新PWM信号的平均值与基准电压相同，以此来控制外部调光电流。本发明所述调光信号仅与输入的低频PWM信号的占空比相关，从而降低对产生调光信号的单片机的要求。本发明在调光大电流时输出模拟信号作为调光信号，在低频PWM信号到模拟信号的转换过程中无需使用大电容，从而使得输出的模拟信号对输入的低频PWM信号可以即时响应，并且可以集成在芯片内部以简化外围电路。在调光小电流时输出频率为
Figure PCTCN2021132133-appb-000018
幅值减小至
Figure PCTCN2021132133-appb-000019
的新PWM信号作为调光信号，且该新PWM信号的平均值与基准电压相同，以此降低对 输入的低频PWM信号的编制要求；同时该新PWM信号的频率与输入的低频PWM信号的频率无关，可以通过选择合适的高频时钟信号频率及循环计数器位数，使得该新PWM信号的频率高于人眼能够看到闪烁的频率，避免调光频率受限，实现输出无频闪，并且该新PWM信号的幅值的减小可以减少音频噪声的产生。本发明对于多个LED灯并联的情况，只要高频时钟信号的采样频率一致，即使调光到小亮度时，多灯调光一致性也会很好。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (15)

  1. 一种LED调光电路，其特征在于，所述LED调光电路包括：
    低电平电压产生模块，用于根据高频时钟信号对低频PWM信号进行周期内的低电平计数以得到低电平时间，之后对所述低电平时间进行转换处理以得到低电平电压；
    高电平电压产生模块，用于根据高频时钟信号对低频PWM信号进行周期内的高电平计数以得到高电平时间，之后对所述高电平时间进行转换处理以得到高电平电压；
    基准电压产生模块，连接于所述低电平电压产生模块的输出端及所述高电平电压产生模块的输出端，用于通过恒定电流对电容充电以得到一电容端电压，并根据所述电容端电压和所述高电平电压的比较结果得到一高频开关信号；同时将所述低电平电压与所述高电平电压之和与所述电容端电压进行比较，根据比较结果控制所述高频开关信号的周期；之后在所述高频开关信号的控制下，基于参考电压进行电容充放电以产生一仅与所述低频PWM信号占空比相关的基准电压；
    调光信号产生模块，连接于所述基准电压产生模块的输出端，用于在所述基准电压大于设定电压时，输出所述基准电压作为调光信号；在所述基准电压小于所述设定电压时，输出一幅值为所述设定电压且频率与所述低频PWM信号无关的新PWM信号作为所述调光信号，其中所述新的平均值与所述基准电压相同。
  2. 根据权利要求1所述的LED调光电路，其特征在于，所述低电平电压产生模块包括：
    上升沿检测单元，用于在所述低频PWM信号的上升沿到来时产生一低电平计数结束信号；
    第一计数器，其时钟输入端接入所述高频时钟信号，其复位端连接于所述上升沿检测单元的输出端，用于根据所述高频时钟信号对所述低频PWM信号进行周期内的低电平计数，并在所述低电平计数结束信号有效时进行复位操作以完成低电平计数，同时开始下一次的高电平计数；
    第一数模转换器，连接于所述第一计数器的输出端，用于对所述第一计数器输出的低电平时间进行数模转换；
    低电平电压锁存单元，连接于所述第一数模转换器的输出端，用于在所述低电平计数结束信号有效时，对所述第一数模转换器的输出进行锁存以得到所述低电平电压；
    所述高电平电压产生模块包括：
    下降沿检测单元，用于在所述低频PWM信号的下降沿到来时产生一高电平计数结束信号；
    第二计数器，其时钟输入端接入所述高频时钟信号，其复位端连接于所述下降沿检测 单元的输出端，用于根据所述高频时钟信号对所述低频PWM信号进行周期内的高电平计数，并在所述高电平计数结束信号有效时进行复位操作以完成高电平计数，同时开始下一次的低电平计数；
    第二数模转换器，连接于所述第二计数器的输出端，用于对所述第二计数器输出的高电平时间进行数模转换；
    高电平电压锁存单元，连接于所述第二数模转换器的输出端，用于在所述高电平计数结束信号有效时，对所述第二数模转换器的输出进行锁存以得到所述高电平电压；
    其中，所述第一计数器与所述第二计数器相同，所述第一数模转换器与所述第二数模转换器相同。
  3. 根据权利要求2所述的LED调光电路，其特征在于，所述低电平电压产生模块与所述高电平电压产生模块共用一个计数器及数模转换器；此时，所述计数器的复位端通过第一加法器连接于所述上升沿检测单元的输出端及所述下降沿检测单元的输出端，所述计数器的输出端连接于所述数模转换器的输入端，所述数模转换器的输出端连接于所述低电平电压锁存单元的输入端及所述高电平电压锁存单元的输入端。
  4. 根据权利要求3所述的LED调光电路，其特征在于，所述低电平电压锁存单元包括：第一开关及第一电容，所述第一开关的控制端连接于所述上升沿检测单元的输出端，所述第一开关的第一连接端连接于所述数模转换器的输出端，所述第一开关的第二连接端连接于所述第一电容的一端，并作为所述低电平电压产生模块的输出端，所述第一电容的另一端接地；
    所述高电平电压锁存单元包括：第二开关及第二电容，所述第二开关的控制端连接于所述下降沿检测单元的输出端，所述第二开关的第一连接端连接于所述数模转换器的输出端，所述第二开关的第二连接端连接于所述第二电容的一端，并作为所述高电平电压产生模块的输出端，所述第二电容的另一端接地。
  5. 根据权利要求4所述的LED调光电路，其特征在于，所述LED调光电路还包括：
    低电平电压清零模块，连接于所述第一电容的两端，用于在所述低频PWM信号为高电平且所述计数器发生计数溢出时，对所述第一电容中锁存的所述低电平电压进行清零操作；
    高电平电压清零模块，连接于所述第二电容的两端，用于在所述低频PWM信号为低电平且所述计数器发生计数溢出时，对所述第二电容中锁存的所述高电平电压进行清零操作。
  6. 根据权利要求5所述的LED调光电路，其特征在于，所述低电平电压清零模块包括：
    高电平检测单元，用于在所述低频PWM信号为高电平时产生高电平检测信号；
    第一与门，其一输入端连接于所述高电平检测单元的输出端，其另一输入端连接于所述计数器的计数溢出端，用于在所述高电平检测信号有效且所述计数器发生计数溢出时产生低电平电压清零驱动信号；
    第一MOS管，其栅极端连接于所述第一与门的输出端，其漏极端连接于所述第一电容的一端，其源极端连接于所述第一电容的另一端，用于在所述低电平电压清零驱动信号有效时导通，以对所述第一电容中锁存的所述低电平电压进行清零操作；
    所述高电平电压清零模块包括：
    低电平检测单元，用于在所述低频PWM信号为低电平时产生低电平检测信号；
    第二与门，其一输入端连接于所述低电平检测单元的输出端，其另一输入端连接于所述计数器的计数溢出端，用于在所述低电平检测信号有效且所述计数器发生计数溢出时产生高电平电压清零驱动信号；
    第二MOS管，其栅极端连接于所述第二与门的输出端，其漏极端连接于所述第二电容的一端，其源极端连接于所述第二电容的另一端，用于在所述高电平电压清零驱动信号有效时导通，以对所述第二电容中锁存的所述高电平电压进行清零操作。
  7. 根据权利要求6所述的LED调光电路，其特征在于，所述低电平电压产生模块还包括：
    低电平辅助传输单元，连接于所述数模转换器及所述第一电容之间，用于在所述低电平检测信号有效时，将所述数模转换器的输出传输至所述第一电容；
    所述高电平电压产生模块还包括：
    高电平辅助传输单元，连接于所述数模转换器及所述第二电容之间，用于在所述高电平检测信号有效时，将所述数模转换器的输出传输至所述第二电容。
  8. 根据权利要求7所述的LED调光电路，其特征在于，所述低电平辅助传输单元包括：第三开关及第一二极管，所述第三开关的控制端连接于所述低电平检测单元的输出端，所述第三开关的第一连接端连接于所述数模转换器的输出端，所述第三开关的第二连接端连接于所述第一二极管的正极端，所述第一二极管的负极端连接于所述第一电容的一端；
    所述高电平辅助传输单元包括：第四开关及第二二极管，所述第四开关的控制端连接于所述高电平检测单元的输出端，所述第四开关的第一连接端连接于所述数模转换器的输出端，所述第四开关的第二连接端连接于所述第二二极管的正极端，所述第二二极管的负极端连接于所述第二电容的一端。
  9. 根据权利要求1所述的LED调光电路，其特征在于，所述基准电压产生模块包括：
    低电平电压缓存单元，连接于所述低电平电压产生模块的输出端，用于缓存所述低电平电压；
    高电平电压缓存单元，连接于所述高电平电压产生模块的输出端，用于缓存所述高电平电压；
    恒流源及第三电容，所述恒流源的电流输入端接入电源电压，所述恒流源的电流输出端连接于所述第三电容的一端，所述第三电容的另一端接地，用于通过所述恒流源提供的恒定电流对所述第三电容充电，以在所述第三电容的一端产生电容端电压；
    第一比较器，其同相输入端连接于所述第三电容的一端，其反相输入端连接于所述高电平电压缓存单元的输出端，用于对所述电容端电压及所述高电平电压进行比较并根据比较结果得到所述高频开关信号；
    第二比较器，其同相输入端连接于所述第三电容的一端，其反相输入端通过第二加法器连接于所述低电平电压缓存单元的输出端及所述高电平电压缓存单元的输出端，用于对所述电容端电压及所述低电平电压与所述高电平电压之和进行比较，并在所述电容端电压不小于所述低电平电压与所述高电平电压之和时产生放电驱动信号；
    第三MOS管，其栅极端连接于所述第二比较器的输出端，其漏极端连接于所述第三电容的一端，其源极端连接于所述第三电容的另一端，用于在所述放电驱动信号有效时导通，以对所述第三电容进行放电操作，并在放电结束后开始下一周期，以此控制所述高频开关信号的周期；
    基准电压产生单元，连接于所述第一比较器的输出端，用于在所述高频开关信号的控制下，基于所述参考电压进行电容充放电以产生所述基准电压。
  10. 根据权利要求9所述的LED调光电路，其特征在于，所述基准电压产生单元包括：第一电阻、第二电阻、第五开关、第四电容及运算放大器，所述第一电阻的一端接入所述参考电压，所述第一电阻的另一端连接于所述第五开关的第一连接端及所述第二电阻的一端，所述第五开关的控制端连接于所述第一比较器的输出端，所述第五开关的第二连接端接地，所述第二电阻的另一端连接于所述第四电容的一端及所述运算放大器的同相输入端，所述第四电容的另一端接地，所述运算放大器的反相输入端连接于其输出端，并作为所述基准电压产生模块的输出端。
  11. 根据权利要求1所述的LED调光电路，其特征在于，所述调光信号产生模块包括：
    开关控制信号产生单元，用于在所述基准电压大于所述设定电压时产生模拟输出开关控制信号，在所述基准电压小于所述设定电压时，根据所述低频PWM信号的高电平计数及循环计数器对所述高频时钟信号的计数产生PWM输出开关控制信号；
    输出控制单元，连接于所述基准电压产生模块的输出端及所述开关控制信号产生单元的输出端，用于在所述基准电压大于所述设定电压时，在所述模拟输出开关控制信号的控制下输出所述基准电压作为调光信号；在所述基准电压小于所述设定电压时，在所述PWM输出开关控制信号的控制下输出新PWM信号作为所述调光信号。
  12. 根据权利要求11所述的LED调光电路，其特征在于，所述开关控制信号产生单元包括：
    寄存器，用于在所述低频PWM信号的下降沿到来时，锁存所述高电平电压产生模块中的高电平计数；
    循环计数器，其时钟输入端接入所述高频时钟信号，用于对所述高频时钟信号进行循环计数；
    异或门，其一输入端连接于所述寄存器的输出端，其另一输入端连接于所述循环计数器的输出端，用于在所述寄存器中锁存的高电平计数与所述循环计数器对所述高频时钟信号的计数一致时产生时钟触发信号；
    第三与门，其一输入端通过第一反相器连接于所述循环计数器的计数溢出端，其另一输入端连接于所述输出控制单元的控制信号输出端，用于在所述基准电压大于所述设定电压或所述循环计数器发生计数溢出时产生置位触发信号；
    D触发器，其时钟输入端连接于所述异或门的输出端，其数据端接入低电平，其置位端连接于所述第三与门的输出端，其输出端作为所述开关控制信号产生单元的输出端，用于在所述置位触发信号有效时产生开关导通信号，在所述时钟触发信号有效时产生开关断开信号。
  13. 根据权利要求11所述的LED调光电路，其特征在于，所述输出控制单元包括：第二反相器、第三比较器、第六开关、第七开关及第八开关，所述第三比较器的同相输入端连接于所述基准电压产生模块的输出端及所述第六开关的第一连接端，所述第三比较器的反相输入端连接于所述第七开关的第一连接端，并接入所述设定电压，所述第三比较器的输出端连接于所述第二反相器的输入端及所述第六开关的控制端，所述第二反相器的输出端连接于所述第七开关的控制端，并作为所述输出控制单元的控制信号输出端，所述第六开关的第二连接端连接于所述第七开关的第二连接端及所述第八开关的第一连接端，所述第八开关的控制端连接于所述开关控制信号产生单元的输出端，所述第八开关的第二连接端作为所述调光信号产生模块的调光信号输出端。
  14. 根据权利要求2所述的LED调光电路，其特征在于，所述基准电压产生模块包括：
    低电平电压缓存单元，连接于所述低电平电压产生模块的输出端，用于缓存所述低电 平电压；
    高电平电压缓存单元，连接于所述高电平电压产生模块的输出端，用于缓存所述高电平电压；
    恒流源及第三电容，所述恒流源的电流输入端接入电源电压，所述恒流源的电流输出端连接于所述第三电容的一端，所述第三电容的另一端接地，用于通过所述恒流源提供的恒定电流对所述第三电容充电，以在所述第三电容的一端产生电容端电压；
    第一比较器，其同相输入端连接于所述第三电容的一端，其反相输入端连接于所述高电平电压缓存单元的输出端，用于对所述电容端电压及所述高电平电压进行比较并根据比较结果得到所述高频开关信号；
    第二比较器，其同相输入端连接于所述第三电容的一端，其反相输入端通过第二加法器连接于所述低电平电压缓存单元的输出端及所述高电平电压缓存单元的输出端，用于对所述电容端电压及所述低电平电压与所述高电平电压之和进行比较，并在所述电容端电压不小于所述低电平电压与所述高电平电压之和时产生放电驱动信号；
    第三MOS管，其栅极端连接于所述第二比较器的输出端，其漏极端连接于所述第三电容的一端，其源极端连接于所述第三电容的另一端，用于在所述放电驱动信号有效时导通，以对所述第三电容进行放电操作，并在放电结束后开始下一周期，以此控制所述高频开关信号的周期；
    基准电压产生单元，连接于所述第一比较器的输出端，用于在所述高频开关信号的控制下，基于所述参考电压进行电容充放电以产生所述基准电压。
  15. 根据权利要求3所述的LED调光电路，其特征在于，所述基准电压产生模块包括：
    低电平电压缓存单元，连接于所述低电平电压产生模块的输出端，用于缓存所述低电平电压；
    高电平电压缓存单元，连接于所述高电平电压产生模块的输出端，用于缓存所述高电平电压；
    恒流源及第三电容，所述恒流源的电流输入端接入电源电压，所述恒流源的电流输出端连接于所述第三电容的一端，所述第三电容的另一端接地，用于通过所述恒流源提供的恒定电流对所述第三电容充电，以在所述第三电容的一端产生电容端电压；
    第一比较器，其同相输入端连接于所述第三电容的一端，其反相输入端连接于所述高电平电压缓存单元的输出端，用于对所述电容端电压及所述高电平电压进行比较并根据比较结果得到所述高频开关信号；
    第二比较器，其同相输入端连接于所述第三电容的一端，其反相输入端通过第二加法 器连接于所述低电平电压缓存单元的输出端及所述高电平电压缓存单元的输出端，用于对所述电容端电压及所述低电平电压与所述高电平电压之和进行比较，并在所述电容端电压不小于所述低电平电压与所述高电平电压之和时产生放电驱动信号；
    第三MOS管，其栅极端连接于所述第二比较器的输出端，其漏极端连接于所述第三电容的一端，其源极端连接于所述第三电容的另一端，用于在所述放电驱动信号有效时导通，以对所述第三电容进行放电操作，并在放电结束后开始下一周期，以此控制所述高频开关信号的周期；
    基准电压产生单元，连接于所述第一比较器的输出端，用于在所述高频开关信号的控制下，基于所述参考电压进行电容充放电以产生所述基准电压。
PCT/CN2021/132133 2020-12-30 2021-11-22 一种led调光电路 WO2022142856A1 (zh)

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