WO2022142699A1 - 支付方法、装置、电子设备和计算机可读存储介质 - Google Patents

支付方法、装置、电子设备和计算机可读存储介质 Download PDF

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Publication number
WO2022142699A1
WO2022142699A1 PCT/CN2021/127877 CN2021127877W WO2022142699A1 WO 2022142699 A1 WO2022142699 A1 WO 2022142699A1 CN 2021127877 W CN2021127877 W CN 2021127877W WO 2022142699 A1 WO2022142699 A1 WO 2022142699A1
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WIPO (PCT)
Prior art keywords
payment
processor
graphic code
instruction
wearable device
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PCT/CN2021/127877
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English (en)
French (fr)
Inventor
黄健辉
高金泽
周利宾
李丁义
李启明
苏伟
王梁
Original Assignee
Oppo广东移动通信有限公司
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Application filed by Oppo广东移动通信有限公司 filed Critical Oppo广东移动通信有限公司
Priority to EP21913443.4A priority Critical patent/EP4270287A4/en
Publication of WO2022142699A1 publication Critical patent/WO2022142699A1/zh
Priority to US18/344,407 priority patent/US20230342749A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q20/00—Payment architectures, schemes or protocols
    • G06Q20/30—Payment architectures, schemes or protocols characterised by the use of specific devices or networks
    • G06Q20/32—Payment architectures, schemes or protocols characterised by the use of specific devices or networks using wireless devices
    • G06Q20/321—Payment architectures, schemes or protocols characterised by the use of specific devices or networks using wireless devices using wearable devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q20/00—Payment architectures, schemes or protocols
    • G06Q20/30—Payment architectures, schemes or protocols characterised by the use of specific devices or networks
    • G06Q20/32—Payment architectures, schemes or protocols characterised by the use of specific devices or networks using wireless devices
    • G06Q20/327—Short range or proximity payments by means of M-devices
    • G06Q20/3274—Short range or proximity payments by means of M-devices using a pictured code, e.g. barcode or QR-code, being displayed on the M-device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q20/00—Payment architectures, schemes or protocols
    • G06Q20/38—Payment protocols; Details thereof
    • G06Q20/382—Payment protocols; Details thereof insuring higher security of transaction
    • G06Q20/3821—Electronic credentials
    • G06Q20/38215—Use of certificates or encrypted proofs of transaction rights
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q20/00—Payment architectures, schemes or protocols
    • G06Q20/38—Payment protocols; Details thereof
    • G06Q20/382—Payment protocols; Details thereof insuring higher security of transaction
    • G06Q20/3829—Payment protocols; Details thereof insuring higher security of transaction involving key management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q2220/00—Business processing using cryptography

Definitions

  • the present application relates to the field of communication technologies, and in particular, to a payment method, an apparatus, an electronic device and a computer-readable storage medium.
  • Smart wearable devices are becoming more and more popular, especially smart watches and bracelets have been loved by more and more young people. Smart wearable devices not only have the functions of traditional watches, such as clocks, but also have some functions of other electronic devices, such as payment functions.
  • the traditional payment method using smart wearable devices can only complete the payment through a system with strong performance, and cannot complete the payment under a system with low performance.
  • Various embodiments of the present application provide a payment method, apparatus, electronic device, and computer-readable storage medium.
  • a payment method applied to a wearable device comprising a first processor and a second processor, wherein the first processor is used to run a first system, and the second processor is used to run a first processor In a second system, when the wearable device is in the second system state, the power consumption of the second processor is lower than the power consumption of the first processor, and the method includes:
  • the payment is completed through the payment graphic code.
  • a payment device applied to a wearable device comprising a first processor and a second processor, wherein the first processor is used to run a first system, and the second processor is used to run a first processor In a second system, when the wearable device is in the second system state, the power consumption of the second processor is lower than the power consumption of the first processor, and the apparatus includes:
  • a payment instruction sending module configured to obtain a payment instruction and send the payment instruction to the first system
  • a payment graphic code receiving module configured to receive the payment graphic code returned by the first system according to the payment instruction
  • a payment module for completing payment through the payment graphic code.
  • An electronic device includes a memory and a processor, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the processor executes the operations of the above method.
  • a computer-readable storage medium having a computer program stored thereon, the computer program implementing the operations of the above method when executed by a processor.
  • the above payment method, device, electronic device and computer-readable storage medium are applied to wearable devices
  • the wearable device includes a first processor and a second processor, the first processor is used for running the first system, and the second processor is used for Run the second system, the wearable device is in the second system state, the power consumption of the second processor is lower than the power consumption of the first processor, obtain a payment instruction, and send the payment instruction to the first system; receive the first
  • the system returns the payment graphic code according to the payment instruction; the payment is completed through the payment graphic code, and the entire payment process is in the second system state, controlled by a low-power processor, and the payment graphic code is received and displayed through dual-core communication.
  • the high-performance system completes the payment, and uses the high-performance of the second system to complete the payment function that cannot be realized on the low-performance system.
  • a payment method applied to a wearable device comprising a first processor and a second processor, wherein the first processor is used to run a first system, and the second processor is used to run a first processor In a second system, when the wearable device is in the second system state, the power consumption of the second processor is lower than the power consumption of the first processor, and the method includes:
  • the payment graphic code is sent to the second system, and the payment graphic code is used to complete payment through the second system.
  • a payment device applied to a wearable device comprising a first processor and a second processor, wherein the first processor is used to run a first system, and the second processor is used to run a first processor In a second system, when the wearable device is in the second system state, the power consumption of the second processor is lower than the power consumption of the first processor, and the apparatus includes:
  • a payment graphic code generation module configured to receive a payment instruction sent by the second system, and generate a corresponding payment graphic code according to the payment instruction;
  • a sending module configured to send the payment graphic code to the second system, where the payment graphic code is used to complete payment through the second system.
  • An electronic device includes a memory and a processor, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the processor executes the operations of the above method.
  • a computer-readable storage medium having a computer program stored thereon, the computer program implementing the operations of the above method when executed by a processor.
  • the above payment method, device, electronic device and computer-readable storage medium are applied to a wearable device, and the wearable device includes a first processor and a second processor, wherein the first processor is used to run the first system, and the second processor
  • the wearable device is used to run the second system, the wearable device is in the second system state, the power consumption of the second processor is lower than the power consumption of the first processor, receives the payment instruction sent by the second system, and generates a corresponding payment instruction according to the payment instruction.
  • the payment graphic code is sent to the second system, and the payment graphic code is used to complete the payment through the second system.
  • the entire payment process is in the second system state, controlled by a low-power processor, receives and displays the payment graphic code through dual-core communication, and completes the payment through the low-performance system.
  • the payment function implemented on the performance system.
  • FIG. 1 is an application environment diagram of a payment method in one embodiment.
  • FIG. 2 is a flowchart of a payment method in one embodiment.
  • FIG. 3 is a flowchart of a payment method in another embodiment.
  • FIG. 4 is a flowchart of uplink data packet transmission in one embodiment.
  • FIG. 5 is a schematic diagram of the internal structure of a wearable device in one embodiment.
  • FIG. 6 is an interactive schematic diagram of a payment method in a specific embodiment.
  • FIG. 7 is a flowchart of a payment method in one embodiment.
  • FIG. 8 is a structural block diagram of a payment device in one embodiment.
  • FIG. 9 is a structural block diagram of a payment device in another embodiment.
  • FIG. 10 is a schematic diagram of the internal structure of an electronic device in one embodiment.
  • first, second, etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element.
  • a first processor may be referred to as a second processor, and a first processor may be referred to as a second processor, both being processors, but not the same processor.
  • FIG. 1 is a schematic diagram of an application environment of a payment method in one embodiment.
  • the application environment includes a wearable device, and the wearable device includes a first processor 110 and a second processor 120 .
  • Both the first processor 110 and the second processor 120 are microprocessors, wherein the first processor 110 may serve as a main processor, and the second processor 120 may serve as a co-processor.
  • the first processor 110 and the second processor 120 can be configured with corresponding microprocessors according to actual applications, for example, the first processor 110 is configured as a Qualcomm processor, and the second processor 120 is configured as an MCU processor, and the first step is not described here.
  • a processor 110 and a second processor 120 are defined.
  • the first processor 110 and the second processor 120 respectively integrate different operating systems, the first processor is used to run the first system, the second processor is used to run the second system, and the consumption of the first system integrated by the first processor 110 is The power consumption is higher than the power consumption of the second system integrated with the second processor 120 .
  • the first processor 110 may be a CPU (Central Process Unit, central processing unit) processor, corresponding to the first system may be an Android (Android) system;
  • the second processor 120 may be an MCU (Microcontroller Unit, micro-controller) unit) processor;
  • the corresponding second system may be an RTOS (Real Time Operating System, real-time operating system) system. That is, the wearable device is an electronic device with dual cores and dual systems.
  • the wearable device may be, but not limited to, a smart watch, a smart bracelet, and the like.
  • the wearable device can include multiple operating states.
  • the first system state means that the wearable device is controlled and operated by the first processor and is responsible for the logical operation of the data.
  • the second processor plays an auxiliary role and is used to collect data and provide it to the first processor.
  • the first system state it can mainly run the first system, and the second system is in a dormant state most of the time, and it can also run the first system and the second system at the same time, such as running Android at the same time.
  • the system and RTOS system can not only ensure the operation of the basic functions of the wearable device, but also ensure the operation of the extended functions of the wearable device, and provide more complete functions.
  • the second system state means that the wearable device mainly runs or only runs the second system, which is controlled by the second processor. For example, if the Android system is turned off and only the RTOS system is run, it can provide ultra-long standby capability with low power consumption.
  • the main frequency of the CPU can reach 1.2GHz (gigahertz), and the main frequency of the MCU is about 320MHz (megahertz), so the power consumption of the first processor is higher than that of the second processor, and the power consumption of the first system is higher than The power consumption of the second system.
  • FIG. 2 is a flowchart of a payment method in one embodiment.
  • the payment method in this embodiment running in the second system state and controlled by the second processor, includes the following operations:
  • a payment instruction is acquired, and the payment instruction is sent to the first system.
  • the wearable device is currently running in the second system state, and in this state, the second processor controls the data processing of the wearable device.
  • the wearable device can automatically switch from the first system state to the second system state according to the current operating state. For example, when it is detected that the current power level of the wearable device is lower than a preset threshold, it can automatically switch to the second system state. It can also receive the user's operation, control the wearable device to run in the second system state according to the user's operation, run in the second system state, and complete various functions through the low-performance system, which can save the power of the wearable device and increase the standby time.
  • the payment instruction is used to instruct the first system to generate a corresponding payment graphic code.
  • the payment instruction may carry a time stamp, so that the first system generates a payment graphic code that changes dynamically with time according to the time stamp.
  • Algorithms and forms for generating payment graphic codes are not limited, including but not limited to stacked/row-type 2D barcodes, matrix 2D barcodes, etc.
  • the user's operation is monitored through the second system, and when a payment operation is monitored, a payment instruction is generated according to the payment operation, and the payment instruction is an instruction generated when payment by a graphic code is required.
  • the wearable device is an electronic watch, and the payment instruction is generated by the user acting on the payment interface currently displayed by the electronic watch.
  • the payment operations include but are not limited to touch operations, gesture operations, and voice operations.
  • the payment graphic code is a graphic code carrying payment information, which may be in the form of a two-dimensional code or other forms, where the payment information includes but is not limited to payment account identification, payment user identity information, time stamp information, payment flow code, etc.
  • the algorithm for generating the payment graphic code is complex, and the processing capability of the second system is limited, and a payment instruction needs to be sent to the first system to generate the payment graphic code through the first system.
  • the communication between the first system and the second system can complete data exchange through the communication between the first processor and the second processor.
  • the first processor and the second processor can communicate through a predefined protocol.
  • the dual-core communication channel communicates between the Qualcomm chip and the MCU chip through the SPI (Serial Peripheral Interface, serial peripheral interface) protocol. Reliable data transmission.
  • the payment graphic code returned by the first system according to the payment instruction may be an unencrypted payment graphic code, or an encrypted payment graphic code generated after encryption.
  • the first system and the second system may predetermine an encryption algorithm, so that when the second system receives the encrypted payment graphic code, it can correctly decrypt to obtain the decrypted payment graphic code.
  • the encryption algorithms include but are not limited to symmetric encryption algorithms, asymmetric encryption algorithms, and the like.
  • the RSA encryption algorithm is used to ensure that the encrypted two-dimensional code data is not stolen, and the safe use of the two-dimensional code in the second system state is ensured, wherein the RSA encryption algorithm is an asymmetric encryption algorithm, which can be used directly In the case of passing the key, the decryption is completed, the security of the information is ensured, and the risk of being cracked caused by the direct passing of the key is avoided.
  • the private key is kept by one party for decryption, and the public key is sent to the other party to encrypt the information.
  • the second system parses the payment graphic code, renders it, and displays it on the corresponding payment interface, and obtains the information in the payment graphic code by scanning the code scanning device, thereby completing the payment.
  • the payment graphic code is transmitted to the payment application, the payment application is rendered by the parsing and rendering module, and the payment graphic code is displayed on the graphic code display interface of the payment application.
  • the subsequent display and payment process can be completed through the second system, and the payment function can also be completed in a low-performance system.
  • the payment method is applied to a wearable device
  • the wearable device includes a first processor and a second processor
  • the first processor is used to run the first system
  • the second processor is used to run the second system
  • the wearable When the device is in the second system state, the power consumption of the second processor is lower than the power consumption of the first processor, obtains the payment instruction, and sends the payment instruction to the first system; receives the return of the first system according to the payment instruction
  • the payment graphic code is completed; the payment is completed through the payment graphic code, and the entire payment process is in the second system state, controlled by a low-power processor, the payment graphic code is received and displayed through dual-core communication, and the payment is completed through the low-performance system.
  • the high performance of the second system accomplishes payment functions that could not otherwise be implemented on a low performance system.
  • the payment instruction is used to wake up the first system, and instruct the first system to generate a payment graphic code according to the payment instruction.
  • the method further includes: returning response information to the first system, where the response information is used to instruct the first system Enter sleep state.
  • the first system will be woken up by the payment instruction only when the payment graphic code is generated. After receiving the payment graphic code returned by the first system, the first system will be instructed to enter the sleep state by returning the response information to the first system.
  • the process of displaying and paying can be completed through the second system.
  • the first system is in a dormant state, which saves the power consumption of the wearable device.
  • the payment function can also be completed in a state of low power, and the first system can be controlled during the entire payment process. Dormant part of the time.
  • the first system is woken up only when the payment graphic code is generated, and the first system enters a dormant state after receiving the payment graphic code, thereby further reducing the power consumption of the first system, completing payment under low power consumption conditions, and improving resource utilization.
  • returning the response information to the first system includes: verifying the payment graphic code, and when the verification is passed, generating the response information.
  • the payment graphic code is verified, and when the verification is passed, the response information is returned to the first system.
  • the payment graphic code may include current verification information, the standard verification information is pre-stored in the second system, and the first system extracts the current verification information from the received payment graphic code, if the current verification information is not extracted, or the extracted If the current verification information does not match the standard verification information, it means that the verification of the payment graphic code fails. It may be damaged and a new payment graphic code needs to be requested again from the first system. If the verification is passed, a response message is generated, and the response message is used to notify the first system to receive a valid payment graphic code, thereby switching the first system to a sleep state to save power consumption.
  • a notification can be sent back to the first system again, so that the first system regenerates the payment graphic code and returns it to the second system again.
  • the invalid payment graphic code can be detected through verification, so as to return a re-send notification to the first system device, and the re-send notification can carry the current time , for the first system to regenerate the updated payment graphic code according to the current time.
  • the validity of the payment graphic code is improved, and payment failure is avoided. Only when the verification is passed, the response information is generated to further ensure the reliability of the payment graphic code.
  • a pre-payment processing request sent by the first system is received, where the pre-payment processing request is generated by the first system according to the user's payment authority instruction.
  • the user payment permission instruction is an instruction generated when the user supports graphic code payment when the wearable device is used, and can be generated by an operation acting on the permission setting interface of the wearable device in the first system state, wherein in the first system state Mainly run the first system, receive permission setting operations through the first system, and generate user payment permission instructions.
  • the user payment authorization instruction is generated by acting on the user payment authorization button in the pop-up box of the wearable device interface.
  • the first processor After the first system obtains the user's payment permission instruction, it means that the user agrees to the graphic code payment, then the first processor generates a pre-payment processing request and sends it to the second processor.
  • the pre-payment processing request is used to instruct the second processor to use encryption based on The algorithm generates the corresponding public key and private key, so as to ensure the secure transmission of the payment graphic code and the validity of the payment.
  • a corresponding public key and a private key are generated based on an encryption algorithm according to the pre-payment processing request, and the private key is stored in the second system.
  • the second system needs to generate the corresponding public key and private key based on an encryption algorithm in advance, and the public key is stored in the first system, so that the first system can use the public key after generating the payment graphic code to encrypt.
  • the private key is stored in the second system, so that the second system can decrypt the encrypted payment graphic code after receiving it.
  • the algorithm for generating the corresponding public key and private key can be customized.
  • the public key and the private key are generated by the RSA asymmetric encryption algorithm.
  • the RSA asymmetric encryption algorithm ensures that the co-prime number is as large as possible. To ensure high reliability of encryption.
  • the public key is sent to the first system for storage.
  • the second system sends the public key to the first system for storage through a dual-core communication protocol.
  • the distribution of the generated public key relies on reliable dual-core communication to achieve channel security, so that the overall reliability of the payment graphic code can be achieved.
  • the first system instructs the second system to generate a public key and a private key according to an encryption algorithm, and sends the public key to the first system through dual-core communication;
  • a system stores it, waits for the first system to send a graphic code payment instruction, and generates a public key and a private key in advance to ensure the security of subsequent payment graphic code transmission and improve the reliability of payment.
  • operation 204 includes: receiving the payment graphic code encrypted by the first system according to the public key; and decrypting the encrypted payment graphic code according to the private key to obtain the payment graphic code.
  • the second system decrypts the encrypted payment graphic code with the private key to obtain the decrypted payment graphic code, and only the private key can successfully decrypt the payment graphic code, thereby improving the security of the payment graphic code transmission.
  • the public key is transmitted to the first system through the second system, and the encrypted payment graphic code is transmitted to the second system through the first system. Even if both are intercepted by hackers, there is no danger because only the second system's Only the private key can decrypt the message, preventing the leakage of the message content.
  • operation 206 includes: transmitting the payment graphic code to a user interface; and displaying the payment graphic code through the user interface.
  • the second system sends the payment graphic code to the UI user interface for analysis and display, and completes the graphic code payment in the low power consumption mode.
  • the display screen of the wearable device is connected to the first processor and the second processor through MIPI (Mobile Industry Processor Interface), and the first processor or the second processor can output data are displayed.
  • MIPI Mobile Industry Processor Interface
  • the data parsing and display of the graphic code is completed by the low-power processor, that is, the second processor, which saves the power consumption of the wearable device.
  • the display of the payment graphic code in the second system state, can be performed through the low-performance system, which ensures the use of the payment function of the wearable device under the low-performance system, and reduces the power consumption of the wearable device.
  • the method further includes: detecting the running state of the wearable device; when the running state satisfies the low power consumption condition, switching the wearable device to run in the second system state, and controlling the first system to enter the sleep state.
  • the running state of the wearable device includes the device information state of the wearable device itself, and may also include the user information state collected by the wearable device.
  • the device information status includes power information status, device temperature status, device motion status, etc.
  • the power information status includes low power status and high power status
  • device temperature status includes normal temperature status and abnormal temperature status
  • device motion status includes equipment movement speed, Device rotation angle, etc.
  • the user information state includes at least one of the user's heart rate and attention information, such as eyeball position information, and cardiopulmonary data, but is not limited thereto.
  • Low power consumption conditions can be customized, such as low battery status, abnormal temperature status, equipment movement speed greater than the preset threshold status, heart rate lower than the preset threshold status status, etc., can be considered to meet the low power consumption conditions.
  • each state in the device information state and the user information state is formed into a state vector, and whether the low power consumption condition is satisfied is determined according to the state vector.
  • a standard state vector corresponding to the low power consumption condition is preset, and the wearable The current state vector formed by each state of the device is matched with the standard state vector, and if the matching is successful, it is considered that the low power consumption condition is satisfied. It can flexibly judge whether the wearable device satisfies the low power consumption condition according to various state settings of the wearable device, so as to switch the wearable device to the second system state to run, control the first system to enter the sleep state, and save power consumption.
  • the running state of the wearable device is automatically detected, and when the running state meets the low power consumption condition, the operation of the wearable device is automatically switched to the running state of the second system, and the first system is controlled to enter the sleep state, thereby saving power. consumption.
  • the uplink data packet is a data packet transmitted by the second processor to the first processor.
  • sending the uplink data packet to the first processor by the second processor includes the following operations:
  • a controlled interrupt signal is sent to the first processor, so that the first processor sends a master control response signal according to the controlled interrupt signal, and reads the uplink data packet from the second processor.
  • the uplink data packet may include at least one of an operation instruction and service data received or generated by the second processor.
  • the uplink data packet may be the payment instruction obtained by the second system, the response information generated after receiving the payment graphic code, and the corresponding public key generated based on the encryption algorithm.
  • the controlled interrupt signal is used to interrupt to indicate that the first processor has uplink data that needs to be transmitted to the first processor. Specifically, when detecting that there is an uplink data packet, the second processor of the electronic device can generate a corresponding controlled interrupt signal according to the uplink data packet, and after locking the data transmission interface, pass the generated controlled interrupt signal through the controlled interrupt The interface is sent to the first processor.
  • the first processor may read the uplink data packet from the second processor according to the controlled interrupt signal, and send a master response signal to the second processor.
  • the master response signal is used to indicate that the first processor is in a state of data transmission.
  • a reset controlled interrupt signal is sent to the first processor, so that the first processor, according to the reset controlled interrupt signal, after completing the reading of the uplink data packet, Reset the master response signal.
  • the second processor may reset the controlled interrupt signal after the transmission of the uplink data packet is completed.
  • the first processor may receive the reset controlled interrupt signal.
  • the reset controlled interrupt signal may indicate that the second processor has completed the transfer of data.
  • the first processor may reset the master response signal when acquiring the reset controlled interrupt signal.
  • the first processor can read the data packet when receiving the controlled interrupt signal, and reset the master control response according to the controlled interrupt signal reset by the second processor after the data reading is completed.
  • the reset master response signal means that a single data transmission is completed, which can reduce the delay of processor communication and improve the efficiency of processor communication.
  • the wearable device includes a first processor 310 corresponding to the first system and a second processor 320 corresponding to the second system, and the wearable device may include a heart rate sensor 321, an acceleration + gyroscope 322, an atmospheric pressure sensor 323, a touch sensor 324, magnetic sensor 325, micro differential pressure sensor 326 and other sensors.
  • the second processor 320 may be connected with a sensor included in the wearable device for acquiring data collected by the sensor.
  • the second processor 320 can also be connected with a GPS (Global Positioning System, global positioning system) module 327 for acquiring the positioning data received by the GPS antenna; and connected with a debugging (DEBUG) module 328 for outputting the debugging of the wearable device data.
  • the first processor 310 and the second processor 320 are connected through SPI (Serial Peripheral Interface, serial peripheral interface), so that the first system and the second system can transmit communication data through the SPI bus.
  • the display screen 330 is connected to the first processor 310 and the second processor 320 through MIPI (Mobile Industry Processor Interface), and can display the data output by the first processor 310 or the second processor 320.
  • the first processor 310 also includes a sensor hub driver, which can be used to drive data collection and processing of each sensor.
  • the first processor 310 is a Qualcomm chip, on which the Android system runs
  • the second processor 320 is an MCU chip, on which the RTOS system runs
  • the payment method includes the following operations:
  • the Android system sends a pre-payment processing request to the MCU.
  • the MCU uses the RSA encryption algorithm to generate the public key and private key, sends the public key to the Android system through the dual-core communication SPI protocol, and saves the private key locally for decrypting the QR code display.
  • the Android system stores the public key after receiving it, and waits for the MCU to send the QR code payment instruction.
  • the MCU will monitor the user's payment action in a low-power state. If it monitors the QR code payment request, it will send the payment instruction to the Android system to wake up the Android system.
  • the Android system After the Android system receives the payment instruction, it wakes up the Android system to generate a QR code, and encrypts the generated QR code with the pre-stored public key.
  • the Android system transmits the encrypted QR code to the MCU through the dual-core communication SPI protocol.
  • the MCU After the MCU receives the data of the payment instruction response, it decrypts the QR code data through its own private key, and returns the response information to the Android system, which instructs the Android system to enter the sleep state.
  • the MCU sends the QR code data to the UI for analysis and display, and completes the QR code payment under the low-performance system.
  • the dual-core communication channel uses the SPI protocol to perform reliable data transmission between the Qualcomm chip and the MCU chip, and the RSA encryption algorithm is used to ensure that the encrypted QR code data is not stolen, and to ensure that the data is not stolen in a low-power mode and a low-performance system.
  • the safe use of QR code borrowing the high-performance multi-function support of the Android system, the MCU receives the QR code data sent by the Android system, and completes the QR code payment safely and reliably under low power consumption conditions
  • a payment method is provided, applied to a wearable device, the wearable device includes a first processor and a second processor, wherein the first processor is used for The first system is run, the second processor is used to run the second system, the wearable device is in the second system state, and the power consumption of the second processor is lower than that of the first processor. consumption, including the following operations:
  • a payment instruction sent by the second system is received, and a corresponding payment graphic code is generated according to the payment instruction.
  • a payment graphic code is sent to the second system, and the payment graphic code is used to complete payment through the second system.
  • the wearable device includes a first processor and a second processor, wherein the first processor is used to run the first system, the second processor is used to run the second system, and the wearable device is in the second system state
  • the power consumption of the second processor is lower than the power consumption of the first processor, receives the payment instruction sent by the second system, and generates a corresponding payment graphic code according to the payment instruction; sends the payment graphic code to the second system, and pays The graphic code is used to complete the payment through the second system.
  • the entire payment process is in the second system state, controlled by a low-power processor, receives and displays the payment graphic code through dual-core communication, and completes the payment through the low-performance system.
  • the payment function implemented on the performance system.
  • operation 502 includes: entering a working state according to the payment instruction. After operation 504, the method further includes: receiving response information returned by the second system, and entering a sleep state according to the response information.
  • the method further includes: when in a working state, acquiring a user payment authority instruction; sending a pre-payment processing request to the second system according to the user's payment authority instruction, where the pre-payment processing request is used to instruct the second system to base on an encryption algorithm Generate the corresponding public key and private key, and store the private key in the second system; receive the public key returned by the second system, and store the public key.
  • operation 502 includes: performing encryption according to the public key to generate an encrypted payment graphic code.
  • Operation 504 includes sending the encrypted payment graphic code to the second system.
  • the downlink data packet is a data packet transmitted by the first processor to the second processor
  • the first processor sending the downlink data packet to the second processor includes the following operations: when detecting that there is downlink data
  • the first processor sends a master control interrupt signal to the second processor; the first processor receives the controlled response signal returned by the second processor according to the master control interrupt signal; the first processor according to the controlled response signal Send the downlink data packet to the second processor, and reset the main control interrupt signal after the transmission is completed; the reset main control interrupt signal is used to instruct the second processor to reset the controlled interrupt after completing the processing of the downlink data packet response signal.
  • the downlink data packet may contain at least one of an operation instruction and service data received or generated by the first processor, such as a payment graphic code.
  • the operation instruction may be used to instruct the second processor to perform a corresponding service operation after being transmitted to the second processor.
  • the service data is used to provide data support for the second processor to perform a service operation corresponding to the service data after being transmitted to the second processor.
  • the master control interrupt signal is used to interrupt to indicate that the second processor has downlink data that needs to be transmitted to the second processor. Specifically, after detecting a downlink data packet, the first processor of the electronic device can generate a corresponding master control interrupt signal according to the downlink data packet, and send the generated master control interrupt signal to the second processor through the master control interrupt interface .
  • the controlled response signal is used to indicate that the second processor is ready to receive the downlink data packet. Data transmission between the first processor and the second processor needs to be implemented through a data transmission interface.
  • the reset master interrupt signal may indicate that the first processor has completed the transmission of data.
  • the first processor may reset the master control interrupt signal after the downlink data packet is sent, so as to notify the second processor that the downlink data packet has been sent.
  • the second processor receives the downlink data packet and can process the downlink data packet, and the second processor can reset the controlled response signal when the reset master interrupt signal is obtained and the processing of the downlink data packet is completed.
  • the second processor may set the controlled acknowledgement interface to a low state.
  • the reset controlled response signal is used to notify the first processor that the second processor has finished processing the downlink data packets, and the first processor can send the master control to the second processor again according to the reset controlled response signal. Interrupt signal for data transfer.
  • the first processor may send a master control interrupt signal to the second processor, and receive a controlled response signal returned by the second processor according to the master control interrupt signal.
  • the control response signal can send the downlink data packet to the second processor, and reset the main control interrupt signal after the transmission is completed.
  • the reset main control interrupt signal can instruct the second processor to complete the processing of the downlink data packet. Reset the controlled answer signal. That is, the data packet can be transmitted when the controlled response signal is received, and the main control interrupt signal can be reset after the transmission is completed.
  • the reset main control interrupt signal means that the single data transmission is completed, and no controlled interrupt needs to be introduced.
  • the second confirmation of the signal and the master response signal can reduce the delay of processor communication and improve the efficiency of processor communication.
  • FIG. 8 is a structural block diagram of a payment device according to an embodiment.
  • a payment apparatus 600 is provided, which is applied to a wearable device, and the wearable device includes a first processor and a second processor, wherein the first processor is used to run the first system, The second processor is configured to run a second system, the wearable device is in the second system state, and the power consumption of the second processor is lower than the power consumption of the first processor;
  • the apparatus includes : payment instruction sending module 602, payment graphic code receiving module 604, response module 606 and payment module 608, wherein:
  • the payment instruction sending module 602 is used for acquiring the payment instruction and sending the payment instruction to the first system.
  • the payment graphic code receiving module 604 is configured to receive the payment graphic code returned by the first system according to the payment instruction.
  • the payment module 606 is used to complete the payment through the payment graphic code.
  • the above payment device completes the payment through the payment graphic code, and the entire payment process is in the second system state, controlled by a low-power processor, receives and displays the payment graphic code through dual-core communication, and completes the payment through the low-performance system.
  • the high performance of the second system completes the payment function that cannot be realized on the low performance system.
  • the payment instruction is used to wake up the first system and instruct the first system to generate a payment graphic code according to the payment instruction
  • the device further includes:
  • the response module 608 is configured to return response information to the first system, where the response information is used to instruct the first system to enter a sleep state.
  • the first system is woken up only when the payment graphic code is generated, and the first system enters a dormant state after receiving the payment graphic code, thereby further reducing the power consumption of the first system, completing payment under low power consumption conditions, and improving resource utilization.
  • the response module 608 is further configured to verify the payment graphic code, and when the verification is passed, generate response information.
  • the validity of the payment graphic code is improved, and payment failure is avoided. Only when the verification is passed, the response information is generated to further ensure the reliability of the payment graphic code.
  • the apparatus further includes:
  • the pre-processing module 610 is configured to receive a pre-payment processing request sent by the first system, the pre-payment processing request is generated by the first system according to the user's payment authority instruction; key and private key, store the private key in the second system, and send the public key to the first system for storage.
  • the first system instructs the second system to generate a public key and a private key according to an encryption algorithm, and sends the public key to the first system through dual-core communication; After the system receives the public key, it stores it, waits for the first system to send an instruction for graphic code payment, and generates the public key and private key in advance to ensure the security of subsequent payment graphic code transmission, and to improve the reliability of payment.
  • the payment graphic code receiving module 604 is further configured to receive the payment graphic code encrypted by the first system according to the public key; decrypt the encrypted payment graphic code according to the private key to obtain the payment graphic code.
  • the public key is transmitted to the first system through the second system, and the encrypted payment graphic code is transmitted to the second system through the first system. Even if they are all intercepted by hackers, there is no danger, because only the private data of the second system is transmitted. Only the key can decrypt the message, preventing the leakage of the message content.
  • the payment module 606 is further configured to transmit the payment graphic code to the user interface; the payment graphic code is displayed through the user interface.
  • the display of the payment graphic code in the second system state, can be performed through the low-performance system, which ensures the use of the payment function of the wearable device in the low-performance system and reduces the power consumption of the wearable device.
  • the apparatus further includes:
  • the mode switching module 612 is configured to detect the running state of the wearable device, and when the running state meets the low power consumption condition, switch the wearable device to run in the second system state, and control the first system to enter the sleep state.
  • the running state of the wearable device is automatically detected, and when the running state meets the low power consumption condition, the operation of the wearable device is automatically switched to the running state of the second system, and the first system is controlled to enter the sleep state, thereby saving power. consumption.
  • the uplink data packet is a data packet transmitted by the second processor to the first processor, and the apparatus further includes:
  • an uplink data communication module 614 configured to send a controlled interrupt signal to the first processor, so that the first processor sends a master control response signal according to the controlled interrupt signal, and reads an uplink data packet from the second processor; After the transmission of the uplink data packet is completed, a reset controlled interrupt signal is sent to the first processor, so that the first processor, according to the reset controlled interrupt signal, after completing the reading of the uplink data packet, restarts the Set the master response signal
  • the first processor may read the data packet when receiving the controlled interrupt signal, and reset the master control response according to the controlled interrupt signal reset by the second processor after the data reading is completed
  • the reset master response signal means that a single data transmission is completed, which can reduce the delay of processor communication and improve the efficiency of processor communication.
  • FIG. 9 is a structural block diagram of a payment device according to an embodiment.
  • a payment apparatus 700 is provided, which is applied to a wearable device.
  • the wearable device includes a first processor and a second processor, wherein the first processor is used for running the first system, and the second processor is used for running the first system.
  • the wearable device When running the second system, the wearable device is in the second system state, and the power consumption of the second processor is lower than the power consumption of the first processor; the device includes: a payment graphic code generation module 702, and a sending module 704, wherein:
  • the payment graphic code generating module 702 is configured to receive a payment instruction sent by the second system, and generate a corresponding payment graphic code according to the payment instruction.
  • a sending module 704, configured to send the payment graphic code to the second system, where the payment graphic code is used to complete payment through the second system.
  • the entire payment process is in the second system state, controlled by a low-power processor, receives and displays the payment graphic code through dual-core communication, and completes the payment through the low-performance system, using the high-performance of the second system.
  • a low-power processor receives and displays the payment graphic code through dual-core communication, and completes the payment through the low-performance system, using the high-performance of the second system.
  • the payment graphic code generation module 702 is further configured to enter the working state according to the payment instruction, and the apparatus further includes: a sleep module 706, configured to receive the response information returned by the second system, and enter the sleep state according to the response information.
  • the first system is woken up only when the payment graphic code is generated, and the first system enters a dormant state after receiving the payment graphic code, thereby further reducing the power consumption of the first system, completing payment under low power consumption conditions, and improving resource utilization.
  • the apparatus further includes:
  • the pre-processing module 708 is used to obtain a user payment permission instruction when in a working state; send a pre-payment processing request to the second system according to the user's payment permission instruction, and the pre-payment processing request is used to instruct the second system to generate an encryption algorithm based on
  • the corresponding public key and private key are stored in the second system; the public key is received by the second system, and the public key is stored.
  • the first system instructs the second system to generate a public key and a private key according to an encryption algorithm, and sends the public key to the first system through dual-core communication; After the system receives the public key, it stores it, waits for the first system to send an instruction for graphic code payment, and generates the public key and private key in advance to ensure the security of subsequent payment graphic code transmission, and to improve the reliability of payment.
  • the payment graphic code generating module 702 is further configured to perform encryption according to the public key to generate an encrypted payment graphic code.
  • the sending module 704 is further configured to send the encrypted payment graphic code to the second system.
  • the public key is transmitted to the first system through the second system, and the encrypted payment graphic code is transmitted to the second system through the first system. Even if they are all intercepted by hackers, there is no danger, because only the private data of the second system is transmitted. Only the key can decrypt the message, preventing the leakage of the message content.
  • the downlink data packet is a data packet transmitted by the first processor to the second processor, and the apparatus further includes:
  • the downlink data communication module 710 is configured to send the main control interrupt signal to the second processor through the first processor when it is detected that there is a downlink data packet; the first processor receives the received message returned by the second processor according to the main control interrupt signal. control response signal; the first processor sends the downlink data packet to the second processor according to the controlled response signal, and resets the master control interrupt signal after the transmission is completed; the reset master control interrupt signal is used to instruct the second processor After the processing of the downstream data packet is completed, the controlled response signal is reset.
  • the first processor may send a master control interrupt signal to the second processor, and receive a controlled response signal returned by the second processor according to the master control interrupt signal.
  • the control response signal can send the downlink data packet to the second processor, and reset the main control interrupt signal after the transmission is completed.
  • the reset main control interrupt signal can instruct the second processor to complete the processing of the downlink data packet. Reset the controlled answer signal. That is, the data packet can be transmitted when the controlled response signal is received, and the main control interrupt signal can be reset after the transmission is completed.
  • the reset main control interrupt signal means that the single data transmission is completed, and no controlled interrupt needs to be introduced.
  • the second confirmation of the signal and the master response signal can reduce the delay of processor communication and improve the efficiency of processor communication.
  • each module in the above payment device is only used for illustration. In other embodiments, the payment device may be divided into different modules as required to complete all or part of the functions of the above payment device.
  • Each module in the above payment device can be implemented in whole or in part by software, hardware and combinations thereof.
  • the above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, and can also be stored in the memory in the computer device in the form of software, so that the processor can call and execute the corresponding operations of the above-mentioned modules.
  • FIG. 10 is a schematic diagram of the internal structure of an electronic device in one embodiment.
  • the electronic device includes a processor and a memory connected by a system bus.
  • the processor is used to provide computing and control capabilities to support the operation of the entire electronic device.
  • the memory may include non-volatile storage media and internal memory.
  • the nonvolatile storage medium stores an operating system and a computer program.
  • the computer program can be executed by the processor to implement a payment method provided by the following embodiments.
  • Internal memory provides a cached execution environment for operating system computer programs in non-volatile storage media.
  • the electronic device may be various wearable devices.
  • each module in the payment device provided in the embodiments of the present application may be in the form of a computer program.
  • the computer program can be run on a terminal or server.
  • the program modules constituted by the computer program can be stored on the memory of the electronic device.
  • the operations of the methods described in the embodiments of the present application are implemented.
  • Embodiments of the present application also provide a computer-readable storage medium.
  • One or more non-transitory computer-readable storage media containing computer-executable instructions that, when executed by one or more processors, cause the processors to perform the operations of the payment method.
  • Nonvolatile memory may include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory.
  • Volatile memory may include random access memory (RAM), which acts as external cache memory.
  • RAM is available in various forms such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous Link (Synchlink) DRAM (SLDRAM), Memory Bus (Rambus) Direct RAM (RDRAM), Direct Memory Bus Dynamic RAM (DRDRAM), and Memory Bus Dynamic RAM (RDRAM).
  • SRAM static RAM
  • DRAM dynamic RAM
  • SDRAM synchronous DRAM
  • DDR SDRAM double data rate SDRAM
  • ESDRAM enhanced SDRAM
  • SLDRAM synchronous Link (Synchlink) DRAM
  • SLDRAM synchronous Link (Synchlink) DRAM
  • Memory Bus Radbus
  • RDRAM Direct RAM
  • DRAM Direct Memory Bus Dynamic RAM
  • RDRAM Memory Bus Dynamic RAM

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Abstract

一种支付方法，包括：获取支付指令，将所述支付指令发送至所述第一系统；接收所述第一系统根据所述支付指令返回的支付图形码；通过低性能的系统完成支付。

Description

支付方法、装置、电子设备和计算机可读存储介质
相关申请的交叉引用
本申请要求于2020年12月30日提交中国专利局、申请号为202011630586.1、发明名称为“支付方法、装置、电子设备和计算机可读存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术领域，特别是涉及一种支付方法、装置、电子设备和计算机可读存储介质。
背景技术
智能穿戴设备越来越普及,特别是智能手表和手环已经受到越来越多年轻人的喜爱。智能穿戴设备不仅拥有传统手表的功能，例如时钟等，也拥有其他电子设备的一些功能，例如支付功能等。
然而，传统的采用智能穿戴设备进行支付的方法，只能通过性能较强的系统完成支付，无法在低性能的系统下完成支付。
发明内容
根据本申请的各种实施例提供了一种支付方法、装置、电子设备、计算机可读存储介质。
一种支付方法，应用于可穿戴设备，所述可穿戴设备包括第一处理器和第二处理器，其中，所述第一处理器用于运行第一系统，所述第二处理器用于运行第二系统，所述可穿戴设备处于所述第二系统状态下，所述第二处理器的功耗低于所述第一处理器的功耗，所述方法包括：
获取支付指令，将所述支付指令发送至所述第一系统；
接收所述第一系统根据所述支付指令返回的支付图形码；
通过所述支付图形码完成支付。
一种支付装置，应用于可穿戴设备，所述可穿戴设备包括第一处理器和第二处理器，其中，所述第一处理器用于运行第一系统，所述第二处理器用于运行第二系统，所述可穿戴设备处于所述第二系统状态下，所述第二处理器的功耗低于所述第一处理器的功耗，所述装置包括：
支付指令发送模块，用于获取支付指令，将所述支付指令发送至所述第一系统；
支付图形码接收模块，用于接收所述第一系统根据所述支付指令返回的支付图形码；
支付模块，用于通过所述支付图形码完成支付。
一种电子设备，包括存储器及处理器，所述存储器中储存有计算机程序，所述计算机程序被所述处理器执行时，使得所述处理器执行如上述方法的操作。
一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现如上述方法的操作。
上述支付方法、装置、电子设备和计算机可读存储介质，应用于可穿戴设备，可穿戴设备包括第一处理器和第二处理器，第一处理器用于运行第一系统，第二处理器用于运行第二系统，可穿戴设备处于第二系统状态下，第二处理器的功耗低于所述第一处理器的功耗，获取支付指令，将支付指令发送至第一系统；接收第一系统根据所述支付指令返回的支付图形码；通过支付图形码完成支付，整个支付过程处于第二系统状态下，由低功耗的处理器控制，通过双核通信接收支付图形码并展示，通过低性能的系统完成支付，借第二系统的高性能完成本不可以在低性能的系统上实现的支付功能。
一种支付方法，应用于可穿戴设备，所述可穿戴设备包括第一处理器和第二处理器，其中，所述第一处理器用于运行第一系统，所述第二处理器用于运行第二系统，所述可穿戴设备处于所述第二系统状态下，所述第二处理器的功耗低于所述第一处理器的功耗，所述方法包括：
接收所述第二系统发送的支付指令，根据所述支付指令生成对应的支付图形码；
向所述第二系统发送所述支付图形码，所述支付图形码用于通过所述第二系统完成支付。
一种支付装置，应用于可穿戴设备，所述可穿戴设备包括第一处理器和第二处理器，其中，所述第一处理器用于运行第一系统，所述第二处理器用于运行第二系统，所述可穿戴设备处于所述第二系统状态下，所述第二处理器的功耗低于所述第一处理器的功耗，所述装置包括：
支付图形码生成模块，用于接收所述第二系统发送的支付指令，根据所述支付指令生成对应的支付图形码；
发送模块，用于向所述第二系统发送所述支付图形码，所述支付图形码用于通过所述第二系统完成支付。
一种电子设备，包括存储器及处理器，所述存储器中储存有计算机程序，所述计算机程序被所述处理器执行时，使得所述处理器执行如上述方法的操作。
一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现如上述方法的操作。
上述支付方法、装置、电子设备和计算机可读存储介质，应用于可穿戴设备，可穿戴设备包括第一处理器和第二处理器，其中，第一处理器用于运行第一系统，第二处理器用于运行第二系统，可穿戴设备处于第二系统状态下，第二处理器的功耗低于所述第一处理器的功耗，接收第二系统发送的支付指令，根据支付指令生成对应的支付图形码；向第二系统发送支付图形码，支付图形码用于通过第二系统完成支付。整个支付过程处于第二系统状态下，由低功耗的处理器控制，通过双核通信接收支付图形码并展示，通过低性能的系统完成支付，借第二系统的高性能完成本不可以在低性能的系统上实现的支付功能。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一个实施例中支付方法的应用环境图。
图2为一个实施例中支付方法的流程图。
图3为另一个实施例中的支付方法的流程图。
图4为一个实施例中上行数据包传输的流程图。
图5为一个实施例中可穿戴设备的内部结构示意图。
图6为一个具体的实施例中支付方法的交互示意图。
图7为一个实施例中支付方法的流程图。
图8为一个实施例中支付装置的结构框图。
图9为另一个实施例中支付装置的结构框图。
图10为一个实施例中电子设备的内部结构示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
可以理解，本申请所使用的术语“第一”、“第二”等可在本文中用于描述各种元件，但这些元件不受这些术语限制。这些术语仅用于将第一个元件与另一个元件区分。举例来说，在不脱离本申请的范围的情况下，可以将第一处理器称为第二处理器，第一处理器称为第二处理器，两者都是处理器，但其不是同一处理器。
图1为一个实施例中支付方法的应用环境示意图。如图1所示，该应用环境包括可穿戴设备，可穿戴设备包括第一处理器110和第二处理器120。第一处理器110和第二处理器120均为微处理器，其中，第一处理器110可以作为主处理器，第二处理器120可以作为协处理器。第一处理器110和第二处理器120可以根据实际应用配置相应的微处理器，如第一处理器110配置为高通处理器，第二处理器120配置为MCU处理器，在此不做第一处理器110和第二处理器120进行限定。第一处理器110和第二处理120分别集成了不同的操作系统，第一处理器用于运行第一系统，第二处理器用于运行第二系统，第一处理器110集成的第一系统的耗电量高于第二处理器120集成的第二系统的耗电量。例如，以第一处理器110可以是CPU(Central Process Unit，中央处理器)处理器，对应于第一系统可以是安卓(Android)系统；第二处理器120可以是MCU(Microcontroller Unit，微控制单元)处理器；对应的第二系统可以是RTOS(Real Time Operating System，实时操作系统)系统。即可穿戴设备为双核双系统的电子设备。
其中，可穿戴设备可以但不限于是智能手表、智能手环等。可穿戴设备可包括多种运行状态，第一系统状态是指可穿戴设备由第一处理器控制运行，负责数据的逻辑运算，第二处理器起辅助作用，用于采集数据提供给第一处理器，如采集用户的状态数据等，在第一系统状态下，可主要运行第一系统，第二系统大部分时间处于休眠状态，也可同时运行第一系统和第二系统，如同时运行Android系统和RTOS系统，不仅能够保证可穿戴设备的基础功能的运行，还能保证可穿戴设备的扩展功能的运行，提供较完备的功能。第二系统状态是指可穿戴设备主要运行或只运行第二系统，由第二处理器控制运行，如关闭Android系统，只运行RTOS系统，可以提供低功耗的超长待机能力。其中，CPU的主频可达到1.2GHz(吉赫兹)，而MCU的主频约320MHz(兆赫兹)，因此第一处理器的功耗高于第二处理器，第一系统的功耗高于第二系统的功耗。
图2为一个实施例中支付方法的流程图。本实施例中的支付方法，运行于第二系统状态下，由第二处理器控制，包括以下操作：
操作202，获取支付指令，将支付指令发送至所述第一系统。
其中，可穿戴设备当前运行在第二系统状态下，此状态下由第二处理器控制可穿戴设备的数据处理。可穿戴设备可以根据当前运行状态自动由第一系统状态切换至第二系统状态，如当检测到可穿戴设备当前电量低于预设阈值时，自动切换至第二系统状态。也可以接收用户的操作，根据用户操作控制可穿戴设备运行于第二系统状态，在第二系统状态下运行，通过低性能的系统完成各种功能，可节省可穿戴设备的电量，增加待机时长。支付指令用于指示第一系统生成对应的支付图形码。在一个实施例中，支付指令中可携带时间戳，以使第一系统根据时间戳生成随时间动态变化的支付图形码。生成支付图形码的算法和形式不限，包括但不限于堆叠式/行排式二维条码、矩阵式二维条码等。
具体地，通过第二系统监听用户的操作，当监听到支付操作时，根据支付操作生成支付指令，该支付指令是需要通过图形码支付时生成的指令。在一个实施例中，可穿戴设备为电子手表，通过用户作用于电子手表当前显示的支付界面的操作，生成支付指令。其中支付操作包括但不限于触摸操作、手势操作、语音操作等。
操作204，接收第一系统根据支付指令返回的支付图形码。
其中，支付图形码是携带支付信息的图形码，可以为二维码的形式或其它形式，其中支付信息包括但不限于支付帐户标识、支付用户身份信息、时间戳信息、支付流水编码等。
由于支付的完成需要生成支付图形码，生成支付图形码的算法复杂，第二系统的处理能力有限，需要向第一系统发送支付指令，通过第一系统生成支付图形码。其中，第一系统和 第二系统之间的通信，可通过第一处理器与第二处理器的通信完成数据交换。第一处理器与第二处理器可通过预先定义的协议进行通信，在一个实施例中，双核通信通道通过SPI(Serial Peripheral Interface，串行外设接口)协议进行高通芯片和MCU芯片之间的可靠数据传输。
具体地，第一系统根据支付指令返回的支付图形码可以是未加密的支付图形码，也可以是经过加密后生成的加密的支付图形码。第一系统和第二系统可预先约定加密算法，使得第二系统在接收到加密的支付图形码时，进行正确解密得到解密的支付图形码。其中加密算法包括但不限于对称加密算法，非对称加密算法等。
在一个实施例中，采用RSA加密算法保证加密的二维码数据不被窃取，保证第二系统状态下二维码的安全使用，其中RSA加密算法是一种非对称加密算法，可以在不直接传递密钥的情况下，完成解密，确保信息的安全性，避免了直接传递密钥所造成的被破解的风险，是由一对密钥来进行加解密的过程，分别称为公钥和私钥，私钥由一方保存用于解密，公钥用于发送至另一方对信息进行加密。
操作206，通过支付图形码完成支付。
具体地，第二系统对支付图形码进行解析，进行渲染并展示在对应的支付界面上，通过扫码设备的扫描获取支付图形码中的信息，从而完成支付。在一个实施例中，将支付图形码传递至支付应用，支付应用通过解析渲染模块进行渲染，并在支付应用的图形码展示界面展示支付图形码。后续展示支付的过程通过第二系统就可完成，在低性能的系统下也能完成支付功能。
在本实施例中，支付方法应用于可穿戴设备，可穿戴设备包括第一处理器和第二处理器，第一处理器用于运行第一系统，第二处理器用于运行第二系统，可穿戴设备处于第二系统状态下，第二处理器的功耗低于所述第一处理器的功耗，获取支付指令，将支付指令发送至第一系统；接收第一系统根据所述支付指令返回的支付图形码；通过支付图形码完成支付，整个支付过程处于第二系统状态下，由低功耗的处理器控制，通过双核通信接收支付图形码并展示，通过低性能的系统完成支付，借第二系统的高性能完成本不可以在低性能的系统上实现的支付功能。
在一个实施例中，支付指令用于唤醒第一系统，指示第一系统根据支付指令生成支付图形码，操作204之后，还包括：向第一系统返回应答信息，应答信息用于指示第一系统进入休眠状态。
具体地，只有生成支付图形码时才会通过支付指令唤醒第一系统，当接收到第一系统返回的支付图形码后，通过向第一系统返回应答信息，指示第一系统进入休眠状态，后续展示支付的过程通过第二系统就可完成，第一系统处于休眠状态，节省了可穿戴设备的功耗，在电量较低的状态下也能完成支付功能，控制整个支付过程中第一系统大部分时间处于休眠状态。
本实施例中，只有生成支付图形码时唤醒第一系统，接收到支付图形码后第一系统进入休眠状态，从而进一步减少第一系统的功耗消耗，在低功耗条件下完成支付，提高了资源利用率。
在一个实施例中，向第一系统返回应答信息包括：对支付图形码进行验证，当验证通过时，生成应答信息。
具体地，对支付图形码进行验证，当验证通过时，向第一系统返回应答信息。支付图形码中可包括当前验证信息，在第二系统中预先存储了标准验证信息，第一系统从接收到的支付图形码中提取当前验证信息，如果未提取到当前验证信息，或提取得到的当前验证信息与标准验证信息不匹配，则说明支付图形码验证未通过。可能被损坏，需要向第一系统再次请求新的支付图形码。如果验证通过，则生成应答信息，应答信息用于通知第一系统收到有效的支付图形码，从而将第一系统切换至休眠状态，节省功耗。
当验证不通过时，可以向第一系统返回重新发送通知，以使第一系统重新生成支付图形码再次返回至第二系统。当支付图形码在传输过程中被损坏，或生成的支付图形码错误时， 可通过验证检测出无效的支付图形码，从而向第一系统器返回重新发送通知，重新发送通知中可携带当前时间，用于第一系统根据当前时间重新生成更新的支付图形码。
本实施例中，通过验证操作，提高了支付图形码的有效性，避免支付失败。只有验证通过时，才生成应答信息进一步保证了支付图形码的可靠性。
在一个实施例中，如图3所示，操作202之前，还包括：
操作302，接收第一系统发送的支付前处理请求，支付前处理请求是第一系统根据用户支付权限指令生成的。
其中，用户支付权限指令是当用户支持图形码支付在可穿戴设备使用时生成的指令，可在第一系统状态下通过作用于可穿戴设备的权限设置界面的操作生成，其中第一系统状态下主要运行第一系统，通过第一系统接收权限设置操作，生成用户支付权限指令。在一个实施例中，通过作用于可穿戴设备界面的弹出框中用户支付授权按键的操作生成用户支付权限指令。
当第一系统获取用户支付权限指令后，表示用户同意图形码支付，则第一处理器生成支付前处理请求，并发送至第二处理器，支付前处理请求用于指示第二处理器基于加密算法生成对应的公钥和私钥，从而保证支付图形码的安全传输，保证支付的有效性。
操作304，根据支付前处理请求基于加密算法生成对应的公钥和私钥，在第二系统存储所述私钥。
具体地，为了保证支付图形码的安全传输，需要预先由第二系统基于加密算法生成对应的公钥和私钥，公钥存储于第一系统，便于第一系统生成支付图形码后使用公钥进行加密。私钥存储于第二系统，便于第二系统收到加密的支付图形码后进行解密。其中，生成对应的公钥和私钥的算法可自定义，在一个实施例中，通过RSA非对称加密算法来生成公钥和私钥，RSA非对称加密算法保证尽可能大的互质素数来保证加密的高可靠性。
操作306，将公钥发送至述第一系统进行存储。
具体地，第二系统通过双核通信协议将公钥发送至第一系统进行存储。生成的公钥的分发依靠可靠的双核通信来做到通道安全，以此可做到支付图形码的整体可靠性。
在本实施例中，当确认用户同意使用可穿戴设备进行图形码支付后，第一系统指示第二系统根据加密算法生成公钥和私钥，将公钥通过双核通信发送给第一系统；第一系统接收到公钥后进行存储，等待第一系统发送图形码支付的指令，通过预先生成公钥和私钥保证后续支付图形码传输的安全性，提高支付的可靠率。
在一个实施例中，操作204包括：接收第一系统根据公钥加密的支付图形码；根据私钥对加密的支付图形码进行解密得到支付图形码。
具体地，第二系统通过私钥对加密的支付图形码进行解密得到解密的支付图形码，只有私钥才能解密成功从而使用支付图形码，提高了支付图形码传输的安全性。
在本实施例中，通过第二系统传递公钥给第一系统，通过第一系统传递加密的支付图形码给第二系统，即使都被黑客截获，也没有危险性，因为只有第二系统的私钥才能对消息进行解密，防止了消息内容的泄露。
在一个实施例中，操作206包括：将所述支付图形码传递至用户界面；通过用户界面展示支付图形码。
具体地，第二系统将支付图形码发送到UI用户界面进行解析和展示，完成低功耗模式下的图形码支付。在一个实施例中，可穿戴设备的显示屏通过MIPI(Mobile Industry Processor Interface，移动产业处理器接口)与第一处理器和第二处理器连接，可以将第一处理器或第二处理器输出的数据进行展示。图形码的数据解析和展示由低功耗处理器，即第二处理器完成，节省了可穿戴设备的功耗。
在本实施例中，在第二系统状态下，通过低性能系统可以进行支付图形码的展示，保证 了可穿戴设备在低性能系统下的支付功能使用，并且降低了可穿戴设备的功耗。
在一个实施例中，方法还包括：检测可穿戴设备的运行状态；当运行状态满足低功耗条件时，将可穿戴设备切换至第二系统状态运行，控制第一系统进入休眠状态。
具体地，可穿戴设备的运行状态包括可穿戴设备自身的设备信息状态，还可包括可穿戴设备采集的用户信息状态。其中设备信息状态包括电量信息状态、设备温度状态、设备运动状态等，电量信息状态包括低电量状态和高电量状态，设备温度状态包括正常温度状态和异常温度状态，设备运动状态包括设备运动速度、设备旋转角度等。用户信息状态包括用户的心率、注意力信息，如眼球位置信息、心肺数据中至少一种但不限于此。低功耗条件可以自定义，如低电量状态、异常温度状态、设备运动速度大于预设阈值状态、心率低于预设阈值状态等都可以认为满足低功耗条件。
在一个实施例中，通过将设备信息状态、用户信息状态中的各个状态形成状态向量，根据状态向量确定是否满足低功耗条件，如预先设置低功耗条件对应的标准状态向量，将可穿戴设备的各个状态形成的当前状态向量与标准状态向量进行匹配，如果匹配成功，则认为满足低功耗条件。可灵活根据可穿戴设备的各个状态设置判断可穿戴设备是否满足低功耗条件，从而将可穿戴设备切换至第二系统状态运行，控制第一系统进入休眠状态，节省功耗。
在本实施例中，自动检测可穿戴设备的运行状态，当运行状态满足低功耗条件时，将可穿戴设备运行自动切换至第二系统状态运行，控制第一系统进入休眠状态，从而节省功耗。
在一个实施例中，上行数据包是第二处理器传输给第一处理器的数据包，如图4所示，第二处理器将上行数据包发送至所述第一处理器包括以下操作：
操作402,向第一处理器发送受控中断信号，以使第一处理器根据所述受控中断信号发送主控应答信号，并从第二处理器读取所述上行数据包。
其中，上行数据包可以包含由第二处理器接收或生成的操作指令和业务数据中的至少一种。例如，上行数据包可以是第二系统获取的支付指令，接收到支付图形码后生成的应答信息，基于加密算法生成对应的公钥等。
受控中断信号用于中断指示第一处理器有上行数据需要传输给第一处理器。具体地，在检测到有上行数据包时，电子设备的第二处理器可以根据上行数据包生成对应的受控中断信号，并在锁定数据传输接口之后将生成的受控中断信号通过受控中断接口发送给第一处理器。
第一处理器可以根据受控中断信号从第二处理器读取上行数据包，并向第二处理器发送主控应答信号。主控应答信号用于表征第一处理器处于数据传输的状态。
操作404,在上行数据包传输完成后，向第一处理器发送重置的受控中断信号，以使第一处理器根据重置的受控中断信号，在完成上行数据包的读取后，重置主控应答信号。
具体地，第二处理器可以在上行数据包传输完成后，重置受控中断信号。第一处理器可以接收重置的受控中断信号。重置的受控中断信号可以表征第二处理器已经完成数据的传输。第一处理器可以在获取到重置的受控中断信号时，重置主控应答信号。
上述实施例中，第一处理器可以在接收到受控中断信号时则进行数据包的读取，并在数据读取完成后根据第二处理器重置的受控中断信号重置主控应答信号，重置的主控应答信号即表示单次数据传输完成，可以减少处理器通信的时延，提高处理器通信的效率。
具体地，如图5所示，为一个实施例中可穿戴设备的内部结构示意图。可穿戴设备包括对应于第一系统的第一处理器310和对应于第二系统的第二处理器320，可穿戴设备可以包括心率传感器321、加速度+陀螺仪322、大气压力传感器323、触摸传感器324、磁力传感器325、微压差传感器326等传感器中的一种或多种。第二处理器320可以与可穿戴设备包含的传感器连接，用于获取传感器采集的数据。第二处理器320还可以与GPS(Global Positioning System，全球定位系统)模块327连接，用于获取GPS天线接收的定位数据；及与调试(DEBUG)模块328连接，用于输出可穿戴设备的调试数据。第一处理器310和第二处理器320之间通过SPI(Serial Peripheral Interface，串行外设接口)连接，从而第一系统和第二系统可以通过SPI总线进行通信数据的传输。显示屏330通过MIPI(Mobile Industry Processor  Interface，移动产业处理器接口)与第一处理器310和第二处理器320连接，可以将第一处理器310或第二处理器320输出的数据进行展示。第一处理器310还包括传感器集线器驱动，可以用于驱动各传感器的数据采集及处理。
在一个具体的实施例中，如图6所示，第一处理器310为高通芯片，其上运行Android系统，第二处理器320为MCU芯片，其上运行RTOS系统，支付方法包括以下操作：
1、通过Android系统接收作用于界面的二维码支付权限操作，确定用户有支付需求，生成支付前处理请求；
2、Android系统发送支付前处理请求至MCU，MCU使用RSA加密算法生成公钥和私钥，将公钥通过双核通信SPI协议发送给Android系统，在本地保存私钥用于解密二维码显示。
3、Android系统接收到公钥后进行存储，等待MCU发送二维码支付指令。
4、MCU会在低功耗状态下监听用户的支付动作，如果监听到二维码支付请求，将支付指令发送给Android系统，以唤醒Android系统。
5、Android系统收到支付指令后，唤醒Android系统生成二维码，并将生成的二维码通过预先存储的公钥进行加密。
6、Android系统将加密的二维码通过双核通信SPI协议传输给MCU。
7、MCU收到支付指令应答的数据后通过自身私钥解密出二维码数据，向Android系统返回应答信息，应答信息指示Android系统进入休眠状态。
8、MCU将二维码数据发送到UI进行解析和展示，完成低性能系统下的二维码支付。
本实施例中，双核通信通道通过SPI协议进行高通芯片和MCU芯片之间的可靠数据传输，使用RSA加密算法保证加密的二维码数据不被窃取，保证低功耗模式下和低性能系统下二维码的安全使用，借用Android系统的高性能多功能支持，MCU接收Android系统发送的二维码数据，安全且可靠的在低功耗条件下完成二维码支付
在一个实施例中，如图7所示，提供了一种支付方法，应用于可穿戴设备，所述可穿戴设备包括第一处理器和第二处理器，其中，所述第一处理器用于运行第一系统，所述第二处理器用于运行第二系统，所述可穿戴设备处于所述第二系统状态下，所述第二处理器的功耗低于所述第一处理器的功耗，包括以下操作：
操作502，接收第二系统发送的支付指令，根据支付指令生成对应的支付图形码。
操作504，向第二系统发送支付图形码，支付图形码用于通过第二系统完成支付。
在本实施例中，可穿戴设备包括第一处理器和第二处理器，其中，第一处理器用于运行第一系统，第二处理器用于运行第二系统，可穿戴设备处于第二系统状态下，第二处理器的功耗低于所述第一处理器的功耗，接收第二系统发送的支付指令，根据支付指令生成对应的支付图形码；向第二系统发送支付图形码，支付图形码用于通过第二系统完成支付。整个支付过程处于第二系统状态下，由低功耗的处理器控制，通过双核通信接收支付图形码并展示，通过低性能的系统完成支付，借第二系统的高性能完成本不可以在低性能的系统上实现的支付功能。
在一个实施例中，操作502包括：根据所述支付指令进入工作状态。操作504之后，还包括：接收第二系统返回的应答信息，根据应答信息进入休眠状态。
在一个实施例中，方法还包括：当处于工作状态时，获取用户支付权限指令；根据用户支付权限指令向第二系统发送支付前处理请求，支付前处理请求用于指示第二系统基于加密算法生成对应的公钥和私钥，在第二系统存储私钥；接收第二系统返回的公钥，存储公钥。
在一个实施例中，操作502包括：根据公钥进行加密生成加密的支付图形码。操作504包括：向第二系统发送加密的支付图形码。
在一个实施例中，下行数据包是第一处理器传输给第二处理器的数据包，第一处理器将下行数据包发送至所述第二处理器包括以下操作：当检测到有下行数据包时，第一处理器发送主控中断信号给第二处理器；第一处理器接收所述第二处理器根据主控中断信号返回的受控应答信号；第一处理器根据受控应答信号将下行数据包发送给第二处理器，并在发送完成后重置主控中断信号；重置的主控中断信号用于指示第二处理器在完成下行数据包的处理后，重置受控应答信号。
具体地，下行数据包可以包含由第一处理器接收或生成的操作指令和业务数据中的至少一种，如可以为支付图形码。其中，操作指令可以用于在传输给第二处理器之后，指示第二处理器执行对应的业务操作。业务数据用于在传输给第二处理器之后，为第二处理器执行业务数据对应的业务操作提供数据支持。
主控中断信号用于中断指示第二处理器有下行数据需要传输给第二处理器。具体地，在检测到有下行数据包，电子设备的第一处理器可以根据下行数据包生成对应的主控中断信号，并将生成的主控中断信号通过主控中断接口发送给第二处理器。受控应答信号用于表征第二处理器已经做好接收下行数据包的准备。第一处理器和第二处理器之间的数据传输需要通过数据传输接口实现。
重置的主控中断信号可以表征第一处理器已经完成数据的传输。第一处理器可以在下行数据包发送完成后，重置主控中断信号，以通知第二处理器下行数据包已经发送完成。第二处理器接收下行数据包，可以对下行数据包进行处理，第二处理器可以在获取到重置的主控中断信号、且完成对下行数据包的处理时，重置受控应答信号。第二处理器可以将受控应答接口设置为低电平状态。重置的受控应答信号用于通知第一处理器，第二处理器已经完成对下行数据包的处理，第一处理器可以根据重置的受控应答信号再次向第二处理器发送主控中断信号以进行数据的传输。
本实施例中，当检测到下行数据包时，第一处理器可以发送主控中断信号给第二处理器，并接收第二处理器根据主控中断信号返回的受控应答信号，根据该受控应答信号即可以将下行数据包发送给第二处理器，并在发送完成后重置主控中断信号，重置的主控中断信号可以指示第二处理器在完成下行数据包的处理后，重置受控应答信号。即可以在接收到受控应答信号时则进行数据包的传输，并在传输完成后重置主控中断信号，重置的主控中断信号即表示单次数据传输完成，不需要引入受控中断信号和主控应答信号进行二次确认，可以减少处理器通信的时延，提高处理器通信的效率。
应该理解的是，虽然图2-图4和图6-图7的流程图中的各个操作按照箭头的指示依次显示，但是这些操作并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些操作的执行并没有严格的顺序限制，这些操作可以以其它的顺序执行。而且，图2-图4和图6-图7中的至少一部分操作可以包括多个子操作或者多个阶段，这些子操作或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些子操作或者阶段的执行顺序也不必然是依次进行，而是可以与其它操作或者其它操作的子操作或者阶段的至少一部分轮流或者交替地执行。
图8为一个实施例的支付装置的结构框图。如图8所示，提供了一种支付装置600，应用于可穿戴设备，所述可穿戴设备包括第一处理器和第二处理器，其中，所述第一处理器用于运行第一系统，所述第二处理器用于运行第二系统，所述可穿戴设备处于所述第二系统状态下，所述第二处理器的功耗低于所述第一处理器的功耗；该装置包括：支付指令发送模块602、支付图形码接收模块604、应答模块606和支付模块608，其中：
支付指令发送模块602，用于获取支付指令，将支付指令发送至第一系统。
支付图形码接收模块604，用于接收第一系统根据支付指令返回的支付图形码。
支付模块606，用于通过支付图形码完成支付。
上述支付装置，通过支付图形码完成支付，整个支付过程处于第二系统状态下，由低功耗的处理器控制，通过双核通信接收支付图形码并展示，通过低性能的系统完成支付，借第二系统的高性能完成本不可以在低性能的系统上实现的支付功能。
在一个实施例中，支付指令用于唤醒所述第一系统，指示第一系统根据支付指令生成支付图形码，装置还包括：
应答模块608，用于向第一系统返回应答信息，应答信息用于指示第一系统进入休眠状态。
本实施例中，只有生成支付图形码时唤醒第一系统，接收到支付图形码后第一系统进入休眠状态，从而进一步减少第一系统的功耗消耗，在低功耗条件下完成支付，提高了资源利用率。
在一个实施例中，应答模块608还用于对支付图形码进行验证，当验证通过时，生成应答信息。
本实施例中，通过验证操作，提高了支付图形码的有效性，避免支付失败。只有验证通过时，才生成应答信息进一步保证了支付图形码的可靠性。
在一个实施例中，装置还包括：
前处理模块610，用于接收第一系统发送的支付前处理请求，所述支付前处理请求是所述第一系统根据用户支付权限指令生成的；根据支付前处理请求基于加密算法生成对应的公钥和私钥，在第二系统存储私钥，将公钥发送至第一系统进行存储。
本实施例中，当确认用户同意使用可穿戴设备进行图形码支付后，第一系统指示第二系统根据加密算法生成公钥和私钥，将公钥通过双核通信发送给第一系统；第一系统接收到公钥后进行存储，等待第一系统发送图形码支付的指令，通过预先生成公钥和私钥保证后续支付图形码传输的安全性，提高支付的可靠率。
在一个实施例中，支付图形码接收模块604还用于接收第一系统根据公钥加密的支付图形码；根据私钥对所述加密的支付图形码进行解密得到支付图形码。
本实施例中，通过第二系统传递公钥给第一系统，通过第一系统传递加密的支付图形码给第二系统，即使都被黑客截获，也没有危险性，因为只有第二系统的私钥才能对消息进行解密，防止了消息内容的泄露。
在一个实施例中，支付模块606还用于将支付图形码传递至用户界面；通过用户界面展示支付图形码。
本实施例中，在第二系统状态下，通过低性能系统可以进行支付图形码的展示，保证了可穿戴设备在低性能系统下的支付功能使用，并且降低了可穿戴设备的功耗。
在一个实施例中，装置还包括：
模式切换模块612，用于检测可穿戴设备的运行状态，当运行状态满足低功耗条件时，将可穿戴设备切换至所述第二系统状态运行，控制第一系统进入休眠状态。
在本实施例中，自动检测可穿戴设备的运行状态，当运行状态满足低功耗条件时，将可穿戴设备运行自动切换至第二系统状态运行，控制第一系统进入休眠状态，从而节省功耗。
在一个实施例中，上行数据包是第二处理器传输给第一处理器的数据包，装置还包括：
上行数据通信模块614，用于向第一处理器发送受控中断信号，以使第一处理器根据所述受控中断信号发送主控应答信号，并从第二处理器读取上行数据包；在上行数据包传输完成后，向第一处理器发送重置的受控中断信号，以使第一处理器根据所述重置的受控中断信号，在完成上行数据包的读取后，重置主控应答信号
本实施例中，第一处理器可以在接收到受控中断信号时则进行数据包的读取，并在数据读取完成后根据第二处理器重置的受控中断信号重置主控应答信号，重置的主控应答信号即表示单次数据传输完成，可以减少处理器通信的时延，提高处理器通信的效率。
图9为一个实施例的支付装置的结构框图。如图9所示，提供了一种支付装置700，应用于可穿戴设备，可穿戴设备包括第一处理器和第二处理器，其中，第一处理器用于运行第一系统，第二处理器用于运行第二系统，可穿戴设备处于第二系统状态下，第二处理器的功耗低于第一处理器的功耗；该装置包括：支付图形码生成模块702、发送模块704，其中：
支付图形码生成模块702，用于接收所述第二系统发送的支付指令，根据所述支付指令生成对应的支付图形码。
发送模块704，用于向所述第二系统发送所述支付图形码，所述支付图形码用于通过所述第二系统完成支付。
在本实施例中，整个支付过程处于第二系统状态下，由低功耗的处理器控制，通过双核通信接收支付图形码并展示，通过低性能的系统完成支付，借第二系统的高性能完成本不可以在低性能的系统上实现的支付功能。
在一个实施例中，支付图形码生成模块702还用于根据支付指令进入工作状态，装置还包括：休眠模块706，用于接收第二系统返回的应答信息，根据应答信息进入休眠状态。
本实施例中，只有生成支付图形码时唤醒第一系统，接收到支付图形码后第一系统进入休眠状态，从而进一步减少第一系统的功耗消耗，在低功耗条件下完成支付，提高了资源利用率。
在一个实施例中，装置还包括：
前处理模块708，用于当处于工作状态时，获取用户支付权限指令；根据用户支付权限指令向第二系统发送支付前处理请求，支付前处理请求用于指示所述第二系统基于加密算法生成对应的公钥和私钥，在第二系统存储私钥；接收所述第二系统返回的公钥，存储公钥。
本实施例中，当确认用户同意使用可穿戴设备进行图形码支付后，第一系统指示第二系统根据加密算法生成公钥和私钥，将公钥通过双核通信发送给第一系统；第一系统接收到公钥后进行存储，等待第一系统发送图形码支付的指令，通过预先生成公钥和私钥保证后续支付图形码传输的安全性，提高支付的可靠率。
在一个实施例中，支付图形码生成模块702还用于根据公钥进行加密生成加密的支付图形码。发送模块704还用于向第二系统发送加密的支付图形码。
本实施例中，通过第二系统传递公钥给第一系统，通过第一系统传递加密的支付图形码给第二系统，即使都被黑客截获，也没有危险性，因为只有第二系统的私钥才能对消息进行解密，防止了消息内容的泄露。
在一个实施例中，下行数据包是第一处理器传输给第二处理器的数据包，装置还包括：
下行数据通信模块710，用于当检测到有下行数据包时，通过第一处理器发送主控中断信号给第二处理器；第一处理器接收第二处理器根据主控中断信号返回的受控应答信号；第一处理器根据受控应答信号将下行数据包发送给第二处理器，并在发送完成后重置主控中断信号；重置的主控中断信号用于指示第二处理器在完成下行数据包的处理后，重置受控应答信号。
本实施例中，当检测到下行数据包时，第一处理器可以发送主控中断信号给第二处理器，并接收第二处理器根据主控中断信号返回的受控应答信号，根据该受控应答信号即可以将下行数据包发送给第二处理器，并在发送完成后重置主控中断信号，重置的主控中断信号可以指示第二处理器在完成下行数据包的处理后，重置受控应答信号。即可以在接收到受控应答信号时则进行数据包的传输，并在传输完成后重置主控中断信号，重置的主控中断信号即表示单次数据传输完成，不需要引入受控中断信号和主控应答信号进行二次确认，可以减少处理器通信的时延，提高处理器通信的效率。
上述支付装置中各个模块的划分仅用于举例说明，在其他实施例中，可将支付装置按照需要划分为不同的模块，以完成上述支付装置的全部或部分功能。
关于支付装置的具体限定可以参见上文中对于支付方法的限定，在此不再赘述。上述支付装置中的各个模块可全部或部分通过软件、硬件及其组合来实现。上述各模块可以硬件形 式内嵌于或独立于计算机设备中的处理器中，也可以以软件形式存储于计算机设备中的存储器中，以便于处理器调用执行以上各个模块对应的操作。
图10为一个实施例中电子设备的内部结构示意图。如图10所示，该电子设备包括通过系统总线连接的处理器和存储器。其中，该处理器用于提供计算和控制能力，支撑整个电子设备的运行。存储器可包括非易失性存储介质及内存储器。非易失性存储介质存储有操作系统和计算机程序。该计算机程序可被处理器所执行，以用于实现以下各个实施例所提供的一种支付方法。内存储器为非易失性存储介质中的操作系统计算机程序提供高速缓存的运行环境。该电子设备可以各种穿戴式设备。
本申请实施例中提供的支付装置中的各个模块的实现可为计算机程序的形式。该计算机程序可在终端或服务器上运行。该计算机程序构成的程序模块可存储在电子设备的存储器上。该计算机程序被处理器执行时，实现本申请实施例中所描述方法的操作。
本申请实施例还提供了一种计算机可读存储介质。一个或多个包含计算机可执行指令的非易失性计算机可读存储介质，当所述计算机可执行指令被一个或多个处理器执行时，使得所述处理器执行支付方法的操作。
一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行支付方法。
本申请所使用的对存储器、存储、数据库或其它介质的任何引用可包括非易失性和/或易失性存储器。非易失性存储器可包括只读存储器(ROM)、可编程ROM(PROM)、电可编程ROM(EPROM)、电可擦除可编程ROM(EEPROM)或闪存。易失性存储器可包括随机存取存储器(RAM)，它用作外部高速缓冲存储器。作为说明而非局限，RAM以多种形式可得，诸如静态RAM(SRAM)、动态RAM(DRAM)、同步DRAM(SDRAM)、双数据率SDRAM(DDR SDRAM)、增强型SDRAM(ESDRAM)、同步链路(Synchlink)DRAM(SLDRAM)、存储器总线(Rambus)直接RAM(RDRAM)、直接存储器总线动态RAM(DRDRAM)、以及存储器总线动态RAM(RDRAM)。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种支付方法，应用于可穿戴设备，所述可穿戴设备包括第一处理器和第二处理器，其中，所述第一处理器用于运行第一系统，所述第二处理器用于运行第二系统，所述可穿戴设备处于所述第二系统状态下，所述第二处理器的功耗低于所述第一处理器的功耗，所述方法包括：
    获取支付指令，将所述支付指令发送至所述第一系统；
    接收所述第一系统根据所述支付指令返回的支付图形码；及
    通过所述支付图形码完成支付。
  2. 根据权利要求1所述的方法，所述支付指令用于唤醒所述第一系统，指示所述第一系统根据所述支付指令生成所述支付图形码；所述接收所述第一系统根据所述支付指令返回的支付图形码之后，还包括：
    向所述第一系统返回应答信息，所述应答信息用于指示所述第一系统进入休眠状态。
  3. 根据权利要求2所述的方法，所述向所述第一系统返回应答信息包括：
    对所述支付图形码进行验证，当验证通过时，生成所述应答信息。
  4. 根据权利要求1所述的方法，所述获取支付指令之前，还包括：
    接收所述第一系统发送的支付前处理请求，所述支付前处理请求是所述第一系统根据用户支付权限指令生成的；
    根据所述支付前处理请求基于加密算法生成对应的公钥和私钥，在所述第二系统存储所述私钥；及
    将所述公钥发送至所述第一系统进行存储。
  5. 根据权利要求4所述的方法，所述接收所述第一系统根据所述支付指令返回的支付图形码包括：
    接收所述第一系统根据所述公钥加密的支付图形码；及
    根据所述私钥对所述加密的支付图形码进行解密得到所述支付图形码。
  6. 根据权利要求1所述的方法，所述通过所述支付图形码完成支付包括：
    将所述支付图形码传递至用户界面；及
    通过所述用户界面展示所述支付图形码。
  7. 根据权利要求1所述的方法，所述方法还包括：
    检测所述可穿戴设备的运行状态；及
    当所述运行状态满足低功耗条件时，将所述可穿戴设备切换至所述第二系统状态运行，控制所述第一系统进入休眠状态。
  8. 根据权利要求1所述的方法，上行数据包是第二处理器传输给第一处理器的数据包，第二处理器将上行数据包发送至所述第一处理器包括以下操作：
    向所述第一处理器发送受控中断信号，以使所述第一处理器根据所述受控中断信号发送主控应答信号，并从所述第二处理器读取所述上行数据包；及
    在所述上行数据包传输完成后，向所述第一处理器发送重置的受控中断信号，以使所述第一处理器根据所述重置的受控中断信号，在完成所述上行数据包的读取后，重置所述主控应答信号。
  9. 一种支付方法，应用于可穿戴设备，所述可穿戴设备包括第一处理器和第二处理器，其中，所述第一处理器用于运行第一系统，所述第二处理器用于运行第二系统，所述可穿戴设备处于所述第二系统状态下，所述第二处理器的功耗低于所述第一处理器的功耗，所述方法包括：
    接收所述第二系统发送的支付指令，根据所述支付指令生成对应的支付图形码；及
    向所述第二系统发送所述支付图形码，所述支付图形码用于通过所述第二系统完成支付。
  10. 根据权利要求9所述的方法，所述接收所述第二系统发送的支付指令，根据所述支 付指令生成对应的支付图形码包括：
    根据所述支付指令进入工作状态；
    所述向所述第二系统发送所述支付图形码之后，还包括；
    接收所述第二系统返回的应答信息；及
    根据所述应答信息进入休眠状态。
  11. 根据权利要求9所述的方法，所述方法还包括：
    当处于工作状态时，获取用户支付权限指令；
    根据所述用户支付权限指令向第二系统发送支付前处理请求，所述支付前处理请求用于指示所述第二系统基于加密算法生成对应的公钥和私钥，在所述第二系统存储所述私钥；及
    接收所述第二系统返回的所述公钥，存储所述公钥。
  12. 根据权利要求11所述的方法，所述根据所述支付指令生成对应的支付图形码包括：
    根据所述公钥进行加密生成加密的支付图形码；及
    所述向所述第二系统发送所述支付图形码，包括：
    向所述第二系统发送所述加密的支付图形码。
  13. 一种支付装置，应用于可穿戴设备，所述可穿戴设备包括第一处理器和第二处理器，其中，所述第一处理器用于运行第一系统，所述第二处理器用于运行第二系统，所述可穿戴设备处于所述第二系统状态下，所述第二处理器的功耗低于所述第一处理器的功耗，所述装置包括：
    支付指令发送模块，用于获取支付指令，将所述支付指令发送至所述第一系统；
    支付图形码接收模块，用于接收所述第一系统根据所述支付指令返回的支付图形码；及支付模块，用于通过所述支付图形码完成支付。
  14. 根据权利要求13所述的装置，所述支付指令用于唤醒所述第一系统，指示所述第一系统根据所述支付指令生成所述支付图形码；所述装置还包括应答模块，所述应答模块用于向所述第一系统返回应答信息，所述应答信息用于指示所述第一系统进入休眠状态。
  15. 根据权利要求13所述的装置，所述装置还包括前处理模块，所述前处理模块用于接收所述第一系统发送的支付前处理请求，所述支付前处理请求是所述第一系统根据用户支付权限指令生成的；根据所述支付前处理请求基于加密算法生成对应的公钥和私钥，在所述第二系统存储所述私钥；及将所述公钥发送至所述第一系统进行存储。
  16. 一种支付装置，应用于可穿戴设备，所述可穿戴设备包括第一处理器和第二处理器，其中，所述第一处理器用于运行第一系统，所述第二处理器用于运行第二系统，所述可穿戴设备处于所述第二系统状态下，所述第二处理器的功耗低于所述第一处理器的功耗，所述装置包括：
    支付图形码生成模块，用于接收所述第二系统发送的支付指令，根据所述支付指令生成对应的支付图形码；及
    发送模块，用于向所述第二系统发送所述支付图形码，所述支付图形码用于通过所述第二系统完成支付。
  17. 根据权利要求16所述的装置，所述支付图形码生成模块还用于根据所述支付指令进入工作状态；所述装置还包括休眠模块，所述休眠模块还用于接收所述第二系统返回的应答信息；根据所述应答信息进入休眠状态。
  18. 根据权利要求16所述的装置，所述装置还包括前处理模块，所述前处理模块用于当处于工作状态时，获取用户支付权限指令；根据所述用户支付权限指令向第二系统发送支付前处理请求，所述支付前处理请求用于指示所述第二系统基于加密算法生成对应的公钥和私钥，在所述第二系统存储所述私钥；及接收所述第二系统返回的所述公钥，存储所述公钥。
  19. 一种电子设备，包括存储器及处理器，所述存储器中储存有计算机程序，所述计算机程序被所述处理器执行时，使得所述处理器执行如权利要求1至8或9至12中任一项所述方法的操作。
  20. 一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现如权利要求1至8或9至12中任一项所述方法的操作。
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