WO2022141735A1 - Processing apparatus, processing method, and related device - Google Patents

Abstract

The present application provides a processing apparatus, a processing method, and a related device. The processing apparatus comprises: a processor, a frequency modulation controller, and a frequency modulator. The processor comprises a first processor core. The frequency modulation controller is used for: obtaining at least one load type of the first processor core; determining a target frequency of a target object on the basis of the at least one load type, the target object comprising a memory; and calling the frequency modulator on the basis of the target frequency to adjust the working frequency of the target object. According to the present application, the performance and energy efficiency of the processor can be well optimized.

Description

Processing device, processing method and related equipment

This application claims the priority of the international application filed with the China Patent Office on December 31, 2020, the application number is PCT/CN2020/142512, and the application name is "processing device, processing method and related equipment", the entire contents of which are incorporated by reference in this application.

technical field

The present application relates to the technical field of processors, and in particular, to a processing apparatus, a processing method, and related equipment.

Background technique

With the increasing demand for computing power and computing efficiency of mobile terminals, the central processing unit (CPU) of a system on a chip (SoC) and its corresponding storage system are increasingly complex. The development of single-cluster into double-cluster or even multi-cluster, and the introduction of L3 cache and even L4 cache, etc., pose great challenges to the optimization of processor and memory performance and energy efficiency of computer systems.

To sum up, how to better optimize the performance of the processor and the memory and the energy efficiency of the computer system is a technical problem to be solved by those skilled in the art.

SUMMARY OF THE INVENTION

Embodiments of the present application provide a processing apparatus, a processing method, and related equipment, which can better optimize the performance of a processor and a memory and the energy efficiency of a computer system.

In a first aspect, an embodiment of the present application provides a processing device, the processing device includes a processor, a frequency modulation controller, and a frequency modulator, the processor includes a first processor core; the frequency modulation controller is used to: obtain the first processing at least one load type of the processor core; determining a target frequency of the target object based on the at least one load type; the target object includes a memory; calling the frequency regulator to adjust the operating frequency of the target object based on the target frequency.

Optionally, the memory may include at least one of a memory and an asynchronous cache.

Optionally, the foregoing load types may include computational loads, cache-dependent loads, and memory-dependent loads.

Since the working frequency of the memory that is best matched to different types of loads may be different, in this application, the working frequency of the corresponding memory is adjusted according to the workload type of the processor core (for example, if the workload is memory-dependent, the working frequency of the memory can be appropriately adjusted). If the workload is computing-dependent, the working frequency of the memory can be appropriately adjusted), so that the memory can better cooperate with the processor to process the workload for different workload types, and can reduce the system workload during processing. Caton can optimize the energy efficiency of the system while meeting the processing efficiency required by the workload, that is, the performance of the processor and memory can meet the needs of the workload while optimizing the energy efficiency of the system. In addition, compared with the existing technical solutions, the existing technical solutions ignore not only the processor core itself, but also the memory (such as asynchronous cache and/or asynchronous cache) that affects the processor performance and system energy efficiency. In order to better optimize the performance of the processor and the energy efficiency of the system, it is necessary to optimize the performance of the asynchronous memory, thereby better optimizing the energy efficiency of the system.

In a possible implementation manner, the above-mentioned target object further includes the above-mentioned first processor core; the frequency modulation controller is further configured to: based on the target frequency of the first processor core, call the frequency controller to adjust the frequency of the first processor core. There is a mapping relationship between the working frequency, the target frequency of the first processor core and the target frequency of the memory.

Due to the different operating frequencies of processors and memories that are best matched for different types of loads, in this application, the processor core and the asynchronous storage system can be regarded as one, and the operating frequencies can be optimized simultaneously by using algorithms and frequency modulation methods. The operating frequency of the storage system and the processor core is matched with the workload that needs to be processed, so that the overall performance requirements of the processor and the memory can be met while unnecessary energy consumption can be saved, thereby optimizing the energy efficiency of the system.

In addition, there is a mapping relationship between the target frequency of the first processor core and the target frequency of the memory, and the mapping relationship enables the performance and energy efficiency of the processor to be optimal at the same time, that is, the target frequency of the first processor core and The target frequency of the memory simultaneously runs and processes the corresponding workload, which can meet the performance requirements of the workload on the processor and the memory, save unnecessary energy consumption, and optimize the energy efficiency of the system.

In a possible implementation manner, the above-mentioned processor further includes at least one second processor core, the above-mentioned first processor core and the at least one second processor core form a cluster, and the frequency modulation controller is further configured to The target frequency of a processor core determines the operating frequency of the cluster.

Optionally, the at least one second processor core may include one or more of the above-mentioned first processor cores.

Since the processor cores in a cluster share one operating frequency, in this application, when one or more target frequencies of one or more processor cores in a cluster are obtained, it is necessary to arbitrate based on these target frequencies. A unified optimized frequency is used as the working frequency of the one cluster.

In a possible implementation manner, the above-mentioned processor includes n above-mentioned first processor cores, where n is a positive integer; the above-mentioned frequency modulation controller is further configured to: determine for at least one load type of each of the first processor cores A target frequency of the memory; determining the optimal operating frequency of the memory based on the n target frequencies of the memory; calling the frequency regulator to adjust the operating frequency of the memory to the optimal operating frequency.

Since the memory is shared by the entire processor and has only one operating frequency, in the present application, when multiple optimized operating frequencies of the memory are obtained, a unified optimized frequency also needs to be arbitrated as the operating frequency of the memory.

In a possible implementation manner, the processing apparatus further includes: a load classifier, configured to obtain load classification feature information in the first processor core, and based on the load classification feature information, load the first processor core The at least one load type is obtained through classification; the frequency modulation controller is specifically configured to: obtain the at least one load type from the load classifier.

Optionally, the load classification feature information includes clock signal inversion information in the first processor core.

In this application, the load classifier can be implemented by one or more of hardware, software or firmware, and can classify the load in the processor core in a fine-grained manner, so as to cooperate with the frequency modulation controller to obtain a reasonable and accurate optimized frequency .

In a possible implementation manner, the frequency regulation controller is further configured to: acquire the load of the first processor core; and determine the target of the target object based on the at least one load type when the load meets a preset condition frequency.

Optionally, the load amount is the load amount of the first processor core in a first time period, and the first time period and the time period in which the first processor core obtains the load amount are two adjacent ones. a time period, and the first time period occurs first.

Optionally, the preset condition may include: the load is greater than the first load threshold or the load is less than the second load threshold. Wherein, the first load threshold is greater than the second load threshold.

The present application shows that the processing of frequency optimization and adjustment is triggered only when the load satisfies the preset conditions, which can reduce the resources consumed by triggering adjustment anytime and anywhere.

In addition, optionally, the present application may set two thresholds, one is the up-frequency threshold (the above-mentioned first load threshold), and the other is the down-frequency threshold (the above-mentioned second load threshold), when the load is greater than the up-frequency threshold , it indicates that the load of the processor core is heavy and the processing speed cannot keep up. In order to improve the performance, the frequency needs to be increased. When the load is less than the frequency reduction threshold, it indicates that the load of the processor core is light, and such a fast processing speed is not required. In order to save energy consumption, frequency reduction is required. Setting the two thresholds can also more reasonably perform frequency regulation on processor cores and the like, and can also reduce additional resource consumption of frequent frequency regulation.

In a possible implementation, the above-mentioned frequency modulation controller is specifically used for:

Based on the current operating frequency of the target object, the current performance information of the processor is searched in the first mapping table corresponding to the first load type, where the first mapping table includes the mapping between the operating frequency of the target object and the performance information of the processor relationship; the first load type is the type with the most occurrences among the at least one load type; adjust the current performance information based on the load amount to obtain target performance information; look up in the first mapping table based on the target performance information The first target frequency of the target object, and the first target frequency is taken as the target frequency of the target object.

In the present application, the corresponding target frequency is calculated based on the load type with the largest number of occurrences or the largest proportion, so that the processor core can achieve better performance and energy efficiency as much as possible when processing the load. In addition, the present application obtains the target frequency through the above-mentioned frequency-performance mapping table. Since these mapping tables are the optimal solution sets that satisfy various constraints obtained through offline training, the obtained target frequency is more ideal. Based on the obtained target frequency Processing loads can be better optimized for performance and energy efficiency.

In a possible implementation manner, the first mapping table further includes a mapping relationship between the operating frequency of the target object and the power consumption of the processor; the frequency modulation controller is further configured to: based on the power consumption constraint of the processor The second target frequency of the target object is searched in the first mapping table; if the first target frequency and the second target frequency are different, the target frequency of the target object is determined to be the second target frequency.

In this application, considering the multiple aspects of frequency, performance and power consumption (ie, energy efficiency), a more reasonable and accurate operating frequency is matched for the memory and/or processor core while satisfying the power consumption constraints and performance requirements at the same time, The performance of the processor and memory and the energy efficiency of the system can be better optimized. In addition, the above frequency-performance-power consumption mapping table is also the optimal solution set obtained by offline training and satisfying various constraints, so the obtained target frequency is more ideal, and the processing load based on the obtained target frequency can obtain better performance and efficiency.

In a possible implementation manner, the above-mentioned at least one load type is m load types, and m is an integer greater than 1; each type of the m load types corresponds to a mapping table, and the mapping table includes the target object's The mapping relationship between the operating frequency and the performance information of the processor; the frequency modulation controller is specifically used for:

Based on the current working frequency of the target object, look up a current performance information of the processor in each of the mapping tables; adjust the m current performance information based on the load to obtain m target performance information; based on the m current performance information The target performance information finds m groups of first optimized frequencies of the target object in the m mapping tables; the m groups of first optimized frequencies are processed based on the load distribution weights of the m load types to obtain a third target frequency, which is the The third target frequency is used as the target frequency of the target object, and the load distribution weight indicates the proportion of the load of each type of the m types.

The present application performs processing based on the load distribution weight to obtain the target frequency, which can also enable the processor core to achieve better performance and energy efficiency when processing the load corresponding to the load type. The present application also uses the above frequency-performance mapping table to obtain the target frequency. Since these mapping tables are the optimal solution sets that satisfy various constraints obtained through offline training, the obtained target frequency is more ideal. Based on the obtained target frequency processing load for better performance and energy efficiency.

In a possible implementation manner, the above m mapping tables further include a mapping relationship between the operating frequency of the target object and the power consumption of the processor; the frequency modulation controller is further configured to: based on the power consumption constraint of the processor Find m groups of second optimized frequencies of the target object in the m mapping tables respectively; process the m groups of second optimized frequencies based on the load distribution weight to obtain the fourth target frequency of the target object; in the third target When the frequency is different from the fourth target frequency, the target frequency of the target object is determined to be the fourth target frequency.

Similarly, in this application, from the aspects of frequency, performance and power consumption (ie energy efficiency), a more reasonable and accurate matching for the memory and/or processor core is made while satisfying the power consumption constraints and performance requirements at the same time. Operating frequency to better optimize processor and memory performance and system energy efficiency. In addition, the above frequency-performance-power consumption mapping table is also the optimal solution set obtained by offline training and satisfying various constraints, so the obtained target frequency is more ideal, and the processing load based on the obtained target frequency can obtain better performance and efficiency.

In a second aspect, the present application provides a processing method, which is applied to a processing device, where the processing device includes a processor, a frequency modulation controller, and a frequency modulator, and the processor includes a first processor core; the method includes: using the frequency modulation The controller does the following:

Acquire at least one load type of the first processor core; determine a target frequency of the target object based on the at least one load type; the target object includes a memory; call the frequency regulator based on the target frequency to adjust the operating frequency of the target object.

In a possible implementation manner, the above-mentioned memory includes at least one of a memory and an asynchronous cache.

In a possible implementation manner, the above load types include computational loads, cache-dependent loads, and memory-dependent loads.

In a possible implementation manner, the above-mentioned target object further includes the above-mentioned first processor core; the above-mentioned method further includes: performing the following operations through the above-mentioned frequency modulation controller:

Based on the target frequency of the first processor core, the frequency regulator is called to adjust the operating frequency of the first processor core, and there is a mapping relationship between the target frequency of the first processor core and the target frequency of the memory.

In a possible implementation manner, the above-mentioned processor further includes at least one second processor core, and the above-mentioned first processor core and the above-mentioned at least one second processor core form a cluster; the above-mentioned method further includes: using the above-mentioned frequency modulation controller according to the The target frequency of the first processor core determines the operating frequency of the cluster.

In a possible implementation manner, the above-mentioned processor includes n above-mentioned first processor cores, and the above-mentioned n is a positive integer; the above-mentioned method further includes: performing the following operations through the above-mentioned frequency modulation controller:

A target frequency of the memory is determined for at least one load type of each of the first processor cores; an optimized operating frequency of the memory is determined based on the n target frequencies of the memory; the frequency regulator is called to adjust the operating frequency of the memory to the above-mentioned Optimize operating frequency.

In a possible implementation manner, the above-mentioned processing apparatus further includes a load classifier, and the above-mentioned method further includes:

Obtain the load classification feature information in the first processor core through the load classifier, and classify the load in the first processor core based on the load classification feature information to obtain the at least one load type; The above-mentioned at least one load type is obtained from the above-mentioned load classifier.

In a possible implementation manner, the load classification feature information includes clock signal inversion information in the first processor core.

In a possible implementation, the above method also includes:

Obtaining the load amount of the first processor core through the frequency regulation controller; the determining the target frequency of the target object based on the at least one load type includes: when the load amount satisfies a preset condition, determining the above-mentioned at least one load type target frequency.

In a possible implementation manner, the above-mentioned determination of the above-mentioned target frequency based on the above-mentioned at least one load type includes:

Based on the current operating frequency of the target object, the current performance information of the processor is searched in the first mapping table corresponding to the first load type, where the first mapping table includes the mapping between the operating frequency of the target object and the performance information of the processor The above-mentioned first load type is the type with the most occurrences among the above-mentioned at least one load type; the above-mentioned current performance information is adjusted based on the above-mentioned load amount to obtain target performance information; based on the above-mentioned target performance information, look up in the above-mentioned first mapping table For the first target frequency of the target object, the first target frequency is taken as the target frequency of the target object.

In a possible implementation manner, the above-mentioned first mapping table further includes a mapping relationship between the operating frequency of the above-mentioned target object and the power consumption of the above-mentioned processor; the above-mentioned method further includes: performing the following operations through the above-mentioned frequency modulation controller:

Based on the power consumption constraint of the processor, the second target frequency of the target object is searched in the first mapping table; when the first target frequency and the second target frequency are different, the target frequency of the target object is determined as the above-mentioned second target frequency.

In a possible implementation manner, the above-mentioned at least one load type is m load types, and the above-mentioned m is an integer greater than 1; each type of the above-mentioned m load types corresponds to a mapping table, and the above-mentioned mapping table includes the above-mentioned target object. The mapping relationship between the operating frequency and the performance information of the above-mentioned processor; the above-mentioned determination of the above-mentioned target frequency based on the above-mentioned at least one load type includes:

Based on the current working frequency of the target object, a current performance information of the processor is searched in each of the above mapping tables; based on the above load, the m pieces of current performance information are adjusted to obtain m pieces of target performance information; The target performance information is to find m groups of first optimized frequencies of the target object in the above m mapping tables; based on the load distribution weights of the above m load types, the above m groups of first optimized frequencies are processed to obtain a third target frequency, and the above The third target frequency is used as the target frequency of the target object, and the load distribution weight indicates the proportion of the load of each of the m types.

In a possible implementation manner, the above-mentioned m mapping tables further include a mapping relationship between the operating frequency of the above-mentioned target object and the power consumption of the above-mentioned processor; the above-mentioned method further includes: performing the following operations through the above-mentioned frequency modulation controller:

Based on the power consumption constraints of the processor, the m groups of second optimized frequencies of the target object are respectively searched in the m mapping tables; the m groups of second optimized frequencies are processed based on the load distribution weight to obtain the fourth optimal frequency of the target object target frequency; when the third target frequency and the fourth target frequency are different, determine the target frequency of the target object as the fourth target frequency.

In a third aspect, the present application provides an electronic device, the device comprising: the processing device according to any one of the above-mentioned first aspect, and a discrete device coupled to the processing device.

In a fourth aspect, the present application provides a system-on-chip, where the system-on-chip includes the processing device provided by any one of the implementation manners of the first aspect. The system-on-chip may consist of a processing chip, or may include a processing chip and other discrete devices.

In a fifth aspect, the present application provides a computer program, the computer program including instructions, when executed by the computer program processor, enables the processor to execute the processing method flow described in any one of the second aspect above.

The solutions provided in the second aspect to the fifth aspect are used to implement or cooperate with the processor provided in the first aspect, and thus can achieve the same or corresponding beneficial effects as those of the first aspect, which will not be repeated here.

To sum up, using the solution provided by the present application can better optimize the performance of the processor and the energy efficiency of the system.

Description of drawings

In order to more clearly describe the technical solutions in the embodiments of the present invention or the background technology, the accompanying drawings required in the embodiments or the background technology of the present invention will be described below.

FIG. 1 is a schematic structural diagram of a processing apparatus according to an embodiment of the present application.

FIG. 2 is a schematic structural diagram of a load classifier according to an embodiment of the present application.

FIG. 3 is a schematic diagram of a relationship between another load type and a mapping table provided by an embodiment of the present application.

FIG. 4 and FIG. 5 are schematic flow charts of functions implemented by modules in a processing device provided by an embodiment of the present application.

FIG. 6 is a schematic flowchart of a processing method provided by an embodiment of the present application.

Detailed ways

The embodiments of the present invention will be described below with reference to the accompanying drawings in the embodiments of the present invention.

The terms "first", "second", "third" and "fourth" in the description and claims of the present application and the drawings are used to distinguish different objects, rather than to describe a specific order . Furthermore, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but optionally also includes unlisted steps or units, or optionally also includes For other steps or units inherent to these processes, methods, products or devices.

Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor a separate or alternative embodiment that is mutually exclusive of other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

First, some terms in this application will be explained so as to facilitate the understanding of those skilled in the art.

(1) Task scheduling, the task scheduling described in this application refers to that the operating system allocates thread task scheduling to multiple processor cores in the processor for execution. A task is a series of operations that work together to achieve a certain purpose, which can be a process or a thread.

(2) Dynamic voltage and frequency scaling (DVFS), DVFS technology can dynamically adjust the operating frequency and voltage of the chip according to the different needs of the computing power of the tasks that the chip is running, so as to achieve the purpose of energy saving.

(3) The processor can be a central processing unit (CPU), a general-purpose processor, a digital signal processor, an integrated circuit (IC), a field programmable gate array (Field Programmable Gate Array, FPGA) ) or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A processor may also be a combination that performs computing functions, such as a combination comprising one or more microprocessors, a combination of a digital signal processor and a microprocessor, and the like.

(4) The processor core, which refers to the core of the processor, controls the execution of all operations such as computing, accepting/storing commands, and processing data.

(5) Performance. In this application, the execution time of a unit instruction (Delay Per Instruction, DPI) can be used to judge the performance of the processor in handling a certain type of load. When the processor is processing a certain type of load, the unit instruction The less execution time, the better the performance. Similarly, the number of instructions executed per unit time (Instructions Per Seconds, IPS) can also be used to judge the performance of the processor in handling a certain type of load. When the processor is processing a certain type of load, the number of instructions executed per unit time The more, the better the performance.

(6) Energy efficiency, which refers to the ratio of the services provided by the computer to the total energy consumed. In this application, energy efficiency can be measured by the number of instructions executed per unit energy consumed (IPS Per Watt). When a computer system (including a processor system and a memory system, etc.) processes a certain type of load, the more instructions executed by consuming unit energy, the better the energy efficiency of the computer system.

(7) Computer instructions are the instructions and commands to direct the work of the machine, the program is a series of instructions arranged in a certain order, and the process of executing the program is the working process of the computer. The instruction set is a set of instructions used in the processor to calculate and control the computer system. Each processor specifies a series of instruction systems that cooperate with its hardware circuit when it is designed. The strength of the instruction is also an important indicator of the processor, and the instruction set is one of the most effective tools to improve the efficiency of the microprocessor. Common instruction set architectures (Instruction Set Architecture, ISA) include complex instruction set computing (Complex Instruction Set Computing, CISC) and reduced instruction set computing (Reduced Instruction Set Computing, RISC). Among them, the typical representatives of CISC are X86, RISC Typical representatives are the Advanced RISC Machine (ARM) architecture and the Microprocessor without interlocked pipelined stages (MIPS) architecture.

(8) A process is often defined as the execution of a program. A process can be regarded as an independent program with its complete data space and code space in memory. Data and variables owned by a process belong only to itself.

(9) A thread is a program that runs alone in a process. That is, threads exist within processes. A process consists of one or more threads, each thread sharing the same code and global data, but each has its own stack. Since the stack is one per thread, local variables are private to each thread. Since all threads share the same code and global data, they are tighter than processes and tend to interact more than separate processes, and the interaction between threads is easier because they themselves have some shared memory for communication : Global data for the process.

In order to facilitate understanding of the embodiments of the present application, the following first analyzes and proposes specific technical problems to be solved by the present application.

Generally speaking, the higher the operating frequency of the processor, the faster the speed of executing tasks and the better the performance. However, the higher the operating frequency, the more energy it needs to consume, the greater the power consumption, and the more energy efficient the computer system is. Difference. To balance performance and energy efficiency, tasks can be scheduled and the operating frequency of the processor can be tuned. The existing scheduling-frequency modulation scheme integrates the completely fair scheduler (CFS) and the dynamic voltage and frequency scaling (DVFS) technology. In the scheduler CFS, through the preset DVFS energy and performance The scaling table senses the result of energy consumption in the scheduling process, and then controls the DVFS to adjust the working frequency of the CPU to optimize the energy efficiency of the scheduling. At the same time, DVFS runs periodically, sustaining target performance and energy efficiency. However, the optimization of performance and energy efficiency brought about by this integration is limited to certain fixed scenarios, such as the first time a new thread is issued, the old thread is awakened, and the thread needs to be migrated. There is no ongoing guarantee.

For tasks that run for a long time, in order to ensure the continuous performance and energy efficiency optimization of the task. The current scheduling FM system still needs to rely on the periodic execution of DVFS. In theory, the finer the execution interval of DVFS, the greater the benefit of the system. But it is limited by the execution overhead of DVFS itself. This interval cannot be made more fine-grained.

In addition, the above-mentioned CFS and DVFS fusion scheme relies on a fixed performance and power consumption conversion table to optimize task performance and energy efficiency, but this table is not universally applicable under different task types. Moreover, this solution only adjusts the working frequency of the CPU, and does not involve the working frequency of the memory such as memory and asynchronous cache, so the optimization of performance and energy efficiency is limited.

Based on the above description, the technical problems to be solved by this application may include the following:

1. The problem that the scheduling-frequency modulation system cannot sustain the target performance and energy efficiency.

2. The DVFS system cannot track the load in a fine-grained manner to iteratively optimize the energy efficiency.

3. The accuracy of the behavior of scheduling-frequency modulation system aiming at target performance and energy efficiency under different task types.

4. The frequency modulation behavior cannot be linked with the storage system to more comprehensively optimize the performance of the entire processor and system energy efficiency.

In order to solve the above technical problems, firstly, the present application provides a device. Please refer to FIG. 1. FIG. 1 is a schematic structural diagram of a device 10 including scheduling and frequency modulation functions provided by an embodiment of the present application. The device 10 may be located in any electronic device, such as a computer, a computer, a mobile phone, a tablet, etc. in the device. Specifically, the device 10 may be a chip or a chip set or a circuit board on which the chip or the chip set is mounted. The chip or chip set or the circuit board on which the chip or chip set is mounted can be driven by necessary software.

The apparatus 10 includes a processor 101 , and a frequency modulation controller 102 , a frequency modulator 103 , an asynchronous buffer 104 and a memory 105 coupled to the processor 101 .

The processor 101 includes one or more processor cores (Core). FIG. 1 takes N (N is an integer greater than 0) processor cores 1011 as an example, including a processor core (Core) 1, a processor core (Core) 2. ... and the processor core (Core) (N-1). Each processor core 1011 includes a load classifier and an operation control unit. The load classifier in each processor core 1011 is used to classify the load in each processor core 1011 . The operation control unit in each processor core 1011 may be used to control the execution and operation of hardware such as load classifiers in each processor core 1011 .

In a possible implementation, the load classifier can also be implemented in software. Optionally, the software-implemented load classifier may be configured in the processor core 1011 or in the frequency modulation controller 102 . If configured in the processor 101 , the load classifier directly obtains the characteristic information of the load classification from the processor core 1011 , classifies the load, and outputs the load classification result to the frequency modulation controller 102 . If configured in the FM controller 102, the load classifier can obtain the load classification feature information from the processor core 1011, and the FM controller 102 performs load classification calculation based on the obtained load classification feature information to obtain the load classification information. The load classification feature information will be introduced later, and will not be described in detail here.

If the processor 101 includes multiple processor cores 1011, the multiple processor cores 1011 may be divided into multiple clusters, and each cluster includes at least one processor core. For example, if the processor 101 includes 8 processor cores 1011, then the 8 processor cores 1011 can be divided into three clusters, two of which can include 3 processor cores 1011, and the remaining one cluster includes 2 processors device core 1011. The operating frequencies of the processor cores in each cluster are the same, that is, the processor cores in each cluster share one operating frequency.

The frequency modulation controller 102 is configured to calculate the optimized frequency of the operating frequency of the relevant components in the device (for example, each processor core 1011, the memory 105, and/or the asynchronous cache 104, etc.) based on the classification result of the above-mentioned load classifier, and then call the frequency regulator 103 to The operating frequency of the related components is adjusted to the corresponding optimized frequency to optimize the performance of the processor and the energy efficiency of the computer system.

The FM controller 102 may be a low-power processor, such as a low-power CPU, a low-power microcontroller (MCU), or a low-power state machine, or the like.

The frequency regulator 103 may obtain the optimal operating frequency of the processor from the frequency regulation controller 102, and then adjust the operating frequency of the above-mentioned one or more processor cores based on the optimal frequency. Optionally, the frequency regulator 103 may also obtain the optimal operating frequencies of the asynchronous cache 104 and the memory 105 from the frequency regulation controller 102, and then adjust the operating frequencies of the asynchronous cache 104 and the memory 105 respectively based on these optimal frequencies.

The frequency modulator 103 may be a dynamic voltage and frequency scaling (DVFS) module or the like.

The memory 105 may include, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read only memory (EPROM), or Portable read-only memory (compact disc read-only memory, CD-ROM), etc.

Optionally, the asynchronous cache 104 may be a cache memory, usually composed of static random access memory (SRAM). Asynchronous cache 104 may include a L3 cache and/or a L4 cache. It should be noted that since the operating frequency of the synchronous cache (such as the L1 cache, etc.) is the same as the operating frequency of the processor core, and the operating frequency of the asynchronous cache 104 is different from that of the processor core 1011, so in this In the application, the operating frequency of the asynchronous cache can be further optimized and adjusted to further optimize the performance of the processor and the energy efficiency of the entire computer system. In addition, in a possible implementation manner, the secondary cache may be a synchronous cache, and in another possible implementation manner, the secondary cache is an asynchronous cache.

Optionally, the memory 105 may be a DDR memory, where the DDR is an abbreviation for double data rate synchronous dynamic random access memory (DDR SDRAM).

At least one of the one or more processor cores (Cores) included in the processor 101 is used to run the task scheduler 106. The task scheduler 106 is implemented by a computer program, and the task scheduler 106 may be a scheduler in an operating system (operating system, OS), and is used to assign task scheduling to the one or more processor cores through the scheduling channel 107 in execution.

As can be seen in FIG. 1, the task scheduler 106 may send frequency modulation constraints to the frequency modulation controller 102, which may be power consumption constraints, performance constraints, or the like. The task scheduler 106 may also obtain scheduling suggestions from the frequency regulation controller 102, and the scheduling suggestions may include suggestions such as load balancing, task migration, or power-on/off policies. For example, when the frequency regulation controller 102 obtains that the processor cores in the same cluster have unbalanced loads or different load types, which are not conducive to optimization, it will send a load balancing suggestion to the task scheduler 106 . Exemplarily, the load balancing suggestion may include information such as the load situation and load type of each processor core in the cluster.

Optionally, the task scheduler 106 may also send a frequency modulation request to the frequency modulator 103, so as to call the frequency modulator 103 to perform frequency modulation.

To sum up, the device 10 provided by the present application decouples hardware frequency modulation control from software thread scheduling, software is responsible for coarse-grained scheduling and provides frequency modulation constraints to hardware; hardware controls fine-grained frequency modulation and provides scheduling advice to software; A combination of fine-tuning and fine-tuning. The combination of the frequency modulation controller and the load classifier in the device 10 provided by the present application can track and iterate the load in a timely manner, increase and decrease the frequency in a timely manner, and optimize energy efficiency and performance in a timely and continuous manner. At the same time, implementing load tracking and frequency modulation control through hardware can effectively reduce software load and overhead. In addition, the FM controller provides FM control of the processor and memory to optimize energy efficiency and performance from a system-wide perspective.

Based on the software and hardware architecture of the above device, in the embodiment of the present application, the specific functions implemented by each component in the device 10 may include the following:

The load classifier in each processor core 1011 is used to classify the load in each processor core 1011 to obtain load classification information, where the load classification information is used to indicate to which the load in each processor core 1011 belongs load type.

In a possible implementation manner, the load classifier may also be configured in the frequency modulation controller 102 to classify the load in each processor core 1011 . This application mainly focuses on configuring the load classifier in the processor core 1011 . For the case where the load classifier is configured in the frequency modulation controller 102, reference may be made to the corresponding description, which will not be repeated in this application.

In a specific embodiment, the load type may include computational type, cache-dependent type, memory-dependent type, idle type, and the like. Wherein, if the processor core only needs to access the first-level cache and/or the second-level cache to obtain the required data in the process of executing the load, then the load is a computational load. If the processor core needs to access the L3 cache and/or the L4 cache to obtain data in the process of executing the load, the load is a cache-dependent load. If the processor core needs to access the memory to obtain data during the execution of the load, the load is a memory-dependent load. When the processor core executes an idle load, that is, when the suspending work is suspended, the type of the load in the processor core 1011 is the idle type.

The following takes the load classifier in the processor core 1011-0 as an example. The load classifier can be a classification algorithm implemented by a hardware circuit or a software program, such as a softmax classification algorithm. The softmax classification algorithm includes a pre-trained The model can take the load classification feature information in the processor core 1011-0 (optionally, it can also include the synchronization cache) as input, and the processor core 1011-0 can be output after the calculation and judgment of the model. The classification information of the load within 0. The load classification feature information includes one or more of clock signal inversions and performance events (events) in the processor core 1011-0 (optionally, may also include in the synchronization buffer). The performance event may include one or more events such as a command and/or a level signal within a preset duration. To facilitate understanding of the load classifier, reference can be made to Figure 2.

FIG. 2 exemplarily shows a schematic structural diagram of a load classifier implemented by a hardware circuit. As can be seen, the load classifier may include a counter 201 , a processing unit 202 and a memory 203 . Wherein, the processing unit 202 may include a multiply-accumulate (multiply accumulate, MAC) unit, a comparison and control unit, and other units for performing operations such as calculation, comparison, and control processing. The memory 203 can be a static random-access memory (static random-access memory, SRAM) or the like. Exemplarily, the load classifier is input to the counter with one or more of the clock signal inversion and the performance event of the above-mentioned processor core 1011-0 (optionally, the synchronization buffer may also be included) within the first preset duration. In 201, it is used to count the number of times the clock signal is flipped and\or the number or duration of performance events within the first preset time period. If the performance event includes instructions within the first preset duration, the counter 201 can be used to count the number of the instructions; if the performance event includes events such as level signals, the counter 201 can be used to count the level signals and other events in the first The duration of the preset duration, etc., and then the front-end execution efficiency within the first preset duration and/or the back-end execution efficiency within the first preset duration can be counted. After the counter 201 completes the statistics of the input within the first preset time period, the statistical results are input into the processing unit 202, and the processing unit 202 obtains information such as pre-trained calculation parameters from the memory 203, and then the processing unit 202 will count the results. Calculate and compare with pre-trained computing parameters and other information, and finally output a specific load type.

The load classifier may periodically classify the load in the processor core 1011-0 using the first preset duration as a period, or may use a second preset duration greater than the first preset duration as cycle. The period may also be called a classification window, then the load classifier periodically classifies the load of the processor core 1011-0 in each classification window to obtain the type of the load in each classification window. The size of the first preset duration and the second preset duration may be 100 microseconds, 10 milliseconds, or 1 second, etc. The present application does not limit the sizes of the first preset duration and the second preset duration.

Optionally, the size of the first preset duration and the second preset duration are configured by the frequency modulation controller 102; or, the size of the first preset duration and the second preset duration are determined by each processor core. The load classifier in 1011 is determined by interrupt triggering the FM controller 102.

The frequency modulation controller 102 is configured to obtain the target load classification information of the first processor core from the first processor core; determine the target frequency of the target object based on the target load classification information; and then call the frequency regulator based on the target frequency 103 Adjust the working frequency of the target object.

The first processor core is one of the above-mentioned one or more processor cores 1011 . As long as the processor core 1011 satisfies the preset condition, the processor core 1011 is the first processor core.

The preset condition is that the load of the processor core 1011 in the first window is greater than the first threshold or less than the second threshold. The first window and the window where the processor core 1011 is located are adjacent windows, and the first window appears first. Optionally, the first window may include one or more classification periods of the foregoing load classifiers, that is, the first window may include one or more of the foregoing classification windows.

The above-mentioned first threshold and second threshold are collectively referred to as a load threshold, and the first threshold is greater than the second threshold. Specifically, the first threshold may be an up-frequency load threshold, and the second threshold may be a down-frequency load threshold. The value of the up-frequency load threshold may be, for example, 70% or 80%, and the value of the down-frequency load threshold may be 50% or 60%, etc. The application does not limit the specific value of the load threshold.

When the load of the processor core 1011 in the first window is greater than the up-frequency load threshold, it indicates that the load of the processor core 1011 is too heavy and the processing speed cannot keep up. The operating frequency corresponding to 1011 is up-converted. When the load of the processor core 1011 in the first window is less than the frequency reduction load threshold, it indicates that the load of the processor core 1011 is light, and such a fast processing speed is not required. The operating frequency corresponding to the core 1011 is down-converted.

In a possible implementation manner, the first thresholds of different processor cores may be the same or different; the second thresholds of different processor cores may be the same or different.

In a possible implementation manner, the first thresholds of the processor cores in the same cluster may be the same, and the second thresholds of the processor cores in the same cluster may be the same; and the first thresholds of the processor cores in different clusters may be the same. The threshold may be different, and the second threshold may be different for processor cores in different clusters.

The above-mentioned target object may include at least one of the first processor core and the memory. The memory includes at least one of a memory and an asynchronous cache. Exemplarily, the memory may be the memory 105 shown in FIG. 1 , and the asynchronous cache may be the asynchronous cache 104 shown in FIG. 1 .

The foregoing load classification information may include a specific type to which a specific load belongs. For example, assuming that the first window includes two classification windows (classification window 1 and classification window 2), then, exemplarily, the load classification information in the first window may be: the load type obtained by classification window 1 is computing The load type obtained by classification window 2 is cache-dependent.

In a specific embodiment, the frequency modulation controller 102 can monitor the load of the above-mentioned one or more processor cores 1011 in each window. Taking the processor core 1011-0 as an example, in the When the load in the first window is greater than the first threshold or less than the second threshold (in this case, the processor core 1011-0 is the above-mentioned first processor core), the FM controller 102 will be triggered based on the first window. According to the load situation, the optimized frequency is calculated, and then the frequency regulator 103 is called for frequency regulation.

The frequency modulation controller 102 can obtain the load amount of the processor core 1011-0 in the first window in various ways, two of which are exemplarily introduced below:

The first method is to obtain the load amount in the first window calculated by the processor core 1011-0 from the processor core 1011-0.

Specifically, the processor core 1011-0 can perceive its own load in the first window. Specifically, the processor core 1011-0 in the first window can know the busy and idle periods of time. Then, by calculating the ratio of the busy duration to the total duration in the window, the load in the first window can be obtained. The total duration in this window is the sum of the busy duration and the idle duration. The busy duration refers to the duration that the processor core 1011-0 needs to process a task for completing a certain target, and the idle duration refers to the duration that the processor core 1011-0 is suspended, that is, the work is suspended. For example, if the total duration of the first window is 10 seconds, the busy duration is 8 seconds, and the idle duration is 2 seconds, then the load in the first window is 8/10=80%. After the processor and 1011-0 calculate the load in the first window, the load can be sent to the frequency modulation controller 102 for further processing.

The second is obtaining real-time load classification information from the load classifier in the processor core 1011-0, and calculating the real-time load of the processor core 1011-0 in the first window based on the real-time load classification information.

Specifically, the FM controller 102 can acquire the load classification information in each window of the load classifier in the processor core 1011-0 in real time, then the FM controller 102 can acquire the load classification information in the processor core 1011-0 in real time The load classification information of the controller in the above-mentioned first window, since the load classification information indicates the load type of each classification window included in the first window, then, calculate the load type except the idle type in the load classification information. The ratio of the number of load types to the total number of load types in the load classification information can obtain the load amount in the first window. For example, assuming that the first window includes 4 classification windows (classification window 1, classification window 2, classification window 3 and classification window 4), the load classification information in the first window is: the load type obtained by classification window 1 is the calculation The load type obtained by the classification window 2 is the cache-dependent type, the load type obtained by the classification window 3 is the computational type, and the load type obtained by the classification window 4 is the idle type. Then, the load in the first window is 3/4=75%.

After acquiring the load amount of the processor core 1011-0 in the first window, the frequency modulation controller 102 compares the load amount with the above-mentioned first threshold and the second threshold respectively, and the processor core 1011-0 is in the first window In the case where the load is greater than the first threshold or less than the second threshold, the target object (including the processor core 1011-0, target frequency of at least one of asynchronous cache 104 and memory 105).

The following describes the process of calculating the target frequency of the target object.

The frequency modulation controller 102 may calculate the load distribution weight according to the load classification information in the first window obtained from the load classifier in the processor core 1011-0. Specifically, the load classification information indicates that the load types of the processor core 1011-0 in the first window include m (where m is an integer greater than 1) load types, then the load distribution weight indicates that among the m types Load ratio for each type. For ease of understanding, examples are given below.

Assuming that the processor core 1011-0 includes 10 classification windows (may be referred to as the 1st classification window, the 2nd classification window, ... and the 10th classification window) in the first window, the load classifier within the 10 classification windows The load classification information obtained after classifying the load of the , the loads in the seventh classification window are memory-dependent loads, and the loads in the eighth and tenth classification windows are idle-type loads. After the FM controller 102 obtains the load classification information, it can be known from statistics that the total number of load types of the processor core 1011-0 in the first window is 10, and then the calculated load distribution weight is: The weight of the computational load is 3/10, cache-dependent loads are weighted 4/10, memory-dependent loads are weighted 1/10, and idle type loads are weighted 2/10.

In addition, the frequency modulation controller 102 also needs to calculate the load scaling ratio, and the target performance can be calculated based on the load scaling ratio, so that the optimal frequency can be found based on the target performance. Specifically, if the load of the processor core 1011-0 in the first window is greater than the first load threshold (the first load threshold may also be referred to as an up-frequency load threshold), then the load scaling ratio is the first load threshold and the ratio of this load. If the load of the processor core 1011-0 in the first window is less than the second load threshold (the second load threshold may also be called the underclocking load threshold), then the load scaling ratio is the second load threshold and the load quantity ratio.

In a possible implementation manner, the performance described in this application may also be that the larger the value, the better the performance. Then, when calculating the load scaling ratio, if the load of the processor core 1011-0 in the first window is greater than the first load threshold, then the load scaling ratio is the ratio of the load amount to the first load threshold. If the load of the processor core 1011-0 in the first window is less than the second load threshold, the load scaling ratio is the ratio of the load to the second load threshold. It should be noted that the method described in the above paragraph of this application is used as an example for introduction.

The frequency modulation controller 102 also needs to acquire the current operating frequency of the target object. In a possible implementation manner, the current operating frequency of the target object can be obtained from the frequency regulator 103, and the current operating frequency of the target object includes the current operating frequency of the processor core 1011-0. The current operating frequency also includes the current operating frequency of the asynchronous cache 104 and/or the memory 105 . In a possible implementation manner, the frequency modulation controller 102 can interact with the processor core running the task scheduler 106 to obtain the current operating frequency of the processor core 1011-0 from the task scheduler 106, and optionally, can also obtain asynchronous Current operating frequency of cache 104 and/or memory 105. Since the task scheduler 106 needs to know the conditions of each processor core, memory and other modules in the processor in order to make task scheduling decisions, the task scheduler 106 can obtain information such as the operating frequency of each processor core and memory in real time.

In another possible implementation manner, the frequency modulation controller 102 may directly interact with the processor core 1011-0 to obtain the current operating frequency of the processor core 1011-0. Optionally, the frequency modulation controller 102 may also interact with the memory, that is, the asynchronous cache 104 and/or the memory 105 to obtain the current operating frequency of the asynchronous cache 104 and/or the memory 105 .

After acquiring the current operating frequency corresponding to the processor core 1011-0, the FM controller 102 acquires the current performance information of the processor 101 based on the current operating frequency, where the current performance refers to the time when the load is processed at the current operating frequency of the target object performance of the processor 101 . Then, target performance information is calculated based on the current performance information and the load scaling ratio calculated above, and then the target frequency of the target object is determined based on the calculated target performance information.

Before introducing the specific process of determining the target frequency of the target object, the frequency-performance mapping table maintained in the frequency modulation controller 102 is introduced below.

Specifically, the frequency-performance relationship mapping table (hereinafter referred to as the mapping table) corresponding to each processor core is maintained in the frequency modulation controller 102, and the mapping table corresponding to each processor core may also include multiple, the multiple The mapping table is a mapping table corresponding to each of the multiple load types.

The frequency-performance mapping table can be obtained by offline training. Specifically, firstly, the load classifier described above can be used to perform offline training and classification for the loads of different processor cores to obtain different load types. Then, for different load types, the performance of processors corresponding to different operating frequencies of processor cores and/or memories is predicted through a linear regression model, thereby establishing frequency-performance mapping tables corresponding to different load types in different processor cores.

Optionally, the above-mentioned linear regression model may include, but is not limited to, a first-order or higher-order polynomial, and the input variables of the model may include, but are not limited to, the frequency value of the operating frequency of the processor core and/or memory, the linear combination of frequency values, the Ratios or normalized frequency values, etc. The linear regression algorithm corresponding to the linear regression model may include, but is not limited to, the least squares method or the least squares method with a regularization term.

It should be noted that the mapping table corresponding to the processor core refers to that the data in the mapping table is applicable to the processor core. The mapping table corresponding to a certain load type records the mapping relationship between the operating frequency of the processor core and the processor performance when the processor core executes the load of this load type; optionally, the mapping table corresponding to the certain load type What can also be recorded in is the mapping relationship between the operating frequency of the memory and the performance of the processor when the processor core executes the load of the load type.

When the mapping table simultaneously records the mapping relationship between the operating frequency of the processor core, the operating frequency of the memory and the processor performance, the operating frequency of the processor sum and the operating frequency of the memory in the mapping table satisfy a certain mapping relationship, so that The performance of the processor can reach an ideal optimized state, and at the same time, the energy efficiency of the entire computer system can also be better optimized.

For ease of understanding, reference may be made to FIG. 3 . In FIG. 3 , the mapping table corresponding to each processor core is exemplarily drawn, and the mapping table corresponding to each processor core also includes mapping tables corresponding to multiple load types. Examples of workloads, cache-dependent workloads, and memory-dependent workloads are shown.

For ease of understanding, reference may be made to Table 1, which exemplarily shows a part of a mapping table of a certain load type.

Table 1

Operating frequency of the processor core/Hz	Memory operating frequency/Hz	Cache operating frequency/Hz	performance
100	50	40	a1
200	50	49	a2
200	50	52	a3
300	50	53	a4
400	55	53	a5
500	51	52	a6

As can be seen in Table 1, the unit of operating frequency is Hertz (Hz). Assuming that Table 1 shows a mapping table of computing loads corresponding to the processor core 1011-0, for example, in Table 1, when the processor core 1011-0 operates at a frequency of 100 Hz, and the memory and cache are The performance of the processor core 1011-0 is a1 when processing a computational load at operating frequencies of 50 Hz and 40 Hz. In addition, the higher the operating frequency of the processor core, the lower the performance, indicating that it takes less time to execute a load, so the performance is better.

Based on the above description, the following describes the specific process of determining the target frequency of the above-mentioned target object. There are two possible implementation manners for this process, which are introduced separately below.

The first possible implementation is to select the load type with the largest weight among the above load distribution weights for calculation.

Specifically, after the frequency modulation controller 102 calculates and obtains the load distribution weight of the processor core 1011-0 in the first window, it can obtain the load type with the largest weight (which may be referred to as the first load type, or the load type with the largest weight is also known as the load type with the largest weight). It can be said that it is the load type that occurs most frequently in the first window), and then the mapping table of the first load type corresponding to the processor core 1011-0 is found. Taking the current operating frequency of the target object obtained above as an index, the performance information mapped to the current operating frequency is found in the mapping table of the first load type, which may be called first performance information, and the first performance information is the processor 101's current performance information.

For example, assuming that the mapping table of the first load type is shown in Table 1, the obtained current operating frequency corresponding to the processor core 1011-0 is: the operating frequency of the processor core 1011-0 is 100 Hz, and the operating frequency of the memory is 50 Hz. If the working frequency of the hertz and the cache is 40 Hz, then compare the working frequencies with the frequencies in Table 1, and finally find the performance information mapped by the frequencies as a1.

After the FM controller 102 finds the first performance information, it can multiply the first performance information by the load scaling ratio calculated above to obtain new performance information, and the new performance is the expected processor core 1011-0 The performance when handling the load of the first load type may also be referred to as the target performance. Then, the operating frequency mapped by the target performance information is searched in the mapping table of the first load type with the target performance information as an index, and the found operating frequency is the optimized frequency.

For example, taking Table 1 as an example, the first performance information found in Table 1 above is a1. Assuming that the load scaling ratio calculated above is 0.84, the target performance information is a1*0.84≈a2. Then, the By comparing a2 with the performance in Table 1, the optimized frequency of the mapping can be found: the optimized operating frequency of the processor core 1011-0 is 300, the optimized operating frequency of the memory is 50, and the optimized operating frequency of the cache is 53.

The second possible implementation is to perform weighted average calculation based on the above load distribution weights.

In a specific embodiment, the FM controller 102 knows that the first window includes m types of loads based on the obtained load classification information of the processor core 1011-0 in the first window, and the m types are specifically: which load types. Then, the frequency modulation controller 102 calculates and processes the m types of loads respectively to obtain m groups of optimal operating frequencies of the target object, and then performs a weighted average of the m groups of optimal operating frequencies based on the load distribution weight to obtain the The target frequency of the target object.

Specifically, first, the frequency modulation controller 102 obtains the i-th performance in the i-th mapping table based on the current operating frequency of the target object obtained above. The i-th mapping table is a mapping table of the i-th load type among the above m types. The value of i is an integer between 1 and m. Then, the frequency modulation controller 102 multiplies the i-th performance by the load scaling ratio calculated above to obtain the i-th target performance information. Then, the ith group of optimized operating frequencies is found in the ith mapping table using the ith target performance information as an index. After the above calculation and processing, the frequency modulation controller 102 obtains m groups of optimal operating frequencies, and then calculates and obtains the above-mentioned target optimal operating frequencies based on the m groups of optimal operating frequencies and the above-mentioned load distribution weight. For ease of understanding, examples are given below.

Assuming that the above m types are computational and cache-dependent, and the weights of the two types are 0.4 and 0.6, respectively, two groups of optimized operating frequencies are obtained after calculation and processing. It is assumed that a set of optimal operating frequencies found in the mapping table of the computing load are: the optimal operating frequency of the processor core is 100 Hz, the optimal operating frequency of the memory is 50 Hz, and the optimal operating frequency of the cache is 40 Hz. It is assumed that a set of optimal operating frequencies found in the mapping table of cached loads are: the optimal operating frequency of the processor core is 200 Hz, the optimal operating frequency of the memory is 50 Hz, and the optimal operating frequency of the cache is 49 Hz. Then, the optimized operating frequency of the processor core in the target frequency is: 100*0.4+200*0.6=2239, the optimized operating frequency of the memory in the target frequency is: 50*0.4+50*0.6=50, the optimization of the cache in the target frequency The working frequency is: 40*0.4+49*0.6=1025.6.

In a possible implementation manner, the above m load types may be some types of multiple types to which the load of the processor core 1011-0 in the first window belongs. For example, it is assumed that the types of loads of the processor core 1011-0 in the first window include three types: computation type, cache-dependent type, and memory-dependent type, and the above-mentioned m loads may only include computation in the three types type and cache-dependent type. In a specific embodiment, the m types may be pre-configured types, that is, the frequency modulation controller 102 may acquire external configuration information, and the configuration information indicates which specific load types the m types are.

In a possible implementation manner, in the above process of looking up the operating frequency mapped by the target performance information in the mapping table using the target performance information as an index, the frequency modulation controller 102 may obtain performance constraints from the task scheduler 106, including But not limited to the first performance threshold, the second performance threshold and the third performance threshold. If the FM controller 102 obtains the first performance threshold from the task scheduler 106, the frequency points whose performance is higher than the first performance threshold in Table 1 will not be used for frequency search; if the FM controller 102 obtains the first performance threshold from the task scheduler If the second performance threshold is obtained in 106, the frequency points whose performance is lower than the second performance threshold in Table 1 will not be used for frequency search; if the frequency modulation controller 102 obtains the third performance threshold from the task scheduler 106, Then the frequency point closest to the third performance threshold in Table 1 will be searched. Doing so allows the processor and/or memory to work under certain performance constraints, while also optimizing the performance of the processor and/or memory and the energy efficiency of the system.

In a possible implementation manner, the above-mentioned mapping table may further include power consumption information, that is, the mapping table may be a frequency-performance-power consumption mapping table.

The frequency-performance-power consumption mapping table is similar to the above-mentioned frequency-performance mapping table, and may be obtained by offline training. Similarly, the load classifier described above can be used to perform offline training and classification for the load of different processor cores to obtain different load types. Then, for different load types, the performance and power consumption of the processor corresponding to different operating frequencies of the processor core and/or memory are predicted through a linear regression model, thereby establishing the frequency-performance corresponding to different load types in different processor cores. - Power consumption mapping table. For the description of the linear regression model, please refer to the previous introduction, which will not be repeated here.

To facilitate the understanding of the above frequency-performance-power consumption mapping table, please refer to Table 2.

Table 2

Operating frequency of the processor core/Hz	Memory operating frequency/Hz	Cache operating frequency/Hz	performance	Power consumption/w
100	50	40	a1	w1
200	50	49	a2	w2
200	50	52	a3	w3
300	50	53	a4	w4
400	55	53	a5	w5
500	51	52	a6	w6

Table 2 exemplarily shows a part of the frequency-performance-power consumption mapping table. Compared with Table 1, there is one more power consumption information in Table 2. Power consumption refers to the energy consumed per unit time. The unit is watt (w). Table 2 lists the corresponding performance and power consumption of the processor when the processor core handles a certain type of load under various corresponding operating frequencies. The greater the operating frequency of the processor core, the greater the corresponding power consumption, indicating that more energy needs to be consumed.

In this case, the frequency modulation controller 102 may also acquire the power consumption constraints on the above-mentioned processor 101, and then look up the optimized frequency of the target object in the mapping table based on the acquired power consumption constraints. For example, taking Table 2 as an example, assuming that the obtained power consumption constraint is w5, then the corresponding optimized operating frequency can be found by searching in Table 2 with w5 as an index: the optimized operating frequency of the processor core is 400 Hz, and the memory The optimized operating frequency is 55 Hz and the optimized operating frequency of the cache is 53 Hz.

In a specific embodiment, the frequency modulation controller 102 may obtain the power consumption constraint of the processor 101 based on one or more of temperature control, thermal design power (TDP) control, and single-core overclocking control. Specifically, the temperature control will give the allocated power consumption quota according to the current temperature and the temperature control target temperature, according to the prediction model or the proportional-integral-differential (Proportional-Integral-Differential, PID) algorithm. TDP is to directly allocate the upper limit of power consumption, the upper limit of power consumption is the power consumption constraint, and the source of TDP can be the configuration of the operating system. Single-core overclocking control is similar to TDP control, and it also directly allocates the upper limit of power consumption.

To sum up, if there is no power consumption constraint, the target frequency of the processed target object can be calculated by adopting any one of the first possible implementation manner and the second possible implementation manner.

If there is a power consumption constraint, if the optimized frequency of the target object obtained based on the power consumption constraint is calculated and processed by using any one of the first possible implementation manner and the second possible implementation manner above The optimization frequency of the target object is the same, then, the target frequency of the target object is still the optimization frequency obtained by calculation and processing using any one of the first possible implementation manner and the second possible implementation manner.

If the optimized frequency of the target object obtained based on the power consumption constraint is different from the optimized frequency of the target object obtained by calculation and processing using any of the first possible implementation manner and the second possible implementation manner, Then, the target frequency of the target object is the optimized frequency obtained based on the power consumption constraint. This is because the power consumption constraint has a higher priority, and the processor core needs to work under the condition that the power consumption constraint is satisfied.

In a possible implementation manner, for the above-mentioned frequency-performance-power consumption mapping table, the power consumption in the mapping table is the fixed chip corner (chip corner refers to the process of chip making due to materials and/or welding, gluing, etc.) (deviation caused by other operations) and a fixed ambient temperature, but the actual power consumption is affected by the ambient temperature and the chip corner, and there will be changes. Therefore, the power consumption of the processor can be obtained in real time to analyze the power consumption data in the mapping table. Minor corrections to improve data accuracy.

Optionally, the frequency modulation controller 102 may acquire real-time power consumption from a power sensor (power sensor) in real time, and then update the acquired power consumption to a corresponding frequency-performance-power consumption mapping table. The power consumption sensor can detect the power consumption of the processor in real time, and send the detected power consumption to the frequency modulation controller 102 . For ease of understanding, examples are given below.

Taking the data in Table 2 as an example, suppose that Table 2 is the mapping table of the computing load corresponding to the processor core 1011-0. The operating frequency of the processor core 1011-0 is 100 Hz, and the operating frequency of the memory 105 is 50 Hz. Hertz, when the operating frequency of the asynchronous cache 104 is 40 Hz, the power consumption of the processor 101 is limited to w1 when the processor core 1011-0 processes the computing load. Due to the influence of the ambient temperature, etc., in the process of processing the computing load by the processor core 1011-0, the power consumption sensor actually detects that the size of the power consumption constraint of the processor 101 is w1'. Then, after obtaining the detected power consumption constraint size from the power consumption sensor, the frequency modulation controller 102 sets the working frequency of the processor core in Table 2 to 100 Hz, the working frequency of the memory 105 to 50 Hz, and the working frequency of the asynchronous cache 104 to be 100 Hz. The power consumption mapped at a frequency of 40 Hz is updated to w1', and the updated mapping can be found in Table 3.

table 3

Operating frequency of the processor core/Hz	Memory operating frequency/Hz	Cache operating frequency/Hz	performance	Power consumption/w
100	50	40	a1	w1'
200	50	49	a2	w2
200	50	52	a3	w3
300	50	53	a4	w4
400	55	53	a5	w5
500	51	52	a6	w6

Optionally, the frequency modulation controller 102 may also acquire the real-time power consumption of the processor by establishing a power consumption acquisition model, and then update the acquired real-time power consumption into the corresponding mapping table.

To sum up, the performance and energy efficiency of the processor cores corresponding to different load types are different. Therefore, this application starts from the load type, and considers the frequency, performance and power consumption (ie energy efficiency), so as to match the processor cores. A more reasonable and accurate operating frequency can better optimize the performance and energy efficiency of the processor core.

In addition, the operating frequency of the cache and memory can also be optimized in this application. Since only optimizing the operating frequency of the processor core can improve performance and energy consumption to a limited extent, optimizing the operating frequency of the cache and memory at the same time can further improve processing. The performance and energy efficiency of the core can better adapt to various types of load tasks, meet the needs of different load tasks, reduce system freezes and improve system energy efficiency.

In addition, the present application obtains the target frequency through the above-mentioned frequency-performance mapping table or frequency-performance-power consumption mapping table. Since these mapping tables are the optimal solution sets obtained by offline training and satisfying various constraints, the obtained target frequency The frequency is more ideal, and better performance and energy efficiency can be achieved by processing the load based on the target frequency obtained.

Based on the above description, the frequency modulation controller 102 can acquire the target frequency of a processor core. Based on the above description of FIG. 1 , in the case where the processor 101 includes multiple processor cores 1011 , the multiple processor cores 1011 can be divided into multiple clusters, and the operating frequency of the processor cores in each cluster same. Based on this, if in the cluster where the processor core 1011-0 is located, the load of other processor cores except the processor core 1011-0 in the first window is also greater than the first threshold or less than the second threshold, That is, the other processor core is also the first processor core, and the frequency modulation controller 102 is also triggered to calculate the optimized frequency based on the load condition of each processor core in the other processor cores within the first window to obtain the frequency modulation controller 102. The target frequency of each processor.

Then, for the cluster where the processor core 1011-0 is located, the frequency modulation controller 102 obtains the target frequencies of multiple processor cores, but the operating frequencies of the processor cores in each cluster are the same (for the convenience of description, it can be called a processor The optimized operating frequency of the processor core in the cluster where the core 1011-0 is located is the first optimized operating frequency), so the first optimized operating frequency needs to be determined from the target frequencies of the plurality of processor cores. The frequency modulation controller 102 may arbitrate based on the target frequencies of the plurality of processor cores.

In a possible implementation manner, the frequency modulation controller 102 may select the maximum frequency among the target frequencies of the plurality of processor cores as the first optimized operating frequency.

In another possible implementation manner, the frequency modulation controller 102 may select the minimum frequency among the target frequencies of the multiple processor cores as the first optimized operating frequency.

In another possible implementation manner, the frequency modulation controller 102 takes the average value of the target frequencies of the plurality of processor cores as the above-mentioned first optimized operating frequency.

After determining the above-mentioned first optimal operating frequency, the frequency modulation controller 102 sends the first optimal operating frequency to the frequency regulator 103, and the frequency regulator 103 adjusts the operating frequency of the processor cores in the cluster where the processor core 1011-0 is located to be the The first optimizes the operating frequency.

In a possible implementation manner, if only some of the processor cores in the cluster where the processor core 1011-0 is located are the above-mentioned first processor core, the frequency modulation controller 102 only calculates each The target frequency of the processor core. One or more processor cores other than the part of the first processor core in the cluster where the processor core 1011-0 is located may be referred to as a second processor core. In order to determine the first optimized operating frequency of the cluster, the frequency modulation controller 102 may be based on the target frequency of each processor core in the part of the first processor core (hereinafter referred to as multiple optimized frequencies), and based on the second processor core The current operating frequency of the core is arbitrated.

In a possible implementation manner, the frequency modulation controller 102 may select the largest frequency from the above-mentioned multiple optimal frequencies and the current operating frequency of the second processor core as the above-mentioned first optimal operating frequency.

In another possible implementation manner, the frequency modulation controller 102 may select the minimum frequency from the above-mentioned multiple optimal frequencies and the current operating frequency of the second processor core as the above-mentioned first optimal operating frequency.

In another possible implementation manner, the frequency modulation controller 102 may take the average value of the above-mentioned multiple optimal frequencies and the current operating frequency of the second processor core as the above-mentioned first optimal operating frequency.

After determining the above-mentioned first optimal operating frequency, the frequency modulation controller 102 sends the first optimal operating frequency to the frequency regulator 103, and the frequency regulator 103 adjusts the operating frequency of the processor cores in the cluster where the processor core 1011-0 is located to be the The first optimizes the operating frequency.

It should be noted that the above only takes the processor core 1011-0 and the cluster where the processor core 1011-0 is located as an example. 0 and the description of the cluster where the processor core 1011-0 is located will not be repeated.

In a possible implementation, if the target object includes the memory, the frequency modulation controller 102 also calculates the target frequency of the memory, and can call the frequency modulator 103 to adjust the operating frequency of the memory based on the target frequency of the memory. As for the memory, whether it is the asynchronous cache 104 or the memory 105, it is shared by the multiple processor cores 1011 included in the processor 101, so both the asynchronous cache 104 and the memory 105 have only one operating frequency. In the following, the asynchronous cache 104 is used as an example for introduction. For the related description of the memory 105, reference may also be made to the introduction of the asynchronous cache 104, and details are not repeated here.

If there are multiple first processor cores in the above-mentioned first window, the frequency modulation controller 102 may calculate and obtain the corresponding target frequency based on the load conditions of the multiple first processor cores in the first window. The target frequency corresponding to each of the plurality of first processor cores includes a target frequency of the asynchronous cache 104 .

If the plurality of first processor cores include all processor cores in the processor 101 , the frequency modulation controller 102 may determine an optimal frequency from the plurality of target frequencies in the asynchronous cache 104 , and the optimal frequency may be referred to as a second optimal frequency working frequency.

In a possible implementation manner, the frequency modulation controller 102 may select the largest frequency from the multiple target frequencies of the asynchronous buffer 104 as the second optimized operating frequency.

In another possible implementation manner, the frequency modulation controller 102 may select the minimum frequency from the multiple target frequencies of the asynchronous buffer 104 as the second optimized operating frequency.

In another possible implementation manner, the frequency modulation controller 102 may take the average value of multiple target frequencies in the asynchronous buffer 104 as the second optimized operating frequency.

If the plurality of first processor cores include some of the processor cores in the processor 101 , the frequency modulation controller 102 may determine the second optimal operating frequency from the plurality of target frequencies of the asynchronous buffer 104 and the current operating frequency of the asynchronous buffer 104 .

In a possible implementation manner, the frequency modulation controller 102 may select the largest frequency from the multiple target frequencies of the asynchronous buffer 104 and the current operating frequency of the asynchronous buffer 104 as the second optimized operating frequency.

In another possible implementation, the frequency modulation controller 102 may select the minimum frequency from the multiple target frequencies of the asynchronous buffer 104 and the current operating frequency of the asynchronous buffer 104 as the second optimized operating frequency.

In another possible implementation, the frequency modulation controller 102 may take the average value of the multiple target frequencies of the asynchronous buffer 104 and the current operating frequency of the asynchronous buffer 104 as the second optimized operating frequency.

After determining the second optimal operating frequency, the frequency modulation controller 102 sends the second optimal operating frequency to the frequency regulator 103 , and the frequency regulator 103 adjusts the operating frequency of the asynchronous buffer 104 to be the second optimal operating frequency.

To facilitate understanding of the various operations performed by the FM controller 102, reference may be made to FIG. 4 and FIG. 5 . FIG. 4 takes the processor 101 including 8 processor cores 1011 as an example. The 8 processor cores are divided into three clusters, wherein the processor cores (cores) 0 to 2 are the first cluster, and the processor cores (core) 3 To 5 is the second cluster, and processors (cores) 6 and 7 are the third cluster. FIG. 4 shows the connection relationship between the processor cores of the three clusters and the corresponding processing channels in the FM controller 102 , and also shows the arbitration of the operating frequency of the processor cores among the clusters and the overall control of the operating frequency of the memory. Process schematic. Fig. 5 takes the processor core (core) 0 as an example to illustrate the process that the frequency modulation controller 102 included in the corresponding processing channel obtains the target frequency corresponding to the processor core based on the load condition of the processor core.

In the processing channel of the processor core (core) 0 shown in FIG. 5 , the FM controller 102 first obtains the external configuration information of the first window size and the configuration information of the load type, and then performs load classification analysis based on these information, that is, the The load classification information obtained from the processor core (core) 0 is analyzed and processed. It can be known from the foregoing description that the size of the first window may include one or more classification windows of the load classifier in the processor core (core) 0 . The configuration information of the load type mainly includes the above m types of information.

Then, the frequency modulation controller 102 calculates the load amount, load scaling ratio and load distribution weight of the processor core (core) 0, obtains the current operating frequency corresponding to the processor core (core) 0, and queries the mapping table based on the current operating frequency to obtain The current performance is then calculated based on the load scaling ratio and the load distribution weight to obtain the target frequency corresponding to the processor core (core) 0.

Assuming that the eight processor cores in FIG. 4 all satisfy the frequency adjustment conditions, that is, the above preset conditions are satisfied, then the frequency modulation controller 102 processes each processor core to obtain the target frequency corresponding to each processor core. Then, based on these target frequencies, a final frequency for adjustment is determined for each cluster, and a final frequency for adjustment is determined for the memory, and the determined frequency is sent to the frequency modulator 103, which is based on the received frequency. Frequency adjusts the operating frequency of each cluster and the operating frequency of the memory.

In addition, after the steps of querying and processing the mapping table and the arbitration of the operating frequency of the processor cores between clusters, the frequency modulation controller 102 may send a power-on/off suggestion for the corresponding processor core to the task scheduler. In addition, after the working frequency arbitration of the processor cores among the clusters, the frequency modulation controller 102 may send a load balancing suggestion and the like to the task scheduler.

For the specific implementation of the steps shown in FIG. 4 and FIG. 5 , refer to the above detailed description based on FIG. 1 , and details are not repeated here.

Please refer to FIG. 6 , which is a schematic flowchart of a processing method provided by an embodiment of the present invention, and the processing method can be applied to a processing apparatus. The processing device may include a processor, a frequency modulation controller and a frequency modulator, the processor including a first processor core. Exemplarily, the processing apparatus may be the apparatus 10 shown in FIG. 1 , and the first processor core may be any one of the multiple processor cores shown in FIG. 1 . The method includes but is not limited to the following steps:

S601. Acquire at least one load type of the first processor core through the frequency modulation controller.

S602: Determine, by the frequency modulation controller, a target frequency of a target object based on the at least one load type; the target object includes a memory.

S603 , using the frequency modulation controller to call the frequency modulator based on the target frequency to adjust the working frequency of the target object.

In a possible implementation manner, the above-mentioned memory includes at least one of a memory and an asynchronous cache.

In a possible implementation manner, the above load types include computational loads, cache-dependent loads, and memory-dependent loads.

In a possible implementation manner, the above-mentioned target object further includes the above-mentioned first processor core; the above-mentioned method further includes: performing the following operations through the above-mentioned frequency modulation controller:

Based on the target frequency of the first processor core, the frequency regulator is called to adjust the operating frequency of the first processor core, and there is a mapping relationship between the target frequency of the first processor core and the target frequency of the memory.

In a possible implementation manner, the above-mentioned processor further includes at least one second processor core, and the above-mentioned first processor core and the above-mentioned at least one second processor core form a cluster; the above-mentioned method further includes: using the above-mentioned frequency modulation controller according to the The target frequency of the first processor core determines the operating frequency of the cluster.

In a possible implementation manner, the above-mentioned processor includes n above-mentioned first processor cores, and the above-mentioned n is a positive integer; the above-mentioned method further includes: performing the following operations through the above-mentioned frequency modulation controller:

Determine a target frequency of the memory for at least one load type of each of the first processor cores; determine the optimal operating frequency of the memory based on the n target frequencies of the memory; call the frequency regulator to adjust the operating frequency of the memory to the above Optimize operating frequency.

In a possible implementation manner, the above-mentioned processing apparatus further includes a load classifier, and the above-mentioned method further includes:

Obtain the load classification feature information in the first processor core through the load classifier, and classify the load in the first processor core based on the load classification feature information to obtain the at least one load type; The above-mentioned at least one load type is obtained from the above-mentioned load classifier.

In a possible implementation manner, the load classification feature information includes clock signal inversion information in the first processor core.

In a possible implementation, the above method also includes:

Obtaining the load amount of the first processor core through the frequency regulation controller; the determining the target frequency of the target object based on the at least one load type includes: when the load amount satisfies a preset condition, determining the above-mentioned at least one load type target frequency.

In a possible implementation manner, the above-mentioned determination of the above-mentioned target frequency based on the above-mentioned at least one load type includes:

Based on the current operating frequency of the target object, the current performance information of the processor is searched in the first mapping table corresponding to the first load type, where the first mapping table includes the mapping between the operating frequency of the target object and the performance information of the processor relationship; the above-mentioned first load type is the type with the most occurrences among the above-mentioned at least one load type; the above-mentioned current performance information is adjusted based on the above-mentioned load amount to obtain target performance information; based on the above-mentioned target performance information, look up in the above-mentioned first mapping table For the first target frequency of the target object, the first target frequency is taken as the target frequency of the target object.

In a possible implementation manner, the above-mentioned first mapping table further includes a mapping relationship between the operating frequency of the above-mentioned target object and the power consumption of the above-mentioned processor; the above-mentioned method further includes: performing the following operations through the above-mentioned frequency modulation controller:

Based on the power consumption constraint of the processor, the second target frequency of the target object is searched in the first mapping table; when the first target frequency and the second target frequency are different, the target frequency of the target object is determined as the above-mentioned second target frequency.

In a possible implementation manner, the above-mentioned at least one load type is m load types, and the above-mentioned m is an integer greater than 1; each type of the above-mentioned m load types corresponds to a mapping table, and the above-mentioned mapping table includes the above-mentioned target object. The mapping relationship between the operating frequency and the performance information of the above-mentioned processor; the above-mentioned determination of the above-mentioned target frequency based on the above-mentioned at least one load type includes:

Based on the current working frequency of the target object, a current performance information of the processor is searched in each of the above mapping tables; based on the above load, the m pieces of current performance information are adjusted to obtain m pieces of target performance information; The target performance information is to find m groups of first optimized frequencies of the target object in the above m mapping tables; based on the load distribution weights of the above m load types, the above m groups of first optimized frequencies are processed to obtain a third target frequency, and the above The third target frequency is used as the target frequency of the target object, and the load distribution weight indicates the proportion of the load of each of the m types.

In a possible implementation manner, the above-mentioned m mapping tables further include a mapping relationship between the operating frequency of the above-mentioned target object and the power consumption of the above-mentioned processor; the above-mentioned method further includes: performing the following operations through the above-mentioned frequency modulation controller:

Based on the power consumption constraints of the processor, the m groups of second optimized frequencies of the target object are respectively searched in the m mapping tables; the m groups of second optimized frequencies are processed based on the load distribution weight to obtain the fourth optimal frequency of the target object target frequency; when the third target frequency and the fourth target frequency are different, determine the target frequency of the target object as the fourth target frequency.

It should be noted that, for the specific flow of the processing method described in FIG. 6 and possible implementations thereof, reference may be made to the relevant descriptions in the embodiments described in FIG. 1 to FIG. 5 , and details are not repeated here.

The present application provides a computer program, the computer program including instructions, when executed by the computer program processor, enables the processor to execute the processing method flow described in any one of the above-mentioned FIG. 6 and its possible implementation manners.

The above are only a few embodiments of the present invention, and those skilled in the art can make various changes or modifications to the present invention according to the disclosure of the application documents without departing from the spirit and scope of the present invention. For example, the specific shape or structure of each component in the drawings of the embodiments of the present invention can be adjusted according to actual application scenarios.

In the several embodiments provided in this application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented. On the other hand, the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.

In the above-mentioned embodiments, it may be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented in software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer may be a general purpose computer, special purpose computer, computer network, or other programmable device. The computer instructions may be stored in or transmitted over a computer-readable storage medium. The computer instructions can be sent from a website site, computer, server, or data center via wired (eg, coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (eg, infrared, wireless, microwave, etc.) another website site, computer, server or data center for transmission. The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that includes an integration of one or more available media. The available media may be magnetic media (eg, floppy disks, hard disks, magnetic tapes), optical media (eg, digital versatile discs (DVDs)), or semiconductor media (eg, solid state disks (SSDs)) )Wait.

Claims (27)

1. A processing device, characterized in that the processing device comprises a processor, a frequency modulation controller and a frequency regulator, the processor comprises a first processor core; the frequency modulation controller is used for:

   obtaining at least one load type of the first processor core;

   A target frequency of a target object is determined based on the at least one load type; the target object includes a memory;

   The frequency modulator is called based on the target frequency to adjust the operating frequency of the target object.
2. The apparatus of claim 1, wherein the memory comprises at least one of a memory and an asynchronous cache.
3. The apparatus according to claim 1 or 2, wherein the target object further comprises the first processor core; the frequency modulation controller is further configured to:

   The frequency regulator is called to adjust the operating frequency of the first processor core based on the target frequency of the first processor core, and there is a mapping relationship between the target frequency of the first processor core and the target frequency of the memory.
4. The device of claim 3, wherein:

   The processor further includes at least one second processor core, and the first processor core and the at least one second processor core form a cluster;

   The frequency modulation controller is further configured to determine the operating frequency of the cluster according to the target frequency of the first processor core.
5. The apparatus according to any one of claims 1 to 4, wherein the processor comprises n of the first processor cores, and n is a positive integer; the frequency modulation controller is further configured to:

   determining a target frequency of the memory for at least one load type of each of the first processor cores;

   determining an optimal operating frequency of the memory based on the n target frequencies of the memory;

   Invoke the frequency regulator to adjust the working frequency of the memory to the optimized working frequency.
6. The device according to any one of claims 1 to 5, wherein the device further comprises:

   a load classifier, configured to obtain load classification feature information in the first processor core, and classify the load in the first processor core based on the load classification feature information to obtain the at least one load type;

   The frequency modulation controller is specifically configured to: acquire the at least one load type from the load classifier.
7. The apparatus according to claim 6, wherein the load classification characteristic information comprises clock signal inversion information in the first processor core.
8. The device according to any one of claims 1 to 7, wherein the frequency modulation controller is further configured to:

   obtaining the load of the first processor core;

   The target frequency is determined based on the at least one load type when the load amount satisfies a preset condition.
9. The device according to claim 8, wherein the frequency modulation controller is specifically used for:

   Based on the current operating frequency of the target object, the current performance information of the processor is searched in the first mapping table corresponding to the first load type, where the first mapping table includes the operating frequency of the target object and the processor's current performance information. A mapping relationship of performance information; the first load type is the type with the most occurrences in the at least one load type;

   adjusting the current performance information based on the load to obtain target performance information;

   The first target frequency of the target object is searched in the first mapping table based on the target performance information, and the first target frequency is used as the target frequency of the target object.
10. The apparatus according to claim 9, wherein the first mapping table further includes a mapping relationship between the operating frequency of the target object and the power consumption of the processor;

    The FM controller is also used for:

    looking up the second target frequency of the target object in the first mapping table based on the power consumption constraint of the processor;

    When the first target frequency and the second target frequency are different, the target frequency of the target object is determined to be the second target frequency.
11. The apparatus according to claim 8, wherein the at least one load type is m load types, and the m is an integer greater than 1; each type of the m load types corresponds to a mapping table, and the The mapping table includes the mapping relationship between the operating frequency of the target object and the performance information of the processor; the frequency modulation controller is specifically used for:

    Searching for a current performance information of the processor in each of the mapping tables based on the current operating frequency of the target object;

    respectively adjusting the m pieces of current performance information based on the load to obtain m pieces of target performance information;

    looking up m groups of first optimization frequencies of the target object in the m mapping tables based on the m target performance information;

    The m groups of first optimized frequencies are processed based on the load distribution weights of the m load types to obtain a third target frequency, and the third target frequency is used as the target frequency of the target object, and the load distribution weight indicates The proportion of the load for each of the m types.
12. The device according to claim 11, wherein the m mapping tables further include a mapping relationship between the operating frequency of the target object and the power consumption of the processor;

    The FM controller is also used for:

    looking up m groups of second optimized frequencies of the target object in the m mapping tables respectively based on the power consumption constraints of the processor;

    processing the m groups of second optimized frequencies based on the load distribution weight to obtain the fourth target frequency of the target object;

    When the third target frequency and the fourth target frequency are different, the target frequency of the target object is determined to be the fourth target frequency.
13. The apparatus according to any one of claims 1-12, wherein the load types include computing loads, cache-dependent loads, and memory-dependent loads.
14. A processing method, characterized in that the method is applied to a processing device, the processing device includes a processor, a frequency modulation controller and a frequency modulator, the processor includes a first processor core; the method includes: The FM controller performs the following operations:

    obtaining at least one load type of the first processor core;

    A target frequency of a target object is determined based on the at least one load type; the target object includes a memory;

    The frequency modulator is called based on the target frequency to adjust the operating frequency of the target object.
15. The method of claim 14, wherein the memory comprises at least one of a memory and an asynchronous cache.
16. The method according to claim 14 or 15, wherein the target object further comprises the first processor core; the method further comprises: performing the following operations through the frequency modulation controller:

    The frequency regulator is called to adjust the operating frequency of the first processor core based on the target frequency of the first processor core, and there is a mapping relationship between the target frequency of the first processor core and the target frequency of the memory.
17. The method of claim 16, wherein the processor further comprises at least one second processor core, and the first processor core and the at least one second processor core form a cluster; the method Also includes:

    The operating frequency of the cluster is determined by the frequency modulation controller according to the target frequency of the first processor core.
18. The method according to any one of claims 14 to 17, wherein the processor comprises n of the first processor cores, and n is a positive integer; the method further comprises: adjusting the frequency by the frequency modulation The controller does the following:

    determining a target frequency of the memory for at least one load type of each of the first processor cores;

    determining an optimal operating frequency of the memory based on the n target frequencies of the memory;

    Invoke the frequency regulator to adjust the working frequency of the memory to the optimized working frequency.
19. The method according to any one of claims 14 to 18, wherein the processing device further comprises a load classifier, and the method further comprises:

    Obtain load classification feature information in the first processor core by the load classifier, and classify the load in the first processor core based on the load classification feature information to obtain the at least one load type;

    The at least one load type is obtained from the load classifier by the frequency modulation controller.
20. The method according to claim 19, wherein the load classification characteristic information comprises clock signal inversion information in the first processor core.
21. The method according to any one of claims 14 to 20, wherein the method further comprises:

    Obtain the load amount of the first processor core through the frequency modulation controller;

    The determining the target frequency of the target object based on the at least one load type includes:

    The target frequency is determined based on the at least one load type when the load amount satisfies a preset condition.
22. The method of claim 21, wherein the determining the target frequency based on the at least one load type comprises:

    Based on the current operating frequency of the target object, the current performance information of the processor is searched in the first mapping table corresponding to the first load type, where the first mapping table includes the operating frequency of the target object and the processor's current performance information. A mapping relationship of performance information; the first load type is the type with the most occurrences in the at least one load type;

    adjusting the current performance information based on the load to obtain target performance information;

    The first target frequency of the target object is searched in the first mapping table based on the target performance information, and the first target frequency is used as the target frequency of the target object.
23. The method according to claim 22, wherein the first mapping table further includes a mapping relationship between the operating frequency of the target object and the power consumption of the processor; the method further comprises: using the The FM controller performs the following operations:

    looking up the second target frequency of the target object in the first mapping table based on the power consumption constraint of the processor;

    When the first target frequency and the second target frequency are different, the target frequency of the target object is determined to be the second target frequency.
24. The method according to claim 21, wherein the at least one load type is m load types, and the m is an integer greater than 1; each type of the m load types corresponds to a mapping table, and the The mapping table includes the mapping relationship between the operating frequency of the target object and the performance information of the processor;

    The determining of the target frequency based on the at least one load type includes:

    Searching for a current performance information of the processor in each of the mapping tables based on the current operating frequency of the target object;

    respectively adjusting the m pieces of current performance information based on the load to obtain m pieces of target performance information;

    looking up m groups of first optimization frequencies of the target object in the m mapping tables based on the m target performance information;

    The m groups of first optimized frequencies are processed based on the load distribution weights of the m load types to obtain a third target frequency, and the third target frequency is used as the target frequency of the target object, and the load distribution weight indicates The proportion of the load for each of the m types.
25. The method according to claim 24, wherein the m mapping tables further include a mapping relationship between the operating frequency of the target object and the power consumption of the processor; the method further comprises: using the The FM controller performs the following operations:

    looking up m groups of second optimized frequencies of the target object in the m mapping tables respectively based on the power consumption constraints of the processor;

    processing the m groups of second optimized frequencies based on the load distribution weight to obtain the fourth target frequency of the target object;

    When the third target frequency and the fourth target frequency are different, the target frequency of the target object is determined to be the fourth target frequency.
26. The method according to any one of claims 14-25, wherein the load types include computational loads, cache-dependent loads, and memory-dependent loads.
27. An electronic device, comprising: the processing device according to any one of claims 1 to 13, and a discrete device coupled to the processing device.

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