WO2022141427A1 - Chip, chip packaging structure, and electronic device - Google Patents

Abstract

Embodiments of the present application relate to the technical field of semiconductors and provide a chip, a chip packaging structure, and an electronic device, where in a manufacturing process of a chip, utilizing an existing metal layer as a connection point between a TSV structure and a chip internal circuit avoids the addition of a TSV technical process, thereby reducing the manufacturing costs of a chip. The chip comprises a substrate and a first metal layer arranged above the substrate; a TSV structure is arranged within the substrate; the TSV structure is a structure formed from filling a conductive material within a through hole after etching and drilling a bottom portion of the substrate; and the first metal layer comprises first metal wiring and second metal wiring; wherein the first metal wiring is used for connecting an internal circuit of the chip; and the second metal wiring is used for connecting a first end of the TSV structure.

Description

Chip, chip package structure and electronic equipment technical field

The present application relates to the field of semiconductor technology, and in particular, to a chip, a chip packaging structure and an electronic device.

Background technique

Through silicon via (TSV) packaging technology is a three-dimensional (3 dimensions, 3D) integrated circuit packaging technology. This technology drills holes on the back of the chip and fills the etched through holes with conductive materials as a TSV structure so that external signals can be connected to the internal circuits of the chip through the TSV structure in the backside of the chip. When the TSV structure is connected to the internal circuit of the chip, the TSV pad is generally used as its connection point.

At present, in chips using TSV packaging technology, special layers required by TSV pads are generally added as TSV pads in the chip manufacturing process. The special level required for adding TSV pads in the chip manufacturing process needs to be introduced into the TSV process, and the manufacturing process of ordinary chips cannot be used, which increases the manufacturing cost of the chip.

SUMMARY OF THE INVENTION

Embodiments of the present application provide a chip, a chip packaging structure, and an electronic device. During the manufacturing process of the chip, the existing metal layer is used as the connection point between the TSV structure and the internal circuit of the chip, so as to avoid increasing the TSV process, thereby reducing the cost of the chip. cost of production.

To achieve the above object, the application adopts the following technical solutions:

In a first aspect, an embodiment of the present application provides a chip. The chip includes a substrate and a first metal layer disposed over the substrate. A TSV structure is provided in the substrate. The TSV structure refers to a structure formed by etching a drill hole from the bottom of the substrate and filling the etched through hole with a conductive material. The first metal layer includes a first metal trace and a second metal trace. Wherein, the first metal trace is used to connect the internal circuit of the chip. The second metal trace is used to connect the first end of the TSV structure.

Based on the chip described in the first aspect, in the chip, a TSV structure is formed by etched and drilled from the bottom of the substrate and filled with conductive material, and the existing metal layer above the substrate, such as metal traces in the first metal layer, is used as the chip The connection point between the internal circuit and the TSV structure can avoid adding other processes in the chip manufacturing process, such as the TSV process, thereby reducing the manufacturing cost of the chip and improving the manufacturing efficiency of the chip.

Optionally, the internal circuit of the chip may include a current source, and the current source may include a first transistor and a second transistor. The first metal trace may be used to connect the first transistor and the second transistor. In this way, each transistor in the internal circuit can be connected through the first metal wiring.

In a possible implementation manner, a second metal layer may be disposed above the first metal layer. The second metal layer may include third metal traces. The third metal wiring is connected to the second metal wiring through the via hole. The second metal wiring is a metal sheet M1, the third metal wiring is a metal sheet M2, and a plurality of holes are provided on both the metal sheet M1 and the metal sheet M2. In this way, the requirements for metal density in chip design rules can be met, and the influence of structural stress on the bulge and depression of metal traces in the metal layer can be reduced, and the stability and reliability of the chip can be improved.

Further, the holes on the metal sheet M1 and the holes on the metal sheet M2 are arranged in a staggered manner, and the merged area where the metal sheet M1 and the metal sheet M2 are overlapped covers the TSV structure. In this way, in the process of chip packaging, when the substrate is etched and drilled, the etching solution of the drilling hole can be effectively blocked, and the excessive corrosion of the internal structure of the chip by the etching solution can be prevented, so as to ensure that the metal in the first metal layer can escape. The good contact between the wire and the TSV structure improves the stability and reliability of the chip.

In a possible implementation manner, a third metal layer may be disposed above the second metal layer. The third metal layer may include fourth metal traces. The fourth metal wiring is connected to the third metal wiring through the via hole. The fourth metal wiring is a metal sheet M3, and the metal sheet M3 is provided with a plurality of holes. In this way, the influence of the structural stress of the metal layer on the chip can be further reduced, the good contact between the metal wires and the good contact between the metal wires and the TSV structure can be further ensured, and the reliability of the chip can be further improved.

Further, the holes on the metal sheet M1 , the metal sheet M2 and the metal sheet M3 are arranged in a staggered manner, and the merged area where the metal sheet M1 , the metal sheet M2 and the metal sheet M3 overlap can cover the TSV structure. In this way, the influence of the etching solution on the internal structure of the chip during the etching process can be further prevented, thereby improving the stability and reliability of the chip.

In a possible implementation manner, a fourth metal layer may be provided on the third metal layer. The fourth metal layer includes fifth metal traces. The fifth metal wiring is connected to the fourth metal wiring through the via hole. The fifth metal wiring includes a metal sheet M4, and the metal sheet M4 is provided with a plurality of holes. In this way, the influence of the structural stress of the metal layer on the chip can be further reduced, the good contact between the metal wires and the good contact between the metal wires and the TSV structure can be further ensured, and the reliability of the chip can be further improved.

Further, the holes on the metal sheet M3 and the holes on the metal sheet M4 are staggered, and the merged area where the metal sheet M3 and the metal sheet M3 are overlapped covers the TSV structure. In this way, when the substrate is etched during the chip packaging process, the etching solution for etching the drilling hole can be further blocked, and the stability and reliability of the chip can be further improved.

Optionally, the upper part of the substrate is provided with an N-type well, and the N-type well surrounds the TSV structure. A deep N-type well is also arranged below the N-type well, and the TSV structure passes through the deep N-type well and extends to the first metal layer, so that the TSV structure is located in an independent P-type substrate. The N-type well is provided with a first via hole; the P-type substrate is provided with a second via hole. In this way, the TSV structure fabricated in the packaging process of the chip can be located in an independent P-type substrate, so that the TSV area where the TSV structure is located can form an isolation effect from the circuit area, so as to reduce the interference between signals and improve the performance and performance of the chip. reliability.

Optionally, the upper part of the substrate is provided with an N-type well, and the TSV structure passes through the deep N-type well and extends to the first metal layer, so that the TSV structure is located in an independent N-type substrate. A first via hole is provided on the N-type well. In this way, the TSV structure fabricated in the packaging process of the chip can be located in an independent N-type substrate, so as to form an isolation effect between the TSV area where the TSV structure is located and the circuit area, so as to reduce the interference between signals and improve the performance and performance of the chip. reliability.

Optionally, a plurality of TSV structures are disposed in the substrate, and second ends of the plurality of TSV structures are used to connect to ground pads at the bottom of the chip. In this way, the TSV structure can be used to connect the external ground pads to achieve the purpose of grounding the internal circuits in the chip.

Optionally, a top metal pad is also provided on the top of the chip. The top metal pad is coupled with the TSV structure, and the top metal pad is also used to connect the package pad through the wirebond. In this way, the chip can also be applied to other packaging technologies other than the TSV packaging technology, thereby improving the flexibility of chip packaging.

In a second aspect, an embodiment of the present application provides a chip package structure, and the chip package structure further includes a chip substrate and a first chip, and the first chip is any one of the possible chips in the first aspect above. The TSV structure of the first chip is connected to the ground pad at the bottom of the first chip; the ground pad at the bottom of the first chip is attached to the chip substrate.

Optionally, the top metal pads of the first chip are connected to the package pads through wirebonds.

In a possible implementation manner, the second chip may be disposed above the first chip. The second chip may be any of the possible chips in the first aspect above. The TSV structure of the second chip is coupled to the top metal pad of the first chip.

In a possible implementation manner, a third chip may also be disposed above the second chip. The third chip may be any of the possible chips in the first aspect above. The TSV structure of the third chip is coupled to the top metal pad of the second chip.

In a third aspect, an embodiment of the present application provides an electronic device. The electronic device includes a transceiver chip, and the transceiver chip includes any one of the possible chip packaging structures in the second aspect above.

Optionally, the electronic device may further include a baseband processing chip coupled with the transceiver chip.

Optionally, the electronic device further includes a printed circuit board, and the transceiver chip is arranged on the printed circuit board.

It can be understood that, the chip packaging structure and electronic equipment provided above can all be implemented by the chip provided above or associated with the chip provided above. Therefore, the beneficial effects that can be achieved can be referred to above. The beneficial effects of the provided chip will not be repeated here.

Description of drawings

FIG. 1 is a schematic diagram 1 of a cross-sectional structure of a chip according to an embodiment of the present application;

FIG. 2 is a top view of the structure of a metal sheet M1 in a first metal layer in a chip according to an embodiment of the present application;

FIG. 3 is a top view of the structure of the metal sheet M2 in the second metal layer in a chip according to an embodiment of the present application;

FIG. 4 is a top view of the structure after the metal sheet M1 shown in FIG. 2 and the metal sheet M2 shown in FIG. 3 are overlapped;

5 is a second schematic diagram of a cross-sectional structure of a chip according to an embodiment of the present application;

6 is a schematic diagram 3 of a cross-sectional structure of a chip according to an embodiment of the present application;

FIG. 7 is a schematic diagram 4 of a cross-sectional structure of a chip according to an embodiment of the present application;

FIG. 8 is a schematic cross-sectional structure diagram of the chip shown in FIG. 7 after etching the TSV structure;

9 is a top view of the structure in which the first metal layer and the second metal layer are fabricated in the deep N well region in the chip shown in FIG. 8;

FIG. 10 is a schematic diagram 5 of a cross-sectional structure of a chip according to an embodiment of the present application;

11 is a schematic cross-sectional structure diagram of the chip shown in FIG. 10 after etching the TSV structure;

12 is a top view of the structure in which the first metal layer and the second metal layer are fabricated in the N-well region in the chip shown in FIG. 10;

FIG. 13 is a first structural schematic diagram of a chip packaging structure provided by an embodiment of the application;

14 is a second structural schematic diagram of a chip packaging structure provided by an embodiment of the application;

FIG. 15 is a schematic structural diagram 1 of an electronic device provided by an embodiment of the application;

FIG. 16 is a second schematic structural diagram of an electronic device provided by an embodiment of the application;

FIG. 17 is a third schematic structural diagram of an electronic device according to an embodiment of the present application.

01-substrate; 001-TSV structure; 100-TSV pad; 200-middle metal level; 300-top metal level; 400-internal circuit; 101-first metal layer; 1011-metal trace A; 102 - second metal layer; 1021 - metal trace B; 103 - third metal layer; 104 - fourth metal layer; 120 - metal overlap area; 111 - first via hole; 112 - second via hole; 113 - third via hole; 201 - first middle metal layer; 202 - second middle metal layer; 211 - fourth via hole; 212 - fifth via hole; 301 - first top metal layer; 3011 - top layer metal pad; 311-sixth via hole; 401-deep N-type well; 402-N-type well; 403-first via hole; 404-second via hole; 1100-first chip; 1200-second chip ; 1300 - the third chip; 1101 - the ground pad; 1102 - the chip substrate; 1103 - the package pad; 1104 - the solder joint; 1105 - the wire.

Detailed ways

Below, the terms involved in the embodiments of the present application are explained:

1) Through silicon via (TSV) packaging technology

TSV packaging technology is a three-dimensional (3dimensions, 3D) integrated circuit packaging technology. This technology drills holes on the back of the chip and fills the etched through holes with conductive materials, so that external signals can be connected to the back of the chip. the internal circuitry of the chip.

2) TSV structure

For a chip using the TSV packaging process, a drill hole is etched on the back of the chip, and a conductive material is filled in the etched through hole, and the structure formed after filling the conductive material in the through hole is a TSV structure.

3) TSV pad

The TSV pad serves as the connection point between the TSV structure and the internal circuitry of the chip.

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments.

Hereinafter, the terms "first", "second", etc. are only used for descriptive purposes, and should not be understood as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature defined as "first", "second", etc., may expressly or implicitly include one or more of that feature.

In addition, in this application, orientation terms such as "upper" and "lower" are defined relative to the orientation in which the components in the drawings are schematically placed. It should be understood that these directional terms are relative concepts, and they are used for relative In the description and clarification of the drawings, it may change correspondingly according to the change of the orientation in which the components are placed in the drawings.

In this application, unless otherwise expressly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" may be a fixed connection, a detachable connection, or an integrated body; it may be directly connected, or Can be indirectly connected through an intermediary. Furthermore, the term "coupled" may be a manner of electrical connection that enables signal transmission. "Coupling" can be a direct electrical connection or an indirect electrical connection through an intermediate medium.

In the chip manufacturing process, the internal circuit of the chip is generally arranged on the substrate of the chip, and then the metal layers that meet the requirements of chip manufacturing are fabricated on the substrate of the chip, generally including the bottom metal, the middle metal and the top metal. one or more. Insulating materials can be filled in each metal level to ensure the insulation requirements between different metal levels.

In the TSV packaging process, in order to realize the signal connection between the external signal and the internal circuit of the chip, the TSV pad structure is generally used as the connection point between the internal circuit of the chip and the external signal.

FIG. 1 is a schematic diagram 1 of a cross-sectional structure of a chip according to an embodiment of the present application. Referring to FIG. 1 , the chip includes a substrate 01 . The substrate 01 can be divided into a circuit area and a TSV area. In the circuit area of the substrate 01, a transistor is usually used as the internal circuit 400 of the chip. For example, to realize the conversion of a digital signal to an analog signal, the internal circuit of the chip may be a digital-to-analog converter (DAC) ) circuit. Taking the chip implementing the DAC function as an example, one of the internal circuits of the chip, such as the first internal circuit, may include at least one current source, and the current source may include two transistors, such as a first transistor and a second transistor.

In order to realize the connection between the internal circuit of the chip and the external signal, for the chip using the TSV packaging process, a hole is etched on the back of the chip, and the etched through hole is filled with conductive material, so that the external signal can pass through the back of the chip. Connect to the internal circuitry of the chip. It should be understood that the back of the chip may generally refer to the bottom of the chip substrate 01 . In the chip shown in FIG. 1 , the structure formed by filling the conductive material in the through hole after etching the drilling hole in the substrate 01 can be used as the TSV structure 001 .

In the prior art, the connection between the internal circuit of the chip and the external signal is realized by the TSV process. Generally, a special level required by the TSV pad is added as the TSV pad in the chip manufacturing process, so that one end of the TSV pad can be connected to the internal circuit of the chip. connection, so that the other end of the TSV pad is connected to the TSV structure 001, so as to realize the connection between the internal circuit of the chip and the external signal. However, adding a special level of TSV pads in the chip manufacturing process requires the introduction of a TSV process, and the ordinary chip manufacturing process is no longer applicable, which will increase the manufacturing cost of the chip.

In the embodiment of the present application, the existing metal layer in the chip fabrication process is used as the TSV pad, thereby reducing the fabrication cost of the chip. The following shows how to use an existing metal level as a TSV pad with a specific example.

Example 1, please refer to FIG. 1 , a first metal layer 101 is disposed above the substrate 01 of the chip. The first metal layer 101 may include metal traces A (ie, second metal traces) and metal traces A' (ie, first metal traces). The metal trace A' is used to connect the internal circuit of the chip, the metal trace A is used to connect the first end of the TSV structure 001, and the second end of the TSV structure 001 can be used to connect to the ground pad 1101 at the bottom of the chip. In addition, the metal trace A and the metal trace A' also have an electrical connection relationship. In this way, the connection between the internal circuit of the chip and the external ground signal can be realized through the metal trace A in the first metal layer 101 . That is to say, the metal trace A can be used as the TSV pad to realize the connection point between the internal circuit of the chip and the external ground signal. In this way, by using the metal traces in the existing metal layers as the TSV pads, it is possible to avoid adding a special layer and introducing a new fabrication process, thereby reducing the fabrication cost of the chip and improving the fabrication efficiency of the chip.

It should be understood that the electrical connection between the metal trace A and the metal trace A' may be a direct connection between the metal trace A and the metal trace A'. For example, if a whole piece of metal is used, it may also be the metal trace A. It is indirectly connected to the metal trace A' through other metal layers, for example, the indirect connection is realized through via holes filled with conductive materials between different metal layers.

It should be noted that, when realizing the connection between the internal circuit of the chip and the external signal (such as a ground signal), in the packaging step of the chip, usually start etching and drilling at the bottom of the substrate 01 of the chip until the first metal layer The metal trace A in 101 is then filled with conductive material as the TSV structure 001 in the through hole formed by etching, so that the metal trace A can be connected to the TSV structure 001 as a connection point between the chip circuit and external signals.

In addition, in order to block the etchant when drilling the back of the chip, the metal trace A in the first metal layer 101 may be a whole piece of metal. Since the metal layer near the substrate 01 (or the TSV structure 001) is generally the bottom metal of the chip, the bottom metal of the chip is relatively thin. Due to the lack of the support function of the substrate 01 in some areas of the metal sheet M1, the bulging phenomenon is prone to occur, which makes the structure of the metal layers in the chip unstable. As such, when the first metal layer 101 is used as the TSV pad, the connection between the metal sheet M1 and the TSV structure 001 may be unstable, thereby affecting the reliability of the chip.

Please continue to refer to FIG. 1 , a second metal layer 102 may be disposed above the first metal layer 101 in the above-mentioned chip, and the metal traces in the first metal layer 101 and the second metal layer 102 may be used as the TSV pad 100 . Similar to the first metal layer 101, the second metal layer 102 may include a metal trace B (ie, a third metal trace), and the metal trace B and the metal trace A have an electrical connection relationship, for example, through the metal trace A first via hole 111 disposed between the wire B and the metal trace A realizes the coupling, wherein the first via hole 111 is filled with a conductive material. Of course, in order to realize the connection with the internal circuit of the chip, the second metal layer 102 may further include a metal wire B', which is used for electrical connection with the metal wire A' in the first metal layer 101, thereby indirectly connecting the internal circuit of the chip.

Optionally, in the chip shown in FIG. 1, the metal wire A may be a metal sheet M1, and the metal wire B may be a metal sheet M2; a plurality of holes are provided on both the metal sheet M1 and the metal sheet M2, so that Reduce the distribution density of metal flakes in each metal layer. In this way, the chip can not only meet the metal density requirement in the chip design rule, but also avoid the bulging phenomenon of the metal sheet, thereby improving the reliability of the chip.

Further, in order to block the etching solution when the backside of the chip is etched and drilled, the holes on the metal sheet M1 and the metal sheet M2 are arranged in a staggered manner, and the merged area where the metal sheet M1 and the metal sheet M2 overlap can cover the TSV structure 001, that is, In other words, the area formed by the vertical projection of the metal sheet M1 and the metal sheet M2 on the chip surface can cover the TSV structure 001 . In this way, after the metal sheet M1 and the metal sheet M2 are taken as a whole, a complete metal sheet can actually be formed to prevent the corrosion of the corrosive liquid during the etching process.

For details, please refer to FIGS. 2 , 3 and 4 , wherein FIG. 2 is a top view of the structure of the metal trace A. In the figure, 5×5 holes are provided on the metal sheet M1 in the metal trace A1011 . Figure 3 is a top view of the structure of the metal trace B. In the figure, 6×6 holes are set on the metal sheet M2 in the metal trace B1021; it can be seen that the arrangement positions of the holes in the metal sheet M2 and the metal sheet M1 are different . It should be noted that the area covered by the metal sheet M1 and the metal sheet M2 should exceed the area where the TSV structure 001 is located; the number of holes in the metal sheet M1 in FIG. 2 and the metal sheet M2 in FIG. 3 may be more or less, for Depending on the chip process, the number of holes in the metal sheet M1 and the metal sheet M2 may be different.

FIG. 4 is a schematic structural diagram of the metal sheet M1 in FIG. 2 and the metal sheet M2 in FIG. 3 after overlapping. As can be seen from FIG. 4 , the metal sheet M1 and the metal sheet M2 also have a metal overlapping area 120 after being overlapped; in order to realize the electrical connection between the metal trace A and the metal trace B, the first via 111 is provided in the metal Overlapping region 120.

In this way, in the chip shown in FIG. 1 , the metal trace A in the first metal layer 101 and the metal trace B in the second metal layer 102 can be used together as the TSV pad 100 , which can realize the use of existing The metal traces in the metal layer are used as TSV pads to connect the internal circuits of the chip and external signals, thereby reducing the manufacturing cost of the chip; it can also reduce the impact of the structural stress in each metal layer on the chip, ensuring that the Good contact between metal traces and good contact between the metal traces and the TSV structure; it can also block the corrosive liquid when the TSV is etched and drilled to prevent the corrosion of the corrosive liquid, thereby improving the stability and reliability of the chip.

Example 2, FIG. 5 is a schematic diagram 2 of a cross-sectional structure of a chip according to an embodiment of the present application. Compared with the chip shown in FIG. 1 , the first metal layer 101 , the second metal layer 102 and the third metal layer 103 may be arranged on the substrate 01 of the chip shown in FIG. 5 in sequence, and the first metal layer 101 , the second metal layer 102 The metal traces in the metal layer 102 and the third metal layer 103 are used as the TSV pads 100 . The structures of the first metal layer 101 and the second metal layer 102 are the same as or similar to the structure of the chip shown in FIG. 1 , and will not be repeated here. In FIG. 5, the third metal layer 103 is located above the second metal layer 102, and the third metal layer 103 may include a metal trace C, and the metal trace C and the metal trace B have an electrical connection relationship, such as The coupling is achieved through a second via hole 112 disposed between the metal trace C and the metal trace B, wherein the second via hole 112 is filled with a conductive material. In order to realize the connection with the internal circuit of the chip, the third metal layer 103 may further include a metal wiring C' for electrically connecting with the metal wiring B' in the second metal layer 102, thereby indirectly connecting the internal circuit of the chip.

Similarly, in order to meet the metal density requirement in the chip design rule, the metal trace C in the third metal layer 103 may be a metal sheet M3, and the metal sheet M3 is also provided with a plurality of holes. In order to block the etchant when the backside of the chip is etched and drilled, the holes on the metal sheet M1, the metal sheet M2 and the metal sheet M3 are staggered, and the merged area after the metal sheet M1, the metal sheet M2 and the metal sheet M3 overlap can cover the TSV. The structure 001, that is, the area formed by the vertical projection of the metal sheet M1, the metal sheet M2 and the metal sheet M3 on the chip surface, may cover the TSV structure 001. In this way, the metal traces in the first metal layer 101, the second metal layer 102 and the third metal layer 103 are used as the TSV pads 100, so that the metal traces in the existing metal layers can be used as TSV soldering pads. It connects the internal circuit of the chip and the external signal, thereby reducing the manufacturing cost of the chip; it can also reduce the impact of structural stress in each metal layer on the chip, and ensure good contact between the metal traces in the chip and metal traces. Good contact between the wire and the TSV structure; it can also block the corrosive liquid when the TSV is etched and drilled to prevent the erosion of the corrosive liquid, thereby improving the stability and reliability of the chip.

Example 3, FIG. 6 is a schematic diagram 3 of a cross-sectional structure of a chip according to an embodiment of the present application. Compared with the chip shown in FIG. 1 , a first metal layer 101 , a second metal layer 102 , a third metal layer 103 and a fourth metal layer 104 may be arranged on the substrate 01 of the chip in sequence, and the first metal layer 101 , The metal traces in the second metal layer 102 , the third metal layer 103 and the fourth metal layer 104 are used as the TSV pad 100 . The basic structures of the first metal layer 101 , the second metal layer 102 and the third metal layer 103 are the same as or similar to the chips shown in FIG. 1 and FIG. 2 , and will not be repeated here. In FIG. 4 , the fourth metal layer 104 is located above the third metal layer 103 , and the fourth metal layer 104 may include a metal trace D, and the metal trace D and the metal trace C in the third metal layer 103 are electrically connected The connection relationship, for example, can be coupled through a third via hole 113 disposed between the metal trace D and the metal trace C, wherein the third via hole 113 is filled with conductive material. In order to realize the connection with the internal circuit of the chip, the third metal layer 103 may further include a metal wiring D', which is used for electrical connection with the metal wiring C' in the third metal layer 103, thereby indirectly connecting the internal circuit of the chip.

Similarly, in order to meet the metal density requirement in the chip design rule, the metal wiring D in the fourth metal layer 104 can be a metal sheet M4, and the metal sheet M4 is also provided with a plurality of holes. In order to block the etchant when the backside of the chip is etched and drilled, the holes on the metal sheet M3 and the metal sheet M4 are staggered, and the merged area after the metal sheet M3 and the metal sheet M4 overlap can cover the TSV structure 001, that is, the metal sheet The area formed by the vertical projection of the sheet M3 and the metal sheet M4 on the chip surface can cover the TSV structure 001 .

It should be noted that, in FIG. 6 , after the metal sheet M1 in the first metal layer 101 and the metal sheet M2 in the second metal layer 102 overlap, the TSV structure 001 may be covered; the TSV structure 001 may not be covered. In FIG. 6, if the metal sheet M1 and the metal sheet M2 can cover the TSV structure 001 after overlapping, the metal sheets M3 and M4 can further reduce the influence on the internal structure of the chip during the TSV etching process, and further improve the stability and performance of the chip. reliability.

It should be understood that the shapes of the holes on the metal sheet M1, metal sheet M2, metal sheet M3 and metal sheet M4 that may be involved in the chips shown in FIG. 1, FIG. 5, and FIG. 6 may be rectangles, squares, circles or other Irregular shapes, such as trapezoids, etc. The width of the hole can be between one micrometer and several tens of micrometers, which can meet the chip design rules and the metal density requirements in the chip fabrication process. The embodiments of the present application do not specifically limit the shapes and widths of the holes on the metal sheet M1, the metal sheet M2, the metal sheet M3, and the metal sheet M4.

In addition, the metal layers involved in the chip in the embodiments of the present application are not limited to the first metal layer 101 , the second metal layer 102 , the third metal layer 103 and the fourth metal layer 104 , and other metal layers may also exist, such as The fifth metal layer in the bottom metal, the middle metal layer 200, and the like. The embodiments of the present application also do not specifically limit the number of metal layers in various types of chips. Taking the metal layer in the chip shown in FIG. 1 , FIG. 5 and FIG. 6 further including the middle metal layer 200 as an example, that is to say, above the second metal layer 102 of the chip shown in FIG. 1 , as shown in FIG. 5 Above the third metal layer 103 of the chip shown in FIG. 6 and above the fourth metal layer 104 in the chip shown in FIG. 201 and the metal traces of the second metal layer 102 can be coupled through a fourth via 211, and between the second middle metal layer 202 and the metal traces of the first intermediate metal layer 201 can be coupled through a fifth via hole 212 is coupled.

Example 4, FIG. 7 is a schematic diagram 4 of a structure of a chip according to an embodiment of the present application. The first metal layer 101 in the chips shown in FIGS. 1 , 5 and 6 is arranged in the deep N-well region. More specifically, an N-type well 402 may also be provided on the upper portion of the substrate 01 in the chips described in FIG. 1 , FIG. 5 and FIG. 6 . Please refer to FIG. 7 , in conjunction with FIG. 8 and FIG. 9 , the N-type well 402 on the upper part of the substrate 01 can be a structure that penetrates through the middle, such as a ring shape or a shape similar to a rectangular frame, which can make the TSV structure fabricated during chip packaging. 001 is surrounded by N-type well 402 . A deep N-type well 401 is also provided below the N-type well 402 . The deep N-type well 401 is arranged next to the N-type well 402, and the deep N-type well 401 can cover the hollow region of the N-type well 402 above it, so that the N-type well 402 and the deep N-type well 401 are formed. The structure can divide the substrate 01 into two separate regions. A region above the deep N-type well 401 is formed as a P-type substrate 405 .

Correspondingly, as shown in FIG. 8 , when the chip is packaged, in the process of etching through holes in the substrate 01 to form the TSV structure 001 , etching can be performed along the center of the deep N-type well 401 so that the deep N-type well 401 forms a central through hole. structure, so that the fabricated TSV structure 001 is also located in the independent P-type substrate 405, and then the TSV area where the TSV structure 001 is located forms an isolation effect from the circuit area, so as to reduce the interference between signals and improve the performance and performance of the chip. reliability. In addition, in order to form an isolation effect between the TSV region and the circuit region, a first via hole 403 can be provided on the N-type well 402 for connecting the power supply potential; Two vias 404 make the P-type substrate 405 grounded.

Example 5, FIG. 10 is a schematic structural diagram 5 of a chip according to an embodiment of the present application. The first metal layer 101 in the chips shown in FIGS. 1 , 5 and 6 is arranged in the N-well region. More specifically, an N-type well 402 may also be provided on the upper portion of the substrate 01 in the chips described in FIG. 1 , FIG. 5 and FIG. 6 . Please refer to FIG. 10 , in conjunction with FIG. 11 and FIG. 12 , the N-type well 402 on the upper part of the substrate 01 may be a solid structure.

Correspondingly, as shown in FIG. 11 , during chip packaging, during the process of etching through holes in the substrate 01 to form the TSV structure 001 , the N-type well 402 can be etched along the center of the N-type well 402 to form a structure that penetrates through the middle. , so that the fabricated TSV structure 001 is also located in an independent N-type substrate, thereby forming an isolation effect between the TSV region where the TSV structure 001 is located and the circuit region, so as to reduce the interference between signals and improve the performance and reliability of the chip. In addition, in order to form an isolation effect between the TSV region and the circuit region, a first via hole 403 may be provided on the N-type well 402 for connecting the power supply potential.

In addition, in the chips shown in FIG. 1 , FIG. 5 , FIG. 6 , FIG. 7 , FIG. 8 , FIG. 10 and FIG. 11 , multiple TSV structures 001 in the substrate 01 may be provided, and each TSV structure 001 has a second Both terminals can be used to connect to the ground pads 1101 at the bottom of the corresponding chip. A top metal layer 300 may also be provided on the top of the chip. The top metal layer 300 may include a first top metal layer 301 and a sixth via hole 311. The first top metal layer 301 includes a top metal pad 3011, and the top metal The pads 3011 are coupled with the metal traces A in the first metal layer 101, thereby realizing coupling with the TSV structure. It should be understood that since the first metal layer 101 can be the bottom metal of the chip, generally far from the top of the chip, the top metal pads 3011 in the chip can pass through other media, such as the metal traces in the middle metal layer 200 and the various The vias between the metal traces realize the coupling. For example, in the chip shown in FIG. 1 , the top metal pad 3011 can be coupled to the metal traces in the second middle metal layer 202 through the sixth via 311 . In addition, the top metal pads 3011 provided in the chip can also be used to connect the package pads outside the chip through wires 1105 (wirebond).

The above is an introduction to the chip structure, and the package structure of the chip shown in FIG. 1 , FIG. 5 , FIG. 6 , FIG. 8 , and FIG. 11 is described below. For the convenience of description, the following describes the combination of metal trace A, metal trace A and metal trace B of the chip shown in FIG. 1 , and metal trace A, metal trace B and metal trace of the chip shown in FIG. 5 . The combination of C, the metal trace A, the metal trace B, the metal trace C, and the metal trace D of the chip shown in FIG. 6 are collectively referred to as the TSV pad 100 .

FIG. 13 is a schematic structural diagram 1 of a chip packaging structure according to an embodiment of the present application. The chip package structure includes a chip substrate 1102 and a first chip 1100 . The first chip 1100 includes a TSV structure 001 and a TSV pad 100 , the TSV structure 001 in the first chip 1100 is connected to the ground pad 1101 at the bottom of the first chip 1100 , and the ground pad 1101 at the bottom of the first chip 1100 is attached It is combined on the chip substrate 1102, so as to realize the connection between the internal circuit of the chip and the grounding pad 1101 outside the chip, so that the internal circuit of the chip can meet the grounding requirement.

In addition, for the chips shown in Figure 1, Figure 5, Figure 6, Figure 8 and Figure 11, in addition to using TSV packaging technology, the TSV structure 001 is used to realize the connection between the internal circuit of the chip and the external signal. In other packaging forms, for example, the top metal pad 3011 of the first chip 1100 is connected to the external package pad 1103 through wires 1105 (wirebond), as shown in FIG. The pads 3011 are connected to the pads 1104 on the package pads 1103 .

FIG. 14 is a second structural schematic diagram of a chip packaging structure provided by an embodiment of the present application. The chip packaging structure can be applied to three-dimensional stacked packaging scenarios, such as memory chips. The chip package structure may include a first chip 1100 and a second chip 1200 , and the second chip 1200 is stacked above the first chip 1100 , so that the TSV structure 001 in the second chip 1200 can be welded with the top layer metal in the first chip 1100 The disks 3011 are coupled to each other. A third chip 1300 may also be disposed above the second chip 1200 , and the TSV structure 001 of the third chip 1300 is coupled to the top metal pad 3011 of the second chip 1200 .

The embodiments of the present application provide an electronic device. The electronic device may include a mobile phone (mobile phone), a tablet computer (pad), a computer, a smart wearable product (for example, a smart watch, a smart bracelet), a virtual reality (virtual reality, VR) terminal device, an augmented reality (augmented reality), AR) terminal equipment and other electronic products. The embodiments of the present application do not specifically limit the specific form of the above electronic device.

The above electronic device includes an external component and at least one chip package structure coupled to the external component. The chip package structure may be the chip package structure shown in FIG. 13 and FIG. 14 . Wherein, the above-mentioned external components may include at least one of a package substrate, a silicon-based interposer (interposer), and at least one redistribution layer (RDL) of a fan-out type (integrated fan-out, InFO). The chips in the chip packaging structure may be logic chips or memory chips. In addition, electronic equipment also includes printed circuit boards (PCBs). The aforementioned external components may also be coupled to the PCB through electrical connectors. In this case, the above-mentioned chip package structure can realize signal transmission through external components and other chips or chip package structures on the PCB.

FIG. 15 is a first schematic structural diagram of an electronic device according to an embodiment of the present application. The electronic device may be a terminal or a base station. As shown in FIG. 15 , the electronic device may include an application subsystem, a memory, a massive storage, a baseband subsystem, a radio frequency integrated circuit (RFIC), a radio frequency front end, RFFE) devices, and antennas (antenna, ANT), these devices can be coupled through various interconnecting buses or other electrical connections. Each system or circuit in the electronic device can be implemented by using the chips shown in FIGS. 1 , 5 , 6 , 8 and 10 , or by using the chip packaging structure shown in FIGS. 13 and 14 .

In FIG. 15 , ANT_1 represents the first antenna, ANT_N represents the Nth antenna, and N is a positive integer greater than 1. Tx represents the transmit path, Rx represents the receive path, and different numbers represent different paths. FBRx represents the feedback receiving path, PRx represents the primary receiving path, and DRx represents the diversity receiving path. HB means high frequency, LB means low frequency, both refer to the relative high and low frequency. BB stands for baseband. It should be understood that the labels and components in FIG. 5 are for illustrative purposes only, and are only used as a possible implementation manner, and the embodiments of the present application also include other implementation manners.

Among them, the application subsystem can be used as the main control system or main computing system of the wireless communication device to run the main operating system and application programs, manage the hardware and software resources of the entire wireless communication device, and provide users with a user interface. The application subsystem may include one or more processing cores. In addition, the application subsystem may also include driver software related to other subsystems (eg, baseband subsystem). The baseband subsystem may also include one or more processing cores, as well as hardware accelerators (HACs) and caches.

In Figure 15, the RFFE device, RFIC 1 (and optionally RFIC 2) can collectively form the RF subsystem. The RF subsystem can be further divided into the RF receive path (RF receive path) and the RF transmit path (RF transmit path). The RF receive channel can receive the RF signal through the antenna, process the RF signal (eg, amplify, filter and down-convert) to obtain the baseband signal, and transmit it to the baseband subsystem. The RF transmit channel can receive the baseband signal from the baseband subsystem, perform RF processing (such as up-conversion, amplification and filtering) on the baseband signal to obtain the RF signal, and finally radiate the RF signal into space through the antenna. Specifically, the radio frequency subsystem may include an antenna switch, an antenna tuner, a low noise amplifier (LNA), a power amplifier (PA), a mixer (mixer), a local oscillator (LOO) ), filters and other electronic devices, which can be integrated into one or more chips as required. Antennas can also sometimes be considered part of the RF subsystem.

The baseband subsystem can extract useful information or data bits from the baseband signal, or convert the information or data bits into the baseband signal to be transmitted. These information or data bits may be data representing user data or control information such as voice, text, video, etc. For example, the baseband subsystem can implement signal processing operations such as modulation and demodulation, encoding and decoding. Different radio access technologies, such as 5G NR and 4G LTE, tend to have different baseband signal processing operations. Therefore, in order to support the convergence of multiple mobile communication modes, the baseband subsystem may simultaneously include multiple processing cores, or multiple HACs.

In addition, since the radio frequency signal is an analog signal, the signal processed by the baseband subsystem is mainly a digital signal, and an analog-to-digital conversion device is also required in the wireless communication device. The analog-to-digital conversion device includes an analog-to-digital converter (ADC) that converts an analog signal to a digital signal, and a digital-to-analog converter (DAC) that converts a digital signal to an analog signal. In the electronic device in the embodiment of the present application, the analog-to-digital conversion device may use the chips shown in FIG. 1 , FIG. 5 , FIG. 6 , FIG. 8 , and FIG. 10 , and the analog-to-digital conversion device It can be arranged in the radio frequency subsystem, that is, the transceiver chip.

It should be understood that, in this embodiment of the present application, the processing core may represent a processor, and the processor may be a general-purpose processor or a processor designed for a specific field. For example, the processor may be a central processing unit (center processing unit, CPU), or may be a digital signal processor (digital signal processor, DSP). The processor may also be a microcontroller (micro control unit, MCU), a graphics processor (graphics processing unit, GPU), an image signal processor (image signal processing, ISP), an audio signal processor (audio signal processor, ASP) ), and processors specially designed for artificial intelligence (AI) applications. AI processors include, but are not limited to, neural network processing units (NPUs), tensor processing units (TPUs), and processors called AI engines.

Hardware accelerators can be used to implement some sub-functions with high processing overhead, such as data packet assembly and parsing, data packet encryption and decryption, etc. These sub-functions can also be implemented using general-purpose processors, but hardware accelerators may be more appropriate due to performance or cost considerations. Therefore, the type and number of hardware accelerators can be specifically selected based on requirements. In a specific implementation manner, one or a combination of a field programmable gate array (FPGA) and an application specific integrated circuit (ASIC) can be used for implementation. Of course, one or more processing cores may also be used in a hardware accelerator.

Memory can be divided into volatile memory (volatile memory) and non-volatile memory (non-volatile memory, NVM). Volatile memory refers to memory in which data stored inside is lost when the power supply is interrupted. At present, volatile memory is mainly random access memory (random access memory, RAM), including static random access memory (static RAM, SRAM) and dynamic random access memory (dynamic RAM, DRAM). Non-volatile memory refers to memory whose internal data will not be lost even if the power supply is interrupted. Common non-volatile memories include read only memory (ROM), optical disks, magnetic disks, and various memories based on flash memory technology. Generally speaking, memory can choose volatile memory, and mass storage can choose non-volatile memory, such as magnetic disk or flash memory.

In the embodiment of the present application, the baseband subsystem and the radio frequency subsystem together form a communication subsystem, which provides a wireless communication function for a wireless communication device. Generally, the baseband subsystem is responsible for managing the hardware and software resources of the communication subsystem, and can configure the working parameters of the radio frequency subsystem. One or more processing cores of the baseband subsystem may be integrated into one or more chips, which may be referred to as baseband processing chips or baseband chips. Similarly, RFICs may be referred to as radio frequency processing chips or radio frequency chips. In addition, with the evolution of technology, the functional division of the radio frequency subsystem and the baseband subsystem in the communication subsystem can also be adjusted. For example, the functions of part of the radio frequency subsystem are integrated into the baseband subsystem, or the functions of part of the baseband subsystem are integrated into the radio frequency subsystem. In practical applications, based on the needs of the application scenarios, the wireless communication device may adopt combinations of different numbers and types of processing cores.

In this embodiment of the present application, the radio frequency subsystem may include an independent antenna, an independent radio frequency front end (RF front end, RFFE) device, and an independent radio frequency chip. A radio frequency chip is also sometimes referred to as a receiver, transmitter, transceiver, or transceiver chip. Antennas, RF front-end devices, and RF processing chips can all be manufactured and sold separately. Of course, the RF subsystem can also use different devices or different integration methods based on power consumption and performance requirements. For example, some devices belonging to the RF front-end are integrated into the RF chip, and even the antenna and the RF front-end devices are integrated into the RF chip. The RF chip can also be called a RF antenna module or an antenna module.

In this embodiment of the present application, the baseband subsystem may be used as an independent chip, and the chip may be called a modem chip. The hardware components of the baseband subsystem can be manufactured and sold in units of modem chips. Modem chips are also sometimes called baseband chips or baseband processors. In addition, the baseband subsystem can also be further integrated in the SoC chip, and manufactured and sold in the unit of SoC chip. The software components of the baseband subsystem can be built into the hardware components of the chip before the chip leaves the factory, or can be imported into the hardware components of the chip from other non-volatile memory after the chip leaves the factory, or can also be downloaded online through the network. and update these software components.

In addition, the electronic device may further include a printed circuit board on which the transceiver chip is disposed.

FIG. 16 is a second schematic structural diagram of an electronic device according to an embodiment of the present application. Fig. 16 shows some common devices used for RF signal processing in electronic equipment, and the device can adopt the chip shown in Fig. 1, Fig. 5, Fig. 6, Fig. 8 and Fig. 10 or the chip package structure shown in Fig. 13 and Fig. 14 to fulfill. It should be understood that although FIG. 16 shows only one radio frequency receiving channel and one radio frequency transmitting channel, the wireless communication device in the embodiment of the present application is not limited to this, and the wireless communication device may include one or more radio frequency receiving channels and radio frequency transmitting channels .

For the radio frequency receiving channel, the radio frequency signal received from the antenna is selected by the antenna switch and sent to the radio frequency receiving channel. Since the RF signal received from the antenna is usually very weak, it is usually amplified by a low noise amplifier (LNA). The amplified signal first goes through the down-conversion processing of the mixer, then passes through the filter and the analog-to-digital converter ADC, and finally completes the baseband signal processing. For the radio frequency transmission channel, the baseband signal can be converted into an analog signal through the digital-to-analog converter DAC, and the analog signal is converted into a radio frequency signal through the up-conversion processing of the mixer, and the radio frequency signal is processed by the filter and the power amplifier PA, Finally, through the selection of the antenna switch, it radiates outward from the appropriate antenna.

Among them, in the mixer, the input signal and the local oscillator LO signal are mixed, and up-conversion (corresponding to the radio frequency transmit channel) or down-conversion (corresponding to the radio frequency receive channel) operation can be realized. Among them, the local oscillator LO is a common term in the field of radio frequency, usually referred to as the local oscillator. The local oscillator is sometimes called a frequency synthesizer or frequency synthesizer, or simply frequency synthesizer. The main function of the local oscillator or frequency synthesizer is to provide the specific frequency required for radio frequency processing, such as the frequency point of the carrier. Higher frequencies can be implemented using devices such as phase locked loops (PLLs) or delay locked loops (DLLs). The lower frequency can be realized by directly using a crystal oscillator, or by dividing the frequency of the high-frequency signal generated by devices such as PLL.

FIG. 17 is a third schematic structural diagram of an electronic device according to an embodiment of the present application. FIG. 17 shows some common devices used for photoelectric processing in electronic equipment, and the devices can adopt the chips shown in FIG. 1 , FIG. 5 , FIG. 6 , FIG. 8 and FIG. 10 . The electronic device includes at least one signal sending channel and at least one signal receiving channel.

For the signal transmission channel, the electrical signal is sent to the laser (light amplification by stimulated emission of radiation, LASER) through the transmission path (transmit, TX) in the optical module, and the laser LASER converts the electrical signal into an optical signal and then realizes the light through the optical fiber. sending of signals.

For the signal receiving channel, when the optical signal sent by the optical fiber is received, the received optical signal is converted into an electrical signal through a photodiode (PD), and received through the receiving path (receive, RX) in the optical module to realize the electrical signal. reception. The electronic device in FIG. 17 can realize mutual conversion between optical signals and electrical signals, and can transmit and receive signals through optical fibers.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited to this. should be covered within the scope of protection of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims (19)

1. A chip, characterized by comprising a substrate and a first metal layer disposed above the substrate;

   The substrate is provided with a TSV structure;

   the first metal layer includes a first metal trace and a second metal trace;

   the first metal trace is used to connect the internal circuit of the chip;

   the second metal trace is used to connect the first end of the TSV structure;

   The second end of the TSV structure is used to connect to the ground pad at the bottom of the chip.
2. The chip according to claim 1, wherein the internal circuit comprises a current source, the current source comprises a first transistor and a second transistor, and the first metal trace is used to connect the first transistor and the second transistor.
3. The chip according to claim 1 or 2, further comprising a second metal layer disposed above the first metal layer; the second metal layer comprising a third metal wiring; the third metal The wiring is connected to the second metal wiring through the via hole;

   The second metal wiring is a metal sheet M1, the third metal wiring is a metal sheet M2, and a plurality of holes are provided on both the metal sheet M1 and the metal sheet M2.
4. The chip according to claim 3, wherein the holes on the metal sheet M1 and the holes on the metal sheet M2 are staggered, and the merged area after the metal sheet M1 and the metal sheet M2 are overlapped Overwrite the TSV structure.
5. The chip according to claim 3 or 4, further comprising a third metal layer disposed above the second metal layer, the third metal layer comprising a fourth metal wiring; the fourth metal The wiring is connected to the third metal wiring through the via hole;

   The fourth metal wiring is a metal sheet M3, and the metal sheet M3 is provided with a plurality of holes.
6. The chip according to claim 5, wherein the holes on the metal sheet M1, the metal sheet M2 and the metal sheet M3 are staggered, and the metal sheet M1, the metal sheet M2 and the The merged area where the metal sheets M3 are overlapped covers the TSV structure.
7. The chip according to claim 5 or 6, further comprising a fourth metal layer disposed above the third metal layer,

   The fourth metal layer includes a fifth metal wiring; the fifth metal wiring is connected to the fourth metal wiring through a via hole;

   The fifth metal wiring includes a metal sheet M4, and the metal sheet M4 is provided with a plurality of holes.
8. The chip according to claim 7, wherein the holes on the metal sheet M3 and the holes on the metal sheet M4 are staggered, and the merged area after the metal sheet M3 and the metal sheet M3 overlap Overwrite the TSV structure.
9. The chip according to any one of claims 1 to 8, wherein an N-type well is provided on the upper part of the substrate, and the N-type well surrounds the TSV structure;

   A deep N-type well is also arranged below the N-type well, and the TSV structure passes through the deep N-type well and extends to the first metal layer, so that the TSV structure is located in an independent P-type substrate ;

   The N-type well is provided with a first via hole; the P-type substrate is provided with a second via hole.
10. The chip according to any one of claims 1 to 8, wherein an N-type well is disposed on the upper part of the substrate, and the TSV structure passes through the N-type well and extends to the first metal layer , so that the TSV structure is located in an independent N-type substrate;

    The N-type well is provided with a first via hole.
11. The chip according to any one of claims 1 to 10, wherein a plurality of the TSV structures are provided in the substrate.
12. The chip according to any one of claims 1 to 11, wherein a top metal pad is further provided on the top of the chip, the top metal pad is coupled with the TSV structure, and the top metal pad is welded The pads are also used to connect the package pads with wirebonds.
13. A chip packaging structure, comprising a chip substrate and a first chip, wherein the first chip is the chip according to claim 12;

    The ground pad on the bottom of the first chip is coupled with the ground terminal on the chip substrate.
14. The chip packaging structure according to claim 13, wherein the top metal pads of the first chip are connected to the packaging pads through wirebonds.
15. The chip package structure according to claim 13, wherein a second chip is disposed above the first chip; the second chip is the chip according to claim 12;

    The TSV structure of the second chip is coupled to the top metal pad of the first chip.
16. The chip packaging structure according to claim 15, wherein a third chip is further disposed above the second chip, and the third chip is the chip according to claim 12;

    The TSV structure of the third chip is coupled to the top metal pad of the second chip.
17. An electronic device, characterized in that it includes a transceiver chip, and the transceiver chip includes the chip package structure according to any one of claims 13 to 16 .
18. The electronic device according to claim 17, further comprising a baseband processing chip, the baseband processing chip being coupled to the transceiver chip.
19. The electronic device according to claim 17 or 18, further comprising a printed circuit board, and the transceiver chip is disposed on the printed circuit board.

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