WO2022133969A1 - 信号处理方法及装置、显示装置 - Google Patents

信号处理方法及装置、显示装置 Download PDF

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Publication number
WO2022133969A1
WO2022133969A1 PCT/CN2020/139193 CN2020139193W WO2022133969A1 WO 2022133969 A1 WO2022133969 A1 WO 2022133969A1 CN 2020139193 W CN2020139193 W CN 2020139193W WO 2022133969 A1 WO2022133969 A1 WO 2022133969A1
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WIPO (PCT)
Prior art keywords
signal
pulse
pulses
pixel clock
frame synchronization
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PCT/CN2020/139193
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English (en)
French (fr)
Inventor
马希通
时晓东
耿立华
夏友祥
张晓�
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/139193 priority Critical patent/WO2022133969A1/zh
Priority to CN202080003634.6A priority patent/CN114982250B/zh
Priority to US17/598,952 priority patent/US11582368B2/en
Publication of WO2022133969A1 publication Critical patent/WO2022133969A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/06—Generation of synchronising signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/12—Synchronisation between the display unit and other units, e.g. other display units, video-disc players
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/436—Interfacing a local distribution network, e.g. communicating with another STB or one or more peripheral devices inside the home
    • H04N21/4363—Adapting the video stream to a specific local network, e.g. a Bluetooth® network
    • H04N21/43632—Adapting the video stream to a specific local network, e.g. a Bluetooth® network involving a wired protocol, e.g. IEEE 1394
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/08—Separation of synchronising signals from picture signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0693—Calibration of display systems
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0435—Change or adaptation of the frame rate of the video stream

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a signal processing method and device, and a display device.
  • a signal processing method includes: obtaining a first frame synchronization signal; the first frame synchronization signal includes a plurality of first pulses, the trailing edge of one first pulse and the leading edge of the next first pulse after the first pulse.
  • the time between is a first time, and the first time corresponds to a first integer number of pulses of the first pixel clock signal; a synchronization calibration signal is generated; the synchronization calibration signal includes a plurality of second pulses, and the trigger of each second pulse is The edge is at the same time as the trailing edge of one of the first pulses; the triggering edge of the second pulse is the leading edge or trailing edge of the second pulse, and the width of the second pulse is the same as the pulse of the first pixel clock signal. the width or the pulse width of the second pixel clock signal is equal; a second frame synchronization signal is generated; the second frame synchronization signal includes a plurality of third pulses, and the trigger edge of each second pulse is closest to the second pulse.
  • the time between the leading edges of one of the third pulses is a second time, and the second time corresponds to the first integer number of pulses of the second pixel clock signal.
  • the generating the second frame synchronization signal includes: counting the number of pulses of the second pixel clock signal; when the number of pulses of the second pixel clock signal reaches the first integer , generate the leading edge of the third pulse in the second frame synchronization signal; in the case where the number of pulses of the second pixel clock signal does not reach the second integer, in response to the trigger edge of the second pulse, generate the trailing edge of the third pulse in the second frame synchronization signal, and return the count of the number of pulses of the second pixel clock signal; or, in response to the number of pulses of the second pixel clock signal the number reaches a second integer, generating a trailing edge of the third pulse in the second frame synchronization signal, and returning the count of the number of pulses of the second pixel clock signal; and in response to the second The trigger edge of the pulse returns the number of pulses of the second pixel clock signal for performing the counting.
  • the generating the synchronization calibration signal includes: obtaining a first signal, where the first signal and the first frame synchronization signal are inverted signals of each other; obtaining a second signal, the second signal is in phase with each other Delay the first pixel clock signal or the second pixel clock signal by one pulse width from the first frame synchronization signal; obtain the synchronization calibration signal according to the first signal and the second signal.
  • the obtaining the synchronization calibration signal according to the first signal and the second signal includes: performing a logical operation on the first signal and the second signal to obtain the synchronization Calibration signal.
  • the obtaining the first signal includes: inverting the first frame synchronization signal to obtain the first signal.
  • the frequency of the second pixel clock signal is substantially equal to the frequency of the first pixel clock signal; within the time period of at least one group of two adjacent second pulses in the synchronization calibration signal, The second frame sync signal has a third pulse.
  • the number of pulses of the second pixel clock signal corresponding to the pulse width of the third pulse is less than or equal to the number of pulses of the first pixel clock signal corresponding to the pulse width of the first pulse number.
  • N times the frequency of the second pixel clock signal is substantially equal to the frequency of the first pixel clock signal; N is an integer greater than 1; at least one group of adjacent in the synchronization calibration signal During the period of two second pulses, the second frame synchronization signal has N third pulses.
  • N is 2.
  • the second frame synchronization signal has two third pulses within a time period of at least one group of two adjacent second pulses in the synchronization calibration signal.
  • the number of pulses of the second pixel clock signal corresponding to the pulse width of the previous third pulse in the two third pulses is equal to the number of pulses of the first pixel clock signal corresponding to the pulse width of the first pulse.
  • the number of pulses; the number of pulses of the second pixel clock signal corresponding to the pulse width of the next third pulse in the two third pulses is less than or equal to the first pulse corresponding to the pulse width of the first pulse.
  • the number of pulses of the pixel clock signal is less than or equal to the first pulse corresponding to the pulse width of the first pulse.
  • the obtaining the first frame synchronization signal includes obtaining a first video signal, the first video signal including the first frame synchronization signal and video data.
  • the signal processing method further includes: writing the video data into a storage device; reading the video data from the storage device according to the second frame synchronization signal to obtain a second video signal; the second video signal includes the second frame synchronization signal and the video data.
  • the signal processing method further comprises: outputting the second video signal.
  • the signal processing method further includes: detecting and obtaining a first frame rate of the first video signal; obtaining a range of a second frame rate of the display module; at N times the first frame rate
  • the second frame synchronization signal has N third pulses within a time period of at least one group of two adjacent second pulses in the synchronization calibration signal ; N is an integer greater than 1.
  • the first frame rate is within the range of the second frame rate
  • the second frame is synchronized within a time period of at least one group of two adjacent second pulses in the synchronization calibration signal
  • the signal has a third pulse.
  • a signal processing apparatus in another aspect, includes: a signal input unit, a first signal processing unit and a second signal processing unit.
  • the signal input unit is configured to obtain a first frame synchronization signal.
  • the first frame synchronization signal includes a plurality of first pulses, and the time between the trailing edge of a first pulse and the leading edge of the next first pulse of the first pulse is a first time, and the first time corresponds to A first integer number of pulses of the first pixel clock signal.
  • the first signal processing unit is configured to generate a synchronization calibration signal.
  • the synchronization calibration signal includes a plurality of second pulses, and the trigger edge of each second pulse is at the same time as the trailing edge of one of the first pulses; the trigger edge of the second pulse is the second pulse the leading edge or trailing edge, the width of the second pulse is equal to the pulse width of the first pixel clock signal or the pulse width of the second pixel clock signal.
  • the second signal processing unit is configured to generate a second frame synchronization signal.
  • the second frame synchronization signal includes a plurality of third pulses, and the time between the trigger edge of each second pulse and the leading edge of the closest third pulse after the second pulse is the second time, so The second time corresponds to the first integer number of pulses of the second pixel clock signal.
  • the signal input unit is configured to obtain a first video signal including the first frame synchronization signal and video data.
  • the signal processing apparatus further includes: a data writing unit, a data reading unit and a signal outputting unit.
  • the data writing unit is configured to write video data in the first video signal to a storage device.
  • the data reading unit is configured to read the video data in the storage device according to the second frame synchronization signal.
  • the signal output unit is configured to output a second video signal including the second frame synchronization signal and the video data.
  • a signal processing apparatus includes: a memory and a processor.
  • One or more computer programs are stored in the memory.
  • the processor is coupled to the memory; the processor is configured to execute the computer program such that the processor implements the signal processing method as described in any of the above embodiments.
  • a signal processing apparatus is provided.
  • the signal processing device is a chip.
  • the chip is configured to implement the signal processing method as described in any of the above embodiments.
  • a display device in yet another aspect, includes: a display module and the signal processing device according to any one of the above embodiments.
  • the signal processing device is coupled to the display module; the signal processing device is configured to output a second video signal to the display module.
  • the display device further includes: a storage device.
  • the storage device is coupled to the signal processing device.
  • the storage device is configured to store video data in the first video signal.
  • a computer-readable storage medium stores computer program instructions that, when executed on a processor, cause the processor to execute the signal processing method described in any of the above embodiments.
  • a computer program product includes computer program instructions that, when executed on a computer, cause the computer to execute the signal processing method according to any one of the above embodiments.
  • a computer program When the computer program is executed on a computer, the computer program causes the computer to execute the signal processing method as described in any of the above embodiments.
  • FIG. 1 is a structural diagram of a display device according to some embodiments.
  • FIG. 2 is a structural diagram of a display module according to some embodiments.
  • FIG. 3 is a structural diagram of a signal processing apparatus according to some embodiments.
  • FIG. 4 is another structural diagram of a display device according to some embodiments.
  • Fig. 5 is a kind of transmission process diagram of the video signal in the signal processing method according to some embodiments.
  • 6A is a signal timing diagram of a signal processing method according to some embodiments.
  • 6B is another transmission process diagram of a video signal in a signal processing method according to some embodiments.
  • 7A is another signal timing diagram of a signal processing method according to some embodiments.
  • Fig. 7B is another transmission process diagram of a video signal in a signal processing method according to some embodiments.
  • FIG. 8 is yet another signal timing diagram of a signal processing method according to some embodiments.
  • 9A is another signal timing diagram of a signal processing method according to some embodiments.
  • 9B is another signal timing diagram of a signal processing method according to some embodiments.
  • FIG. 10A is yet another signal timing diagram of a signal processing method according to some embodiments.
  • 10B is another signal timing diagram of a signal processing method according to some embodiments.
  • 11 is yet another signal timing diagram of a signal processing method according to some embodiments.
  • FIG. 13 is yet another signal timing diagram of a signal processing method according to some embodiments.
  • FIG. 14 is yet another structural diagram of a display device according to some embodiments.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as “first” or “second” may expressly or implicitly include one or more of that feature.
  • plural means two or more.
  • the expressions “coupled” and “connected” and their derivatives may be used.
  • the term “connected” may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact.
  • the terms “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, yet still co-operate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited by the content herein.
  • the term “if” is optionally construed to mean “when” or “at” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrases “if it is determined that" or “if a [statement or event] is detected” are optionally interpreted to mean “in determining" or “in response to determining" or “on detection of [recited condition or event]” or “in response to detection of [recited condition or event]”.
  • the display device may be any device that displays text or images, whether in motion (eg, video) or stationary (eg, still images).
  • the display device may be one of a variety of electronic devices in which the embodiments may be implemented or associated with a variety of electronic devices, such as, but not limited to, mobile Phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers/navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, TV monitors, tablets Displays, computer monitors, automotive displays (eg, odometer displays, etc.), navigators, cockpit controls and/or displays, camera view displays (eg, displays for rear-view cameras in vehicles), electronic photographs, electronic billboards, or Signs, projectors, architectural structures, packaging and aesthetic structures (eg, a display for an image of a piece of jewelry), etc.
  • the embodiments of the present disclosure do not specifically limit the specific form
  • the display device 100 includes a display module 200 and a signal processing device 300 .
  • the display module 200 is coupled to the signal processing device 300 .
  • the display module 200 includes a display panel 210 .
  • the display panel may include a liquid crystal display panel (LCD, Liquid Crystal Display) or a self-luminous display panel, such as an OLED (Organic Light Emitting Diode)-based display panel or an LED (Light Emitting Diode, Light Emitting Diode)-based display panel. Diode) display panel, etc.
  • the display module when the display panel is a liquid crystal display panel, the display module further includes a backlight module.
  • the display panel 210 has a display area (Active Area, AA) and a peripheral area S. Wherein, the peripheral area S is located at least on the outer side of the AA area.
  • the display panel 200 includes a plurality of pixels P disposed in the AA area.
  • the plurality of pixels P may be arranged in an array. For example, pixels arranged in a row along the X direction (horizontal direction) in FIG. 2 are called a row of pixels, and pixels arranged in a row along the Y direction (vertical direction) in FIG. 2 are called a column of pixels.
  • each pixel includes a plurality of sub-pixels; the plurality of sub-pixels includes sub-pixels of a first color, sub-pixels of a second color, and sub-pixels of a third color.
  • the first color, the second color and the third color are three primary colors; for example, the first color, the second color and the third color are red, green and blue, respectively; that is, the plurality of sub-pixels include red sub-pixels, green subpixel and blue subpixel.
  • the signal processing device is configured to receive the first video signal and output the second video signal.
  • the display module is configured to display an image corresponding to the second video signal according to the second video signal from the signal processing device.
  • the display device may have a video signal input interface to receive video signals.
  • the video signal input interface may include SDI (Serial Digital Interface, Serial Digital Interface), HDMI (High Definition Multimedia Interface, High Definition Multimedia Interface) or DP (Display Interface, Display Port) and the like.
  • the video signal input interface may be included in the signal processing device.
  • the signal processing device also includes a video signal multiplexer (MUX).
  • the video signal multiplexer is configured to select one video signal to output from the video signal multiplexer among a plurality of video signals input to the video signal multiplexer. Wherein, the video signal output from the video signal multiplexer can be used as the first video signal in the text.
  • the video signals include timing signals and video data
  • the timing signals include synchronization signals and enable signals (ie, valid data strobe signals or data enable signals); synchronization signals include line synchronization signals and frame synchronization signals (ie field sync signal).
  • the first video signal includes a first timing signal and video data
  • the first timing signal includes a first synchronization signal and a first enable signal
  • the first synchronization signal includes a first frame synchronization signal and a first line synchronization signal
  • the second The video signal includes a second timing signal and video data
  • the second timing signal includes a second synchronization signal and a second enable signal
  • the second synchronization signal includes a second frame synchronization signal and a second line synchronization signal.
  • the line synchronization signal usually selects the valid line signal interval on the display panel
  • the frame synchronization signal usually selects the valid field signal interval on the display panel. For example, under the combined action of the line synchronization signal and the frame synchronization signal, a section of valid video data corresponding to the display panel can be selected.
  • valid video data (valid RGB data) only occupies a part of the period of the video signal, and the line blanking and vertical blanking periods of the video signal do not contain valid video data. Therefore, when the relevant circuit in the display device processes the video signal, the enable signal can be used to distinguish the interval including the valid video data from the blanking interval not including the valid video data. Whether it is a line synchronization signal or a frame synchronization signal, the enable signal should be matched.
  • the part of the enable signal corresponding to the line synchronization signal cooperates with the line synchronization signal; in the frame synchronization signal
  • the part of the enable signal corresponding to the frame synchronization signal cooperates with the frame synchronization signal to ensure that the display panel can effectively display the corresponding video signal.
  • the display module 200 further includes a controller 220, for example, the controller may be TCON (Timming Controller, timing controller).
  • the controller 220 is coupled to the display panel 210 .
  • the controller is configured to receive the second video signal from the signal processing device, and control the display panel to display an image corresponding to the second video signal.
  • the display module further includes a driver chip (Driver IC).
  • the driver chip is bound to the display panel, and the control chip is coupled to the controller.
  • the signal processing device transmits the second video signal to the controller, the controller outputs the control signal to the driving chip, and the driving chip outputs the driving signal to the display panel according to the control signal, so as to drive the display panel to display, so as to display the first video signal.
  • the signal processing apparatus 300 includes a memory 301 and a processor 302 .
  • the memory 301 is coupled to the processor 302 .
  • One or more computer programs executable on the processor 302 are stored in the memory 301 .
  • the processor 302 executes the computer program, the processor 302 implements the signal processing method described in any of the following embodiments.
  • the above-mentioned processor 302 may be one processor, or may be a collective term for multiple processing elements.
  • the processor 302 may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more programs for controlling the present disclosure Implementing integrated circuits, such as one or more microprocessors.
  • the above-mentioned memory 301 may be a memory, or may be a collective name of a plurality of storage elements, and is used to store executable program codes and the like.
  • the memory 301 may include random access memory (Random Access Memory, RAM), and may also include non-volatile memory (non-volatile memory), such as disk memory, flash memory (Flash), and the like.
  • the memory 301 is used for storing the application code for executing the solution of the present disclosure, and the execution is controlled by the processor 302 .
  • the processor 302 is configured to execute the application program code stored in the memory 301 to control the processor 302 to implement the data transmission method provided by any of the following embodiments of the present disclosure.
  • the signal processing apparatus 300 may be a chip.
  • the chip is configured to implement the signal processing method as in any of the following embodiments.
  • the chip may be a programmable device.
  • the programmable device is CPLD (Complex Programmable Logic Device), EPLD (Erasable Programmable Logic Device, Erasable Editable Logic Device) or FPGA (Field Programmable Gate Array, Field Programmable Gate Array) .
  • the display device 100 further includes a storage device 400 .
  • the storage device 400 is coupled to the signal processing device 300.
  • the storage device 400 is configured to store video data in the first video signal.
  • the storage device 400 may be located within the signal processing device 300 .
  • the storage device may include random access memory or double-rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SRAM), for example, the storage device may be DDR3.
  • DDR SRAM Double Data Rate Synchronous Dynamic Random Access Memory
  • the frame rate of the video signal received by the signal processing device in the display device does not match the frame rate of the video signal that can be displayed normally by the display module in the display device.
  • the video signal received by the signal processing device The frame rate is 25Hz, and the frame rate of the video signal that the display module can display normally is 60Hz.
  • the signal processing device receives 5 frames of video signals (for example, refer to the input frames A1, A2, A3, A4, A5 in Figure 5). ), the signal processing device outputs 12 frames of video signals to the display module (for example, referring to the output frames A1, A1, A1, A1, A2, A2, A3, A3, A3, A4, A4, A5, A5 in FIG.
  • some of the input video signals (A1 and A3) are copied 3 times and then output, and some of the input video signals (A2, A4 and A5) are copied twice and then output.
  • the video signal input by the signal processing device and the video signal output are not synchronized, that is, the input frame and the output frame of the signal processing device are not synchronized, and the output frame is not uniformly copied to the input frame, for example, some input frames may be Correspondingly outputs 3 frames, and some input frames can output 2 frames correspondingly, which may easily lead to frame skipping or missing frames in the display and reduce the display effect.
  • a display device with high requirements for displaying images such as a monitor, may reduce the authenticity of the display.
  • Embodiments of the present disclosure provide a signal processing method.
  • the signal processing method is applied to a signal processing apparatus, such as the signal processing apparatus 300 in FIG. 1 , FIG. 3 and FIG. 4 .
  • the signal processing method includes:
  • the first frame synchronization signal Source_Vsync includes a plurality of first pulses M1.
  • the time between the trailing edge of one first pulse and the leading edge of the next first pulse of the first pulse is the first time T1.
  • the first time corresponds to a first integer number of pulses of the first pixel clock signal.
  • obtaining the first frame synchronization signal includes: obtaining a first video signal.
  • the first video signal includes a first frame synchronization signal and video data.
  • the video data includes pixel data, such as the display grayscale of each sub-pixel in the display module.
  • the first pixel clock corresponding to the first time between the trailing edge (ie falling edge) of a first pulse in the first frame synchronization signal and the leading edge (ie rising edge) of the next first pulse of the first pulse
  • the number of pulses of the signal is the first integer number; between the trailing edge (ie falling edge) of a first pulse in the first frame synchronization signal and the leading edge (ie rising edge) of the next first pulse of the first pulse
  • the number of clock cycles of the first pixel clock signal is the first integer number, for example, the clock cycle can be understood as the time from the leading edge (or trailing edge) of a pulse to the next pulse of the one pulse.
  • the time between leading (or trailing) edges Exemplarily, referring to FIG.
  • the first video signal further includes a first enable signal Source_DE.
  • the first integer is (VBP+VAC+VFP)
  • VBP represents the period between the trailing edge of a first pulse of the first frame synchronization signal and the leading edge of the pulse of the first enable signal Source_DE (the leading edge of valid video data)
  • the number of pulses of the first pixel clock signal (PCLK1), VAC represents the total number of rows of pixels in the display module
  • VFP represents the leading edge of a first pulse of the first frame synchronization signal to the pulse of the first enable signal Source_DE.
  • the number of pulses of the first pixel clock signal between trailing edges (trailing edges of valid video data). For example, when the resolution of the display module is 1920 ⁇ 1080, the VBP is 36, the VFP is 4, and the VAC is 1080.
  • the first pixel clock signal can be obtained according to the first frame synchronization signal, the first line synchronization signal and the first enable signal in the first video signal.
  • the first pixel clock signal is related to the first frame rate of the first video signal.
  • the frequency of the first pixel clock signal is the product of the first frame rate of the first video signal, HTT and VTT, where HTT represents a line
  • HTT represents a line
  • VTT represents the total number of HTTs within a frame time.
  • the HTT is 2200 and the VTT is 1125, then the frequency of the first pixel clock signal is 148.5MHz;
  • the frame rate of the first video signal is 30Hz, the HTT is 2200 and the VTT is 1125, then the frequency of the first pixel clock signal is 74.5MHz;
  • the frame rate of the first video signal is 50Hz, the HTT is 2640, VTT is 1125, then the frequency of the first pixel clock signal is 148.5MHz;
  • the frame rate of the first video signal is 25Hz, HTT is 2640, VTT is 1125, then the frequency of the first pixel clock signal is 74.5 MHz;
  • the frame rate of the first video signal is 48Hz, the HTT is 2570 and the VTT is 1125, then the frequency of the first pixel clock signal is 148.5MHz;
  • the frame rate of the first video signal is 24Hz,
  • the HTT is 2750 and the VTT is 1125, so the frequency of
  • the synchronization calibration signal Sync_eof includes a plurality of second pulses M2.
  • the trigger edge of each second pulse is at the same time as the trailing edge of a first pulse.
  • the trigger edge of the second pulse is the leading edge (refer to FIG. 6A ) or the trailing edge (refer to FIG. 13 ) of the second pulse, and the width of the second pulse is equal to the pulse width of the first pixel clock signal or the pulse width of the second pixel clock signal .
  • the frequency of the second pixel clock signal can be obtained according to the second frame rate of the display module.
  • the frequency of the first pixel clock signal is the product of the second frame rate of the display module, HTT and VTT.
  • the range of the second frame rate of the display module may be about 40 Hz to 70 Hz, for example, the second frame rate is 48 Hz, 50 Hz, or 60 Hz.
  • generating a synchronization calibration signal includes:
  • the first signal Q1 and the first frame synchronization signal Source_Vsync are mutually inverted signals. It can be understood that the phase of the first signal and the phase of the first frame synchronization signal differ by 180 degrees.
  • obtaining the first signal includes: inverting the first frame synchronization signal to obtain the first signal.
  • the first frame synchronization signal can be inverted by an inverter.
  • the inverter is included in the signal processing device.
  • obtaining the first signal includes: after registering the first frame synchronization signal for a preset time, obtaining the first signal.
  • the first frame synchronization signal may be registered for a preset time through a register, for example, the preset time may be the time required to delay the phase of the first frame synchronization signal by 180 degrees to obtain the first signal.
  • this register is included in the signal processing device.
  • the second signal Q2 is delayed by one pulse width of the first pixel clock signal or the second pixel clock signal compared with the first frame synchronization signal Source_Vsync, that is, the second signal Q2 is compared with the first frame synchronization signal Source_Vsync is delayed by one pulse width K PCLK1 of the first pixel clock signal, or the second signal Q2 is delayed by one pulse width K PCLK2 of the second pixel clock signal compared to the first frame synchronization signal Source_Vsync .
  • one pulse width of the first pixel clock signal or the second pixel clock signal may be registered with the first frame synchronization signal to obtain the second signal.
  • obtaining the synchronization calibration signal according to the first signal and the second signal includes: performing a logical operation on the first signal and the second signal to obtain the synchronization calibration signal.
  • the output signal is the synchronization calibration signal.
  • the logic circuit is included in a signal processing device.
  • the logic operation may be an AND operation; the logic circuit may be an AND gate.
  • the output signal is the synchronous calibration signal; for example, the AND gate is included in the signal processing device.
  • the leading edge of the second pulse in the synchronization calibration signal is at the same time as the trailing edge of a first pulse in the first frame synchronization signal, and at this time, the leading edge of the second pulse is used as the trigger edge of the second pulse.
  • the trailing edge of the second pulse is used as the triggering edge of the second pulse, it can be designed according to the actual situation with reference to FIG. 13 , which is not limited here.
  • the second frame synchronization signal includes a plurality of third pulses M3, and the trigger edge (eg, leading edge) of each second pulse M2 is closest to the third pulse M3 after the second pulse M2
  • the time between the leading edges of is the second time T2, and the second time corresponds to the first integer number of pulses of the second pixel clock signal.
  • generating the second frame synchronization signal includes:
  • the number of pulses of the second pixel clock signal is counted.
  • the number of pulses of the second pixel clock signal in response to the trigger edge of the second pulse, generate the trailing edge of the third pulse in the second frame synchronization signal, and return to perform statistics on the second pixel The number of pulses of the clock signal.
  • the values of the row counter r_PCNT and the column counter r_LCNT are both in the initialization state.
  • the values of the row counter r_PCNT and the column counter r_LCNT are both 0.
  • the number of pulses of the second pixel clock signal can be counted from the moment when the values of the row counter r_PCNT and the column counter r_LCNT are both in the initialization state.
  • the value of the line counter r_PCNT is incremented by 1.
  • the value of the row counter r_PCNT reaches the first parameter, for example the first parameter is HTT
  • the value of the row counter r_PCNT returns to initialization, and the value of the column counter r_LCNT is incremented by 1; from the moment when the value of the row counter r_PCNT reaches HTT, the row counter r_PCNT The value of is recounted from initialization.
  • the second parameter is (VBP+VAC+VFP)
  • the number of pulses of the second pixel clock signal reaches the first integer
  • the second frame synchronization is generated The leading edge of the third pulse in the signal.
  • the first integer is the product of the first parameter and the second parameter, for example, the first integer is HTT ⁇ (VBP+VAC+VFP).
  • the third parameter is (VBP+VAC+VFP+VSW)
  • the number of pulses of the second pixel clock signal reaches the second integer
  • the second integer is the product of the first parameter and the third parameter, for example, the second integer is HTT ⁇ (VBP+VAC+VFP+VSW).
  • the second frame synchronization signal is generated
  • the trailing edge of the third pulse of , and the values of the row counter r_PCNT and the column counter r_LCNT are reset to the initialization state, starting from the trigger edge of the second pulse, count the number of pulses of the second pixel clock signal again.
  • the signal processing method further includes: in response to the number of pulses of the second pixel clock signal reaching a second integer, while generating the trailing edge of the third pulse in the second frame synchronization signal, returning to perform counting of the second pixels.
  • the number of pulses of the clock signal is not limited to: in response to the number of pulses of the second pixel clock signal reaching a second integer, while generating the trailing edge of the third pulse in the second frame synchronization signal, returning to perform counting of the second pixels. The number of pulses of the clock signal.
  • the value of the column counter r_LCNT reaches the third parameter
  • the number of pulses of the second pixel clock signal reaches the second integer
  • the trailing edge of the third pulse in the second frame synchronization signal is generated.
  • the values of the row counter r_PCNT and the column counter r_LCNT are reset to the initialized state, and the number of pulses of the second pixel clock signal is counted again after the number of pulses of the second pixel clock signal reaches the second integer.
  • the values of the row counter r_PCNT and the column counter r_LCNT are preferentially initialized at the moment of the trigger edge of the second pulse compared to the moment when the number of pulses of the second pixel clock signal reaches the second integer.
  • the number of pulses of the second pixel clock signal reaching the second integer means that within a statistical period, the one statistical period may start from the moment when the trigger edge of a second pulse of the synchronization calibration signal is located, and the first A period of time until the number of pulses of the two-pixel clock signal reaches the time of VTT.
  • the frequency of the second pixel clock signal is approximately equal to the frequency of the first pixel clock signal.
  • approximately equal to can be understood as the ratio of the frequency of the second pixel clock signal to the first pixel clock signal is within the range of the first threshold; for example, the range of the first threshold is 0.9-1.1, for example, the first threshold may be 0.999 , 1, or 1.001.
  • the frequency of the first pixel clock signal is about 148.5MHz, and the frequency of the second pixel clock signal is about 148.5Hz.
  • the first frame rate of the first video signal is about 48 Hz
  • the second frame rate corresponding to the display module is about 48 Hz
  • the first frame rate of the first video signal is about 50 Hz
  • the corresponding The second frame rate is about 50 Hz
  • the first frame rate of the first video signal is about 60 Hz
  • the second frame rate corresponding to the display module is about 60 Hz.
  • the second frame synchronization signal has one third pulse within a time period of at least one group of two adjacent second pulses in the synchronization calibration signal.
  • the second The frame synchronization signal VTG_Vsync has a third pulse M3.
  • one frame of the second video signal may be output.
  • the output frame is A1, that is, in the time period when the input frame of the first video signal is A2, the output frame of the second video signal is A1, A1 and A2 respectively represent different video data, and A1 is the video data of the previous frame of A2.
  • the number of pulses of the second pixel clock signal corresponding to the pulse width of the third pulse is less than or equal to the number of pulses of the first pixel clock signal corresponding to the pulse width of the first pulse (refer to FIG. 9A and FIG. 9B .
  • the trigger edge of one second pulse corresponds to the time interval of the leading edge of the closest third pulse after the second pulse
  • the number of pulses of the second pixel clock signal is the first integer number.
  • the second frame synchronization signal is at a low level, that is, the second frame synchronization signal is in the blanking phase;
  • the number of pulses of the second pixel clock signal reaches the second integer number, and the pulse width of the generated third pulse is equal to the pulse width of the first pulse of the first frame synchronization signal.
  • N times the frequency of the second pixel clock signal is approximately equal to the frequency of the first pixel clock signal.
  • N is an integer greater than 1, for example, N is 2 or 3.
  • approximately equal to can be understood as the ratio of N times the frequency of the second pixel clock signal to the first pixel clock signal within the range of the second threshold; for example, the range of the second threshold is 0.9-1.1, for example, the second threshold Can be 0.99, 0.999, 1, or 1.001.
  • the frequency of the first pixel clock signal is about 74.25MHz
  • the frequency of the second pixel clock signal is about 148.5Hz.
  • the first frame rate of the first video signal is about 24 Hz
  • the second frame rate corresponding to the display module is about 48 Hz
  • the first frame rate of the first video signal is about 25 Hz
  • the corresponding The second frame rate is about 50 Hz
  • the first frame rate of the first video signal is about 30 Hz
  • the second frame rate corresponding to the display module is about 60 Hz.
  • the second frame synchronization signal has N third pulses within a time period of at least one group of two adjacent second pulses in the synchronization calibration signal.
  • the N third pulses are adjacent.
  • N is 2;
  • the second frame synchronization signal has two third pulses within the time period of at least one group of adjacent two second pulses in the synchronization calibration signal.
  • Sync_eof in the time period of at least one group of two adjacent second pulses M2 in the synchronization calibration signal Sync_eof, that is, in the time period between the leading edges of the adjacent two second pulses M2, the second The frame synchronization signal VTG_Vsync has two third pulses M3.
  • two frames of the second video signal may be output during a period of time during which one frame of the first video signal is input.
  • the output frames are A1 and A1, that is, in the time period when the input first video signal is A2, the output two frames of the second video signal are respectively for A1.
  • the number of pulses of the second pixel clock signal corresponding to the pulse width of the previous third pulse among the two third pulses is equal to the number of pulses of the first pixel clock signal corresponding to the pulse width of the first pulse.
  • the number of pulses of the second pixel clock signal corresponding to the pulse width of the latter third pulse is less than or equal to the number of pulses of the first pixel clock signal corresponding to the pulse width of the first pulse (refer to FIG. 10A ).
  • the number of pulses of the second pixel clock signal corresponding to the pulse width of the third pulse is not necessarily an integer.
  • the pulse width of the former third pulse among the two third pulses is greater than or equal to the pulse width of the latter third pulse.
  • the leading edge of the previous third pulse in the two third pulses is the closest third pulse before the previous third pulse.
  • the time interval between the leading edges of the two pulses corresponds to the first integer number of pulses of the second pixel clock signal, and the leading edge of the previous third pulse among the two third pulses is the closest second pulse before the previous third pulse.
  • the time interval of the leading edge corresponds to a second integer number of pulses of the second pixel clock signal.
  • the leading edge of the last third pulse in the two third pulses corresponds to the time interval of the trailing edge of the previous third pulse
  • the first integer number of pulses of the second pixel clock signal that is, the pulses of the second pixel clock signal within the time interval between the leading edge of the next third pulse of the two third pulses and the trailing edge of the previous third pulse
  • the number is the first integer number.
  • the next third pulse in the two consecutive third pulses in the second frame synchronization signal is counted from the time of the trailing edge of the previous third pulse.
  • the number of pulses of the two-pixel clock signal does not reach the second integer number, then the number of pulses of the second pixel clock signal corresponding to the pulse width of the next third pulse generated is smaller than the number of pulses of the first pulse of the first frame synchronization signal.
  • the number of pulses of the first pixel clock signal corresponding to the pulse width is
  • the second frame The synchronization signal is at a low level, that is, the second frame synchronization signal is in the blanking phase; or, if at the moment when the second pulse of the synchronization calibration signal arrives, the number of pulses of the second pixel clock signal reaches the second integer number , the number of pulses of the second pixel clock signal corresponding to the pulse width of the last third pulse is equal to the number of pulses of the first pixel clock signal corresponding to the pulse width of the first pulse of the first frame synchronization signal.
  • an embodiment of the present disclosure provides a signal processing method, wherein the time between the trailing edge of a first pulse and the leading edge of the next first pulse in the obtained first frame synchronization signal is the first time, and the first The time corresponds to the first integer number of pulses of the first pixel clock signal; the trigger edge of each second pulse in the generated synchronization calibration signal is at the same time as the trailing edge of a first pulse; the generated second frame synchronization signal, every The time between the trigger edge of the second pulse and the leading edge of the closest third pulse after the second pulse is the second time, and the second time corresponds to the first integer number of pulses of the second pixel clock signal.
  • the trailing edge of each first pulse (that is, the trigger edge of the second pulse) is the same as that after the first pulse.
  • the time between the leading edges of the closest third pulse remains unchanged, so that the synchronization between the second frame synchronization signal and the first frame synchronization signal can be guaranteed.
  • one frame of video signal can be output, so that the input frame and the output frame can achieve single-frame synchronization; or, during the period of inputting one frame of video signal, two frames of video signal can be output, so that The output frame can achieve double frame synchronization with respect to the input frame.
  • the time delay between the input frame video signal and the output frame video signal of the signal processing device can be avoided, and the delay time is continuously accumulated with the increase of the number of frames, resulting in frame skipping between the output frame and the input frame or a difference of at least
  • the problem of uneven output frames can also be avoided, so that the accuracy of the displayed image can be improved, and the authenticity of the displayed image can also be improved.
  • the number of pulses of the second pixel clock signal can be counted to generate the third pulse of the second frame synchronization signal, so that the second frame synchronization signal can be reduced.
  • the number of pulses of the second pixel clock signal corresponding to the pulse width of the third pulse of the frame synchronization signal, so that at the end of an input frame, the trailing edge of the third pulse will not be delayed from the trailing edge of the first pulse, ensuring that The input frame and output frame are synchronized, which can improve the display effect.
  • the signal processing method further includes: writing video data into a storage device; and reading the video data from the storage device according to the second frame synchronization signal to obtain a second video signal.
  • the second video signal includes a second frame synchronization signal and video data.
  • the second enable signal VTG_DE (refer to FIG. 12 ) can be obtained, and according to the second enable signal VTG_DE, video data is read from the storage device to obtain the second video signal.
  • the frequency of the first pixel clock signal is equal to the frequency of the second pixel clock signal
  • the first frame rate of the first video signal is equal to the second frame rate of the display module.
  • the signal processing device receives one frame of video signal (ie the first video signal), the signal processing device may output one frame of the video signal (ie the second video signal).
  • the signal processing device obtains one frame of video signal (ie, the first video signal), the signal processing apparatus may output two frames of video signals (ie, the second video signal), and the video data corresponding to the two frames of video signals are the same.
  • the pulse width of the second enable signal VTG_DE is the duration of VAC.
  • the second enable signal VTG_DE is a high level signal.
  • the pulse width of the second row synchronization signal VTG_Hsync is the duration of HSW, and HSW represents the effective width of the pulse of the second row synchronization signal VTG_Hsync.
  • the second line synchronization signal VTG_Hsync is a high level signal
  • HFP Indicates the number of pulses of the second pixel clock signal between the leading edge of the pulse of the second line synchronization signal and the trailing edge of the second enable signal (the trailing edge of the valid video data)
  • HAC indicates the number of pixels in a row of pixels in the display module. The total number of pixels. For example, when the resolution of the display module is 1920 ⁇ 1080, the HAC is 1920, the HFP is 88, and the HSW is 44.
  • the signal processing apparatus may include a write controller (WDMA) and a read controller (RDMA).
  • the writing controller is used to control the writing of the video data into the storage device; the reading controller is used to control the reading of the video data from the storage device.
  • the signal processing device may further include a read-write controller (MIG) and a bus arbiter (AXI Interconnect).
  • the read-write controller can be used to control the timing of reading and writing video data to the storage device, for example, the read-write controller can be used to control the timing of writing the video data into the storage device by the write controller, and, control the read controller The timing of reading video data from the storage device avoids mutual interference between writing and reading video data.
  • the bus arbiter may be used to enable the signal processing device to exchange data with the storage device through the bus arbiter.
  • the signal processing method further includes outputting a second video signal.
  • the signal processing device outputs the second video signal to the display module, and the display module can display the image corresponding to the second video signal.
  • the signal processing apparatus may output the second video signal to the display module through a VBO (V-by-One, high-definition digital display interface); for example, the signal processing apparatus may include a VBO interface.
  • the display module includes a timing controller and a display panel, and the timing controller controls the display panel to display an image corresponding to the video data according to the second synchronization signal and the video data in the second video signal.
  • the video data in the video signal output by the signal processing device is the video data in the video signal of the previous frame of the input video signal of one frame.
  • the signal processing device outputs one frame within the time period during which the signal processing device obtains one frame of video signal. video signal, so that the input frame and output frame of the signal processing device can achieve single-frame synchronization; in the case where N times the first frame rate of the first video signal is within the range of the second frame rate of the display module, the signal processing During the time period when the device obtains one frame of video signal, the signal processing device outputs N frames of video signals, so that the output frame of the signal processing device can achieve N frame synchronization with respect to the input frame.
  • the input frame and the output frame are not synchronized, and the time delay of the input frame video signal and the output frame video signal of the signal processing device can also be avoided, and the delay time is accumulated with the increase of the number of frames.
  • the output frame and the input frame to skip the frame or have a difference of at least one frame. In this way, there is an error between the video signal output by the signal processing device to the display module and the video signal received by the signal processing device, and the image displayed by the display module has an error. Accuracy is reduced, affecting the authenticity of the displayed image.
  • the signal processing method further includes: detecting and obtaining a first frame rate of the first video signal; and obtaining a range of the second frame rate of the display module.
  • the second frame synchronization signal in the case where N times the first frame rate is within the range of the second frame rate, in the time period of at least one group of two adjacent second pulses in the synchronization calibration signal, the second frame synchronization signal has N a third pulse. N is an integer greater than 1.
  • the second frame synchronization signal has one third pulse within a time period of at least one group of two adjacent second pulses in the synchronization calibration signal.
  • one input frame of the signal processing apparatus corresponds to N frames of output frames, and is in an N frame synchronization mode.
  • twice the first frame rate that is, N is 2
  • one input frame of the signal processing apparatus corresponds to two output frames, in a double frame synchronization mode.
  • the first frame rate is within the range of the second frame rate
  • one frame of input frame of the signal processing device corresponds to one frame of output frame, in a single-frame synchronization mode; in this case, the signal processing device can At a frame rate, different second frame synchronization signals are generated by calling the corresponding program.
  • the signal processing apparatus further includes a frame rate detector, which can detect and obtain the first frame rate of the first video signal.
  • the signal processing apparatus can be reset (ie, initialized) by the reset signal, so as to avoid the interference of the noise signal.
  • Embodiments of the present disclosure provide a signal processing apparatus.
  • the signal processing apparatus can implement the signal processing method described in any of the above embodiments.
  • the signal processing apparatus 300 includes: a signal input unit 310 , a first signal processing unit 320 and a second signal processing unit 330 .
  • the signal input unit is configured to obtain the first frame synchronization signal.
  • the first frame synchronization signal includes a plurality of first pulses, the time between the trailing edge of one first pulse and the leading edge of the next first pulse after the first pulse is the first time, and the first time corresponds to a first integer number of Pulse of the first pixel clock signal.
  • the first signal processing unit is configured to generate a synchronization calibration signal.
  • the synchronization calibration signal includes a plurality of second pulses, and the trigger edge of each second pulse is at the same time as the trailing edge of a first pulse; the trigger edge of the second pulse is the leading edge or trailing edge of the second pulse, and the second The pulse width is equal to the pulse width of the first pixel clock signal or the pulse width of the second pixel clock signal.
  • the second signal processing unit is configured to generate a second frame synchronization signal.
  • the second frame synchronization signal includes a plurality of third pulses; the time between the trigger edge of each second pulse and the leading edge of the closest third pulse after the second pulse is the second time, and the second time corresponds to the first An integer number of pulses of the second pixel clock signal.
  • the signal input unit is configured to obtain the first video signal.
  • the first video signal includes a first frame synchronization signal and video data.
  • the signal processing apparatus 300 further includes: a data writing unit 340 , a data reading unit 350 and a signal outputting unit 360 .
  • the data writing unit is configured to write the video data in the first video signal into the storage device.
  • the data reading unit is configured to read the video data in the storage device according to the second frame synchronization signal.
  • the signal output unit is configured to output a second video signal including a second frame synchronization signal and video data.
  • the apparatus embodiment described in FIG. 14 is only illustrative.
  • the division of the above-mentioned units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated. to another system, or some features can be ignored, or not implemented.
  • Each functional unit in each embodiment of the present application may be integrated into one processing module, or each unit may exist physically alone, or two or more units may be integrated into one module.
  • the above-mentioned units in FIG. 14 may be implemented in the form of hardware, or may be implemented in the form of software functional units. For example, when implemented by software, the above-mentioned first signal processing unit and second signal processing unit, etc.
  • the above-mentioned units in FIG. 14 can also be implemented by different hardware in the computer (display device), for example, the signal input unit, the first signal processing unit and the second signal processing unit are implemented by a part of processing resources in at least one processor (for example, a multi-core One core or two cores in the processor) are implemented, while the data writing unit, the data reading unit and the signal output unit are processed by the rest of the at least one processor (eg other cores in a multi-core processor). For example, it is implemented in the form of hardware.
  • the above-mentioned signal processing apparatus can be a programmable device, such as a hardware programmable device, such as an FPGA (Field Programmable Gate Array, Field Programmable Gate Array).
  • the first signal processing unit, the second signal processing unit, the signal input unit, the data writing unit, the data reading unit, and the signal output unit in the above-mentioned signal processing apparatus may all include configurable logic modules ( Configurable Logic Block, CLB), and the different units are coupled through an internal connection line (Interconnect).
  • CLB Configurable Logic Block
  • the above-mentioned functional units can also be realized by a combination of software and hardware, for example, the signal input unit, the data writing unit, the data reading unit and the signal output unit are realized by hardware circuits, while the first signal processing unit and the second signal processing unit are realized by hardware circuits.
  • the unit is a software function module generated after the CPU reads the program code stored in the memory.
  • the signal input unit 310 , the first signal processing unit 320 , the second signal processing unit 330 , the data writing unit 340 , the data reading unit 350 and the signal output unit 360 realize the above functions for more details, please refer to the previous methods. The descriptions in the embodiments are not repeated here.
  • the computer program product includes one or more computer instructions.
  • the computer may be a general purpose computer, special purpose computer, computer network, or other programmable device.
  • the computer instructions may be stored in a computer-readable storage medium.
  • the computer-readable storage medium can be any available medium that can be accessed by a computer, or a data storage device such as a server, data center, etc. that includes one or more available media integrated.
  • the available media may be magnetic media (eg, floppy disks, magnetic disks, magnetic tapes), optical media (eg, DVD (Digital Versatile Disk)), or semiconductor media (eg, solid state drives (SSD)), etc. .
  • Some embodiments of the present disclosure provide a computer-readable storage medium (eg, a non-transitory computer-readable storage medium) having computer program instructions stored therein that when executed on a processor , causing the processor to execute the signal processing method described in any of the foregoing embodiments, for example, one or more steps in the signal processing method.
  • a computer-readable storage medium eg, a non-transitory computer-readable storage medium
  • the above-mentioned computer-readable storage media may include, but are not limited to: magnetic storage devices (eg, hard disks, floppy disks or magnetic tapes, etc.), optical disks (eg, CDs (Compact Disk), DVDs, etc.), smart cards and Flash memory device (eg, EPROM (Erasable Programmable Read-Only Memory), card, stick or key drive, etc.).
  • the various computer-readable storage media described in this disclosure may represent one or more devices and/or other machine-readable storage media for storing information.
  • the term "machine-readable storage medium" may include, but is not limited to, wireless channels and various other media capable of storing, containing, and/or carrying instructions and/or data.
  • the computer program product includes computer program instructions that, when executed on a computer, cause the computer to perform the signal processing method described in the above embodiments, eg, one or more steps in the signal processing method.
  • Some embodiments of the present disclosure also provide a computer program.
  • the computer program When the computer program is executed on a computer, the computer program causes the computer to execute the signal processing method described in the above-mentioned embodiments, eg, one or more steps in the signal processing method.

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Abstract

一种信号处理方法，包括：获得第一帧同步信号；第一帧同步信号包括多个第一脉冲，一个第一脉冲的后沿和第一脉冲的后一第一脉冲的前沿之间的时间为第一时间，第一时间对应第一整数个第一像素时钟信号的脉冲；生成同步校准信号；同步校准信号包括多个第二脉冲，每个第二脉冲的触发沿与一个第一脉冲的后沿处于同一时刻；第二脉冲的触发沿为第二脉冲的前沿或后沿，第二脉冲的宽度与第一像素时钟信号的脉冲宽度或第二像素时钟信号的脉冲宽度相等；生成第二帧同步信号；第二帧同步信号包括多个第三脉冲，每个第二脉冲的触发沿与第二脉冲之后最靠近的一个第三脉冲的前沿之间的时间为第二时间，第二时间对应第一整数个第二像素时钟信号的脉冲。

Description

信号处理方法及装置、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种信号处理方法及装置、显示装置。
背景技术
随着显示产品的普及，显示产品的显示效果的要求越来越高。例如，在显示产品显示图像的过程中，不希望衍生出新的图像，这样可以更真实的还原图像。
发明内容
一方面，提供一种信号处理方法。所述信号处理方法包括：获得第一帧同步信号；所述第一帧同步信号包括多个第一脉冲，一个第一脉冲的后沿和所述第一脉冲的后一第一脉冲的前沿之间的时间为第一时间，所述第一时间对应第一整数个第一像素时钟信号的脉冲；生成同步校准信号；所述同步校准信号包括多个第二脉冲，每个第二脉冲的触发沿与一个所述第一脉冲的后沿处于同一时刻；所述第二脉冲的触发沿为所述第二脉冲的前沿或后沿，所述第二脉冲的宽度与第一像素时钟信号的脉冲宽度或第二像素时钟信号的脉冲宽度相等；生成第二帧同步信号；所述第二帧同步信号包括多个第三脉冲，每个第二脉冲的触发沿与所述第二脉冲之后最靠近的一个所述第三脉冲的前沿之间的时间为第二时间，所述第二时间对应所述第一整数个所述第二像素时钟信号的脉冲。
在一些实施例中，所述生成第二帧同步信号包括：统计所述第二像素时钟信号的脉冲个数；在所述第二像素时钟信号的脉冲个数达到所述第一整数的情况下，生成所述第二帧同步信号中的第三脉冲的前沿；在所述第二像素时钟信号的脉冲个数未达到第二整数的情况下，响应于所述第二脉冲的触发沿，生成所述第二帧同步信号中的所述第三脉冲的后沿，并返回执行所述统计所述第二像素时钟信号的脉冲个数；或者，响应于所述第二像素时钟信号的脉冲个数达到第二整数，生成所述第二帧同步信号中的所述第三脉冲的后沿，并返回执行所述统计所述第二像素时钟信号的脉冲个数；以及响应于所述第二脉冲的触发沿，返回执行所述统计所述第二像素时钟信号的脉冲个数。
在一些实施例中，所述生成同步校准信号，包括：获得第一信号，所述第一信号和所述第一帧同步信号互为反转信号；获得第二信号，所述第二信号相比于所述第一帧同步信号延迟所述第一像素时钟信号或所述第二像素时 钟信号的一个脉冲宽度；根据所述第一信号和所述第二信号，得到所述同步校准信号。
在一些实施例中，所述根据所述第一信号和所述第二信号，得到所述同步校准信号，包括：将所述第一信号和所述第二信号进行逻辑运算，得到所述同步校准信号。
在一些实施例中，所述获得第一信号，包括：对所述第一帧同步信号取反，得到所述第一信号。
在一些实施例中，所述第二像素时钟信号的频率大致等于所述第一像素时钟信号的频率；在所述同步校准信号中的至少一组相邻两个第二脉冲的时间段内，所述第二帧同步信号具有一个第三脉冲。
在一些实施例中，所述第三脉冲的脉冲宽度对应的所述第二像素时钟信号的脉冲个数小于或等于所述第一脉冲的脉冲宽度对应的所述第一像素时钟信号的脉冲个数。
在一些实施例中，所述第二像素时钟信号的频率的N倍大致等于所述第一像素时钟信号的频率；N为大于1的整数；在所述同步校准信号中的至少一组相邻两个第二脉冲的时间段内，所述第二帧同步信号具有N个第三脉冲。
在一些实施例中，N为2。在所述同步校准信号中的至少一组相邻两个第二脉冲的时间段内，所述第二帧同步信号具有两个第三脉冲。所述两个第三脉冲中的前一第三脉冲的脉冲宽度对应的所述第二像素时钟信号的脉冲个数等于所述第一脉冲的脉冲宽度对应的所述第一像素时钟信号的脉冲个数；所述两个第三脉冲中的后一第三脉冲的脉冲宽度对应的所述第二像素时钟信号的脉冲个数小于或等于所述第一脉冲的脉冲宽度对应的所述第一像素时钟信号的脉冲个数。
在一些实施例中，所述获得第一帧同步信号包括：获得第一视频信号，所述第一视频信号包括所述第一帧同步信号和视频数据。
在一些实施例中，所述信号处理方法还包括：将所述视频数据写入存储装置；根据所述第二帧同步信号，从所述存储装置中读取所述视频数据，得到第二视频信号；所述第二视频信号包括所述第二帧同步信号和所述视频数据。
在一些实施例中，所述信号处理方法还包括：输出所述第二视频信号。
在一些实施例中，所述信号处理方法还包括：检测得到所述第一视频信号的第一帧率；获得显示模组的第二帧率的范围；在所述第一帧率的N倍位于所述第二帧率的范围内的情况下，在所述同步校准信号中的至少一组相邻 两个第二脉冲的时间段内，所述第二帧同步信号具有N个第三脉冲；N为大于1的整数。在所述第一帧率位于所述第二帧率的范围内的情况下，在所述同步校准信号中的至少一组相邻两个第二脉冲的时间段内，所述第二帧同步信号具有一个第三脉冲。
另一方面，提供一种信号处理装置。所述信号处理装置包括：信号输入单元、第一信号处理单元和第二信号处理单元。所述信号输入单元被配置为获得第一帧同步信号。所述第一帧同步信号包括多个第一脉冲，一个第一脉冲的后沿和所述第一脉冲的后一第一脉冲的前沿之间的时间为第一时间，所述第一时间对应第一整数个第一像素时钟信号的脉冲。所述第一信号处理单元被配置为生成同步校准信号。其中，所述同步校准信号包括多个第二脉冲，每个第二脉冲的触发沿与一个所述第一脉冲的后沿处于同一时刻；所述第二脉冲的触发沿为所述第二脉冲的前沿或后沿，所述第二脉冲的宽度与第一像素时钟信号的脉冲宽度或第二像素时钟信号的脉冲宽度相等。所述第二信号处理单元被配置为生成第二帧同步信号。所述第二帧同步信号包括多个第三脉冲，每个第二脉冲的触发沿与所述第二脉冲之后最靠近的一个所述第三脉冲的前沿之间的时间为第二时间，所述第二时间对应所述第一整数个所述第二像素时钟信号的脉冲。
在一些实施例中，所述信号输入单元被配置为获得第一视频信号，所述第一视频信号包括所述第一帧同步信号和视频数据。
在一些实施例中，所述信号处理装置还包括：数据写入单元、数据读取单元和信号输出单元。所述数据写入单元被配置为将所述第一视频信号中的视频数据写入存储装置。所述数据读取单元被配置为根据所述第二帧同步信号，读取所述存储装置中的所述视频数据。所述信号输出单元被配置为输出包括所述第二帧同步信号和所述视频数据的第二视频信号。
又一方面，提供一种信号处理装置。所述信号处理装置包括：存储器和处理器。所述存储器中存储一个或多个计算机程序。所述处理器与所述存储器耦接；所述处理器被配置为执行所述计算机程序，以使得所述处理器实现如上述任一实施例中所述的信号处理方法。
又一方面，提供一种信号处理装置。所述信号处理装置为芯片。所述芯片被配置为实现如上述任一实施例中所述的信号处理方法。
又一方面，提供一种显示装置。所述显示装置包括：显示模组和如上述任一实施例所述的信号处理装置。所述信号处理装置与所述显示模组耦接；所述信号处理装置被配置为将第二视频信号输出至所述显示模组。
在一些实施例中，所述显示装置还包括：存储装置。所述存储装置与所述信号处理装置耦接。所述存储装置被配置为存储第一视频信号中的视频数据。
再一方面，提供一种计算机可读存储介质。所述计算机可读存储介质存储有计算机程序指令，所述计算机程序指令在处理器上运行时，使得所述处理器执行如上述任一实施例所述的信号处理方法。
又一方面，提供一种计算机程序产品。所述计算机程序产品包括计算机程序指令，在计算机上执行所述计算机程序指令时，所述计算机程序指令使计算机执行如上述任一实施例所述的信号处理方法。
又一方面，提供一种计算机程序。当所述计算机程序在计算机上执行时，所述计算机程序使计算机执行如上述任一实施例所述的信号处理方法。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的显示装置的一种结构图；
图2为根据一些实施例的显示模组的一种结构图；
图3为根据一些实施例的信号处理装置的一种结构图；
图4为根据一些实施例的显示装置的另一种结构图；
图5为根据一些实施例的信号处理方法中视频信号的一种传输过程图；
图6A为根据一些实施例的信号处理方法的一种信号时序图；
图6B为根据一些实施例的信号处理方法中视频信号的另一种传输过程图；
图7A为根据一些实施例的信号处理方法的另一种信号时序图；
图7B为根据一些实施例的信号处理方法中视频信号的又一种传输过程图；
图8为根据一些实施例的信号处理方法的又一种信号时序图；
图9A为根据一些实施例的信号处理方法的又一种信号时序图；
图9B为根据一些实施例的信号处理方法的又一种信号时序图；
图10A为根据一些实施例的信号处理方法的又一种信号时序图；
图10B为根据一些实施例的信号处理方法的又一种信号时序图；
图11为根据一些实施例的信号处理方法的又一种信号时序图；
图12为根据一些实施例的信号处理方法的又一种信号时序图；
图13为根据一些实施例的信号处理方法的又一种信号时序图；
图14为根据一些实施例的显示装置的又一种结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是 “当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
如本文所使用的那样，“大致”、“约”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
本公开的实施例提供一种显示装置。示例性地，该显示装置可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是图像的任何装置。示例性地，显示装置可以是多种电子装置中的一种，所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。本公开的实施例对上述显示装置的具体形式不做特殊限制。
在一些实施例中，如图1所示，显示装置100包括显示模组200和信号处理装置300。其中，显示模组200与信号处理装置300耦接。
示例性地，如图2所示，显示模组200包括显示面板210。示例性地，显示面板可以包括液晶显示面板(LCD，Liquid Crystal Display)或者自发光型显示面板，例如基于OLED(Organic Light Emitting Diode，有机发光二极管)的显示面板或者基于LED(发光二极管，Light Emitting Diode)的显示面板等。示例性地，在显示面板为液晶显示面板的情况下，显示模组还包括背光模组。
示例性地，如图2所示，显示面板210具有显示区(Active Area，AA)和周边区S。其中，周边区S至少位于AA区外一侧。其中，显示面板200包括设置于AA区中的多个像素P。示例性地，多个像素P可以呈阵列排布。例如，沿图2中X方向(水平方向)排列成一排的像素称为一行像素，沿图2中Y方向(竖直方向)排列成一排的像素称为一列像素。示例性地，每个 像素包括多个子像素；多个子像素包括第一颜色子像素、第二颜色子像素和第三颜色子像素。例如，第一颜色、第二颜色和第三颜色为三基色；例如，第一颜色、第二颜色和第三颜色分别为红色、绿色和蓝色；即，多个子像素包括红色子像素、绿色子像素和蓝色子像素。
其中，信号处理装置被配置为接收第一视频信号，输出第二视频信号。显示模组被配置为根据来自信号处理装置的第二视频信号，显示第二视频信号对应的图像。
示例性地，显示装置可以具有视频信号输入接口，以接收视频信号。例如，视频信号输入接口可以包括SDI(串行数字接口，Serial Digital Interface)、HDMI(高清晰度多媒体接口，High Definition Multimedia Interface)或者DP(显示接口，Display Port)等。示例性地，视频信号输入接口可以包含于信号处理装置中。信号处理装置还包括视频信号多路选通器(MUX)。视频信号多路选通器被配置为在输入至视频信号多路选通器的多个视频信号中，选择一个视频信号从视频信号多路选通器输出。其中，从视频信号多路选通器输出的视频信号可以作为文中的第一视频信号。
示例性地，视频信号包括时序信号和视频数据，时序信号包括同步信号和使能信号(也即有效数据选通信号或数据使能信号)；同步信号包括行同步信号和帧同步信号(也即场同步信号)。例如，第一视频信号包括第一时序信号和视频数据，第一时序信号包括第一同步信号和第一使能信号，第一同步信号包括第一帧同步信号和第一行同步信号；第二视频信号包括第二时序信号和视频数据，第二时序信号包括第二同步信号和第二使能信号，第二同步信号包括第二帧同步信号和第二行同步信号。
其中，行同步信号通常是选择出显示面板上有效行信号区间，帧同步信号通常是选择出显示面板上有效场信号区间。例如，在行同步信号和帧同步信号的共同作用下，可将选择出显示面板对应的有效视频数据的区间。
可以理解的是，在视频信号中，有效视频数据(有效RGB数据)只占视频信号周期中的一部分，而视频信号的行消隐和场消隐期间并不包含有效的视频数据。因此，显示装置中的有关电路在处理视频信号时，可以通过使能信号，将包含有效视频数据的区间和不包含有效视频数据的消隐区间区分开来。不管是行同步信号还是帧同步信号，都应当配合使能信号。例如，在行同步信号作用于像素的过程中，例如，在行同步信号驱动像素中的像素电路的过程中，使能信号中与行同步信号对应的部分与行同步信号配合；在帧同步信号作用于像素的过程中，例如，在帧同步信号驱动像素中的像素电路的 过程中，使能信号中与帧同步信号对应的部分与帧同步信号配合，以保证显示面板可以有效显示视频信号对应的图像。
示例性地，如图2所示，显示模组200还包括控制器220，例如，控制器可以为TCON(Timming Controller，时序控制器)。控制器220与显示面板210耦接。其中，控制器被配置为接收来自信号处理装置的第二视频信号，控制显示面板显示第二视频信号对应的图像。示例性地，显示模组还包括驱动芯片(Driver IC)。驱动芯片与显示面板绑定，控制芯片与控制器耦接。在此情况下，信号处理装置将第二视频信号传输至控制器，该控制器向驱动芯片输出控制信号，驱动芯片根据控制信号向显示面板输出驱动信号，以驱动显示面板进行显示，以显示第二视频信号中的视频数据对应的图像。
本公开的实施例提供的一种信号处理装置，如图3所示，信号处理装置300包括存储器301和处理器302。其中，存储器301与处理器302耦接。
存储器301中存储可在处理器302上运行的一个或多个计算机程序。处理器302执行该计算机程序时，以使处理器302实现如下述任一实施例所述的信号处理方法。
示例性地，上述处理器302可以是一个处理器，也可以是多个处理元件的统称。例如，该处理器302可以是一个通用中央处理器(central processing unit，CPU)，微处理器，特定应用集成电路(application specific integrated circuit，ASIC)，或一个或多个用于控制本公开方案程序执行的集成电路，例如：一个或多个微处理器。示例性地，上述存储器301可以是一个存储器，也可以是多个存储元件的统称，且用于存储可执行程序代码等。且存储器301可以包括随机存储器(Random Access Memory，RAM)，也可以包括非易失性存储器(non-volatile memory)，例如磁盘存储器，闪存(Flash)等。
其中，存储器301用于存储执行本公开方案的应用程序代码，并由处理器302来控制执行。处理器302用于执行存储器301中存储的应用程序代码，以控制处理器302实现本公开下述任一实施例提供的数据传输方法。
本公开的实施例提供一种信号处理装置。其中，如图4所示，信号处理装置300可以为芯片。该芯片被配置为实现如下述任一实施例中的信号处理方法。示例性地，该芯片可以为可编程器件。例如，该可编程器件为CPLD(Complex Programmable Logic Device，复杂可编程逻辑器件)、EPLD(Erasable Programmable Logic Device，可擦除可编辑逻辑器件)或者FPGA(Field Programmable Gate Array，现场可编程门阵列)。
在一些实施例中，如图4所示，显示装置100还包括存储装置400。存储 装置400与信号处理装置300耦接。存储装置400被配置为存储第一视频信号中的视频数据。示例性地，存储装置400可以位于信号处理装置300内。示例性地，存储装置可以包括随机存储器或者双倍速率同步动态随机存储器(Double Data Rate Synchronous Dynamic Random Access Memory，DDR SRAM)，例如存储装置可以为DDR3。
相关技术中，显示装置中的信号处理装置接收到的视频信号的帧率和与显示装置中的显示模组可以正常显示的视频信号的帧率不匹配，例如，信号处理装置接收到的视频信号的帧率为25Hz，显示模组可以正常显示的视频信号的帧率为60Hz，此时，信号处理装置接收5帧视频信号(例如参考图5中的输入帧A1、A2、A3、A4、A5)，信号处理装置向显示模组输出12帧视频信号(例如参考图5中的输出帧A1、A1、A1、A2、A2、A3、A3、A3、A4、A4、A5、A5)，在信号处理装置输出的12帧视频信号中，部分是对输入的一些视频信号(A1和A3)复制3次后输出，部分是对输入的一些视频信号(A2、A4和A5)复制2次后输出，在此情况下，信号处理装置输入的视频信号和输出的视频信号不同步，即，信号处理装置的输入帧和输出帧不同步，且输出帧对输入帧的复制不均匀，例如部分输入帧可以对应输出3帧，部分输入帧可以对应输出2帧，容易导致显示出现跳帧或漏帧的情况，降低显示效果。示例性地，对于显示图像要求较高的显示装置，例如监视器，会降低显示的真实性。
本公开的实施例提供一种信号处理方法。示例性地，该信号处理方法应用于信号处理装置，例如图1、图3和图4中的信号处理装置300。其中，信号处理方法包括：
S10、获得第一帧同步信号。其中，参考图6A和图7A，第一帧同步信号Source_Vsync包括多个第一脉冲M1。一个第一脉冲的后沿和第一脉冲的后一第一脉冲的前沿之间的时间为第一时间T1。第一时间对应第一整数个第一像素时钟信号的脉冲。
示例性地，获得第一帧同步信号包括：获得第一视频信号。其中，第一视频信号包括第一帧同步信号和视频数据。可以理解的是，视频数据包括像素数据，例如显示模组中的各个子像素的显示灰阶。
其中，第一帧同步信号中的一个第一脉冲的后沿(即下降沿)和第一脉冲的后一第一脉冲的前沿(即上升沿)之间的第一时间对应的第一像素时钟信号的脉冲的个数为第一整数个；在第一帧同步信号中的一个第一脉冲的后沿(即下降沿)和第一脉冲的后一第一脉冲的前沿(即上升沿)之间的第一 时间段内，第一像素时钟信号的时钟周期的个数为第一整数个，例如，时钟周期可以理解为一个脉冲的前沿(或后沿)至该一个脉冲的下一个脉冲的前沿(或后沿)之间的时间。示例性地，参考图8，第一视频信号还包括第一使能信号Source_DE。例如，该第一整数为(VBP+VAC+VFP)，VBP表示第一帧同步信号的一个第一脉冲的后沿到第一使能信号Source_DE的脉冲的前沿(有效视频数据的前沿)之间的第一像素时钟信号(PCLK1)的脉冲的个数，VAC表示显示模组中像素的总行数，VFP表示第一帧同步信号的一个第一脉冲的前沿到第一使能信号Source_DE的脉冲的后沿(有效视频数据的后沿)之间的第一像素时钟信号的脉冲的个数。例如，对于显示模组的分辨率为1920×1080的情况，VBP为36，VFP为4，VAC为1080。
其中，第一像素时钟信号可以根据第一视频信号中的第一帧同步信号、第一行同步信号和第一使能信号得到。第一像素时钟信号与第一视频信号的第一帧率有关，例如，第一像素时钟信号的频率为第一视频信号的第一帧率、HTT和VTT三者的乘积，其中，HTT表示一行像素的像素时钟周期的总数，VTT表示一帧时间内HTT的总数。例如，对于显示模组的分辨率为1920×1080的情况，在第一视频信号的帧率为60Hz的情况下，HTT为2200，VTT为1125，则第一像素时钟信号的频率为148.5MHz；在第一视频信号的帧率为30Hz的情况下，HTT为2200，VTT为1125，则第一像素时钟信号的频率为74.5MHz；在第一视频信号的帧率为50Hz的情况下，HTT为2640，VTT为1125，则第一像素时钟信号的频率为148.5MHz；在第一视频信号的帧率为25Hz的情况下，HTT为2640，VTT为1125，则第一像素时钟信号的频率为74.5MHz；在第一视频信号的帧率为48Hz的情况下，HTT为2570，VTT为1125，则第一像素时钟信号的频率为148.5MHz；在第一视频信号的帧率为24Hz的情况下，HTT为2750，VTT为1125，则第一像素时钟信号的频率为74.5MHz。其中，第一帧同步信号的第一脉冲的脉冲宽度为VSW，即，VSW为第一帧同步信号的有效宽度；例如，对于显示模组的分辨率为1920×1080的情况，VSW为5。
S20、生成同步校准信号。其中，参考图6A和图7A，同步校准信号Sync_eof包括多个第二脉冲M2。每个第二脉冲的触发沿与一个第一脉冲的后沿处于同一时刻。第二脉冲的触发沿为第二脉冲的前沿(参考图6A)或后沿(参考图13)，第二脉冲的宽度与第一像素时钟信号的脉冲宽度或第二像素时钟信号的脉冲宽度相等。
其中，可以根据显示模组的第二帧率得到第二像素时钟信号的频率。例 如，第一像素时钟信号的频率为显示模组的第二帧率、HTT和VTT三者的乘积。示例性地，显示模组的第二帧率的范围可以约为40Hz～70Hz，例如，第二帧率为48Hz、50Hz或60Hz等。
示例性地，生成同步校准信号，包括：
S21、获得第一信号。其中，参考图11，第一信号Q1和第一帧同步信号Source_Vsync互为反转信号。可以理解都是，第一信号的相位和第一帧同步信号的相位相差180度。
示例性地，获得第一信号包括：对第一帧同步信号取反，得到第一信号。例如，可以通过反相器，对第一帧同步信号取反。例如，该反相器包含与信号处理装置中。
或者，示例性地，获得第一信号包括：将第一帧同步信号寄存预设时间后，得到第一信号。例如，可以通过寄存器，将第一帧同步信号寄存预设时间，例如该预设时间可以是将第一帧同步信号的相位延迟180度所需的时间，得到第一信号。例如，该寄存器包含与信号处理装置中。
S22、获得第二信号。其中，参考图11，第二信号Q2相比于第一帧同步信号Source_Vsync延迟第一像素时钟信号或第二像素时钟信号的一个脉冲宽度，即，第二信号Q2相比于第一帧同步信号Source_Vsync延迟第一像素时钟信号的一个脉冲宽度K PCLK1，或者，第二信号Q2相比于第一帧同步信号Source_Vsync延迟第二像素时钟信号的一个脉冲宽度K PCLK2。
例如，可以将第一帧同步信号寄存第一像素时钟信号或第二像素时钟信号的一个脉冲宽度，得到第二信号。
S23、根据第一信号和第二信号，得到同步校准信号。
示例性地，根据第一信号和第二信号，得到同步校准信号，包括：将第一信号和第二信号进行逻辑运算，得到同步校准信号。例如，将第一信号和第二信号经过逻辑电路后，输出的信号为同步校准信号。例如，该逻辑电路包含于信号处理装置中。例如，该逻辑运算可以为与运算；该逻辑电路可以为与门。例如，将第一信号和第二信号经过与门后，输出的信号为同步校准信号；例如，该与门包含于信号处理装置中。
在此情况下，同步校准信号中的第二脉冲的前沿与第一帧同步信号中的一个第一脉冲的后沿处于同一时刻，此时，第二脉冲的前沿作为第二脉冲的触发沿。另外，对于第二脉冲的后沿作为第二脉冲的触发沿的情况，可以参考图13根据实际情况进行设计，在此不做限定。
S30、生成第二帧同步信号VTG_vsync。其中，参考图6A和图7A，第二 帧同步信号包括多个第三脉冲M3，每个第二脉冲M2的触发沿(例如前沿)与该第二脉冲M2之后最靠近的一个第三脉冲M3的前沿之间的时间为第二时间T2，第二时间对应第一整数个第二像素时钟信号的脉冲。
示例性地，生成第二帧同步信号包括：
统计第二像素时钟信号的脉冲个数。
在第二像素时钟信号的脉冲个数达到第一整数的情况下，生成第二帧同步信号中的第三脉冲的前沿。
在第二像素时钟信号的脉冲个数未达到第二整数的情况下，响应于第二脉冲的触发沿，生成第二帧同步信号中的第三脉冲的后沿，并返回执行统计第二像素时钟信号的脉冲个数。
或者，响应于第二像素时钟信号的脉冲个数达到第二整数，生成第二帧同步信号中的第三脉冲的后沿，并返回执行统计第二像素时钟信号的脉冲个数；以及响应于第二脉冲的触发沿，返回执行统计第二像素时钟信号的脉冲个数。
例如，在同步校准信号的一个第二脉冲的触发沿所在时刻处，行计数器r_PCNT和列计数器r_LCNT的数值均处于初始化状态。例如，在同步校准信号的一个第二脉冲的触发沿所在时刻处，行计数器r_PCNT和列计数器r_LCNT的数值均为0。统计第二像素时钟信号的脉冲个数，例如，可以从行计数器r_PCNT和列计数器r_LCNT的数值均处于初始化状态的时刻开始，统计第二像素时钟信号的脉冲个数。每经过第二像素时钟信号的一个脉冲，行计数器r_PCNT的数值累加1。每当行计数器r_PCNT的数值达到第一参数时，例如第一参数为HTT，行计数器r_PCNT的数值返回初始化，列计数器r_LCNT的数值加1；从行计数器r_PCNT的数值达到HTT的时刻开始，行计数器r_PCNT的数值从初始化开始重新计数。
在列计数器r_LCNT的数值达到第二参数的情况下，例如，第二参数为(VBP+VAC+VFP)，此时，第二像素时钟信号的脉冲个数达到第一整数，生成第二帧同步信号中的第三脉冲的前沿。例如，第一整数为第一参数与第二参数的乘积，例如，第一整数为HTT×(VBP+VAC+VFP)。
在列计数器r_LCNT的数值达到第三参数的情况下，例如，第三参数为(VBP+VAC+VFP+VSW)，此时，第二像素时钟信号的脉冲个数达到第二整数，生成第二帧同步信号中的第三脉冲的后沿。例如，第二整数为第一参数与第三参数的乘积，例如，第二整数为HTT×(VBP+VAC+VFP+VSW)。
在列计数器r_LCNT的数值未达到第三参数的情况下，此时，第二像素 时钟信号的脉冲个数未达到第二整数，在第二脉冲的触发沿的时刻，生成第二帧同步信号中的第三脉冲的后沿，并且，行计数器r_PCNT和列计数器r_LCNT的数值均重置为初始化状态，从第二脉冲的触发沿开始，重新统计第二像素时钟信号的脉冲个数。
需要说明的是，上述是采用两个计数器对第二像素时钟信号的脉冲个数进行统计，但也不限于此，可以根据实际情况进行设计，例如，可以采用一个计数器对第二像素时钟信号的脉冲个数进行统计。
示例性地，信号处理方法还包括：响应于第二像素时钟信号的脉冲个数达到第二整数，在生成第二帧同步信号中的第三脉冲的后沿的同时，返回执行统计第二像素时钟信号的脉冲个数。
例如，在列计数器r_LCNT的数值达到第三参数的情况下，此时，第二像素时钟信号的脉冲个数达到第二整数，生成第二帧同步信号中的第三脉冲的后沿。与此同时，行计数器r_PCNT和列计数器r_LCNT的数值均重置为初始化状态，从第二像素时钟信号的脉冲个数达到第二整数开始，重新统计第二像素时钟信号的脉冲个数。
可以理解的是，相比于在第二像素时钟信号的脉冲个数达到第二整数的时刻，在第二脉冲的触发沿的时刻，行计数器r_PCNT和列计数器r_LCNT的数值优先处于初始化。
需要说明的是，第二像素时钟信号的脉冲个数达到第二整数指的是在一个统计周期内，该一个统计周期可以是从同步校准信号的一个第二脉冲的触发沿所在时刻开始，第二像素时钟信号的脉冲的个数达到VTT的时刻为止的时间段。
在一些实施例中，第二像素时钟信号的频率大致等于第一像素时钟信号的频率。例如，大致等于可以理解为第二像素时钟信号的频率与第一像素时钟信号的比值在第一阈值的范围内；例如，第一阈值的范围为0.9～1.1，例如，第一阈值可以为0.999、1或者1.001。例如，第一像素时钟信号的频率约为148.5MHz，第二像素时钟信号的频率约为148.5Hz。示例性地，第一视频信号的第一帧率约为48Hz，显示模组对应的第二帧率约为48Hz；或者，第一视频信号的第一帧率约为50Hz，显示模组对应的第二帧率约为50Hz；或者，第一视频信号的第一帧率约为60Hz，显示模组对应的第二帧率约为60Hz。
在同步校准信号中的至少一组相邻两个第二脉冲的时间段内，第二帧同步信号具有一个第三脉冲。例如，参考图6A，在同步校准信号Sync_eof中的至少一组相邻两个第二脉冲M2的时间段内，即，相邻两个第二脉冲M2的前 沿之间的时间段内，第二帧同步信号VTG_Vsync具有一个第三脉冲M3。在此情况下，输入一帧第一视频信号的时间段内，可以输出一帧第二视频信号。例如，参考图6B，在输入帧为A2的时间段内，输出帧为A1，即，在输入的一帧第一视频信号为A2的时间段内，输出的一帧第二视频信号为A1，其中A1和A2分别代表不同的视频数据，且A1为A2的前一帧视频数据。
示例性地，第三脉冲的脉冲宽度对应的第二像素时钟信号的脉冲个数小于或等于第一脉冲的脉冲宽度对应的所述第一像素时钟信号的脉冲个数(参考图9A和图9B中的第一帧同步信号Source_Vsync和第二帧同步信号VTG_Vsync)。例如，在同步校准信号中的至少一组相邻两个第二脉冲的时间段内，一个第二脉冲的触发沿与该第二脉冲之后的最靠近的一个第三脉冲的前沿的时间间隔对应第二像素时钟信号的脉冲的个数为第一整数个。
可以理解的是，对于在同步校准信号中的至少一组相邻两个第二脉冲的时间段内，第二帧同步信号中的一个第三脉冲，在该第三脉冲的生成过程中，从相邻两个第二脉冲的前一第二脉冲的前沿的时刻开始，对第二像素时钟信号的脉冲个数进行计数，如果在同步校准信号的第二脉冲的到来的时刻，第二像素时钟信号的脉冲的个数未达到第二整数个，则生成的该第三脉冲的脉冲宽度小于第一帧同步信号的第一脉冲的脉冲宽度，此时，在第三脉冲的后沿至该第三脉冲之后最靠近的第二脉冲的前沿的时间段内，第二帧同步信号处于低电平，即，第二帧同步信号处于消隐阶段；或者，如果在同步校准信号的第二脉冲的到来的时刻，第二像素时钟信号的脉冲的个数达到第二整数个，则生成的该第三脉冲的脉冲宽度等于第一帧同步信号的第一脉冲的脉冲宽度。
在一些实施例中，第二像素时钟信号的频率的N倍大致等于第一像素时钟信号的频率。N为大于1的整数，例如N为2或3。例如，大致等于可以理解为第二像素时钟信号的频率的N倍与第一像素时钟信号的比值在第二阈值的范围内；例如，第二阈值的范围为0.9～1.1，例如，第二阈值可以为0.99、0.999、1或者1.001。例如，第一像素时钟信号的频率约为74.25MHz，第二像素时钟信号的频率约为148.5Hz。示例性地，第一视频信号的第一帧率约为24Hz，显示模组对应的第二帧率约为48Hz；或者，第一视频信号的第一帧率约为25Hz，显示模组对应的第二帧率约为50Hz；或者，第一视频信号的第一帧率约为30Hz，显示模组对应的第二帧率约为60Hz。
在同步校准信号中的至少一组相邻两个第二脉冲的时间段内，第二帧同步信号具有N个第三脉冲。该N个第三脉冲相邻。例如，N为2；在同步校 准信号中的至少一组相邻两个第二脉冲的时间段内，第二帧同步信号具有两个第三脉冲。例如，参考图7A，在同步校准信号Sync_eof中的至少一组相邻两个第二脉冲M2的时间段内，即，相邻两个第二脉冲M2的前沿之间的时间段内，第二帧同步信号VTG_Vsync具有两个第三脉冲M3。在此情况下，输入一帧第一视频信号的时间段内，可以输出两帧第二视频信号。例如，参考图7B，在输入帧为A2的时间段内，输出帧为A1和A1，即，在输入的一帧第一视频信号为A2的时间段内，输出的两帧第二视频信号分别为A1。
示例性地，两个第三脉冲中的前一第三脉冲的脉冲宽度对应的第二像素时钟信号的脉冲个数等于第一脉冲的脉冲宽度对应的第一像素时钟信号的脉冲个数。两个第三脉冲中的后一第三脉冲的脉冲宽度对应的第二像素时钟信号的脉冲个数小于或等于第一脉冲的脉冲宽度对应的第一像素时钟信号的脉冲个数(参考图10A和图10B中的第一帧同步信号Source_Vsync和第二帧同步信号VTG_Vsync)。其中，第三脉冲的脉冲宽度对应的第二像素时钟信号的脉冲个数不一定为整数。例如，两个第三脉冲中的前一第三脉冲的脉冲宽度大于或等于后一第三脉冲的脉冲宽度。
例如，在同步校准信号中的至少一组相邻两个第二脉冲的时间段内，两个第三脉冲中的前一第三脉冲的前沿与该前一第三脉冲之前的最靠近的第二脉冲的前沿的时间间隔对应第一整数个第二像素时钟信号的脉冲，两个第三脉冲中的前一第三脉冲的前沿与该前一第三脉冲之前的最靠近的第二脉冲的前沿的时间间隔对应第二整数个第二像素时钟信号的脉冲。
例如，在同步校准信号中的至少一组相邻两个第二脉冲的时间段内，两个第三脉冲中的后一第三脉冲的前沿与前一第三脉冲的后沿的时间间隔对应第一整数个第二像素时钟信号的脉冲，即，在两个第三脉冲中的后一第三脉冲的前沿与前一第三脉冲的后沿的时间间隔内，第二像素时钟信号的脉冲的个数为第一整数个。
可以理解的是，对于在同步校准信号中的至少一组相邻两个第二脉冲的时间段内，第二帧同步信号中连续的两个第三脉冲中的后一第三脉冲，在该后一第三脉冲的生成过程中，从前一第三脉冲的后沿的时刻开始，对第二像素时钟信号的脉冲个数进行计数，如果在同步校准信号的第二脉冲的到来的时刻，第二像素时钟信号的脉冲的个数未达到第二整数个，则生成的该后一第三脉冲的脉冲宽度对应的第二像素时钟信号的脉冲个数小于第一帧同步信号的第一脉冲的脉冲宽度对应的第一像素时钟信号的脉冲个数，此时，在后一第三脉冲的后沿至该后一第三脉冲之后最靠近的第二脉冲的前沿的时间段 内，第二帧同步信号处于低电平，即，第二帧同步信号处于消隐阶段；或者，如果在同步校准信号的第二脉冲的到来的时刻，第二像素时钟信号的脉冲的个数达到第二整数个，则生成的该后一第三脉冲的脉冲宽度对应的第二像素时钟信号的脉冲个数等于第一帧同步信号的第一脉冲的脉冲宽度对应的第一像素时钟信号的脉冲个数。
因此，本公开的实施例提供一种信号处理方法，获得的第一帧同步信号中的一个第一脉冲的后沿和其后一第一脉冲的前沿之间的时间为第一时间，第一时间对应第一整数个第一像素时钟信号的脉冲；生成的同步校准信号中的每个第二脉冲的触发沿与一个第一脉冲的后沿处于同一时刻；生成的第二帧同步信号，每个第二脉冲的触发沿与第二脉冲之后最靠近的一个第三脉冲的前沿之间的时间为第二时间，第二时间对应第一整数个所述第二像素时钟信号的脉冲。在此情况下，通过同步校准信号，使得在第一帧同步信号的每个第一脉冲的周期内，每个第一脉冲的后沿(即第二脉冲的触发沿)与该第一脉冲之后最靠近的一个第三脉冲的前沿之间的时间保持不变，这样，可以保证第二帧同步信号与第一帧同步信号同步。例如，输入一帧视频信号的时间段内，可以输出一帧视频信号，使得输入帧和输出帧可以实现单帧同步；或者，输入一帧视频信号的时间段内，输出两帧视频信号，使得输出帧相对于输入帧可以实现双帧同步。在此情况下，可以避免信号处理装置的输入帧视频信号和输出帧视频信号出现时间延迟，且延迟的时长随着帧数的增多而不断累积，导致输出帧和输入帧出现跳帧或者相差至少一帧的情况，也可以避免输出帧不均匀的问题，这样，可以提高显示图像的准确性，也可以提高显示图像的真实性。
并且，可以从第一帧同步信号的第一脉冲的后沿开始，对第二像素时钟信号的脉冲个数进行统计，以生成第二帧同步信号的第三脉冲，这样，可以减小第二帧同步信号的第三脉冲的脉冲宽度对应的第二像素时钟信号的脉冲个数，使得在一输入帧的结束时刻处，第三脉冲的后沿不会延迟于第一脉冲的后沿，保证输入帧和输出帧同步，从而可以提高显示效果。
在一些实施例中，信号处理方法还包括：将视频数据写入存储装置；根据第二帧同步信号，从存储装置中读取视频数据，得到第二视频信号。其中第二视频信号包括第二帧同步信号和视频数据。
可以理解的是，根据第二帧同步信号，可以得到第二使能信号VTG_DE(参考图12)，根据第二使能信号VTG_DE，从存储装置中读取视频数据，得到第二视频信号。例如，对于第一像素时钟信号的频率等于第二像素时钟 信号的频率，第一视频信号的第一帧率等于显示模组的第二帧率，此时，在信号处理装置接收一帧视频信号(即第一视频信号)的时间段内，信号处理装置可以输出一帧视频信号(即第二视频信号)。例如，对于第一像素时钟信号的频率小于第二像素时钟信号的频率，第一视频信号的第一帧率小于显示模组的第二帧率，此时，在信号处理装置获得一帧视频信号(即第一视频信号)的时间段内，信号处理装置可以输出两帧视频信号(即第二视频信号)，且该两帧视频信号对应的视频数据相同。
示例性地，第二使能信号VTG_DE的脉冲宽度为VAC的时长。例如，在一个计数周期(VTT)内，在行计数器r_PCNT的数值大于或等于1，且小于HAC，及，列计数器r_LCNT的数值大于VSW+VBP，且小于或等于VSW+VBP+VAC的情况下，第二使能信号VTG_DE为高电平信号。示例性地，第二行同步信号VTG_Hsync的脉冲宽度为HSW的时长，HSW表示第二行同步信号VTG_Hsync的脉冲的有效宽度。在一个计数周期(VTT)内，在行计数器r_PCNT的数值大于(HAC+HFP)，且小于或等于(HAC+HFP+HSW)的情况下，第二行同步信号VTG_Hsync为高电平信号，HFP表示第二行同步信号的脉冲的前沿到第二使能信号的后沿(有效视频数据的后沿)之间的第二像素时钟信号的脉冲的个数，HAC表示显示模组中一行像素中像素的总数。例如，对于显示模组的分辨率为1920×1080的情况，HAC为1920，HFP为88，HSW为44。
示例性地，信号处理装置可以包括写入控制器(WDMA)和读控制器(RDMA)。写入控制器用于控制视频数据写入存储装置中；读取控制器用于控制从存储装置中读取视频数据。信号处理装置还可以包括读写控制器(MIG)和总线仲裁器(AXI Interconnect)。读写控制器可以用于控制对存储装置的读写视频数据的时序，例如，读写控制器可以用于控制写入控制器将视频数据写入存储装置的时序，及，控制读取控制器将视频数据从存储装置中读取的时序，避免写入视频数据和读取视频数据相互干扰。总线仲裁器可以用于使信号处理装置通过总线仲裁器与存储装置进行数据交互。
在一些实施例中，信号处理方法还包括：输出第二视频信号。可以理解都是，信号处理装置将第二视频信号输出至显示模组，显示模组可以显示第二视频信号对应的图像。示例性地，信号处理装置可以通过VBO(V-by-One，高清数字显示接口)向显示模组输出第二视频信号；例如，信号处理装置可以包括VBO接口。例如，显示模组包括时序控制器和显示面板，时序控制器根据第二视频信号中的第二同步信号和视频数据，控制显示面板显示视频数 据对应的图像。其中，在信号处理装置获得的一帧视频信号的时间段内，信号处理装置输出的视频信号中的视频数据为该输入的一帧视频信号的上一帧视频信号中的视频数据。
可以理解的是，在第一视频信号的第一帧率位于显示模组的第二帧率的范围内的情况下，信号处理装置获得一帧视频信号的时间段内，信号处理装置输出一帧视频信号，使得信号处理装置的输入帧和输出帧可以实现单帧同步；在第一视频信号的第一帧率的N倍位于显示模组的第二帧率的范围内的情况下，信号处理装置获得一帧视频信号的时间段内，信号处理装置输出N帧视频信号，使得信号处理装置的输出帧相对于输入帧可以实现N帧同步。在此情况下，可以避免因输入帧和输出帧不同步，也可以避免信号处理装置的输入帧视频信号和输出帧视频信号出现时间延迟，且延迟的时长随着帧数的增多而不断累积，导致输出帧和输入帧出现跳帧或者相差至少一帧的情况，这样，信号处理装置向显示模组输出的视频信号与信号处理装置接收的视频信号之间出现误差，显示模组显示的图像的准确性降低，影响显示图像的真实性。
在一些实施例中，信号处理方法还包括：检测得到第一视频信号的第一帧率；获得显示模组的第二帧率的范围。其中，在第一帧率的N倍位于第二帧率的范围内的情况下，在同步校准信号中的至少一组相邻两个第二脉冲的时间段内，第二帧同步信号具有N个第三脉冲。N为大于1的整数。在第一帧率位于第二帧率的范围内的情况下，在同步校准信号中的至少一组相邻两个第二脉冲的时间段内，第二帧同步信号具有一个第三脉冲。
可以理解的是，在第一帧率的N倍位于第二帧率的范围内的情况下，信号处理装置的一帧输入帧对应N帧输出帧，呈N帧同步模式。在第一帧率的2倍(即N为2)位于第二帧率的范围内的情况下，信号处理装置的一帧输入帧对应两帧输出帧，呈双帧同步模式。在第一帧率位于第二帧率的范围内的情况下，信号处理装置的一帧输入帧对应一帧输出帧，呈单帧同步模式；在此情况下，信号处理装置可以根据不同的第一帧率，通过调用相应的程序生成不同的第二帧同步信号。
示例性地，信号处理装置还包括帧率检测器，该帧率检测器可以检测得到第一视频信号的第一帧率。
此外，在信号处理装置开始进行信号处理之前，可以通过复位信号，对信号处理装置进行复位(也即初始化)，避免噪声信号干扰。
本公开的实施例提供一种信号处理装置。该信号处理装置可以实现上述 任一实施例所述的信号处理方法。其中，如图14所示，信号处理装置300包括：信号输入单元310、第一信号处理单元320和第二信号处理单元330。
信号输入单元被配置为获得第一帧同步信号。其中，第一帧同步信号包括多个第一脉冲，一个第一脉冲的后沿和第一脉冲的后一第一脉冲的前沿之间的时间为第一时间，第一时间对应第一整数个第一像素时钟信号的脉冲。
第一信号处理单元被配置为生成同步校准信号。其中，同步校准信号包括多个第二脉冲，每个第二脉冲的触发沿与一个第一脉冲的后沿处于同一时刻；第二脉冲的触发沿为第二脉冲的前沿或后沿，第二脉冲的宽度与第一像素时钟信号的脉冲宽度或第二像素时钟信号的脉冲宽度相等。
第二信号处理单元被配置为生成第二帧同步信号。其中，第二帧同步信号包括多个第三脉冲；每个第二脉冲的触发沿与第二脉冲之后最靠近的一个第三脉冲的前沿之间的时间为第二时间，第二时间对应第一整数个第二像素时钟信号的脉冲。
在一些实施例中，信号输入单元被配置为获得第一视频信号。第一视频信号包括第一帧同步信号和视频数据。
在一些实施例中，如图14所示，信号处理装置300还包括：数据写入单元340、数据读取单元350和信号输出单元360。其中，数据写入单元被配置为将第一视频信号中的视频数据写入存储装置。数据读取单元被配置为根据第二帧同步信号，读取存储装置中的视频数据。信号输出单元被配置为输出包括第二帧同步信号和视频数据的第二视频信号。
图14所描述的装置实施例仅仅是示意性的，例如，上述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个模块或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。在本申请各个实施例中的各功能单元可以集成在一个处理模块中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个模块中。图14中上述各个单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。例如，采用软件实现时，上述第一信号处理单元和第二信号处理单元等可以是由至少一个处理器读取存储器中存储的程序代码后，生成的软件功能模块来实现。图14中上述各个单元也可以由计算机(显示装置)中的不同硬件分别实现，例如信号输入单元、第一信号处理单元和第二信号处理单元由至少一个处理器中的一部分处理资源(例如多核处理器中的一个核或两个核)实现，而数据写入单元、数据读取单元和信号输出单元由至少一个处理器中的其余部分处理资源(例如多核处理器中的其他核)。例如，采 用硬件的形式实现，示例性地，上述的信号处理装置可以为可编程器件，例如硬件可编程器件，例如FPGA(Field Programmable Gate Array，现场可编程门阵列)。在此情况下，上述的信号处理装置中的第一信号处理单元、第二信号处理单元、信号输入单元、数据写入单元、数据读取单元和信号输出单元等均可以包括可配置逻辑模块(Configurable Logic Block，CLB)，不同单元之间通过内部连接线(Interconnect)耦接。显然上述功能单元也可以采用软件硬件相结合的方式来实现，例如信号输入单元、数据写入单元、数据读取单元和信号输出单元由硬件电路实现，而第一信号处理单元和第二信号处理单元是由CPU读取存储器中存储的程序代码后，生成的软件功能模块。
图14中信号输入单元310、第一信号处理单元320、第二信号处理单元330、数据写入单元340、数据读取单元350和信号输出单元360实现上述功能的更多细节请参考前面各个方法实施例中的描述，在这里不再重复。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件程序实现时，可以全部或部分地以计算机程序产品的形式实现。该计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行该计算机指令时，全部或部分地产生按照本申请实施例中的流程或功能。该计算机可以是通用计算机、专用计算机、计算机网络或者其他可编程装置。该计算机指令可以存储在计算机可读存储介质中。该计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包括一个或多个可用介质集成的服务器、数据中心等数据存储设备。该可用介质可以是磁性介质(例如，软盘、磁盘、磁带)、光介质(例如，DVD(Digital Versatile Disk，数字通用盘))、或者半导体介质(例如固态硬盘(solid state drives，SSD))等。
需要说明的是，上述信号处理装置的有益效果和上述一些实施例所述的信号处理方法的有益效果相同，此处不再赘述。
本公开的一些实施例提供了一种计算机可读存储介质(例如，非暂态计算机可读存储介质)，该计算机可读存储介质中存储有计算机程序指令，计算机程序指令在处理器上运行时，使得处理器执行如上述实施例中任一实施例所述的信号处理方法，例如信号处理方法中的一个或多个步骤。
示例性的，上述计算机可读存储介质可以包括，但不限于：磁存储器件 (例如，硬盘、软盘或磁带等)，光盘(例如，CD(Compact Disk，压缩盘)、DVD等)，智能卡和闪存器件(例如，EPROM(Erasable Programmable Read-Only Memory，可擦写可编程只读存储器)、卡、棒或钥匙驱动器等)。本公开描述的各种计算机可读存储介质可代表用于存储信息的一个或多个设备和/或其它机器可读存储介质。术语“机器可读存储介质”可包括但不限于，无线信道和能够存储、包含和/或承载指令和/或数据的各种其它介质。
本公开的一些实施例还提供了一种计算机程序产品。该计算机程序产品包括计算机程序指令，在计算机上执行该计算机程序指令时，该计算机程序指令使计算机执行如上述实施例所述的信号处理方法，例如信号处理方法中的一个或多个步骤。
本公开的一些实施例还提供了一种计算机程序。当该计算机程序在计算机上执行时，该计算机程序使计算机执行如上述实施例所述的信号处理方法，例如信号处理方法中的一个或多个步骤。
上述计算机可读存储介质、计算机程序产品及计算机程序的有益效果和上述一些实施例所述的信号处理方法的有益效果相同，此处不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种信号处理方法，包括：
    获得第一帧同步信号；所述第一帧同步信号包括多个第一脉冲，一个第一脉冲的后沿和所述第一脉冲的后一第一脉冲的前沿之间的时间为第一时间，所述第一时间对应第一整数个第一像素时钟信号的脉冲；
    生成同步校准信号；所述同步校准信号包括多个第二脉冲，每个第二脉冲的触发沿与一个所述第一脉冲的后沿处于同一时刻；所述第二脉冲的触发沿为所述第二脉冲的前沿或后沿，所述第二脉冲的宽度与第一像素时钟信号的脉冲宽度或第二像素时钟信号的脉冲宽度相等；
    生成第二帧同步信号；所述第二帧同步信号包括多个第三脉冲；其中，每个第二脉冲的触发沿与所述第二脉冲之后最靠近的一个所述第三脉冲的前沿之间的时间为第二时间，所述第二时间对应所述第一整数个所述第二像素时钟信号的脉冲。
  2. 根据权利要求1所述的信号处理方法，其中，所述生成第二帧同步信号包括：
    统计所述第二像素时钟信号的脉冲个数；
    在所述第二像素时钟信号的脉冲个数达到所述第一整数的情况下，生成所述第二帧同步信号中的第三脉冲的前沿；
    在所述第二像素时钟信号的脉冲个数未达到第二整数的情况下，响应于所述第二脉冲的触发沿，生成所述第二帧同步信号中的所述第三脉冲的后沿，并返回执行所述统计所述第二像素时钟信号的脉冲个数；
    或者，
    响应于所述第二像素时钟信号的脉冲个数达到第二整数，生成所述第二帧同步信号中的所述第三脉冲的后沿，并返回执行所述统计所述第二像素时钟信号的脉冲个数；以及响应于所述第二脉冲的触发沿，返回执行所述统计所述第二像素时钟信号的脉冲个数。
  3. 根据权利要求1或2所述的信号处理方法，其中，所述生成同步校准信号，包括：
    获得第一信号，所述第一信号和所述第一帧同步信号互为反转信号；
    获得第二信号，所述第二信号相比于所述第一帧同步信号延迟所述第一像素时钟信号或所述第二像素时钟信号的一个脉冲宽度；
    根据所述第一信号和所述第二信号，得到所述同步校准信号。
  4. 根据权利要求3所述的信号处理方法，其中，所述根据所述第一信号 和所述第二信号，得到所述同步校准信号，包括：
    将所述第一信号和所述第二信号进行逻辑运算，得到所述同步校准信号。
  5. 根据权利要求3或4所述的信号处理方法，其中，所述获得第一信号，包括：
    对所述第一帧同步信号取反，得到所述第一信号。
  6. 根据权利要求1～5中任一项所述的信号处理方法，其中，所述第二像素时钟信号的频率大致等于所述第一像素时钟信号的频率；
    在所述同步校准信号中的至少一组相邻两个第二脉冲的时间段内，所述第二帧同步信号具有一个第三脉冲。
  7. 根据权利要求6所述的信号处理方法，其中，所述第三脉冲的脉冲宽度对应的所述第二像素时钟信号的脉冲个数小于或等于所述第一脉冲的脉冲宽度对应的所述第一像素时钟信号的脉冲个数。
  8. 根据权利要求1～5中任一项所述的信号处理方法，其中，所述第二像素时钟信号的频率的N倍大致等于所述第一像素时钟信号的频率；N为大于1的整数；
    在所述同步校准信号中的至少一组相邻两个第二脉冲的时间段内，所述第二帧同步信号具有N个第三脉冲。
  9. 根据权利要求8所述的信号处理方法，其中，N为2；
    在所述同步校准信号中的至少一组相邻两个第二脉冲的时间段内，所述第二帧同步信号具有两个第三脉冲；所述两个第三脉冲中的前一第三脉冲的脉冲宽度对应的所述第二像素时钟信号的脉冲个数等于所述第一脉冲的脉冲宽度对应的所述第一像素时钟信号的脉冲个数；
    所述两个第三脉冲中的后一第三脉冲的脉冲宽度对应的所述第二像素时钟信号的脉冲个数小于或等于所述第一脉冲的脉冲宽度对应的所述第一像素时钟信号的脉冲个数。
  10. 根据权利要求1～9中任一项所述的信号处理方法，其中，所述获得第一帧同步信号包括：
    获得第一视频信号，所述第一视频信号包括所述第一帧同步信号和视频数据；
    所述信号处理方法还包括：
    将所述视频数据写入存储装置；
    根据所述第二帧同步信号，从所述存储装置中读取所述视频数据，得到第二视频信号；所述第二视频信号包括所述第二帧同步信号和所述视频数据。
  11. 根据权利要求10所述的信号处理方法，还包括：
    输出所述第二视频信号。
  12. 根据权利要求10或11所述的信号处理方法，还包括：
    检测得到所述第一视频信号的第一帧率；
    获得显示模组的第二帧率的范围；
    在所述第一帧率的N倍位于所述第二帧率的范围内的情况下，在所述同步校准信号中的至少一组相邻两个第二脉冲的时间段内，所述第二帧同步信号具有N个第三脉冲；N为大于1的整数；
    在所述第一帧率位于所述第二帧率的范围内的情况下，在所述同步校准信号中的至少一组相邻两个第二脉冲的时间段内，所述第二帧同步信号具有一个第三脉冲。
  13. 一种信号处理装置，包括：
    信号输入单元，被配置为获得第一帧同步信号；所述第一帧同步信号包括多个第一脉冲，一个第一脉冲的后沿和所述第一脉冲的后一第一脉冲的前沿之间的时间为第一时间，所述第一时间对应第一整数个第一像素时钟信号的脉冲；
    第一信号处理单元，被配置为生成同步校准信号；其中，所述同步校准信号包括多个第二脉冲，每个第二脉冲的触发沿与一个所述第一脉冲的后沿处于同一时刻；所述第二脉冲的触发沿为所述第二脉冲的前沿或后沿，所述第二脉冲的宽度与第一像素时钟信号的脉冲宽度或第二像素时钟信号的脉冲宽度相等；
    第二信号处理单元，被配置为生成第二帧同步信号；所述第二帧同步信号包括多个第三脉冲；每个第二脉冲的触发沿与所述第二脉冲之后最靠近的一个所述第三脉冲的前沿之间的时间为第二时间，所述第二时间对应所述第一整数个所述第二像素时钟信号的脉冲。
  14. 根据权利要求13所述的信号处理装置，其中，
    所述信号输入单元被配置为获得第一视频信号，所述第一视频信号包括所述第一帧同步信号和视频数据；
    所述信号处理装置还包括：
    数据写入单元，被配置为将所述第一视频信号中的视频数据写入存储装置；
    数据读取单元，被配置为根据所述第二帧同步信号，读取所述存储装置中的所述视频数据；
    信号输出单元，被配置为输出包括所述第二帧同步信号和所述视频数据的第二视频信号。
  15. 一种信号处理装置，包括：
    存储器；所述存储器中存储一个或多个计算机程序；
    处理器；所述处理器与所述存储器耦接；所述处理器被配置为执行所述计算机程序，以使得所述处理器实现如权利要求1～12中任一项所述的信号处理方法。
  16. 一种信号处理装置，其中，所述信号处理装置为芯片；所述芯片被配置为实现如权利要求1～12中任一项所述的信号处理方法。
  17. 一种显示装置，包括：
    显示模组；和
    如权利要求13～16中任一项所述的信号处理装置；
    所述信号处理装置与所述显示模组耦接；所述信号处理装置被配置为将第二视频信号输出至所述显示模组。
  18. 根据权利要求17所述的显示装置，还包括：
    存储装置，与所述信号处理装置耦接；
    所述存储装置被配置为存储第一视频信号中的视频数据。
  19. 一种计算机可读存储介质，其存储有计算机程序，其中，所述计算机程序在计算机运行时，使得处理器实现如权利要求1～12中任一项所述的信号处理方法。
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WO2020061785A1 (zh) * 2018-09-26 2020-04-02 西安诺瓦电子科技有限公司 视频帧同步系统、视频处理设备和视频帧同步方法

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