WO2022133873A1 - Mécanisme configurable insensible aux défaillances - Google Patents

Mécanisme configurable insensible aux défaillances Download PDF

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Publication number
WO2022133873A1
WO2022133873A1 PCT/CN2020/138892 CN2020138892W WO2022133873A1 WO 2022133873 A1 WO2022133873 A1 WO 2022133873A1 CN 2020138892 W CN2020138892 W CN 2020138892W WO 2022133873 A1 WO2022133873 A1 WO 2022133873A1
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WO
WIPO (PCT)
Prior art keywords
region
update
boot
backup
primary
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PCT/CN2020/138892
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English (en)
Inventor
Kenji Chen
Kevin Zhenyu ZHU
Nivedita Aggarwal
Chao Zhang
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Intel Corporation
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Priority to PCT/CN2020/138892 priority Critical patent/WO2022133873A1/fr
Priority to TW110135650A priority patent/TW202225961A/zh
Publication of WO2022133873A1 publication Critical patent/WO2022133873A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/60—Software deployment
    • G06F8/65—Updates
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping

Definitions

  • a system on chip is an integrated circuit that integrates all components of a computer or other electronic system. These components include a central processing unit (CPU) , memory, input/output (IO) ports and secondary storage, which are all included on a single substrate or microchip. Additionally, SOCs enable the integration of third party components via a standardized on-die interconnect protocol. However, the addition of such components may lead to security vulnerabilities.
  • Figure 1 illustrates one embodiment of a computing device.
  • Figures 2A-2C illustrate embodiments of a platform.
  • Figure 3 illustrates yet another embodiment of a platform.
  • FIGS. 4A &4B illustrate conventional firmware configurations.
  • Figure 5 illustrates one embodiment of a firmware update configuration.
  • Figure 6 is a flow diagram illustrating one embodiment of a fault tolerant update process.
  • Figure 7 illustrates one embodiment of a schematic diagram of an illustrative electronic computing device.
  • update hardware uses hardware registers to addresses associated with the primary and backup boot regions in hardware, and retrieves the addresses from the register upon determining that an update of the primary boot region has been interrupted.
  • references to "one embodiment” , “an embodiment” , “example embodiment” , “various embodiments” , etc., indicate that the embodiment (s) so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Further, some embodiments may have some, all, or none of the features described for other embodiments.
  • Coupled is used to indicate that two or more elements co-operate or interact with each other, but they may or may not have intervening physical or electrical components between them.
  • FIG. 1 illustrates one embodiment of a computing device 100.
  • computing device 100 comprises a computer platform hosting an integrated circuit ( “IC” ) , such as a system on a chip ( “SoC” or “SOC” ) , integrating various hardware and/or software components of computing device 100 on a single chip.
  • IC integrated circuit
  • SoC system on a chip
  • SOC system on a chip
  • computing device 100 may include any number and type of hardware and/or software components, such as (without limitation) graphics processing unit 114 ( “GPU” or simply “graphics processor” ) , graphics driver116 (also referred to as “GPU driver” , “graphics driver logic” , “driver logic” , user-mode driver (UMD) , UMD, user-mode driver framework (UMDF) , UMDF, or simply “driver” ) , central processing unit 112 ( “CPU” or simply “application processor” ) , memory 108, network devices, drivers, or the like, as well as input/output (I/O) sources 104, such as touchscreens, touch panels, touch pads, virtual or regular keyboards, virtual or regular mice, ports, connectors, etc.
  • Computing device 100 may include operating system (OS) 106 serving as an interface between hardware and/or physical resources of computing device 100 and a user.
  • OS operating system
  • computing device 100 may vary from implementation to implementation depending upon numerous factors, such as price constraints, performance requirements, technological improvements, or other circumstances.
  • Embodiments may be implemented as any or a combination of: one or more microchips or integrated circuits interconnected using a parentboard, hardwired logic, software stored by a memory device and executed by a microprocessor, firmware, an application specific integrated circuit (ASIC) , and/or a field programmable gate array (FPGA) .
  • the terms "logic” , “module” , “component” , “engine” , and “mechanism” may include, by way of example, software or hardware and/or a combination thereof, such as firmware.
  • Embodiments may be implemented using one or more memory chips, controllers, CPUs (Central Processing Unit) , microchips or integrated circuits interconnected using a motherboard, an application specific integrated circuit (ASIC) , and/or a field programmable gate array (FPGA) .
  • the term "logic” may include, by way of example, software or hardware and/or combinations of software and hardware.
  • FIGS 2A –2C illustrate embodiments of a platform 200 including a SOC 210 similar to computing device 100 discussed above.
  • platform 200 includes SOC 210 communicatively coupled to one or more software components 280 via CPU 112.
  • SOC 210 includes other computing device components (e.g., memory 108) coupled via a system fabric 205.
  • system fabric 205 comprises an integrated on-chip system fabric (IOSF) to provide a standardized on-die interconnect protocol for coupling interconnect protocol (IP) agents 230 (e.g., IP agents 230A and 230B) within SOC 210.
  • IP interconnect protocol
  • the interconnect protocol provides a standardized interface to enable third parties to design logic such as IP agents to be incorporated in SOC 210.
  • IP agents 230 may include general purpose processors (e.g., in-order or out-of-order cores) , fixed function units, graphics processors, I/O controllers, display controllers, etc.
  • each IP agent 230 includes a hardware interface 235 (e.g., interfaces 235A and 235B) to provide standardization to enable the IP agent 230 to communicate with SOC 210 components.
  • interface 235 provides a standardization to enable the VPU to access memory 108 via fabric 205.
  • SOC 210 also includes a security controller 240 that operates as a security engine to perform various security operations (e.g., security processing, cryptographic functions, etc. ) for SOC 210.
  • security controller 240 comprises an IP agent 230 that is implemented to perform the security operations.
  • SOC 210 includes a non-volatile memory 250.
  • Non-volatile memory 250 may be implemented as a Peripheral Component Interconnect Express (PCIe) storage drive, such as a solid state drives (SSD) or Non-Volatile Memory Express (NVMe) drives.
  • PCIe Peripheral Component Interconnect Express
  • SSD solid state drives
  • NVMe Non-Volatile Memory Express
  • non-volatile memory 250 is implemented to store the platform 200 firmware.
  • non-volatile memory 250 stores boot (e.g., Basic Input/Output System (BIOS) ) and device (e.g., IP agent 230 and security controller 240) firmware.
  • BIOS Basic Input/Output System
  • FIG. 2B illustrates another embodiment of platform 200 including a component 260 coupled to SOC 210 via IP agent 230A.
  • IP agent 230A operates as a bridge, such as a PCIe root port, that connects component 260 to SOC 210.
  • component 260 may be implemented as a PCIe device (e.g., switch or endpoint) that includes a hardware interface 235 to enable component 260 to communicate with SOC 210 components.
  • FIG 2C illustrates yet another embodiment of platform 200 including a computing device 270 coupled to platform 200 via a cloud network 201.
  • computing device 270 comprises a cloud agent that is provided access to SOC 210 via software 280.
  • FIG. 3 illustrates still another embodiment of platform 200 including non-volatile memory 250 coupled to SOC 210 via a serial peripheral interface (SPI) 301.
  • non-volatile memory 250 is implemented as a storage for platform firmware 310.
  • resiliency support is provided for firmware stored in non-volatile memory 250.
  • SPI controller 340 is also coupled to system fabric 205.
  • SPI controller 340 is a flash controller implemented to control access to non-volatile memory 250 via SPI 301.
  • SPI controller 340 facilitates the updating of firmware 310.
  • Firmware such as firmware 310 typically needs to be updated regularly to provide functionality maintenance and vulnerability fixes. Modern infrastructures regularly push firmware updates on systems, such as platform 200. However, end user implementation of these updates is often low since update failures may result in platform malfunctions that can only be restored be by shipping the system to be repaired.
  • Current systems may implement fault tolerant update mechanisms that allow archiving a redundant (or backup copy) of a boot block included in the firmware prior to initiating an update on a primary firmware copy.
  • the fault tolerant update mechanism enables a reset vector address to be automatically switched to the redundant copy of the boot block instead of the faulty primary firmware copy pointed to by the reset vector.
  • FIG. 4A illustrates a firmware configuration 2 n size fault tolerant region. As shown in Figure 4A, the fault tolerant region is a minimum of 1 MB that has to be updated, even when there is an attempt to update only a portion of the main firmware.
  • Figure 4B illustrates another firmware configuration.
  • the fault tolerant region is fixed to the entire boot block size (size of 2 n ) to allow the fault tolerant update mechanism to switch to a different reset vector. Again, the entire fault tolerant region needs to be archived, even though the microcode firmware occupies a very small portion of the fault area.
  • SPI controller 340 includes an update agent 342 to configure a backup region (or block) of firmware 310 with a fault tolerant copy upon determining that there is a firmware update pending during a system start (or boot) .
  • update agent 342 may feature update agent 342 being incorporated in other components (e.g., CPU 112) of platform 200 hardware.
  • platform 200 includes fault tolerant hardware registers that are configured by update agent 342 to store an address of a primary boot region in firmware 310 being updated, as well as an address of the fault tolerant copy prior to beginning a firmware 310 update.
  • CPU 112 includes registers 380.
  • registers 380 include source base, patched size and target base registers to implement boot region updating (or patching) .
  • a source base register provides the base address of the boot (or primary patch) region being patched
  • a patched size register provides the size of the region being patched
  • a target base register provides the base address of the boot region being directed from the source (e.g., backup patch) region.
  • update agent 342 begins an update process by updating a primary patch region of firmware 310. However, upon a determination that the update has been interrupted (e.g., via power failure interrupt or reboot) , CPU 112 remaps the address space associated with the primary patch region to the address space associated with the backup patch region. In one embodiment, update agent 342 recovers the boot code from regular reset vector and ensures that the original boot region is restored with the recovery copy. In such an embodiment, update agent 342 accesses registers 380 to retrieve the addresses associated with the primary and backup patch regions and use the address associated with the backup patch region to access the backup boot code of and restore the primary patch region with the contents the backup boot code at the address associated with the primary patch region. Subsequently, update agent 342 restarts the process of updating the primary patch region of firmware 310.
  • Figure 5 illustrates one embodiment of a modular fault tolerant firmware update configuration.
  • the microcode component within the firmware region is updated, while the other components (e.g., the initial boot block and crypto service) are not updated.
  • the microcode region Prior to the update, the microcode region is backed up in a different location in firmware 310.
  • the base of the region to be updated, its size and location of the backup microcode region in firmware 310 is updated registers 380, as described above. Subsequently, the update may begin.
  • FIG. 6 is a flow diagram illustrating one embodiment of a fault tolerant update process.
  • a request to update a primary patch region is received.
  • fault tolerant patch regions are generated using registers 380 (e.g., source and destination registers) .
  • the update begins.
  • an interrupt of the update is detected.
  • the platform is rebooted.
  • the fault tolerant registers are accessed to retrieve the addresses associated with the primary and backup patch regions.
  • the retrieved addresses are used to restore the primary patch region with the content of the backup patch region.
  • the firmware patch update is restarted.
  • the above-described mechanism provides flexibility to select a fault tolerance patched vector and download modular updates smaller than a full boot block.
  • Figure 7 is a schematic diagram of an illustrative electronic computing device to enable enhanced protection against adversarial attacks according to some embodiments.
  • the computing device 700 includes one or more processors 710 including one or more processors cores 718 and a TEE 764, the TEE including a machine learning service enclave (MLSE) 780.
  • the computing device 700 includes a hardware accelerator 768, the hardware accelerator including a cryptographic engine 782 and a machine learning model 784.
  • the computing device is to provide enhanced protections against ML adversarial attacks, as provided in Figures 1-6.
  • the computing device 700 may additionally include one or more of the following: cache 762, a graphical processing unit (GPU) 712 (which may be the hardware accelerator in some implementations) , a wireless input/output (I/O) interface 720, a wired I/O interface 730, memory circuitry 740, power management circuitry 750, non-transitory storage device 760, and a network interface 770 for connection to a network 772.
  • a graphical processing unit (GPU) 712 which may be the hardware accelerator in some implementations
  • I/O input/output
  • wired I/O interface 730 for connection to a network 772.
  • the processor cores 718 are capable of executing machine-readable instruction sets 714, reading data and/or instruction sets 714 from one or more storage devices 760 and writing data to the one or more storage devices 760.
  • processors including portable electronic or handheld electronic devices, for instance smartphones, portable computers, wearable computers, consumer electronics, personal computers (“PCs” ) , network PCs, minicomputers, server blades, mainframe computers, and the like.
  • the processor cores 718 may include any number of hardwired or configurable circuits, some or all of which may include programmable and/or configurable combinations of electronic components, semiconductor devices, and/or logic elements that are disposed partially or wholly in a PC, server, or other computing system capable of executing processor-readable instructions.
  • the computing device 700 includes a bus or similar communications link 716 that communicably couples and facilitates the exchange of information and/or data between various system components including the processor cores 718, the cache 762, the graphics processor circuitry 712, one or more wireless I/O interfaces 720, one or more wired I/O interfaces 730, one or more storage devices 760, and/or one or more network interfaces 770.
  • the computing device 700 may be referred to in the singular herein, but this is not intended to limit the embodiments to a single computing device 700, since in certain embodiments, there may be more than one computing device 700 that incorporates, includes, or contains any number of communicably coupled, collocated, or remote networked circuits or devices.
  • the processor cores 718 may include any number, type, or combination of currently available or future developed devices capable of executing machine-readable instruction sets.
  • the processor cores 718 may include (or be coupled to) but are not limited to any current or future developed single-or multi-core processor or microprocessor, such as: on or more systems on a chip (SOCs) ; central processing units (CPUs) ; digital signal processors (DSPs) ; graphics processing units (GPUs) ; application-specific integrated circuits (ASICs) , programmable logic units, field programmable gate arrays (FPGAs) , and the like.
  • SOCs systems on a chip
  • CPUs central processing units
  • DSPs digital signal processors
  • GPUs graphics processing units
  • ASICs application-specific integrated circuits
  • FPGAs field programmable gate arrays
  • the system memory 740 may include read-only memory ( “ROM” ) 742 and random access memory ( “RAM” ) 746.
  • ROM read-only memory
  • RAM random access memory
  • a portion of the ROM 742 may be used to store or otherwise retain a basic input/output system ( “BIOS” ) 744.
  • BIOS basic input/output system
  • the BIOS 744 provides basic functionality to the computing device 700, for example by causing the processor cores 718 to load and/or execute one or more machine-readable instruction sets 714.
  • At least some of the one or more machine-readable instruction sets 714 cause at least a portion of the processor cores 718 to provide, create, produce, transition, and/or function as a dedicated, specific, and particular machine, for example a word processing machine, a digital image acquisition machine, a media playing machine, a gaming system, a communications device, a smartphone, or similar.
  • the computing device 700 may include at least one wireless input/output (I/O) interface 720.
  • the at least one wireless I/O interface 720 may be communicably coupled to one or more physical output devices 722 (tactile devices, video displays, audio output devices, hardcopy output devices, etc. ) .
  • the at least one wireless I/O interface 720 may communicably couple to one or more physical input devices 724 (pointing devices, touchscreens, keyboards, tactile devices, etc. ) .
  • the at least one wireless I/O interface 720 may include any currently available or future developed wireless I/O interface.
  • Example wireless I/O interfaces include, but are not limited to: near field communication (NFC) , and similar.
  • NFC near field communication
  • the computing device 700 may include one or more wired input/output (I/O) interfaces 730.
  • the at least one wired I/O interface 730 may be communicably coupled to one or more physical output devices 722 (tactile devices, video displays, audio output devices, hardcopy output devices, etc. ) .
  • the at least one wired I/O interface 730 may be communicably coupled to one or more physical input devices 724 (pointing devices, touchscreens, keyboards, tactile devices, etc. ) .
  • the wired I/O interface 730 may include any currently available or future developed I/O interface.
  • Example wired I/O interfaces include, but are not limited to: universal serial bus (USB) , IEEE 1394(“FireWire” ) , and similar.
  • the computing device 700 may include one or more communicably coupled, non-transitory, data storage devices 760.
  • the data storage devices 760 may include one or more hard disk drives (HDDs) and/or one or more solid-state storage devices (SSDs) .
  • the one or more data storage devices 760 may include any current or future developed storage appliances, network storage devices, and/or systems. Non- limiting examples of such data storage devices 760 may include, but are not limited to, any current or future developed non-transitory storage appliances or devices, such as one or more magnetic storage devices, one or more optical storage devices, one or more electro-resistive storage devices, one or more molecular storage devices, one or more quantum storage devices, or various combinations thereof.
  • the one or more data storage devices 760 may include one or more removable storage devices, such as one or more flash drives, flash memories, flash storage units, or similar appliances or devices capable of communicable coupling to and decoupling from the computing device 700.
  • the one or more data storage devices 760 may include interfaces or controllers (not shown) communicatively coupling the respective storage device or system to the bus 716.
  • the one or more data storage devices 760 may store, retain, or otherwise contain machine-readable instruction sets, data structures, program modules, data stores, databases, logical structures, and/or other data useful to the processor cores 718 and/or graphics processor circuitry 712 and/or one or more applications executed on or by the processor cores 718 and/or graphics processor circuitry 712.
  • one or more data storage devices 760 may be communicably coupled to the processor cores 718, for example via the bus 716 or via one or more wired communications interfaces 730 (e.g., Universal Serial Bus or USB) ; one or more wireless communications interfaces 720 (e.g., Near Field Communication or NFC) ; and/or one or more network interfaces 770 (IEEE 802.3 or Ethernet, IEEE 802.11, or etc. ) .
  • wired communications interfaces 730 e.g., Universal Serial Bus or USB
  • wireless communications interfaces 720 e.g., Near Field Communication or NFC
  • network interfaces 770 IEEE 802.3 or Ethernet, IEEE 802.11, or etc.
  • Processor-readable instruction sets 714 and other programs, applications, logic sets, and/or modules may be stored in whole or in part in the system memory 740. Such instruction sets 714 may be transferred, in whole or in part, from the one or more data storage devices 760. The instruction sets 714 may be loaded, stored, or otherwise retained in system memory 740, in whole or in part, during execution by the processor cores 718 and/or graphics processor circuitry 712.
  • the computing device 700 may include power management circuitry 750 that controls one or more operational aspects of the energy storage device 752.
  • the energy storage device 752 may include one or more primary (i.e., non-rechargeable) or secondary (i.e., rechargeable) batteries or similar energy storage devices.
  • the energy storage device 752 may include one or more supercapacitors or ultracapacitors.
  • the power management circuitry 750 may alter, adjust, or control the flow of energy from an external power source 754 to the energy storage device 752 and/or to the computing device 700.
  • the power source 754 may include, but is not limited to, a solar power system, a commercial electric grid, a portable generator, an external energy storage device, or any combination thereof.
  • the processor cores 718, the graphics processor circuitry 712, the wireless I/O interface 720, the wired I/O interface 730, the storage device 760, and the network interface 770 are illustrated as communicatively coupled to each other via the bus 716, thereby providing connectivity between the above-described components.
  • the above-described components may be communicatively coupled in a different manner than illustrated in Figure 7.
  • one or more of the above-described components may be directly coupled to other components, or may be coupled to each other, via one or more intermediary components (not shown) .
  • one or more of the above-described components may be integrated into the processor cores 718 and/or the graphics processor circuitry 712.
  • all or a portion of the bus 716 may be omitted and the components are coupled directly to each other using suitable wired or wireless connections.
  • Embodiments may be provided, for example, as a computer program product which may include one or more transitory or non-transitory machine-readable storage media having stored thereon machine-executable instructions that, when executed by one or more machines such as a computer, network of computers, or other electronic devices, may result in the one or more machines carrying out operations in accordance with embodiments described herein.
  • a machine-readable medium may include, but is not limited to, floppy diskettes, optical disks, CD-ROMs (Compact Disc-Read Only Memories) , and magneto-optical disks, ROMs, RAMs, EPROMs (Erasable Programmable Read Only Memories) , EEPROMs (Electrically Erasable Programmable Read Only Memories) , magnetic or optical cards, flash memory, or other type of media/machine-readable medium suitable for storing machine-executable instructions.
  • Example 1 includes an apparatus to facilitate firmware fault tolerance in a computer system platform, comprising a non-volatile memory to store firmware for a computer system platform, wherein the firmware comprises a primary boot region including boot code and a backup boot region including a backup copy of the boot code, a plurality of registers to store addresses associated with the primary boot region and the backup boot region and update hardware to perform an update of the primary boot region and access the registers to perform a platform boot upon determining that the update has been interrupted.
  • the firmware comprises a primary boot region including boot code and a backup boot region including a backup copy of the boot code, a plurality of registers to store addresses associated with the primary boot region and the backup boot region and update hardware to perform an update of the primary boot region and access the registers to perform a platform boot upon determining that the update has been interrupted.
  • Example 2 includes the subject matter of Example 1, wherein the update hardware retrieves addresses associated with the primary and backup regions from the registers upon determining that the update has been interrupted.
  • Example 3 includes the subject matter of Examples 1 and 2, further comprising a processor to remap the address associated with the primary region to the address associated with the backup region.
  • Example 4 includes the subject matter of Examples 1-3, wherein the update hardware accesses the address associated with the backup region to retrieve the backup copy of the boot code.
  • Example 5 includes the subject matter of Examples 1-4, wherein the update hardware restores the primary boot region with the backup boot code at the address associated with the primary boot region.
  • Example 6 includes the subject matter of Examples 1-5, wherein the registers comprise a source base register to provide a base address of the primary boot region and a target base register to provide a base address of the backup boot region.
  • Example 7 includes the subject matter of Examples 1-6, wherein the update hardware stores the base address of the primary boot region and the base address of the backup boot region in the registers prior to beginning the update.
  • Example 8 includes the subject matter of Examples 1-7, wherein the registers further comprise a patched size register a provide a size of a component with the primary boot region that is being updated.
  • Example 9 includes the subject matter of Examples 1-8, wherein the size of the component is less than the primary boot region.
  • Example 10 includes the subject matter of Examples 1-9, wherein the update hardware restarts the update after the primary boot region has been restored.
  • Example 11 includes a method to facilitate firmware fault tolerance in a computer system platform, comprising performing an update of a primary boot region within non-volatile memory firmware, determining that the update has been interrupted and accessing registers in within the platform to perform a platform boot upon determining that the update has been interrupted.
  • Example 12 includes the subject matter of Example 11, wherein accessing the registers comprises retrieving addresses associated with the primary boot region and a backup region from the registers upon determining that the update has been interrupted and accessing the address associated with the backup region retrieve the address associated with the backup region to retrieve the backup copy of the boot code.
  • Example 13 includes the subject matter of Examples 11 and 12, further comprising remapping the address associated with the primary region to the address associated with the backup region.
  • Example 14 includes the subject matter of Examples 11-13, further comprising restoring the primary boot region with the backup boot code at the address associated with the primary boot region.
  • Example 15 includes the subject matter of Examples 11-14, further comprising storing the base address of the primary boot region and the base address of the backup boot region in the registers prior to beginning the update.
  • Example 16 includes the subject matter of Examples 11-15, further comprising restarting the update after the primary boot region has been restored.
  • Example 17 includes at least one computer readable medium having instructions stored thereon, which when executed by one or more processors, cause the processors to perform an update of a primary boot region within non-volatile memory firmware, determine that the update has been interrupted and access registers in within the platform to perform a platform boot upon determining that the update has been interrupted.
  • Example 18 includes the subject matter of Example 17, wherein accessing the registers retrieving addresses associated with the primary boot region and a backup region from the registers upon determining that the update has been interrupted and accessing the address associated with the backup region retrieve the address associated with the backup region to retrieve the backup copy of the boot code.
  • Example 19 includes the subject matter of Examples 17 and 18, having instructions stored thereon, which when executed by one or more processors, further cause the processors to remap the address associated with the primary region to the address associated with the backup region.
  • Example 20 includes the subject matter of Examples 17-19, having instructions stored thereon, which when executed by one or more processors, further cause the processors to restore the primary boot region with the backup boot code at the address associated with the primary boot region.
  • Example 21 includes the subject matter of Examples 17-20, having instructions stored thereon, which when executed by one or more processors, further cause the processors to storing the base address of the primary boot region and the base address of the backup boot region in the registers prior to beginning the update.

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Abstract

L'invention concerne un appareil destiné à faciliter la tolérance aux défaillances de micrologiciel dans une plateforme de système informatique. L'appareil comprend une mémoire non volatile destinée à stocker un micrologiciel pour une plateforme de système informatique, le micrologiciel comprenant une région d'amorçage primaire comprenant du code d'amorçage, et une région d'amorçage de sauvegarde comprenant une copie de sauvegarde du code d'amorçage, une pluralité de registres destinés à stocker des adresses associées à la région d'amorçage primaire et à la région d'amorçage de sauvegarde et du matériel de mise à jour destiné à réaliser une mise à jour de la région d'amorçage primaire et à accéder aux registres pour effectuer un amorçage de plateforme lors de la détermination que la mise à jour a été interrompue.
PCT/CN2020/138892 2020-12-24 2020-12-24 Mécanisme configurable insensible aux défaillances WO2022133873A1 (fr)

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