WO2022126584A1

WO2022126584A1 - Link reestablishment method and device

Info

Publication number: WO2022126584A1
Application number: PCT/CN2020/137557
Authority: WO
Inventors: 李孝严; 刘荣国
Original assignee: 华为技术有限公司
Priority date: 2020-12-18
Filing date: 2020-12-18
Publication date: 2022-06-23
Also published as: CN116569127A

Abstract

Provided are a link reestablishment method and device, which can solve the problem of the time required for link reestablishment being relatively long when a data link is abnormal and a data read/write failure occurs, and can avoid data read/write lagging. The link reestablishment method comprises: when the adjustment of a first data transmission link between a master chip and a flash memory fails, the master chip receiving a second level signal, the duration of which is longer than that of a first level signal, from the flash memory, wherein the second level signal is used for indicating that the first data transmission link is abnormal; and the master chip immediately sending a link establishment command to the flash memory after receiving the second level signal so as to establish a second data transmission link.

Description

Link re-establishment method and device

technical field

The present application relates to the field of data reading and writing, and in particular, to a link reconstruction method and device.

Background technique

The electronic device may include a main chip and flash memory. The main chip can

) data read and write commands, initiate data read and write operations to the flash memory, for example, the read and write operations can be completed through the data transmission link between the main chip and the flash memory. However, environmental factors such as high temperature and high voltage of the main chip or flash memory may cause abnormal data transmission links, resulting in failure of read and write operations. Therefore, when the data transmission link is abnormal, it is necessary to restore the data transmission link as soon as possible to ensure normal read and write operations.

At present, the main chip can adjust the working parameters of the data transmission link between the main chip and the flash memory according to the level signal from the flash memory. If the data transmission link is still abnormal, the main chip can also rebuild the data transmission link. Specifically, the main chip sends a read and write request to the flash memory. If the main chip does not receive a read and write response from the flash memory within a long period of time (eg, 3 seconds, 5 seconds), the main chip can execute the data transmission chain. Road reconstruction process. However, since the rebuilding process of the data transmission link takes a long time, data read/write freezes, resulting in poor user experience.

SUMMARY OF THE INVENTION

The embodiments of the present application provide a link reconstruction method and device, which can solve the problem that when data read/write fails, the main chip takes a long time to send a data read/write request to rebuild the link, and avoid data read/write Caton, improve user experience.

To achieve the above object, the application adopts the following technical solutions:

In a first aspect, the present application provides a link reconstruction method, which is applied to a flash memory of an electronic device, and the electronic device further includes a main chip. The method includes: when the flash memory detects that the first data transmission link is in an abnormal state, the flash memory adjusts the first parameter. The first parameter is a working parameter for the flash memory to transmit data on the first data transmission link, and the first data transmission link is a communication link between the flash memory and the main chip. The flash memory sends a first level signal to the main chip, where the first level signal is used to request the main chip to restore the first data transmission link. If the flash memory detects that the recovery of the first data transmission link fails, it sends a second level signal to the main chip. Wherein, the duration of the second level signal is greater than the duration of the first level signal. The flash receives the link building command from the main chip. The flash memory establishes a second data transmission link according to the link establishment command.

Based on the link reconstruction method provided in the first aspect, in the case that the adjustment of the first data transmission link between the main chip and the flash memory fails, the main chip receives the second power from the flash memory that is longer than the duration of the first level signal. The second level signal is used to indicate that the first data transmission link is abnormal. After the main chip receives the second level signal, it immediately sends a link building command to the flash memory to establish a second data transmission link without waiting for a longer time, which can greatly reduce the cost of rebuilding the link when the data link is abnormal. time to avoid data read/write freezes, thereby improving user experience. In addition, the second level signal of the flash memory requesting the main chip 101 to rebuild the second data transmission link is a stable signal (without jumping), and even if the first data transmission link is abnormal, the main chip can accurately detect the second level signal. Flat signal, high reliability.

In a possible design solution, the difference between the duration of the second level signal and the duration of the first level signal may be greater than or equal to the first threshold. Since the difference between the duration of the second-level signal and the duration of the first-level signal is greater than or equal to the first threshold, the main chip can accurately distinguish the first-level signal and the second-level signal, so that the subsequent The first data transmission link is restored according to the first level signal, and the second data transmission link is re-established according to the second level signal.

Further, the duration of the second level signal may be greater than or equal to the second threshold. Wherein, the second threshold is greater than the duration of the first level signal, so as to distinguish the first level signal and the second level signal.

In a possible design solution, before the flash memory adjusts the first parameter, the method described in the first aspect may further include: when the first data transmission link is in a normal state, the flash memory sends the second level to the main chip. The duration of the signal is the same as the duration of the first level signal. Therefore, when the main chip subsequently detects the level signal, it can compare the duration of the detected level signal with the first threshold and the second threshold, so as to determine whether the detected level signal is the first level signal or the second level signal. level signal, so that the first data transmission link can be subsequently restored according to the first level signal, and the second data transmission link can be re-established according to the second level signal.

Further, before the flash memory sends the duration of the second level signal and the duration of the first level signal to the host chip, the method of the first aspect may further include: the flash memory receives a data read request from the host chip.

In a possible design solution, the flash memory sends the first level signal and the second high level signal based on the same differential line. The differential line may be a signal line connecting the flash memory and the main chip. Since the first-level signal and the second high-level signal are transmitted based on the same differential line, no additional hardware design is required to save costs.

In a second aspect, the present application further provides another link reconstruction method, which is applied to a main chip of an electronic device, and the electronic device further includes a flash memory. The method includes: the main chip receives a first level signal output by the flash memory, where the first level signal is used to request the main chip to restore the first data transmission link. The main chip restores the first data transmission link in an abnormal state, wherein the first data transmission link is a communication link between the flash memory and the main chip. If the recovery of the first data transmission link fails, the main chip receives the second high-level signal transmitted by the flash memory. Wherein, the duration of the second high-level signal is greater than the set threshold, and the set threshold is greater than or equal to the duration of the first-level signal. A second data transmission link is established according to the second level signal. Wherein, establishing the second data transmission link includes sending a link establishment command to the flash memory.

In a possible design solution, the difference between the duration of the second level signal and the duration of the first level signal is greater than or equal to the first threshold.

Further, the duration of the second level signal is greater than or equal to the second threshold. Wherein, the second threshold is greater than the duration of the first level signal.

In a possible design solution, before the main chip receives the first level signal output by the flash memory, the method provided in the second aspect may further include: when the first data transmission link is in a normal state, the main chip receives the flash memory The duration of the sent second level signal is the same as the duration of the first level signal.

Further, before the main chip receives the duration of the second level signal and the duration of the first level signal sent by the flash memory, the method provided in the second aspect may further include: the main chip sends a data read request to the flash memory.

In a possible design solution, the main chip receives the first level signal and the second high level signal based on the same differential line. The differential line is a signal line connecting the flash memory and the main chip.

In a third aspect, the present application further provides a link reconstruction apparatus, which is applied to a flash memory of an electronic device, and the electronic device further includes a main chip. The device includes a processing unit and a transceiver unit. The processing unit is configured to adjust the first parameter when detecting that the first data transmission link is in an abnormal state. The first parameter is a working parameter for the flash memory to transmit data on the first data transmission link, and the first data transmission link is a communication link between the flash memory and the main chip. The transceiver unit is used for sending a first level signal to the main chip, and the first level signal is used for requesting the main chip to restore the first data transmission link. The processing unit is further configured to control the sending unit to send a second level signal to the main chip if it is detected that the recovery of the first data transmission link fails, wherein the duration of the second level signal is longer than the duration of the first level signal duration. The transceiver unit is also used to receive a link establishment command from the main chip. The processing unit is further configured to establish a second data transmission link according to the link establishment command.

In a possible design solution, the duration of the second level signal is greater than or equal to the second threshold. Wherein, the second threshold is greater than the duration of the first level signal.

In a possible design solution, the transceiver unit can also be used to send the duration of the second level signal and the duration of the first level signal to the main chip when the first data transmission link is in a normal state. .

The transceiver unit can also be used to receive a data read request from the main chip.

In a possible design solution, the transceiver unit may also be used to send the first level signal and the second high level signal based on the same differential line. The differential line is a signal line connecting the flash memory and the main chip.

Optionally, the transceiver unit and the processing unit provided in the third aspect may be integrated into one module, such as a processing module, or may be independently set up respectively. For example, the transceiver unit includes a receiving module and a sending module. Wherein, the sending module is configured to implement the sending function of the link re-establishment apparatus described in the third aspect, and the receiving module is configured to execute the receiving function of the link re-establishment apparatus described in the third aspect.

Optionally, the apparatus provided in the third aspect may further include a storage module. The storage module stores programs or instructions. When the processing module executes the program or the instruction, the apparatus can execute the link reestablishment method provided by the third aspect.

It should be noted that the link reconstruction apparatus described in the third aspect may be terminal equipment or network equipment, or may be a chip (system) or other components or components that can be set in the terminal equipment or network equipment, or may include A device of a terminal device or a network device, which is not limited in this application.

In a fourth aspect, the present application further provides a link reconstruction apparatus, which is applied to a main chip of an electronic device, and the electronic device further includes a flash memory. The device includes a transceiver unit and a processing unit. The transceiver unit is used to receive the first level signal output by the flash memory, and the first level signal is used to request the main chip to restore the first data transmission link. The processing unit is configured to restore the first data transmission link in an abnormal state. The first data transmission link is a communication link between the flash memory and the main chip. The transceiver unit is further configured to receive a second high-level signal transmitted by the flash memory if the first data transmission link fails to recover. Wherein, the duration of the second high-level signal is greater than the set threshold, and the set threshold is greater than or equal to the duration of the first-level signal. The processing unit is further configured to establish a second data transmission link according to the second level signal. Wherein, establishing the second data transmission link includes sending a link establishment command to the flash memory.

In a possible design solution, the transceiver unit can also be used to receive the duration of the second level signal and the duration of the first level signal sent by the flash memory when the first data transmission link is in a normal state. .

Further, the transceiver unit can also be used for the main chip to send a data read request to the flash memory.

In a possible design solution, the transceiver unit may also be used to receive the first level signal and the second high level signal based on the same differential line. The differential line is a signal line connecting the flash memory and the main chip.

Optionally, the transceiver unit and the processing unit provided in the fourth aspect may be integrated into one module, such as a processing module, or may be independently set up respectively. For example, the transceiver unit may include a receiving module and a sending module. Wherein, the sending module is configured to implement the sending function of the link re-establishment apparatus described in the fourth aspect, and the receiving module is configured to execute the receiving function of the link re-establishment apparatus described in the fourth aspect.

Optionally, the apparatus provided in the fourth aspect may further include a storage module. The storage module stores programs or instructions. When the processing module executes the program or the instruction, the apparatus can execute the link re-establishment method provided by the fourth aspect.

It should be noted that the link reconstruction apparatus described in the fourth aspect may be terminal equipment or network equipment, or may be a chip (system) or other components or components that can be set in the terminal equipment or network equipment, or may include A device of a terminal device or a network device, which is not limited in this application.

In a fifth aspect, the present application further provides an electronic device, including a flash memory and a main chip, the flash memory is communicatively connected to the main chip, wherein the flash memory is used to execute the link reconstruction method provided in the first aspect, and the main chip is used to execute the above-mentioned first method. The link reconstruction method provided in the second aspect.

In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium, where the computer-readable storage medium includes a computer program or an instruction, and when the computer program or instruction is run on a computer, the computer executes the first aspect of the embodiment of the present application. or the link reconstruction method of the second aspect.

In a seventh aspect, an embodiment of the present application provides a computer program product, the computer program product includes: a computer program or an instruction, when the computer program or instruction is run on a computer, the computer is made to execute the first aspect or the second aspect of the embodiment of the present application. Aspects of the link re-establishment method.

It can be understood that the link re-establishment method provided in the second aspect, the link re-establishment apparatus provided in the third aspect, the link re-establishment apparatus provided in the fourth aspect, the electronic device provided in the fifth aspect, and the computer provided in the sixth aspect can be The read storage medium and the computer program product provided by the seventh aspect are the same as or corresponding to the technical features of the link reconstruction method provided by the first aspect. Therefore, the beneficial effects that can be achieved can refer to the method provided by the first aspect. The beneficial effects will not be repeated here.

Description of drawings

1 is a schematic diagram of the hardware structure of a mobile phone provided by an embodiment of the present application;

FIG. 2 is an interactive flowchart of a link re-establishment method provided by an embodiment of the present application;

3 is an interactive flowchart for determining that a first data transmission link is in an abnormal state by a flash memory provided by an embodiment of the present application;

FIG. 4 is a connection block diagram of a main chip and a flash memory provided by an embodiment of the present application;

FIG. 5 is an interactive flowchart of restoring a first data transmission link provided by an embodiment of the present application;

6 is a schematic diagram of a software structure of a link re-establishment apparatus provided by an embodiment of the present application;

FIG. 7 is a schematic structural composition diagram of an electronic device provided by an embodiment of the present application.

Detailed ways

The following describes the technical terms involved in the embodiments of the present application.

Universal flash storage: Universal flash storage (UFS) is a memory based on serial data transmission technology that allows multiple erasing during operation. Although there are only two data channels between its internal storage unit and the main chip , but the actual data transfer rate is high. UFS supports full-duplex mode, all data channels can perform read and write operations at the same time, and the response speed of data read and write is also very high.

The technical solutions in the present application will be described below with reference to the accompanying drawings.

The link reconstruction method provided by the embodiment of the present application can be applied to electronic equipment, and the electronic equipment may be a mobile phone, a tablet computer, a notebook computer, an ultra-mobile personal computer (UMPC), a handheld computer, a netbook, Personal digital assistants (personal digital assistants, PDAs), wearable electronic devices, virtual reality devices, etc., are not limited in this embodiment of the present application.

FIG. 1 is a schematic diagram of a hardware structure of a mobile phone 100 according to an embodiment of the present application. Exemplarily, as shown in FIG. 1 , the electronic device in this embodiment of the present application may be a mobile phone 100 . The embodiment will be specifically described below by taking the mobile phone 100 as an example. It should be understood that the illustrated cell phone 100 is only one example of the electronic device described above, and that cell phone 100 may have more or fewer components than those shown, two or more components may be combined, or Different component configurations are possible.

As shown in FIG. 1 , the mobile phone 100 includes a main chip 101, an internal memory 121, an external memory interface 122, an antenna A, a mobile communication module 131, an antenna B, a wireless communication module 132, an audio module 140, a speaker 140A, a receiver 140B, and a microphone 140C , headphone jack 140D, display screen 151, subscriber identification module (SIM) card interface 152, camera 153, buttons 154, sensor module 160, universal serial bus (universal serial bus, USB) interface 170, charging management module 180 , a power management module 181 and a battery 182 . In other embodiments, the cell phone 100 may also include a motor, an indicator, and the like.

The main chip 101 may include one or more processing units. For example, the main chip 101 may include an application processor (AP), a modem, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, Digital signal processor (digital signal processor, DSP), baseband processor, and/or neural-network processing unit (neural-network processing unit, NPU), etc. It should be noted that different processing units may be independent devices, or may be integrated into one or more independent processors, and may be integrated with other modules in the mobile phone 100 in the same device. Taking the modem as an example, the modem can be a processing unit independent of the main chip 101, or can be integrated with other processing units (such as AP, ISP, GPU, etc.) in the same device, and can also integrate some or all functions with mobile communication Module 131 is integrated in the same device.

Internal memory 121 may be used to store data and/or at least one computer program including instructions. Specifically, the internal memory 121 may include a program storage area and a data storage area. Wherein, the program storage area can store at least one computer program. The computer program may include application programs (such as gallery, contacts, etc.), operating systems (such as Android operating system, or IOS operating system, etc.), or other programs, and the like. The storage data area can store at least one of data created during use of the mobile phone 100, data received from other devices (eg, other mobile phones 100, network devices, servers, etc.), or data pre-stored before leaving the factory. For example, the data stored in the internal memory 121 may be at least one of information such as images, files, or logos.

In some embodiments, the internal memory 121 may include high-speed random access memory and/or non-volatile memory. For example, the internal memory 121 includes one or more magnetic disk storage devices, flash memory (flash), or universal flash storage (UFS), or the like.

Wherein, the main chip 101 can make the mobile phone 100 realize one or more functions by calling one or more computer programs and/or data stored in the internal memory 121 to meet the needs of the user. For example, the main chip 101 may cause the electronic device to execute the link reconstruction method provided in the embodiments of the present application by invoking the instructions and data stored in the internal memory 121 .

The external memory interface 122 can be used to connect an external memory card (eg, a micro SD card) to expand the storage capacity of the mobile phone 100 . The external memory card communicates with the main chip 101 through the external memory interface 122 to realize the data storage function. For example, save files such as images, music, videos, etc. in an external memory card.

In some embodiments, a cache area may also be set in the main chip 101 to store the instructions and/or data that the main chip 101 needs to use cyclically. call directly. This helps to avoid repeated accesses, reduces the waiting time of the main chip 101, and thus helps to improve the efficiency of the system. For example, the cache area may be implemented by a cache memory.

Antenna A and Antenna B are used to transmit and receive electromagnetic wave signals. Each antenna in handset 100 may be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve antenna utilization. For example, the antenna A can be multiplexed into the diversity antenna of the wireless local area network. In other embodiments, the antenna may be used in conjunction with a tuning switch.

The mobile communication module 131 may be used to implement the communication between the mobile phone 100 and the network device according to the mobile communication technology (eg, 2G, 3G, 4G or 5G, etc.) supported by the mobile phone 100 . For example, the mobile communication technology supported by the mobile phone 100 may include at least one of GSM, GPRS, CDMA, WCDMA, TD-SCDMA, LTE, or NR. For example, the mobile phone 100 supports GSM. After the mobile phone 100 accesses the network through the cell provided by the BTS in the GSM communication system, the network signal strength of the accessed cell can be not lower than the judgment threshold, that is, the mobile phone 100 In the state of being on the network, the communication between the mobile phone 100 and the BTS is realized through the mobile communication module 131 . For example, the mobile communication module 131 can amplify the modulated signal of the modem and send it to the network device via the antenna A; the mobile communication module 131 can also receive the signal sent by the network device through the antenna A, amplify it, and then send it to the modem, where the The modem demodulates the received signal into a low-frequency baseband signal, and then performs other corresponding processing. In some embodiments, the mobile communication module 131 may include a filter, a switch, a power amplifier, a low noise amplifier (LNA), and the like.

The wireless communication module 132 can provide applications on the mobile phone 100 including wireless local area networks (WLAN) (such as wireless-fidelity (Wi-Fi) networks), Bluetooth (BT), global Solutions for wireless communication such as global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), and infrared technology (IR). The GNSS may include a global positioning system (global positioning system, GPS), a global navigation satellite system (GLONASS), a Beidou satellite navigation system (beidou navigation satellite system, BDS), a quasi-zenith satellite system (quasi - at least one of zenith satellite system, QZSS) and/or satellite based augmentation systems (SBAS), etc. For example, the wireless communication module 132 may be one or more devices integrating at least one communication processing module. The wireless communication module 132 can communicate with the corresponding device through the antenna B according to the wireless communication technology (eg, Wi-Fi, Bluetooth, FM, NFC, etc.) supported by itself.

The mobile phone 100 can implement audio functions through an audio module 140, a speaker 140A, a receiver 140B, a microphone 140C, an earphone interface 140D, an AP, and the like. Such as music playback, recording, etc.

The mobile phone 100 may implement a display function through the GPU, the display screen 151, and the AP. The display screen 151 may be used to display images, videos, and the like. The display screen 151 may include a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active matrix organic light emitting diode, or an active matrix organic light emitting diode (active-matrix organic light). emitting diode, AMOLED), flexible light-emitting diode (flex light-emitting diode, FLED), Miniled, MicroLed, Micro-oLed, quantum dot light-emitting diode (quantum dot light emitting diodes, QLED) and so on. In some embodiments, the mobile phone 100 may include one or N display screens 151 , where N is a positive integer greater than one.

The keys 154 may include a power key, a volume key, and the like. The keys 154 may be mechanical keys, virtual buttons, virtual options, or the like. The cell phone 100 can receive key input and generate key signal input related to user settings and function control of the cell phone 100 . For example, the mobile phone 100 may, in response to selecting the virtual option for indicating consent to participate in the "User Experience Improvement Program", collect statistics or collect some information about the user's use of the mobile phone 100, so as to provide the user with more personalized services, thereby improving the user experience .

Sensor module 160 may include one or more sensors. For example, the sensor module 160 includes an acceleration sensor 160A, a touch sensor 160B, a fingerprint sensor 160C, and the like. In some embodiments, the sensor module 160 may further include a pressure sensor, a gyroscope sensor, an environmental sensor, a distance sensor, a proximity light sensor, a bone conduction sensor, and the like.

The acceleration sensor (ACC sensor) 160A can collect the magnitude of the acceleration of the mobile phone 100 in various directions (generally three axes). When the mobile phone 100 is stationary, the magnitude and direction of gravity can be detected. In addition, the acceleration sensor 160A can also be used for recognizing the posture of the mobile phone 100, and is applied to applications such as switching between horizontal and vertical screens, and a pedometer. In some embodiments, the acceleration sensor 160A can be connected to the main chip 101 through a microcontroller unit (MCU), thereby helping to save the power consumption of the mobile phone 100 . For example, the acceleration sensor 160A can be connected to the AP and the modem through the MCU. In some embodiments, the MCU may be a general-purpose smart sensor hub.

The touch sensor 160B may also be referred to as a "touch panel". The touch sensor 160B may be disposed on the display screen 151 , and the touch sensor 160B and the display screen 151 form a touch screen, also called a “touch screen”. The touch sensor 160B is used to detect a touch operation on or near it. The touch sensor 160B may communicate the detected touch operation to the AP to determine the touch event type. Then, the mobile phone 100 provides visual output related to the touch operation through the display screen 151 according to the determined touch event type. In other embodiments, the touch sensor 160B may also be disposed on the surface of the mobile phone 100 , which is different from the position where the display screen 151 is located.

The fingerprint sensor 160C is used to collect fingerprints. The mobile phone 100 can use the collected fingerprint characteristics to unlock the fingerprint, access the application lock, take a picture with the fingerprint, answer the incoming call with the fingerprint, and the like.

In other embodiments, the main chip 101 may further include one or more interfaces. For example, the interface may be the SIM card interface 152 . For another example, the interface may also be the USB interface 170 . For another example, the interface may also be an integrated circuit (inter-integrated circuit, I2C) interface, an integrated circuit audio (inter-integrated circuit sound, I2S) interface, a pulse code modulation (pulse code modulation, PCM) interface, a universal asynchronous transceiver transmitter (universal asynchronous receiver/transmitter, UART) interface, mobile industry processor interface (mobile industry processor interface, MIPI), general-purpose input/output (general-purpose input/output, GPIO) interface, etc. It can be understood that, the main chip 101 provided in this embodiment of the present application can be connected to different modules of the mobile phone 100 through an interface, so that the mobile phone 100 can implement different functions. such as sending and receiving information. It should be noted that, the embodiment of the present application does not limit the connection manner of the interface in the mobile phone 100 .

The SIM card interface 152 is used to connect a SIM card. The SIM card can be contacted and separated from the mobile phone 100 by inserting into the SIM card interface 152 or pulling out from the SIM card interface 152 . The mobile phone 100 may support 1 or N SIM card interfaces, where N is a positive integer greater than 1. The SIM card interface 152 can support Nano SIM cards, Micro SIM cards, SIM cards, and the like. Multiple cards can be inserted into the same SIM card interface 152 at the same time. The types of the plurality of cards may be the same or different. The SIM card interface 152 may also be compatible with different types of SIM cards. In some embodiments, the SIM card interface 152 may also be compatible with external memory cards. The mobile phone 100 implements functions such as calling and data communication through the SIM card. In some embodiments, the mobile phone 100 may also adopt an eSIM, that is, an embedded SIM card. The eSIM card can be embedded in the mobile phone 100 and cannot be separated from the mobile phone 100 .

The USB interface 170 is an interface that conforms to the USB standard specification, and may specifically be a Mini USB interface, a Micro USB interface, a USB Type C interface, and the like. The USB interface 170 can be used to connect a charger to charge the mobile phone 100, and can also be used to transfer data between the mobile phone 100 and peripheral devices. It can also be used to connect headphones to play audio through the headphones. The interface can also be used to connect other electronic devices, such as AR devices.

It can be understood that, the interface connection relationship between the modules illustrated in the embodiment of the present invention is only a schematic illustration, and does not constitute a structural limitation of the mobile phone 100 . In other embodiments of the present application, the mobile phone 100 may also adopt different interface connection manners in the foregoing embodiments, or a combination of multiple interface connection manners.

The charging management module 180 is used to receive charging input from the charger. The charger may be a wireless charger or a wired charger. The power management module 181 is used for connecting the battery 182 , the charging management module 180 and the main chip 101 . The power management module 181 receives input from the battery 182 and/or the charging management module 180 to supply power to modules such as the main chip 101 . In some embodiments, the power management module 181 can also be used to monitor parameters such as battery capacity, battery cycle times, battery health status (leakage, impedance).

It should be understood that the structure of the mobile phone 100 shown in FIG. 1 is only an example. The mobile phone 100 of the embodiment of the present application may have more or less components than those shown in the figures, may combine two or more components, or may have different component configurations. The various components shown in the figures may be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing and/or application specific integrated circuits.

Exemplarily, FIG. 2 is a schematic flowchart of a link reestablishment method provided by an embodiment of the present application. The link reconstruction method can be applied to the flash memory 103 and the main chip 101 in the above-mentioned mobile phone 100 . The method includes:

S201 , the main chip 101 sends a data read/write request to the flash memory 103 , and the flash memory 103 receives the data read/write request from the main chip 101 .

Exemplarily, the main chip 101 may include a software layer and a physical layer. Wherein, the software layer may include at least one application program among email, instant chat application, shopping application, game application, etc., which is not limited herein. Specifically, the user can open the instant chat application on the home page of the mobile phone 100 . If the instant chat application receives a picture message, the software layer of the main chip 101 can write the picture information into the double data rate synchronous dynamic random access memory (DDR), and notify the main chip 101 The physical layer of the device sends a data write request to the flash memory 103, and the data write request is used to instruct the writing of picture information. The flash memory 103 receives a data write request from the physical layer of the host chip 101 .

It should be noted that the picture information is only an example, and the data read/written between the main chip 101 and the flash memory 103 may also be other types of data, such as video information, text information, etc., which are not specifically limited in this embodiment of the present application.

S202, the flash memory 103 detects that the first data transmission link is abnormal.

The first data transmission link may be a communication link between the flash memory 103 and the main chip 101 . The first data transmission link includes a first transmission channel and a second transmission channel. The first transmission channel is a transmission channel through which the flash memory 103 sends data to the main chip 101 , and the second transmission channel is a transmission channel through which the main chip 101 sends data to the flash memory 103 . .

Exemplarily, the abnormality of the first data transmission link refers to: the first transmission channel cannot complete the data transmission and/or the second transmission channel cannot complete the data transmission, or, the data transmission of the first transmission channel and/or the second transmission channel The rate does not meet the business requirements.

Specifically, the flash memory 103 may detect whether the first data transmission link is abnormal after receiving the data write request. FIG. 3 is an interactive flowchart for determining that a first data transmission link is in an abnormal state by a flash memory provided by an embodiment of the present application. 3, the main chip 101 sends a data read request to the flash memory 103, the flash memory 103 feeds back to the main chip an acknowledgement packet of receiving the data read request, and then the flash memory 103 sends a data packet to the main chip 101, if the flash memory 103 The flash memory 103 may determine that the first data transmission link is abnormal if the acknowledgement packet of the received data packet is not received from the main chip 101 . Wherein, the data packet may include the above-mentioned picture information.

It should be noted that if the flash memory 103 detects that the first data transmission link is normal, it only needs to perform the normal read and write operations, and does not need to perform the following S203-S208. For the specific implementation, please refer to the existing implementation. The embodiments are not repeated here.

S203, the flash memory 103 adjusts the first parameter.

The first parameter is a working parameter for the flash memory 103 to transmit data in the first data transmission link. For example, the high data transmission rate of the flash memory 103 in the first transmission channel is adjusted to a low data transmission rate. The first data transmission link is the communication link between the flash memory 103 and the main chip 101 .

S204 , the flash memory 103 sends the first level signal to the main chip 101 , and the main chip 101 receives the first level signal from the flash memory 103 .

The first level signal is used to request the master chip 101 to restore the first data transmission link. The duration of the first level signal is specified by the communication protocol between the main chip 101 and the flash memory 103 , such as 2 ms, 1.5 ms, etc., which is not limited here. The first level signal may be a high level signal or a low level signal, which is not limited herein.

FIG. 4 is a block diagram of connection between the main chip 101 and the flash memory 103 according to an embodiment of the present application. As shown in FIG. 4 , a differential line 401 is connected between the flash memory 103 and the main chip 101 , and the flash memory 103 can send a first level signal to the main chip 101 through the differential line 401 . In the above S204, the flash memory 103 sends the first level signal to the main chip 101, and the main chip 101 receives the first level signal from the flash memory 103, which can be specifically implemented as: assuming that the first level signal is a high level signal, the flash memory 103 The two connecting lines of the differential line 401 can be driven to output a high-level signal, and the duration of the high-level signal is the preset duration of the first level signal; accordingly, if the main chip 101 detects a If the signal is a high-level signal, and the duration of the high-level signal reaches the duration of the first-level signal, the main chip 101 can confirm that the high-level signal is the first-level signal, that is, the main chip 101 receives first level signal. In view of the fact that the anti-interference ability of the level signal output by the differential mode is stronger than that of the level signal output by the non-differential mode (such as the single-wire mode), the transmission of the first level signal through the differential line 401 can improve the first power level. reliability of the signal.

S205, the main chip 101 restores the first data transmission link in the abnormal state.

S206, the flash memory 103 detects that the first data transmission link has not been successfully restored.

FIG. 5 is an interactive flowchart of restoring a first data transmission link provided by an embodiment of the present application. Exemplarily, as shown in FIG. 5 , the process of restoring the first data transmission link may include: the main chip 101 adjusts the second parameter. Wherein, the second parameter is a working parameter of the main chip 101 for data transmission in the first data transmission link. For example, the high data transmission rate of the main chip 101 in the first transmission channel is adjusted to a low data transmission rate. The first parameter and the second parameter are equal. The main chip 101 receives the first data packet from the flash memory 103, and the first data packet carries a recovery request. If the main chip 101 receives the first data packet, parses the first data packet and recognizes the recovery request, the main chip 101 adjusts the third parameter, which may be the operating parameter of the main chip 101 on the second transmission channel. For example, the high data transmission rate of the main chip 101 in the second transmission channel is adjusted to a low data transmission rate. The main chip 101 sends the third level signal to the flash memory 103, and after the flash memory 103 receives the third level signal from the main chip 101, it considers that the first data packet is successfully sent to the main chip 101, that is, the first transmission channel is successfully restored. Conversely, if the flash memory 103 does not receive the first level signal from the main chip 101 after sending the first data packet, it is considered that the first data packet failed to be sent to the main chip 101, that is, the first transmission channel failed to recover.

Please continue to refer to FIG. 5 , the flash memory 103 adjusts the fourth parameter after receiving the first level signal from the main chip 101 . The method of adjusting the fourth parameter may be: adjusting the high data transmission rate of the flash memory 103 in the second transmission channel to the low data transmission rate. Among them, the third parameter is equal to the fourth parameter. The main chip 101 sends the second data packet to the flash memory 103. If the flash memory 103 receives the second data packet from the main chip 101, it is considered that the second transmission channel is restored successfully; otherwise, if the flash memory 103 does not receive the second data packet from the main chip 101 , it is considered that the recovery of the second transmission channel fails.

It should be noted that when any one of the first transmission channel and the second transmission channel fails to recover, the flash memory 103 determines that the first data transmission link is not recovered successfully. In addition, if the flash memory 103 detects that the first data transmission link is successfully restored, it only needs to perform the normal read and write operations, and does not need to perform the following S208-S212. For the specific implementation, please refer to the existing implementation manner, the embodiment of the present application No longer.

S207 , the flash memory 103 sends a second level signal to the main chip 101 , and the main chip 101 receives the second level signal from the flash memory 103 .

In order to distinguish between the first level signal requesting the master chip 101 to restore the first data transmission link and the second level signal requesting the master chip 101 to rebuild the link, the duration of the second level signal can be set to be longer than the first level signal. The duration of a level signal. For example, when the duration of the first level signal is 2ms, the duration of the second level signal may be 5ms, 6ms, 7ms, etc., which is not limited herein.

It should be noted that when the first data transmission link is in a normal state, the main chip 101 can receive the duration of the second level signal and the duration of the first level signal from the flash memory 103 so that the main chip 101 Identify the second level signal and the first level signal.

Exemplarily, the duration of the second level signal and the duration of the first level signal may be sent by the flash memory 103 to the main chip 101 actively, or the flash memory 101 may send a data read request to the flash memory 103 after the flash memory 103 sends a data read request. 103; it may also be pre-configured on the main chip 101, which is not limited here.

In a possible implementation manner, the difference between the duration of the second level signal and the duration of the first level signal is greater than or equal to the first threshold. Wherein, the first threshold may be 3ms, 5ms, 7ms, etc., which is not limited herein. For example, the duration of the first level signal is 3ms and the duration of the second level signal is 6ms; or, the duration of the second level signal is 3ms and the duration of the second level signal is 8ms. Since the difference between the duration of the second-level signal and the duration of the first-level signal is greater than or equal to the first threshold, the main chip 101 can accurately distinguish the first-level signal and the second-level signal.

In another implementation manner, the duration of the second level signal is greater than or equal to the second threshold, and the second threshold is greater than the duration of the first level signal. The second threshold may be stored in a register set by the main chip 101, and the main chip 101 may access the register at any time to obtain the second threshold.

For example, the second threshold may be that after the main chip 101 obtains the duration of the first level signal and the duration of the second level signal, the duration of the signal is greater than the duration of the first level signal and less than the second level. The value of the duration of the signal is obtained. For example, if the duration of the first level signal is 2ms and the duration of the second level signal is 10ms, the main chip 101 may determine that the second threshold is 6ms. Understandably, when the duration of the second-level signal is greater than the second threshold, the difference between the duration of the first-level signal and the first-level signal is relatively large, so that the main chip 101 can accurately distinguish the first-level signal and the second-level signal. Signal.

It should be understood that, as shown in FIG. 4 , in order to save hardware resources, the flash memory 103 can send the first level signal and the second high level signal to the main chip 101 based on the same differential line 401 . The above differential lines 401 are all signal lines connecting the flash memory 103 and the main chip 101 . Since the first-level signal and the second high-level signal are transmitted based on the same differential line, there is no need to increase additional hardware resources to save costs.

In addition, two sets of differential lines 401 may also be provided between the flash memory 103 and the main chip 101 , wherein one set of differential lines 401 is used to transmit first level signals, and the other set of differential lines 401 is used to transmit second level signals. It can be understood that the two groups of differential lines have different pin identifiers, and the main chip 101 can determine that the received level signal is the first level signal or the second level signal according to the pin identifiers of the differential lines.

It should be noted that, when there are two sets of differential lines, the duration of the first level signal and the duration of the second level signal may be irrelevant.

S208, the main chip 101 establishes a second data transmission link, and the flash memory 103 establishes a second data transmission link.

The establishment of the second data transmission link by the main chip 101 includes sending a link establishment command to the flash memory 103 ; the establishment of the second data transmission link by the flash memory 103 includes receiving a chain establishment command from the main chip 101 .

As shown in FIG. 4 , a reset line 402 is further connected between the flash memory 103 and the main chip 101 . The link building command may include a reset command. The specific process of S208 includes: the main chip 101 restarts by controlling its own reset pin to reset, and then the main chip 101 sends a reset command to the flash memory 103 through the reset line 402 to enable the reset pin of the flash memory 103 to reset, thereby controlling the flash memory 103 to restart . Then the main chip 101 and the flash memory 103 shake hands again, and cooperate with each other to establish a second data transmission link. Therefore, the main chip 101 can immediately read and write data to the flash memory 103 normally through the second data transmission link. For example, the main chip 101 writes the above-mentioned picture information to the flash memory 103 through the second data transmission link.

According to the experiment of the inventor, in the prior art, the main chip 101 needs to wait for 3 seconds to 5 seconds to initiate the establishment of the second data transmission link from issuing a data read and write request, while the embodiment of the present application only needs to wait for 3 seconds to 5 seconds from issuing a data read and write request. Waiting for 5ms-10ms, the second data transmission link will be established, which can greatly reduce the time it takes to rebuild the link when the data link is abnormal, so as to avoid data read/write freezes, thereby improving the user experience. In addition, the second level signal of the flash memory requesting the main chip 101 to rebuild the second data transmission link is a stable signal (without jumping), even if the first data transmission link is abnormal, the main chip 101 can accurately detect the second level signal. level signal, high reliability.

FIG. 6 is a schematic diagram of a software structure of a link re-establishment apparatus provided by an embodiment of the present application. Referring to FIG. 6 , the link rebuilding apparatus 600 can be applied to a flash memory of an electronic device, and the electronic device further includes a main chip 101 . As shown in FIG. 4 , a differential line 401 and a reset line 402 are connected between the flash memory 103 and the main chip 101 . The function of the differential line 401 in the embodiment of the present application is the same as that of the differential line 401 in the above-mentioned embodiment; the function of the reset line 402 in this embodiment is the same as that of the reset line 402 in the above-mentioned embodiment, which will not be repeated here. . As shown in FIG. 6 , the link re-establishment apparatus 600 includes a processing unit 601 and a transceiver unit 602 . The transceiver unit 602 is configured to execute S201, S204, and S207 in the foregoing embodiments; the processing unit 601 is configured to execute S202, S203, S206, and S208 in the foregoing embodiments.

In addition, the link re-establishment apparatus 600 may also be applied to the main chip 101 . When the link re-establishment apparatus 600 is applied to the main chip 101, the transceiver unit 602 is configured to execute S201, S204, and S207 in the foregoing embodiment, and the processing unit 601 is configured to execute S205 and S208 in the foregoing embodiment.

Optionally, the link re-establishment apparatus 600 may further include a storage unit (not shown in FIG. 6 ). The storage unit stores programs or instructions. When the processing unit executes the program or the instruction, the link re-establishment apparatus 600 can execute the link re-establishment method in FIG. 2 or FIG. 4 .

Optionally, the transceiver unit may be integrated into one unit, or may be divided into a receiving unit and a transmitting unit. Wherein, the sending unit is configured to perform the sending function of the link re-establishment apparatus 600 , and the receiving unit is configured to perform the receiving function of the link re-establishment apparatus 600 .

It should be noted that, the basic principles and technical effects of the link re-establishment apparatus 600 provided by the embodiments of the present application are the same as those of the above-mentioned method embodiments. Corresponding content in the method embodiment.

Exemplarily, FIG. 7 is a schematic structural diagram of an electronic device 700 provided by an embodiment of the present application. Below in conjunction with FIG. 7 , each component of the electronic device 700 will be specifically introduced:

The main chip 701 is the control center of the electronic device 700 , and the main chip 701 may include a processor 7011 and a processor 7022 . For example, both the processor 7011 and the processor 7022 may include one or more central processing units (CPUs), may also include specific integrated circuits (application specific integrated circuits, ASICs), or may be configured to implement the present application One or more integrated circuits of an embodiment, for example: one or more microprocessors (digital signal processors, DSP), or, one or more field programmable gate arrays (field programmable gate array, FPGA).

Optionally, the main chip 701 can execute various functions of the electronic device 700 by running or executing software programs stored in the ROM 702 and calling data stored in the ROM 702 . For example, the main chip 701 may execute S201 , S204 , S205 , S207 , and S208 in the foregoing embodiments of the present application, which are not limited herein.

In a specific implementation, as an embodiment, the main chip 701 may include one or more CPUs, such as CPU0 and CPU1 shown in FIG. 7 .

The read-only memory 702 is used to store the software program for executing the solution of the present application, and is controlled and executed by the main chip 701. For the specific implementation, reference may be made to the above method embodiments, which will not be repeated here.

Optionally, the read-only memory 702 may be an electrically erasable programmable read-only memory (electrically erasable programmable read-only memory, EEPROM), a compact disc read-only memory (CD-ROM), or other optical disk storage, Optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or capable of carrying or storing desired program code in the form of instructions or data structures and capable of Any other medium that can be accessed by a computer, but is not limited to this. The read-only memory 702 may be integrated with the main chip 701, or may exist independently, and be coupled to the main chip 701 through an interface circuit (not shown in FIG. 7) of the electronic device 700, which is not specifically limited in this embodiment of the present application.

The transceiver 703 is used for communication with other electronic devices. For example, the electronic device 700 is an electronic device, and the transceiver 703 may be used to communicate with a network device, or communicate with another electronic device. For another example, the electronic device 700 is a network device, and the transceiver 703 can be used to communicate with the electronic device or communicate with another network device.

Optionally, transceiver 703 may include a receiver and a transmitter (not shown separately in FIG. 7). Among them, the receiver is used to realize the receiving function, and the transmitter is used to realize the sending function.

Optionally, the transceiver 703 may be integrated with the main chip 701, or may exist independently, and be coupled to the main chip 701 through an interface circuit (not shown in FIG. 7 ) of the electronic device 700, which is not performed in this embodiment of the present application Specific restrictions.

The flash memory 704 is a memory based on serial data transmission technology that allows to be erased or written multiple times during operation. Although there are only two data channels between its internal storage unit and the main chip, due to the use of serial data transmission, its actual The data transfer speed is very high. UFS supports full-duplex mode, all data channels can perform read and write operations at the same time, and the response speed of data read and write is also very high. The flash memory 704 may execute S201 , S202 , S203 , S204 , S206 , S207 , and S208 in the above embodiments of the present application.

It should be noted that the structure of the electronic device 700 shown in FIG. 7 does not constitute a limitation on the link reconstruction apparatus, and the actual link reconstruction apparatus may include more or less components than those shown in the figure, or a combination of certain some components, or a different arrangement of components.

In addition, for the technical effect of the electronic device 700, reference may be made to the technical effect of the link re-establishment method described in the foregoing method embodiments, which will not be repeated here.

Embodiments of the present application further provide a computer-readable storage medium, where computer program codes are stored in the computer-readable storage medium, and when the processor executes the computer program codes, the electronic device executes the methods in the foregoing embodiments.

The embodiments of the present application also provide a computer program product, which when the computer program product runs on the electronic device, enables the electronic device to execute the method in the above-mentioned embodiments.

From the description of the above embodiments, those skilled in the art can clearly understand that for the convenience and brevity of the description, only the division of the above functional modules is used as an example for illustration. In practical applications, the above functions can be allocated as required. It is completed by different functional modules, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. For the specific working process of the system, apparatus and unit described above, reference may be made to the corresponding process in the foregoing method embodiments, and details are not described herein again.

Each functional unit in each of the embodiments of the embodiments of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit. The above-mentioned integrated units may be implemented in the form of hardware, or may be implemented in the form of software functional units.

The integrated unit, if implemented in the form of a software functional unit and sold or used as an independent product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of the present application can be embodied in the form of software products in essence, or the parts that make contributions to the prior art, or all or part of the technical solutions, and the computer software products are stored in a storage The medium includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: flash memory, removable hard disk, read-only memory, random access memory, magnetic disk or optical disk and other media that can store program codes.

The above are only specific implementations of the embodiments of the present application, but the protection scope of the embodiments of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the embodiments of the present application shall be covered by this within the protection scope of the application examples. Therefore, the protection scope of the embodiments of the present application should be subject to the protection scope of the claims.

Claims

A link reconstruction method, characterized in that it is applied to a flash memory of an electronic device, the electronic device further includes a main chip, and the method includes:

When the flash memory detects that the first data transmission link is in an abnormal state, the flash memory adjusts a first parameter, where the first parameter is the operation of the flash memory to transmit data on the first data transmission link parameter, the first data transmission link is the communication link between the flash memory and the main chip;

The flash memory sends a first level signal to the main chip, where the first level signal is used to request the main chip to restore the first data transmission link;

If the flash memory detects that the recovery of the first data transmission link fails, it sends a second level signal to the main chip, wherein the duration of the second level signal is longer than the first level signal the duration of

the flash memory receives a link establishment command from the main chip;

The flash memory establishes a second data transmission link according to the link establishment command.
The method according to claim 1, wherein a difference between the duration of the second level signal and the duration of the first level signal is greater than or equal to a first threshold.
The method according to claim 1 or 2, wherein the duration of the second level signal is greater than or equal to a second threshold, wherein the second threshold is greater than the duration of the first level signal .
The method according to any one of claims 1-3, wherein before the flash memory adjusts the first parameter, the method further comprises:

When the first data transmission link is in a normal state, the flash memory transmits the duration of the second level signal and the duration of the first level signal to the master chip.
The method according to claim 4, wherein before the flash memory sends the duration of the second level signal and the duration of the first level signal to the host chip, the method further include:

The flash memory receives a data read request from the main chip.
The method according to any one of claims 1-5, wherein the flash memory transmits the first level signal and the second level signal based on the same differential line, wherein the differential line is a connection the signal line between the flash memory and the main chip.
A link reconstruction method, characterized in that it is applied to a main chip of an electronic device, the electronic device further includes a flash memory, and the method includes:

the main chip receives a first level signal output by the flash memory, where the first level signal is used to request the main chip to restore the first data transmission link;

The main chip restores the first data transmission link in an abnormal state, wherein the first data transmission link is a communication link between the flash memory and the main chip;

If the recovery of the first data transmission link fails, the master chip receives a second level signal transmitted by the flash memory, wherein the duration of the second level signal is greater than a set threshold, and the set The threshold value is greater than or equal to the duration of the first level signal;

Establishing a second data transmission link according to the second level signal, wherein the establishing the second data transmission link includes sending a link establishment command to the flash memory.
The method according to claim 7, wherein a difference between the duration of the second level signal and the duration of the first level signal is greater than or equal to a first threshold.
The method according to claim 7 or 8, wherein the duration of the second level signal is greater than or equal to a second threshold, wherein the second threshold is greater than the duration of the first level signal .
The method according to any one of claims 7-9, wherein before the master chip receives the first level signal output by the flash memory, the method further comprises:

When the first data transmission link is in a normal state, the main chip receives the duration of the second level signal sent by the flash memory and the duration of the first level signal.
The method according to claim 10, wherein before the master chip receives the duration of the second level signal and the duration of the first level signal sent by the flash memory, the method Also includes:

The main chip sends a data read request to the flash memory.
The method according to any one of claims 7-11, wherein the main chip receives the first level signal and the second level signal based on the same differential line, wherein the differential line is a connection Signal lines between the flash memory and the main chip.
A link reconstruction device, characterized in that it is applied to a flash memory of an electronic device, the electronic device further includes a main chip, and the device includes a processing unit and a transceiver unit; wherein,

The processing unit is configured to adjust a first parameter when detecting that the first data transmission link is in an abnormal state, wherein the first parameter is the operation of the flash memory to transmit data on the first data transmission link parameter, the first data transmission link is the communication link between the flash memory and the main chip;

the transceiver unit, configured to send a first level signal to the main chip, where the first level signal is used to request the main chip to restore the first data transmission link;

The processing unit is further configured to control the transceiver unit to send a second level signal to the main chip if it is detected that the recovery of the first data transmission link fails, wherein the value of the second level signal is The duration is longer than the duration of the first level signal;

The transceiver unit is further configured to receive a link establishment command from the main chip;

The processing unit is further configured to establish a second data transmission link according to the link establishment command.
The apparatus according to claim 13, wherein a difference between the duration of the second level signal and the duration of the first level signal is greater than or equal to a first threshold.
The apparatus according to claim 13 or 14, wherein the duration of the second level signal is greater than or equal to a second threshold, wherein the second threshold is greater than the duration of the first level signal .
The device according to any one of claims 13-15, characterized in that,

The transceiver unit is further configured to send the duration of the second level signal and the duration of the first level signal to the master chip when the first data transmission link is in a normal state duration.
The apparatus of claim 16, wherein:

The transceiver unit is further configured to receive a data read request from the main chip.
The device according to any one of claims 13-17, characterized in that,

The transceiver unit is further configured to send the first level signal and the second level signal based on the same differential line, wherein the differential line is a signal line connecting the flash memory and the main chip.
A link reconstruction device, characterized in that it is applied to a main chip of an electronic device, the electronic device further includes a flash memory, and the device includes a transceiver unit and a processing unit; wherein,

the transceiver unit, configured to receive a first level signal output by the flash memory, where the first level signal is used to request the main chip to restore the first data transmission link;

the processing unit, configured to restore a first data transmission link in an abnormal state, wherein the first data transmission link is a communication link between the flash memory and the main chip;

The transceiver unit is further configured to receive a second level signal transmitted by the flash memory if the first data transmission link fails to recover, wherein the duration of the second level signal is greater than a set threshold, The set threshold is greater than or equal to the duration of the first level signal;

The processing unit is further configured to establish a second data transmission link according to the second level signal, wherein the establishing of the second data transmission link includes sending a link establishment command to the flash memory.
The apparatus according to claim 19, wherein a difference between the duration of the second level signal and the duration of the first level signal is greater than or equal to a first threshold.
The apparatus according to claim 19 or 20, wherein the duration of the second level signal is greater than or equal to a second threshold, wherein the second threshold is greater than the duration of the first level signal .
The device according to any one of claims 19-21, wherein the transceiver unit is further configured to receive all data sent by the flash memory when the first data transmission link is in a normal state. The duration of the second level signal is the same as the duration of the first level signal.
The device according to claim 22, wherein the transceiver unit is further configured to send a data read request to the flash memory by the master chip.
The device according to any one of claims 19-23, wherein the transceiver unit is further configured to receive the first level signal and the second level signal based on the same differential line, wherein the The differential line is a signal line connecting the flash memory and the main chip.
An electronic device, characterized in that it comprises a flash memory and a main chip, the flash memory is communicatively connected to the main chip, wherein the flash memory is used to perform the link reconstruction according to any one of claims 1-6 The method, the main chip is configured to execute the link re-establishment method according to any one of claims 7-12.