WO2022121585A1 - 一种片上亚波长束缚波导及其制备方法 - Google Patents

一种片上亚波长束缚波导及其制备方法 Download PDF

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WO2022121585A1
WO2022121585A1 PCT/CN2021/128981 CN2021128981W WO2022121585A1 WO 2022121585 A1 WO2022121585 A1 WO 2022121585A1 CN 2021128981 W CN2021128981 W CN 2021128981W WO 2022121585 A1 WO2022121585 A1 WO 2022121585A1
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chip
subwavelength
optical waveguide
layer
refractive index
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张福平
管志强
徐红星
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武汉大学
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    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/107—Subwavelength-diameter waveguides, e.g. nanowires
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/13—Integrated optical circuits characterised by the manufacturing method
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B2006/12035—Materials
    • G02B2006/12038—Glass (SiO2 based materials)
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B2006/12166—Manufacturing methods

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  • the invention relates to an on-chip subwavelength confinement waveguide and a preparation method thereof.
  • Surface plasmon resonance is the collective oscillation behavior of electron gas in metals under the action of an external electromagnetic field. Because the dispersion of its wave behavior is closer to the wave behavior of electron gas, surface plasmon resonance has strong evanescent wave propagation behavior and electromagnetic energy energy binding ability. Metal plasmon waveguides based on surface plasmon resonance provide a key technical path for on-chip optical waveguides that break through the diffraction limit of optical wavelengths, and have important application prospects in high-integration optical chips.
  • plasmon waveguides can also use micro-nano processing technology.
  • the cross-section of metal waveguides formed by micro-nano processing is generally rectangular.
  • the rectangular plasmon waveguide forms a leakage mode due to the planar contact surface with the substrate during the propagation process, resulting in the leakage of a large amount of energy from the substrate.
  • the effective refractive index of the plasmon waveguide in the general bound mode is relatively high, so it is more localized.
  • this high effective refractive index mode when free-space photons are coupled into the plasmonic waveguide, Due to the mismatch in momentum, the efficiency is very low.
  • the present invention proposes an on-chip subwavelength confinement waveguide and a preparation method thereof.
  • An on-chip subwavelength bound optical waveguide comprising a substrate and a metal nanostructure, a high-refractive-index dielectric layer is arranged between the substrate and the metal nanostructure, and the high-refractive index dielectric layer material has a higher refractive index than the substrate .
  • the cross section of the metal nanostructure is a rectangular structure, the thickness is 50 to 250 nanometers, and the width is 50 to 500 nanometers.
  • the material of the substrate is silicon dioxide; the material of the high refractive index medium layer is silicon or aluminum oxide; and the material of the metal nanostructure includes gold, silver, aluminum, and copper.
  • the thickness of the high refractive index medium layer is 10-500 nm.
  • the thickness of the high refractive index medium layer is 0.225 to 0.275 times the transmission wavelength of light in the medium.
  • the effective refractive index of the on-chip subwavelength waveguide is 1.06 to 1.1.
  • Another object of the present invention is to provide a method for preparing the above-mentioned on-chip subwavelength bound optical waveguide, comprising the following steps:
  • a pattern template is made on the upper surface of the high-refractive index medium layer, then metal is deposited, and then the template is peeled off to obtain a metal nanostructure.
  • a layer of trimethoxysilane molecules is self-assembled on the surface thereof, and the thickness of the trimethoxysilane molecular layer is 0.7 to 3.5 nanometers.
  • an isolation layer is deposited on the surface of the metal nanostructure, and the thickness of the isolation layer is 0-10 nm.
  • Another object of the present invention is to provide the application of the above-mentioned on-chip subwavelength-bound optical waveguide, as a modulator, to modulate the conduction behavior of plasmons by adjusting the thickness of the high-refractive-index dielectric layer.
  • the energy that should be leaked into the substrate due to the mode is affected by the high-refractive-index layer, the mode in the high-refractive-index layer and the original plasmon waveguide
  • the modes are coupled to form new hybrid modes.
  • the final mode energy is mainly distributed on the side away from the substrate, mainly in the air, so that it has a smaller effective refractive index, and free-space photons are easier to perform momentum compensation, and thus more easily coupled into the plasmon.
  • the present invention can also be compatible with commercial silicon-based nano-fabrication without the need for unpopular and complicated process technologies.
  • Plasmons can be excited by using an air objective lens, without complex refractive index matching oil (which may contaminate the sample), which is more practical in some usage scenarios, such as the need for the electric field to leak into the air for gas detection, etc.
  • the invention uses a high refractive index thin layer to suppress the leakage of the rectangular plasmon waveguide on the dielectric substrate, improves the conduction efficiency, increases the coupling of free photons into the waveguide, and solves the problem of the large loss of the plasmon on the substrate.
  • This problem provides a new idea, and it is possible to modulate the conduction behavior of plasmons through its thickness, and it may be made into photonic chips such as modulated optical switches, which has a positive promotion for plasmonic optical chips and other application fields. effect.
  • FIG. 1 is a schematic structural diagram of an on-chip subwavelength bound waveguide and an excitation plasmon method according to Embodiment 1 of the present invention, wherein FIG. 1(a) is the yz cross section of the substrate structure, and FIG.
  • Fig. 2 is the scanning electron microscope image of the metal nanowire of the rectangular cross-section made on the layered substrate;
  • Fig. 3 is the technological manufacture flow of this structure
  • Figure 4 is a microscope view of the conduction properties of different high-refractive-index thin layers of the same size nano-waveguide (cross-section width 300 nanometers, height 150 nanometers, length 8 micrometers), and the graph is the change of the end scattering intensity;
  • Fig. 5 shows the relationship between the variation of the scattering intensity of the tip in Fig. 4 and the thickness, which is represented by a star point, and the solid line is the simulation result;
  • Figure 6 shows the fitting of the conduction characteristics of three high-refractive-index layers with different thicknesses in the experiment. It can be seen that under a specific thickness (45 nm), the coupling efficiency is obviously enhanced and the conduction loss is reduced;
  • Figure 7 shows the simulated conducted electric field distribution, with the energy mainly distributed on the side away from the substrate.
  • the on-chip subwavelength confinement waveguide in this embodiment adopts a commercial SOI substrate, including a bottom silicon layer, a top silicon layer, and a silicon dioxide layer between them, and the top silicon is used as a high-refractive index medium layer, etc.
  • the plasmonic waveguide is located on the top silicon layer, wherein the thickness of the top silicon layer is 50 nanometers, the thickness of the silicon dioxide layer is 3 micrometers, and the thickness of the bottom silicon layer is 750 micrometers.
  • the width is 300 nanometers and the length is 8 micrometers.
  • Fig. 2 is a scanning electron microscope image of the fabricated silicon waveguide, and the small image on the right shows that the cross-section is nearly rectangular.
  • the fabrication process is shown in Figure 3.
  • the commercial SOI substrate with the top silicon thickness of 220 nm was cleaned, and the top silicon was etched into a thin silicon layer with a thickness of 50 nm by reactive ion etching technology, and then the substrate was soaked in A layer of MPTMS molecules (0.7 nm) was modified on the silicon thin layer in toluene dissolved with MPTMS (alcohol propyl trimethoxysilane) to increase the adhesion of the metal and improve the surface roughness of the nano-gold waveguide.
  • the photoresist (polymethyl methacrylate, PMMA) waveguide pattern is then fabricated by electron beam exposure technology.
  • a 150-nanometer-thick gold film is deposited by thermal evaporation, and the required plasmonic waveguide is formed by a stripping process, and the surface roughness is further reduced by annealing.
  • Some protective layers eg, aluminum oxide
  • Figure 4 shows the micrographs of the conduction performance of nanowaveguides of the same size with different high refractive index thin layer thicknesses, which illustrate the variation of tip scattering intensity.
  • the thickness of the silicon thin layer in the 7 pictures is 0 nanometer (without silicon), 53 nanometers, 69 nanometers, 97 nanometers, 149 nanometers, 177 nanometers, 220 nanometers, and the bottom of each picture is the focused laser spot (polarization mode up and down direction). ), the upper bright spot is the scattering point of the plasmon at the other end of the metal waveguide. It can be seen that the propagation effects are different in the case of silicon layers with different thicknesses.
  • the tip scattering intensity results are plotted in Fig.
  • the conduction strength is greatly enhanced at certain thicknesses, and the conduction is very poor at certain thicknesses, indicating that the thickness of the silicon layer has a periodic modulation effect on the conduction behavior of the plasmonic waveguide, which can realize the switching of plasmonics.
  • the scattered light from the tip is basically undetectable, while strong propagation can be seen in the 50 nm silicon layer, indicating that the presence of the silicon layer can greatly increase its conductivity.
  • the four different sets of data points in Figure 6 represent the variation of the tip scattering intensity with the metal waveguide length (5 ⁇ m to 14 ⁇ m) at four different silicon layer thicknesses (0 nm, 17 nm, 45 nm, 77 nm). And its propagation length L and coupling strength A are fitted by the curve, and the curve is represented by a solid line.
  • the propagation length represents the length through which the energy decays to its original 1/e intensity, using the formula It can be seen that the role of the silicon layer is not only to reduce the loss, but also to improve the coupling efficiency.
  • Figure 7 shows that the waveguide with 45nm thick silicon layer has better conduction effect than the 95nm silicon layer (above).
  • the mode distribution is more localized in the upper air, while at 95 nm, it is mostly distributed in the substrate, which will cause the leaky mode to dissipate a large amount of energy in the substrate, resulting in very large losses.
  • a good conduction effect of plasmons on the substrate can be achieved without medium matching such as oil, and the conduction effect can be modulated by the substrate. It makes him very suitable for the fabrication and application of some photonic chips such as optical switches in the fields of plasmonic photonic chips.

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Abstract

一种片上亚波长束缚光波导，包括衬底和金属纳米结构，衬底和金属纳米结构之间设置有高折射率介质层，高折射率介质层材料的折射率高于衬底。由于衬底上高折射率介质层的存在，波导更容易耦合进等离激元，采用空气物镜就可激发等离激元，在某些使用场景更加实用，比如需要电场外漏于空气中实现气体检测等。通过其厚度来调制等离激元的传导行为，做成可调制的光开关等光子芯片，为等离激元光芯片等应用领域有积极的推动作用。

Description

一种片上亚波长束缚波导及其制备方法 技术领域
本发明涉及一种片上亚波长束缚波导及其制备方法。
背景技术
表面等离激元共振是外加电磁场作用下金属中电子气的集体震荡行为。由于其波动行为的色散更接近电子气的波动行为，表面等离激元共振具有很强的倏逝波传播行为和电磁能能量束缚能力。基于表面等离激元共振的金属等离激元波导为片上尺寸突破光波长衍射极限的光波导提供了关键的技术路径，在高集成度光芯片方面具有重要的应用前景。
表面等离激元波导存在的一个问题是由于金属中电阻损耗的存在，如果能量分布在金属中过多则会导致损耗的加大，而在介质中分布的过多则导致波导尺寸的增加。所以选择合适的波导结构对等离激元波导的传播行为造成很大的影响。在科研中，有使用化学合成的金属纳米线，此种纳米线的表面光滑，呈现一个类圆形的截面，这种等离激元波导传播特性优良，但局限于在具体使用中很难使得纳米线选择性的生长，因而难以实现工业化。
在工业中电子芯片都使用微纳加工技术，同样的，等离激元波导也可以使用微纳加工技术，然而微纳加工形成的金属波导截面一般为矩形。而矩形的等离激元波导在传播过程中由于和衬底为一个平面接触面，从而形成泄露模式，导致很大的能量从衬底中泄露出来。
另外一般束缚模式的等离激元波导的有效折射率比较高，从而更加局域，可是在这种高有效折射率的模式中，在将自由空间的光子耦合到等离激元波导中时，由于动量的不匹配，效率非常低。
因此，改善矩形波导在衬底上的等离激元波导特性将对纳米光子芯片将起到很大的推动性作用。
发明内容
为了抑制矩形等离激元波导中泄露模式的形成，提高传输效率，增加自由空间中光子的耦合效率，本发明提出了一种片上亚波长束缚波导及其制备方法。
本发明解决上述技术问题所采用的方案是：
一种片上亚波长束缚光波导，包括衬底和金属纳米结构，所述衬底和金属纳米结构之间设置有高折射率介质层，所述高折射率介质层材料的折射率高于衬底。
优选地，所述金属纳米结构的截面为矩形结构，厚度50至250纳米，宽度为50至500纳米。
优选地，所述衬底材料为二氧化硅；所述高折射率介质层材料为硅或者氧化铝；所述金属纳米结构的材质包括金，银，铝，铜。
优选地，所述高折射率介质层的厚度为10～500nm。
优选地，所述高折射率介质层的厚度为光在介质中的传导波长的0.225～0.275倍。
优选地，所述片上亚波长波导的有效折射率为1.06至1.1。
本发明的另一目的是提供上述片上亚波长束缚光波导的制备方法，包括如下步骤：
(1)提供表面带有高折射率介质层的衬底，使高折射率介质层的表面平整；
(2)在所述高折射率介质层上表面制作出图形模板，然后沉积金属，再剥离模板得到金属纳米结构。
优选地，在高折射率介质层表面制作图形模板前，先在其表面自组装一层三甲氧基硅烷分子，所述三甲氧基硅烷分子层的厚度为0.7至3.5纳米。
优选地，步骤(2)在剥离模板之前，在金属纳米结构表面沉积一层隔离层，所述隔离层的厚度为0～10nm。
本发明的另一目的是提供上述片上亚波长束缚光波导的应用，作为调制器，通过调整高折射率介质层的厚度来调制等离激元的传导行为。
本发明中，由于衬底上高折射率介质层的存在，本应该由于模式而泄露到衬底中的能量被高折射率层影响，高折射率层中的模式和原本等离激元波导中的模式进行耦合而形成新的杂化模式。最终模式能量主要分布在远离衬底的一侧，主要分布在空气中，从而拥有较小的有效折射率，自由空间光子更容易进行动量补偿，从而更容易耦合进等离激元。本发明还可以与商业硅基纳米制造相兼容，无需冷门、复杂的工艺技术。采用空气物镜就可激发等离激元，无需复杂的折射率匹配油(有可能污染样品)，在某些使用场景更加实用，比如需要电场外漏于空气中实现气体检测等。本发明利用高折射率薄层来抑制矩形等离激元波导在介质衬底上的泄露，提高了传导效率，增加自由光子到波导中的耦合，为解决等离激元在衬底上损耗大的问题提供了一条新思路，并有可能通过其厚度来调制等离激元的传导行为，可能做成可调制的光开关等光子芯片，为等离激元光芯片等应用领域有积极的推动作用。
附图说明
图1为本发明实施例1片上亚波长束缚波导的结构示意图以及激发等离激元方式，其中图(a)为衬底结构的yz截面，图(b)为xz截面；
图2为制作出的矩形截面的金属纳米线在层状衬底上的扫描电镜图；
图3为该结构的工艺制作流程；
图4为不同的高折射率薄层的同样尺寸纳米波导(截面宽300纳米，高150纳米，长度 8微米)的传导性能的显微镜图，图示为端头散射强度变化；
图5为图四中端头散射强度变化随着厚度的关系，由星状点表示，实线为仿真结果；
图6为实验中三种不同厚度高折射率层的传导特性拟合，可以看出特定厚度(45纳米)下有很明显的增强耦合效率和降低传导损耗的结果；
图7为仿真的传导电场分布，能量主要分布在远离衬底的一侧。
具体实施方式
为更好的理解本发明，下面的实施例是对本发明的进一步说明，但本发明的内容不仅仅局限于下面的实施例。
实施例1
如图1所示，本实施例片上亚波长束缚波导采用商业SOI衬底，包括底层硅层、顶层硅层以及位于二者之间的二氧化硅层，顶层硅作为高折射率介质层，等离激元波导位于顶层硅层之上，其中顶层硅层厚度50纳米，二氧化硅层厚度3微米，底层硅层750微米，等离激元波导为金材质的矩形结构，截面高度150纳米，宽度300纳米，长度8微米。图2为制作的硅波导的扫描电镜图，右侧小图显示了截面为接近矩形的形状。
制作流程如图3所示，首先将顶层硅厚度为220纳米的商业SOI衬底清洗，通过反应离子刻蚀技术将顶层硅刻蚀成厚度为50纳米的硅薄层，然后将衬底浸泡在溶解有MPTMS(醇基丙基三甲氧基矽烷)的甲苯中，以在硅薄层上修饰一层MPTMS分子(0.7纳米)来增加金属的粘附性，提高纳米金波导表面粗糙度。再利用电子束曝光技术制作出光刻胶(聚甲基丙烯酸甲酯，PMMA)波导图形。然后利用热蒸发沉积150纳米厚的金薄膜，并通过溶脱工艺形成需要的等离激元波导，通过退火使得表面粗糙度进一步减小。可以制作一些保护层(例如氧化铝)保护金属波导。
将制作好的样品放在100倍空气物镜(NA＝0.9)下，利用660纳米波长激光垂直通过物镜聚焦到等离激元波导一端，偏振方向为平行于波导长轴方向，利用同一个物镜收集另外端头的散射光，并通过相机成像，激光功率1微瓦，相机曝光时间33毫秒。
图4中显示出不同的高折射率薄层厚度，同样尺寸的纳米波导的传导性能的显微镜图，图示体现端头散射强度变化。7幅图中硅薄层厚度依次为0纳米(没有硅)，53纳米，69纳米，97纳米，149纳米，177纳米，220纳米，其中每幅图下为聚焦的激光光斑(偏振方式上下方向)，上部亮点为等离激元在金属波导另外一端的散射点。可见不同厚度硅层情形下传播效果不同。端头散射强度结果绘制在图5中，由星表示，并和时域有限差分仿真的结果比较得到比较符合的结果。可知在某些厚度下传导强度大大增强，在某些厚度则传导很差，说明此硅层厚度对等离激元波导传导行为有周期性调制作用，可以实现等离激元的开关。在没 有硅层情况下基本探测不到端头的散射光，而在50纳米硅层可以看到很强的传播，说明硅层的存在可以大幅增加其传导性能。
图6中四组不同数据点代表在四种不同硅层厚度下(0纳米，17纳米，45纳米，77纳米)端头的散射强度随着金属波导长度(5微米到14微米)的变化。并且由曲线拟合出其传播长度L和耦合强度A，曲线由实线表示。传播长度表示能量衰减到原来的1/e强度时通过的长度，使用公式
Figure PCTCN2021128981-appb-000001
可见硅层的作用不仅仅是减小了损耗，同样也提高了耦合效率。
图7中表现出45纳米厚硅层比95纳米硅层时波导拥有更好的传导效果(上图)，端头散射时45纳米硅层波导明显优于95纳米硅层波导，而45纳米时模式分布更加局域在上部空气中，而95纳米时很多分布在衬底之中，这将导致泄露模式将大量能量散失在衬底中，造成非常大的损耗。
本实施例中，由于结构的设计，使得不需要油等介质匹配也能达到很好的等离激元在衬底上的传导效果，并且传导效果可以被衬底调制。使得他非常适合在等离激元光子芯片等领域进行一些光开关等光子芯片的制作和应用。
以上所述是本发明的优选实施方式而已，当然不能以此来限定本发明之权利范围，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和变动，这些改进和变动也视为本发明的保护范围。

Claims (10)

  1. 一种片上亚波长束缚光波导，其特征在于，包括衬底和金属纳米结构，所述衬底和金属纳米结构之间设置有高折射率介质层，所述高折射率介质层材料的折射率高于衬底。
  2. 根据权利要求1所述的片上亚波长束缚光波导，其特征在于，所述金属纳米结构的截面为矩形结构，厚度50至250纳米，宽度为50至500纳米。
  3. 根据权利要求1所述的片上亚波长束缚光波导，其特征在于，所述衬底材料为二氧化硅；所述高折射率介质层材料为硅或者氧化铝；所述金属纳米结构的材质包括金，银，铝，铜。
  4. 根据权利要求1所述的片上亚波长束缚光波导，其特征在于，所述高折射率介质层的厚度为10～500nm。
  5. 根据权利要求1所述的片上亚波长束缚光波导，其特征在于，所述高折射率介质层的厚度为光在介质中的传导波长的0.225～0.275倍。
  6. 根据权利要求1所述的片上亚波长束缚光波导，其特征在于，所述片上亚波长波导的有效折射率为1.06至1.1。
  7. 如权利要求1～6任一项所述一种片上亚波长束缚光波导的制备方法，其特征在于，包括如下步骤：
    (1)提供表面带有高折射率介质层的衬底，使高折射率介质层的表面平整；
    (2)在所述高折射率介质层上表面制作出图形模板，然后沉积金属，再剥离模板得到金属纳米结构。
  8. 根据权利要求7所述的片上亚波长束缚光波导制备方法，其特征在于，在高折射率介质层表面制作图形模板前，先在其表面自组装一层三甲氧基硅烷分子，所述三甲氧基硅烷分子层的厚度为0.7至3.5纳米。
  9. 根据权利要求7所述的片上亚波长束缚光波导制备方法，其特征在于，步骤(2)在剥离模板之前，在金属纳米结构表面沉积一层隔离层，所述隔离层的厚度为0～10nm。
  10. 根据权利要求1～6任一项所述的片上亚波长束缚光波导或者权利要求7～9任一项制备方法所得片上亚波长束缚光波导的应用，其特征在于，作为调制器，通过调整高折射率介质层的厚度来调制等离激元的传导行为。
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