WO2022119107A1

WO2022119107A1 - Display device and method for manufacturing light-emitting element

Info

Publication number: WO2022119107A1
Application number: PCT/KR2021/014137
Authority: WO
Inventors: 이소영; 김동욱; 유철종; 김세영
Original assignee: 삼성디스플레이 주식회사
Priority date: 2020-12-02
Filing date: 2021-10-13
Publication date: 2022-06-09
Also published as: TW202230818A; US20220173277A1; CN116648784A; KR20220078016A

Abstract

A display device and a manufacturing method for a light-emitting element are provided. The display device includes: a first electrode and a second electrode spaced apart from each other; and a light-emitting element arranged between the first electrode and the second electrode, wherein the light-emitting element includes a first area having a first diameter, a second area having a second diameter greater than the first diameter, a first insulating layer surrounding the first area, and a second insulating layer arranged on the first insulating layer, wherein the second insulating layer surrounds the second area exposed by the first insulating layer.

Description

Method for manufacturing a display device and a light emitting device

The present invention relates to a display device and a method of manufacturing a light emitting device.

Recently, as interest in information display has increased, research and development on display devices is continuously being made.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a light emitting device and a display device capable of minimizing surface defects of the light emitting device.

The problems of the present invention are not limited to the problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

A display device according to an exemplary embodiment includes a first electrode and a second electrode spaced apart from each other, and a light emitting device disposed between the first electrode and the second electrode, the light emitting device comprising: A first region having a first diameter, a second region having a second diameter greater than the first diameter, a first insulating film surrounding the first region, and a second insulating film disposed on the first insulating film, , the second insulating layer surrounds the second region exposed by the first insulating layer.

The light emitting device further includes a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer, the active layer comprising the It may be disposed in the first area.

The first semiconductor layer may be disposed in the first region.

The first semiconductor layer may include a p-type semiconductor layer.

The first insulating layer may directly cover the first semiconductor layer, the active layer, and the second semiconductor layer in the first region.

The second insulating layer may directly cover the second semiconductor layer in the second region exposed by the first insulating layer.

The display device may further include a first contact electrode electrically connecting the first electrode and the first semiconductor layer, and a second contact electrode electrically connecting the second electrode and the second semiconductor layer. .

The first contact electrode may be in contact with the first semiconductor layer exposed by the second insulating layer, and the second contact electrode may be in contact with the second semiconductor layer exposed by the second insulating layer.

At least one of a side surface of the first region and a side surface of the second region of the light emitting device may include an inclined portion.

A light emitting device according to an embodiment of the present invention provides a first region having a first diameter, a second region having a second diameter greater than the first diameter, a first insulating film surrounding the first region, and and a second insulating layer surrounding the second region exposed by the first insulating layer.

The light emitting device further includes a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer, wherein the active layer includes the first semiconductor layer. 1 diameter.

At least one of a side surface of the first area and a side surface of the second area may include an inclined portion.

The first insulating layer may directly cover the inclined portion of the first region.

The second insulating layer may directly cover the inclined portion of the second region.

The first insulating layer and the second insulating layer may include the same material.

The light emitting device may further include a third insulating layer disposed on the first insulating layer and the second insulating layer.

The first insulating layer and the second insulating layer may include different materials.

A method of manufacturing a light emitting device according to an embodiment for solving the above problems includes the steps of: forming a light emitting laminate on a laminate substrate; forming a first insulating layer surrounding the first area of the light emitting patterns, and forming second areas of the light emitting patterns by performing secondary etching of the light emitting patterns, wherein the second area of the light emitting patterns The diameter of is formed to be larger than the diameter of the first region.

The light emitting laminate may include a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer.

In the forming of the first region, the first semiconductor layer and the active layer may be first etched.

The first insulating layer may be directly formed on the first semiconductor layer and the active layer.

The method of manufacturing the light emitting device may further include surface-treating the first region or the second region.

The method of manufacturing the light emitting device may further include forming a second insulating layer surrounding the first region and the second region.

The method of manufacturing the light emitting device may further include removing the first insulating layer after forming the second region.

The method of manufacturing the light emitting device may further include forming a third insulating layer surrounding the first region and the second region.

The method of manufacturing the light emitting device may further include forming a fourth insulating layer on the third insulating layer.

Details of other embodiments are included in the detailed description and drawings.

According to the exemplary embodiment of the present invention, damage to the first region can be prevented in the process of etching the second region by forming the first insulating layer on the first region of the light emitting device. Accordingly, it is possible to improve the lifespan and efficiency by minimizing surface defects of the light emitting device.

Effects according to the embodiments are not limited by the contents exemplified above, and more various effects are included in the present specification.

1 and 2 are perspective and cross-sectional views illustrating a light emitting device according to an exemplary embodiment.

3 is a cross-sectional view illustrating a light emitting device according to another exemplary embodiment.

4 is a cross-sectional view illustrating a light emitting device according to another embodiment.

5 is a cross-sectional view illustrating a light emitting device according to another embodiment.

6 is a cross-sectional view illustrating a light emitting device according to another embodiment.

7 is a cross-sectional view illustrating a light emitting device according to another exemplary embodiment.

8 is a cross-sectional view illustrating a light emitting device according to another embodiment.

9 is a cross-sectional view illustrating a light emitting device according to another embodiment.

10 is a cross-sectional view illustrating a light emitting device according to another embodiment.

11 is a cross-sectional view illustrating a light emitting device according to another embodiment.

12 is a cross-sectional view illustrating a light emitting device according to another exemplary embodiment.

13 to 20 are cross-sectional views of a process step-by-step process of a method of manufacturing a light emitting device according to an exemplary embodiment.

21 to 25 are cross-sectional views of a process step-by-step process of a method of manufacturing a light emitting device according to another embodiment.

26 is a cross-sectional view illustrating a display device according to an exemplary embodiment.

Advantages and features of the present invention, and a method of achieving the same, will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various different forms. The present embodiments are provided so that the disclosure of the present invention is complete, and to fully inform those of ordinary skill in the art to which the present invention belongs, the scope of the invention, and the present invention will be defined by the scope of the claims. only

The terminology used herein is for the purpose of describing the embodiments and is not intended to limit the present invention. In this specification, the singular also includes the plural unless otherwise specified. As used herein, “comprises” and/or “comprising” refers to the presence of one or more other components, steps, acts and/or elements in the stated element, step, operation and/or element. or addition is not excluded.

In addition, "connection" or "connection" may refer to a physical and/or electrical connection or connection inclusively. It may also refer generically to a direct or indirect connection or connection and an integral or non-integral connection or connection.

Reference to an element or layer "on" of another element or layer includes any intervening layer or other element directly on or in the middle of the other element or layer. Like reference numerals refer to like elements throughout.

Although the first, second, etc. are used to describe various elements, these elements are not limited by these terms, of course. These terms are only used to distinguish one component from another. Accordingly, it goes without saying that the first component mentioned below may be the second component within the spirit of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 and 2 are perspective and cross-sectional views illustrating a light emitting device according to an exemplary embodiment. Although the columnar light emitting device LD is illustrated in FIGS. 1 and 2 , the type and/or shape of the light emitting device LD is not limited thereto.

1 and 2 , the light emitting device LD may include a first semiconductor layer 11 , an active layer 12 , and a second semiconductor layer 13 . For example, the light emitting device LD may include a first semiconductor layer 11 , an active layer 12 , and a second semiconductor layer 13 sequentially stacked in one direction.

The light emitting device LD may be formed in a pillar shape extending in one direction. The light emitting device LD may have a first end EP1 and a second end EP2 . One of the first and second semiconductor layers 11 and 13 may be disposed on the first end EP1 of the light emitting device LD. The other one of the first and second semiconductor layers 11 and 13 may be disposed at the second end EP2 of the light emitting device LD.

In some embodiments, the light emitting device LD may be a light emitting device manufactured in a pillar shape through an etching method or the like. In this specification, the columnar shape encompasses a rod-like shape with an aspect ratio greater than 1, or a bar-like shape, such as a circular column or a polygonal column, and the shape of its cross-section is limited. it is not

The light emitting device LD may have a size as small as a nanometer scale to a micrometer scale. As an example, each of the light emitting devices LD may have a diameter (or width) and/or a length ranging from a nanometer scale to a micrometer scale. However, the size of the light emitting device LD is not limited thereto, and the size of the light emitting device LD may vary depending on design conditions of various devices using a light emitting device using the light emitting device LD as a light source, for example, a display device. It can be variously changed.

The first semiconductor layer 11 may be a semiconductor layer of the first conductivity type. For example, the first semiconductor layer 11 may include a p-type semiconductor layer. For example, the first semiconductor layer 11 includes at least one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor layer doped with a first conductivity type dopant such as Mg. can However, the material constituting the first semiconductor layer 11 is not limited thereto, and various materials other than this may constitute the first semiconductor layer 11 .

The active layer 12 is disposed between the first semiconductor layer 11 and the second semiconductor layer 13 and may be formed in a single-quantum well or multi-quantum well structure. . The position of the active layer 12 may be variously changed according to the type of the light emitting device LD. A cladding layer (not shown) doped with a conductive dopant may be formed on the upper and/or lower portions of the active layer 12 . For example, the cladding layer may be formed of AlGaN or InAlGaN. According to an embodiment, a material such as AlGaN or InAlGaN may be used to form the active layer 12 , and in addition to this, various materials may constitute the active layer 12 .

The second semiconductor layer 13 is disposed on the active layer 12 , and may include a semiconductor layer of a different type from that of the first semiconductor layer 11 . The second semiconductor layer 13 may include an n-type semiconductor layer. For example, the second semiconductor layer 13 includes a semiconductor material of any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and is an n-type semiconductor doped with a second conductivity type dopant such as Si, Ge, Sn, etc. layers may be included. However, the material constituting the second semiconductor layer 13 is not limited thereto, and in addition, the second semiconductor layer 13 may be formed of various materials.

When a voltage equal to or greater than the threshold voltage is applied to both ends of the light emitting device LD, the light emitting device LD emits light while electron-hole pairs are combined in the active layer 12 . By controlling the light emission of the light emitting device LD using this principle, the light emitting device LD can be used as a light source of various light emitting devices including pixels of a display device.

The light emitting device LD may include a first area A1 and a second area A2 having different diameters. In an embodiment, the first area A1 may have a first diameter D1 , and the second area A2 may have a second diameter D2 greater than the first diameter D1 . Here, each diameter D1 and D2 may mean an average diameter of each area A1 and A2. The difference in diameter between the first area A1 and the second area A2 may be caused by sequentially etching the respective areas A1 and A2 in the process of manufacturing the light emitting device LD. A detailed description thereof will be described later with reference to FIGS. 13 to 20 .

A first semiconductor layer 11 and/or an active layer 12 may be disposed in the first area A1 . A second semiconductor layer 13 may be disposed in the second area A2 . That is, the first semiconductor layer 11 may have a first diameter D1 , the active layer 12 may have a first diameter D1 , and the second semiconductor layer 13 may have a second diameter D2 . have. Also, the area of the first semiconductor layer 11 at the first end EP1 may be smaller than the area of the second semiconductor layer 13 at the second end EP2 . In some embodiments, a portion of the second semiconductor layer 13 may be further disposed in the first area A1 . In this case, the second semiconductor layer 13 of the first region A1 has a first diameter D1 , and the second semiconductor layer 13 of the second region A2 has a second diameter D2 . can However, the present invention is not necessarily limited thereto, and the relative positions of the first semiconductor layer 11 , the active layer 12 , and/or the second semiconductor layer 13 may be variously changed.

The light emitting device LD may further include a first insulating layer INF1 and a second insulating layer INF2 formed on the surface. The first insulating layer INF1 may be partially formed only in the first area A1 . For example, the first insulating layer INF1 may be formed to surround the first area A1 . The first insulating layer INF1 may be directly disposed on the surface of the first semiconductor layer 11 , the active layer 12 , and/or the second semiconductor layer 13 of the first region A1 . The first insulating layer INF1 may expose the first and second ends EP1 and EP2 of the light emitting device LD having different polarities. The first insulating layer INF1 may include aluminum oxide (AlOx), aluminum nitride (AlNx), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), zirconium oxide (ZrOx), hafnium oxide (HfOx), and at least one of titanium oxide (TiOx). When the first insulating layer INF1 is formed on the first area A1 , it is possible to prevent damage to the active layer 12 of the first area A1 and the like in the process of etching the second area A2 . Lifespan and efficiency may be improved by minimizing surface defects of the light emitting device LD.

A second insulating layer INF2 may be disposed on the first insulating layer INF1 . The second insulating layer INF2 may be disposed to surround the first insulating layer INF1 . The second insulating layer INF2 may be directly disposed on the surface of the first insulating layer INF1 . Also, the second insulating layer INF2 may be formed to surround the second area A2 exposed by the first insulating layer INF1 . The second insulating layer INF2 may be directly disposed on the surface of the second semiconductor layer 13 of the second area A2 exposed by the first insulating layer INF1 . The second insulating layer INF2 may expose the first and second ends EP1 and EP2 of the light emitting device LD having different polarities.

In an embodiment, the second insulating layer INF2 may include the same material as the above-described first insulating layer INF1 . For example, the second insulating layer INF2 may include aluminum oxide (AlOx), aluminum nitride (AlNx), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), zirconium oxide (ZrOx), and hafnium oxide. It may include at least one of (HfOx) and titanium oxide (TiOx). When the first insulating layer INF1 and the second insulating layer INF2 are made of the same material, insulating layers INF1 and INF2 having different thicknesses may be formed in the first area A1 and the second area A2 . For example, the thickness of the insulating layers INF1 and INF2 of the first area A1 may be greater than the thickness of the insulating layer INF2 of the second area A2 .

In another embodiment, the second insulating layer INF2 may include a material different from that of the first insulating layer INF1 . When the first insulating layer INF1 and the second insulating layer INF2 are made of different materials, a double insulating layer may be formed in the first region A1 and a single insulating layer may be formed in the second region A2 . When the second insulating layer INF2 is formed on the first insulating layer INF1 , the active layer 12 includes at least one electrode (eg, at least one of the contact electrodes connected to both ends of the light emitting device LD). contact electrode) and the like can be prevented from being short-circuited. Accordingly, electrical stability of the light emitting device LD may be secured.

In some embodiments, the light emitting device LD further includes additional components in addition to the first semiconductor layer 11 , the active layer 12 , the second semiconductor layer 13 , and/or the insulating layers INF1 and INF2 surrounding them. can do. For example, an electrode layer may be further disposed on the first and second ends EP1 and EP2 of the light emitting device LD, respectively. The electrode layer may include a transparent metal or a transparent metal oxide. For example, the electrode layer may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and zinc tin oxide (ZTO), but is not limited thereto.

Meanwhile, although the columnar light emitting device LD is illustrated in FIGS. 1 and 2 , the type, structure, and/or shape of the light emitting device LD may be variously changed. For example, the light emitting device LD may have a core-shell structure having a polygonal pyramid shape.

The light emitting device including the above-described light emitting device LD may be used in various types of devices requiring a light source, including a display device. For example, a plurality of light emitting devices LD may be disposed in each pixel of the display panel, and the light emitting devices LD may be used as a light source of each pixel. However, the field of application of the light emitting device LD is not limited to the above-described example. For example, the light emitting device LD may be used in other types of devices that require a light source, such as a lighting device.

Hereinafter, another embodiment will be described. In the following embodiments, the same components as those already described are referred to by the same reference numerals, and duplicate descriptions will be omitted or simplified.

Referring to FIG. 3 , the light emitting device LD according to the present exemplary embodiment is distinguished from the exemplary embodiment of FIGS. 1 and 2 in that the side surface of the first area A1 includes the inclined portion I1 . For example, a side surface of the first semiconductor layer 11 and/or the active layer 12 of the first region A1 may include an inclined portion I1 . In some embodiments, a side surface of the second semiconductor layer 13 of the first region A1 may include an inclined portion I1 . As the side surface of the first area A1 includes the inclined portion I1 having a predetermined inclination, the first area A1 has a shape in which the first diameter D1 decreases toward the first end EP1. can have As such, when the side surface of the first area A1 includes the inclined portion I1 , the first end EP1 and the second end EP2 are formed through the inclined portion I1 of the first area A1 . Since they can be easily identified, it is possible to determine whether or not the light emitting devices LD are aligned by deflection by using an optical inspector. For the first semiconductor layer 11 , the active layer 12 , the second semiconductor layer 13 , the first insulating layer INF1 , and the second insulating layer INF2 of the light emitting device LD, see FIGS. 1 and 2 . Since it has been described above, overlapping contents are omitted.

Referring to FIG. 4 , the light emitting device LD according to the present exemplary embodiment is distinguished from the exemplary embodiments of FIGS. 1 and 2 in that the side surface of the second area A2 includes the inclined portion I2 . For example, a side surface of the second semiconductor layer 13 of the second region A2 may include an inclined portion I2 . As the side surface of the second area A2 includes the inclined portion I2 having a predetermined inclination, the second area A2 has a shape in which the second diameter D2 increases toward the second end EP2. can have As such, when the side surface of the second area A2 includes the inclined portion I2 , the first end EP1 and the second end EP2 are formed through the inclined portion I2 of the second area A2 . Since they can be easily identified, it is possible to determine whether or not the light emitting devices LD are aligned by deflection by using an optical inspector.

Referring to FIG. 5 , the light emitting device LD according to the present exemplary embodiment includes a third insulating layer INF3 and a fourth insulating layer INF4 surrounding the first area A1 and the second area A2 . is distinguished from the embodiment of FIGS. 1 and 2 in FIG. The third insulating layer INF3 may be formed to surround the first area A1 and the second area A2 . The third insulating layer INF3 is disposed directly on the surface of the first semiconductor layer 11 , the active layer 12 , and/or the second semiconductor layer 13 of the first region A1 and the second region A2 . can be The third insulating layer INF3 may expose the first and second ends EP1 and EP2 of the light emitting device LD having different polarities. The third insulating layer INF3 may include aluminum oxide (AlOx), aluminum nitride (AlNx), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), zirconium oxide (ZrOx), hafnium oxide (HfOx), and at least one of titanium oxide (TiOx).

A fourth insulating layer INF4 may be disposed on the third insulating layer INF3 . The fourth insulating layer INF4 may be disposed to surround the third insulating layer INF3 . The fourth insulating layer INF4 may be directly disposed on the surface of the third insulating layer INF3 . The fourth insulating layer INF4 may expose the first and second ends EP1 and EP2 of the light emitting device LD having different polarities. The fourth insulating layer INF4 may include the same material as the above-described third insulating layer INF3 . For example, the fourth insulating layer INF4 may include aluminum oxide (AlOx), aluminum nitride (AlNx), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), zirconium oxide (ZrOx), and hafnium oxide. It may include at least one of (HfOx) and titanium oxide (TiOx). However, the present invention is not limited thereto, and the fourth insulating layer INF4 may include a material different from that of the third insulating layer INF3 .

Meanwhile, a difference in inner diameters of the third insulating layer INF3 and the fourth insulating layer INF4 may occur in each of the regions A1 and A2 due to a difference in diameter between the first area A1 and the second area A2 . For example, the inner diameter of the third insulating layer INF3 of the first area A1 may be smaller than the inner diameter of the third insulating layer INF3 of the second area A2 . Similarly, the inner diameter of the fourth insulating layer INF4 of the first area A1 may be smaller than the inner diameter of the fourth insulating layer INF4 of the second area A2 .

Referring to FIG. 6 , the light emitting device LD according to the present exemplary embodiment includes a first insulating layer INF1 and a second insulating layer INF2 respectively surrounding the first area A1 and the second area A2 . It is distinguished from the embodiment of FIGS. 1 and 2 in that respect.

The first insulating layer INF1 may be directly disposed on the surface of the first semiconductor layer 11 , the active layer 12 , and/or the second semiconductor layer 13 of the first region A1 . The first insulating layer INF1 may include aluminum oxide (AlOx), aluminum nitride (AlNx), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), zirconium oxide (ZrOx), hafnium oxide (HfOx), and at least one of titanium oxide (TiOx).

The second insulating layer INF2 may be directly disposed on the surface of the second semiconductor layer 13 of the second area A2 . The second insulating layer INF2 may include aluminum oxide (AlOx), aluminum nitride (AlNx), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), zirconium oxide (ZrOx), hafnium oxide (HfOx), and at least one of titanium oxide (TiOx). In some embodiments, the second insulating layer INF2 may include the same material as the first insulating layer INF1 . In this case, the first insulating layer INF1 and the second insulating layer INF2 may be simultaneously formed in the same process, but are not limited thereto.

A third insulating layer INF3 may be disposed on the first insulating layer INF1 and the second insulating layer INF2 . The third insulating layer INF3 may be disposed to surround the first insulating layer INF1 and the second insulating layer INF2 . The third insulating layer INF3 may be directly disposed on the surfaces of the first insulating layer INF1 and the second insulating layer INF2 . The third insulating layer INF3 may expose the first and second ends EP1 and EP2 of the light emitting device LD having different polarities. The third insulating layer INF3 may include aluminum oxide (AlOx), aluminum nitride (AlNx), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), zirconium oxide (ZrOx), hafnium oxide (HfOx), and at least one of titanium oxide (TiOx).

Referring to FIG. 7 , the light emitting device LD according to the present embodiment is distinguished from the embodiments of FIGS. 1 and 2 in that the second insulating layer INF2 is omitted. As the second insulating layer INF2 is omitted, not only the second end EP2 of the light emitting device LD but also the side surface of the second area A2 may be exposed. That is, the side surface of the second semiconductor layer 13 of the second area A2 may be exposed. Accordingly, it is possible to stably connect the second semiconductor layer 13 and a second contact electrode (CNE2 of FIG. 26 ) to be described later.

Referring to FIG. 8 , in the light emitting device LD according to the present exemplary embodiment, the second semiconductor layer 13 is disposed at the first end EP1 , and the first semiconductor layer 11 is disposed at the second end EP2 . It is distinguished from the embodiment of FIGS. 1 and 2 in that it is arranged.

Specifically, the second semiconductor layer 13 may be disposed in the first area A1 . A first semiconductor layer 11 and/or an active layer 12 may be disposed in the second area A2 . That is, the first semiconductor layer 11 may have a second diameter D2 , the active layer 12 may have a second diameter D2 , and the second semiconductor layer 13 may have a first diameter D1 . have. Also, the area of the second semiconductor layer 13 at the first end EP1 may be smaller than the area of the first semiconductor layer 11 at the second end EP2 . In some embodiments, a portion of the second semiconductor layer 13 may be further disposed in the second area A2 . In this case, the second semiconductor layer 13 of the first region A1 has a first diameter D1 , and the second semiconductor layer 13 of the second region A2 has a second diameter D2 . can However, the present invention is not necessarily limited thereto, and the relative positions of the first semiconductor layer 11 , the active layer 12 , and/or the second semiconductor layer 13 may be variously changed.

Referring to FIG. 9 , the light emitting device LD according to the present exemplary embodiment is distinguished from the exemplary embodiment of FIG. 8 in that the side surface of the first area A1 includes the inclined portion I1 . For example, a side surface of the second semiconductor layer 13 of the first region A1 may include an inclined portion I1 . As the side surface of the first area A1 includes the inclined portion I1 having a predetermined inclination, the first area A1 has a shape in which the first diameter D1 decreases toward the first end EP1. can have As such, when the side surface of the first area A1 includes the inclined portion I1 , the first end EP1 and the second end EP2 are formed through the inclined portion I1 of the first area A1 . Since they can be easily identified, it is possible to determine whether or not the light emitting devices LD are aligned by deflection by using an optical inspector.

Referring to FIG. 10 , the light emitting device LD according to the present exemplary embodiment is distinguished from the exemplary embodiment of FIG. 8 in that the side surface of the second area A2 includes the inclined portion I2 . For example, a side surface of the first semiconductor layer 11 and/or the active layer 12 of the second region A2 may include the inclined portion I2 . In some embodiments, a side surface of the second semiconductor layer 13 of the second region A2 may include an inclined portion I2 . As the side surface of the second area A2 includes the inclined portion I2 having a predetermined inclination, the second area A2 has a shape in which the second diameter D2 increases toward the second end EP2. can have As such, when the side surface of the second area A2 includes the inclined portion I2 , the first end EP1 and the second end EP2 are formed through the inclined portion I2 of the second area A2 . Since they can be easily identified, it is possible to determine whether or not the light emitting devices LD are aligned by deflection by using an optical inspector.

Referring to FIG. 11 , the light emitting device LD according to the present exemplary embodiment includes a third insulating layer INF3 and a fourth insulating layer INF4 surrounding the first area A1 and the second area A2 . is distinguished from the embodiment of FIG. 8 . The third insulating layer INF3 may be formed to surround the first area A1 and the second area A2 . The third insulating layer INF3 is disposed directly on the surface of the first semiconductor layer 11 , the active layer 12 , and/or the second semiconductor layer 13 of the first region A1 and the second region A2 . can be The third insulating layer INF3 may expose the first and second ends EP1 and EP2 of the light emitting device LD having different polarities. The third insulating layer INF3 may include aluminum oxide (AlOx), aluminum nitride (AlNx), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), zirconium oxide (ZrOx), hafnium oxide (HfOx), and at least one of titanium oxide (TiOx).

Referring to FIG. 12 , the light emitting device LD according to the present exemplary embodiment includes a first insulating layer INF1 and a second insulating layer INF2 respectively surrounding the first area A1 and the second area A2 . It is distinguished from the embodiment of FIG. 8 in this respect.

The first insulating layer INF1 may be directly disposed on the surface of the second semiconductor layer 13 of the first area A1 . The first insulating layer INF1 may include aluminum oxide (AlOx), aluminum nitride (AlNx), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), zirconium oxide (ZrOx), hafnium oxide (HfOx), and at least one of titanium oxide (TiOx).

The second insulating layer INF2 may be directly disposed on the surface of the first semiconductor layer 11 , the active layer 12 , and/or the second semiconductor layer 13 of the second region A2 . The second insulating layer INF2 may include aluminum oxide (AlOx), aluminum nitride (AlNx), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), zirconium oxide (ZrOx), hafnium oxide (HfOx), and at least one of titanium oxide (TiOx). In some embodiments, the second insulating layer INF2 may include the same material as the first insulating layer INF1 . In this case, the first insulating layer INF1 and the second insulating layer INF2 may be simultaneously formed in the same process, but are not limited thereto.

Subsequently, a method of manufacturing the light emitting device according to the above-described embodiments will be described.

13 to 20 are cross-sectional views of a process step-by-step process of a method of manufacturing a light emitting device according to an exemplary embodiment. Hereinafter, components substantially identical to those of FIGS. 1 to 11 are denoted by the same reference numerals and detailed reference numerals are omitted.

Referring to FIG. 13 , the light emitting laminates LDs are formed on the laminate substrate 1 .

The laminate substrate 1 may include a sapphire substrate and a transparent substrate such as glass. However, the present invention is not limited thereto, and may be formed of a conductive substrate such as GaN, SiC, ZnO, Si, GaP, and GaAs. Hereinafter, the case where the laminated substrate 1 is a sapphire substrate is illustrated and described.

The light emitting stacks LDs may be formed by growing a seed crystal by an epitaxial method. In some embodiments, the light emitting laminates (LDs) may be formed by electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), or dual thermal deposition. It may be formed by dual-type thermal evaporation, sputtering, or metal organic chemical vapor deposition (MOCVD), preferably by metal-organic chemical vapor deposition (MOCVD). may be formed, but is not necessarily limited thereto.

A precursor material for forming the light emitting laminates (LDs) is not particularly limited within a range that can be generally selected for forming a target material. For example, the precursor material may be a metal precursor including an alkyl group such as a methyl group or an ethyl group. For example, it may be a compound such as trimethyl gallium (Ga(CH ₃ ) ₃ ), trimethyl aluminum (Al(CH ₃ ) ₃ ), triethyl phosphate ((C ₂ H ₅ ) ₃ PO ₄ ), but not necessarily limited thereto it's not going to be The light emitting stack LDs may include a first semiconductor layer 11 , an active layer 12 , and a second semiconductor layer 13 . 13 illustrates a case in which the second semiconductor layer 13 is first formed on the laminate substrate 1 , and then the active layer 12 and the first semiconductor layer 11 are sequentially formed, but the present invention is not limited thereto. . According to an embodiment, the first semiconductor layer 11 is first formed on the laminate substrate 1 , and then the active layer 12 and the second semiconductor layer 13 are sequentially formed, as shown in FIGS. 8 to 11 . Light emitting devices LD may be manufactured.

Although not shown separately, a buffer layer and/or a sacrificial layer may be further disposed between the multilayer substrate 1 and the second semiconductor layer 13 . The buffer layer may serve to reduce a lattice constant difference between the multilayer substrate 1 and the second semiconductor layer 13 . For example, the buffer layer may include an undoped semiconductor, and may include substantially the same material as the second semiconductor layer 13 , but may be a material that is not doped with n-type or p-type. In an exemplary embodiment, the buffer layer may be at least one of undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, but is not limited thereto. The sacrificial layer may include a material capable of smoothly growing crystals of the semiconductor layer in a subsequent process. The sacrificial layer may include at least one of an insulating material and a conductive material. For example, the sacrificial layer may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), etc. as an insulating material, and as a conductive material, ITO, IZO, IGO, ZnO, graphene, graphene It may include a fin oxide (graphene oxide) and the like, but is not necessarily limited thereto.

Referring to FIG. 14 , the first area A1 of the light emitting patterns LDp is formed by first etching the light emitting stack LDs. The first semiconductor layer 11 and the active layer 12 of the emission patterns LDp may be etched by the primary etching. In some embodiments, the second semiconductor layer 13 of the emission patterns LDp may be partially etched by the primary etching. The process of primary etching the light emitting stack (LDs) may be performed by a conventional method. For example, the etching process may be a dry etching method, a wet etching method, reactive ion etching (RIE), inductively coupled plasma reactive ion etching (ICP-RIE), or the like. In an embodiment, when the first area A1 of the light emitting patterns LDp is formed through dry etching, an inclined portion I1 may be formed on a side surface of the first area A1 . That is, the inclined portion I1 may be formed on a side surface of the first semiconductor layer 11 and/or the active layer 12 in the first region A1 . In some embodiments, when the second semiconductor layer 13 is partially etched by the primary etching, the inclined portion I1 may also be formed on the side surface of the second semiconductor layer 13 of the first region A1. have. Since the other inclined portions I1 have been described with reference to FIG. 3 and the like, overlapping contents will be omitted.

Referring to FIG. 15 , the inclined portion I1 of the first area A1 is removed by surface treatment of the first area A1 of the emission patterns LDp. The surface treatment may be performed using an alkaline aqueous solution. For example, the surface treatment may include at least one of potassium hydroxide (KOH), sodium hydroxide (NaOH), tetramethyl ammonium hydroxide (TMAH), and hydrazine (N ₂ H ₄ ). However, it is not necessarily limited thereto. In some embodiments, the surface treatment step may be omitted. As shown in FIGS. 3 and 9 , in the light emitting device LD manufactured by omitting the surface treatment step, the side surface of the first area A1 may include an inclined portion I1 .

Referring to FIG. 16 , a first insulating layer INF1 is formed on the first area A1 of the emission patterns LDp. The first insulating layer INF1 may be partially formed only in the first area A1 exposed by the primary etching. For example, the first insulating layer INF1 may be formed to surround the first area A1 . The first insulating layer INF1 may be directly disposed on the surface of the first semiconductor layer 11 , the active layer 12 , and/or the second semiconductor layer 13 of the first region A1 . The first insulating layer INF1 may include aluminum oxide (AlOx), aluminum nitride (AlNx), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), zirconium oxide (ZrOx), hafnium oxide (HfOx), and titanium oxide (TiOx). The first insulating layer INF1 may be formed on the first area A1 to prevent damage to the first area A1, particularly, the active layer 12 of the first area A1 in a subsequent process.

Referring to FIG. 17 , a second area A2 of the emission patterns LDp is formed by performing secondary etching of the emission patterns LDp. The second semiconductor layer 13 of the emission patterns LDp may be etched by the secondary etching. During the secondary etching of the second semiconductor layer 13 , the first region A1 may be protected by the first insulating layer INF1 , thereby minimizing surface defects of the light emitting device LD to improve lifespan and efficiency. It can be done as described above.

In an embodiment, the diameter of the second area A2 may be larger than the diameter of the first area A1 . The process of secondary etching the emission patterns LDp may be performed by a conventional method. For example, the etching process may be a dry etching method, a wet etching method, reactive ion etching (RIE), inductively coupled plasma reactive ion etching (ICP-RIE), or the like. In an embodiment, when the second area A2 of the light emitting patterns LDp is formed through dry etching, an inclined portion I2 may be formed on a side surface of the second area A2 . That is, the inclined portion I2 may be formed on a side surface of the second semiconductor layer 13 in the second region A2 . Since the other inclined portions I2 have been described with reference to FIGS. 4 and 10 , overlapping contents will be omitted.

Referring to FIG. 18 , the second area A2 of the emission patterns LDp is then surface-treated to remove the inclined portion I2 of the second area A2 . The surface treatment may be performed using an alkaline aqueous solution. For example, the surface treatment may include at least one of potassium hydroxide (KOH), sodium hydroxide (NaOH), tetramethyl ammonium hydroxide (TMAH), and hydrazine (N ₂ H ₄ ). However, it is not necessarily limited thereto. In some embodiments, the surface treatment step may be omitted. As shown in FIGS. 4 and 10 , in the light emitting device LD manufactured by omitting the surface treatment step, a side surface of the second area A2 may include an inclined portion I2 .

Referring to FIG. 19 , a second insulating layer INF2 is formed on the first area A1 and the second area A2 of the emission patterns LDp. The second insulating layer INF2 may be formed to surround the first insulating layer INF1 . The second insulating layer INF2 may be directly formed on the surface of the first insulating layer INF1 . Also, the second insulating layer INF2 may be formed to surround the second area A2 exposed by the first insulating layer INF1 . The second insulating layer INF2 may be directly formed on the surface of the second semiconductor layer 13 of the second area A2 exposed by the first insulating layer INF1 . The second insulating layer INF2 may be formed of the same material as the above-described first insulating layer INF1 . For example, the second insulating layer INF2 may include aluminum oxide (AlOx), aluminum nitride (AlNx), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), zirconium oxide (ZrOx), and hafnium oxide. It may be formed of at least one of (HfOx) and titanium oxide (TiOx). However, the present invention is not limited thereto, and the second insulating layer INF2 may be formed of a material different from that of the first insulating layer INF1 . In some embodiments, the step of forming the second insulating layer INF2 may be omitted. As illustrated in FIG. 7 , in the light emitting device LD manufactured by omitting the step of forming the second insulating layer INF2 , the side surface of the second semiconductor layer 13 of the second area A2 may be exposed. .

Referring to FIG. 20 , the light emitting devices LDs illustrated in FIGS. 1 and 2 may be manufactured by separating the plurality of light emitting patterns LDp from the laminate substrate 1 . According to the method of manufacturing the light emitting device LD according to the above-described embodiment, the process of secondary etching the second region A2 by forming the first insulating layer INF1 on the first etched first region A1 As described above, it is possible to prevent the first area A1 from being damaged in the light emitting device LD, thereby minimizing surface defects of the light emitting device LD, thereby improving the lifespan and efficiency.

Next, another embodiment will be described. In the following embodiments, the same components as those already described are referred to by the same reference numerals, and duplicate descriptions will be omitted or simplified.

21 to 25 are cross-sectional views of a process step-by-step process of a method of manufacturing a light emitting device according to another embodiment. 21 to 25 are cross-sectional views for explaining the method of manufacturing the light emitting device LD of FIGS. 5 and 11 . Components substantially identical to those of FIGS. 5 and 11 are denoted by the same reference numerals and detailed reference numerals are omitted.

Referring to FIG. 21 , the first insulating layer INF1 is formed on the first etched area A1 , and the second area A2 of the light emitting patterns LDp is formed through the secondary etching. Since the detailed manufacturing process for this has been described with reference to FIGS. 13 to 18 , overlapping content will be omitted.

Referring to FIG. 22 , the first insulating layer INF1 of the first area A1 of the emission patterns LDp is removed. As the first insulating layer INF1 is removed, a side surface of the first area A1 may be exposed. For example, side surfaces of the first semiconductor layer 11 and the active layer 12 of the first region A1 may be exposed. According to an embodiment, when the second semiconductor layer 13 is further disposed in the first area A1 , the second semiconductor layer 13 of the first area A1 is removed as the first insulating layer INF1 is removed. The sides may also be exposed.

Referring to FIG. 23 , a third insulating layer INF3 is then formed on the first area A1 and the second area A2 of the emission patterns LDp. The third insulating layer INF3 may be formed to surround the first area A1 and the second area A2 . The third insulating layer INF3 may be directly formed on the surfaces of the first area A1 and the second area A2 . For example, the third insulating layer INF3 is formed on the surfaces of the first semiconductor layer 11 , the active layer 12 , and the second semiconductor layer 13 in the first region A1 and the second region A2 . can be formed directly. The third insulating layer IN3 may include aluminum oxide (AlOx), aluminum nitride (AlNx), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), zirconium oxide (ZrOx), hafnium oxide (HfOx), and titanium oxide (TiOx), but is not necessarily limited thereto.

Referring to FIG. 24 , a fourth insulating layer INF4 is formed on the third insulating layer INF3 . The fourth insulating layer INF4 may be formed to surround the third insulating layer INF3 . The fourth insulating layer INF4 may be directly formed on the surface of the third insulating layer INF3 . The fourth insulating layer INF4 may be formed of the same material as the above-described third insulating layer INF3 . For example, the fourth insulating layer INF4 may include aluminum oxide (AlOx), aluminum nitride (AlNx), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), zirconium oxide (ZrOx), and hafnium oxide. It may be formed of at least one of (HfOx) and titanium oxide (TiOx). However, the present invention is not limited thereto, and the fourth insulating layer INF4 may be formed of a material different from that of the third insulating layer INF3 .

Referring to FIG. 25 , the light emitting devices LDs illustrated in FIGS. 5 and 11 may be manufactured by separating the plurality of light emitting patterns LDp from the laminate substrate 1 . According to the method of manufacturing the light emitting device LD according to the above-described embodiment, the process of secondary etching the second region A2 by forming the first insulating layer INF1 on the first etched first region A1 As described above, it is possible to prevent the first area A1 from being damaged in the light emitting device LD, and thus the lifespan and efficiency of the light emitting device LD can be improved.

Subsequently, a display device including the light emitting device according to the above-described embodiments will be described.

26 is a cross-sectional view illustrating a display device according to an exemplary embodiment. 26 is a cross-sectional view illustrating a display device including the light emitting device LD described with reference to FIGS. 1 to 25 , and in particular, a pixel PXL included in the display device will be mainly shown. 26 schematically shows the structure of each pixel PXL centered on one light emitting element LD, and shows a transistor T connected to the first electrode ELT1 among various circuit elements. . Meanwhile, the structure and/or the position of each layer of the transistor T is not limited to the embodiment illustrated in FIG. 26 , and may be variously changed according to the embodiment.

Referring to FIG. 26 , a pixel PXL and a display device including the same include a substrate SUB, a transistor T, first and second electrodes ELT1 and ELT2 , light emitting devices LD, and first and second contact electrodes CNE1 and CNE2.

The substrate SUB constitutes the base member and may be a rigid or flexible substrate or film. For example, the substrate SUB may be a rigid substrate made of glass or tempered glass, a flexible substrate (or thin film) made of plastic or metal, or at least one insulating layer. The material and/or physical properties of the substrate SUB are not particularly limited. In an embodiment, the substrate SUB may be substantially transparent. Here, the term "substantially transparent" may mean that light can be transmitted with a predetermined transmittance or higher. In another embodiment, the substrate SUB may be translucent or opaque. Also, the substrate SUB may include a reflective material according to an embodiment.

A buffer layer BFL may be disposed on the substrate SUB. The buffer layer BFL may prevent impurities from diffusing into each circuit element. The buffer layer BFL may be composed of a single layer, but may also be composed of at least two or more multi-layers. When the buffer layer BFL is formed of multiple layers, each layer may be formed of the same material or may be formed of different materials. Various circuit elements such as transistors T and various wirings connected to the circuit elements may be disposed on the buffer layer BFL. The buffer layer BFL may be omitted in some embodiments.

The transistor T may include a semiconductor pattern SCP, a gate electrode GE, and first and second transistor electrodes TE1 and TE2, respectively. Meanwhile, although FIG. 26 illustrates an embodiment in which the transistor T includes the first and second transistor electrodes TE1 and TE2 formed separately from the semiconductor pattern SCP, the present invention is not limited thereto. For example, in another embodiment, the first and/or second transistor electrodes TE1 and TE2 provided in the at least one transistor T may be integrated with each semiconductor pattern SCP.

The semiconductor pattern SCP may be disposed on the buffer layer BFL. For example, the semiconductor pattern SCP may be disposed between the substrate SUB on which the buffer layer BFL is formed and the gate insulating layer GI. The semiconductor pattern SCP is positioned in a first region in contact with each of the first transistor electrodes TE1 , a second region in contact with each of the second transistor electrodes TE2 , and between the first and second regions. It may include a defined channel region. According to an embodiment, one of the first and second regions may be a source region and the other may be a drain region.

In some embodiments, the semiconductor pattern SCP may be a semiconductor pattern made of polysilicon, amorphous silicon, oxide semiconductor, or the like. In addition, the channel region of the semiconductor pattern SCP may be an intrinsic semiconductor pattern as a semiconductor pattern not doped with impurities, and the first and second regions of the semiconductor pattern SCP may be semiconductor patterns doped with a predetermined impurity, respectively. .

The gate insulating layer GI may be disposed on the semiconductor pattern SCP. For example, the gate insulating layer GI may be disposed between the semiconductor pattern SCP and the gate electrode GE. The gate insulating layer (GI) may be composed of a single layer or multiple layers, and may include various types of organic/inorganic insulating materials including silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy). can

The gate electrode GE may be disposed on the gate insulating layer GI. For example, the gate electrode GE may be disposed to overlap the semiconductor pattern SCP with the gate insulating layer GI interposed therebetween.

The first interlayer insulating layer ILD1 may be disposed on the gate electrode GE. For example, the first interlayer insulating layer ILD1 may be disposed between the gate electrode GE and the first and second transistor electrodes TE1 and TE2 . The first interlayer insulating layer ILD1 may be configured as a single layer or multiple layers, and may include at least one inorganic insulating material and/or an organic insulating material. For example, the first interlayer insulating layer ILD1 may include various types of organic/inorganic insulating materials including silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy). The constituent material of the interlayer insulating layer ILD1 is not particularly limited.

The first and second transistor electrodes TE1 and TE2 may be disposed on each semiconductor pattern SCP with at least one first interlayer insulating layer ILD1 interposed therebetween. For example, the first and second transistor electrodes TE1 and TE2 have the gate insulating layer GI and the first interlayer insulating layer ILD1 interposed therebetween, and are disposed on different ends of the semiconductor pattern SCP. can be formed in The first and second transistor electrodes TE1 and TE2 may be electrically connected to each semiconductor pattern SCP. For example, the first and second transistor electrodes TE1 and TE2 may be connected to the first of the semiconductor pattern SCP through contact holes penetrating the gate insulating layer GI and the first interlayer insulating layer ILD1 . and the second regions. According to an embodiment, one of the first and second transistor electrodes TE1 and TE2 may be a source electrode, and the other may be a drain electrode.

The transistor T may be connected to at least one pixel electrode. For example, the transistor T may have a first electrode of the corresponding pixel PXL through a contact hole (eg, the first contact hole CH1 ) passing through the passivation layer PSV and/or the bridge pattern BRP. (ELT1) may be electrically connected.

The power wiring PL2 may be formed of the same layer as the gate electrode GE of the transistors T or the first and second transistor electrodes TE1 and TE2 , or may be formed of a different layer. For example, the power wiring PL2 may be disposed on the second interlayer insulating layer ILD2 and may be at least partially covered by the passivation layer PSV. The power line PL2 may be electrically connected to the second electrode ELT2 disposed on the passivation layer PSV through the second contact hole CH2 passing through the passivation layer PSV. However, the position and/or structure of the power wiring PL2 may be variously changed.

The second interlayer insulating layer ILD2 is disposed on the first interlayer insulating layer ILD1 and may cover the first and second transistor electrodes TE1 and TE2 disposed on the first interlayer insulating layer ILD1 . can The second interlayer insulating layer ILD2 may be configured as a single layer or multiple layers, and may include at least one inorganic insulating material and/or an organic insulating material. For example, the second interlayer insulating layer ILD2 may include various types of organic/inorganic insulating materials including silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy). However, the present invention is not limited thereto.

A bridge pattern BRP and a power wiring PL2 for electrically connecting the transistor T and the first electrode ELT1 may be formed on the second interlayer insulating layer ILD2 . However, the second interlayer insulating layer ILD2 may be omitted in some embodiments.

A protective layer PSV may be disposed on circuit elements including the transistors T and/or wirings including the power line PL2 . The passivation layer PSV may be configured as a single layer or multiple layers, and may include at least one inorganic insulating material and/or an organic insulating material. For example, the passivation layer PSV may include at least an organic insulating layer and serve to substantially planarize the lower step.

A bank BNK protruding in the third direction (Z-axis direction) may be disposed on the passivation layer PSV. The bank BNK may be formed in a separate or integrated pattern.

The bank BNK may have various shapes according to embodiments. In an embodiment, the bank BNK may be a bank structure having a positive taper structure. For example, the bank BNK may be formed to have an inclined surface inclined at a predetermined angle with respect to the substrate SUB as shown in FIG. 26 . However, the present invention is not necessarily limited thereto, and the bank BNK may have a curved surface or a stepped sidewall. As an example, the bank BNK may have a cross-section such as a semicircle or a semi-ellipse shape.

The electrodes and insulating layers disposed on the bank BNK may have a shape corresponding to the bank BNK. For example, the bank BNK transmits the light emitted from the light emitting devices LD together with the first and second electrodes ELT1 and ELT2 formed thereon in the front direction of the pixel PXL, that is, the third direction. (Z-axis direction) may serve as a reflective member to improve the light output efficiency of the display device.

The bank BNK may include an insulating material including at least one inorganic material and/or an organic material. For example, the bank BNK may include at least one inorganic layer including various inorganic insulating materials including silicon nitride (SiNx) or silicon oxide (SiOx). Alternatively, the bank BNK includes at least one layer of an organic layer and/or a photoresist layer including various types of organic insulating materials, or a single or multi-layered insulator including organic/inorganic materials in combination. may be configured. That is, the constituent material and/or the pattern shape of the bank BNK may be variously changed.

First and second electrodes ELT1 and ELT2 may be disposed on the bank BNK. The first and second electrodes ELT1 and ELT2 may be formed to be spaced apart from each other. The first and second electrodes ELT1 and ELT2 apply a first alignment signal (or a first alignment voltage) and a second alignment signal (or a second alignment voltage), respectively, in the alignment step of the light emitting elements LD. can be supplied. For example, one of the first and second electrodes ELT1 and ELT2 receives an AC alignment signal, and the other of the first and second electrodes ELT1 and ELT2 has a constant voltage level. A voltage (eg, a ground voltage) may be supplied. Accordingly, an electric field is formed between the first and second electrodes ELT1 and ELT2 so that the light emitting devices LD supplied to each of the pixels PXL are applied to the first and second electrodes ELT1 and ELT2 . can be arranged between

The first electrode ELT1 may be electrically connected to the bridge pattern BRP through the first contact hole CH1 , and may be electrically connected to the transistor T through this. However, the present invention is not necessarily limited thereto, and the first electrode ELT1 may be directly connected to a predetermined power line or signal line.

The second electrode ELT2 may be electrically connected to the power line PL2 through the second contact hole CH2 . However, the present invention is not necessarily limited thereto, and the second electrode ELT2 may be directly connected to a predetermined power line or signal line.

Each of the first and second electrodes ELT1 and ELT2 may include at least one conductive material. For example, each of the first and second electrodes ELT1 and ELT2 may include silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), and nickel (Ni). ), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), at least one of various metal materials including copper (Cu), or an alloy containing the same, ITO ( Indium Tin Oxide), IZO(Indium Zinc Oxide), ITZO(Indium Tin Zinc Oxide), ZnO(Zinc Oxide), AZO(Aluminum Zinc Oxide), GZO(Gallium Zinc Oxide), ZTO(Zinc Tin Oxide), GTO(Gallium) It may include, but is not limited to, at least one of a conductive oxide such as tin oxide) or fluorine tin oxide (FTO), and a conductive polymer such as PEDOT. For example, each of the first and second electrodes ELT1 and ELT2 may include another conductive material, such as a carbon nano tube or graphene. In addition, each of the first and second electrodes ELT1 and ELT2 may be configured as a single layer or a multilayer. For example, each of the first and second electrodes ELT1 and ELT2 may include a reflective electrode layer including a reflective conductive material. In addition, the first and second electrodes ELT1 and ELT2 include at least one transparent electrode layer disposed above and/or below the reflective electrode layer, respectively, and at least covering an upper portion of the reflective electrode layer and/or the transparent electrode layer. At least one of one conductive capping layer may be optionally further included.

A first insulating layer INS1 may be disposed on one region of the first and second electrodes ELT1 and ELT2 . The first insulating layer INS1 may be configured as a single layer or multiple layers, and may include at least one inorganic insulating material and/or an organic insulating material. For example, the first insulating layer INS1 includes various types of organic/inorganic insulating materials including silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), or aluminum oxide (AlOx). can do.

The light emitting devices LD may be supplied and aligned between the first and second electrodes ELT1 and ELT2 . The light emitting devices LD may be manufactured by the method of manufacturing the light emitting device described with reference to FIGS. 13 to 25 . That is, by forming the first insulating layer INF1 on the first etched area A1 , it is possible to prevent the first area A1 from being damaged during the secondary etching of the second area A2 . As described above, the lifespan and efficiency of the light emitting device LD can be improved.

The light emitting elements LD may be prepared in a dispersed form in a predetermined solution, and may be supplied to the light emitting area of each pixel PXL through an inkjet printing method or the like. For example, the light emitting devices LD may be dispersed in a volatile solvent and provided in each light emitting region. At this time, when a predetermined voltage is supplied through the first and second electrodes ELT1 and ELT2 of each of the pixels PXL, an electric field is formed between the first and second electrodes ELT1 and ELT2. , the light emitting devices LD may be aligned between the first and second electrodes ELT1 and ELT2 . After the light emitting devices LD are aligned, the solvent may be evaporated or removed by other methods to stably arrange the light emitting devices LD between the first and second electrodes ELT1 and ELT2. have. Meanwhile, although one light emitting device LD disposed in each pixel PXL is illustrated in FIG. 26 , each pixel PXL includes a plurality of light emitting devices provided between the first and second electrodes ELT1 and ELT2 . may include LDs. Accordingly, hereinafter, it is assumed that the pixel PXL includes a plurality of light emitting elements LD.

A second insulating layer INS2 may be disposed on one region of the light emitting devices LD. For example, the second insulating layer INS2 may be formed on one region of each of the light emitting devices LD to expose the first and second ends EP1 and EP2 of each of the light emitting devices LD. have. For example, the second insulating layer INS2 may be locally disposed on one region including the central region of each of the light emitting devices LD. When the second insulating layer INS2 is formed on the light emitting devices LD after alignment of the light emitting devices LD is completed, it is possible to prevent the light emitting devices LD from being separated from the aligned positions.

The second insulating layer INS2 may be configured as a single layer or multiple layers, and may include at least one inorganic insulating material and/or an organic insulating material. For example, the second insulating layer INS2 may include various types of organic/inorganic insulating materials including silicon nitride (SiNx), silicon oxide (SiOx), aluminum oxide (AlOx), photoresist (PR), and the like. can

The first and second contact electrodes CNE1 and CNE2 are respectively disposed on both ends of the light emitting devices LD not covered by the second insulating layer INS2 , that is, the first and second ends EP1 and EP2 . ) can be placed. In an embodiment, the first and second contact electrodes CNE1 and CNE2 may be sequentially formed on different layers on one surface of the substrate SUB as shown in FIG. 26 . For example, a third insulating layer INS3 may be disposed between the contact electrodes CNE1 and CNE2 formed of different conductive layers. Meanwhile, the formation order of the first and second contact electrodes CNE1 and CNE2 may vary according to embodiments. For example, in another embodiment, before the first contact electrode CNE1 is formed, the second contact electrode CNE2 is first formed to cover the second contact electrode CNE2 and the second insulating layer INS2 . After the third insulating layer INS3 is formed, the first contact electrode CNE1 may be formed on the third insulating layer INS3 . However, the present invention is not limited thereto, and the first and second contact electrodes CNE1 and CNE2 may be formed of the same conductive layer.

In addition, the first and second contact electrodes CNE1 and CNE2 are disposed on the first and second electrodes ELT1 and ELT2 to cover the exposed areas of each of the first and second electrodes ELT1 and ELT2 , respectively. can be placed. For example, the first and second contact electrodes CNE1 and CNE2 may be electrically connected to the first and second electrodes ELT1 and ELT2 at the top of the bank BNK or around the bank BNK. It may be disposed on at least one region of each of the first and second electrodes ELT1 and ELT2 . Accordingly, the first and second contact electrodes CNE1 and CNE2 may be electrically connected to the first and second electrodes ELT1 and ELT2, respectively. That is, the first electrode ELT1 may be electrically connected to the first end EP1 of the adjacent light emitting device LD through the first contact electrode CNE1 . Also, the second electrode ELT2 may be electrically connected to the second end EP2 of the adjacent light emitting device LD through the second contact electrode CNE2 .

The first and second contact electrodes CNE1 and CNE2 may be formed of various transparent conductive materials. For example, the first and second contact electrodes CNE1 and CNE2 may include indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), and aluminum zinc oxide (AZO). ), GZO (Gallium Zinc Oxide), ZTO (Zinc Tin Oxide), GTO (Gallium Tin Oxide), or FTO (Fluorine Tin Oxide), including at least one of a variety of transparent conductive materials including, and substantially to satisfy a predetermined light transmittance It may be implemented as transparent or semi-transparent. Accordingly, the light emitted from the light emitting devices LD through the respective first and second ends EP1 and EP2 passes through the first and second contact electrodes CNE1 and CNE2 to pass through the display panel PNL. ) can be released to the outside.

The third insulating layer INS3 may be disposed between the first contact electrode CNE1 and the second contact electrode CNE2 . When the third insulating layer INS3 is formed between the first contact electrode CNE1 and the second contact electrode CNE2 as described above, the first and second contact electrodes CNE1, CNE2 may be stably separated to secure electrical stability between the first and second ends EP1 and EP2 of the light emitting elements LD. Accordingly, it is possible to effectively prevent a short defect from occurring between the first and second ends EP1 and EP2 of the light emitting elements LD. The third insulating layer INS3 may be configured as a single layer or multiple layers, and may include at least one inorganic insulating material and/or an organic insulating material. For example, the third insulating layer INS3 may include various types of organic/inorganic insulating materials including silicon nitride (SiNx), silicon oxide (SiOx), aluminum oxide (AlOx), photoresist (PR), and the like. can

A fourth insulating layer INS4 may be disposed on the first and second contact electrodes CNE1 and CNE2 and/or the third insulating layer INS3 . For example, the fourth insulating layer INS4 may include the first and second electrodes ELT1 and ELT2, the first, second and/or third insulating layers INS1, INS2, INS3, and the light emitting devices LD) and the first and second contact electrodes CNE1 and CNE2. The fourth insulating layer INS4 may include at least one inorganic layer and/or an organic layer.

The fourth insulating layer INS4 may be configured as a single layer or multiple layers, and may include at least one inorganic insulating material and/or an organic insulating material. For example, the fourth insulating layer INS4 may include various types of organic/inorganic insulating materials including silicon nitride (SiNx), silicon oxide (SiOx), or aluminum oxide (AlOx).

In an embodiment, the fourth insulating layer INS4 may include a thin film encapsulation layer having a multilayer structure. For example, the fourth insulating layer INS4 is a thin film encapsulation layer having a multilayer structure including at least two inorganic insulating layers and at least one organic insulating layer interposed between the at least two inorganic insulating layers. can be configured. However, the present invention is not necessarily limited thereto, and the material and/or structure of the fourth insulating layer INS4 may be variously changed. In some embodiments, a color conversion layer and/or a color filter layer may be further formed on the fourth insulating layer INS4 , but the present invention is not limited thereto.

A person of ordinary skill in the art related to this embodiment will understand that it can be implemented in a modified form without departing from the essential characteristics of the above description. Therefore, the disclosed methods are to be considered in an illustrative rather than a restrictive sense. The scope of the present invention is indicated in the claims rather than the foregoing description, and all differences within the scope equivalent thereto should be construed as being included in the present invention.

Claims

first and second electrodes spaced apart from each other; and

A light emitting device disposed between the first electrode and the second electrode,

The light emitting device is

a first region having a first diameter;

a second region having a second diameter greater than the first diameter;

a first insulating film surrounding the first region; and

a second insulating film disposed on the first insulating film;

The second insulating layer surrounds the second region exposed by the first insulating layer.
According to claim 1,

The light emitting device is

a first semiconductor layer;

a second semiconductor layer disposed on the first semiconductor layer; and

Further comprising an active layer disposed between the first semiconductor layer and the second semiconductor layer,

The active layer is disposed in the first area.
3. The method of claim 2,

The first semiconductor layer is disposed in the first region.
4. The method of claim 3,

and the first semiconductor layer includes a p-type semiconductor layer.
3. The method of claim 2,

The first insulating layer directly covers the first semiconductor layer, the active layer, and the second semiconductor layer in the first region.
6. The method of claim 5,

The second insulating layer directly covers the second semiconductor layer of the second region exposed by the first insulating layer.
6. The method of claim 5,

a first contact electrode electrically connecting the first electrode and the first semiconductor layer; and

and a second contact electrode electrically connecting the second electrode and the second semiconductor layer.
8. The method of claim 7,

the first contact electrode is in contact with the first semiconductor layer exposed by the second insulating layer;

The second contact electrode is in contact with a second semiconductor layer exposed by the second insulating layer.
According to claim 1,

At least one of a side surface of the first area and a side surface of the second area of the light emitting device includes an inclined portion.
a first region having a first diameter;

a second region having a second diameter greater than the first diameter;

a first insulating film surrounding the first region; and

and a second insulating layer surrounding the second region exposed by the first insulating layer.
11. The method of claim 10,

a first semiconductor layer;

a second semiconductor layer disposed on the first semiconductor layer; and

Further comprising an active layer disposed between the first semiconductor layer and the second semiconductor layer,

The active layer is a light emitting device having the first diameter.
12. The method of claim 11,

The first insulating layer directly covers the first semiconductor layer, the active layer, and the second semiconductor layer in the first region.
12. The method of claim 11,

The second insulating layer directly covers the second semiconductor layer of the second region exposed by the first insulating layer.
11. The method of claim 10,

At least one of a side surface of the first region and a side surface of the second region includes an inclined portion.
15. The method of claim 14,

The first insulating layer directly covers the inclined portion of the first region.
15. The method of claim 14,

The second insulating layer directly covers the inclined portion of the second region.
11. The method of claim 10,

The first insulating layer and the second insulating layer are light emitting devices including the same material.
18. The method of claim 17,

The light emitting device further comprising a third insulating layer disposed on the first insulating layer and the second insulating layer.
11. The method of claim 10,

The first insulating layer and the second insulating layer are light emitting devices including different materials.
forming a light emitting laminate on a laminate substrate;

forming first regions of light emitting patterns by first etching the light emitting stack;

forming a first insulating layer surrounding the first area of the light emitting patterns; and

forming a second region of the emission patterns by secondary etching the emission patterns;

A method of manufacturing a light emitting device in which a diameter of the second region of the emission patterns is larger than a diameter of the first region.
21. The method of claim 20,

The light emitting laminate,

a first semiconductor layer;

a second semiconductor layer disposed on the first semiconductor layer; and

and an active layer disposed between the first semiconductor layer and the second semiconductor layer.
22. The method of claim 21,

A method of manufacturing a light emitting device in which the first semiconductor layer and the active layer are primarily etched in the forming of the first region.
23. The method of claim 22,

The method of manufacturing a light emitting device in which the first insulating layer is directly formed on the first semiconductor layer and the active layer.
21. The method of claim 20,

The method of manufacturing a light emitting device further comprising the step of surface-treating the first region or the second region.
21. The method of claim 20,

The method of manufacturing a light emitting device further comprising the step of forming a second insulating film surrounding the first region and the second region.
21. The method of claim 20,

The method of manufacturing a light emitting device further comprising the step of removing the first insulating layer after the step of forming the second region.
27. The method of claim 26,

The method of manufacturing a light emitting device further comprising the step of forming a third insulating layer surrounding the first region and the second region.
28. The method of claim 27,

The method of manufacturing a light emitting device further comprising the step of forming a fourth insulating film on the third insulating film.