WO2022119093A1

WO2022119093A1 - Display device and control method thereof

Info

Publication number: WO2022119093A1
Application number: PCT/KR2021/013580
Authority: WO
Inventors: 구정민; 이규헌
Original assignee: 삼성전자주식회사
Priority date: 2020-12-02
Filing date: 2021-10-05
Publication date: 2022-06-09
Also published as: KR20220077733A

Abstract

A display device is disclosed. The display device may comprise: a display panel including a plurality of gate lines; and a processor which adjusts the resolution of a content on the basis of the resolution of the display panel, and controls the display panel to synchronize the driving timings of at least two adjacent gate lines among the plurality of gate lines to output the content with the adjusted resolution, wherein the processor controls the display panel to change the gate lines, the driving timings of which are synchronized, according to frames.

Description

Display device and its control method

The present disclosure relates to a display apparatus and a control method thereof, and more particularly, to a display apparatus for image-processing content and displaying image-processed content, and a control method therefor.

With the development of video equipment, high-quality content is being produced. In particular, recently, content having a frame rate of 120 Hz or higher is sometimes produced.

However, since most of the conventional display devices have an operating frequency of 60 Hz or less, some frames are removed when content having a frame rate greater than or equal to the operating frequency of the display device is reproduced. Alternatively, the operating frequency of the display device may be implemented as 120 Hz in hardware, but in this case, there is a problem in that the manufacturing cost increases.

Accordingly, a method of reproducing content at a frame rate higher than the operating frequency of the display device has been developed.

For example, when the operating frequency of the display device is 60 Hz and the frame rate of the content is 120 Hz, as shown in FIG. The display time can be cut in half. In this case, the display device displays one data line through two consecutive gate lines, and can display 120Hz content without skipping a frame. Hereinafter, the above operation of the display apparatus will be referred to as a DLG (Dual Line Gating) mode.

However, when operating in the DLG mode, there is a problem in that jagging becomes severe. Jagging is also referred to as a stepping phenomenon. It is a phenomenon seen in a raster method that displays lines with dots. When drawing figures such as diagonal lines, circles, curves, etc., the outline is not smooth and becomes uneven in a step shape.

For example, as shown in FIG. 1B , when a diagonal line is displayed, jagging is more severe during DLG driving than during normal driving, which means that two consecutive gate lines are driven simultaneously and one color is displayed for each column. because it is displayed. That is, as a color to be displayed by one pixel is displayed by two adjacent upper and lower pixels, it is identified that the pixel is enlarged, and thus jagging is increased.

Accordingly, there is a need to develop a method for minimizing jagging when operating in the DLG mode.

SUMMARY The present disclosure has been made in accordance with the above-described needs, and an object of the present disclosure is to provide a display device and a control method thereof for reducing jagging that occurs when the display device operates in a dual line gating (DLG) mode.

According to an embodiment of the present disclosure for achieving the above object, a display device adjusts the resolution of content based on a display panel including a plurality of gate lines and the resolution of the display panel, and the plurality of gate lines and a processor controlling the display panel to output the content whose resolution is adjusted by synchronizing driving timings of at least two adjacent gate lines, wherein the processor is configured to change the gate lines synchronizing the driving timings for each frame. You can control the display panel.

In addition, the processor adjusts the vertical resolution of the content to half the vertical resolution of the display panel and outputs one of an odd-numbered frame and an even-numbered frame from a plurality of frames included in the content. Synchronize each of the even-numbered lines with an adjacent upper line, and synchronize each of the even-numbered lines among the plurality of gate lines with an adjacent lower line when the remainder of the odd-numbered frame and the even-numbered frame are output from the plurality of frames The display panel can be controlled.

In addition, the processor synchronizes the plurality of first gate lines and the plurality of second gate lines, respectively, in a first frame, and in a second frame following the first frame, some gate lines and the plurality of first gate lines The display panel may be controlled to synchronize some of the plurality of second gate lines.

In addition, the processor identifies a motion value of each of a plurality of frames included in the content, and in a frame in which the identified motion value is less than or equal to a threshold value among the plurality of frames, changes the gate line for synchronizing the driving timing for each frame. The display panel can be controlled.

In addition, the processor identifies an object region from the content, and in the case of a plurality of gate lines corresponding to the object region among the plurality of gate lines, the display panel is configured to change the gate line for synchronizing the driving timing for each frame. can be controlled

Also, the object area may include at least one of a text area, a graphic area, and an artifact area.

In addition, the processor may identify a type of the content and, if the identified type is a preset type, may control the display panel to change a gate line for synchronizing the driving timing for each frame.

In addition, further comprising a user interface, the processor is a user command for changing the operation mode to the second mode through the user interface while operating in a first mode that does not change the gate line for synchronizing the driving timing for each frame When this is received, the display panel may be controlled to change the gate line for synchronizing the driving timing for each frame.

In addition, the processor may adjust the vertical resolution of the content based on an equal value of the vertical resolution of the display panel.

In addition, the display panel may further include a plurality of data lines formed perpendicular to the plurality of gate lines, and each of the plurality of data lines may provide data to pixels in the same column.

Meanwhile, according to an embodiment of the present disclosure, a method of controlling a display apparatus includes adjusting the resolution of content based on the resolution of a display panel including a plurality of gate lines, and at least two adjacent gates among the plurality of gate lines. and outputting the content whose resolution is adjusted by synchronizing the driving timing of the lines, wherein the outputting may change the gate lines for synchronizing the driving timing for each frame.

In addition, the adjusting step adjusts the vertical resolution of the content to half the vertical resolution of the display panel, and the outputting step outputs one of an odd-numbered frame and an even-numbered frame from a plurality of frames included in the content In the case of synchronizing each of the even-numbered lines among the plurality of gate lines with an adjacent upper line, and outputting the remainder of the odd-numbered frame and the even-numbered frame in the plurality of frames, the even-numbered lines of the plurality of gate lines are each can be synchronized with the adjacent lower line.

In addition, the outputting includes synchronizing the plurality of first gate lines and the plurality of second gate lines, respectively, in a first frame, and some gate lines among the plurality of first gate lines in a second frame following the first frame and some of the plurality of second gate lines may be synchronized.

In addition, the method further includes the step of identifying a motion value of each of a plurality of frames included in the content, wherein the outputting step synchronizes the driving timing in a frame in which the identified motion value is less than or equal to a threshold value among the plurality of frames The gate line can be changed for each frame.

The method may further include identifying an object region from the content, wherein the outputting includes, in the case of a plurality of gate lines corresponding to the object region among the plurality of gate lines, a gate line synchronizing the driving timing as a frame. can be changed much.

The method may further include identifying a type of the content, and the outputting may change a gate line for synchronizing the driving timing for each frame if the identified type is a preset type.

In addition, the outputting step is to synchronize the driving timing when a user command for changing the operation mode to the second mode is received while the gate line for synchronizing the driving timing is operated in the first mode for each frame. The gate line can be changed for each frame.

In addition, the adjusting may include adjusting the vertical resolution of the content based on an equal value of the vertical resolution of the display panel.

According to another embodiment of the present disclosure for achieving the above object, the display apparatus adjusts the vertical resolution of a display panel including a plurality of gate lines and content to half of the vertical resolution of the display panel, and the plurality of The resolution-adjusted content is output by synchronizing driving timings of at least two adjacent gate lines among the gate lines, and at least one of a motion value of each of a plurality of frames included in the content, an object region of the content, or a type of the content. and a processor for controlling the display panel to change the gate lines for synchronizing the driving timing based on one frame by frame, wherein the processor selects one of an odd-numbered frame and an even-numbered frame from a plurality of frames included in the content. When outputting, each even-numbered line of the plurality of gate lines is synchronized with an adjacent upper line, and when outputting the remainder of the odd-numbered frame and the even-numbered frame in the plurality of frames, an even-numbered line of the plurality of gate lines The display panel can be controlled to synchronize each with an adjacent lower line.

According to various embodiments of the present disclosure as described above, the display device may reduce jagging that occurs when operating in the DLG (Dual Line Gating) mode by changing the gate lines for synchronizing the driving timing for each frame. .

In addition, the display device can adaptively reduce jagging even without user manipulation by changing gate lines for synchronizing driving timing based on at least one of a frame-by-frame motion value of the content or an object in the content for each frame. .

1A and 1B are diagrams for explaining the problems of the prior art.

2A is a block diagram illustrating a configuration of a display device according to an embodiment of the present disclosure.

2B is a block diagram illustrating a configuration of a display device according to another embodiment of the present disclosure.

2C is a view for explaining a structure of a display panel according to an embodiment of the present disclosure.

3A and 3B are diagrams for explaining a DLG mode for helping understanding of the present disclosure.

4A to 4C are diagrams for explaining an operation of displaying content according to a DLG mode according to an embodiment of the present disclosure.

5A and 5B are diagrams for explaining an operation of changing gate lines for synchronizing driving timing for each frame according to an embodiment of the present disclosure;

6 is a diagram for explaining an operation of changing gate lines for synchronizing driving timing based on a motion value for each frame according to an embodiment of the present disclosure.

7 is a diagram for explaining an operation of changing gate lines for synchronizing driving timing based on an object region for each frame according to an embodiment of the present disclosure.

8 is a flowchart illustrating a method of controlling a display apparatus according to an embodiment of the present disclosure.

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Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings.

Terms used in the embodiments of the present disclosure are selected as currently widely used general terms as possible while considering the functions in the present disclosure, which may vary depending on the intention or precedent of a person skilled in the art, the emergence of new technology, etc. . In addition, in a specific case, there is a term arbitrarily selected by the applicant, and in this case, the meaning will be described in detail in the description of the corresponding disclosure. Therefore, the terms used in the present disclosure should be defined based on the meaning of the term and the contents of the present disclosure, rather than the simple name of the term.

In this specification, expressions such as “have,” “may have,” “include,” or “may include” indicate the presence of a corresponding characteristic (eg, a numerical value, function, operation, or component such as a part). and does not exclude the presence of additional features.

The expression "at least one of A and/or B" is to be understood as indicating either "A" or "B" or "A and B".

As used herein, expressions such as "first," "second," "first," or "second," can modify various elements, regardless of order and/or importance, and refer to one element. It is used only to distinguish it from other components, and does not limit the components.

The singular expression includes the plural expression unless the context clearly dictates otherwise. In the present application, terms such as "comprises" or "consisting of" are intended to designate that the features, numbers, steps, operations, components, parts, or combinations thereof described in the specification exist, and are intended to indicate that one or more other It should be understood that this does not preclude the possibility of addition or presence of features or numbers, steps, operations, components, parts, or combinations thereof.

In this specification, the term user may refer to a person who uses the display device or a device (eg, an artificial intelligence electronic device) using the display device.

Hereinafter, an embodiment of the present disclosure will be described in more detail with reference to the accompanying drawings.

2A is a block diagram illustrating a configuration of a display apparatus 100 according to an embodiment of the present disclosure.

The display device 100 is a device that displays content, and includes a TV, a desktop PC, a notebook computer, a video wall, a large format display (LFD), a digital signage, a digital information display (DID), and a projector display. , a digital video disk (DVD) player, a refrigerator, a washing machine, a smartphone, a tablet PC, a monitor, smart glasses, a smart watch, and the like, and any device capable of displaying content may be used.

According to FIG. 2A , the display apparatus 100 includes a display panel 110 and a processor 120 . However, the present invention is not limited thereto, and the display apparatus 100 may be implemented in a form in which some components are excluded, or in a form in which other components are further included.

The display panel 110 may include a plurality of gate lines. The display panel 110 may sequentially drive a plurality of gate lines one by one. For example, the display panel 110 having a resolution of 7680×4320 may include a gate line of 4320 . In addition, the display panel 110 may sequentially drive a plurality of gate lines one by one to output a frame having a resolution of 7680×4320 at 60Hz.

Alternatively, the display panel 110 may synchronize driving timings of at least two adjacent gate lines among the plurality of gate lines under the control of the processor 120 . For example, the display panel 110 of 7680 × 4320 resolution synchronizes the driving timings of two adjacent gate lines, and sequentially drives the synchronized gate lines to output a 7680 × 4320 resolution frame at 120 Hz. may be

The display panel 110 may further include a plurality of data lines formed perpendicular to the plurality of gate lines. Here, each of the plurality of data lines may provide data to pixels in the same column.

The display panel 110 may include a timing controller TCON for controlling a plurality of gate lines included in the display panel 110 . The timing controller receives an input signal (IS), a horizontal synchronization signal (Hsync), a vertical synchronization signal (Vsync), and a main clock signal (MCLK) from the outside to receive an image data signal, a scan control signal, a data control signal, and a light emission control signal. and the like to control the display panel 110 . However, the present invention is not limited thereto, and the timing controller may be included in the processor 120 to be described later, or may be implemented in a form independent of the display panel 110 and the processor 120 .

Hereinafter, the above operation of the display panel 110 will be referred to as a DLG (Dual Line Gating) mode. However, this is only a name for convenience of description, and may include a case of simultaneously driving three or more adjacent gate lines.

Meanwhile, the display panel 110 may be implemented in various forms such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display, a plasma display panel (PDP), a micro LED, a laser display, VR, and glass. The display panel 110 may include a driving circuit, a backlight unit, and the like, which may be implemented in the form of an a-si TFT, a low temperature poly silicon (LTPS) TFT, or an organic TFT (OTFT). Meanwhile, the display panel 110 may be implemented as a touch screen combined with a touch sensor, a flexible display, a three-dimensional display, or the like.

The processor 120 controls the overall operation of the display apparatus 100 . Specifically, the processor 120 may be connected to each component of the display apparatus 100 to control overall operation of the display apparatus 100 . For example, the processor 120 may be connected to a component such as the display panel 110 to control the operation of the display apparatus 100 . Also, the processor 120 may include an image processing unit (not shown), a scaler (not shown), a frame rate change unit (not shown), and a timing controller (TCON, not shown). However, the present invention is not limited thereto, and each configuration may be implemented separately. In this case, the processor 120 is connected to an image processing unit, a scaler, a frame rate change unit, and a timing controller to control the operation of the display apparatus 100 . Also, this will be described with reference to the drawings to be described later.

According to an embodiment, the processor 120 may be implemented as a digital signal processor (DSP), a microprocessor, or a time controller (TCON). However, the present invention is not limited thereto, and the central processing unit ( central processing unit (CPU)), micro controller unit (MCU), micro processing unit (MPU), controller, application processor (AP), or communication processor (CP), ARM processor In addition, the processor 120 may be implemented as a SoC (System on Chip) or LSI (large scale integration) in which a processing algorithm is embedded, or an FPGA ( Field programmable gate array) may be implemented.

The processor 120 may adjust the resolution of the content based on the resolution of the display panel 110 . For example, if the resolution of the display panel 110 is 7680×4320, the processor 120 may adjust the content to a resolution of 7680×2160. However, the present invention is not limited thereto, and the processor 120 may adjust the vertical resolution of the content based on the equal value of the vertical resolution of the display panel 110 .

In particular, when the display apparatus 100 operates in the DLG mode, the processor 120 may adjust the vertical resolution of the content based on an equal value of the vertical resolution of the display panel 110 . When the display apparatus 100 operates in the normal mode, the processor 120 may adjust the resolution of the content to correspond to the vertical resolution of the display panel 110 .

The processor 120 may control the display panel 110 to output content whose resolution is adjusted by synchronizing driving timings of at least two adjacent gate lines among the plurality of gate lines. Here, the processor 120 may control the display panel to change the gate lines for synchronizing the driving timing for each frame.

For example, the processor 120 adjusts the vertical resolution of the content to half the vertical resolution of the display panel 110 and outputs one of an odd-numbered frame and an even-numbered frame from among the plurality of gate lines. Display panel 110 to synchronize each of the even-numbered lines with the adjacent upper line, and synchronize each of the even-numbered lines among the plurality of gate lines with the adjacent lower line when outputting the remainder of the odd-numbered frame and the even-numbered frame from the plurality of frames. can be controlled.

That is, the processor 120 synchronizes the plurality of first gate lines and the plurality of second gate lines in the first frame, respectively, and in the second frame following the first frame, some gate lines and a plurality of the plurality of first gate lines The display panel 110 may be controlled to synchronize some of the second gate lines of the .

Jagging can be minimized through this operation.

Meanwhile, the processor 120 identifies a motion value of each of a plurality of frames, and in a frame in which the identified motion value is less than or equal to a threshold value among the plurality of frames, the display panel 110 is configured to change the gate line for synchronizing the driving timing for each frame. You can also control it.

When the motion value is low, there is little screen change, and accordingly, jagging may be more severe. Accordingly, the processor 120 may reduce jagging by controlling the display panel 110 to change the gate line for synchronizing the driving timing for each frame in a frame having a motion value equal to or less than a threshold value.

Alternatively, the processor 120 identifies the object region from the content, and in the case of a plurality of gate lines corresponding to the object region among the plurality of gate lines, the display panel 110 is configured to change the gate line for synchronizing the driving timing for each frame. You can also control it.

For example, in a frame, jagging is not noticeable in a landscape area because the boundary is complicated, but in an area such as a building, the jagging may be severe because it includes a straight boundary. Accordingly, the processor 120 identifies a preset object region in the content, and in the case of a plurality of gate lines corresponding to the object region, by controlling the display panel 110 to change the gate line for synchronizing the driving timing for each frame. Jagging can be reduced.

Here, the object area may include at least one of a text area, a graphic area, and an artifact area. However, the present invention is not limited thereto, and the object region may be any region as long as the boundary is clear, such as a straight line, and thus jagging may be severe.

Meanwhile, the processor 120 may identify the type of content and, if the identified type is a preset type, may control the display panel 110 to change the gate line for synchronizing the driving timing for each frame.

For example, the processor 120 may reduce jagging by controlling the display panel 110 to change the gate line for synchronizing the driving timing for each frame in the case of content with many letters, such as home shopping.

Although it has been described above that the frame motion value, the object region, or the type of content are individually considered, the present invention is not limited thereto. For example, the processor 120 may control the display panel 110 to change the gate line for synchronizing the driving timing for each frame based on at least one of a frame motion value, an object region, and a content type.

Meanwhile, the display apparatus 100 further includes a user interface, and the processor 120 operates in the second mode through the user interface while operating in the first mode in which the gate line for synchronizing driving timing is not changed for each frame. When a user command for changing a mode is received, the display panel 110 may be controlled to change the gate line for synchronizing the driving timing for each frame.

That is, the processor 120 may control the display panel 110 to change the gate line for synchronizing the driving timing for each frame based on a user command, and user convenience may be improved through this operation.

Although FIG. 2A shows only the minimum configuration necessary for the operation of the present disclosure, the display apparatus 100 may further include other configurations, which will be described with reference to FIG. 2B .

2B is a block diagram illustrating the configuration of the display apparatus 100 according to another embodiment of the present disclosure.

According to FIG. 2B , the display apparatus 100 includes a display panel 110 and a processor 120 as well as a communication interface 130 , a memory 140 , a user interface 150 , an image processing unit 160 , and a scaler 170 . , the frame rate change unit 180 and the timing controller 190 may be further included. A description of the configuration overlapping with that of FIG. 2A among the configurations of FIG. 2B will be omitted. FIG. 2B illustrates an apparatus in which the image processing unit 160 , the scaler 170 , the frame rate change unit 180 , and the timing controller 190 are separately implemented as the processor 120 . In this case, the processor 120 may perform image processing by controlling the image processing unit 160 , the scaler 170 , the frame rate change unit 180 , and the timing controller 190 .

The communication interface 130 is configured to communicate with various types of external devices according to various types of communication methods. For example, the display apparatus 100 may receive content from an external device through the communication interface 130 .

The communication interface 130 may include a Wi-Fi module, a Bluetooth module, an infrared communication module, and a wireless communication module. Here, each communication module may be implemented in the form of at least one hardware chip.

The Wi-Fi module and the Bluetooth module perform communication using a Wi-Fi method and a Bluetooth method, respectively. In the case of using a Wi-Fi module or a Bluetooth module, various types of connection information such as an SSID and a session key are first transmitted and received, and then various types of information can be transmitted/received after communication connection using this. The infrared communication module communicates according to the infrared data association (IrDA) technology, which wirelessly transmits data in a short distance using infrared that is between visible light and millimeter waves.

In addition to the above-described communication methods, the wireless communication module includes Zigbee, 3rd Generation (3G), 3rd Generation Partnership Project (3GPP), Long Term Evolution (LTE), LTE Advanced (LTE-A), 4th Generation (4G), 5G It may include at least one communication chip that performs communication according to various wireless communication standards such as (5th Generation).

Alternatively, the communication interface 130 may include a wired communication interface such as HDMI, DP, Thunderbolt, USB, RGB, D-SUB, DVI, or the like.

In addition, the communication interface 130 may include at least one of a local area network (LAN) module, an Ethernet module, or a wired communication module for performing communication using a pair cable, a coaxial cable, or an optical fiber cable.

The memory 140 may refer to hardware that stores information such as data in an electrical or magnetic form so that the processor 120 can access it. To this end, the memory 140 may be implemented with at least one hardware selected from nonvolatile memory, volatile memory, flash memory, hard disk drive (HDD) or solid state drive (SSD), RAM, ROM, etc. .

At least one instruction or module required for the operation of the display device 100 or the processor 120 may be stored in the memory 140 . Here, the instruction is a unit of code for instructing the operation of the display device 100 or the processor 120, and may be written in machine language, which is a language that a computer can understand. A module may be a set of instructions that perform a specific task of a unit of work.

The memory 140 may store data that is information in units of bits or bytes that can represent characters, numbers, images, and the like. For example, the memory 140 may store contents, a DLG driving module, a motion value calculation module, an object region identification module, and the like.

The memory 140 is accessed by the processor 120 , and reading/writing/modification/deletion/update of instructions, modules, or data may be performed by the processor 120 .

The user interface 150 may be implemented as a button, a touch pad, a mouse, and a keyboard, or may be implemented as a touch screen capable of performing the above-described display function and manipulation input function together. Here, the button may be various types of buttons such as a mechanical button, a touch pad, a wheel, etc. formed in an arbitrary area such as the front, side, or rear of the main body of the display apparatus 100 .

Meanwhile, the display apparatus 100 may further include a microphone (not shown), and may receive a user's voice through the microphone. The display apparatus 100 may digitize the user's voice received through the microphone and perform a corresponding operation based on the digitized user's voice. Alternatively, the display device 100 may receive a user voice input by a separate device such as a remote control device (not shown) from the corresponding device.

Here, the remote control device may be a device manufactured to control the display device 100 . However, the present invention is not limited thereto, and the remote control device may be a device in which an application for controlling the display device 100 is installed in a device such as a smart phone.

In this case, the display apparatus 100 includes an IR receiver, and may receive a control signal from a remote control device through the IR receiver. However, the present invention is not limited thereto, and the display device 100 may receive a control signal from a remote control device through Bluetooth, Wi-Fi, etc., and any communication standard capable of receiving a control signal from the remote control device may be used. do.

The remote control apparatus may include a microphone for receiving a user's voice, a communication unit for digitizing the received user's voice, and transmitting the digitized user's voice to the display apparatus 100 .

Here, the processor 120 may directly identify the digitized user's voice, but may transmit it to an external server such as an STT server and receive a corresponding control command from the external server.

The image processing unit 160 may process content into an image. For example, each of the image processing units 160 may decode received content.

The scaler 170 may adjust the resolution of the content. For example, the scaler 170 may adjust the vertical resolution of the content based on an equal value of the vertical resolution of the display panel 110 .

The frame rate change unit 180 may change the frame rate of content. For example, when the display apparatus 100 operates in a normal mode, the frame rate change unit 180 may change content of 120 Hz to content of 60 Hz through frame skipping. Alternatively, when the display apparatus 100 operates in the DLG mode, the frame rate change unit 180 may change content of 60 Hz to content of 120 Hz through frame copying or interpolation.

The timing controller 190 receives an input signal IS, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a main clock signal MCLK from the processor 120 to receive an image data signal, a scan control signal, and data A control signal, a light emission control signal, etc. may be generated and provided to the display panel 110 .

In the above, the image processing unit 160, the scaler 170, the frame rate change unit 180, and the timing controller 190 have been described as being implemented individually, but the present invention is not limited thereto. For example, at least some of the image processing unit 160 , the scaler 170 , the frame rate change unit 180 , or the timing controller 190 may be implemented as one configuration. Also, at least some of the image processing unit 160 , the scaler 170 , the frame rate change unit 180 , or the timing controller 190 may be implemented as a component of the display panel 110 or the processor 120 .

2C is a view for explaining the structure of the display panel 110 according to an embodiment of the present disclosure.

The display panel 110 is formed so that the gate lines GL1 to GLn and the data lines DL1 to DLm cross each other, and the R, G, and B sub-pixels PR, PG, and PB are formed at the intersections. can be formed. The adjacent R, G, and B sub-pixels PR, PG, and PB constitute one pixel. That is, each pixel includes an R sub-pixel PR displaying red (R), a G sub-pixel PG displaying green (G), and a B sub-pixel PB displaying blue (B). The color of the subject can be reproduced with the three primary colors (R), green (G), and blue (B).

When the display panel 110 is implemented as an LCD panel, each of the sub-pixels PR, PG, and PB includes a pixel electrode and a common electrode, and the light transmittance is changed as the liquid crystal arrangement is changed by an electric field formed by a potential difference between the electrodes. will do The TFTs formed at the intersections of the gate lines GL1 to GLn and the data lines DL1 to DLm respectively respond to the scan pulses from the gate lines GL1 to GLn. Data, that is, red (R), green (G), and blue (B) data may be supplied to the pixel electrodes of each of the sub-pixels PR, PG, and PB.

The display panel 110 may further include a backlight unit 111 , a backlight driver 112 , and a panel driver 113 .

The backlight driver 112 may be implemented in a form including a driver IC for driving the backlight unit 111 . According to an example, the driver IC may be implemented as hardware separate from the processor 120 . For example, when the light sources included in the backlight unit 111 are implemented as LED devices, the driver IC may be implemented as at least one LED driver that controls the current applied to the LED devices. According to an embodiment, the LED driver may be disposed at a rear end of a power supply (eg, a switching mode power supply (SMPS)) to receive voltage from the power supply. However, according to another embodiment, a voltage may be applied from a separate power supply device. Alternatively, it is also possible to be implemented in the form of a module in which the SMPS and the LED driver are integrated into one.

The panel driver 113 may be implemented in a form including a driver IC for driving the display panel 110 . According to an example, the driver IC may be implemented as hardware separate from the processor 120 . For example, the panel driver 113 may include a data driver 113-1 supplying video data to data lines and a gate driver 113-2 supplying scan pulses to the gate lines.

The data driver 113 - 1 is a means for generating a data signal, and receives R/G/B image data from the processor 120 or the timing controller to generate a data signal. Also, the data driver 113 - 1 applies a data signal generated by being connected to the data lines DL1 , DL2 , DL3 , ..., DLm of the display panel 110 to the display panel 110 .

The gate driver 113-2 (or scan driver) is a means for generating a gate signal (or scan signal), and is connected to the gate lines GL1, GL2, GL3, ..., GLn to transmit the gate signal to the display panel ( 110) to a specific line. The data signal output from the data driver 113 - 1 is transmitted to the pixel to which the gate signal is transmitted.

The processor 120 may control the gate driver 113 - 2 to synchronize driving timings of at least two adjacent gate lines among the plurality of gate lines. That is, the processor 120 may control the display panel 110 by transmitting a signal to at least one of the data driver 113 - 1 and the gate driver 113 - 2 . Through this operation, the frame display time is shortened, and content can be displayed at a frame rate higher than the operating frequency of the display panel 110 . Also, the processor 120 may reduce jagging by controlling the display panel 110 to change the gate lines for synchronizing the driving timing for each frame.

As described above, the display apparatus 100 may reduce jagging that occurs when operating in the DLG mode by changing the gate lines for synchronizing the driving timing for each frame.

Hereinafter, the operation of the display apparatus 100 will be described in more detail with reference to various drawings. In the following drawings, each embodiment may be implemented individually or may be implemented in a combined form. Also, hereinafter, it is assumed that the display apparatus 100 operates in the DLG mode.

The display panel 110 may be implemented as a panel having a resolution of x × y. For example, the display panel 110 may be implemented as a panel having a resolution of 7680×4320. Alternatively, the display panel 110 may be implemented as a panel having a resolution of 3840×2160. However, this is only an embodiment, and the display panel 110 may be implemented with any number of different resolutions. In addition, the horizontal and vertical ratios of the display panel 110 may also vary, such as 21:9 or 32:9.

In FIG. 3A , the display panel 110 implemented as a panel having a resolution of x × y is shown, and only the vertical resolution is displayed in a divided state for convenience of explanation. That is, the display panel 110 implemented as a panel having a resolution of x × y may be divided into y horizontally long regions.

The y long horizontal regions may be driven through one gate line. That is, the display panel 110 may include as many as y gate lines.

3B is a diagram for explaining an operating frequency of the display panel 110 according to an embodiment of the present disclosure. In FIG. 3B , it is assumed that the display panel 110 is a 60Hz panel.

As shown in FIG. 3B , the display panel 110 may display 60 frames for 1 second. That is, the display panel 110 may display one frame for 1/60s.

The display panel 110 may sequentially drive y gate lines to display one frame for 1/60s. Assuming that one gate line is driven at a time, the unit time for driving one gate line is 1/(60×y)s, and when driving all the gate lines, it is repeated y times, so it takes 1/60s of time.

Alternatively, as in an embodiment of the present disclosure, when two gate lines are driven at the same time, the unit time is 1/(60×y)s, but since the number of repetitions to drive all the gate lines is y/2 times, 1 /120s will be taken.

Also, when two gate lines are simultaneously driven, pixels adjacent in the vertical direction display the same color. That is, in order for pixels adjacent in the vertical direction to display the same color, the display panel 110 may be implemented as a panel having a 1D1G stripe structure. In this case, since the gate terminals of the pixels adjacent in the vertical direction are simultaneously turned on and the same data value is input, the two pixels adjacent in the vertical direction may display the same color.

On the other hand, in the case of a panel having a 1D1G crossed structure or a panel having a 2DHG structure, even if the first gate line and the second gate line are simultaneously driven, the data values input to the vertically adjacent pixels are different, so that the two vertically adjacent pixels are different. color is displayed, and the present disclosure cannot be applied. However, even in the case of a panel having a 1D1G crossed structure or a panel having a 2DHG structure, the present disclosure may be applied as long as it is a technology capable of displaying the same color by simultaneously driving adjacent pixels in the vertical direction.

4A to 4C are diagrams for explaining an operation of displaying content according to a DLG mode according to an embodiment of the present disclosure. 4A to 4C, it is assumed that the display panel 110 is a 60Hz panel and the frame rate of the content is 120Hz.

The processor 120 may adjust the resolution of the mixed content based on the equal value of the vertical resolution of the display panel 110 . For example, as shown in FIG. 4A , when the display panel 110 is a panel having a resolution of 7680×4320, the processor 120 may adjust the resolution of the content to 7680×2160.

The display panel 110 may simultaneously drive two adjacent gate lines among the plurality of gate lines. For example, as shown in FIG. 4B , the display panel 110 may display the pixel line of the first row of the content whose resolution is adjusted to 7680×2160 by driving the upper two adjacent gate lines 410 . have. In addition, the display panel 110 may display the pixel line of the second row of the content whose resolution is adjusted to 7680×2160 by driving the next upper two adjacent gate lines 420 .

In this way, the display panel 110 can reduce the time for displaying one frame in half. For example, when the display panel 110 does not perform the operation shown in FIGS. 4A and 4B , as shown in the upper part of FIG. 4C , one frame may be displayed for 1/60s. On the other hand, when the display panel 110 performs the operation shown in FIGS. 4A and 4B , as shown in the lower part of FIG. 4C , one frame may be displayed for 1/120s. That is, the display panel 110 may display two frames for 1/60s.

As a result, in the case of the upper part of FIG. 4C , the display panel 110 displays 60 frames for 1 second, but in the case of the lower part of FIG. 4C , 120 frames can be displayed during 1 second. That is, in the DLG mode, while the driving speed of the gate line of the display panel 110 is maintained as it is, it is possible to reduce the time to display one frame through a decrease in vertical resolution, thereby providing an effect such as an increase in the frame rate.

The left side of FIG. 5A shows a case of operating in the normal mode. Here, when the display apparatus 100 operates in the DLG mode as shown on the right side of FIG. 5B , the processor 120 may adjust the vertical resolution of the content to half the vertical resolution of the display panel 110 .

In addition, the processor 120 synchronizes each of the even-numbered lines among the plurality of gate lines with an adjacent upper line when outputting the 2n-th frame from the plurality of frames, and when outputting the 2n+1-th frame from the plurality of frames, the plurality of The display panel 110 may be controlled to synchronize each even-numbered line among the gate lines with an adjacent lower line. Here, n is an integer greater than or equal to 0, and it is assumed that the plurality of frames are indexed from the 0th frame.

More specifically, for example, when outputting the 2n-th frame, the processor 120 simultaneously drives the first and second gate lines from the upper side based on the first line data of the content whose resolution is adjusted, and the third and fourth The second gate line may be simultaneously driven based on the second line data of the content whose resolution is adjusted, and the remaining gate lines may be driven in the same manner. In addition, when the 2n+1th frame is output, the processor 120 drives the first gate line from the upper side based on the first line data of the content whose resolution is adjusted, and adjusts the resolution of the second and third gate lines. It is simultaneously driven based on the second line data of the content, and the fourth and fifth gate lines are simultaneously driven based on the third line data of the content whose resolution is adjusted, and the remaining gate lines can be driven in the same way. .

However, the present invention is not limited thereto, and the processor 120 may adjust the resolution of the content to the resolution of the display panel 110 . Then, as shown in FIG. 5A , the processor 120 simultaneously drives the first and second gate lines from the upper side when outputting the 2n-th frame based on the first line data of the content whose resolution is adjusted, and three The fourth and fourth gate lines may be simultaneously driven based on the third line data of the content whose resolution is adjusted, and the remaining gate lines may be driven in the same manner. In addition, when outputting the 2n+1th frame, the processor 120 simultaneously drives the second and third gate lines from the upper side based on the second line data of the content whose resolution is adjusted, and the fourth and fifth gate lines may be simultaneously driven based on the fourth line data of the content whose resolution has been adjusted, and the remaining gate lines may be driven in the same manner.

When content is output in the above manner, the diagonal area may be illustrated as shown in FIG. 5B . In particular, as the 2n-th frame and the 2n+1-th frame are alternately displayed, jagging can be reduced as shown in the last diagram of FIG. 5B .

The processor 120 may identify a motion value of each of the plurality of frames. For example, the processor 120 may obtain the motion value of the nth frame by averaging the difference between the n−1th frame and the nth frame. However, the present invention is not limited thereto, and the processor 120 may acquire the motion value in various ways.

The processor 120 may control the display panel 110 to change the gate line for synchronizing the driving timing for each frame in a frame in which the identified motion value is equal to or less than the threshold value among the plurality of frames.

For example, in FIG. 6 , it is assumed that the motion values of the three left frames exceed the threshold and the motion values of the right three frames are less than or equal to the threshold. In this case, the processor 120 operates in the DLG mode for the three left frames based on the motion value of each frame, but does not change the gate line for synchronizing the driving timing for each frame, and enters the DLG mode for the right three frames However, the gate line for synchronizing the driving timing may be changed for each frame.

The processor 120 may identify the object area from the content. For example, the processor 120 may identify at least one of a text area, a graphic area, and an artifact area from the content.

In the case of a plurality of gate lines corresponding to the identified region among the plurality of gate lines, the processor 120 may control the display panel 110 to change the gate line for synchronizing driving timing for each frame.

For example, when the lower side of FIG. 7 is identified as the object region, the processor 120 operates in the DLG mode and displays the gate lines corresponding to the lower side of FIG. 7 to change the gate lines for synchronizing the driving timing for each frame. The panel 110 can be controlled. In addition, in the case of the gate lines corresponding to the upper side of FIG. 7 , the processor 120 may control the display panel 110 to operate in the DLG mode but not to change the gate lines for synchronizing the driving timing for each frame.

First, the resolution of the content is adjusted based on the resolution of the display panel including the plurality of gate lines ( S810 ). Then, the resolution-adjusted content is output by synchronizing driving timings of at least two adjacent gate lines among the plurality of gate lines ( S820 ). Here, in the step of outputting ( S820 ), the gate lines for synchronizing the driving timing may be changed for each frame.

In addition, the adjusting step (S810) adjusts the vertical resolution of the content to half the vertical resolution of the display panel, and the outputting step (S820) is one of an odd-numbered frame and an even-numbered frame from a plurality of frames included in the content When outputting, each of the even-numbered lines among the plurality of gate lines is synchronized with the adjacent upper line, and when outputting the remainder of the odd-numbered frame and the even-numbered frame in the plurality of frames, each of the even-numbered lines among the plurality of gate lines is connected to the adjacent lower line can be synchronized with

And, in the outputting ( S820 ), the plurality of first gate lines and the plurality of second gate lines are each synchronized in the first frame, and some gate lines among the plurality of first gate lines in the second frame following the first frame and some gate lines among the plurality of second gate lines may be synchronized.

Meanwhile, the method further includes identifying a motion value of each of a plurality of frames included in the content, and outputting ( S820 ) is a gate line for synchronizing driving timing in a frame in which the identified motion value among the plurality of frames is equal to or less than a threshold value. can be changed for each frame.

Alternatively, the method further includes the step of identifying the object region from the content, and outputting ( S820 ) may include, in the case of a plurality of gate lines corresponding to the object region among the plurality of gate lines, changing the gate line for synchronizing the driving timing for each frame. can

Here, the object area may include at least one of a text area, a graphic area, and an artifact area.

Meanwhile, the method further includes identifying the type of content, and outputting ( S820 ) may change the gate line for synchronizing the driving timing for each frame if the identified type is a preset type.

And, the step of outputting (S820) is to synchronize the driving timing when a user command to change the operation mode to the second mode is received while operating in the first mode in which the gate line for synchronizing the driving timing is not changed for each frame. The gate line can be changed for each frame.

Meanwhile, in the adjusting ( S810 ), the vertical resolution of the content may be adjusted based on the equal value of the vertical resolution of the display panel.

Meanwhile, although it has been described above that the display device performs the operation, the present invention is not limited thereto. For example, the server may adjust the resolution of the content based on the resolution of the display panel and provide the content whose resolution is adjusted to the display device. In this case, the server may provide a control signal for instructing the display device to operate in the DLG mode to the display device. That is, the server may perform all operations other than the DLG mode operation, and the display device may operate in the DLG mode under the control of the server.

Meanwhile, according to a temporary example of the present disclosure, the various embodiments described above may be implemented as software including instructions stored in a machine-readable storage media readable by a machine (eg, a computer). can The device is a device capable of calling a stored command from a storage medium and operating according to the called command, and may include an electronic device (eg, the electronic device A) according to the disclosed embodiments. When the instruction is executed by the processor, the processor may perform a function corresponding to the instruction by using other components directly or under the control of the processor. Instructions may include code generated or executed by a compiler or interpreter. The device-readable storage medium may be provided in the form of a non-transitory storage medium. Here, 'non-transitory' means that the storage medium does not include a signal and is tangible, and does not distinguish that data is semi-permanently or temporarily stored in the storage medium.

Also, according to an embodiment of the present disclosure, the method according to the various embodiments described above may be included in a computer program product and provided. Computer program products may be traded between sellers and buyers as commodities. The computer program product may be distributed in the form of a machine-readable storage medium (eg, compact disc read only memory (CD-ROM)) or online through an application store (eg, Play Store™). In the case of online distribution, at least a portion of the computer program product may be temporarily stored or temporarily generated in a storage medium such as a memory of a server of a manufacturer, a server of an application store, or a relay server.

In addition, according to an embodiment of the present disclosure, the various embodiments described above are stored in a recording medium readable by a computer or a similar device using software, hardware, or a combination thereof. can be implemented in In some cases, the embodiments described herein may be implemented by the processor itself. According to the software implementation, embodiments such as procedures and functions described in this specification may be implemented as separate software modules. Each of the software modules may perform one or more functions and operations described herein.

Meanwhile, computer instructions for performing the processing operation of the device according to the above-described various embodiments may be stored in a non-transitory computer-readable medium. When the computer instructions stored in the non-transitory computer-readable medium are executed by the processor of the specific device, the specific device performs the processing operation in the device according to the various embodiments described above. The non-transitory computer-readable medium refers to a medium that stores data semi-permanently, not a medium that stores data for a short moment, such as a register, cache, memory, etc., and can be read by a device. Specific examples of the non-transitory computer-readable medium may include a CD, DVD, hard disk, Blu-ray disk, USB, memory card, ROM, and the like.

In addition, each of the components (eg, a module or a program) according to the above-described various embodiments may be composed of a single or a plurality of entities, and some sub-components of the aforementioned sub-components may be omitted, or other sub-components may be omitted. Components may be further included in various embodiments. Alternatively or additionally, some components (eg, a module or a program) may be integrated into a single entity to perform the same or similar functions performed by each corresponding component prior to integration. According to various embodiments, operations performed by a module, program, or other component are sequentially, parallel, repetitively or heuristically executed, or at least some operations are executed in a different order, are omitted, or other operations are added. can be

In the above, preferred embodiments of the present disclosure have been illustrated and described, but the present disclosure is not limited to the specific embodiments described above, and it is common in the technical field pertaining to the present disclosure without departing from the gist of the present disclosure as claimed in the claims. Various modifications may be made by those having the knowledge of

Claims

In the display device,

a display panel including a plurality of gate lines; and

Adjusting the resolution of the content based on the resolution of the display panel,

a processor for controlling the display panel to output the content whose resolution is adjusted by synchronizing driving timings of at least two adjacent gate lines among the plurality of gate lines; and

The processor is

and controlling the display panel to change the gate lines for synchronizing the driving timing for each frame.
According to claim 1,

The processor is

adjusting the vertical resolution of the content to half of the vertical resolution of the display panel;

When one of an odd-numbered frame and an even-numbered frame is output from a plurality of frames included in the content, each of the even-numbered lines among the plurality of gate lines is synchronized with an adjacent upper line, and in the plurality of frames, the odd-numbered frame and and controlling the display panel to synchronize each even-numbered line among the plurality of gate lines with an adjacent lower line when the remainder of the even-numbered frame is output.
According to claim 1,

The processor is

Synchronize each of the plurality of first gate lines and the plurality of second gate lines in a first frame, and in a second frame following the first frame, some gate lines of the plurality of first gate lines and the plurality of second gates and controlling the display panel to synchronize some gate lines of the lines.
According to claim 1,

The processor is

Identifies a motion value of each of a plurality of frames included in the content,

and controlling the display panel to change a gate line for synchronizing the driving timing for each frame in a frame in which the identified motion value is less than or equal to a threshold value among the plurality of frames.
According to claim 1,

The processor is

identify an object area in the content;

In the case of a plurality of gate lines corresponding to the object region among the plurality of gate lines, the display device is configured to control the display panel to change the gate lines for synchronizing the driving timing for each frame.
6. The method of claim 5,

The object area is

A display device comprising at least one of a text area, a graphics area, or an artifact area.
According to claim 1,

The processor is

identify the type of content;

If the identified type is a preset type, controlling the display panel to change the gate line for synchronizing the driving timing for each frame.
According to claim 1,

User interface; further comprising,

The processor is

When a user command for changing the operation mode to the second mode is received through the user interface while operating in the first mode in which the gate line for synchronizing the driving timing is not changed for each frame, the gate line for synchronizing the driving timing A display device for controlling the display panel to change .
According to claim 1,

The processor is

The display apparatus of claim 1, wherein the vertical resolution of the content is adjusted based on the equal value of the vertical resolution of the display panel.
According to claim 1,

The display panel,

Further comprising a plurality of data lines formed perpendicular to the plurality of gate lines,

Each of the plurality of data lines,

A display device that provides data to pixels in the same column.
A method for controlling a display device, comprising:

adjusting the resolution of the content based on the resolution of the display panel including the plurality of gate lines; and

outputting the content whose resolution is adjusted by synchronizing driving timings of at least two adjacent gate lines among the plurality of gate lines;

The output step is

A control method of changing the gate lines for synchronizing the driving timing for each frame.
12. The method of claim 11,

The adjusting step is

adjusting the vertical resolution of the content to half of the vertical resolution of the display panel;

The output step is

When one of an odd-numbered frame and an even-numbered frame is output from a plurality of frames included in the content, each of the even-numbered lines among the plurality of gate lines is synchronized with an adjacent upper line, and in the plurality of frames, the odd-numbered frame and and synchronizing each of the even-numbered lines among the plurality of gate lines with an adjacent lower line when the remainder of the even-numbered frame is output.
12. The method of claim 11,

The output step is

Synchronize each of the plurality of first gate lines and the plurality of second gate lines in a first frame, and in a second frame following the first frame, some gate lines of the plurality of first gate lines and the plurality of second gates A method of controlling, synchronizing some of the gate lines of the lines.
12. The method of claim 11,

Further comprising; identifying a motion value of each of a plurality of frames included in the content;

The output step is

In a frame in which the identified motion value is equal to or less than a threshold value among the plurality of frames, a gate line for synchronizing the driving timing is changed for each frame.
12. The method of claim 11,

further comprising; identifying an object region in the content;

The output step is

In the case of a plurality of gate lines corresponding to the object region among the plurality of gate lines, a gate line for synchronizing the driving timing is changed for each frame.