WO2022118646A1 - Integrated circuit and high frequency module - Google Patents
Integrated circuit and high frequency module Download PDFInfo
- Publication number
- WO2022118646A1 WO2022118646A1 PCT/JP2021/041934 JP2021041934W WO2022118646A1 WO 2022118646 A1 WO2022118646 A1 WO 2022118646A1 JP 2021041934 W JP2021041934 W JP 2021041934W WO 2022118646 A1 WO2022118646 A1 WO 2022118646A1
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- WIPO (PCT)
- Prior art keywords
- circuit
- base material
- integrated circuit
- power amplifier
- layer
- Prior art date
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Images
Classifications
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H03F2203/7209—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal the gated amplifier being switched from a first band to a second band
Definitions
- the present invention relates to integrated circuits and high frequency modules.
- the miniaturization of the high frequency module is realized by stacking the controller on the power amplifier arranged on the package substrate.
- the electric circuit (controller) laminated on the electric power amplifier may be heated by the heat generated by the electric power amplifier, and the characteristics of the electric circuit may be deteriorated.
- the present invention provides an integrated circuit and a high frequency module that can contribute to the miniaturization of the high frequency module and suppress the deterioration of the characteristics of the electric circuit due to heat.
- the integrated circuit according to one aspect of the present invention has a first base material in which at least a part is composed of a first semiconductor material and an electric circuit is formed, and at least a part has a lower thermal conductivity than the first semiconductor material. It is composed of a second base material formed of a second semiconductor material having a power amplification circuit, and a low heat conduction material having at least a part having a lower thermal conductivity than that of the second semiconductor material, and is composed of an electric circuit and power amplification. It comprises a low thermal conductive member disposed between the circuits, and at least a part of the first base material overlaps with at least a part of the second base material in a plan view.
- the integrated circuit is composed of a first substrate in which at least a part is made of silicon or gallium nitride and an electric circuit is formed, and at least a part is made of gallium arsenic or silicon germanium, and power is amplified. It comprises a second substrate on which a circuit is formed and a low thermal conductivity member which is at least partially composed of glass or epoxy resin and is arranged between an electric circuit and a power amplifier circuit, and at least one of the first substrates. The portion overlaps at least a part of the second base material in a plan view.
- the integrated circuit according to one aspect of the present invention has a first base material in which at least a part is composed of a first semiconductor material and an electric circuit is formed, and at least a part has a lower thermal conductivity than the first semiconductor material. It is provided with a second base material made of a second semiconductor material and having a power amplification circuit formed therein, and a gap portion located between an electric circuit and a power amplification circuit is formed inside the first base material. At least a part of the first base material overlaps with at least a part of the second base material in a plan view.
- the integrated circuit according to one aspect of the present invention is composed of a first substrate in which at least a part is made of silicon or gallium nitride and an electric circuit is formed, and at least a part is made of gallium arsenic or silicon germanium, and power is amplified.
- a second base material on which a circuit is formed is provided, and a gap portion located between an electric circuit and a power amplifier circuit is formed inside the first base material, and at least a part of the first base material. Overlaps at least a portion of the second substrate in plan view.
- the integrated circuit According to the integrated circuit according to one aspect of the present invention, it is possible to contribute to the miniaturization of the high frequency module and suppress the deterioration of the characteristics of the power amplifier circuit due to heat.
- FIG. 1 is a circuit configuration diagram of a high frequency module and a communication device according to an embodiment.
- FIG. 2 is a plan view of the high frequency module according to the embodiment.
- FIG. 3 is a cross-sectional view of the high frequency module according to the embodiment.
- FIG. 4 is a partial cross-sectional view of the high frequency module according to the embodiment.
- FIG. 5 is a partial cross-sectional view of the high frequency module according to the embodiment.
- FIG. 6 is a circuit layout diagram in the integrated circuit according to the embodiment.
- FIG. 7 is a partial cross-sectional view of a high frequency module according to a modified example of the embodiment.
- each figure is a schematic diagram in which emphasis, omission, or ratio is adjusted as appropriate to show the present invention, and is not necessarily exactly illustrated. What is the actual shape, positional relationship, and ratio? May be different. In each figure, substantially the same configuration is designated by the same reference numeral, and duplicate description may be omitted or simplified.
- the x-axis and the y-axis are axes orthogonal to each other on a plane parallel to the main surface of the module substrate.
- the x-axis is parallel to the first side of the module substrate and the y-axis is parallel to the second side orthogonal to the first side of the module substrate.
- the z-axis is an axis perpendicular to the main surface of the module substrate, the positive direction thereof indicates an upward direction, and the negative direction thereof indicates a downward direction.
- connection includes not only the case of being directly connected by a connection terminal and / or a wiring conductor, but also the case of being electrically connected via another circuit element. Further, “connected between A and B” means that both A and B are connected between A and B.
- planar view means that an object is projected orthographically projected onto the xy plane from the positive side of the z-axis.
- a overlaps with B in a plan view means that the region of A orthographically projected on the xy plane overlaps with the region of B orthographically projected on the xy plane.
- Cross-section view means to cut and view in a cross-section perpendicular to the xy plane.
- a is arranged between B and C in a cross-sectional view means a plurality of lines connecting an arbitrary point in the region of B and an arbitrary point in the region of C in a cross section perpendicular to the xy plane.
- the component is laminated on another component arranged on the substrate), and a part or all of the component is embedded and arranged in the substrate.
- the component is arranged on the main surface of the board means that the component is arranged on the main surface in a state of being in contact with the main surface of the board, and the component is mainly arranged without contacting the main surface. This includes arranging above the surface and embedding a part of the component in the substrate from the main surface side.
- the object A is composed of the material B
- the principal component means a component having the largest weight ratio among a plurality of components contained in an object.
- FIG. 1 is a circuit configuration diagram of a high frequency module 1 and a communication device 5 according to an embodiment.
- the communication device 5 includes a high frequency module 1, an antenna 2, an RFIC (Radio Frequency Integrated Circuit) 3, and a BBIC (Baseband Integrated Circuit) 4.
- a high frequency module 1 As shown in FIG. 1, the communication device 5 according to the present embodiment includes a high frequency module 1, an antenna 2, an RFIC (Radio Frequency Integrated Circuit) 3, and a BBIC (Baseband Integrated Circuit) 4.
- RFIC Radio Frequency Integrated Circuit
- BBIC Baseband Integrated Circuit
- the high frequency module 1 transmits a high frequency signal between the antenna 2 and the RFIC 3.
- the internal configuration of the high frequency module 1 will be described later.
- the antenna 2 is connected to the antenna connection terminal 100 of the high frequency module 1, receives a high frequency signal from the outside, and outputs the high frequency signal to the high frequency module 1.
- RFIC3 is an example of a signal processing circuit that processes high frequency signals. Specifically, the RFIC 3 processes the high frequency reception signal input via the reception path of the high frequency module 1 by down-conversion or the like, and outputs the reception signal generated by the signal processing to the BBIC 4. Further, the RFIC 3 has a control unit that controls a switch circuit, an amplifier circuit, and the like included in the high frequency module 1. A part or all of the function of the RFIC3 as a control unit may be configured outside the RFIC3, or may be configured in, for example, the BBIC4 or the high frequency module 1.
- the BBIC 4 is a baseband signal processing circuit that processes signals using an intermediate frequency band having a lower frequency than the high frequency signal transmitted by the high frequency module 1.
- the signal processed by the BBIC 4 for example, an image signal for displaying an image and / or an audio signal for a call via a speaker are used.
- the antenna 2 and the BBIC 4 are not essential components.
- the high frequency module 1 includes a power amplifier circuit 11, a low noise amplifier circuit 21, an impedance matching circuit (MN) 41 to 44, a switch circuit 51 to 55, and a duplexer circuit 61 and 62. It includes a control circuit 80, an antenna connection terminal 100, high frequency input terminals 111 and 112, high frequency output terminals 121 and 122, and a control terminal 130.
- MN impedance matching circuit
- the antenna connection terminal 100 is connected to the antenna 2 outside the high frequency module 1.
- Each of the high frequency input terminals 111 and 112 is an input terminal for receiving a high frequency transmission signal from the outside of the high frequency module 1.
- the high frequency input terminals 111 and 112 are connected to the RFIC 3 outside the high frequency module 1.
- Each of the high frequency output terminals 121 and 122 is an output terminal for providing a high frequency reception signal to the outside of the high frequency module 1.
- the high frequency output terminals 121 and 122 are connected to the RFIC 3 outside the high frequency module 1.
- the control terminal 130 is a terminal for transmitting a control signal. That is, the control terminal 130 is a terminal for receiving a control signal from the outside of the high frequency module 1 and / or a terminal for supplying a control signal to the outside of the high frequency module 1.
- the control signal is a signal related to the control of electronic components included in the high frequency module 1. Specifically, the control signal is, for example, a digital signal for controlling the power amplifier circuit 11.
- the power amplifier circuit 11 can amplify the transmission signals of the bands A and B.
- the input end of the power amplifier circuit 11 is connected to the high frequency input terminals 111 and 112 via the switch circuit 52.
- the output end of the power amplifier circuit 11 is connected to the transmission filter circuits 61T and 62T via the impedance matching circuit 41 and the switch circuit 51.
- the configuration of the power amplifier circuit 11 is not particularly limited.
- the power amplification circuit 11 may be a multi-stage amplifier circuit or a differential amplifier type amplifier circuit.
- the low noise amplifier circuit 21 can amplify the received signals of bands A and B.
- the input end of the low noise amplifier circuit 21 is connected to the reception filter circuits 61R and 62R via the impedance matching circuit 42 and the switch circuit 54.
- the output end of the low noise amplifier circuit 21 is connected to the high frequency output terminals 121 and 122 via the switch circuit 55.
- the impedance matching circuit 41 is connected to the output end of the power amplifier circuit 11 and is connected to the input ends of the transmission filter circuits 61T and 62T via the switch circuit 51.
- the impedance matching circuit 41 can perform impedance matching between the output impedance of the power amplifier circuit 11 and the input impedance of the switch circuit 51.
- the impedance matching circuit 42 is connected to the input end of the low noise amplifier circuit 21 and is connected to the output ends of the reception filter circuits 61R and 62R via the switch circuit 54.
- the impedance matching circuit 42 can perform impedance matching between the output impedance of the switch circuit 54 and the input impedance of the low noise amplifier circuit 21.
- the impedance matching circuit 43 is connected to the output end of the transmission filter circuit 61T and the input end of the reception filter circuit 61R, and is connected to the antenna connection terminal 100 via the switch circuit 53.
- the impedance matching circuit 43 can achieve impedance matching between the switch circuit 53 and the duplexer circuit 61.
- the impedance matching circuit 44 is connected to the output end of the transmission filter circuit 62T and the input end of the reception filter circuit 62R, and is connected to the antenna connection terminal 100 via the switch circuit 53. Impedance matching circuit 44 can achieve impedance matching between the switch circuit 53 and the duplexer circuit 62.
- the switch circuit 51 is an example of the first switch circuit, and is connected between the output end of the power amplifier circuit 11 and the input ends of the transmission filter circuits 61T and 62T.
- the switch circuit 51 has terminals 511 to 513.
- the terminal 511 is connected to the output end of the power amplifier circuit 11 via the impedance matching circuit 41.
- the terminal 512 is connected to the input end of the transmission filter circuit 61T.
- the terminal 513 is connected to the input end of the transmission filter circuit 62T.
- the switch circuit 51 can connect the terminal 511 to any of the terminals 512 and 513, for example, based on the control signal from the RFIC3. That is, the switch circuit 51 can switch the connection of the output end of the power amplifier circuit 11 between the transmission filter circuits 61T and 62T.
- the switch circuit 51 is configured by using, for example, a SPDT (Single-Pole Double-Throw) type switch, and may be called a band select switch.
- the switch circuit 52 is an example of a second switch circuit, and is connected between the high frequency input terminals 111 and 112 and the input end of the power amplifier circuit 11.
- the switch circuit 52 has terminals 521 to 523.
- the terminal 521 is connected to the input end of the power amplifier circuit 11.
- the terminals 522 and 523 are connected to the high frequency input terminals 111 and 112, respectively.
- the switch circuit 52 can connect the terminal 521 to any of the terminals 522 and 523, for example, based on the control signal from the RFIC3. That is, the switch circuit 52 can switch the connection of the input end of the power amplifier circuit 11 between the high frequency input terminals 111 and 112.
- the switch circuit 52 is configured by using, for example, a SPDT type switch, and is sometimes called an in-switch.
- the switch circuit 53 is an example of a third switch circuit, and is connected between the antenna connection terminal 100 and the duplexer circuits 61 and 62.
- the switch circuit 53 has terminals 531 to 533.
- the terminal 531 is connected to the antenna connection terminal 100.
- the terminal 532 is connected to the output end of the transmission filter circuit 61T and the input end of the reception filter circuit 61R via the impedance matching circuit 43.
- the terminal 533 is connected to the output end of the transmission filter circuit 62T and the input end of the reception filter circuit 62R via the impedance matching circuit 44.
- the switch circuit 53 can connect the terminal 531 to one or both of the terminals 532 and 533, for example, based on the control signal from the RFIC3. That is, the switch circuit 53 can switch the connection and non-connection of the antenna connection terminal 100 and the duplexer circuit 61, and can switch the connection and non-connection of the antenna connection terminal 100 and the duplexer circuit 62.
- the switch circuit 53 is configured by using, for example, a multi-connection type switch, and is sometimes called an antenna switch.
- the switch circuit 54 is connected between the input end of the low noise amplifier circuit 21 and the output ends of the reception filter circuits 61R and 62R.
- the switch circuit 54 has terminals 541 to 543.
- the terminal 541 is connected to the input end of the low noise amplifier circuit 21 via an impedance matching circuit 42.
- the terminal 542 is connected to the output end of the reception filter circuit 61R.
- the terminal 543 is connected to the output end of the reception filter circuit 62R.
- the switch circuit 54 can connect the terminal 541 to any of the terminals 542 and 543, for example, based on the control signal from the RFIC3. That is, the switch circuit 54 can switch the connection of the input end of the low noise amplifier circuit 21 between the reception filter circuits 61R and 62R.
- the switch circuit 54 is configured by using, for example, a SPDT type switch.
- the switch circuit 55 is connected between the high frequency output terminals 121 and 122 and the output end of the low noise amplifier circuit 21.
- the switch circuit 55 has terminals 551 to 553.
- the terminal 551 is connected to the output end of the low noise amplifier circuit 21.
- the terminals 552 and 553 are connected to the high frequency output terminals 121 and 122, respectively.
- the switch circuit 55 can connect the terminal 551 to any of the terminals 552 and 553, for example, based on the control signal from the RFIC3. That is, the switch circuit 55 can switch the connection of the output end of the low noise amplifier circuit 21 between the high frequency output terminals 121 and 122.
- the switch circuit 55 is configured by using, for example, a SPDT type switch, and is sometimes called an out switch.
- the duplexer circuit 61 can pass a high frequency signal of band A.
- the duplexer circuit 61 transmits the transmission signal and the reception signal of the band A by the frequency division duplex (FDD) method.
- the duplexer circuit 61 includes a transmission filter circuit 61T and a reception filter circuit 61R.
- the transmission filter circuit 61T (A-Tx) has a pass band including the uplink operation band of band A. As a result, the transmission filter circuit 61T can pass the transmission signal of the band A.
- the transmission filter circuit 61T is connected between the power amplifier circuit 11 and the antenna connection terminal 100. Specifically, the input end of the transmission filter circuit 61T is connected to the output end of the power amplifier circuit 11 via the switch circuit 51 and the impedance matching circuit 41. On the other hand, the output end of the transmission filter circuit 61T is connected to the antenna connection terminal 100 via the impedance matching circuit 43 and the switch circuit 53.
- the reception filter circuit 61R (A-Rx) has a pass band including the downlink operation band of band A. As a result, the reception filter circuit 61R can pass the reception signal of the band A.
- the reception filter circuit 61R is connected between the antenna connection terminal 100 and the low noise amplifier circuit 21. Specifically, the input end of the reception filter circuit 61R is connected to the antenna connection terminal 100 via the impedance matching circuit 43 and the switch circuit 53. On the other hand, the output end of the reception filter circuit 61R is connected to the low noise amplifier circuit 21 via the switch circuit 54 and the impedance matching circuit 42.
- the duplexer circuit 62 can pass a high frequency signal of band B.
- the duplexer circuit 62 transmits the transmission signal and the reception signal of the band B by the FDD method.
- the duplexer circuit 62 includes a transmit filter circuit 62T and a receive filter circuit 62R.
- the transmission filter circuit 62T (B-Tx) has a pass band including the uplink operation band of band B. As a result, the transmission filter circuit 62T can pass the transmission signal of band B.
- the transmission filter circuit 62T is connected between the power amplifier circuit 11 and the antenna connection terminal 100. Specifically, the input end of the transmission filter circuit 62T is connected to the output end of the power amplifier circuit 11 via the switch circuit 51 and the impedance matching circuit 41. On the other hand, the output end of the transmission filter circuit 62T is connected to the antenna connection terminal 100 via the impedance matching circuit 44 and the switch circuit 53.
- the reception filter circuit 62R (B-Rx) has a pass band including the downlink operation band of band B. As a result, the reception filter circuit 62R can pass the reception signal of the band B.
- the reception filter circuit 62R is connected between the antenna connection terminal 100 and the low noise amplifier circuit 21. Specifically, the input end of the reception filter circuit 62R is connected to the antenna connection terminal 100 via the impedance matching circuit 44 and the switch circuit 53. On the other hand, the output end of the reception filter circuit 62R is connected to the low noise amplifier circuit 21 via the switch circuit 54 and the impedance matching circuit 42.
- the control circuit 80 is a power amplifier controller that controls the power amplifier circuit 11.
- the control circuit 80 receives a control signal from the RFIC 3 via the control terminal 130, and outputs the control signal to the power amplifier circuit 11.
- the high frequency module 1 may include at least a power amplifier circuit 11 and an electric circuit (for example, a control circuit 80), and may not include other circuits.
- FIG. 2 is a plan view of the high frequency module 1 according to the embodiment.
- FIG. 3 is a cross-sectional view of the high frequency module 1 according to the embodiment. The cross section of the high frequency module 1 in FIG. 3 is the cross section of the iii-iii line of FIG.
- the high frequency module 1 further includes a module substrate 90, a resin member 91, a shield electrode layer 92, and a plurality of external connection terminals 150, in addition to the components configured in the circuit shown in FIG. In FIG. 2, the resin member 91 and the shield electrode layer 92 are not shown. Further, in FIGS. 2 and 3, the wiring for connecting the plurality of components arranged on the module board 90 is omitted.
- the module board 90 has main surfaces 90a and 90b facing each other.
- the module substrate 90 has a rectangular shape in a plan view, but the shape of the module substrate 90 is not limited to this.
- the module substrate 90 include a low-temperature co-fired ceramics (LTCC: Low Temperature Co-fired Ceramics) substrate having a laminated structure of a plurality of dielectric layers, a high-temperature co-fired ceramics (HTCC: High Temperature Co-fired Ceramics) substrate, and the like.
- LTCC Low Temperature Co-fired Ceramics
- HTCC High Temperature Co-fired Ceramics
- a board having a built-in component, a board having a redistribution layer (RDL: Redistribution Layer), a printed circuit board, or the like can be used, but is not limited thereto.
- RDL Redistribution Layer
- Integrated circuits 20 and 70, impedance matching circuits 41 to 44, switch circuits 53, and duplexer circuits 61 and 62 are arranged on the main surface 90a.
- the main surface 90a and the parts on the main surface 90a are covered with the resin member 91.
- the integrated circuit 20 includes a low noise amplifier circuit 21 and switch circuits 54 and 55.
- the integrated circuit 20 is configured by using, for example, CMOS (Complementary Metal Oxide Semiconductor), and may be specifically manufactured by an SOI (Silicon on Insulator) process. This makes it possible to manufacture the integrated circuit 20 at low cost.
- CMOS Complementary Metal Oxide Semiconductor
- SOI Silicon on Insulator
- the integrated circuit 20 may be composed of at least one of gallium arsenide, silicon germanium (SiGe), and gallium nitride (GaN). This makes it possible to realize a high-quality low-noise amplifier circuit 21 and switch circuits 54 and 55.
- the integrated circuit 70 includes a first base material 71 and a second base material 72.
- the second base material 72 and the first base material 71 are laminated in this order on the main surface 90a of the module substrate 90. Details of the integrated circuit 70 will be described later with reference to FIGS. 4 to 6.
- Each of the impedance matching circuits 41 to 44 includes a matching element.
- a matching element an inductor and / or a capacitor can be used.
- Each of the matching elements included in the impedance matching circuits 41 to 44 is configured by using a surface mount component (SMD: Surface Mount Device). Note that some or all of the matching elements included in the impedance matching circuits 41 to 44 may be configured by using an integrated passive device (IPD).
- SMD Surface Mount Device
- the switch circuit 53 is composed of, for example, a plurality of MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistor) connected in series.
- MOSFETs Metal-Oxide-Semiconductor Field-Effect Transistor
- the number of stages of MOSFETs connected in series may be determined according to the required withstand voltage, and is not particularly limited.
- Each of the duplexer circuits 61 and 62 is configured using, for example, any of a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, an LC resonance filter, and a dielectric filter. It may, and is not limited to, these.
- SAW surface acoustic wave
- BAW bulk acoustic wave
- LC resonance filter an LC resonance filter
- dielectric filter a dielectric filter
- the resin member 91 covers the main surface 90a and the parts on the main surface 90a.
- the resin member 91 has a function of ensuring reliability such as mechanical strength and moisture resistance of the parts on the main surface 90a.
- the resin member 91 may be omitted.
- the shield electrode layer 92 is, for example, a metal thin film formed by a sputtering method, and is formed so as to cover the upper surface and side surfaces of the resin member 91 and the side surfaces of the module substrate 90.
- the shield electrode layer 92 is set to the ground potential and suppresses external noise from invading the components constituting the high frequency module 1.
- a plurality of external connection terminals 150 are arranged on the main surface 90b.
- the plurality of external connection terminals 150 include an antenna connection terminal 100 shown in FIG. 1, high frequency input terminals 111 and 112, high frequency output terminals 121 and 122, and a ground terminal in addition to the control terminal 130.
- Each of the plurality of external connection terminals 150 is joined to an input / output terminal and / or a ground terminal or the like on the mother board arranged in the negative direction of the z-axis of the high frequency module 1.
- a bump electrode can be used, but the present invention is not limited thereto.
- the component arrangement shown in FIGS. 2 and 3 is an example and is not limited thereto.
- some or all of the plurality of parts may be arranged on the main surface 90b of the module board 90.
- the main surface 90b and the parts on the main surface 90b may be covered with the resin member.
- FIGS. 4 and 5 are partial cross-sectional views of the high frequency module 1 according to the embodiment.
- FIG. 6 is a circuit layout diagram in the integrated circuit 70 according to the embodiment. Specifically, FIG. 4 is an enlarged cross-sectional view of the integrated circuit 70, FIG. 5 is an enlarged cross-sectional view of the second base material 72, and FIG. 6 is a perspective plan view of the integrated circuit 70.
- the wiring and the illustration of the electrode are omitted except for a part.
- the broken line indicates the outer shape of the first base material 71, the second base material 72, and the low heat conductive member 73.
- the integrated circuit 70 includes a first base material 71, a second base material 72, and a low heat conductive member 73.
- the first base material 71 will be described. At least a part of the first base material 71 is made of the first semiconductor material.
- silicon (Si) is used as the first semiconductor material.
- the first semiconductor material is not limited to silicon.
- InN indium phosphide
- AlN aluminum nitride
- Si germanium
- SiC silicon carbide
- III gallium oxide
- Ga 2 O 3 gallium oxide
- a switch circuit 51 and 52 and a control circuit 80 are formed on the first base material 71.
- the electric circuit formed on the first base material 71 is not limited to the switch circuits 51 and 52 and the control circuit 80.
- only one or a few of the switch circuits 51 and 52 and the control circuit 80 may be formed on the first substrate 71.
- a control circuit (not shown) for controlling the switch circuit 51 and / or 52 may be formed on the first base material 71.
- at least one of the impedance matching circuits 41 to 44 may be formed on the first base material 71.
- the first base material 71 has surfaces 71a and 71b facing each other.
- the surfaces 71a and 71b are examples of the first surface and the second surface, respectively.
- An electrode 717 is arranged on the surface 71b.
- the first substrate 71 includes a silicon substrate 711, a silicon dioxide (SiO 2 ) layer 712, a silicon layer 713, a silicon dioxide layer 714, and a silicon nitride (SiN) layer 715.
- the silicon dioxide layer 712, the silicon layer 713, the silicon dioxide layer 714, and the silicon nitride layer 715 are laminated on the silicon substrate 711 in this order.
- the silicon substrate 711 is made of, for example, a silicon single crystal and is used as a support substrate.
- the silicon dioxide layer 712 is arranged on the silicon substrate 711 and is used as an insulating layer.
- the silicon layer 713 is arranged on the silicon dioxide layer 712 and is used as a device layer.
- a plurality of circuit elements 7130 constituting the control circuit 80 are formed on the silicon layer 713.
- the silicon dioxide layer 714 is arranged on the silicon layer 713 and is used as a wiring forming layer.
- the silicon dioxide layer 714 is formed with wiring for connecting the control circuit 80 and the switch circuits 51 and 52 formed on the silicon layer 713 to the electrodes 716 formed on the surface of the silicon nitride layer 715.
- This wiring includes a plurality of wiring layers (not shown) and a plurality of via electrodes 7140 connecting the plurality of wiring layers.
- the plurality of wiring layers and the plurality of via electrodes 7140 are made of, for example, copper or aluminum.
- the silicon nitride layer 715 is arranged on the silicon dioxide layer 714 and is used as a passivation layer.
- An electrode 716 is formed as a rewiring layer on a part of the surface of the silicon nitride layer 715. Further, the second base material 72 and the low heat conductive member 73 are bonded to the other part of the surface of the silicon nitride layer 715.
- the electrode 716 is joined to an electrode (not shown) arranged on the module substrate 90 via the electrode 717.
- the surface of the electrode 716 is coated with a resin layer 718 as an insulating film.
- the plurality of electrodes 717 is an example of the first electrode.
- Each of the plurality of electrodes 717 is an electrode protruding from the first base material 71 toward the main surface 90a of the module substrate 90, and the tip thereof is joined to the main surface 90a.
- Each of the plurality of electrodes 717 has a columnar conductor 717a and a bump electrode 717b.
- the bump electrode 717b is joined to an electrode (not shown) arranged on the main surface 90a of the module substrate 90.
- the first base material 71 is not limited to the configuration shown in FIG.
- the first substrate 71 may not include one or some of the plurality of layers on the silicon substrate 711.
- the second base material 72 will be described. At least a part of the second base material 72 is made of a second semiconductor material having a lower thermal conductivity than the first semiconductor material. Gallium arsenide is used as the second semiconductor material. The second semiconductor material is not limited to gallium arsenide.
- a power amplifier circuit 11 is formed on the second base material 72. Specifically, on the second base material 72, a plurality of circuit elements 721 and electrodes for applying a voltage to the plurality of circuit elements 721 (not shown) or electrodes for supplying a current (FIG.). (Not shown) and are formed.
- the plurality of circuit elements 721 are, for example, heterojunction bipolar transistors (HBTs) in which a plurality of unit transistors are connected in parallel, and constitute a power amplifier circuit 11.
- HBTs heterojunction bipolar transistors
- the second base material 72 has surfaces 72a and 72b facing each other.
- the surfaces 72a and 72b are examples of the third surface and the fourth surface, respectively.
- An electrode 724 is arranged on the surface 72b.
- the second base material 72 includes a semiconductor layer 72A, an epitaxial layer 72B formed on the surface of the semiconductor layer 72A, a plurality of circuit elements 721, and electrodes 722 and 733.
- the semiconductor layer 72A is made of a second semiconductor material and is bonded to the silicon nitride layer 715 of the first base material 71.
- the semiconductor layer 72A is, for example, a GaAs layer.
- the circuit element 721 has a collector layer 721C, a base layer 721B, and an emitter layer 721E.
- the collector layer 721C, the base layer 721B, and the emitter layer 721E are laminated on the epitaxial layer 72B in this order. That is, in the circuit element 721, the collector layer 721C, the base layer 721B, and the emitter layer 721E are laminated in this order from the first base material 71 side.
- the collector layer 721C is composed of n-type gallium arsenide
- the base layer 721B is composed of p-type gallium arsenide
- the emitter layer 721E is composed of n-type indium gallium phosphide (InGaP).
- the emitter layer 721E is bonded to the electrode 723 via an electrode 722 formed on the surface of the second base material 72.
- the electrode 723 is joined to the main surface 90a of the module substrate 90 via the electrode 724.
- the electrode 724 is an example of the second electrode, and protrudes from the second base material 72 toward the main surface 90a of the module substrate 90, and the tip thereof is joined to the main surface 90a.
- the electrode 724 functions as a heat dissipation path for the heat generated by the power amplifier circuit 11.
- the electrode 724 has a columnar conductor 724a and a bump electrode 724b.
- the bump electrode 724b is bonded to an electrode (not shown) arranged on the main surface 90a of the module substrate 90.
- the second base material 72 is not limited to the configurations shown in FIGS. 4 and 5.
- the low heat conductive member 73 will be described. At least a part of the low thermal conductive member 73 is made of a low thermal conductive material having a lower thermal conductivity than the second semiconductor material.
- a low thermal conductivity material glass, synthetic polymer compounds and the like can be used.
- the synthetic polymer compound an epoxy resin can be used, and other synthetic resins or synthetic rubbers may be used.
- the low heat conductive member 73 is formed between an electric circuit formed on the first base material 71 (for example, a control circuit 80, a switch circuit 51 or 52, etc.) and a power amplification circuit 11 formed on the second base material 72. Have been placed.
- the low heat conductive member 73 is arranged on the surface 71b of the first base material 71, and is arranged between the control circuit 80 and the power amplification circuit 11 in a cross-sectional view.
- the arrangement of the low heat conductive member 73 is not limited to the arrangement shown in FIG.
- the low heat conductive member 73 may be arranged in the first base material 71.
- the low heat conductive member 73 has surfaces 73a and 73b.
- the surface 73a is in contact with the surface 71b of the first base material 71.
- a part of the surface 73b is in contact with the surface 72a of the second base material 72.
- the shape of the low heat conductive member 73 is not limited to the sheet shape.
- the low heat conductive member 73 may have a block shape.
- the low heat conductive member 73 may include a plurality of layers. In this case, at least one of the plurality of layers may be composed of a low thermal conductive material.
- a part of the low heat conductive member 73 overlaps with a part of the electric circuit (control circuit 80, switch circuit 51 and 52) formed on the first base material 71 in a plan view. Further, another part of the low heat conductive member 73 overlaps with a part of the power amplifier circuit 11 in a plan view.
- the circuit arrangement in the integrated circuit 70 in FIG. 6 is merely an example, and is not limited to this arrangement.
- the low heat conductive member 73 does not have to overlap with the power amplifier circuit 11 and / or the control circuit 80 or the like in a plan view.
- the integrated circuit 70 is the first unit in which at least a part thereof is composed of the first semiconductor material and the electric circuit (for example, the control circuit 80 or the switch circuit 51 or 52) is formed.
- a second base material 72 in which the material 71 is composed of at least a second semiconductor material having a lower thermal conductivity than the first semiconductor material and a power amplification circuit 11 is formed, and at least a part of the second semiconductor. It comprises a low heat conductive member 73, which is made of a low heat conductive material having a lower heat conductivity than the material and is arranged between an electric circuit and a power amplification circuit 11, and at least a part of the first base material 71 is a flat surface. Visually, it overlaps with at least a part of the second base material 72.
- the integrated circuit 70 is a miniaturization of the high frequency module 1. Can contribute to. Further, the heat generated by the power amplifier circuit 11 formed on the second base material 72 is further composed of the first semiconductor material having a higher thermal conductivity than the second semiconductor material constituting the second base material 72. It can be discharged to the first base material 71. At this time, since the low heat conductive member 73 having a lower heat conductivity than that of the second semiconductor material is arranged between the power amplification circuit 11 and the electric circuit, heat transfer from the power amplification circuit 11 to the electric circuit is suppressed. It is possible to suppress deterioration of the characteristics of the electric circuit due to heat.
- At least a part of the low heat conductive member 73 may overlap with at least a part of the electric circuit in a plan view.
- the low heat conduction member 73 can effectively suppress heat transfer from the power amplifier circuit 11 to the electric circuit, and can suppress deterioration of the characteristics of the electric circuit due to heat.
- At least a part of the low heat conductive member 73 may overlap with at least a part of the power amplifier circuit 11 in a plan view.
- the low heat conduction member 73 can effectively suppress heat transfer from the power amplifier circuit 11 to the electric circuit, and can suppress deterioration of the characteristics of the electric circuit due to heat.
- the low heat conductive member 73 may have a sheet shape.
- the low heat conductive member 73 can widely block the heat transfer path from the power amplification circuit 11 to the electric circuit, it is possible to effectively suppress the heat transfer from the power amplification circuit 11 to the electric circuit. It is possible to suppress deterioration of the characteristics of the electric circuit due to heat.
- the electric circuit includes a control circuit 80 for controlling the power amplifier circuit 11, a switch circuit 51 connected to the output end of the power amplifier circuit 11, and a power amplifier circuit 11. It may include at least one of a switch circuit 52 connected to the input end of the.
- At least one of the control circuit 80 and the switch circuits 51 and 52 connected to the power amplification circuit 11 formed on the second base material 72 is formed on the first base material 71, so that the power amplification
- the wiring length between the circuit 11 and the control circuit 80 and at least one of the switch circuits 51 and 52 can be shortened. Therefore, it is possible to reduce the influence of digital noise due to the control signal, and reduce the wiring loss and the inconsistency loss due to the stray capacitance of the wiring.
- the first base material 71 is arranged on the surface 71a, the surface 71b on the opposite side of the surface 71a and facing the second base material 72, and the surface 71b. It may have an electrode 717 and the like.
- the heat in the first base material 71 can be discharged to the module substrate 90 via the electrode 717, and the heat dissipation of the integrated circuit 70 can be improved.
- the second base material 72 has a surface 72a facing the first base material 71, a surface 72b on the opposite side of the surface 72a, and electrodes arranged on the surface 72b. 724 and may have.
- heat can be discharged from the surface 72b of the second base material 72 to the module substrate 90 via the electrode 724, and the heat dissipation of the integrated circuit 70 can be improved.
- the power amplifier circuit 11 includes a circuit element 721 having a collector layer 721C, a base layer 721B, and an emitter layer 721E, and includes a collector layer 721C, a base layer 721B, and an emitter layer 721E. May be laminated in this order from the first base material 71 side.
- the area of the collector layer 721C is larger than the area of each of the base layer 721B and the emitter layer 721E. Therefore, by joining the collector layer 721C to the first base material 71, the joining area can be increased as compared with the case where the base layer 721B or the emitter layer 721E is joined to the first base material 71. As a result, it is possible to strengthen the bonding between the first base material 71 and the second base material 72 and prevent the second base material 72 from peeling off from the first base material 71.
- the integrated circuit 70 has a first base material 71 in which at least a part thereof is made of silicon or gallium nitride and an electric circuit (for example, a control circuit 80 or a switch circuit 51 or 52) is formed.
- an electric circuit for example, a control circuit 80 or a switch circuit 51 or 52
- the second substrate 72 which is at least partially composed of gallium arsenic or silicon germanium and has a power amplification circuit 11 formed, and the electric circuit and the power amplification circuit 11 which is at least partially composed of glass or epoxy resin.
- the low thermal conductive member 73 arranged in the above is provided, and at least a part of the first base material 71 overlaps with at least a part of the second base material 72 in a plan view.
- the integrated circuit 70 is a miniaturization of the high frequency module 1. Can contribute to. Further, the heat generated by the power amplification circuit 11 formed on the second base material 72 is composed of silicon or gallium nitride having a higher thermal conductivity than gallium arsenide or silicon germanium constituting the second base material 72. It can be discharged to the first base material 71.
- the low heat conductive member 73 made of glass or epoxy resin having a lower heat conductivity than that of the second semiconductor material is arranged between the power amplification circuit 11 and the electric circuit, electricity is supplied from the power amplification circuit 11. It is possible to suppress heat transfer to the circuit, and it is possible to suppress deterioration of the characteristics of the electric circuit due to heat.
- the high frequency module 1 includes a module substrate 90 having a main surface 90a and an integrated circuit 70 arranged on the main surface 90a, and the first base material 71 has a main surface via an electrode 717. It is bonded to 90a, and the second base material 72 is bonded to the main surface 90a via the electrode 724.
- the heat generated by the power amplifier circuit 11 formed on the second base material 72 is composed of the first semiconductor material having a higher thermal conductivity than the second semiconductor material constituting the second base material 72. It can be effectively discharged to the module substrate 90 via the first base material 71 and the electrode 717.
- the low heat conductive member 73 having a low heat conductivity is arranged between the electric circuit and the power amplification circuit 11, the amount of heat transfer from the power amplification circuit 11 to the electric circuit is suppressed, and the characteristics of the electric circuit due to heat are suppressed. Deterioration can be suppressed.
- the communication device 5 includes an RFIC 3 for processing a high frequency signal and a high frequency module 1 for transmitting a high frequency signal between the RFIC 3 and the antenna 2.
- the same effect as that of the high frequency module 1 can be realized.
- circuit configuration diagram, the plan view, and the cross-sectional view of the high frequency module 1 according to the present modification are the same as those of the high frequency module 1 according to the above embodiment, the illustration and description are omitted, and the integration according to the present modification is omitted.
- the configuration of the circuit 70A will be described with reference to FIG. 7.
- FIG. 7 is a partial cross-sectional view of the high frequency module 1 according to the modified example. Specifically, FIG. 7 is an enlarged cross-sectional view of the integrated circuit 70A. In FIG. 7, the wiring and the illustration of the electrodes are omitted except for a part.
- the integrated circuit 70A has a gap portion 73A instead of the low heat conductive member 73.
- the void portion 73A is a space formed in the first base material 71 and has a lower thermal conductivity than the second base material 72.
- the gap portion 73A is arranged between the control circuit 80 and the power amplifier circuit 11 in a cross-sectional view.
- the void portion 73A is a void intentionally formed into a predetermined shape, unlike bubbles that can be uniformly or randomly mixed in the first base material 71. Therefore, the gap portion 73A can have a non-spherical shape, and in FIG. 7, it spreads like a sheet along the xy plane in the first base material 71.
- Non-spherical shape means a shape that is not spherical.
- the arrangement and shape of the gap portion 73A is not limited to the arrangement and shape of FIG. 7.
- the integrated circuit 70A is a first base material in which at least a part thereof is made of a first semiconductor material and an electric circuit (for example, a control circuit 80 or a switch circuit 51 or 52) is formed.
- the first base material 71 comprises 71 and a second base material 72 in which at least a part thereof is composed of a second semiconductor material having a lower thermal conductivity than the first semiconductor material and a power amplification circuit 11 is formed.
- a gap portion 73A located between the electric circuit and the power amplification circuit 11 is formed inside the first base material 71, and at least a part of the first base material 71 is at least a part of the second base material 72 in a plan view. overlapping.
- the integrated circuit 70 is a miniaturization of the high frequency module 1. Can contribute to. Further, the heat generated by the power amplifier circuit 11 formed on the second base material 72 is further composed of the first semiconductor material having a higher thermal conductivity than the second semiconductor material constituting the second base material 72. It can be discharged to the first base material 71. At this time, since the gap portion 73A is arranged between the power amplification circuit 11 and the electric circuit, heat transfer from the power amplification circuit 11 to the electric circuit can be suppressed, and deterioration of the characteristics of the electric circuit due to heat can be suppressed. It can be suppressed.
- At least a part of the gap portion 73A may overlap with at least a part of the electric circuit in a plan view.
- the gap portion 73A can effectively suppress heat transfer from the power amplifier circuit 11 to the electric circuit, and can suppress deterioration of the characteristics of the electric circuit due to heat.
- At least a part of the gap portion 73A may overlap with at least a part of the power amplifier circuit 11 in a plan view.
- the gap portion 73A can effectively suppress heat transfer from the power amplifier circuit 11 to the electric circuit, and can suppress deterioration of the characteristics of the electric circuit due to heat.
- the gap portion 73A may have a non-spherical shape.
- a non-spherical shape can be used as the shape of the gap portion 73A, and by adopting a shape suitable for the arrangement of the power amplification circuit 11 and the electric circuit, heat is transferred from the power amplification circuit 11 to the electric circuit. Can be effectively suppressed, and deterioration of the characteristics of the electric circuit due to heat can be suppressed.
- the gap portion 73A may be spread in a sheet shape in the first base material 71.
- the heat transfer path from the power amplification circuit 11 to the electric circuit can be widely blocked, the heat transfer from the power amplification circuit 11 to the electric circuit can be effectively suppressed, and the electric circuit due to heat can be effectively suppressed. It is possible to suppress the deterioration of the characteristics of.
- the electric circuit includes a control circuit 80 for controlling the power amplifier circuit 11, a switch circuit 51 connected to the output end of the power amplifier circuit 11, and a power amplifier circuit 11. It may include at least one of a switch circuit 52 connected to the input end.
- At least one of the control circuit 80 and the switch circuits 51 and 52 connected to the power amplification circuit 11 formed on the second base material 72 is formed on the first base material 71, so that the power amplification
- the wiring length between the circuit 11 and the control circuit 80 and at least one of the switch circuits 51 and 52 can be shortened. Therefore, it is possible to reduce the influence of digital noise due to the control signal, and reduce the wiring loss and the inconsistency loss due to the stray capacitance of the wiring.
- the first base material 71 has a surface 71a, a surface 71b on the opposite side of the surface 71a and facing the second base material 72, and an electrode arranged on the surface 71b. 717 and may have.
- the heat in the first base material 71 can be discharged to the module substrate 90 via the electrode 717, and the heat dissipation of the integrated circuit 70A can be improved.
- the second base material 72 has a surface 72a facing the first base material 71, a surface 72b on the opposite side of the surface 72a, and an electrode 724 arranged on the surface 72b. And may have.
- heat can be discharged from the surface 72b of the second base material 72 to the module substrate 90 via the electrode 724, and the heat dissipation of the integrated circuit 70A can be improved.
- the power amplifier circuit 11 includes a circuit element 721 having a collector layer 721C, a base layer 721B, and an emitter layer 721E, and the collector layer 721C, the base layer 721B, and the emitter layer 721E are included. , May be laminated in this order from the first base material 71 side.
- the area of the collector layer 721C is larger than the area of each of the base layer 721B and the emitter layer 721E. Therefore, by joining the collector layer 721C to the first base material 71, the joining area can be increased as compared with the case where the base layer 721B or the emitter layer 721E is joined to the first base material 71. As a result, it is possible to strengthen the bonding between the first base material 71 and the second base material 72 and prevent the second base material 72 from peeling off from the first base material 71.
- the integrated circuit 70A is a first base material in which at least a part thereof is made of silicon or gallium nitride and an electric circuit (for example, a control circuit 80 or a switch circuit 51 or 52) is formed.
- a second base material 72 in which at least a part thereof is composed of gallium arsenic or silicon germanium and a power amplification circuit 11 is formed is provided, and an electric circuit and a power amplification circuit are provided inside the first base material 71.
- a gap portion 73A located between 11 is formed, and at least a part of the first base material 71 overlaps with at least a part of the second base material 72 in a plan view.
- the integrated circuit 70 is a miniaturization of the high frequency module 1. Can contribute to. Further, the heat generated by the power amplification circuit 11 formed on the second base material 72 is composed of silicon or gallium nitride having a higher thermal conductivity than gallium arsenide or silicon germanium constituting the second base material 72. It can be discharged to the first base material 71.
- the gap portion 73A is arranged between the power amplification circuit 11 and the electric circuit, heat transfer from the power amplification circuit 11 to the electric circuit can be suppressed, and deterioration of the characteristics of the electric circuit due to heat can be suppressed. It can be suppressed.
- the high frequency module 1 includes a module substrate 90 having a main surface 90a and an integrated circuit 70 arranged on the main surface 90a, and the first base material 71 has a main surface 90a via an electrode 717.
- the second base material 72 is bonded to the main surface 90a via the electrode 724.
- the heat generated by the power amplifier circuit 11 formed on the second base material 72 is composed of the first semiconductor material having a higher thermal conductivity than the second semiconductor material constituting the second base material 72. It can be effectively discharged to the module substrate 90 via the first base material 71 and the electrode 717. At this time, since the gap portion 73A is formed between the electric circuit and the power amplification circuit 11, the amount of heat transfer from the power amplification circuit 11 to the electric circuit is suppressed, and deterioration of the characteristics of the electric circuit due to heat is suppressed. Can be done.
- the high-frequency module 1 corresponds to the FDD band, but is not limited to this.
- the high frequency module 1 may correspond to a time division duplex (TDD: Time Division Duplex) band, or may correspond to both an FDD band and a TDD band.
- the high frequency module 1 may include a filter circuit having a pass band including a band for TDD, and a switch circuit for switching transmission and reception.
- the present invention can be widely used in communication devices such as mobile phones as a high frequency module arranged in the front end portion.
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Abstract
An integrated circuit (70) comprises: a first substrate (71) at least partially composed of a first semiconductor material and having an electric circuit (for example, a control circuit (80) or a switch circuit (51, 52)); a second substrate (72) which is at least partially composed of a second semiconductor material having a thermal conductivity lower than that of the first semiconductor material, and has a power amplifier circuit (11); and a low thermal conductivity member (73) which is at least partially composed of a low thermal conductivity material having a thermal conductivity lower than that of the second semiconductor material, and is disposed between the electric circuit and the power amplifier circuit (11). At least a part of the first substrate (71) overlaps at least a part of the second substrate (72) in plan view.
Description
本発明は、集積回路及び高周波モジュールに関する。
The present invention relates to integrated circuits and high frequency modules.
携帯電話などの移動体通信機器では、特に、マルチバンド化の進展に伴い、高周波フロントエンド回路を構成する回路素子の配置構成が複雑化されている。
In mobile communication devices such as mobile phones, the arrangement of circuit elements constituting high-frequency front-end circuits has become complicated, especially with the progress of multi-band.
特許文献１の高周波モジュールでは、パッケージ基板上に配置された電力増幅器の上方にコントローラを積層することで、高周波モジュールの小型化が実現されている。
In the high frequency module of Patent Document 1, the miniaturization of the high frequency module is realized by stacking the controller on the power amplifier arranged on the package substrate.
しかしながら、上記従来技術では、電力増幅器で発生した熱によって、電力増幅器上に積層された電気回路（コントローラ）が加熱され、電気回路の特性が劣化する場合がある。
However, in the above-mentioned conventional technique, the electric circuit (controller) laminated on the electric power amplifier may be heated by the heat generated by the electric power amplifier, and the characteristics of the electric circuit may be deteriorated.
そこで、本発明は、高周波モジュールの小型化に貢献することができ、熱による電気回路の特性の劣化を抑制することができる集積回路及び高周波モジュールを提供する。
Therefore, the present invention provides an integrated circuit and a high frequency module that can contribute to the miniaturization of the high frequency module and suppress the deterioration of the characteristics of the electric circuit due to heat.
本発明の一態様に係る集積回路は、少なくとも一部が第１半導体材料で構成され、電気回路が形成された第１基材と、少なくとも一部が第１半導体材料よりも低い熱伝導率を有する第２半導体材料で構成され、電力増幅回路が形成された第２基材と、少なくとも一部が第２半導体材料よりも低い熱伝導率を有する低熱伝導材料で構成され、電気回路及び電力増幅回路の間に配置された低熱伝導部材と、を備え、第１基材の少なくとも一部は、平面視において第２基材の少なくとも一部と重なっている。
The integrated circuit according to one aspect of the present invention has a first base material in which at least a part is composed of a first semiconductor material and an electric circuit is formed, and at least a part has a lower thermal conductivity than the first semiconductor material. It is composed of a second base material formed of a second semiconductor material having a power amplification circuit, and a low heat conduction material having at least a part having a lower thermal conductivity than that of the second semiconductor material, and is composed of an electric circuit and power amplification. It comprises a low thermal conductive member disposed between the circuits, and at least a part of the first base material overlaps with at least a part of the second base material in a plan view.
本発明の一態様に係る集積回路は、少なくとも一部がシリコン又は窒化ガリウムで構成され、電気回路が形成された第１基材と、少なくとも一部がガリウムヒ素又はシリコンゲルマニウムで構成され、電力増幅回路が形成された第２基材と、少なくとも一部がガラス又はエポキシ樹脂で構成され、電気回路及び電力増幅回路の間に配置された低熱伝導部材と、を備え、第１基材の少なくとも一部は、平面視において第２基材の少なくとも一部と重なっている。
The integrated circuit according to one aspect of the present invention is composed of a first substrate in which at least a part is made of silicon or gallium nitride and an electric circuit is formed, and at least a part is made of gallium arsenic or silicon germanium, and power is amplified. It comprises a second substrate on which a circuit is formed and a low thermal conductivity member which is at least partially composed of glass or epoxy resin and is arranged between an electric circuit and a power amplifier circuit, and at least one of the first substrates. The portion overlaps at least a part of the second base material in a plan view.
本発明の一態様に係る集積回路は、少なくとも一部が第１半導体材料で構成され、電気回路が形成された第１基材と、少なくとも一部が第１半導体材料よりも低い熱伝導率を有する第２半導体材料で構成され、電力増幅回路が形成された第２基材と、を備え、第１基材の内部には、電気回路及び電力増幅回路の間に位置する空隙部が形成されており、第１基材の少なくとも一部は、平面視において第２基材の少なくとも一部と重なっている。
The integrated circuit according to one aspect of the present invention has a first base material in which at least a part is composed of a first semiconductor material and an electric circuit is formed, and at least a part has a lower thermal conductivity than the first semiconductor material. It is provided with a second base material made of a second semiconductor material and having a power amplification circuit formed therein, and a gap portion located between an electric circuit and a power amplification circuit is formed inside the first base material. At least a part of the first base material overlaps with at least a part of the second base material in a plan view.
本発明の一態様に係る集積回路は、少なくとも一部がシリコン又は窒化ガリウムで構成され、電気回路が形成された第１基材と、少なくとも一部がガリウムヒ素又はシリコンゲルマニウムで構成され、電力増幅回路が形成された第２基材と、を備え、第１基材の内部には、電気回路及び電力増幅回路の間に位置する空隙部が形成されており、第１基材の少なくとも一部は、平面視において第２基材の少なくとも一部と重なっている。
The integrated circuit according to one aspect of the present invention is composed of a first substrate in which at least a part is made of silicon or gallium nitride and an electric circuit is formed, and at least a part is made of gallium arsenic or silicon germanium, and power is amplified. A second base material on which a circuit is formed is provided, and a gap portion located between an electric circuit and a power amplifier circuit is formed inside the first base material, and at least a part of the first base material. Overlaps at least a portion of the second substrate in plan view.
本発明の一態様に係る集積回路によれば、高周波モジュールの小型化に貢献することができ、熱による電力増幅回路の特性の劣化を抑制することができる。
According to the integrated circuit according to one aspect of the present invention, it is possible to contribute to the miniaturization of the high frequency module and suppress the deterioration of the characteristics of the power amplifier circuit due to heat.
以下、本発明の実施の形態について、図面を用いて詳細に説明する。なお、以下で説明する実施の形態は、いずれも包括的又は具体的な例を示すものである。以下の実施の形態で示される数値、形状、材料、構成要素、構成要素の配置及び接続形態などは、一例であり、本発明を限定する主旨ではない。
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. It should be noted that all of the embodiments described below show comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement of components, connection modes, etc. shown in the following embodiments are examples, and are not intended to limit the present invention.
なお、各図は、本発明を示すために適宜強調、省略、又は比率の調整を行った模式図であり、必ずしも厳密に図示されたものではなく、実際の形状、位置関係、及び比率とは異なる場合がある。各図において、実質的に同一の構成に対しては同一の符号を付しており、重複する説明は省略又は簡素化される場合がある。
It should be noted that each figure is a schematic diagram in which emphasis, omission, or ratio is adjusted as appropriate to show the present invention, and is not necessarily exactly illustrated. What is the actual shape, positional relationship, and ratio? May be different. In each figure, substantially the same configuration is designated by the same reference numeral, and duplicate description may be omitted or simplified.
以下の各図において、ｘ軸及びｙ軸は、モジュール基板の主面と平行な平面上で互いに直交する軸である。具体的には、平面視においてモジュール基板が矩形状を有する場合、ｘ軸は、モジュール基板の第１辺に平行であり、ｙ軸は、モジュール基板の第１辺と直交する第２辺に平行である。また、ｚ軸は、モジュール基板の主面に垂直な軸であり、その正方向は上方向を示し、その負方向は下方向を示す。
In each of the following figures, the x-axis and the y-axis are axes orthogonal to each other on a plane parallel to the main surface of the module substrate. Specifically, when the module substrate has a rectangular shape in a plan view, the x-axis is parallel to the first side of the module substrate and the y-axis is parallel to the second side orthogonal to the first side of the module substrate. Is. Further, the z-axis is an axis perpendicular to the main surface of the module substrate, the positive direction thereof indicates an upward direction, and the negative direction thereof indicates a downward direction.
本発明の回路構成において、「接続される」とは、接続端子及び／又は配線導体で直接接続される場合だけでなく、他の回路素子を介して電気的に接続される場合も含む。また、「Ａ及びＢの間に接続される」とは、Ａ及びＢの間でＡ及びＢの両方に接続されることを意味する。
In the circuit configuration of the present invention, "connected" includes not only the case of being directly connected by a connection terminal and / or a wiring conductor, but also the case of being electrically connected via another circuit element. Further, "connected between A and B" means that both A and B are connected between A and B.
本発明の部品配置において、「平面視」とは、ｚ軸正側からｘｙ平面に物体を正投影して見ることを意味する。「平面視において、ＡはＢと重なる」とは、ｘｙ平面に正投影されたＡの領域が、ｘｙ平面に正投影されたＢの領域と重なることを意味する。「断面視」とは、ｘｙ平面に垂直な断面で切断して見ることを意味する。「断面視においてＡがＢ及びＣの間に配置される」とは、ｘｙ平面に垂直な断面において、Ｂの領域内の任意の点とＣの領域内の任意の点とを結ぶ複数の線分のうちの少なくとも１つがＡの領域を通ることを意味する。「ＡがＢ及びＣの間に配置される」とは、Ｂ内の任意の点とＣ内の任意の点とを結ぶ複数の線分のうちの少なくとも１つがＡを通ることを意味する。また、「平行」及び「垂直」などの要素間の関係性を示す用語、及び、「矩形」などの要素の形状を示す用語、並びに、数値範囲は、厳格な意味のみを表すのではなく、実質的に同等な範囲、例えば数％程度の誤差をも含むことを意味する。
In the component arrangement of the present invention, "planar view" means that an object is projected orthographically projected onto the xy plane from the positive side of the z-axis. "A overlaps with B in a plan view" means that the region of A orthographically projected on the xy plane overlaps with the region of B orthographically projected on the xy plane. "Cross-section view" means to cut and view in a cross-section perpendicular to the xy plane. "A is arranged between B and C in a cross-sectional view" means a plurality of lines connecting an arbitrary point in the region of B and an arbitrary point in the region of C in a cross section perpendicular to the xy plane. It means that at least one of the minutes passes through the region of A. "A is placed between B and C" means that at least one of a plurality of line segments connecting any point in B and any point in C passes through A. In addition, terms that indicate relationships between elements such as "parallel" and "vertical", terms that indicate the shape of elements such as "rectangle", and numerical ranges do not mean only strict meanings. It means that a substantially equivalent range, for example, an error of about several percent is included.
また、「部品が基板に配置される」とは、部品が基板と接触した状態で基板上に配置されることに加えて、基板と接触せずに基板の上方に配置されること（例えば、部品が、基板上に配置された他の部品上に積層されること）、及び、部品の一部又は全部が基板内に埋め込まれて配置されることを含む。また、「部品が基板の主面に配置される」とは、部品が基板の主面と接触した状態で主面上に配置されることに加えて、部品が主面と接触せずに主面の上方に配置されること、及び、部品の一部が主面側から基板内に埋め込まれて配置されることを含む。
Further, "the component is arranged on the substrate" means that the component is arranged on the substrate in a state of being in contact with the substrate and is arranged above the substrate without contacting the substrate (for example,). The component is laminated on another component arranged on the substrate), and a part or all of the component is embedded and arranged in the substrate. Further, "the component is arranged on the main surface of the board" means that the component is arranged on the main surface in a state of being in contact with the main surface of the board, and the component is mainly arranged without contacting the main surface. This includes arranging above the surface and embedding a part of the component in the substrate from the main surface side.
本発明の材料構成において、「物体Ａが材料Ｂで構成される」とは、Ａの主成分がＢであることを意味する。ここで、主成分とは、物体に含まれる複数の成分のうち最も大きい重量比率を有する成分を意味する。
In the material composition of the present invention, "the object A is composed of the material B" means that the main component of A is B. Here, the principal component means a component having the largest weight ratio among a plurality of components contained in an object.
（実施の形態）
［１．１ 高周波モジュール１及び通信装置５の回路構成］
本実施の形態に係る高周波モジュール１及びそれを備える通信装置５の回路構成について、図１を参照しながら説明する。図１は、実施の形態に係る高周波モジュール１及び通信装置５の回路構成図である。 (Embodiment)
[1.1 Circuit configuration ofhigh frequency module 1 and communication device 5]
The circuit configuration of thehigh frequency module 1 and the communication device 5 including the high frequency module 1 according to the present embodiment will be described with reference to FIG. FIG. 1 is a circuit configuration diagram of a high frequency module 1 and a communication device 5 according to an embodiment.
［１．１ 高周波モジュール１及び通信装置５の回路構成］
本実施の形態に係る高周波モジュール１及びそれを備える通信装置５の回路構成について、図１を参照しながら説明する。図１は、実施の形態に係る高周波モジュール１及び通信装置５の回路構成図である。 (Embodiment)
[1.1 Circuit configuration of
The circuit configuration of the
［１．１．１ 通信装置５の回路構成］
図１に示すように、本実施の形態に係る通信装置５は、高周波モジュール１と、アンテナ２と、ＲＦＩＣ（Radio Frequency Integrated Circuit）３と、ＢＢＩＣ（Baseband Integrated Circuit）４と、を備える。 [1.1.1 Circuit configuration of communication device 5]
As shown in FIG. 1, thecommunication device 5 according to the present embodiment includes a high frequency module 1, an antenna 2, an RFIC (Radio Frequency Integrated Circuit) 3, and a BBIC (Baseband Integrated Circuit) 4.
図１に示すように、本実施の形態に係る通信装置５は、高周波モジュール１と、アンテナ２と、ＲＦＩＣ（Radio Frequency Integrated Circuit）３と、ＢＢＩＣ（Baseband Integrated Circuit）４と、を備える。 [1.1.1 Circuit configuration of communication device 5]
As shown in FIG. 1, the
高周波モジュール１は、アンテナ２とＲＦＩＣ３との間で高周波信号を伝送する。高周波モジュール１の内部構成については後述する。
The high frequency module 1 transmits a high frequency signal between the antenna 2 and the RFIC 3. The internal configuration of the high frequency module 1 will be described later.
アンテナ２は、高周波モジュール１のアンテナ接続端子１００に接続され、外部から高周波信号を受信して高周波モジュール１へ出力する。
The antenna 2 is connected to the antenna connection terminal 100 of the high frequency module 1, receives a high frequency signal from the outside, and outputs the high frequency signal to the high frequency module 1.
ＲＦＩＣ３は、高周波信号を処理する信号処理回路の一例である。具体的には、ＲＦＩＣ３は、高周波モジュール１の受信経路を介して入力された高周波受信信号を、ダウンコンバート等により信号処理し、当該信号処理して生成された受信信号をＢＢＩＣ４へ出力する。また、ＲＦＩＣ３は、高周波モジュール１が有するスイッチ回路及び増幅回路等を制御する制御部を有する。なお、ＲＦＩＣ３の制御部としての機能の一部又は全部は、ＲＦＩＣ３の外部に構成されてもよく、例えば、ＢＢＩＣ４又は高周波モジュール１に構成されてもよい。
RFIC3 is an example of a signal processing circuit that processes high frequency signals. Specifically, the RFIC 3 processes the high frequency reception signal input via the reception path of the high frequency module 1 by down-conversion or the like, and outputs the reception signal generated by the signal processing to the BBIC 4. Further, the RFIC 3 has a control unit that controls a switch circuit, an amplifier circuit, and the like included in the high frequency module 1. A part or all of the function of the RFIC3 as a control unit may be configured outside the RFIC3, or may be configured in, for example, the BBIC4 or the high frequency module 1.
ＢＢＩＣ４は、高周波モジュール１が伝送する高周波信号よりも低周波の中間周波数帯域を用いて信号処理するベースバンド信号処理回路である。ＢＢＩＣ４で処理される信号としては、例えば、画像表示のための画像信号、及び／又は、スピーカを介した通話のために音声信号が用いられる。
The BBIC 4 is a baseband signal processing circuit that processes signals using an intermediate frequency band having a lower frequency than the high frequency signal transmitted by the high frequency module 1. As the signal processed by the BBIC 4, for example, an image signal for displaying an image and / or an audio signal for a call via a speaker are used.
なお、本実施の形態に係る通信装置５において、アンテナ２とＢＢＩＣ４とは、必須の構成要素ではない。
In the communication device 5 according to the present embodiment, the antenna 2 and the BBIC 4 are not essential components.
［１．１．２ 高周波モジュール１の回路構成］
次に、高周波モジュール１の回路構成について説明する。図１に示すように、高周波モジュール１は、電力増幅回路１１と、低雑音増幅回路２１と、インピーダンス整合回路（ＭＮ）４１～４４と、スイッチ回路５１～５５と、デュプレクサ回路６１及び６２と、制御回路８０と、アンテナ接続端子１００と、高周波入力端子１１１及び１１２と、高周波出力端子１２１及び１２２と、制御端子１３０と、を備える。 [1.1.2 Circuit configuration of high frequency module 1]
Next, the circuit configuration of thehigh frequency module 1 will be described. As shown in FIG. 1, the high frequency module 1 includes a power amplifier circuit 11, a low noise amplifier circuit 21, an impedance matching circuit (MN) 41 to 44, a switch circuit 51 to 55, and a duplexer circuit 61 and 62. It includes a control circuit 80, an antenna connection terminal 100, high frequency input terminals 111 and 112, high frequency output terminals 121 and 122, and a control terminal 130.
次に、高周波モジュール１の回路構成について説明する。図１に示すように、高周波モジュール１は、電力増幅回路１１と、低雑音増幅回路２１と、インピーダンス整合回路（ＭＮ）４１～４４と、スイッチ回路５１～５５と、デュプレクサ回路６１及び６２と、制御回路８０と、アンテナ接続端子１００と、高周波入力端子１１１及び１１２と、高周波出力端子１２１及び１２２と、制御端子１３０と、を備える。 [1.1.2 Circuit configuration of high frequency module 1]
Next, the circuit configuration of the
アンテナ接続端子１００は、高周波モジュール１の外部でアンテナ２に接続されている。
The antenna connection terminal 100 is connected to the antenna 2 outside the high frequency module 1.
高周波入力端子１１１及び１１２の各々は、高周波モジュール１の外部から高周波送信信号を受けるための入力端子である。本実施の形態では、高周波入力端子１１１及び１１２は、高周波モジュール１の外部でＲＦＩＣ３に接続されている。
Each of the high frequency input terminals 111 and 112 is an input terminal for receiving a high frequency transmission signal from the outside of the high frequency module 1. In this embodiment, the high frequency input terminals 111 and 112 are connected to the RFIC 3 outside the high frequency module 1.
高周波出力端子１２１及び１２２の各々は、高周波モジュール１の外部に高周波受信信号を提供するための出力端子である。本実施の形態では、高周波出力端子１２１及び１２２は、高周波モジュール１の外部でＲＦＩＣ３に接続されている。
Each of the high frequency output terminals 121 and 122 is an output terminal for providing a high frequency reception signal to the outside of the high frequency module 1. In this embodiment, the high frequency output terminals 121 and 122 are connected to the RFIC 3 outside the high frequency module 1.
制御端子１３０は、制御信号を伝送するための端子である。つまり、制御端子１３０は、高周波モジュール１の外部から制御信号を受けるための端子、及び／又は、高周波モジュール１の外部に制御信号を供給するための端子である。制御信号とは、高周波モジュール１に含まれる電子部品の制御に関する信号である。具体的には、制御信号は、例えば、電力増幅回路１１を制御するためのデジタル信号である。
The control terminal 130 is a terminal for transmitting a control signal. That is, the control terminal 130 is a terminal for receiving a control signal from the outside of the high frequency module 1 and / or a terminal for supplying a control signal to the outside of the high frequency module 1. The control signal is a signal related to the control of electronic components included in the high frequency module 1. Specifically, the control signal is, for example, a digital signal for controlling the power amplifier circuit 11.
電力増幅回路１１は、バンドＡ及びＢの送信信号を増幅することができる。電力増幅回路１１の入力端は、スイッチ回路５２を介して高周波入力端子１１１及び１１２に接続される。電力増幅回路１１の出力端は、インピーダンス整合回路４１及びスイッチ回路５１を介して送信フィルタ回路６１Ｔ及び６２Ｔに接続される。
The power amplifier circuit 11 can amplify the transmission signals of the bands A and B. The input end of the power amplifier circuit 11 is connected to the high frequency input terminals 111 and 112 via the switch circuit 52. The output end of the power amplifier circuit 11 is connected to the transmission filter circuits 61T and 62T via the impedance matching circuit 41 and the switch circuit 51.
なお、電力増幅回路１１の構成は、特に限定されない。例えば、電力増幅回路１１は、多段増幅回路であってもよく、差動増幅型の増幅回路であってもよい。
The configuration of the power amplifier circuit 11 is not particularly limited. For example, the power amplification circuit 11 may be a multi-stage amplifier circuit or a differential amplifier type amplifier circuit.
低雑音増幅回路２１は、バンドＡ及びＢの受信信号を増幅することができる。低雑音増幅回路２１の入力端は、インピーダンス整合回路４２及びスイッチ回路５４を介して受信フィルタ回路６１Ｒ及び６２Ｒに接続される。低雑音増幅回路２１の出力端は、スイッチ回路５５を介して高周波出力端子１２１及び１２２に接続される。
The low noise amplifier circuit 21 can amplify the received signals of bands A and B. The input end of the low noise amplifier circuit 21 is connected to the reception filter circuits 61R and 62R via the impedance matching circuit 42 and the switch circuit 54. The output end of the low noise amplifier circuit 21 is connected to the high frequency output terminals 121 and 122 via the switch circuit 55.
インピーダンス整合回路４１は、電力増幅回路１１の出力端に接続され、かつ、スイッチ回路５１を介して送信フィルタ回路６１Ｔ及び６２Ｔの入力端に接続される。インピーダンス整合回路４１は、電力増幅回路１１の出力インピーダンスとスイッチ回路５１の入力インピーダンスとの間でインピーダンス整合をとることができる。
The impedance matching circuit 41 is connected to the output end of the power amplifier circuit 11 and is connected to the input ends of the transmission filter circuits 61T and 62T via the switch circuit 51. The impedance matching circuit 41 can perform impedance matching between the output impedance of the power amplifier circuit 11 and the input impedance of the switch circuit 51.
インピーダンス整合回路４２は、低雑音増幅回路２１の入力端に接続され、かつ、スイッチ回路５４を介して受信フィルタ回路６１Ｒ及び６２Ｒの出力端に接続される。インピーダンス整合回路４２は、スイッチ回路５４の出力インピーダンスと低雑音増幅回路２１の入力インピーダンスとの間でインピーダンス整合をとることができる。
The impedance matching circuit 42 is connected to the input end of the low noise amplifier circuit 21 and is connected to the output ends of the reception filter circuits 61R and 62R via the switch circuit 54. The impedance matching circuit 42 can perform impedance matching between the output impedance of the switch circuit 54 and the input impedance of the low noise amplifier circuit 21.
インピーダンス整合回路４３は、送信フィルタ回路６１Ｔの出力端及び受信フィルタ回路６１Ｒの入力端に接続され、かつ、スイッチ回路５３を介してアンテナ接続端子１００に接続される。インピーダンス整合回路４３は、スイッチ回路５３とデュプレクサ回路６１との間でインピーダンス整合をとることができる。
The impedance matching circuit 43 is connected to the output end of the transmission filter circuit 61T and the input end of the reception filter circuit 61R, and is connected to the antenna connection terminal 100 via the switch circuit 53. The impedance matching circuit 43 can achieve impedance matching between the switch circuit 53 and the duplexer circuit 61.
インピーダンス整合回路４４は、送信フィルタ回路６２Ｔの出力端及び受信フィルタ回路６２Ｒの入力端に接続され、かつ、スイッチ回路５３を介してアンテナ接続端子１００に接続される。インピーダンス整合回路４４は、スイッチ回路５３とデュプレクサ回路６２との間でインピーダンス整合をとることができる。
The impedance matching circuit 44 is connected to the output end of the transmission filter circuit 62T and the input end of the reception filter circuit 62R, and is connected to the antenna connection terminal 100 via the switch circuit 53. Impedance matching circuit 44 can achieve impedance matching between the switch circuit 53 and the duplexer circuit 62.
スイッチ回路５１は、第１スイッチ回路の一例であり、電力増幅回路１１の出力端と送信フィルタ回路６１Ｔ及び６２Ｔの入力端との間に接続されている。スイッチ回路５１は、端子５１１～５１３を有する。端子５１１は、インピーダンス整合回路４１を介して電力増幅回路１１の出力端に接続されている。端子５１２は、送信フィルタ回路６１Ｔの入力端に接続されている。端子５１３は、送信フィルタ回路６２Ｔの入力端に接続されている。
The switch circuit 51 is an example of the first switch circuit, and is connected between the output end of the power amplifier circuit 11 and the input ends of the transmission filter circuits 61T and 62T. The switch circuit 51 has terminals 511 to 513. The terminal 511 is connected to the output end of the power amplifier circuit 11 via the impedance matching circuit 41. The terminal 512 is connected to the input end of the transmission filter circuit 61T. The terminal 513 is connected to the input end of the transmission filter circuit 62T.
この接続構成において、スイッチ回路５１は、例えばＲＦＩＣ３からの制御信号に基づいて、端子５１１を端子５１２及び５１３のいずれかに接続することができる。つまり、スイッチ回路５１は、電力増幅回路１１の出力端の接続を送信フィルタ回路６１Ｔ及び６２Ｔの間で切り替えることができる。スイッチ回路５１は、例えばＳＰＤＴ（Single-Pole Double-Throw）型のスイッチを用いて構成され、バンドセレクトスイッチと呼ばれる場合もある。
In this connection configuration, the switch circuit 51 can connect the terminal 511 to any of the terminals 512 and 513, for example, based on the control signal from the RFIC3. That is, the switch circuit 51 can switch the connection of the output end of the power amplifier circuit 11 between the transmission filter circuits 61T and 62T. The switch circuit 51 is configured by using, for example, a SPDT (Single-Pole Double-Throw) type switch, and may be called a band select switch.
スイッチ回路５２は、第２スイッチ回路の一例であり、高周波入力端子１１１及び１１２と電力増幅回路１１の入力端との間に接続されている。スイッチ回路５２は、端子５２１～５２３を有する。端子５２１は、電力増幅回路１１の入力端に接続されている。端子５２２及び５２３は、高周波入力端子１１１及び１１２にそれぞれ接続されている。
The switch circuit 52 is an example of a second switch circuit, and is connected between the high frequency input terminals 111 and 112 and the input end of the power amplifier circuit 11. The switch circuit 52 has terminals 521 to 523. The terminal 521 is connected to the input end of the power amplifier circuit 11. The terminals 522 and 523 are connected to the high frequency input terminals 111 and 112, respectively.
この接続構成において、スイッチ回路５２は、例えばＲＦＩＣ３からの制御信号に基づいて、端子５２１を端子５２２及び５２３のいずれかに接続することができる。つまり、スイッチ回路５２は、電力増幅回路１１の入力端の接続を高周波入力端子１１１及び１１２の間で切り替えることができる。スイッチ回路５２は、例えばＳＰＤＴ型のスイッチを用いて構成され、インスイッチと呼ばれる場合もある。
In this connection configuration, the switch circuit 52 can connect the terminal 521 to any of the terminals 522 and 523, for example, based on the control signal from the RFIC3. That is, the switch circuit 52 can switch the connection of the input end of the power amplifier circuit 11 between the high frequency input terminals 111 and 112. The switch circuit 52 is configured by using, for example, a SPDT type switch, and is sometimes called an in-switch.
スイッチ回路５３は、第３スイッチ回路の一例であり、アンテナ接続端子１００とデュプレクサ回路６１及び６２との間に接続されている。スイッチ回路５３は、端子５３１～５３３を有する。端子５３１は、アンテナ接続端子１００に接続されている。端子５３２は、インピーダンス整合回路４３を介して送信フィルタ回路６１Ｔの出力端及び受信フィルタ回路６１Ｒの入力端に接続されている。端子５３３は、インピーダンス整合回路４４を介して送信フィルタ回路６２Ｔの出力端及び受信フィルタ回路６２Ｒの入力端に接続されている。
The switch circuit 53 is an example of a third switch circuit, and is connected between the antenna connection terminal 100 and the duplexer circuits 61 and 62. The switch circuit 53 has terminals 531 to 533. The terminal 531 is connected to the antenna connection terminal 100. The terminal 532 is connected to the output end of the transmission filter circuit 61T and the input end of the reception filter circuit 61R via the impedance matching circuit 43. The terminal 533 is connected to the output end of the transmission filter circuit 62T and the input end of the reception filter circuit 62R via the impedance matching circuit 44.
この接続構成において、スイッチ回路５３は、例えばＲＦＩＣ３からの制御信号に基づいて、端子５３１を端子５３２及び５３３の一方又は両方に接続することができる。つまり、スイッチ回路５３は、アンテナ接続端子１００及びデュプレクサ回路６１の接続及び非接続を切り替え、アンテナ接続端子１００及びデュプレクサ回路６２の接続及び非接続を切り替えることができる。スイッチ回路５３は、例えばマルチ接続型のスイッチを用いて構成され、アンテナスイッチと呼ばれる場合もある。
In this connection configuration, the switch circuit 53 can connect the terminal 531 to one or both of the terminals 532 and 533, for example, based on the control signal from the RFIC3. That is, the switch circuit 53 can switch the connection and non-connection of the antenna connection terminal 100 and the duplexer circuit 61, and can switch the connection and non-connection of the antenna connection terminal 100 and the duplexer circuit 62. The switch circuit 53 is configured by using, for example, a multi-connection type switch, and is sometimes called an antenna switch.
スイッチ回路５４は、低雑音増幅回路２１の入力端と受信フィルタ回路６１Ｒ及び６２Ｒの出力端との間に接続されている。スイッチ回路５４は、端子５４１～５４３を有する。端子５４１は、インピーダンス整合回路４２を介して低雑音増幅回路２１の入力端に接続されている。端子５４２は、受信フィルタ回路６１Ｒの出力端に接続されている。端子５４３は、受信フィルタ回路６２Ｒの出力端に接続されている。
The switch circuit 54 is connected between the input end of the low noise amplifier circuit 21 and the output ends of the reception filter circuits 61R and 62R. The switch circuit 54 has terminals 541 to 543. The terminal 541 is connected to the input end of the low noise amplifier circuit 21 via an impedance matching circuit 42. The terminal 542 is connected to the output end of the reception filter circuit 61R. The terminal 543 is connected to the output end of the reception filter circuit 62R.
この接続構成において、スイッチ回路５４は、例えばＲＦＩＣ３からの制御信号に基づいて、端子５４１を端子５４２及び５４３のいずれかに接続することができる。つまり、スイッチ回路５４は、低雑音増幅回路２１の入力端の接続を受信フィルタ回路６１Ｒ及び６２Ｒの間で切り替えることができる。スイッチ回路５４は、例えばＳＰＤＴ型のスイッチを用いて構成される。
In this connection configuration, the switch circuit 54 can connect the terminal 541 to any of the terminals 542 and 543, for example, based on the control signal from the RFIC3. That is, the switch circuit 54 can switch the connection of the input end of the low noise amplifier circuit 21 between the reception filter circuits 61R and 62R. The switch circuit 54 is configured by using, for example, a SPDT type switch.
スイッチ回路５５は、高周波出力端子１２１及び１２２と低雑音増幅回路２１の出力端との間に接続されている。スイッチ回路５５は、端子５５１～５５３を有する。端子５５１は、低雑音増幅回路２１の出力端に接続されている。端子５５２及び５５３は、高周波出力端子１２１及び１２２にそれぞれ接続されている。
The switch circuit 55 is connected between the high frequency output terminals 121 and 122 and the output end of the low noise amplifier circuit 21. The switch circuit 55 has terminals 551 to 553. The terminal 551 is connected to the output end of the low noise amplifier circuit 21. The terminals 552 and 553 are connected to the high frequency output terminals 121 and 122, respectively.
この接続構成において、スイッチ回路５５は、例えばＲＦＩＣ３からの制御信号に基づいて、端子５５１を端子５５２及び５５３のいずれかに接続することができる。つまり、スイッチ回路５５は、低雑音増幅回路２１の出力端の接続を高周波出力端子１２１及び１２２の間で切り替えることができる。スイッチ回路５５は、例えばＳＰＤＴ型のスイッチを用いて構成され、アウトスイッチと呼ばれる場合もある。
In this connection configuration, the switch circuit 55 can connect the terminal 551 to any of the terminals 552 and 553, for example, based on the control signal from the RFIC3. That is, the switch circuit 55 can switch the connection of the output end of the low noise amplifier circuit 21 between the high frequency output terminals 121 and 122. The switch circuit 55 is configured by using, for example, a SPDT type switch, and is sometimes called an out switch.
デュプレクサ回路６１は、バンドＡの高周波信号を通過させることができる。デュプレクサ回路６１は、バンドＡの送信信号と受信信号とを、周波数分割複信（ＦＤＤ：Frequency Division Duplex）方式で伝送する。デュプレクサ回路６１は、送信フィルタ回路６１Ｔ及び受信フィルタ回路６１Ｒを含む。
The duplexer circuit 61 can pass a high frequency signal of band A. The duplexer circuit 61 transmits the transmission signal and the reception signal of the band A by the frequency division duplex (FDD) method. The duplexer circuit 61 includes a transmission filter circuit 61T and a reception filter circuit 61R.
送信フィルタ回路６１Ｔ（Ａ－Ｔｘ）は、バンドＡのアップリンク動作バンドを含む通過帯域を有する。これにより、送信フィルタ回路６１Ｔは、バンドＡの送信信号を通過させることができる。送信フィルタ回路６１Ｔは、電力増幅回路１１とアンテナ接続端子１００との間に接続される。具体的には、送信フィルタ回路６１Ｔの入力端は、スイッチ回路５１及びインピーダンス整合回路４１を介して電力増幅回路１１の出力端に接続される。一方、送信フィルタ回路６１Ｔの出力端は、インピーダンス整合回路４３及びスイッチ回路５３を介してアンテナ接続端子１００に接続される。
The transmission filter circuit 61T (A-Tx) has a pass band including the uplink operation band of band A. As a result, the transmission filter circuit 61T can pass the transmission signal of the band A. The transmission filter circuit 61T is connected between the power amplifier circuit 11 and the antenna connection terminal 100. Specifically, the input end of the transmission filter circuit 61T is connected to the output end of the power amplifier circuit 11 via the switch circuit 51 and the impedance matching circuit 41. On the other hand, the output end of the transmission filter circuit 61T is connected to the antenna connection terminal 100 via the impedance matching circuit 43 and the switch circuit 53.
受信フィルタ回路６１Ｒ（Ａ－Ｒｘ）は、バンドＡのダウンリンク動作バンドを含む通過帯域を有する。これにより、受信フィルタ回路６１Ｒは、バンドＡの受信信号を通過させることができる。受信フィルタ回路６１Ｒは、アンテナ接続端子１００と低雑音増幅回路２１との間に接続される。具体的には、受信フィルタ回路６１Ｒの入力端は、インピーダンス整合回路４３及びスイッチ回路５３を介してアンテナ接続端子１００に接続される。一方、受信フィルタ回路６１Ｒの出力端は、スイッチ回路５４及びインピーダンス整合回路４２を介して低雑音増幅回路２１に接続される。
The reception filter circuit 61R (A-Rx) has a pass band including the downlink operation band of band A. As a result, the reception filter circuit 61R can pass the reception signal of the band A. The reception filter circuit 61R is connected between the antenna connection terminal 100 and the low noise amplifier circuit 21. Specifically, the input end of the reception filter circuit 61R is connected to the antenna connection terminal 100 via the impedance matching circuit 43 and the switch circuit 53. On the other hand, the output end of the reception filter circuit 61R is connected to the low noise amplifier circuit 21 via the switch circuit 54 and the impedance matching circuit 42.
デュプレクサ回路６２は、バンドＢの高周波信号を通過させることができる。デュプレクサ回路６２は、バンドＢの送信信号と受信信号とを、ＦＤＤ方式で伝送する。デュプレクサ回路６２は、送信フィルタ回路６２Ｔ及び受信フィルタ回路６２Ｒを含む。
The duplexer circuit 62 can pass a high frequency signal of band B. The duplexer circuit 62 transmits the transmission signal and the reception signal of the band B by the FDD method. The duplexer circuit 62 includes a transmit filter circuit 62T and a receive filter circuit 62R.
送信フィルタ回路６２Ｔ（Ｂ－Ｔｘ）は、バンドＢのアップリンク動作バンドを含む通過帯域を有する。これにより、送信フィルタ回路６２Ｔは、バンドＢの送信信号を通過させることができる。送信フィルタ回路６２Ｔは、電力増幅回路１１とアンテナ接続端子１００との間に接続される。具体的には、送信フィルタ回路６２Ｔの入力端は、スイッチ回路５１及びインピーダンス整合回路４１を介して電力増幅回路１１の出力端に接続される。一方、送信フィルタ回路６２Ｔの出力端は、インピーダンス整合回路４４及びスイッチ回路５３を介してアンテナ接続端子１００に接続される。
The transmission filter circuit 62T (B-Tx) has a pass band including the uplink operation band of band B. As a result, the transmission filter circuit 62T can pass the transmission signal of band B. The transmission filter circuit 62T is connected between the power amplifier circuit 11 and the antenna connection terminal 100. Specifically, the input end of the transmission filter circuit 62T is connected to the output end of the power amplifier circuit 11 via the switch circuit 51 and the impedance matching circuit 41. On the other hand, the output end of the transmission filter circuit 62T is connected to the antenna connection terminal 100 via the impedance matching circuit 44 and the switch circuit 53.
受信フィルタ回路６２Ｒ（Ｂ－Ｒｘ）は、バンドＢのダウンリンク動作バンドを含む通過帯域を有する。これにより、受信フィルタ回路６２Ｒは、バンドＢの受信信号を通過させることができる。受信フィルタ回路６２Ｒは、アンテナ接続端子１００と低雑音増幅回路２１との間に接続される。具体的には、受信フィルタ回路６２Ｒの入力端は、インピーダンス整合回路４４及びスイッチ回路５３を介してアンテナ接続端子１００に接続される。一方、受信フィルタ回路６２Ｒの出力端は、スイッチ回路５４及びインピーダンス整合回路４２を介して低雑音増幅回路２１に接続される。
The reception filter circuit 62R (B-Rx) has a pass band including the downlink operation band of band B. As a result, the reception filter circuit 62R can pass the reception signal of the band B. The reception filter circuit 62R is connected between the antenna connection terminal 100 and the low noise amplifier circuit 21. Specifically, the input end of the reception filter circuit 62R is connected to the antenna connection terminal 100 via the impedance matching circuit 44 and the switch circuit 53. On the other hand, the output end of the reception filter circuit 62R is connected to the low noise amplifier circuit 21 via the switch circuit 54 and the impedance matching circuit 42.
制御回路８０は、電力増幅回路１１を制御するパワーアンプコントローラである。制御回路８０は、ＲＦＩＣ３から制御端子１３０を介して制御信号を受けて、電力増幅回路１１に制御信号を出力する。
The control circuit 80 is a power amplifier controller that controls the power amplifier circuit 11. The control circuit 80 receives a control signal from the RFIC 3 via the control terminal 130, and outputs the control signal to the power amplifier circuit 11.
なお、図１に表された回路のうちの１以上の回路は、高周波モジュール１に含まれなくてもよい。例えば、高周波モジュール１は、少なくとも、電力増幅回路１１と電気回路（例えば制御回路８０など）とを備えればよく、他の回路を備えなくてもよい。
Note that one or more of the circuits shown in FIG. 1 need not be included in the high frequency module 1. For example, the high frequency module 1 may include at least a power amplifier circuit 11 and an electric circuit (for example, a control circuit 80), and may not include other circuits.
［１．２ 高周波モジュール１の部品配置］
次に、以上のように構成された高周波モジュール１の部品配置の一例について、図２及び図３を参照しながら具体的に説明する。 [1.2 Component placement of high frequency module 1]
Next, an example of the component arrangement of the high-frequency module 1 configured as described above will be specifically described with reference to FIGS. 2 and 3.
次に、以上のように構成された高周波モジュール１の部品配置の一例について、図２及び図３を参照しながら具体的に説明する。 [1.2 Component placement of high frequency module 1]
Next, an example of the component arrangement of the high-
図２は、実施の形態に係る高周波モジュール１の平面図である。図３は、実施の形態に係る高周波モジュール１の断面図である。図３における高周波モジュール１の断面は、図２のｉｉｉ－ｉｉｉ線における断面である。
FIG. 2 is a plan view of the high frequency module 1 according to the embodiment. FIG. 3 is a cross-sectional view of the high frequency module 1 according to the embodiment. The cross section of the high frequency module 1 in FIG. 3 is the cross section of the iii-iii line of FIG.
高周波モジュール１は、図１に示された回路が構成された部品に加えて、さらに、モジュール基板９０と、樹脂部材９１と、シールド電極層９２と、複数の外部接続端子１５０と、を備える。なお、図２では、樹脂部材９１及びシールド電極層９２の図示が省略されている。さらに、図２及び図３では、モジュール基板９０に配置された複数の部品をそれぞれ接続する配線の図示が省略されている。
The high frequency module 1 further includes a module substrate 90, a resin member 91, a shield electrode layer 92, and a plurality of external connection terminals 150, in addition to the components configured in the circuit shown in FIG. In FIG. 2, the resin member 91 and the shield electrode layer 92 are not shown. Further, in FIGS. 2 and 3, the wiring for connecting the plurality of components arranged on the module board 90 is omitted.
モジュール基板９０は、互いに対向する主面９０ａ及び９０ｂを有する。本実施の形態では、モジュール基板９０は、平面視において矩形状を有するが、モジュール基板９０の形状はこれに限定されない。モジュール基板９０としては、例えば、複数の誘電体層の積層構造を有する低温同時焼成セラミックス（ＬＴＣＣ：Low Temperature Co-fired Ceramics）基板、高温同時焼成セラミックス（ＨＴＣＣ：High Temperature Co-fired Ceramics）基板、部品内蔵基板、再配線層（ＲＤＬ：Redistribution Layer）を有する基板、又は、プリント基板等を用いることができるが、これらに限定されない。
The module board 90 has main surfaces 90a and 90b facing each other. In the present embodiment, the module substrate 90 has a rectangular shape in a plan view, but the shape of the module substrate 90 is not limited to this. Examples of the module substrate 90 include a low-temperature co-fired ceramics (LTCC: Low Temperature Co-fired Ceramics) substrate having a laminated structure of a plurality of dielectric layers, a high-temperature co-fired ceramics (HTCC: High Temperature Co-fired Ceramics) substrate, and the like. A board having a built-in component, a board having a redistribution layer (RDL: Redistribution Layer), a printed circuit board, or the like can be used, but is not limited thereto.
主面９０ａには、集積回路２０及び７０と、インピーダンス整合回路４１～４４と、スイッチ回路５３と、デュプレクサ回路６１及び６２と、が配置されている。主面９０ａ及び主面９０ａ上の部品は、樹脂部材９１で覆われている。
Integrated circuits 20 and 70, impedance matching circuits 41 to 44, switch circuits 53, and duplexer circuits 61 and 62 are arranged on the main surface 90a. The main surface 90a and the parts on the main surface 90a are covered with the resin member 91.
集積回路２０は、低雑音増幅回路２１とスイッチ回路５４及び５５を含む。集積回路２０は、例えばＣＭＯＳ（Complementary Metal Oxide Semiconductor）を用いて構成され、具体的にはＳＯＩ（Silicon on Insulator）プロセスにより製造されてもよい。これにより、集積回路２０を安価に製造することが可能となる。なお、集積回路２０は、ガリウムヒ素、シリコンゲルマニウム（ＳｉＧｅ）及び窒化ガリウム（ＧａＮ）のうちの少なくとも１つで構成されてもよい。これにより、高品質な低雑音増幅回路２１とスイッチ回路５４及び５５とを実現することができる。
The integrated circuit 20 includes a low noise amplifier circuit 21 and switch circuits 54 and 55. The integrated circuit 20 is configured by using, for example, CMOS (Complementary Metal Oxide Semiconductor), and may be specifically manufactured by an SOI (Silicon on Insulator) process. This makes it possible to manufacture the integrated circuit 20 at low cost. The integrated circuit 20 may be composed of at least one of gallium arsenide, silicon germanium (SiGe), and gallium nitride (GaN). This makes it possible to realize a high-quality low-noise amplifier circuit 21 and switch circuits 54 and 55.
集積回路７０は、第１基材７１及び第２基材７２を含む。第２基材７２及び第１基材７１は、モジュール基板９０の主面９０ａ上にこの順で積層されている。集積回路７０の詳細については、図４～図６を用いて後述する。
The integrated circuit 70 includes a first base material 71 and a second base material 72. The second base material 72 and the first base material 71 are laminated in this order on the main surface 90a of the module substrate 90. Details of the integrated circuit 70 will be described later with reference to FIGS. 4 to 6.
インピーダンス整合回路４１～４４の各々は、整合素子を含む。整合素子としては、インダクタ及び／又はキャパシタを用いることができる。インピーダンス整合回路４１～４４に含まれる整合素子の各々は、表面実装部品（ＳＭＤ：Surface Mount Device）を用いて構成されている。なお、インピーダンス整合回路４１～４４に含まれる整合素子のいくつか又はすべては、集積型受動デバイス（ＩＰＤ：Integrated Passive Device）を用いて構成されてもよい。
Each of the impedance matching circuits 41 to 44 includes a matching element. As the matching element, an inductor and / or a capacitor can be used. Each of the matching elements included in the impedance matching circuits 41 to 44 is configured by using a surface mount component (SMD: Surface Mount Device). Note that some or all of the matching elements included in the impedance matching circuits 41 to 44 may be configured by using an integrated passive device (IPD).
スイッチ回路５３は、例えば直列接続された複数のＭＯＳＦＥＴ（Metal-Oxide-Semiconductor Field-Effect Transistor）などによって構成されている。ＭＯＳＦＥＴの直列接続の段数は、必要な耐電圧に応じて決定されればよく、特に限定されない。
The switch circuit 53 is composed of, for example, a plurality of MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistor) connected in series. The number of stages of MOSFETs connected in series may be determined according to the required withstand voltage, and is not particularly limited.
デュプレクサ回路６１及び６２の各々は、例えば、弾性表面波（ＳＡＷ：Surface Acoustic Wave）フィルタ、バルク弾性波（ＢＡＷ：Bulk Acoustic Wave）フィルタ、ＬＣ共振フィルタ、及び誘電体フィルタのいずれを用いて構成されてもよく、さらには、これらには限定されない。
Each of the duplexer circuits 61 and 62 is configured using, for example, any of a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, an LC resonance filter, and a dielectric filter. It may, and is not limited to, these.
樹脂部材９１は、主面９０ａ及び主面９０ａ上の部品を覆っている。樹脂部材９１は、主面９０ａ上の部品の機械強度及び耐湿性等の信頼性を確保する機能を有する。なお、樹脂部材９１はなくてもよい。
The resin member 91 covers the main surface 90a and the parts on the main surface 90a. The resin member 91 has a function of ensuring reliability such as mechanical strength and moisture resistance of the parts on the main surface 90a. The resin member 91 may be omitted.
シールド電極層９２は、例えばスパッタ法により形成された金属薄膜であり、樹脂部材９１の上面及び側面と、モジュール基板９０の側面と、を覆うように形成されている。シールド電極層９２は、グランド電位に設定され、外来ノイズが高周波モジュール１を構成する部品に侵入することを抑制する。
The shield electrode layer 92 is, for example, a metal thin film formed by a sputtering method, and is formed so as to cover the upper surface and side surfaces of the resin member 91 and the side surfaces of the module substrate 90. The shield electrode layer 92 is set to the ground potential and suppresses external noise from invading the components constituting the high frequency module 1.
主面９０ｂには、複数の外部接続端子１５０が配置されている。複数の外部接続端子１５０は、図１に示したアンテナ接続端子１００、高周波入力端子１１１及び１１２、高周波出力端子１２１及び１２２、並びに、制御端子１３０に加えて、グランド端子を含む。複数の外部接続端子１５０の各々は、高周波モジュール１のｚ軸負方向に配置されたマザー基板上の入出力端子及び／又はグランド端子等に接合される。複数の外部接続端子１５０としては、例えばバンプ電極を用いることができるが、これに限定されない。
A plurality of external connection terminals 150 are arranged on the main surface 90b. The plurality of external connection terminals 150 include an antenna connection terminal 100 shown in FIG. 1, high frequency input terminals 111 and 112, high frequency output terminals 121 and 122, and a ground terminal in addition to the control terminal 130. Each of the plurality of external connection terminals 150 is joined to an input / output terminal and / or a ground terminal or the like on the mother board arranged in the negative direction of the z-axis of the high frequency module 1. As the plurality of external connection terminals 150, for example, a bump electrode can be used, but the present invention is not limited thereto.
なお、図２及び図３に示す部品配置は、一例であり、これに限定されない。例えば、複数の部品のうちの一部又は全部は、モジュール基板９０の主面９０ｂに配置されてもよい。この場合、主面９０ｂ及び主面９０ｂ上の部品は樹脂部材で覆われてもよい。
Note that the component arrangement shown in FIGS. 2 and 3 is an example and is not limited thereto. For example, some or all of the plurality of parts may be arranged on the main surface 90b of the module board 90. In this case, the main surface 90b and the parts on the main surface 90b may be covered with the resin member.
［１．３ 集積回路７０の構成］
次に、集積回路７０の構成について、図４～図６を参照しながら説明する。図４及び図５は、実施の形態に係る高周波モジュール１の部分断面図である。図６は、実施の形態に係る集積回路７０内の回路配置図である。具体的には、図４は、集積回路７０の拡大断面図であり、図５は、第２基材７２の拡大断面図であり、図６は、集積回路７０の透視平面図である。なお、図４～図６において、配線及び電極の図示は一部を除いて省略されている。また、図６において、破線は、第１基材７１、第２基材７２及び低熱伝導部材７３の外形を表す。 [1.3 Configuration of integrated circuit 70]
Next, the configuration of theintegrated circuit 70 will be described with reference to FIGS. 4 to 6. 4 and 5 are partial cross-sectional views of the high frequency module 1 according to the embodiment. FIG. 6 is a circuit layout diagram in the integrated circuit 70 according to the embodiment. Specifically, FIG. 4 is an enlarged cross-sectional view of the integrated circuit 70, FIG. 5 is an enlarged cross-sectional view of the second base material 72, and FIG. 6 is a perspective plan view of the integrated circuit 70. In addition, in FIGS. 4 to 6, the wiring and the illustration of the electrode are omitted except for a part. Further, in FIG. 6, the broken line indicates the outer shape of the first base material 71, the second base material 72, and the low heat conductive member 73.
次に、集積回路７０の構成について、図４～図６を参照しながら説明する。図４及び図５は、実施の形態に係る高周波モジュール１の部分断面図である。図６は、実施の形態に係る集積回路７０内の回路配置図である。具体的には、図４は、集積回路７０の拡大断面図であり、図５は、第２基材７２の拡大断面図であり、図６は、集積回路７０の透視平面図である。なお、図４～図６において、配線及び電極の図示は一部を除いて省略されている。また、図６において、破線は、第１基材７１、第２基材７２及び低熱伝導部材７３の外形を表す。 [1.3 Configuration of integrated circuit 70]
Next, the configuration of the
図４に示すように、集積回路７０は、第１基材７１、第２基材７２及び低熱伝導部材７３を含む。
As shown in FIG. 4, the integrated circuit 70 includes a first base material 71, a second base material 72, and a low heat conductive member 73.
［１．３．１ 第１基材７１の構成］
ここで、第１基材７１について説明する。第１基材７１の少なくとも一部は、第１半導体材料で構成されている。ここでは、第１半導体材料として、シリコン（Ｓｉ）が用いられている。なお、第１半導体材料は、シリコンに限定されない。例えば、第１半導体材料としては、ガリウムヒ素、ヒ化アルミニウム（ＡｌＡｓ）、ヒ化インジウム（ＩｎＡｓ）、リン化インジウム（ＩｎＰ）、リン化ガリウム（ＧａＰ）、アンチモン化インジウム（ＩｎＳｂ）、窒化ガリウム、窒化インジウム（ＩｎＮ）、窒化アルミニウム（ＡｌＮ）、シリコン、ゲルマニウム（Ｇｅ）、炭化シリコン（ＳｉＣ）、及び、酸化ガリウム（III）（Ｇａ２Ｏ３）のいずれかを主成分として含む材料又はこれら材料のうち複数の材料からなる多元系混晶材料を主成分として含む材料を用いることができ、これらに限定されない。 [13.1 Configuration of First Base Material 71]
Here, thefirst base material 71 will be described. At least a part of the first base material 71 is made of the first semiconductor material. Here, silicon (Si) is used as the first semiconductor material. The first semiconductor material is not limited to silicon. For example, as the first semiconductor material, gallium arsenide, aluminum arsenide (AlAs), indium arsenide (InAs), indium phosphide (InP), gallium phosphide (GaP), indium antimonide (InSb), gallium nitride, etc. A material containing any of indium phosphide (InN), aluminum nitride (AlN), silicon, germanium (Ge), silicon carbide (SiC), and gallium oxide (III) (Ga 2 O 3 ) as a main component, or these materials. Of these, a material containing a multidimensional mixed crystal material composed of a plurality of materials as a main component can be used, and the material is not limited thereto.
ここで、第１基材７１について説明する。第１基材７１の少なくとも一部は、第１半導体材料で構成されている。ここでは、第１半導体材料として、シリコン（Ｓｉ）が用いられている。なお、第１半導体材料は、シリコンに限定されない。例えば、第１半導体材料としては、ガリウムヒ素、ヒ化アルミニウム（ＡｌＡｓ）、ヒ化インジウム（ＩｎＡｓ）、リン化インジウム（ＩｎＰ）、リン化ガリウム（ＧａＰ）、アンチモン化インジウム（ＩｎＳｂ）、窒化ガリウム、窒化インジウム（ＩｎＮ）、窒化アルミニウム（ＡｌＮ）、シリコン、ゲルマニウム（Ｇｅ）、炭化シリコン（ＳｉＣ）、及び、酸化ガリウム（III）（Ｇａ２Ｏ３）のいずれかを主成分として含む材料又はこれら材料のうち複数の材料からなる多元系混晶材料を主成分として含む材料を用いることができ、これらに限定されない。 [13.1 Configuration of First Base Material 71]
Here, the
第１基材７１には、スイッチ回路５１及び５２と制御回路８０とが形成されている。なお、第１基材７１に形成される電気回路は、スイッチ回路５１及び５２と制御回路８０とに限定されない。例えば、スイッチ回路５１及び５２と制御回路８０とのうちのいずれか又はいくつかのみが第１基材７１に形成されてもよい。また、スイッチ回路５１及び／又は５２を制御する制御回路（図示せず）が第１基材７１に形成されてもよい。また、インピーダンス整合回路４１～４４のうちの少なくとも１つが第１基材７１に形成されてもよい。
A switch circuit 51 and 52 and a control circuit 80 are formed on the first base material 71. The electric circuit formed on the first base material 71 is not limited to the switch circuits 51 and 52 and the control circuit 80. For example, only one or a few of the switch circuits 51 and 52 and the control circuit 80 may be formed on the first substrate 71. Further, a control circuit (not shown) for controlling the switch circuit 51 and / or 52 may be formed on the first base material 71. Further, at least one of the impedance matching circuits 41 to 44 may be formed on the first base material 71.
図４に示すように、第１基材７１は、互いに対向する面７１ａ及び７１ｂを有する。面７１ａ及び７１ｂは、それぞれ、第１面及び第２面の一例である。面７１ｂには、電極７１７が配置されている。
As shown in FIG. 4, the first base material 71 has surfaces 71a and 71b facing each other. The surfaces 71a and 71b are examples of the first surface and the second surface, respectively. An electrode 717 is arranged on the surface 71b.
第１基材７１は、シリコン基板７１１と、二酸化シリコン（ＳｉＯ２）層７１２と、シリコン層７１３と、二酸化シリコン層７１４と、窒化シリコン（ＳｉＮ）層７１５と、を含む。二酸化シリコン層７１２、シリコン層７１３、二酸化シリコン層７１４及び窒化シリコン層７１５は、シリコン基板７１１上にこの順で積層されている。
The first substrate 71 includes a silicon substrate 711, a silicon dioxide (SiO 2 ) layer 712, a silicon layer 713, a silicon dioxide layer 714, and a silicon nitride (SiN) layer 715. The silicon dioxide layer 712, the silicon layer 713, the silicon dioxide layer 714, and the silicon nitride layer 715 are laminated on the silicon substrate 711 in this order.
シリコン基板７１１は、例えば、シリコン単結晶で構成され、支持基板として用いられている。
The silicon substrate 711 is made of, for example, a silicon single crystal and is used as a support substrate.
二酸化シリコン層７１２は、シリコン基板７１１上に配置され、絶縁層として用いられている。
The silicon dioxide layer 712 is arranged on the silicon substrate 711 and is used as an insulating layer.
シリコン層７１３は、二酸化シリコン層７１２上に配置され、デバイス層として用いられている。図４の断面では、シリコン層７１３に、制御回路８０を構成する複数の回路素子７１３０が形成されている。
The silicon layer 713 is arranged on the silicon dioxide layer 712 and is used as a device layer. In the cross section of FIG. 4, a plurality of circuit elements 7130 constituting the control circuit 80 are formed on the silicon layer 713.
二酸化シリコン層７１４は、シリコン層７１３上に配置され、配線形成層として用いられている。二酸化シリコン層７１４には、シリコン層７１３に形成された制御回路８０並びにスイッチ回路５１及び５２を、窒化シリコン層７１５の表面に形成された電極７１６に接続するための配線が形成されている。この配線は、複数の配線層（図示せず）と、複数の配線層間を接続する複数のビア電極７１４０と、を含む。複数の配線層及び複数のビア電極７１４０は、例えば、銅又はアルミニウムで構成されている。
The silicon dioxide layer 714 is arranged on the silicon layer 713 and is used as a wiring forming layer. The silicon dioxide layer 714 is formed with wiring for connecting the control circuit 80 and the switch circuits 51 and 52 formed on the silicon layer 713 to the electrodes 716 formed on the surface of the silicon nitride layer 715. This wiring includes a plurality of wiring layers (not shown) and a plurality of via electrodes 7140 connecting the plurality of wiring layers. The plurality of wiring layers and the plurality of via electrodes 7140 are made of, for example, copper or aluminum.
窒化シリコン層７１５は、二酸化シリコン層７１４上に配置され、パッシベーション層として用いられている。窒化シリコン層７１５の表面の一部には、再配線層として電極７１６が形成されている。さらに、窒化シリコン層７１５の表面の他の一部には、第２基材７２及び低熱伝導部材７３が接合されている。
The silicon nitride layer 715 is arranged on the silicon dioxide layer 714 and is used as a passivation layer. An electrode 716 is formed as a rewiring layer on a part of the surface of the silicon nitride layer 715. Further, the second base material 72 and the low heat conductive member 73 are bonded to the other part of the surface of the silicon nitride layer 715.
電極７１６は、電極７１７を介してモジュール基板９０に配置された電極（図示せず）に接合されている。電極７１６の表面は、樹脂層７１８で絶縁皮膜されている。
The electrode 716 is joined to an electrode (not shown) arranged on the module substrate 90 via the electrode 717. The surface of the electrode 716 is coated with a resin layer 718 as an insulating film.
複数の電極７１７は、第１電極の一例である。複数の電極７１７の各々は、第１基材７１からモジュール基板９０の主面９０ａに向かって突出する電極であり、その先端が主面９０ａに接合されている。複数の電極７１７の各々は、柱状導体７１７ａ及びバンプ電極７１７ｂを有する。バンプ電極７１７ｂは、モジュール基板９０の主面９０ａに配置された電極（図示せず）に接合されている。
The plurality of electrodes 717 is an example of the first electrode. Each of the plurality of electrodes 717 is an electrode protruding from the first base material 71 toward the main surface 90a of the module substrate 90, and the tip thereof is joined to the main surface 90a. Each of the plurality of electrodes 717 has a columnar conductor 717a and a bump electrode 717b. The bump electrode 717b is joined to an electrode (not shown) arranged on the main surface 90a of the module substrate 90.
なお、第１基材７１は、図４の構成に限定されない。例えば、第１基材７１は、シリコン基板７１１上の複数の層のうちの１つ又はいくつかを含まなくてもよい。
The first base material 71 is not limited to the configuration shown in FIG. For example, the first substrate 71 may not include one or some of the plurality of layers on the silicon substrate 711.
［１．３．２ 第２基材７２の構成］
次に、第２基材７２について説明する。第２基材７２の少なくとも一部は、第１半導体材料よりも熱伝導率が低い第２半導体材料で構成されている。第２半導体材料としては、ガリウムヒ素が用いられている。なお、第２半導体材料は、ガリウムヒ素に限定されない。例えば、第２半導体材料としては、ガリウムヒ素、ヒ化アルミニウム、ヒ化インジウム、リン化インジウム、リン化ガリウム、アンチモン化インジウム、窒化ガリウム、窒化インジウム、窒化アルミニウム、シリコンゲルマニウム、炭化シリコン、酸化ガリウム（III）、及び、ガリウムビスマス（ＧａＢｉ）のいずれかを主成分として含む材料又はこれら材料のうち複数の材料からなる多元系混晶材料を主成分として含む材料を用いることができ、これらに限定されない。 [1.3.2 Composition of the second base material 72]
Next, thesecond base material 72 will be described. At least a part of the second base material 72 is made of a second semiconductor material having a lower thermal conductivity than the first semiconductor material. Gallium arsenide is used as the second semiconductor material. The second semiconductor material is not limited to gallium arsenide. For example, as the second semiconductor material, gallium arsenide, aluminum arsenide, indium arsenide, indium phosphide, gallium phosphide, indium antimonized, gallium nitride, indium nitride, aluminum nitride, silicon germanium, silicon carbide, gallium oxide ( III), a material containing either gallium bismuth (GaBi) as a main component, or a material containing a multidimensional mixed crystal material consisting of a plurality of these materials as a main component can be used, and is not limited thereto. ..
次に、第２基材７２について説明する。第２基材７２の少なくとも一部は、第１半導体材料よりも熱伝導率が低い第２半導体材料で構成されている。第２半導体材料としては、ガリウムヒ素が用いられている。なお、第２半導体材料は、ガリウムヒ素に限定されない。例えば、第２半導体材料としては、ガリウムヒ素、ヒ化アルミニウム、ヒ化インジウム、リン化インジウム、リン化ガリウム、アンチモン化インジウム、窒化ガリウム、窒化インジウム、窒化アルミニウム、シリコンゲルマニウム、炭化シリコン、酸化ガリウム（III）、及び、ガリウムビスマス（ＧａＢｉ）のいずれかを主成分として含む材料又はこれら材料のうち複数の材料からなる多元系混晶材料を主成分として含む材料を用いることができ、これらに限定されない。 [1.3.2 Composition of the second base material 72]
Next, the
第２基材７２には、電力増幅回路１１が形成されている。具体的には、第２基材７２には、複数の回路素子７２１と、複数の回路素子７２１に電圧を印加するための電極（図示せず）、又は、電流を供給するための電極（図示せず）とが形成されている。複数の回路素子７２１は、例えば、複数の単位トランジスタが並列接続されたヘテロ接合バイポーラトランジスタ（ＨＢＴ）であり、電力増幅回路１１を構成する。
A power amplifier circuit 11 is formed on the second base material 72. Specifically, on the second base material 72, a plurality of circuit elements 721 and electrodes for applying a voltage to the plurality of circuit elements 721 (not shown) or electrodes for supplying a current (FIG.). (Not shown) and are formed. The plurality of circuit elements 721 are, for example, heterojunction bipolar transistors (HBTs) in which a plurality of unit transistors are connected in parallel, and constitute a power amplifier circuit 11.
図５に示すように、第２基材７２は、互いに対向する面７２ａ及び７２ｂを有する。面７２ａ及び７２ｂは、それぞれ、第３面及び第４面の一例である。面７２ｂには、電極７２４が配置されている。
As shown in FIG. 5, the second base material 72 has surfaces 72a and 72b facing each other. The surfaces 72a and 72b are examples of the third surface and the fourth surface, respectively. An electrode 724 is arranged on the surface 72b.
第２基材７２は、半導体層７２Ａと、半導体層７２Ａの表面に形成されたエピタキシャル層７２Ｂと、複数の回路素子７２１と、電極７２２及び７３３と、を備える。半導体層７２Ａは、第２半導体材料で構成されており、第１基材７１の窒化シリコン層７１５に接合されている。半導体層７２Ａは、例えばＧａＡｓ層である。回路素子７２１は、コレクタ層７２１Ｃ、ベース層７２１Ｂ及びエミッタ層７２１Ｅを有する。コレクタ層７２１Ｃ、ベース層７２１Ｂ及びエミッタ層７２１Ｅは、エピタキシャル層７２Ｂ上にこの順で積層されている。つまり、回路素子７２１において、コレクタ層７２１Ｃ、ベース層７２１Ｂ及びエミッタ層７２１Ｅが、第１基材７１側からこの順で積層されている。
The second base material 72 includes a semiconductor layer 72A, an epitaxial layer 72B formed on the surface of the semiconductor layer 72A, a plurality of circuit elements 721, and electrodes 722 and 733. The semiconductor layer 72A is made of a second semiconductor material and is bonded to the silicon nitride layer 715 of the first base material 71. The semiconductor layer 72A is, for example, a GaAs layer. The circuit element 721 has a collector layer 721C, a base layer 721B, and an emitter layer 721E. The collector layer 721C, the base layer 721B, and the emitter layer 721E are laminated on the epitaxial layer 72B in this order. That is, in the circuit element 721, the collector layer 721C, the base layer 721B, and the emitter layer 721E are laminated in this order from the first base material 71 side.
一例として、コレクタ層７２１Ｃはｎ型ガリウムヒ素で構成され、ベース層７２１Ｂはｐ型ガリウムヒ素で構成され、エミッタ層７２１Ｅはｎ型インジウムガリウムリン（ＩｎＧａＰ）で構成されている。エミッタ層７２１Ｅは、第２基材７２の表面に形成された電極７２２を介して電極７２３に接合されている。電極７２３は、電極７２４を介してモジュール基板９０の主面９０ａに接合されている。
As an example, the collector layer 721C is composed of n-type gallium arsenide, the base layer 721B is composed of p-type gallium arsenide, and the emitter layer 721E is composed of n-type indium gallium phosphide (InGaP). The emitter layer 721E is bonded to the electrode 723 via an electrode 722 formed on the surface of the second base material 72. The electrode 723 is joined to the main surface 90a of the module substrate 90 via the electrode 724.
電極７２４は、第２電極の一例であり、第２基材７２からモジュール基板９０の主面９０ａに向かって突出しており、その先端が主面９０ａに接合されている。電極７２４は、電力増幅回路１１で発生した熱の放熱経路として機能する。電極７２４は、柱状導体７２４ａ及びバンプ電極７２４ｂを有する。バンプ電極７２４ｂは、モジュール基板９０の主面９０ａに配置された電極（図示せず）に接合されている。
The electrode 724 is an example of the second electrode, and protrudes from the second base material 72 toward the main surface 90a of the module substrate 90, and the tip thereof is joined to the main surface 90a. The electrode 724 functions as a heat dissipation path for the heat generated by the power amplifier circuit 11. The electrode 724 has a columnar conductor 724a and a bump electrode 724b. The bump electrode 724b is bonded to an electrode (not shown) arranged on the main surface 90a of the module substrate 90.
なお、第２基材７２は、図４及び図５の構成に限定されない。
The second base material 72 is not limited to the configurations shown in FIGS. 4 and 5.
［１．３．３ 低熱伝導部材７３の構成］
次に、低熱伝導部材７３について説明する。低熱伝導部材７３の少なくとも一部は、第２半導体材料よりも熱伝導率が低い低熱伝導材料で構成されている。低熱伝導材料としては、ガラス及び合成高分子化合物などを用いることができる。合成高分子化合物としては、エポキシ樹脂を用いることができ、他の合成樹脂又は合成ゴムが用いられてもよい。 [1.3.3 Configuration of low heat conductive member 73]
Next, the low heatconductive member 73 will be described. At least a part of the low thermal conductive member 73 is made of a low thermal conductive material having a lower thermal conductivity than the second semiconductor material. As the low thermal conductivity material, glass, synthetic polymer compounds and the like can be used. As the synthetic polymer compound, an epoxy resin can be used, and other synthetic resins or synthetic rubbers may be used.
次に、低熱伝導部材７３について説明する。低熱伝導部材７３の少なくとも一部は、第２半導体材料よりも熱伝導率が低い低熱伝導材料で構成されている。低熱伝導材料としては、ガラス及び合成高分子化合物などを用いることができる。合成高分子化合物としては、エポキシ樹脂を用いることができ、他の合成樹脂又は合成ゴムが用いられてもよい。 [1.3.3 Configuration of low heat conductive member 73]
Next, the low heat
低熱伝導部材７３は、第１基材７１に形成された電気回路（例えば、制御回路８０、スイッチ回路５１又は５２など）と、第２基材７２に形成された電力増幅回路１１との間に配置されている。本実施の形態では、低熱伝導部材７３は、第１基材７１の面７１ｂ上に配置され、断面視において制御回路８０と電力増幅回路１１との間に配置されている。なお、低熱伝導部材７３の配置は、図４の配置に限定されない。例えば、低熱伝導部材７３は、第１基材７１内に配置されてもよい。
The low heat conductive member 73 is formed between an electric circuit formed on the first base material 71 (for example, a control circuit 80, a switch circuit 51 or 52, etc.) and a power amplification circuit 11 formed on the second base material 72. Have been placed. In the present embodiment, the low heat conductive member 73 is arranged on the surface 71b of the first base material 71, and is arranged between the control circuit 80 and the power amplification circuit 11 in a cross-sectional view. The arrangement of the low heat conductive member 73 is not limited to the arrangement shown in FIG. For example, the low heat conductive member 73 may be arranged in the first base material 71.
低熱伝導部材７３は、面７３ａ及び７３ｂを有する。面７３ａは、第１基材７１の面７１ｂに接触している。面７３ｂの一部は、第２基材７２の面７２ａに接触している。
The low heat conductive member 73 has surfaces 73a and 73b. The surface 73a is in contact with the surface 71b of the first base material 71. A part of the surface 73b is in contact with the surface 72a of the second base material 72.
なお、低熱伝導部材７３の形状は、シート状に限定されない。例えば、低熱伝導部材７３は、ブロック状であってもよい。また、低熱伝導部材７３は、複数の層を含んでもよい。この場合、複数の層のうちの少なくとも１つが、低熱伝導材料で構成されればよい。
The shape of the low heat conductive member 73 is not limited to the sheet shape. For example, the low heat conductive member 73 may have a block shape. Further, the low heat conductive member 73 may include a plurality of layers. In this case, at least one of the plurality of layers may be composed of a low thermal conductive material.
［１．３．４ 集積回路７０内の回路配置］
次に、平面視における集積回路７０内の回路配置について図６を参照しながら説明する。 [1.3.4 Circuit layout in integrated circuit 70]
Next, the circuit arrangement in theintegrated circuit 70 in a plan view will be described with reference to FIG.
次に、平面視における集積回路７０内の回路配置について図６を参照しながら説明する。 [1.3.4 Circuit layout in integrated circuit 70]
Next, the circuit arrangement in the
図６に示すように、低熱伝導部材７３の一部は、平面視において第１基材７１に形成された電気回路（制御回路８０、スイッチ回路５１及び５２）の一部と重なっている。さらには、低熱伝導部材７３の他の一部は、平面視において電力増幅回路１１の一部と重なっている。
As shown in FIG. 6, a part of the low heat conductive member 73 overlaps with a part of the electric circuit (control circuit 80, switch circuit 51 and 52) formed on the first base material 71 in a plan view. Further, another part of the low heat conductive member 73 overlaps with a part of the power amplifier circuit 11 in a plan view.
なお、図６における集積回路７０内の回路配置は、あくまでも例示であり、この配置に限定されない。例えば、低熱伝導部材７３は、平面視において電力増幅回路１１及び／又は制御回路８０等と重ならなくてもよい。
The circuit arrangement in the integrated circuit 70 in FIG. 6 is merely an example, and is not limited to this arrangement. For example, the low heat conductive member 73 does not have to overlap with the power amplifier circuit 11 and / or the control circuit 80 or the like in a plan view.
［１．４ 効果など］
以上のように、本実施の形態に係る集積回路７０は、少なくとも一部が第１半導体材料で構成され、電気回路（例えば、制御回路８０又はスイッチ回路５１若しくは５２）が形成された第１基材７１と、少なくとも一部が第１半導体材料よりも低い熱伝導率を有する第２半導体材料で構成され、電力増幅回路１１が形成された第２基材７２と、少なくとも一部が第２半導体材料よりも低い熱伝導率を有する低熱伝導材料で構成され、電気回路及び電力増幅回路１１の間に配置された低熱伝導部材７３と、を備え、第１基材７１の少なくとも一部は、平面視において第２基材７２の少なくとも一部と重なっている。 [1.4 Effect, etc.]
As described above, theintegrated circuit 70 according to the present embodiment is the first unit in which at least a part thereof is composed of the first semiconductor material and the electric circuit (for example, the control circuit 80 or the switch circuit 51 or 52) is formed. A second base material 72 in which the material 71 is composed of at least a second semiconductor material having a lower thermal conductivity than the first semiconductor material and a power amplification circuit 11 is formed, and at least a part of the second semiconductor. It comprises a low heat conductive member 73, which is made of a low heat conductive material having a lower heat conductivity than the material and is arranged between an electric circuit and a power amplification circuit 11, and at least a part of the first base material 71 is a flat surface. Visually, it overlaps with at least a part of the second base material 72.
以上のように、本実施の形態に係る集積回路７０は、少なくとも一部が第１半導体材料で構成され、電気回路（例えば、制御回路８０又はスイッチ回路５１若しくは５２）が形成された第１基材７１と、少なくとも一部が第１半導体材料よりも低い熱伝導率を有する第２半導体材料で構成され、電力増幅回路１１が形成された第２基材７２と、少なくとも一部が第２半導体材料よりも低い熱伝導率を有する低熱伝導材料で構成され、電気回路及び電力増幅回路１１の間に配置された低熱伝導部材７３と、を備え、第１基材７１の少なくとも一部は、平面視において第２基材７２の少なくとも一部と重なっている。 [1.4 Effect, etc.]
As described above, the
これによれば、電気回路が形成された第１基材７１に、電力増幅回路１１が形成された第２基材７２が平面視で重ねられるので、集積回路７０は、高周波モジュール１の小型化に貢献することができる。さらに、さらに、第２基材７２に形成された電力増幅回路１１で発生した熱を、第２基材７２を構成する第２半導体材料よりも高い熱伝導率を有する第１半導体材料で構成された第１基材７１に排出することができる。このとき、第２半導体材料よりも低い熱伝導率を有する低熱伝導部材７３が電力増幅回路１１と電気回路との間に配置されるので、電力増幅回路１１から電気回路への伝熱を抑制することができ、熱による電気回路の特性の劣化を抑制することができる。
According to this, since the second base material 72 on which the power amplifier circuit 11 is formed is superposed on the first base material 71 on which the electric circuit is formed in a plan view, the integrated circuit 70 is a miniaturization of the high frequency module 1. Can contribute to. Further, the heat generated by the power amplifier circuit 11 formed on the second base material 72 is further composed of the first semiconductor material having a higher thermal conductivity than the second semiconductor material constituting the second base material 72. It can be discharged to the first base material 71. At this time, since the low heat conductive member 73 having a lower heat conductivity than that of the second semiconductor material is arranged between the power amplification circuit 11 and the electric circuit, heat transfer from the power amplification circuit 11 to the electric circuit is suppressed. It is possible to suppress deterioration of the characteristics of the electric circuit due to heat.
また例えば、本実施の形態に係る集積回路７０において、低熱伝導部材７３の少なくとも一部は、平面視において電気回路の少なくとも一部と重なってもよい。
Further, for example, in the integrated circuit 70 according to the present embodiment, at least a part of the low heat conductive member 73 may overlap with at least a part of the electric circuit in a plan view.
これによれば、低熱伝導部材７３は、電力増幅回路１１から電気回路への伝熱を効果的に抑制することができ、熱による電気回路の特性の劣化を抑制することができる。
According to this, the low heat conduction member 73 can effectively suppress heat transfer from the power amplifier circuit 11 to the electric circuit, and can suppress deterioration of the characteristics of the electric circuit due to heat.
また例えば、本実施の形態に係る集積回路７０において、低熱伝導部材７３の少なくとも一部は、平面視において電力増幅回路１１の少なくとも一部と重なってもよい。
Further, for example, in the integrated circuit 70 according to the present embodiment, at least a part of the low heat conductive member 73 may overlap with at least a part of the power amplifier circuit 11 in a plan view.
これによれば、低熱伝導部材７３は、電力増幅回路１１から電気回路への伝熱を効果的に抑制することができ、熱による電気回路の特性の劣化を抑制することができる。
According to this, the low heat conduction member 73 can effectively suppress heat transfer from the power amplifier circuit 11 to the electric circuit, and can suppress deterioration of the characteristics of the electric circuit due to heat.
また例えば、本実施の形態に係る集積回路７０において、低熱伝導部材７３は、シート形状を有してもよい。
Further, for example, in the integrated circuit 70 according to the present embodiment, the low heat conductive member 73 may have a sheet shape.
これによれば、低熱伝導部材７３は、電力増幅回路１１から電気回路への伝熱経路を広く遮ることができるので、電力増幅回路１１から電気回路への伝熱を効果的に抑制することができ、熱による電気回路の特性の劣化を抑制することができる。
According to this, since the low heat conductive member 73 can widely block the heat transfer path from the power amplification circuit 11 to the electric circuit, it is possible to effectively suppress the heat transfer from the power amplification circuit 11 to the electric circuit. It is possible to suppress deterioration of the characteristics of the electric circuit due to heat.
また例えば、本実施の形態に係る集積回路７０において、電気回路は、電力増幅回路１１を制御する制御回路８０と、電力増幅回路１１の出力端に接続されるスイッチ回路５１と、電力増幅回路１１の入力端に接続されるスイッチ回路５２と、のうちの少なくとも１つを含んでもよい。
Further, for example, in the integrated circuit 70 according to the present embodiment, the electric circuit includes a control circuit 80 for controlling the power amplifier circuit 11, a switch circuit 51 connected to the output end of the power amplifier circuit 11, and a power amplifier circuit 11. It may include at least one of a switch circuit 52 connected to the input end of the.
これによれば、第２基材７２に形成された電力増幅回路１１に接続される制御回路８０並びにスイッチ回路５１及び５２のうちの少なくとも１つが第１基材７１に形成されるので、電力増幅回路１１と制御回路８０並びにスイッチ回路５１及び５２のうちの少なくとも１つとの間の配線長を短縮することができる。したがって、制御信号によるデジタルノイズの影響を低減したり、配線ロス及び配線の浮遊容量による不整合損を低減したりすることができる。
According to this, at least one of the control circuit 80 and the switch circuits 51 and 52 connected to the power amplification circuit 11 formed on the second base material 72 is formed on the first base material 71, so that the power amplification The wiring length between the circuit 11 and the control circuit 80 and at least one of the switch circuits 51 and 52 can be shortened. Therefore, it is possible to reduce the influence of digital noise due to the control signal, and reduce the wiring loss and the inconsistency loss due to the stray capacitance of the wiring.
また例えば、本実施の形態に係る集積回路７０において、第１基材７１は、面７１ａと、面７１ａの反対側にあって第２基材７２と向かい合う面７１ｂと、面７１ｂに配置された電極７１７と、を有してもよい。
Further, for example, in the integrated circuit 70 according to the present embodiment, the first base material 71 is arranged on the surface 71a, the surface 71b on the opposite side of the surface 71a and facing the second base material 72, and the surface 71b. It may have an electrode 717 and the like.
これによれば、第１基材７１内の熱を電極７１７を介してモジュール基板９０に排出することができ、集積回路７０の放熱性を向上させることができる。
According to this, the heat in the first base material 71 can be discharged to the module substrate 90 via the electrode 717, and the heat dissipation of the integrated circuit 70 can be improved.
また例えば、本実施の形態に係る集積回路７０において、第２基材７２は、第１基材７１と向かい合う面７２ａと、面７２ａの反対側にある面７２ｂと、面７２ｂに配置された電極７２４と、を有してもよい。
Further, for example, in the integrated circuit 70 according to the present embodiment, the second base material 72 has a surface 72a facing the first base material 71, a surface 72b on the opposite side of the surface 72a, and electrodes arranged on the surface 72b. 724 and may have.
これによれば、第２基材７２の面７２ｂから電極７２４を介してモジュール基板９０に熱を排出することができ、集積回路７０の放熱性を向上させることができる。
According to this, heat can be discharged from the surface 72b of the second base material 72 to the module substrate 90 via the electrode 724, and the heat dissipation of the integrated circuit 70 can be improved.
また例えば、本実施の形態に係る集積回路７０において、電力増幅回路１１は、コレクタ層７２１Ｃ、ベース層７２１Ｂ及びエミッタ層７２１Ｅを有する回路素子７２１を含み、コレクタ層７２１Ｃ、ベース層７２１Ｂ及びエミッタ層７２１Ｅは、第１基材７１側からこの順で積層されてもよい。
Further, for example, in the integrated circuit 70 according to the present embodiment, the power amplifier circuit 11 includes a circuit element 721 having a collector layer 721C, a base layer 721B, and an emitter layer 721E, and includes a collector layer 721C, a base layer 721B, and an emitter layer 721E. May be laminated in this order from the first base material 71 side.
これによれば、製造プロセスにおいてコレクタ層７２１Ｃ、ベース層７２１Ｂ及びエミッタ層７２１Ｅの各々に接続される配線を簡単にすることができる。また、平面視において、コレクタ層７２１Ｃの面積は、ベース層７２１Ｂ及びエミッタ層７２１Ｅの各々の面積よりも大きい。したがって、コレクタ層７２１Ｃを第１基材７１に接合することで、ベース層７２１Ｂ又はエミッタ層７２１Ｅを第１基材７１に接合する場合よりも、接合面積を増加させることができる。その結果、第１基材７１と第２基材７２との接合を強化して第２基材７２が第１基材７１から剥離することを抑制することができる。
According to this, it is possible to simplify the wiring connected to each of the collector layer 721C, the base layer 721B and the emitter layer 721E in the manufacturing process. Further, in a plan view, the area of the collector layer 721C is larger than the area of each of the base layer 721B and the emitter layer 721E. Therefore, by joining the collector layer 721C to the first base material 71, the joining area can be increased as compared with the case where the base layer 721B or the emitter layer 721E is joined to the first base material 71. As a result, it is possible to strengthen the bonding between the first base material 71 and the second base material 72 and prevent the second base material 72 from peeling off from the first base material 71.
また、本実施の形態に係る集積回路７０は、少なくとも一部がシリコン又は窒化ガリウムで構成され、電気回路（例えば、制御回路８０又はスイッチ回路５１若しくは５２）が形成された第１基材７１と、少なくとも一部がガリウムヒ素又はシリコンゲルマニウムで構成され、電力増幅回路１１が形成された第２基材７２と、少なくとも一部がガラス又はエポキシ樹脂で構成され、電気回路及び電力増幅回路１１の間に配置された低熱伝導部材７３と、を備え、第１基材７１の少なくとも一部は、平面視において第２基材７２の少なくとも一部と重なっている。
Further, the integrated circuit 70 according to the present embodiment has a first base material 71 in which at least a part thereof is made of silicon or gallium nitride and an electric circuit (for example, a control circuit 80 or a switch circuit 51 or 52) is formed. Between the second substrate 72, which is at least partially composed of gallium arsenic or silicon germanium and has a power amplification circuit 11 formed, and the electric circuit and the power amplification circuit 11 which is at least partially composed of glass or epoxy resin. The low thermal conductive member 73 arranged in the above is provided, and at least a part of the first base material 71 overlaps with at least a part of the second base material 72 in a plan view.
これによれば、電気回路が形成された第１基材７１に、電力増幅回路１１が形成された第２基材７２が平面視で重ねられるので、集積回路７０は、高周波モジュール１の小型化に貢献することができる。さらに、さらに、第２基材７２に形成された電力増幅回路１１で発生した熱を、第２基材７２を構成するガリウムヒ素又はシリコンゲルマニウムよりも高い熱伝導率を有するシリコン又は窒化ガリウムで構成された第１基材７１に排出することができる。このとき、第２半導体材料よりも低い熱伝導率を有するガラス又はエポキシ樹脂で構成された低熱伝導部材７３が電力増幅回路１１と電気回路との間に配置されるので、電力増幅回路１１から電気回路への伝熱を抑制することができ、熱による電気回路の特性の劣化を抑制することができる。
According to this, since the second base material 72 on which the power amplifier circuit 11 is formed is superposed on the first base material 71 on which the electric circuit is formed in a plan view, the integrated circuit 70 is a miniaturization of the high frequency module 1. Can contribute to. Further, the heat generated by the power amplification circuit 11 formed on the second base material 72 is composed of silicon or gallium nitride having a higher thermal conductivity than gallium arsenide or silicon germanium constituting the second base material 72. It can be discharged to the first base material 71. At this time, since the low heat conductive member 73 made of glass or epoxy resin having a lower heat conductivity than that of the second semiconductor material is arranged between the power amplification circuit 11 and the electric circuit, electricity is supplied from the power amplification circuit 11. It is possible to suppress heat transfer to the circuit, and it is possible to suppress deterioration of the characteristics of the electric circuit due to heat.
本実施の形態に係る高周波モジュール１は、主面９０ａを有するモジュール基板９０と、主面９０ａに配置された集積回路７０と、を備え、第１基材７１は、電極７１７を介して主面９０ａに接合され、第２基材７２は、電極７２４を介して主面９０ａに接合されている。
The high frequency module 1 according to the present embodiment includes a module substrate 90 having a main surface 90a and an integrated circuit 70 arranged on the main surface 90a, and the first base material 71 has a main surface via an electrode 717. It is bonded to 90a, and the second base material 72 is bonded to the main surface 90a via the electrode 724.
これによれば、第２基材７２に形成された電力増幅回路１１で発生した熱を、第２基材７２を構成する第２半導体材料よりも高い熱伝導率を有する第１半導体材料で構成された第１基材７１及び電極７１７を介してモジュール基板９０に効果的に排出することができる。このとき、低い熱伝導率を有する低熱伝導部材７３が電気回路及び電力増幅回路１１の間に配置されるので、電力増幅回路１１から電気回路への伝熱量を抑制し、熱による電気回路の特性の劣化を抑制することができる。
According to this, the heat generated by the power amplifier circuit 11 formed on the second base material 72 is composed of the first semiconductor material having a higher thermal conductivity than the second semiconductor material constituting the second base material 72. It can be effectively discharged to the module substrate 90 via the first base material 71 and the electrode 717. At this time, since the low heat conductive member 73 having a low heat conductivity is arranged between the electric circuit and the power amplification circuit 11, the amount of heat transfer from the power amplification circuit 11 to the electric circuit is suppressed, and the characteristics of the electric circuit due to heat are suppressed. Deterioration can be suppressed.
本実施の形態に係る通信装置５は、高周波信号を処理するＲＦＩＣ３と、ＲＦＩＣ３とアンテナ２との間で高周波信号を伝送する高周波モジュール１と、を備える。
The communication device 5 according to the present embodiment includes an RFIC 3 for processing a high frequency signal and a high frequency module 1 for transmitting a high frequency signal between the RFIC 3 and the antenna 2.
これによれば、通信装置５において、上記高周波モジュール１と同様の効果を実現することができる。
According to this, in the communication device 5, the same effect as that of the high frequency module 1 can be realized.
（変形例）
次に、変形例について説明する。本変形例では、低熱伝導部材の代わりに空隙部が用いられる点が、上記実施の形態と主として異なる。以下に、上記実施の形態と異なる点を中心に、本変形例について説明する。 (Modification example)
Next, a modification will be described. In this modification, a gap portion is used instead of the low heat conductive member, which is mainly different from the above embodiment. Hereinafter, the present modification will be described with a focus on the differences from the above-described embodiment.
次に、変形例について説明する。本変形例では、低熱伝導部材の代わりに空隙部が用いられる点が、上記実施の形態と主として異なる。以下に、上記実施の形態と異なる点を中心に、本変形例について説明する。 (Modification example)
Next, a modification will be described. In this modification, a gap portion is used instead of the low heat conductive member, which is mainly different from the above embodiment. Hereinafter, the present modification will be described with a focus on the differences from the above-described embodiment.
なお、本変形例に係る高周波モジュール１の回路構成図、平面図及び断面図は、上記実施の形態に係る高周波モジュール１と同様であるので、図示及び説明を省略し、本変形例に係る集積回路７０Ａの構成について、図７を参照しながら説明する。
Since the circuit configuration diagram, the plan view, and the cross-sectional view of the high frequency module 1 according to the present modification are the same as those of the high frequency module 1 according to the above embodiment, the illustration and description are omitted, and the integration according to the present modification is omitted. The configuration of the circuit 70A will be described with reference to FIG. 7.
図７は、変形例に係る高周波モジュール１の部分断面図である。具体的には、図７は、集積回路７０Ａの拡大断面図である。なお、図７において、配線及び電極の図示は一部を除いて省略されている。
FIG. 7 is a partial cross-sectional view of the high frequency module 1 according to the modified example. Specifically, FIG. 7 is an enlarged cross-sectional view of the integrated circuit 70A. In FIG. 7, the wiring and the illustration of the electrodes are omitted except for a part.
集積回路７０Ａは、低熱伝導部材７３の代わりに空隙部７３Ａを有する。空隙部７３Ａは、第１基材７１内に形成された空間であり、第２基材７２よりも低い熱伝導率を有する。本変形例では、空隙部７３Ａは、断面視において制御回路８０と電力増幅回路１１との間に配置されている。
The integrated circuit 70A has a gap portion 73A instead of the low heat conductive member 73. The void portion 73A is a space formed in the first base material 71 and has a lower thermal conductivity than the second base material 72. In this modification, the gap portion 73A is arranged between the control circuit 80 and the power amplifier circuit 11 in a cross-sectional view.
空隙部７３Ａは、第１基材７１内に均一又はランダムに混入しうる気泡とは異なり、意図的に所定の形状に形成された空隙である。したがって、空隙部７３Ａは、非球形状を有することができ、図７では、第１基材７１内でｘｙ平面に沿ってシート状に拡がっている。非球形状とは、球形ではない形状を意味する。なお、空隙部７３Ａの配置及び形状は、図７の配置及び形状に限定されない。
The void portion 73A is a void intentionally formed into a predetermined shape, unlike bubbles that can be uniformly or randomly mixed in the first base material 71. Therefore, the gap portion 73A can have a non-spherical shape, and in FIG. 7, it spreads like a sheet along the xy plane in the first base material 71. Non-spherical shape means a shape that is not spherical. The arrangement and shape of the gap portion 73A is not limited to the arrangement and shape of FIG. 7.
空隙部７３Ａの平面視における配置は、上記実施の形態における低熱伝導部材７３と同様であるので、図示及び説明を省略する。
Since the arrangement of the gap portion 73A in a plan view is the same as that of the low heat conductive member 73 in the above embodiment, the illustration and description will be omitted.
以上のように、本変形例に係る集積回路７０Ａは、少なくとも一部が第１半導体材料で構成され、電気回路（例えば、制御回路８０又はスイッチ回路５１若しくは５２）が形成された第１基材７１と、少なくとも一部が第１半導体材料よりも低い熱伝導率を有する第２半導体材料で構成され、電力増幅回路１１が形成された第２基材７２と、を備え、第１基材７１の内部には、電気回路及び電力増幅回路１１の間に位置する空隙部７３Ａが形成されており、第１基材７１の少なくとも一部は、平面視において第２基材７２の少なくとも一部と重なっている。
As described above, the integrated circuit 70A according to the present modification is a first base material in which at least a part thereof is made of a first semiconductor material and an electric circuit (for example, a control circuit 80 or a switch circuit 51 or 52) is formed. The first base material 71 comprises 71 and a second base material 72 in which at least a part thereof is composed of a second semiconductor material having a lower thermal conductivity than the first semiconductor material and a power amplification circuit 11 is formed. A gap portion 73A located between the electric circuit and the power amplification circuit 11 is formed inside the first base material 71, and at least a part of the first base material 71 is at least a part of the second base material 72 in a plan view. overlapping.
これによれば、電気回路が形成された第１基材７１に、電力増幅回路１１が形成された第２基材７２が平面視で重ねられるので、集積回路７０は、高周波モジュール１の小型化に貢献することができる。さらに、さらに、第２基材７２に形成された電力増幅回路１１で発生した熱を、第２基材７２を構成する第２半導体材料よりも高い熱伝導率を有する第１半導体材料で構成された第１基材７１に排出することができる。このとき、空隙部７３Ａが電力増幅回路１１と電気回路との間に配置されるので、電力増幅回路１１から電気回路への伝熱を抑制することができ、熱による電気回路の特性の劣化を抑制することができる。
According to this, since the second base material 72 on which the power amplifier circuit 11 is formed is superposed on the first base material 71 on which the electric circuit is formed in a plan view, the integrated circuit 70 is a miniaturization of the high frequency module 1. Can contribute to. Further, the heat generated by the power amplifier circuit 11 formed on the second base material 72 is further composed of the first semiconductor material having a higher thermal conductivity than the second semiconductor material constituting the second base material 72. It can be discharged to the first base material 71. At this time, since the gap portion 73A is arranged between the power amplification circuit 11 and the electric circuit, heat transfer from the power amplification circuit 11 to the electric circuit can be suppressed, and deterioration of the characteristics of the electric circuit due to heat can be suppressed. It can be suppressed.
また例えば、本変形例に係る集積回路７０Ａにおいて、空隙部７３Ａの少なくとも一部は、平面視において電気回路の少なくとも一部と重なってもよい。
Further, for example, in the integrated circuit 70A according to the present modification, at least a part of the gap portion 73A may overlap with at least a part of the electric circuit in a plan view.
これによれば、空隙部７３Ａは、電力増幅回路１１から電気回路への伝熱を効果的に抑制することができ、熱による電気回路の特性の劣化を抑制することができる。
According to this, the gap portion 73A can effectively suppress heat transfer from the power amplifier circuit 11 to the electric circuit, and can suppress deterioration of the characteristics of the electric circuit due to heat.
また例えば、本変形例に係る集積回路７０Ａにおいて、空隙部７３Ａの少なくとも一部は、平面視において電力増幅回路１１の少なくとも一部と重なってもよい。
Further, for example, in the integrated circuit 70A according to the present modification, at least a part of the gap portion 73A may overlap with at least a part of the power amplifier circuit 11 in a plan view.
これによれば、空隙部７３Ａは、電力増幅回路１１から電気回路への伝熱を効果的に抑制することができ、熱による電気回路の特性の劣化を抑制することができる。
According to this, the gap portion 73A can effectively suppress heat transfer from the power amplifier circuit 11 to the electric circuit, and can suppress deterioration of the characteristics of the electric circuit due to heat.
また例えば、本変形例に係る集積回路７０Ａにおいて、空隙部７３Ａは非球形状を有してもよい。
Further, for example, in the integrated circuit 70A according to this modification, the gap portion 73A may have a non-spherical shape.
これによれば、空隙部７３Ａの形状として非球形状を用いることができ、電力増幅回路１１及び電気回路の配置に適した形状を採用することで、電力増幅回路１１から電気回路への伝熱を効果的に抑制することができ、熱による電気回路の特性の劣化を抑制することができる。
According to this, a non-spherical shape can be used as the shape of the gap portion 73A, and by adopting a shape suitable for the arrangement of the power amplification circuit 11 and the electric circuit, heat is transferred from the power amplification circuit 11 to the electric circuit. Can be effectively suppressed, and deterioration of the characteristics of the electric circuit due to heat can be suppressed.
また例えば、本変形例に係る集積回路７０Ａにおいて、空隙部７３Ａは、第１基材７１内にシート状に拡がってもよい。
Further, for example, in the integrated circuit 70A according to the present modification, the gap portion 73A may be spread in a sheet shape in the first base material 71.
これによれば、電力増幅回路１１から電気回路への伝熱経路を広く遮ることができるので、電力増幅回路１１から電気回路への伝熱を効果的に抑制することができ、熱による電気回路の特性の劣化を抑制することができる。
According to this, since the heat transfer path from the power amplification circuit 11 to the electric circuit can be widely blocked, the heat transfer from the power amplification circuit 11 to the electric circuit can be effectively suppressed, and the electric circuit due to heat can be effectively suppressed. It is possible to suppress the deterioration of the characteristics of.
また例えば、本変形例に係る集積回路７０Ａにおいて、電気回路は、電力増幅回路１１を制御する制御回路８０と、電力増幅回路１１の出力端に接続されるスイッチ回路５１と、電力増幅回路１１の入力端に接続されるスイッチ回路５２と、のうちの少なくとも１つを含んでもよい。
Further, for example, in the integrated circuit 70A according to the present modification, the electric circuit includes a control circuit 80 for controlling the power amplifier circuit 11, a switch circuit 51 connected to the output end of the power amplifier circuit 11, and a power amplifier circuit 11. It may include at least one of a switch circuit 52 connected to the input end.
これによれば、第２基材７２に形成された電力増幅回路１１に接続される制御回路８０並びにスイッチ回路５１及び５２のうちの少なくとも１つが第１基材７１に形成されるので、電力増幅回路１１と制御回路８０並びにスイッチ回路５１及び５２のうちの少なくとも１つとの間の配線長を短縮することができる。したがって、制御信号によるデジタルノイズの影響を低減したり、配線ロス及び配線の浮遊容量による不整合損を低減したりすることができる。
According to this, at least one of the control circuit 80 and the switch circuits 51 and 52 connected to the power amplification circuit 11 formed on the second base material 72 is formed on the first base material 71, so that the power amplification The wiring length between the circuit 11 and the control circuit 80 and at least one of the switch circuits 51 and 52 can be shortened. Therefore, it is possible to reduce the influence of digital noise due to the control signal, and reduce the wiring loss and the inconsistency loss due to the stray capacitance of the wiring.
また例えば、本変形例に係る集積回路７０Ａにおいて、第１基材７１は、面７１ａと、面７１ａの反対側にあって第２基材７２と向かい合う面７１ｂと、面７１ｂに配置された電極７１７と、を有してもよい。
Further, for example, in the integrated circuit 70A according to the present modification, the first base material 71 has a surface 71a, a surface 71b on the opposite side of the surface 71a and facing the second base material 72, and an electrode arranged on the surface 71b. 717 and may have.
これによれば、第１基材７１内の熱を電極７１７を介してモジュール基板９０に排出することができ、集積回路７０Ａの放熱性を向上させることができる。
According to this, the heat in the first base material 71 can be discharged to the module substrate 90 via the electrode 717, and the heat dissipation of the integrated circuit 70A can be improved.
また例えば、本変形例に係る集積回路７０Ａにおいて、第２基材７２は、第１基材７１と向かい合う面７２ａと、面７２ａの反対側にある面７２ｂと、面７２ｂに配置された電極７２４と、を有してもよい。
Further, for example, in the integrated circuit 70A according to the present modification, the second base material 72 has a surface 72a facing the first base material 71, a surface 72b on the opposite side of the surface 72a, and an electrode 724 arranged on the surface 72b. And may have.
これによれば、第２基材７２の面７２ｂから電極７２４を介してモジュール基板９０に熱を排出することができ、集積回路７０Ａの放熱性を向上させることができる。
According to this, heat can be discharged from the surface 72b of the second base material 72 to the module substrate 90 via the electrode 724, and the heat dissipation of the integrated circuit 70A can be improved.
また例えば、本変形例に係る集積回路７０Ａにおいて、電力増幅回路１１は、コレクタ層７２１Ｃ、ベース層７２１Ｂ及びエミッタ層７２１Ｅを有する回路素子７２１を含み、コレクタ層７２１Ｃ、ベース層７２１Ｂ及びエミッタ層７２１Ｅは、第１基材７１側からこの順で積層されてもよい。
Further, for example, in the integrated circuit 70A according to the present modification, the power amplifier circuit 11 includes a circuit element 721 having a collector layer 721C, a base layer 721B, and an emitter layer 721E, and the collector layer 721C, the base layer 721B, and the emitter layer 721E are included. , May be laminated in this order from the first base material 71 side.
これによれば、製造プロセスにおいてコレクタ層７２１Ｃ、ベース層７２１Ｂ及びエミッタ層７２１Ｅの各々に接続される配線を簡単にすることができる。また、平面視において、コレクタ層７２１Ｃの面積は、ベース層７２１Ｂ及びエミッタ層７２１Ｅの各々の面積よりも大きい。したがって、コレクタ層７２１Ｃを第１基材７１に接合することで、ベース層７２１Ｂ又はエミッタ層７２１Ｅを第１基材７１に接合する場合よりも、接合面積を増加させることができる。その結果、第１基材７１と第２基材７２との接合を強化して第２基材７２が第１基材７１から剥離することを抑制することができる。
According to this, it is possible to simplify the wiring connected to each of the collector layer 721C, the base layer 721B and the emitter layer 721E in the manufacturing process. Further, in a plan view, the area of the collector layer 721C is larger than the area of each of the base layer 721B and the emitter layer 721E. Therefore, by joining the collector layer 721C to the first base material 71, the joining area can be increased as compared with the case where the base layer 721B or the emitter layer 721E is joined to the first base material 71. As a result, it is possible to strengthen the bonding between the first base material 71 and the second base material 72 and prevent the second base material 72 from peeling off from the first base material 71.
以上のように、本変形例に係る集積回路７０Ａは、少なくとも一部がシリコン又は窒化ガリウムで構成され、電気回路（例えば、制御回路８０又はスイッチ回路５１若しくは５２）が形成された第１基材７１と、少なくとも一部がガリウムヒ素又はシリコンゲルマニウムで構成され、電力増幅回路１１が形成された第２基材７２と、を備え、第１基材７１の内部には、電気回路及び電力増幅回路１１の間に位置する空隙部７３Ａが形成されており、第１基材７１の少なくとも一部は、平面視において第２基材７２の少なくとも一部と重なっている。
As described above, the integrated circuit 70A according to the present modification is a first base material in which at least a part thereof is made of silicon or gallium nitride and an electric circuit (for example, a control circuit 80 or a switch circuit 51 or 52) is formed. A second base material 72 in which at least a part thereof is composed of gallium arsenic or silicon germanium and a power amplification circuit 11 is formed is provided, and an electric circuit and a power amplification circuit are provided inside the first base material 71. A gap portion 73A located between 11 is formed, and at least a part of the first base material 71 overlaps with at least a part of the second base material 72 in a plan view.
これによれば、電気回路が形成された第１基材７１に、電力増幅回路１１が形成された第２基材７２が平面視で重ねられるので、集積回路７０は、高周波モジュール１の小型化に貢献することができる。さらに、さらに、第２基材７２に形成された電力増幅回路１１で発生した熱を、第２基材７２を構成するガリウムヒ素又はシリコンゲルマニウムよりも高い熱伝導率を有するシリコン又は窒化ガリウムで構成された第１基材７１に排出することができる。このとき、空隙部７３Ａが電力増幅回路１１と電気回路との間に配置されるので、電力増幅回路１１から電気回路への伝熱を抑制することができ、熱による電気回路の特性の劣化を抑制することができる。
According to this, since the second base material 72 on which the power amplifier circuit 11 is formed is superposed on the first base material 71 on which the electric circuit is formed in a plan view, the integrated circuit 70 is a miniaturization of the high frequency module 1. Can contribute to. Further, the heat generated by the power amplification circuit 11 formed on the second base material 72 is composed of silicon or gallium nitride having a higher thermal conductivity than gallium arsenide or silicon germanium constituting the second base material 72. It can be discharged to the first base material 71. At this time, since the gap portion 73A is arranged between the power amplification circuit 11 and the electric circuit, heat transfer from the power amplification circuit 11 to the electric circuit can be suppressed, and deterioration of the characteristics of the electric circuit due to heat can be suppressed. It can be suppressed.
本変形例に係る高周波モジュール１は、主面９０ａを有するモジュール基板９０と、主面９０ａに配置された集積回路７０と、を備え、第１基材７１は、電極７１７を介して主面９０ａに接合され、第２基材７２は、電極７２４を介して主面９０ａに接合されている。
The high frequency module 1 according to this modification includes a module substrate 90 having a main surface 90a and an integrated circuit 70 arranged on the main surface 90a, and the first base material 71 has a main surface 90a via an electrode 717. The second base material 72 is bonded to the main surface 90a via the electrode 724.
これによれば、第２基材７２に形成された電力増幅回路１１で発生した熱を、第２基材７２を構成する第２半導体材料よりも高い熱伝導率を有する第１半導体材料で構成された第１基材７１及び電極７１７を介してモジュール基板９０に効果的に排出することができる。このとき、空隙部７３Ａが電気回路及び電力増幅回路１１の間に形成されているので、電力増幅回路１１から電気回路への伝熱量を抑制し、熱による電気回路の特性の劣化を抑制することができる。
According to this, the heat generated by the power amplifier circuit 11 formed on the second base material 72 is composed of the first semiconductor material having a higher thermal conductivity than the second semiconductor material constituting the second base material 72. It can be effectively discharged to the module substrate 90 via the first base material 71 and the electrode 717. At this time, since the gap portion 73A is formed between the electric circuit and the power amplification circuit 11, the amount of heat transfer from the power amplification circuit 11 to the electric circuit is suppressed, and deterioration of the characteristics of the electric circuit due to heat is suppressed. Can be done.
（他の実施の形態）
以上、本発明に係る集積回路及び高周波モジュールについて、実施の形態に基づいて説明したが、本発明に係る集積回路及び高周波モジュールは、上記実施の形態に限定されるものではない。上記実施の形態における任意の構成要素を組み合わせて実現される別の実施の形態や、上記実施の形態に対して本発明の主旨を逸脱しない範囲で当業者が思いつく各種変形を施して得られる変形例や、上記高周波モジュールを内蔵した各種機器も本発明に含まれる。 (Other embodiments)
Although the integrated circuit and the high frequency module according to the present invention have been described above based on the embodiment, the integrated circuit and the high frequency module according to the present invention are not limited to the above embodiment. Another embodiment realized by combining arbitrary components in the above embodiment, or modifications obtained by applying various modifications to the above embodiments that can be conceived by those skilled in the art within the range not deviating from the gist of the present invention. Examples and various devices incorporating the above-mentioned high-frequency module are also included in the present invention.
以上、本発明に係る集積回路及び高周波モジュールについて、実施の形態に基づいて説明したが、本発明に係る集積回路及び高周波モジュールは、上記実施の形態に限定されるものではない。上記実施の形態における任意の構成要素を組み合わせて実現される別の実施の形態や、上記実施の形態に対して本発明の主旨を逸脱しない範囲で当業者が思いつく各種変形を施して得られる変形例や、上記高周波モジュールを内蔵した各種機器も本発明に含まれる。 (Other embodiments)
Although the integrated circuit and the high frequency module according to the present invention have been described above based on the embodiment, the integrated circuit and the high frequency module according to the present invention are not limited to the above embodiment. Another embodiment realized by combining arbitrary components in the above embodiment, or modifications obtained by applying various modifications to the above embodiments that can be conceived by those skilled in the art within the range not deviating from the gist of the present invention. Examples and various devices incorporating the above-mentioned high-frequency module are also included in the present invention.
例えば、上記実施の形態及び変形例では、高周波モジュール１は、ＦＤＤ用バンドに対応していたが、これに限定されない。例えば、高周波モジュール１は、時分割複信（ＴＤＤ：Time Division Duplex）用バンドに対応してもよく、ＦＤＤ用バンド及びＴＤＤ用バンドの両方に対応してもよい。この場合、高周波モジュール１は、ＴＤＤ用のバンドを含む通過帯域を有するフィルタ回路と、送信及び受信を切り替えるスイッチ回路とを備えればよい。
For example, in the above-described embodiment and modification, the high-frequency module 1 corresponds to the FDD band, but is not limited to this. For example, the high frequency module 1 may correspond to a time division duplex (TDD: Time Division Duplex) band, or may correspond to both an FDD band and a TDD band. In this case, the high frequency module 1 may include a filter circuit having a pass band including a band for TDD, and a switch circuit for switching transmission and reception.
本発明は、フロントエンド部に配置される高周波モジュールとして、携帯電話などの通信機器に広く利用できる。
The present invention can be widely used in communication devices such as mobile phones as a high frequency module arranged in the front end portion.
１ 高周波モジュール
２ アンテナ
３ ＲＦＩＣ
４ ＢＢＩＣ
５ 通信装置
１１ 電力増幅回路
２０、７０、７０Ａ 集積回路
２１ 低雑音増幅回路
４１、４２、４３、４４ インピーダンス整合回路
５１、５２、５３、５４、５５ スイッチ回路
６１、６２ デュプレクサ回路
６１Ｒ、６２Ｒ 受信フィルタ回路
６１Ｔ、６２Ｔ 送信フィルタ回路
７１ 第１基材
７１ａ、７１ｂ、７２ａ、７２ｂ、７３ａ、７３ｂ 面
７２ 第２基材
７２Ａ 半導体層
７２Ｂ エピタキシャル層
７３ 低熱伝導部材
７３Ａ 空隙部
８０ 制御回路
９０ モジュール基板
９０ａ、９０ｂ 主面
９１ 樹脂部材
９２ シールド電極層
１００ アンテナ接続端子
１１１、１１２ 高周波入力端子
１２１、１２２ 高周波出力端子
１３０ 制御端子
１５０ 外部接続端子
７１１ シリコン基板
７１２、７１４ 二酸化シリコン層
７１３ シリコン層
７１５ 窒化シリコン層
７１６、７１７、７２２、７２３、７２４ 電極
７１７ａ、７２４ａ 柱状導体
７１７ｂ、７２４ｂ バンプ電極
７１８ 樹脂層
７２１、７１３０ 回路素子
７２１Ｂ ベース層
７２１Ｃ コレクタ層
７２１Ｅ エミッタ層
７１４０ ビア電極 1 High frequency module 2Antenna 3 RFIC
4 BBIC
5Communication device 11 Power amplification circuit 20, 70, 70A Integrated circuit 21 Low noise amplification circuit 41, 42, 43, 44 Impedance matching circuit 51, 52, 53, 54, 55 Switch circuit 61, 62 Duplexer circuit 61R, 62R Receive filter Circuit 61T, 62T Transmission filter circuit 71 First base material 71a, 71b, 72a, 72b, 73a, 73b Surface 72 Second base material 72A Semiconductor layer 72B epitaxial layer 73 Low heat conductive member 73A Air gap 80 Control circuit 90 Module board 90a, 90b Main surface 91 Resin member 92 Shielded electrode layer 100 Antenna connection terminal 111, 112 High frequency input terminal 121, 122 High frequency output terminal 130 Control terminal 150 External connection terminal 711 Silicon substrate 712, 714 Silicon dioxide layer 713 Silicon layer 715 Silicon nitride layer 716 , 717, 722, 723, 724 Electrode 717a, 724a Columnar conductor 717b, 724b Bump electrode 718 Resin layer 721, 7130 Circuit element 721B Base layer 721C Collector layer 721E Emitter layer 7140 Via electrode
２ アンテナ
３ ＲＦＩＣ
４ ＢＢＩＣ
５ 通信装置
１１ 電力増幅回路
２０、７０、７０Ａ 集積回路
２１ 低雑音増幅回路
４１、４２、４３、４４ インピーダンス整合回路
５１、５２、５３、５４、５５ スイッチ回路
６１、６２ デュプレクサ回路
６１Ｒ、６２Ｒ 受信フィルタ回路
６１Ｔ、６２Ｔ 送信フィルタ回路
７１ 第１基材
７１ａ、７１ｂ、７２ａ、７２ｂ、７３ａ、７３ｂ 面
７２ 第２基材
７２Ａ 半導体層
７２Ｂ エピタキシャル層
７３ 低熱伝導部材
７３Ａ 空隙部
８０ 制御回路
９０ モジュール基板
９０ａ、９０ｂ 主面
９１ 樹脂部材
９２ シールド電極層
１００ アンテナ接続端子
１１１、１１２ 高周波入力端子
１２１、１２２ 高周波出力端子
１３０ 制御端子
１５０ 外部接続端子
７１１ シリコン基板
７１２、７１４ 二酸化シリコン層
７１３ シリコン層
７１５ 窒化シリコン層
７１６、７１７、７２２、７２３、７２４ 電極
７１７ａ、７２４ａ 柱状導体
７１７ｂ、７２４ｂ バンプ電極
７１８ 樹脂層
７２１、７１３０ 回路素子
７２１Ｂ ベース層
７２１Ｃ コレクタ層
７２１Ｅ エミッタ層
７１４０ ビア電極 1 High frequency module 2
4 BBIC
5
Claims (20)
- 少なくとも一部が第１半導体材料で構成され、電気回路が形成された第１基材と、
少なくとも一部が前記第１半導体材料よりも低い熱伝導率を有する第２半導体材料で構成され、電力増幅回路が形成された第２基材と、
少なくとも一部が前記第２半導体材料よりも低い熱伝導率を有する低熱伝導材料で構成され、前記電気回路及び前記電力増幅回路の間に配置された低熱伝導部材と、を備え、
前記第１基材の少なくとも一部は、平面視において前記第２基材の少なくとも一部と重なっている、
集積回路。 A first base material in which at least a part is composed of a first semiconductor material and an electric circuit is formed, and
A second base material in which at least a part thereof is made of a second semiconductor material having a lower thermal conductivity than the first semiconductor material and a power amplifier circuit is formed, and
At least a part thereof is made of a low thermal conductive material having a lower thermal conductivity than the second semiconductor material, and includes a low thermal conductive member arranged between the electric circuit and the power amplification circuit.
At least a part of the first base material overlaps with at least a part of the second base material in a plan view.
Integrated circuit. - 前記低熱伝導部材の少なくとも一部は、平面視において前記電気回路の少なくとも一部と重なっている、
請求項１に記載の集積回路。 At least a part of the low heat conductive member overlaps with at least a part of the electric circuit in a plan view.
The integrated circuit according to claim 1. - 前記低熱伝導部材の少なくとも一部は、平面視において前記電力増幅回路の少なくとも一部と重なっている、
請求項１又は２に記載の集積回路。 At least a part of the low heat conductive member overlaps with at least a part of the power amplifier circuit in a plan view.
The integrated circuit according to claim 1 or 2. - 前記低熱伝導部材はシート形状を有する、
請求項３に記載の集積回路。 The low heat conductive member has a sheet shape.
The integrated circuit according to claim 3. - 前記電気回路は、前記電力増幅回路を制御する制御回路と、前記電力増幅回路の出力端に接続される第１スイッチ回路と、前記電力増幅回路の入力端に接続される第２スイッチ回路と、のうちの少なくとも１つを含む、
請求項１～４のいずれか１項に記載の集積回路。 The electric circuit includes a control circuit for controlling the power amplifier circuit, a first switch circuit connected to the output end of the power amplification circuit, and a second switch circuit connected to the input end of the power amplification circuit. Including at least one of
The integrated circuit according to any one of claims 1 to 4. - 前記第１基材は、
第１面と、
前記第１面の反対側にあって前記第２基材と向かい合う第２面と、
前記第２面に配置された第１電極と、を有する、
請求項１～５のいずれか１項に記載の集積回路。 The first base material is
The first side and
The second surface on the opposite side of the first surface and facing the second base material,
It has a first electrode arranged on the second surface, and has.
The integrated circuit according to any one of claims 1 to 5. - 前記第２基材は、
前記第１基材と向かい合う第３面と、
前記第３面の反対側にある第４面と、
前記第４面に配置された第２電極と、を有する、
請求項１～６のいずれか１項に記載の集積回路。 The second base material is
The third surface facing the first base material and
The fourth surface on the opposite side of the third surface and
It has a second electrode arranged on the fourth surface.
The integrated circuit according to any one of claims 1 to 6. - 前記電力増幅回路は、コレクタ層、ベース層及びエミッタ層を有する回路素子を含み、
前記コレクタ層、前記ベース層及び前記エミッタ層は、前記第１基材側からこの順で積層されている、
請求項１～７のいずれか１項に記載の集積回路。 The power amplifier circuit includes circuit elements having a collector layer, a base layer and an emitter layer.
The collector layer, the base layer, and the emitter layer are laminated in this order from the first base material side.
The integrated circuit according to any one of claims 1 to 7. - 少なくとも一部がシリコン又は窒化ガリウムで構成され、電気回路が形成された第１基材と、
少なくとも一部がガリウムヒ素又はシリコンゲルマニウムで構成され、電力増幅回路が形成された第２基材と、
少なくとも一部がガラス又はエポキシ樹脂で構成され、前記電気回路及び前記電力増幅回路の間に配置された低熱伝導部材と、を備え、
前記第１基材の少なくとも一部は、平面視において前記第２基材の少なくとも一部と重なっている、
集積回路。 A first substrate, which is at least partially composed of silicon or gallium nitride and has an electric circuit formed therein.
A second base material in which at least a part is composed of gallium arsenide or silicon germanium and a power amplifier circuit is formed, and
It comprises a low thermal conductivity member, which is at least partially composed of glass or epoxy resin and is arranged between the electric circuit and the power amplification circuit.
At least a part of the first base material overlaps with at least a part of the second base material in a plan view.
Integrated circuit. - 少なくとも一部が第１半導体材料で構成され、電気回路が形成された第１基材と、
少なくとも一部が前記第１半導体材料よりも低い熱伝導率を有する第２半導体材料で構成され、電力増幅回路が形成された第２基材と、を備え、
前記第１基材の内部には、前記電気回路及び前記電力増幅回路の間に位置する空隙部が形成されており、
前記第１基材の少なくとも一部は、平面視において前記第２基材の少なくとも一部と重なっている、
集積回路。 A first base material in which at least a part is composed of a first semiconductor material and an electric circuit is formed, and
A second base material, which is at least partially composed of a second semiconductor material having a lower thermal conductivity than the first semiconductor material and has a power amplifier circuit formed therein, is provided.
Inside the first base material, a gap portion located between the electric circuit and the power amplification circuit is formed.
At least a part of the first base material overlaps with at least a part of the second base material in a plan view.
Integrated circuit. - 前記空隙部の少なくとも一部は、平面視において前記電気回路の少なくとも一部と重なっている、
請求項１０に記載の集積回路。 At least a portion of the gap overlaps with at least a portion of the electrical circuit in plan view.
The integrated circuit according to claim 10. - 前記空隙部の少なくとも一部は、平面視において前記電力増幅回路の少なくとも一部と重なっている、
請求項１０又は１１に記載の集積回路。 At least a part of the gap portion overlaps with at least a part of the power amplifier circuit in a plan view.
The integrated circuit according to claim 10 or 11. - 前記空隙部は非球形状を有する、
請求項１０～１２のいずれか１項に記載の集積回路。 The void has a non-spherical shape.
The integrated circuit according to any one of claims 10 to 12. - 前記空隙部は、前記第１基材内にシート状に拡がっている、
請求項１３に記載の集積回路。 The gap portion extends like a sheet in the first base material.
The integrated circuit according to claim 13. - 前記電気回路は、前記電力増幅回路を制御する制御回路と、前記電力増幅回路の出力端に接続される第１スイッチ回路と、前記電力増幅回路の入力端に接続される第２スイッチ回路と、のうちの少なくとも１つを含む、
請求項１０～１４のいずれか１項に記載の集積回路。 The electric circuit includes a control circuit for controlling the power amplifier circuit, a first switch circuit connected to the output end of the power amplification circuit, and a second switch circuit connected to the input end of the power amplification circuit. Including at least one of
The integrated circuit according to any one of claims 10 to 14. - 前記第１基材は、
第１面と、
前記第１面の反対側にあって前記第２基材と向かい合う第２面と、
前記第２面上に配置された第１電極と、を有する、
請求項１０～１５のいずれか１項に記載の集積回路。 The first base material is
The first side and
The second surface on the opposite side of the first surface and facing the second base material,
It has a first electrode arranged on the second surface, and has.
The integrated circuit according to any one of claims 10 to 15. - 前記第２基材は、
前記第１基材と向かい合う第３面と、
前記第３面の反対側にある第４面と、
前記第４面に配置された第２電極と、を有する、
請求項１０～１６のいずれか１項に記載の集積回路。 The second base material is
The third surface facing the first base material and
The fourth surface on the opposite side of the third surface and
It has a second electrode arranged on the fourth surface.
The integrated circuit according to any one of claims 10 to 16. - 前記電力増幅回路は、コレクタ層、ベース層及びエミッタ層を有する回路素子を含み、
前記コレクタ層、前記ベース層及び前記エミッタ層は、前記第１基材側からこの順で積層されている、
請求項１０～１７のいずれか１項に記載の集積回路。 The power amplifier circuit includes circuit elements having a collector layer, a base layer and an emitter layer.
The collector layer, the base layer, and the emitter layer are laminated in this order from the first base material side.
The integrated circuit according to any one of claims 10 to 17. - 少なくとも一部がシリコン又は窒化ガリウムで構成され、電気回路が形成された第１基材と、
少なくとも一部がガリウムヒ素又はシリコンゲルマニウムで構成され、電力増幅回路が形成された第２基材と、を備え、
前記第１基材の内部には、前記電気回路及び前記電力増幅回路の間に位置する空隙部が形成されており、
前記第１基材の少なくとも一部は、平面視において前記第２基材の少なくとも一部と重なっている、
集積回路。 A first substrate, which is at least partially composed of silicon or gallium nitride and has an electric circuit formed therein.
A second substrate, which is at least partially composed of gallium arsenide or silicon-germanium and has a power amplifier circuit formed therein.
Inside the first base material, a gap portion located between the electric circuit and the power amplification circuit is formed.
At least a part of the first base material overlaps with at least a part of the second base material in a plan view.
Integrated circuit. - 請求項１～１９のいずれか１項に記載の集積回路と、
前記集積回路が配置された主面を有するモジュール基板と、を備え、
前記第１基材は、第１電極を介して前記主面に接合され、
前記第２基材は、第２電極を介して前記主面に接合されている、
高周波モジュール。 The integrated circuit according to any one of claims 1 to 19.
A module board having a main surface on which the integrated circuit is arranged is provided.
The first base material is bonded to the main surface via the first electrode.
The second base material is bonded to the main surface via a second electrode.
High frequency module.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202180079658.4A CN116670817A (en) | 2020-12-02 | 2021-11-15 | Integrated circuit and high frequency module |
| US18/310,038 US20230268297A1 (en) | 2020-12-02 | 2023-05-01 | Integrated circuit and radio-frequency module |
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| Application Number | Priority Date | Filing Date | Title |
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| JP2020200424 | 2020-12-02 | ||
| JP2020-200424 | 2020-12-02 |
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| US18/310,038 Continuation US20230268297A1 (en) | 2020-12-02 | 2023-05-01 | Integrated circuit and radio-frequency module |
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| WO2022118646A1 true WO2022118646A1 (en) | 2022-06-09 |
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| Country | Link |
|---|---|
| US (1) | US20230268297A1 (en) |
| CN (1) | CN116670817A (en) |
| WO (1) | WO2022118646A1 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002217650A (en) * | 2000-11-29 | 2002-08-02 | Nokia Corp | Laminated power amplifier module |
| JP2005302873A (en) * | 2004-04-08 | 2005-10-27 | Mitsubishi Electric Corp | Semiconductor device, method for manufacturing the same and electronic apparatus |
| JP2009541985A (en) * | 2006-06-20 | 2009-11-26 | エヌエックスピー ビー ヴィ | Power amplifier assembly |
| JP2013251330A (en) * | 2012-05-30 | 2013-12-12 | Sumitomo Electric Ind Ltd | Semiconductor device |
-
2021
- 2021-11-15 CN CN202180079658.4A patent/CN116670817A/en active Pending
- 2021-11-15 WO PCT/JP2021/041934 patent/WO2022118646A1/en active Application Filing
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2023
- 2023-05-01 US US18/310,038 patent/US20230268297A1/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002217650A (en) * | 2000-11-29 | 2002-08-02 | Nokia Corp | Laminated power amplifier module |
| JP2005302873A (en) * | 2004-04-08 | 2005-10-27 | Mitsubishi Electric Corp | Semiconductor device, method for manufacturing the same and electronic apparatus |
| JP2009541985A (en) * | 2006-06-20 | 2009-11-26 | エヌエックスピー ビー ヴィ | Power amplifier assembly |
| JP2013251330A (en) * | 2012-05-30 | 2013-12-12 | Sumitomo Electric Ind Ltd | Semiconductor device |
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| Publication number | Publication date |
|---|---|
| CN116670817A (en) | 2023-08-29 |
| US20230268297A1 (en) | 2023-08-24 |
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