WO2022117656A1 - Power semiconductor device and a method for producing a power semiconductor device - Google Patents

Power semiconductor device and a method for producing a power semiconductor device Download PDF

Info

Publication number
WO2022117656A1
WO2022117656A1 PCT/EP2021/083791 EP2021083791W WO2022117656A1 WO 2022117656 A1 WO2022117656 A1 WO 2022117656A1 EP 2021083791 W EP2021083791 W EP 2021083791W WO 2022117656 A1 WO2022117656 A1 WO 2022117656A1
Authority
WO
WIPO (PCT)
Prior art keywords
base layer
layer
zone
semiconductor device
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2021/083791
Other languages
French (fr)
Inventor
Marco Bellini
Lars Knoll
Gianpaolo ROMANO
Yulieth ARANGO
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Energy Ltd
Original Assignee
Hitachi Energy Switzerland AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Energy Switzerland AG filed Critical Hitachi Energy Switzerland AG
Priority to JP2023600081U priority Critical patent/JP3244414U/en
Priority to CN202190000905.2U priority patent/CN220382104U/en
Priority to US18/039,920 priority patent/US12501668B2/en
Priority to DE212021000515.2U priority patent/DE212021000515U1/en
Publication of WO2022117656A1 publication Critical patent/WO2022117656A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H10P30/2042—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors into crystalline silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species

Definitions

  • the invention relates to a power semiconductor device and a method for producing a power semiconductor device.
  • Schottky power semiconductor devices e.g. metal oxide semiconductor field effect transistor (MOSFET) devices or insulated-gate bipolar transistor (IGBT) devices, offering excellent overall performance both for static and dynamic electrical parameters.
  • MOSFET metal oxide semiconductor field effect transistor
  • IGBT insulated-gate bipolar transistor
  • Schottky MOSFET devices do not feature doped contact regions or well regions, e.g. n+ doped contacts or p+ doped wells. This is to say that such Schottky power semiconductor devices do not have a metallurgical junction to protect a gate oxide.
  • a first aspect of the invention relates to a power semiconductor device.
  • the power semiconductor device is, for example a power MOSFET or a power IGBT. Further, the power semiconductor device is, for example, a Schottky power semiconductor device.
  • the power semiconductor device is based, for example, on silicon carbide. This is to say that the power semiconductor device is, for example, either a SiC power MOSFET or a SiC power IGBT.
  • the power semiconductor device comprises an electrode.
  • the electrode can comprise, for example a metal or consists of a metal.
  • the electrode is, for example, an electrode being externally contactable in an electrical conductive manner.
  • the electrode has, for example, a main plain of extension. Lateral directions are aligned parallel to the main plain of extension, and a vertical direction is aligned perpendicular to the main plain of extension.
  • the power semiconductor device comprises a base layer of a first conductivity type provided on the electrode.
  • the base layer for example, comprises a semiconductor material or consists of a semiconductor material.
  • the base layer is an epitaxial base layer.
  • the base layer comprises Silicon Carbide (SiC) , for example.
  • Silicon carbide is a chemical compound of silicon and carbon belonging to the group of carbides.
  • Silicon carbide is a polytype material, wherein some polytypes have a band gap of up to 3.33 eV, such as 2H-S1C, making SiC a semiconductor with a wide band gap.
  • the base layer comprises , for example n-type dopants such that the first conductivity type is an n-type conductivity .
  • a doping concentration of the first dopants of the base layer can be homogeneous . Alternatively, the doping concentration can increase towards the electrode or the doping concentration has a region of higher doping concentration at the electrode .
  • the base layer is , for example , in direct contact to the electrode or i f between the base layer and the electrode no layer of a second conductivity type is provided, the power semiconductor device is a power MOSFET .
  • an inj ecting layer of the second conductivity type is provided on the base layer .
  • the inj ecting layer is arranged between the base layer and the electrode .
  • the power semiconductor device is , for example , a power IGBT .
  • the inj ecting layer comprises p-type dopants such that the second conductivity type is a p-type conductivity .
  • the first conductivity type and the second conductivity type can be inversed .
  • the power semiconductor device comprises at least one contact layer provided on the base layer .
  • the contact layer is arranged on a top surface of the base layer, facing away from the electrode , for example .
  • the contact layer has , for example a main extension direction in lateral directions .
  • the contact layer is , for example , externally contactable in an electrical conductive manner .
  • at least two contact layers are provided on the base layer. In this case, the contact layers are spaced apart from one another.
  • the main extension directions of the contact layers for example, extend parallel to one another.
  • One of the at least two contact layers is formed, e.g., as a source of the power MOSFET and the other one of the at least two contact layers is formed, e.g., as a drain of the power MOSFET.
  • the power semiconductor device comprises a gate contact provided on the base layer and on the contact layer.
  • the gate contact has a main extension direction being parallel to the lateral directions, for example.
  • the main extension direction of the gate contact extends, for example, perpendicular to the main extension directions of the contact layer.
  • the gate contact comprises or consists of at least one of a metal and polysilicon, for example. Further, the gate contact is, at least in regions, externally contactable in an electrical conductive manner.
  • the power semiconductor device comprises an insulation layer between the gate contact and the base layer and between the contact layer and the gate contact.
  • the gate layer is embedded in the insulation layer. This is to say that the insulation layer covers all outer surfaces of the gate contact, except the region for externally contacting.
  • the insulation layer comprises, for example, a dielectric material.
  • the insulation layer is a gate oxide, for example.
  • the insulation layer includes high K dielectric stacks.
  • the k dielectric stacks comprise or consist of materials with a higher relative permittivity than silicon dioxide , so-called high-K materials .
  • the power semiconductor device comprises at least one zone of a second conductivity type di f ferent from the first conductivity type within the base layer .
  • the zone is , for example , embedded within the base layer .
  • embedded can mean that a top surface , a bottom surface and at least two side surfaces of the zone is covered by the base layer .
  • embedded means that an outer surface of the zone is completely covered by the base layer, e . g . , the zone is completely enclosed by the base layer in a three dimensional manner .
  • the zone can have a triangular, a squared, a rectangular, a round, an oval or an elliptic form in a cross section along one of the lateral directions and the vertical direction .
  • the zone comprises , for example p-type dopants such that the second conductivity type is a p-type conductivity .
  • the zone comprises n-type dopants such that the second conductivity type is an n-type conductivity .
  • the second conductivity type is di f ferent from the first conductivity type . This is to say i f the base layer comprises n-type dopants the zone comprises p-type dopants and vice versa .
  • the at least one zone is constructed and arranged to shi ft away a peak electric field generated in the base layer from the insulation layer between the gate contact and the base layer .
  • the peak electric field is an electrical field, which, for example , at least one of temporarily and locally strongly increases or decreases .
  • such electric field is , for example , a combination of two exponential parts , one exponentially increasing part and another exponentially decreasing part .
  • the at least one zone of the second conductivity type is shaped and arranged such that the zone shi fts away the peak electric field produced in the base layer from the interface between the insulation layer of the gate contact and a region of the base layer facing the gate contact .
  • the at least one contact layer is a metallic layer .
  • the metallic layers comprise a metal or consist of a metal .
  • An interface between the metallic layer and the base layer forms , for example , a Schottky contact .
  • a material composition such as a doping concentration of the base layer and a work function of the metallic layer, is selected such that a depletion zone is formed in a region of the interface within the base layer .
  • the at least one contact layer comprises or consists of a semiconductor material having a first region of the first conductivity and a second region of the second conductivity .
  • the first region is configured for external contacting .
  • the second region is arranged between the first region and the dri ft layer .
  • the base layer comprises a plain top surface and the at least one metallic layer does not extend into the base layer in vertical direction .
  • the top surface faces away from the electrode . This is to say that the metallic layer and the base layer do not overlap with one another in vertical direction . In this way, the contact does not require expensive implantation and activation steps .
  • the base layer comprises at least one recessed top surface and the at least one contact layer is provided on the at least one recessed top surface .
  • the base layer comprises a bar structure facing away from the electrode .
  • the bar structure comprises a top surface and at least one side surface .
  • the side surface connects the top surface of the bar structure with the recessed top surface of the base layer .
  • the bar structure extends , exemplarily along a main extension direction in lateral directions being perpendicular to the main extension direction of the gate contact . Further, the bar structure is arranged in a central position of the base layer .
  • the bar structure and the base layer are formed in one piece .
  • the bar structure is a part of the base layer .
  • the contact layer and the base layer overlap with one another in vertical direction .
  • At least one of the gate contact and the insulation layer partially overlaps with the at least one contact layer in lateral directions .
  • an overlap of the at least one of the gate contact and the insulation layer in lateral directions with the at least one contact layer is between at least 0 . 001 pm and at most 3 pm .
  • the overlap of the at least one of the gate contact and the insulation layer in lateral directions with the at least one contact layer is between at least 0 . 2 pm and at most 2 pm .
  • the at least one zone is provided centred in lateral directions with respect to the gate contact .
  • the power semiconductor device comprises at least two contact layers
  • the zone is arranged centred between the contact layers in lateral directions .
  • I f there is only a single zone the zone has equal distances to the contact layers in lateral directions .
  • a centred arrangement of the zone exemplarily improves the controllability of the electric field within the base layer such that the electric field can then extend symmetrically within the base layer .
  • the at least one zone has a main extension direction in lateral directions transverse to a main extension direction of the base layer in lateral directions .
  • the main extension direction of the zone is perpendicular to the main extension direction of the base layer in lateral directions .
  • the at least one zone has a length in lateral directions being equal to the length of the at least one contact layer .
  • the length of the at least one zone is , for example , an extend of the zone in lateral directions along the main extension direction of the zone .
  • the length of the contact layer is , for example , an extend of the contact layer in lateral directions along the main extension direction of the contact layer .
  • E . g . the main extension direction of the contact layers is parallel to the main extension direction of the zone .
  • the length of the zone is equal to a width of at least one of the gate contact and the insulation layer, for example .
  • the width of at least one of the gate contact and the insulation layer is , for example , an extend of at least one of the gate contact and the insulation layer in lateral directions perpendicular to the main extension direction of at least one of the gate contact and the insulation layer .
  • the device can have an improved resistance such that the resistance of the device is suf ficiently low .
  • a distance between the zone and the insulation layer is at most 1 pm .
  • the distance is the minimal distance in vertical direction between the zone and the insulation layer . It is possible that the zone and the insulation layer can be in direct contact with one another . Further, the distance between the zone and the insulation layer is at most 0 . 25 pm, for example .
  • the at least one zone comprises a peak doping concentration being at least 10 15 1 /cm 3 and at most 5xl 0 17 1 /cm 3 .
  • a doping concentration of the zone has a maximum value being the peak doping concentration value within the zone .
  • the at least one zone comprises a peak doping concentration being one to hundred times higher than a peak doping concentration of the base layer .
  • a thickness of the at least one zone is at least 0 . 1 pm and at most 1 pm .
  • the thickness is the minimal extension in vertical direction of the zone .
  • the thickness of the zone is , for example at least 0 . 2 pm and at most 0 . 6 pm .
  • the at least one zone has a width in lateral directions along a main extension direction of the base layer, which is less than 40 % of a length of the gate contact in lateral directions along the main extension direction of the base layer .
  • the main extension direction of the base layer equals a main extension direction of the gate contact .
  • I f the zone has a width being larger than 40 % of the length of the gate contact , a current flow through the base layer is hindered and signi ficantly increase an on-state resistance . Due to such a width of less than 40 % , the on- state resistance increase is negligible .
  • the power semiconductor device comprises at least two zones of the second conductivity type , wherein the at least two zones are provided in a common plane extending in lateral directions .
  • the power semiconductor device comprises at least three zones of the second conductivity type .
  • the at least three zones form a retrograde profile in a cross sectional view perpendicular to lateral directions .
  • the retrograde profile is a doping profile , wherein a peak doping concentration of the doping profile faces away from the contact layer .
  • a peak doping concentration of the retrograde profile faces away from the gate contact .
  • the power semiconductor device comprises the at least two contact layers , the peak is located in the centre between the contact layers .
  • a zone in a region of the peak is arranged further away from the gate contact in vertical direction than a zone in regions not located at the peak .
  • the zones not located at the peak are arranged symmetrically around the zone in the region of the peak .
  • the zones can be arranged on grid points of a regular grid .
  • the grid for example , is a triangular, rectangular or hexagonal grid .
  • the current can spread more evenly .
  • a so-called a dead zone for the current is located around each zone . Due to di f fusion, such a dead zone is , e . g . , smaller than the respective zone .
  • a plurality of zones being smaller than a single zone can spread the current better than the single zone being larger than the plurality of zones .
  • a second aspect of the invention relates to a method for producing a power semiconductor device .
  • the method produces a power semiconductor device described herein above . All features disclosed in connection with the power semiconductor device are therefore also disclosed in connection with the method and vice versa .
  • an electrode is provided .
  • a base layer of a first conductivity type is provided on the electrode .
  • at least one contact layer is applied on the base layer .
  • a gate contact and an insulation layer are applied on the base layer and at least one contact layer, wherein the insulation layer is applied between the gate contact and the base layer and between the at least one contact layer and the gate contact .
  • At least one zone of a second conductivity type is generated within the base layer, wherein the at least one zone is constructed and arranged to shi ft away a peak electric field generated in the base layer from the insulation layer between the gate contact and the base layer .
  • the zone is generated by implanting dopants of the second conductivity type within the base layer .
  • a material of the base layer is grown on top of the generated zone and the adj acent base layer, for example . Due to such an overgrowth process , the zone can be embedded within the base layer .
  • Figures 1 and 2 schematically show sectional views of a MOSFET according to the prior art .
  • Figure 3 schematically shows a current-voltage characteristic of a current for di f ferent gate voltages of a MOSFET according to the prior art .
  • Figure 4 schematically shows a current-voltage characteristic of a current for di f ferent voltages of a MOSFET according to the prior art .
  • Figures 5 schematically shows a sectional view of a power semiconductor device according to an embodiment .
  • Figures 6 schematically shows a doping profile of a MOSFET according to the prior art .
  • Figures 7 and 8 schematically shows a doping profile of a power semiconductor device according to an embodiment .
  • Figures 9 schematically shows an electrical field profile of a MOSFET according to the prior art .
  • Figures 10 and 11 schematically shows an electrical field profile of a power semiconductor device according to an embodiment .
  • Figures 12 schematically shows an electrical current density profile of a MOSFET according to the prior art .
  • Figures 13 and 14 schematically shows an electrical current density profile of a power semiconductor device according to an embodiment .
  • Figures 15 and 16 schematically show sectional views of a power semiconductor device according to an embodiment .
  • Figures 17 and 18 schematically show sectional views of a power semiconductor device according to an embodiment .
  • Figures 19 and 20 schematically show sectional views of a power semiconductor device according to an embodiment .
  • Figures 21 and 22 schematically show sectional views of a power semiconductor device according to an embodiment .
  • Figure 23 shows a flow diagram of a method for producing power semiconductor device according to an embodiment .
  • the MOSFET according to the prior art in Figure 1 comprises an electrode 2 , a base layer 3 being arranged on the electrode 2 , two contact layers 4 being arranged on the base layer 3 , a gate contact 5 being arranged on the base layer 3 , and an insulation layer 6 between the gate contact 5 and the base layer 3 .
  • FIG. 2 a cross-section P, marked in Figure 1 , through the contact layers 4 and the base layer 3 is shown . Further, a main extension direction of the base layer L3 in lateral directions is depicted in Figure 2 .
  • the current-voltage characteristic of Figure 3 shows a drain current Id for di f ferent gate voltages Vg of the MOSFET according to the prior art according to Figures 1 and 2 .
  • the current-voltage characteristic of Figure 5 shows a drain current Id for di f ferent drain voltages Vd of the MOSFET according to the prior art according to Figures 1 and 2 .
  • the power semiconductor device 1 according to the embodiment of Figure 5 comprises an electrode 2 on which a base layer 3 of a first conductivity type is provided . A top surface of the base layer 3 is plain . On this plain top surface of the base layer 3 , two contact layers 4 , each being a metallic layer, are arranged . In a side view of the power semiconductor device 1 , the metallic layers and the base layer 3 do not overlap with one another .
  • a gate contact 5 is provided on the base layer 3 and on the metallic layers .
  • the gate contact 5 is enclosed by an insulation layer 6 , except the region for externally contacting .
  • the insulation layer 6 is arranged between the gate contact 5 and the base layer 3 as well as between the at least two metallic layers and the gate contact 5 .
  • the gate contact 5 and the insulation layer 6 partially overlap in lateral directions with the metallic layers .
  • An overlap of the gate contact 5 and the insulation layer 6 with each of the metallic layers is , for example , is at least 0 . 2 pm and at most 2 pm .
  • a side surface of each of the metallic layers are completely covered by the insulation layer 6 .
  • a zone 7 of a second conductivity type is located within the base layer 3 .
  • an outer surface of the zone 7 is completely covered by the base layer 3 such that the zone 7 is completely enclosed by the base layer 3 in two dimensions .
  • the zone 7 is provided centred in lateral directions with respect to the gate contact 5 .
  • a distance between the zone 7 and the insulation layer 6 is at most 1 pm .
  • the base layer 3 of the first conductivity type comprises n-type dopants .
  • the zone 7 of a second conductivity type comprises p-type dopants . Due to such an arrangement of the zone 7 of the second conductivity type , a peak electric field generated in the base layer 3 is shi fted away from the insulation layer 6 between the gate contact 5 and the base layer 3 .
  • a simulation a doping profile according to Figure 6 corresponds to a MOSFET according to Figures 1 and 2 without having a zone 7 of the second conductivity type .
  • Simulations of doping profiles of the Figures 7 and 8 correspond to a power semiconductor device 1 with a zone 7 of a second conductivity type according to the embodiment of Figure 5 .
  • a doping concentration is represented by shaded areas .
  • shaded areas with a comparatively high density of lines corresponds to a comparatively high doping concentration .
  • shaded areas with a comparatively low density of lines corresponds to a comparatively low doping concentration .
  • the zone 7 of the second conductivity comprises a peak doping concentration being at least 10 15 1 /cm 3 and at most 5xl 0 17 l /cm 3 corresponding to the shaded area with the highest density of lines .
  • a simulation of an electric field profile according to Figure 9 is based on the simulated doping profile according to Figure 6 .
  • an absolute value of an electric field in V/cm is about 1 . 7xl 0 6 V/cm directly below the gate contact 5 in a first region .
  • An electric field of a second region, adj acent to the first region, is about 1 . 6xl 0 6 V/cm .
  • the simulations of an electric field profile according to Figures 10 and 11 are based on the doping profiles of Figures 7 and 8 , respectively .
  • An absolute value of an electric field directly below the gate contact 5 in a first region is reduced with respect to Figure 9 to about 4xl 0 5 V/cm and in a second region to about Ixl O 6 V/cm .
  • a simulation of an electric current density according to Figure 12 is based on the simulated doping profile according to Figure 6 .
  • the simulations of the electric current density according to Figures 13 and 14 are based on the doping profiles of Figures 7 and 8 , respectively .
  • the electric current density below directly below the gate contact 5 in a first region is less for the power semiconductor device 1 according to Figure 13 and 14 .
  • a density of lines of shown shaded areas correspond to a value of the electric current density .
  • the base body of the power semiconductor device 1 comprise in contrast to the embodiment in connection with Figure 5 a bar structure .
  • the bar structure and the base body are formed in one piece . Due to the bar structure , the base body comprises two recessed top surfaces . On each of the two recessed top surfaces one contact layer 4 is arranged .
  • the power semiconductor device 1 is an IGBT .
  • the zone 7 has a main extension direction L7 in lateral directions being perpendicular to a main extension direction of the base layer L3 .
  • the zone 7 has a width in lateral directions along the main extension direction of the base layer L3 , which is less than 40 % of a length of the gate contact 5 in lateral directions along the main extension direction of the base layer L3 .
  • the zone 7 being arranged centred between the two contact layers 4 in lateral directions extend along the main extension direction of the zone L7 over the whole width of the base layer 3 along the main extension direction of the zone L7 .
  • the base layer 3 according to Figures 17 and 18 comprises three zones 7 .
  • the zones 7 are arranged spaced apart from one another .
  • the main extension directions of the zones L7 are running parallel to one another .
  • the zones 7 are arranged in a common plane . This is to say that each zone 7 has a same minimal distant to the gate contact 5 .
  • the three zones 7 according to Figures 19 and 20 form a retrograde profile in a cross sectional view perpendicular to lateral directions .
  • the retrograde profile comprises a peak facing away from the gate contact 5 .
  • the zone 7 in the middle of the three zones 7 has a minimal distance to the gate contact 5 in vertical direction than the outer two zones 7 .
  • the power semiconductor device 1 according to the embodiment of Figures 21 and 22 comprises five zones 7 .
  • Each zone 7 does is formed of a square in plan view . In this embodiment , each zone 7 does not extend over the whole width of the base layer
  • each zones 7 forms a single pocket within the base layer 3 being completely, e . g . three dimensionally, surrounded by the base layer 3 .
  • One of the zones 7 is arranged in centred with respect to the gate contact 5 in lateral directions .
  • Four of the five zones 7 are arranged symmetrically around the zone 7 arranged centred .
  • These four zones 7 are arranged on grid points of a rectangular grid, e . g . in a box-like fashion .
  • an electrode 2 is provided and, in the method step 200 , a base layer 3 of a first conductivity type is provided on the electrode 2 .
  • a next method step 300 at least two contact layers 4 are applied on the base layer 3 .
  • a gate contact 5 and an insulation layer 6 are applied on the base layer 3 and at least two contact layers
  • insulation layer 6 is applied between the gate contact 5 and the base layer 3 and between the at least two contact layers 4 and the gate contact 5
  • At least one zone 7 of a second conductivity type is generated within the base layer 3 , wherein the at least one zone 7 is constructed and arranged to shi ft away a peak electric field generated in the base layer 3 from the insulation layer 6 between the gate contact 5 and the base layer 3 .

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)

Abstract

A power semiconductor device (1) is specified comprising - an electrode (2); - a base layer (3) of a first conductivity type provided on the electrode (2); - at least one contact layer (4) provided on the base layer (3); - a gate contact (5) provided on the base layer (3) and on the at least one contact layer (4); - an insulation layer (6) between the gate contact (5) and the base layer (3) and between the at least one contact layer (4) and the gate contact (5), and - at least one zone (7) of a second conductivity type within the base layer (3), - wherein the at least one zone (7) is constructed and arranged to shift away a peak electric field generated in the base layer (3) from the insulation layer (6) between the gate contact (5) and the base layer (3). Furthermore, a method for producing a power semiconductor device is specified.

Description

Description
Power semiconductor device and a method for producing a power semiconductor device
The invention relates to a power semiconductor device and a method for producing a power semiconductor device.
A large number of systems and applications benefit from modern power semiconductor devices with Schottky contacts, so called Schottky power semiconductor devices, e.g. metal oxide semiconductor field effect transistor (MOSFET) devices or insulated-gate bipolar transistor (IGBT) devices, offering excellent overall performance both for static and dynamic electrical parameters.
For example, Schottky MOSFET devices do not feature doped contact regions or well regions, e.g. n+ doped contacts or p+ doped wells. This is to say that such Schottky power semiconductor devices do not have a metallurgical junction to protect a gate oxide.
It is an object of the invention to provide a power semiconductor device, which has an improved reliability and to provide a method for producing such a power semiconductor device .
The object is achieved by the subject matter of the independent claims. Further, embodiments are evident from the dependent claims and the following description.
A first aspect of the invention relates to a power semiconductor device. The power semiconductor device is, for example a power MOSFET or a power IGBT. Further, the power semiconductor device is, for example, a Schottky power semiconductor device.
The power semiconductor device is based, for example, on silicon carbide. This is to say that the power semiconductor device is, for example, either a SiC power MOSFET or a SiC power IGBT.
According to the embodiment of the first aspect, the power semiconductor device comprises an electrode. The electrode can comprise, for example a metal or consists of a metal. For example, the electrode is, for example, an electrode being externally contactable in an electrical conductive manner.
The electrode has, for example, a main plain of extension. Lateral directions are aligned parallel to the main plain of extension, and a vertical direction is aligned perpendicular to the main plain of extension.
According to the embodiment, the power semiconductor device comprises a base layer of a first conductivity type provided on the electrode. The base layer, for example, comprises a semiconductor material or consists of a semiconductor material. Exemplarily, the base layer is an epitaxial base layer. The base layer comprises Silicon Carbide (SiC) , for example. Silicon carbide is a chemical compound of silicon and carbon belonging to the group of carbides. Silicon carbide is a polytype material, wherein some polytypes have a band gap of up to 3.33 eV, such as 2H-S1C, making SiC a semiconductor with a wide band gap. The base layer comprises , for example n-type dopants such that the first conductivity type is an n-type conductivity . A doping concentration of the first dopants of the base layer can be homogeneous . Alternatively, the doping concentration can increase towards the electrode or the doping concentration has a region of higher doping concentration at the electrode .
The base layer is , for example , in direct contact to the electrode or i f between the base layer and the electrode no layer of a second conductivity type is provided, the power semiconductor device is a power MOSFET .
Alternatively, an inj ecting layer of the second conductivity type is provided on the base layer . For example , the inj ecting layer is arranged between the base layer and the electrode . In this case , the power semiconductor device is , for example , a power IGBT .
For example , the inj ecting layer comprises p-type dopants such that the second conductivity type is a p-type conductivity . Alternatively, the first conductivity type and the second conductivity type can be inversed .
According to the embodiment , the power semiconductor device comprises at least one contact layer provided on the base layer . The contact layer is arranged on a top surface of the base layer, facing away from the electrode , for example . The contact layer has , for example a main extension direction in lateral directions . The contact layer is , for example , externally contactable in an electrical conductive manner . Furthermore, it is possible that at least two contact layers are provided on the base layer. In this case, the contact layers are spaced apart from one another. The main extension directions of the contact layers, for example, extend parallel to one another. One of the at least two contact layers is formed, e.g., as a source of the power MOSFET and the other one of the at least two contact layers is formed, e.g., as a drain of the power MOSFET.
According to the embodiment, the power semiconductor device comprises a gate contact provided on the base layer and on the contact layer. The gate contact has a main extension direction being parallel to the lateral directions, for example. The main extension direction of the gate contact extends, for example, perpendicular to the main extension directions of the contact layer.
The gate contact comprises or consists of at least one of a metal and polysilicon, for example. Further, the gate contact is, at least in regions, externally contactable in an electrical conductive manner.
According to the embodiment, the power semiconductor device comprises an insulation layer between the gate contact and the base layer and between the contact layer and the gate contact. For example, the gate layer is embedded in the insulation layer. This is to say that the insulation layer covers all outer surfaces of the gate contact, except the region for externally contacting.
The insulation layer comprises, for example, a dielectric material. The insulation layer is a gate oxide, for example. E.g. the insulation layer includes high K dielectric stacks. In this case , the k dielectric stacks comprise or consist of materials with a higher relative permittivity than silicon dioxide , so-called high-K materials .
According to the embodiment , the power semiconductor device comprises at least one zone of a second conductivity type di f ferent from the first conductivity type within the base layer . The zone is , for example , embedded within the base layer . In this context , embedded can mean that a top surface , a bottom surface and at least two side surfaces of the zone is covered by the base layer . It is further possible , that embedded means that an outer surface of the zone is completely covered by the base layer, e . g . , the zone is completely enclosed by the base layer in a three dimensional manner . The zone can have a triangular, a squared, a rectangular, a round, an oval or an elliptic form in a cross section along one of the lateral directions and the vertical direction .
The zone comprises , for example p-type dopants such that the second conductivity type is a p-type conductivity . Alternatively, the zone comprises n-type dopants such that the second conductivity type is an n-type conductivity . For example , the second conductivity type is di f ferent from the first conductivity type . This is to say i f the base layer comprises n-type dopants the zone comprises p-type dopants and vice versa .
According to the embodiment of the power semiconductor device , the at least one zone is constructed and arranged to shi ft away a peak electric field generated in the base layer from the insulation layer between the gate contact and the base layer . The peak electric field is an electrical field, which, for example , at least one of temporarily and locally strongly increases or decreases . For example , such electric field is , for example , a combination of two exponential parts , one exponentially increasing part and another exponentially decreasing part .
For example , the at least one zone of the second conductivity type is shaped and arranged such that the zone shi fts away the peak electric field produced in the base layer from the interface between the insulation layer of the gate contact and a region of the base layer facing the gate contact .
According to at least one embodiment of the power semiconductor device , the at least one contact layer is a metallic layer . Exemplarily, the metallic layers comprise a metal or consist of a metal .
An interface between the metallic layer and the base layer forms , for example , a Schottky contact . A material composition, such as a doping concentration of the base layer and a work function of the metallic layer, is selected such that a depletion zone is formed in a region of the interface within the base layer .
Alternatively, the at least one contact layer comprises or consists of a semiconductor material having a first region of the first conductivity and a second region of the second conductivity . In this case the first region is configured for external contacting . The second region is arranged between the first region and the dri ft layer . According to at least one embodiment of the power semiconductor device , the base layer comprises a plain top surface and the at least one metallic layer does not extend into the base layer in vertical direction . For example , the top surface faces away from the electrode . This is to say that the metallic layer and the base layer do not overlap with one another in vertical direction . In this way, the contact does not require expensive implantation and activation steps .
According to at least one embodiment of the power semiconductor device , the base layer comprises at least one recessed top surface and the at least one contact layer is provided on the at least one recessed top surface .
For example , the base layer comprises a bar structure facing away from the electrode . The bar structure comprises a top surface and at least one side surface . The side surface connects the top surface of the bar structure with the recessed top surface of the base layer . The bar structure extends , exemplarily along a main extension direction in lateral directions being perpendicular to the main extension direction of the gate contact . Further, the bar structure is arranged in a central position of the base layer .
E . g . the bar structure and the base layer are formed in one piece . This is to say that the bar structure is a part of the base layer . According to this embodiment , the contact layer and the base layer overlap with one another in vertical direction .
According to at least one embodiment of the power semiconductor device , at least one of the gate contact and the insulation layer partially overlaps with the at least one contact layer in lateral directions .
According to at least one embodiment of the power semiconductor device , an overlap of the at least one of the gate contact and the insulation layer in lateral directions with the at least one contact layer is between at least 0 . 001 pm and at most 3 pm . For example , the overlap of the at least one of the gate contact and the insulation layer in lateral directions with the at least one contact layer is between at least 0 . 2 pm and at most 2 pm .
According to at least one embodiment of the power semiconductor device , the at least one zone is provided centred in lateral directions with respect to the gate contact . For example , i f the power semiconductor device comprises at least two contact layers , the zone is arranged centred between the contact layers in lateral directions . I f there is only a single zone , the zone has equal distances to the contact layers in lateral directions .
A centred arrangement of the zone , exemplarily improves the controllability of the electric field within the base layer such that the electric field can then extend symmetrically within the base layer .
According to at least one embodiment of the power semiconductor device , the at least one zone has a main extension direction in lateral directions transverse to a main extension direction of the base layer in lateral directions . Exemplarily, the main extension direction of the zone is perpendicular to the main extension direction of the base layer in lateral directions . According to at least one embodiment of the power semiconductor device , the at least one zone has a length in lateral directions being equal to the length of the at least one contact layer . The length of the at least one zone is , for example , an extend of the zone in lateral directions along the main extension direction of the zone . The length of the contact layer is , for example , an extend of the contact layer in lateral directions along the main extension direction of the contact layer . E . g . the main extension direction of the contact layers is parallel to the main extension direction of the zone .
In addition or alternatively, the length of the zone is equal to a width of at least one of the gate contact and the insulation layer, for example . The width of at least one of the gate contact and the insulation layer is , for example , an extend of at least one of the gate contact and the insulation layer in lateral directions perpendicular to the main extension direction of at least one of the gate contact and the insulation layer .
Due to such dimensions of the zone , the device can have an improved resistance such that the resistance of the device is suf ficiently low .
According to at least one embodiment of the power semiconductor device , a distance between the zone and the insulation layer is at most 1 pm . The distance is the minimal distance in vertical direction between the zone and the insulation layer . It is possible that the zone and the insulation layer can be in direct contact with one another . Further, the distance between the zone and the insulation layer is at most 0 . 25 pm, for example .
Due to such distances the electric field is suf ficiently low within the base layer in regions of the insulation layer . At the same time , a production ef fort of the zone is reduced having the distance of at most 0 . 25 pm . Thus , a quality of the base layer is maintained . However, in case of using a zone having the distance of at most 1 pm current spreading is improved, as the current can spread more evenly .
According to at least one embodiment of the power semiconductor device , the at least one zone comprises a peak doping concentration being at least 1015 1 /cm3 and at most 5xl 017 1 /cm3. For example , a doping concentration of the zone has a maximum value being the peak doping concentration value within the zone .
According to at least one embodiment of the power semiconductor device , the at least one zone comprises a peak doping concentration being one to hundred times higher than a peak doping concentration of the base layer .
According to at least one embodiment of the power semiconductor device , a thickness of the at least one zone is at least 0 . 1 pm and at most 1 pm . The thickness is the minimal extension in vertical direction of the zone . Further, the thickness of the zone is , for example at least 0 . 2 pm and at most 0 . 6 pm .
According to at least one embodiment of the power semiconductor device , the at least one zone has a width in lateral directions along a main extension direction of the base layer, which is less than 40 % of a length of the gate contact in lateral directions along the main extension direction of the base layer . The main extension direction of the base layer equals a main extension direction of the gate contact . I f the zone has a width being larger than 40 % of the length of the gate contact , a current flow through the base layer is hindered and signi ficantly increase an on-state resistance . Due to such a width of less than 40 % , the on- state resistance increase is negligible .
According to at least one embodiment , the power semiconductor device comprises at least two zones of the second conductivity type , wherein the at least two zones are provided in a common plane extending in lateral directions .
According to at least one embodiment , the power semiconductor device comprises at least three zones of the second conductivity type .
According to at least one embodiment of the power semiconductor device , the at least three zones form a retrograde profile in a cross sectional view perpendicular to lateral directions . The retrograde profile is a doping profile , wherein a peak doping concentration of the doping profile faces away from the contact layer .
According to at least one embodiment of the power semiconductor device , a peak doping concentration of the retrograde profile faces away from the gate contact . For example , i f the power semiconductor device comprises the at least two contact layers , the peak is located in the centre between the contact layers . E . g . a zone in a region of the peak is arranged further away from the gate contact in vertical direction than a zone in regions not located at the peak . For example , the zones not located at the peak are arranged symmetrically around the zone in the region of the peak .
For example , the zones can be arranged on grid points of a regular grid . The grid, for example , is a triangular, rectangular or hexagonal grid .
Due to the arrangement of the zones according to the retrograde profile , the current can spread more evenly .
For example , a so-called a dead zone for the current is located around each zone . Due to di f fusion, such a dead zone is , e . g . , smaller than the respective zone . Thus , a plurality of zones being smaller than a single zone can spread the current better than the single zone being larger than the plurality of zones .
A second aspect of the invention relates to a method for producing a power semiconductor device . Preferably the method produces a power semiconductor device described herein above . All features disclosed in connection with the power semiconductor device are therefore also disclosed in connection with the method and vice versa .
According to the embodiment of the second aspect of the method, an electrode is provided .
According to the embodiment of the method, a base layer of a first conductivity type is provided on the electrode . According to the embodiment of the method, at least one contact layer is applied on the base layer .
According to the embodiment of the method, a gate contact and an insulation layer are applied on the base layer and at least one contact layer, wherein the insulation layer is applied between the gate contact and the base layer and between the at least one contact layer and the gate contact .
According to the embodiment of the method, at least one zone of a second conductivity type is generated within the base layer, wherein the at least one zone is constructed and arranged to shi ft away a peak electric field generated in the base layer from the insulation layer between the gate contact and the base layer . For example , the zone is generated by implanting dopants of the second conductivity type within the base layer . Subsequently, a material of the base layer is grown on top of the generated zone and the adj acent base layer, for example . Due to such an overgrowth process , the zone can be embedded within the base layer .
The subj ect matter of the invention will be explained in more detail in the following with reference to exemplary embodiments which are illustrated in the attached drawings .
Figures 1 and 2 schematically show sectional views of a MOSFET according to the prior art .
Figure 3 schematically shows a current-voltage characteristic of a current for di f ferent gate voltages of a MOSFET according to the prior art . Figure 4 schematically shows a current-voltage characteristic of a current for di f ferent voltages of a MOSFET according to the prior art .
Figures 5 schematically shows a sectional view of a power semiconductor device according to an embodiment .
Figures 6 schematically shows a doping profile of a MOSFET according to the prior art .
Figures 7 and 8 schematically shows a doping profile of a power semiconductor device according to an embodiment .
Figures 9 schematically shows an electrical field profile of a MOSFET according to the prior art .
Figures 10 and 11 schematically shows an electrical field profile of a power semiconductor device according to an embodiment .
Figures 12 schematically shows an electrical current density profile of a MOSFET according to the prior art .
Figures 13 and 14 schematically shows an electrical current density profile of a power semiconductor device according to an embodiment .
Figures 15 and 16 schematically show sectional views of a power semiconductor device according to an embodiment .
Figures 17 and 18 schematically show sectional views of a power semiconductor device according to an embodiment . Figures 19 and 20 schematically show sectional views of a power semiconductor device according to an embodiment .
Figures 21 and 22 schematically show sectional views of a power semiconductor device according to an embodiment .
Figure 23 shows a flow diagram of a method for producing power semiconductor device according to an embodiment .
The reference symbols used in the drawings , and their meanings , are listed in summary form in the list of reference symbols . In principle , identical parts are provided with the same reference symbols in the figures .
The MOSFET according to the prior art in Figure 1 comprises an electrode 2 , a base layer 3 being arranged on the electrode 2 , two contact layers 4 being arranged on the base layer 3 , a gate contact 5 being arranged on the base layer 3 , and an insulation layer 6 between the gate contact 5 and the base layer 3 .
According to Figure 2 a cross-section P, marked in Figure 1 , through the contact layers 4 and the base layer 3 is shown . Further, a main extension direction of the base layer L3 in lateral directions is depicted in Figure 2 .
The current-voltage characteristic of Figure 3 shows a drain current Id for di f ferent gate voltages Vg of the MOSFET according to the prior art according to Figures 1 and 2 .
The current-voltage characteristic of Figure 5 shows a drain current Id for di f ferent drain voltages Vd of the MOSFET according to the prior art according to Figures 1 and 2 . The power semiconductor device 1 according to the embodiment of Figure 5 comprises an electrode 2 on which a base layer 3 of a first conductivity type is provided . A top surface of the base layer 3 is plain . On this plain top surface of the base layer 3 , two contact layers 4 , each being a metallic layer, are arranged . In a side view of the power semiconductor device 1 , the metallic layers and the base layer 3 do not overlap with one another .
In addition, a gate contact 5 is provided on the base layer 3 and on the metallic layers . The gate contact 5 is enclosed by an insulation layer 6 , except the region for externally contacting . The insulation layer 6 is arranged between the gate contact 5 and the base layer 3 as well as between the at least two metallic layers and the gate contact 5 .
The gate contact 5 and the insulation layer 6 partially overlap in lateral directions with the metallic layers . An overlap of the gate contact 5 and the insulation layer 6 with each of the metallic layers is , for example , is at least 0 . 2 pm and at most 2 pm . Furthermore , a side surface of each of the metallic layers are completely covered by the insulation layer 6 .
Moreover, a zone 7 of a second conductivity type is located within the base layer 3 . In this sectional view an outer surface of the zone 7 is completely covered by the base layer 3 such that the zone 7 is completely enclosed by the base layer 3 in two dimensions . Further, the zone 7 is provided centred in lateral directions with respect to the gate contact 5 . For example , a distance between the zone 7 and the insulation layer 6 is at most 1 pm . For example , the base layer 3 of the first conductivity type comprises n-type dopants . In this case , the zone 7 of a second conductivity type comprises p-type dopants . Due to such an arrangement of the zone 7 of the second conductivity type , a peak electric field generated in the base layer 3 is shi fted away from the insulation layer 6 between the gate contact 5 and the base layer 3 .
A simulation a doping profile according to Figure 6 corresponds to a MOSFET according to Figures 1 and 2 without having a zone 7 of the second conductivity type .
Simulations of doping profiles of the Figures 7 and 8 correspond to a power semiconductor device 1 with a zone 7 of a second conductivity type according to the embodiment of Figure 5 . In this cross sectional views , a doping concentration is represented by shaded areas . Here , shaded areas with a comparatively high density of lines corresponds to a comparatively high doping concentration . Consequently, shaded areas with a comparatively low density of lines corresponds to a comparatively low doping concentration . For example , the zone 7 of the second conductivity comprises a peak doping concentration being at least 1015 1 /cm3 and at most 5xl 017l /cm3 corresponding to the shaded area with the highest density of lines .
A simulation of an electric field profile according to Figure 9 is based on the simulated doping profile according to Figure 6 . Here , an absolute value of an electric field in V/cm is about 1 . 7xl 06 V/cm directly below the gate contact 5 in a first region . An electric field of a second region, adj acent to the first region, is about 1 . 6xl 06 V/cm . The simulations of an electric field profile according to Figures 10 and 11 are based on the doping profiles of Figures 7 and 8 , respectively . An absolute value of an electric field directly below the gate contact 5 in a first region is reduced with respect to Figure 9 to about 4xl 05 V/cm and in a second region to about Ixl O6 V/cm .
A simulation of an electric current density according to Figure 12 is based on the simulated doping profile according to Figure 6 . The simulations of the electric current density according to Figures 13 and 14 are based on the doping profiles of Figures 7 and 8 , respectively . The electric current density below directly below the gate contact 5 in a first region is less for the power semiconductor device 1 according to Figure 13 and 14 . Here , a density of lines of shown shaded areas correspond to a value of the electric current density .
The base body of the power semiconductor device 1 according to the embodiment of Figures 15 and 16 comprise in contrast to the embodiment in connection with Figure 5 a bar structure . The bar structure and the base body are formed in one piece . Due to the bar structure , the base body comprises two recessed top surfaces . On each of the two recessed top surfaces one contact layer 4 is arranged .
Furthermore , between the electrode 2 and the base layer 3 , an inj ecting layer 8 of the second conductivity type is arranged . In this exemplary embodiment , the power semiconductor device 1 is an IGBT . According to Figure 16 , showing a schematic top view on the power semiconductor device 1 , the zone 7 has a main extension direction L7 in lateral directions being perpendicular to a main extension direction of the base layer L3 . Furthermore , the zone 7 has a width in lateral directions along the main extension direction of the base layer L3 , which is less than 40 % of a length of the gate contact 5 in lateral directions along the main extension direction of the base layer L3 .
The zone 7 being arranged centred between the two contact layers 4 in lateral directions extend along the main extension direction of the zone L7 over the whole width of the base layer 3 along the main extension direction of the zone L7 .
In contrast to the embodiment of Figures 15 and 16 the base layer 3 according to Figures 17 and 18 comprises three zones 7 . The zones 7 are arranged spaced apart from one another . Furthermore , the main extension directions of the zones L7 are running parallel to one another . In this embodiment , the zones 7 are arranged in a common plane . This is to say that each zone 7 has a same minimal distant to the gate contact 5 .
In contrast to the embodiment of Figures 17 and 18 the three zones 7 according to Figures 19 and 20 form a retrograde profile in a cross sectional view perpendicular to lateral directions . The retrograde profile comprises a peak facing away from the gate contact 5 . The zone 7 in the middle of the three zones 7 has a minimal distance to the gate contact 5 in vertical direction than the outer two zones 7 .
The power semiconductor device 1 according to the embodiment of Figures 21 and 22 comprises five zones 7 . Each zone 7 does is formed of a square in plan view . In this embodiment , each zone 7 does not extend over the whole width of the base layer
3 . Rather, each zones 7 forms a single pocket within the base layer 3 being completely, e . g . three dimensionally, surrounded by the base layer 3 . One of the zones 7 is arranged in centred with respect to the gate contact 5 in lateral directions . Four of the five zones 7 are arranged symmetrically around the zone 7 arranged centred . These four zones 7 are arranged on grid points of a rectangular grid, e . g . in a box-like fashion .
In the method step 100 , according to Figure 23 , an electrode 2 is provided and, in the method step 200 , a base layer 3 of a first conductivity type is provided on the electrode 2 .
Subsequently, in a next method step 300 at least two contact layers 4 are applied on the base layer 3 . In a next method step 400 , a gate contact 5 and an insulation layer 6 are applied on the base layer 3 and at least two contact layers
4 , wherein the insulation layer 6 is applied between the gate contact 5 and the base layer 3 and between the at least two contact layers 4 and the gate contact 5
In the method step 500 , at least one zone 7 of a second conductivity type is generated within the base layer 3 , wherein the at least one zone 7 is constructed and arranged to shi ft away a peak electric field generated in the base layer 3 from the insulation layer 6 between the gate contact 5 and the base layer 3 . List of reference symbols
1 power semiconductor device
2 electrode 3 base layer
4 contact layer
5 gate contact
6 insulation layer
7 zone 8 inj ecting layer
L3 main extension direction of the base layer
L7 main extension direction of the zone 100...500 method steps

Claims

- 22 - Claims
1. A power semiconductor device (1) comprising
- an electrode (2) ;
- a base layer (3) of a first conductivity type provided on the electrode (2) ;
- at least one contact layer (4) provided on the base layer
(3) ;
- a gate contact (5) provided on the base layer (3) and on the at least one contact layer (4) ;
- an insulation layer (6) between the gate contact (5) and the base layer (3) and between the at least one contact layer
(4) and the gate contact (5) , and
- at least one zone (7) of a second conductivity type different from the first conductivity type within the base layer ( 3 ) ,
- wherein the at least one contact layer (4) is arranged on a top surface of the base layer (3) , facing away from the electrode ( 2 ) ,
- wherein the at least one contact layer (4) is a metallic layer,
- an interface between the metallic layer and the base layer
(3) forms a Schottky contact,
- the at least one zone (7) is embedded within the base layer (3) , such that a top surface, a bottom surface and at least two side surfaces of the at least one zone (7) is covered by the base layer (3) , and
- wherein the at least one zone (7) is constructed and arranged to shift away a peak electric field generated in the base layer (3) from the insulation layer (6) between the gate contact (5) and the base layer (3) .
2. The power semiconductor device (1) according to the preceding claim, wherein
- the base layer (3) comprises a plain top surface and the at least one metallic layer does not extend into the base layer (3) in vertical direction, or
- the base layer (3) comprises at least one recessed top surface and the at least one contact layer (4) is provided on the at least one recessed top surface.
3. The power semiconductor device (1) according to one of the preceding claims, wherein at least one of the gate contact
(5) and the insulation layer (6) partially overlaps with the at least one contact layer (4) in lateral directions.
4. The power semiconductor device (1) according to one of the preceding claims, wherein an overlap of the at least one of the gate contact (5) and the insulation layer (6) in lateral directions with the at least one contact layer (4) is at least 0.001 pm and at most 3 pm.
5. The power semiconductor device (1) according to one of the preceding claims, wherein the at least one zone (7) is provided centred in lateral directions with respect to the gate contact (5) .
6. The power semiconductor device (1) according to one of the preceding claims, wherein the at least one zone (7) has a main extension direction (L7) in lateral directions transverse to a main extension direction of the base layer (L3) in lateral directions.
7. The power semiconductor device (1) according to the preceding claim, wherein the at least one zone (7) has a length in lateral directions being equal to a length of the at least one contact layer (4) .
8. The power semiconductor device (1) according to one of the preceding claims, wherein a distance between the at least one zone (7) and the insulation layer (6) is at most 1 pm.
9. The power semiconductor device (1) according to one of the preceding claims, wherein the at least one zone (7) comprises a peak doping concentration being at least 1015 1/cm3 and at most 5x1017 1/cm3.
10. The power semiconductor device (1) according to one of the preceding claims, wherein the at least one zone (7) comprises a peak doping concentration being one to hundred times higher than a peak doping concentration of the base layer ( 3 ) .
11. The power semiconductor device (1) according to one of the preceding claims, wherein a thickness of the at least one zone (7) is at least 0.1 pm and at most 1 pm.
12. The power semiconductor device (1) according to one of the preceding claims, wherein the at least one zone (7) has a width in lateral directions along a main extension direction of the base layer (L3) , which is less than 40 % of a length of the gate contact (5) in lateral directions along the main extension direction of the base layer (L3) .
13. The power semiconductor device (1) according to one of the preceding claims, with at least two zones (7) , wherein the at least two zones (7) are provided in a common plane extending in lateral directions. - 25 -
14. The power semiconductor device (1) according to one of the claims 1 to 12, with at least three zones (7) ,
- wherein the at least three zones (7) form a retrograde profile in a cross sectional view perpendicular to lateral directions, and
- wherein a peak doping concentration of the retrograde profile faces away from the gate contact (5) .
15. A Method for producing a power semiconductor device (1) comprising steps of: providing (c) an electrode (2) ; providing (200) a base layer (3) of a first conductivity type on the electrode (2) ; applying (300) at least one contact layer (4) on the base layer ( 3 ) ; applying (400) a gate contact (5) and an insulation layer (6) on the base layer (3) and at least one contact layer (4) , wherein the insulation layer (6) is applied between the gate contact (5) and the base layer (3) and between the at least one contact layer (4) and the gate contact (5) , and generating (500) at least one zone (7) of a second conductivity type within the base layer (3) ,
- wherein the at least one contact layer (4) is arranged on a top surface of the base layer (3) , facing away from the electrode ( 2 ) ,
- wherein the at least one contact layer (4) is a metallic layer,
- an interface between the metallic layer and the base layer (3) forms a Schottky contact,
- the at least one zone (7) is embedded within the base layer
(3) , such that a top surface, a bottom surface and at least - 26 - two side surfaces of the at least one zone (7) is covered by the base layer (3) , and wherein the at least one zone (7) is constructed and arranged to shift away a peak electric field generated in the base layer (3) from the insulation layer (6) between the gate contact (5) and the base layer (3) .
PCT/EP2021/083791 2020-12-03 2021-12-01 Power semiconductor device and a method for producing a power semiconductor device Ceased WO2022117656A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2023600081U JP3244414U (en) 2020-12-03 2021-12-01 Power semiconductor device and method for manufacturing power semiconductor device
CN202190000905.2U CN220382104U (en) 2020-12-03 2021-12-01 Power semiconductor device
US18/039,920 US12501668B2 (en) 2020-12-03 2021-12-01 Power semiconductor device and a method for producing a power semiconductor device
DE212021000515.2U DE212021000515U1 (en) 2020-12-03 2021-12-01 Power semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP20211565.5 2020-12-03
EP20211565.5A EP4009375B1 (en) 2020-12-03 2020-12-03 Power semiconductor device and a method for producing a power semiconductor device

Publications (1)

Publication Number Publication Date
WO2022117656A1 true WO2022117656A1 (en) 2022-06-09

Family

ID=73698650

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2021/083791 Ceased WO2022117656A1 (en) 2020-12-03 2021-12-01 Power semiconductor device and a method for producing a power semiconductor device

Country Status (6)

Country Link
US (1) US12501668B2 (en)
EP (1) EP4009375B1 (en)
JP (1) JP3244414U (en)
CN (1) CN220382104U (en)
DE (1) DE212021000515U1 (en)
WO (1) WO2022117656A1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5962893A (en) * 1995-04-20 1999-10-05 Kabushiki Kaisha Toshiba Schottky tunneling device
US6091108A (en) * 1997-11-13 2000-07-18 Abb Research Ltd. Semiconductor device of SiC having an insulated gate and buried grid region for high breakdown voltage
US20180308938A1 (en) * 2017-04-24 2018-10-25 Infineon Technologies Ag SiC Semiconductor Device with Offset in Trench Bottom

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH027571A (en) 1988-06-27 1990-01-11 Nissan Motor Co Ltd Semiconductor device
US6979863B2 (en) 2003-04-24 2005-12-27 Cree, Inc. Silicon carbide MOSFETs with integrated antiparallel junction barrier Schottky free wheeling diodes and methods of fabricating the same
US9530844B2 (en) * 2012-12-28 2016-12-27 Cree, Inc. Transistor structures having reduced electrical field at the gate oxide and methods for making same
EP3255676A1 (en) * 2016-06-09 2017-12-13 ABB Schweiz AG Vertical power semiconductor device and method for operating such a device
US10157983B2 (en) * 2017-03-09 2018-12-18 Maxpower Semiconductor Inc. Vertical power MOS-gated device with high dopant concentration N-well below P-well and with floating P-islands
US11056586B2 (en) * 2018-09-28 2021-07-06 General Electric Company Techniques for fabricating charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5962893A (en) * 1995-04-20 1999-10-05 Kabushiki Kaisha Toshiba Schottky tunneling device
US6091108A (en) * 1997-11-13 2000-07-18 Abb Research Ltd. Semiconductor device of SiC having an insulated gate and buried grid region for high breakdown voltage
US20180308938A1 (en) * 2017-04-24 2018-10-25 Infineon Technologies Ag SiC Semiconductor Device with Offset in Trench Bottom

Also Published As

Publication number Publication date
US12501668B2 (en) 2025-12-16
EP4009375A1 (en) 2022-06-08
US20240096937A1 (en) 2024-03-21
CN220382104U (en) 2024-01-23
JP3244414U (en) 2023-11-02
EP4009375B1 (en) 2024-03-06
DE212021000515U1 (en) 2023-08-22

Similar Documents

Publication Publication Date Title
US11233147B2 (en) Semiconductor device
CN113013227B (en) High voltage semiconductor device and method for manufacturing the same
EP3433880B1 (en) Superjunction power semiconductor devices with fast switching capability
US6621132B2 (en) Semiconductor device
US6825565B2 (en) Semiconductor device
US11605713B2 (en) Silicon carbide planar MOSFET with wave-shaped channel regions
KR101106535B1 (en) Power semiconductor device and manufacturing method thereof
JP6475635B2 (en) Semiconductor device with reduced electric field in gate oxide layer
CN105280711B (en) Charge compensation structure and fabrication therefor
EP2342753B1 (en) Insulated gate bipolar transistor
US11316021B2 (en) High density power device with selectively shielded recessed field plate
US11152503B1 (en) Silicon carbide MOSFET with wave-shaped channel regions
US20090273031A1 (en) Semiconductor device
US9013005B2 (en) Semiconductor device and method for manufacturing same
US7049644B2 (en) Lateral junction field effect transistor and method of manufacturing the same
CN115621316B (en) Body-gate lateral double diffused metal oxide semiconductor field effect transistor and manufacturing method thereof
US20200243513A1 (en) A concept for silicon carbide power devices
KR20220143249A (en) Superjunction semiconductor device and method for manufacturing same
US12501668B2 (en) Power semiconductor device and a method for producing a power semiconductor device
US11967634B2 (en) Semiconductor device and method of manufacturing the same
CN112289845A (en) Semiconductor device with JFET area layout design
US20260122960A1 (en) Power semiconductor device and method for producing a power semiconductor device
US20250203926A1 (en) Power semiconductor device and power converter including the same
US12557311B2 (en) Semiconductor device
US20260075861A1 (en) Manufacturing process for silicon carbide power electronic devices having an improved input capacitance definition of the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21823552

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 202347037681

Country of ref document: IN

WWE Wipo information: entry into national phase

Ref document number: 202190000905.2

Country of ref document: CN

Ref document number: 18039920

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: 2023600081

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 212021000515

Country of ref document: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21823552

Country of ref document: EP

Kind code of ref document: A1

WWG Wipo information: grant in national office

Ref document number: 18039920

Country of ref document: US