WO2022116302A1 - 液晶面板驱动电压极性反转方法及电路、液晶面板 - Google Patents

液晶面板驱动电压极性反转方法及电路、液晶面板 Download PDF

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Publication number
WO2022116302A1
WO2022116302A1 PCT/CN2020/137968 CN2020137968W WO2022116302A1 WO 2022116302 A1 WO2022116302 A1 WO 2022116302A1 CN 2020137968 W CN2020137968 W CN 2020137968W WO 2022116302 A1 WO2022116302 A1 WO 2022116302A1
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WIPO (PCT)
Prior art keywords
gate line
voltage signal
data voltage
row
liquid crystal
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Ceased
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PCT/CN2020/137968
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English (en)
French (fr)
Inventor
方晓莉
吴宇
肖光星
高翔
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TCL China Star Optoelectronics Technology Co Ltd
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TCL China Star Optoelectronics Technology Co Ltd
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Publication of WO2022116302A1 publication Critical patent/WO2022116302A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present application relates to the field of display technology, and in particular, to a method and circuit for polarity inversion of a driving voltage of a liquid crystal panel, and a liquid crystal panel.
  • 1line architecture can reduce the flicker problem of the display panel
  • 2line architecture or 1+2line architecture can improve the display panel caused by the viewing angle compensation algorithm.
  • Vertical stripes and diagonal lines have unique advantages in different applications.
  • the pixel units on the scan line will be turned on in sequence, and the driver
  • the polarity of the data voltage signal output on the IC will be reversed for every row or every two rows, and the frequent polarity reversal of the data voltage signal on the display panel will cause the driver
  • the temperature of the IC rises and the power consumption increases.
  • an embodiment of the present application provides a method for inverting the polarity of a driving voltage of a liquid crystal panel, which divides the grid lines of the liquid crystal panel into X continuous grid line groups, where X is an integer not less than 2;
  • the number of gate line rows in each gate line group is the same, and the polarity reversal operation of the driving voltage of each gate line group is performed within the time of 1/X frame Completion, for each gate line group, firstly, within the time of 1/2X frame, turn on the gate line row to which the first data voltage signal is applied to the corresponding pixel unit in turn, and turn on the pixel on the gate line row that is turned on. After the cell is loaded with the first data voltage signal, within the time of 1/2X frame, turn on the gate line row corresponding to the pixel unit to which the second data voltage signal is applied in turn, and load the pixel cell on the gate line row that is turned on. the second data voltage signal.
  • the driving voltage polarity inversion operation is performed on the X consecutive gate line groups in sequence from top to bottom.
  • the voltage polarity of the first data voltage signal is positive and the voltage polarity of the second data voltage signal is negative, or the voltage polarity of the first data voltage signal is negative.
  • the polarity is negative and the voltage polarity of the second data voltage signal is positive.
  • Tcon Only the second data voltage signal of the gate line row to which the second data voltage signal is applied to the corresponding pixel cell in the gate line group is stored in the line buffer data of the IC, and is loaded to the pixel cell on the gate line row that is turned on. After the second data voltage signal, the Tcon No data is stored in the line buffer data of the IC.
  • the gate line row to which the first data voltage signal is applied to the corresponding pixel unit corresponds to the gate line row of the odd-numbered row in the gate line group; the corresponding pixel unit is applied with the second data voltage signal.
  • the gate line behaviors of the data voltage signals correspond to the gate line lines of the even-numbered lines in the gate line group.
  • the gate line behavior to which the first data voltage signal is applied to the corresponding pixel unit corresponds to the order of 1, 2, 5, 6, 9, 10...1+ in the gate line group 4k, 2+4k gate line row; the gate line behavior to which the second data voltage signal is applied to the corresponding pixel unit corresponds to the order of 3, 4, 7, 8, 11, 12...3+4k in the gate line group , 4+4k grid lines; the k is a natural number.
  • the gate line behavior to which the first data voltage signal is applied to the corresponding pixel unit corresponds to the order of the gate line group as 1, 4, 5, 8, 9...4+4k, 5+4k gate line row; the gate line behavior to which the second data voltage signal is applied to the corresponding pixel unit corresponds to the gate line group in the order of 2, 3, 6, 7...2+4k, 3+4k line; the k is a natural number.
  • the present application also provides a circuit for driving voltage polarity inversion of a liquid crystal panel, the circuit adopts the above-mentioned method for driving voltage polarity inversion of a liquid crystal panel, and is used for driving the array substrate in the liquid crystal panel.
  • the liquid crystal panel driving voltage polarity inversion method includes:
  • the number of gate line rows in each gate line group is the same, and the polarity reversal operation of the driving voltage of each gate line group is performed within the time of 1/X frame Completion, for each gate line group, firstly, within the time of 1/2X frame, turn on the gate line row to which the first data voltage signal is applied to the corresponding pixel unit in turn, and turn on the pixel on the gate line row that is turned on. After the cell is loaded with the first data voltage signal, within the time of 1/2X frame, turn on the gate line row corresponding to the pixel unit to which the second data voltage signal is applied in turn, and load the pixel cell on the gate line row that is turned on. the second data voltage signal.
  • the driving voltage polarity inversion operation is performed on the X consecutive gate line groups in sequence from top to bottom.
  • the voltage polarity of the first data voltage signal is positive and the voltage polarity of the second data voltage signal is negative, or the voltage polarity of the first data voltage signal is negative.
  • the polarity is negative and the voltage polarity of the second data voltage signal is positive.
  • the gate line row to which the first data voltage signal is applied to the corresponding pixel unit corresponds to the gate line row of the odd-numbered row in the gate line group; the corresponding pixel unit is applied with the second data voltage signal.
  • the gate line behaviors of the data voltage signals correspond to the gate line lines of the even-numbered lines in the gate line group.
  • the driving architecture of the liquid crystal panel adopts the 1-line architecture
  • the gates of the odd-numbered rows of the first gate line group are turned on in turn.
  • Line row load the first data voltage signal to the pixel unit on the gate line row that is turned on, within the time of the 2X 1/2X frame, turn on the gate line row of the even row in turn, and turn on the gate line row of the turned on gate line row.
  • the pixel unit loads the second data voltage signal.
  • the gate line behavior to which the first data voltage signal is applied to the corresponding pixel unit corresponds to the order of 1, 2, 5, 6, 9, 10...1+ in the gate line group 4k, 2+4k gate line row; the gate line behavior to which the second data voltage signal is applied to the corresponding pixel unit corresponds to the order of 3, 4, 7, 8, 11, 12...3+4k in the gate line group , 4+4k grid lines; the k is a natural number.
  • the first gate line group in the first gate line group is turned on in turn. 2, 5, 6, 9, 10, 1+4k, 2+4k gate line rows, load the first data voltage signal to the pixel unit on the gate line row that is turned on, at the time of the 2X 1/2X frame Inside, turn on the 3rd, 4th, 7th, 8, 11, 12, 3+4k, 4+4k gate line rows in the first gate line group in turn, and load the second gate line row to the pixel unit on the opened gate line row.
  • Data voltage signal; the k is a natural number.
  • the gate line behavior to which the first data voltage signal is applied to the corresponding pixel unit corresponds to the order of the gate line group as 1, 4, 5, 8, 9...4+4k, 5+4k gate line row; the gate line behavior to which the second data voltage signal is applied to the corresponding pixel unit corresponds to the gate line group in the order of 2, 3, 6, 7...2+4k, 3+4k line line.
  • the array substrate includes: a base substrate, gate lines and data lines formed on the base substrate, and the gate lines and the data lines define pixel units;
  • the circuit includes: a gate line driving circuit connected with the gate line and a data driving circuit connected with the data line;
  • the gate line driving circuit is used to turn on the gate line row corresponding to the pixel unit in a certain gate line group to which the first data voltage signal is applied or the corresponding pixel unit to which the second data voltage signal is applied within the time of 1/2X frame. the grid line row;
  • the data driving circuit is configured to load a first data voltage signal to the pixel cells on the gate line row that are turned on or load a second data voltage signal to the pixel cells on the gate line row that is turned on.
  • the present application also provides a liquid crystal panel using the above-mentioned liquid crystal panel driving voltage polarity inversion circuit.
  • the liquid crystal panel driving voltage polarity inversion method divides the gate lines of the liquid crystal panel into X consecutive gate line groups, first applies the first data voltage signal to the corresponding pixel units in a gate line group, and then applies the first data voltage signal to the remaining pixel units.
  • the second data voltage signal is applied to the pixel units in the same gate line group, that is, the pixel units in the same gate line group only need to perform the driving voltage polarity inversion operation once.
  • the polarity of the row will be reversed, reducing the frequency of voltage polarity reversal and reducing the driver
  • the rising temperature of the IC achieves the purpose of saving power.
  • the gate lines of the liquid crystal panel are divided into X gate line groups, and the polarity inversion operation is performed for each gate line group, and the line buffer data of the Tcon IC can only be stored.
  • the unloaded data voltage signal in the gate line group saves Tcon Purpose of IC Resources.
  • FIG. 1 is a flowchart of a method for polarity inversion of a driving voltage of a liquid crystal panel provided by an embodiment of the present application;
  • FIG. 2 is a schematic diagram of dividing the grid lines of the liquid crystal panel into 3 continuous grid line groups from top to bottom in an embodiment of the present application;
  • FIGS. 3( a ) to 3 ( f ) are schematic diagrams of polarities of the first 1/6 frame to the sixth 1/6 frame of the display panel when the method for polarity inversion of the driving voltage of the liquid crystal panel provided by the embodiment of the present application is adopted. .
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, features defined as “first”, “second” may expressly or implicitly include one or more of said features. In the description of the present application, “plurality” means two or more, unless otherwise expressly and specifically defined.
  • a first feature "on” or “under” a second feature may include direct contact between the first and second features, or may include the first and second features Not directly but through additional features between them.
  • the first feature being “above”, “over” and “above” the second feature includes the first feature being directly above and obliquely above the second feature, or simply means that the first feature is level higher than the second feature.
  • the first feature is “below”, “below” and “below” the second feature includes the first feature being directly below and diagonally below the second feature, or simply means that the first feature has a lower level than the second feature.
  • An embodiment of the present application provides a method for inverting the polarity of a driving voltage of a liquid crystal panel.
  • the specific flowchart is shown in FIG. 1 .
  • the grid lines of the liquid crystal panel are evenly divided into X continuous grid line groups from top to bottom. An integer less than 2; within a 1/X frame time, for a gate line group, firstly within a 1/2X frame time, turn on the gate line row corresponding to the pixel unit to which the first data voltage signal is applied in turn, and then turn on the gate line row to which the first data voltage signal is applied to the pixel unit.
  • the gate line rows to which the second data voltage signal is applied to the corresponding pixel cells are turned on in turn within the time of 1/2X frame, and the gate line rows to which the second data voltage signal is applied are turned on in turn within the time of 1/2X frame.
  • the pixel units on the gate line row are loaded with a second data voltage signal, the polarity of the first data voltage signal and the second data voltage signal are opposite, the voltage polarity of the first data voltage signal is positive and the voltage of the second data voltage signal The polarity is negative, or the voltage polarity of the first data voltage signal is negative and the voltage polarity of the second data voltage signal is positive.
  • the same driving voltage polarity inversion operation of the previous gate line group is performed until the driving voltage polarity inversion operation for X gate line groups is completed within one frame.
  • the pixel units in the same gate line group only need to perform the driving voltage polarity inversion operation once, compared to the data voltage signal in each row or each row in the driving process of the existing display panel.
  • the polarity of the two lines will be reversed, reducing the frequency of voltage polarity reversal and reducing the driver
  • the rising temperature of the IC achieves the purpose of saving power.
  • the driving voltage polarity inversion operation when the driving voltage polarity inversion operation is performed on the X continuous gate line groups, the driving voltage polarity inversion operation can be performed on each gate line group in sequence from top to bottom, and the specific process is shown in FIG. 1 . .
  • the driving voltage polarity inversion operation may also be performed on each gate line group in sequence according to a preset sequence.
  • the grid lines of the liquid crystal panel instead of dividing the grid lines of the liquid crystal panel into X consecutive grid line groups from top to bottom, the grid lines of the liquid crystal panel may be divided into grid line rows. For different gate line groups, the driving voltage polarity inversion operation is performed on each gate line group respectively.
  • the second data voltage signal of the gate line row of the signal after loading the second data voltage signal to the pixel unit on the gate line row that is turned on, Tcon No data is stored in the line buffer data of the IC.
  • the storage rule of the line buffer data of the Tcon IC solves whether it is a 1line structure, a 2line structure or a 1+2line structure.
  • the line buffer data of the IC stores the unloaded data voltage signals in the entire display panel, which consumes more Tcon IC resources and achieves the effect of relatively saving Tcon IC resources. It should be noted that, in some specific implementation manners of the liquid crystal panel driving voltage polarity inversion method in the embodiments of the present application, Tcon The line buffer data of the IC can also store unloaded data voltage signals in the entire display panel as needed.
  • the data driving frequency of the liquid crystal panel is set as frame_rate, and the resolution is M*N. If the grid lines of the LCD panel are divided into X continuous grid line groups from top to bottom, X is If the integer is not less than 2, the linebuffer (line buffer) data of Tcon IC has N/2X pieces, and the gate driving frequency is 2X*frame_rate.
  • the gates of the 1st, 3rd, 5th, 7th... rows (that is, odd-numbered rows) in the first gate line group are turned on in turn within the time of the first 1/2X frame.
  • Line row load the first data voltage signal to the pixel unit on the gate line row that is turned on.
  • the linebuffer stores the 2nd, 4th, 6th, 8th... rows (that is, even rows) in the first gate line group.
  • the second data voltage signal of the gate line row turns on the gate lines of the 2nd, 4th, 6th, 8th...
  • the second data voltage signal is loaded to the pixel units on the row of gate lines that are turned on, and there is no data stored in the linebuffer at this time.
  • the linebuffer stores the second data voltage signal of the 2nd, 4th, 6th, 8th... row (ie, even-numbered row) gate line row in the second gate line group.
  • the pixel unit loads the second data voltage signal, and no data is stored in the linebuffer at this time.
  • the second data voltage signal is loaded to the pixel unit on the gate line row that is turned on, and no data is stored in the linebuffer at this time; thus, the polarity inversion operation of the driving voltages for the X gate line groups is completed within one frame.
  • the gate line rows of rows 3, 4, 7, 8, 11, 12... that is, rows 3+4k, 4+4k, k is a natural number
  • the gate lines are opened in the direction of the first gate line group.
  • the second data voltage signal is loaded on the pixel units on the gate line row of the 2nd gate line, and no data is stored in the linebuffer at this time.
  • the second data voltage signal of the row (that is, row 3+4k, row 4+4k, k is a natural number) of the gate line row, within the time of the fourth 1/2X frame, turn on the second gate line group in turn Lines 3, 4, 7, 8, 11, 12... (that is, lines 3+4k, 4+4k, k is a natural number), load the second pixel unit on the opened gate line Data voltage signal, no data is stored in the linebuffer at this time.
  • the second data voltage signal of the gate line row within the time of the 2Xth 1/2X frame , open the gate line row of row 3, 4, 7, 8, 11, 12... (ie row 3+4k, 4+4k, k is a natural number) in the Xth gate line group in turn, and turn on the gate line row to be opened.
  • the pixel units on the gate line row are loaded with the second data voltage signal, and there is no data stored in the linebuffer at this time; thus, the polarity inversion operation of the driving voltages for the X gate line groups is completed within one frame.
  • the lines 1, 4, 5, 8, 9... in the first gate line group are turned on in sequence (that is, the first 4+4k, 5+4k row, k is a natural number) gate line row, load the first data voltage signal to the pixel unit on the opened gate line row, at this time, the linebuffer stores the first gate line group in the first gate line group.
  • 2, 3, 6, 7... rows that is, rows 2+4k, 3+4k, k is a natural number
  • the second data voltage signal of the gate line row is turned on in sequence within the time of the second 1/2X frame Lines 2, 3, 6, 7...
  • the gate line row load the first data voltage signal to the pixel unit on the gate line row that is turned on, at this time, the linebuffer stores the 2nd, 3rd, 6th, 7th... rows in the second gate line group (that is, the 2nd, 3rd, 6th, 7th...
  • the grid lines of the LCD panel are equally divided into 3 consecutive grid line groups from top to bottom, as shown in Figure 2.
  • the panel driving structure adopts a 1-line structure, and adopts the liquid crystal panel driving voltage polarity inversion method according to the embodiment of the present application. shown in Figure 3(f).
  • the linebuffer stores the second, fourth, sixth, eighth... 718 in the second gate line group , 360 second data voltage signals in 720 rows of gate lines, as shown in Figure 3(d), during the fourth 1/6 frame, turn on the second, fourth, and third gate lines in turn in the second gate line group.
  • 6, 8... 718, 720 gate line rows load the second data voltage signal to the pixel cells on the gate line rows that are turned on, and there is no data stored in the linebuffer at this time.
  • the gate line row of row 719 loads the first data voltage signal to the pixel unit on the gate line row that is turned on.
  • the linebuffer stores the 2nd, 4th, 6th, 8th... 718 in the third gate line group.
  • the second data voltage signal of the 720-row gate line row turns on the 2nd, 4th, 6th, 8th...
  • the gate line row of rows 718 and 720 load the second data voltage signal to the pixel unit on the gate line row that is turned on, and there is no stored data in the linebuffer at this time; thus completing the driving of 3 gate line groups in one frame Voltage polarity reversal operation.
  • the embodiment of the present application further provides a circuit for inverting the polarity of a driving voltage of a liquid crystal panel, and the circuit adopts the above-described method for inverting the polarity of a driving voltage of a liquid crystal panel, and is used for driving an array substrate in the liquid crystal panel.
  • the array substrate includes: a base substrate and gate lines and data lines formed on the base substrate, and the gate lines and data lines define pixel units.
  • the circuit includes: a gate line driving circuit connected with the gate line and a data driving circuit connected with the data line.
  • the gate line driving circuit is used to sequentially turn on the gate line row to which the first data voltage signal is applied to the corresponding pixel unit in a certain gate line group or the gate line to which the second data voltage signal is applied to the corresponding pixel unit within the time of 1/2X frame. line line.
  • the data driving circuit is used to load the first data voltage signal to the pixel cells on the gate line row that is turned on or load the second data voltage signal to the pixel cells on the gate line row that is turned on.
  • the embodiment of the present application also provides a liquid crystal panel using the above-mentioned liquid crystal panel driving voltage polarity inversion circuit.
  • a liquid crystal panel using the above-mentioned liquid crystal panel driving voltage polarity inversion circuit.
  • the liquid crystal panel please refer to the above-mentioned liquid crystal panel driving voltage polarity inversion method and liquid crystal panel driving The limitation of the voltage polarity inversion circuit is not repeated here.

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Abstract

公开一种液晶面板驱动电压极性反转方法及电路、液晶面板，栅线分为X个连续栅线组，对于一栅线组，依次打开被施加第一数据电压信号的栅线行，向被打开栅线行上的像素单元加载第一数据电压信号后，再依次打开被施加第二数据电压信号的栅线行，向被打开栅线行上的像素单元加载与第一数据电压信号极性相反的第二数据电压信号。

Description

液晶面板驱动电压极性反转方法及电路、液晶面板 技术领域
本申请涉及显示技术领域，具体涉及一种液晶面板驱动电压极性反转方法及电路、液晶面板。
 背景技术
现有的液晶显示面板驱动架构大多采用1line架构、2line架构或者1+2line架构，其中，1line架构可以减少显示面板的闪烁问题，2line架构或者1+2line架构可改善显示面板因视角补偿算法导致的竖纹和斜线问题，在不同应用场合具有独特的优势。
 技术问题
不论是1line架构、2line架构还是1+2line架构，在显示面板的驱动过程中，扫描线上的像素单元都会依次打开，driver IC 上输出的数据电压信号每行或者每两行的极性就会反转，显示面板上数据电压信号的极性反转频繁会导致driver IC的温度上升，功耗增加。
 技术解决方案
第一方面，本申请实施例提供一种液晶面板驱动电压极性反转方法，将液晶面板栅线分为X个连续的栅线组，所述X为不小于2的整数；
对于一所述栅线组，依次打开对应像素单元被施加第一数据电压信号的栅线行，向被打开的所述栅线行上的像素单元加载第一数据电压信号后，再依次打开对应像素单元被施加第二数据电压信号的栅线行，向被打开的所述栅线行上的像素单元加载第二数据电压信号，所述第一数据电压信号和所述第二数据电压信号极性相反；
对剩余每一所述栅线组进行与上一所述栅线组同样的驱动电压极性反转操作，直至在一帧内完成对X个所述栅线组的驱动电压极性反转操作。
在本申请一种可能的实现方式中，每个所述栅线组的栅线行的个数相同，每个所述栅线组的驱动电压极性反转操作在1/X帧的时间内完成，对于每个所述栅线组，首先在1/2X帧的时间内，依次打开对应像素单元被施加第一数据电压信号的栅线行，向被打开的所述栅线行上的像素单元加载第一数据电压信号后，再在1/2X帧的时间内，依次打开对应像素单元被施加第二数据电压信号的栅线行，向被打开的所述栅线行上的像素单元加载第二数据电压信号。
在本申请一种可能的实现方式中，由上至下依次对所述X个连续的栅线组进行驱动电压极性反转操作。
在本申请一种可能的实现方式中，所述第一数据电压信号的电压极性为正且所述第二数据电压信号的电压极性为负，或者所述第一数据电压信号的电压极性为负且所述第二数据电压信号的电压极性为正。
在本申请一种可能的实现方式中，当对于一所述栅线组，向被打开的所述栅线行上的像素单元加载第一数据电压信号后，Tcon IC的行缓冲数据中只存储该所述栅线组中对应像素单元被施加第二数据电压信号的栅线行的第二数据电压信号，向被打开的所述栅线行上的像素单元加载第二数据电压信号后，所述Tcon IC的行缓冲数据中无存储数据。
在本申请一种可能的实现方式中，所述对应像素单元被施加第一数据电压信号的栅线行为对应所述栅线组中奇数行的栅线行；所述对应像素单元被施加第二数据电压信号的栅线行为对应所述栅线组中偶数行的栅线行。
在本申请一种可能的实现方式中，所述对应像素单元被施加第一数据电压信号的栅线行为对应所述栅线组中排序为1,2,5,6,9,10…1+4k,2+4k的栅线行；所述对应像素单元被施加第二数据电压信号的栅线行为对应所述栅线组中排序为3,4,7,8,11,12…3+4k,4+4k的栅线行；所述k为自然数。
在本申请一种可能的实现方式中，所述对应像素单元被施加第一数据电压信号的栅线行为对应所述栅线组中排序为1,4,5,8,9…4+4k,5+4k的栅线行；所述对应像素单元被施加第二数据电压信号的栅线行为对应所述栅线组中排序为2,3,6,7…2+4k,3+4k的栅线行；所述k为自然数。
第二方面，本申请还提供一种液晶面板驱动电压极性反转电路，所述电路采用上面所述液晶面板驱动电压极性反转方法，用于对液晶面板中的阵列基板进行驱动，所述液晶面板驱动电压极性反转方法包括：
将液晶面板栅线分为X个连续的栅线组，所述X为不小于2的整数；
对于一所述栅线组，依次打开对应像素单元被施加第一数据电压信号的栅线行，向被打开的所述栅线行上的像素单元加载第一数据电压信号后，再依次打开对应像素单元被施加第二数据电压信号的栅线行，向被打开的所述栅线行上的像素单元加载第二数据电压信号，所述第一数据电压信号和所述第二数据电压信号极性相反；
对剩余每一所述栅线组进行与上一所述栅线组同样的驱动电压极性反转操作，直至在一帧内完成对X个所述栅线组的驱动电压极性反转操作。
在本申请一种可能的实现方式中，每个所述栅线组的栅线行的个数相同，每个所述栅线组的驱动电压极性反转操作在1/X帧的时间内完成，对于每个所述栅线组，首先在1/2X帧的时间内，依次打开对应像素单元被施加第一数据电压信号的栅线行，向被打开的所述栅线行上的像素单元加载第一数据电压信号后，再在1/2X帧的时间内，依次打开对应像素单元被施加第二数据电压信号的栅线行，向被打开的所述栅线行上的像素单元加载第二数据电压信号。
在本申请一种可能的实现方式中，由上至下依次对所述X个连续的栅线组进行驱动电压极性反转操作。
在本申请一种可能的实现方式中，所述第一数据电压信号的电压极性为正且所述第二数据电压信号的电压极性为负，或者所述第一数据电压信号的电压极性为负且所述第二数据电压信号的电压极性为正。
在本申请一种可能的实现方式中，对于一所述栅线组，向被打开的所述栅线行上的像素单元加载第一数据电压信号后，Tcon IC的行缓冲数据中只存储该所述栅线组中对应栅线行的第二数据电压信号，向被打开的所述栅线行上的像素单元加载第二数据电压信号后，所述Tcon IC的行缓冲数据中无存储数据。
在本申请一种可能的实现方式中，所述对应像素单元被施加第一数据电压信号的栅线行为对应所述栅线组中奇数行的栅线行；所述对应像素单元被施加第二数据电压信号的栅线行为对应所述栅线组中偶数行的栅线行。
在本申请一种可能的实现方式中，当液晶面板的驱动架构采用1line架构时，在第（2X-1）个1/2X帧的时间内，依次打开第一个栅线组奇数行的栅线行，向被打开的栅线行上的像素单元加载第一数据电压信号，在第2X个1/2X帧的时间内，依次打开偶数行的栅线行，向被打开的栅线行上的像素单元加载第二数据电压信号。
在本申请一种可能的实现方式中，所述对应像素单元被施加第一数据电压信号的栅线行为对应所述栅线组中排序为1,2,5,6,9,10…1+4k,2+4k的栅线行；所述对应像素单元被施加第二数据电压信号的栅线行为对应所述栅线组中排序为3,4,7,8,11,12…3+4k,4+4k的栅线行；所述k为自然数。
在本申请一种可能的实现方式中，当液晶面板的驱动架构采用2line架构时，在第（2X-1）个1/2X帧的时间内，依次打开第一个栅线组中第1,2,5,6,9,10,1+4k,2+4k的栅线行，向被打开的栅线行上的像素单元加载第一数据电压信号，在第2X个1/2X帧的时间内，依次打开第一个栅线组中第3,4,7,8,11,12,3+4k,4+4k的栅线行，向被打开的栅线行上的像素单元加载第二数据电压信号；所述k为自然数。
在本申请一种可能的实现方式中，所述对应像素单元被施加第一数据电压信号的栅线行为对应所述栅线组中排序为1,4,5,8,9…4+4k,5+4k的栅线行；所述对应像素单元被施加第二数据电压信号的栅线行为对应所述栅线组中排序为2,3,6,7…2+4k,3+4k的栅线行。
在本申请一种可能的实现方式中，所述阵列基板包括：衬底基板和形成于所述衬底基板上的栅线和数据线，所述栅线和所述数据线限定像素单元；
所述电路包括：与所述栅线连接的栅线驱动电路和与所述数据线连接的数据驱动电路；
所述栅线驱动电路用于在1/2X帧的时间内，依次打开某一栅线组中对应像素单元被施加第一数据电压信号的栅线行或对应像素单元被施加第二数据电压信号的栅线行；
所述数据驱动电路用于向被打开的所述栅线行上的像素单元加载第一数据电压信号或者向被打开的所述栅线行上的像素单元加载第二数据电压信号。
第三方面，本申请还提供了一种提供一种采用上面所述液晶面板驱动电压极性反转电路的液晶面板。
 有益效果
本申请提供的液晶面板驱动电压极性反转方法，通过将液晶面板栅线分为X个连续的栅线组，对一栅线组内对应像素单元先施加第一数据电压信号后再对剩余的像素单元施加第二数据电压信号，即同一栅线组内的像素单元只需进行一次驱动电压极性反转操作，相对于现有的显示面板的驱动过程中数据电压信号每行或者每两行的极性就会反转的操作，减少了电压极性反转的频率，降低了driver IC的上升温度，达到了省电的目的，同时，将液晶面板栅线分为X个栅线组，对每个栅线组分别进行极性反转操作，Tcon IC的行缓冲数据可仅存储该栅线组中未加载的数据电压信号，达到了节省Tcon IC资源的目的。
 附图说明
图1是本申请实施例提供的液晶面板驱动电压极性反转方法的流程图；
图2是本申请实施例中将液晶面板栅线由上至下平均分为3个连续的栅线组的示意图；
图3（a）至图3（f）是采用本申请实施例提供的液晶面板驱动电压极性反转方法时显示面板第1个1/6帧至第6个1/6帧的极性示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
本申请实施例提供了一种液晶面板驱动电压极性反转方法，具体流程图如图1所示，将液晶面板栅线由上至下平均分为X个连续的栅线组，X为不小于2的整数；在一1/X帧的时间内，对于一栅线组，首先在1/2X帧的时间内，依次打开对应像素单元被施加第一数据电压信号的栅线行，向被打开的所述栅线行上的像素单元加载第一数据电压信号后，再在1/2X帧的时间内，依次打开对应像素单元被施加第二数据电压信号的栅线行，向被打开的所述栅线行上的像素单元加载第二数据电压信号，第一数据电压信号和第二数据电压信号极性相反，第一数据电压信号的电压极性为正且第二数据电压信号的电压极性为负，或者第一数据电压信号的电压极性为负且第二数据电压信号的电压极性为正；在每一1/X帧的时间内，对于剩余每一栅线组进行与上一栅线组同样的驱动电压极性反转操作，直至在一帧内完成对X个栅线组的驱动电压极性反转操作。
所述液晶面板驱动电压极性反转方法，同一栅线组内的像素单元只需进行一次驱动电压极性反转操作，相对于现有的显示面板的驱动过程中数据电压信号每行或者每两行的极性就会反转的操作，减少了电压极性反转的频率，降低了driver IC的上升温度，达到了省电的目的。
具体地，对该X个连续的栅线组进行驱动电压极性反转操作时，可以由上至下依次对每个栅线组进行驱动电压极性反转操作，具体流程如图1所示。也可以根据预设顺序依次对每个栅线组进行驱动电压极性反转操作。可选地，在本申请的另一些实施方式中，可不采用将液晶面板栅线由上至下平均分为X个连续的栅线组的方式，而将液晶面板栅线分为栅线行数不同的栅线组，分别对每个栅线组进行驱动电压极性反转操作。
当对于某一栅线组，向被打开的栅线行上的像素单元加载第一数据电压信号后，Tcon IC的行缓冲数据中只存储该栅线组中对应像素单元被施加第二数据电压信号的栅线行的第二数据电压信号，向被打开的栅线行上的像素单元加载第二数据电压信号后，Tcon IC的行缓冲数据中无存储数据。该Tcon IC的行缓冲数据的存储规则，解决了不论是1line架构、2line架构还是1+2line架构，在显示面板的驱动过程中，如要减少显示面板上数据电压信号的极性反转，则需要在Tcon IC的行缓冲数据中存储整个显示面板中未加载的数据电压信号，会消耗较多的Tcon IC资源的问题，达到了相对节省Tcon IC资源的效果。需要说明的是，本申请实施例的液晶面板驱动电压极性反转方法在一些具体的实施方式中，Tcon IC的行缓冲数据根据需要，也可以存储整个显示面板中未加载的数据电压信号。
在本申请实施例中，具体地，设液晶面板的data驱动频率为frame_rate，分辨率为M*N，若将液晶面板栅线由上至下平均分为X个连续的栅线组，X为不小于2的整数，则Tcon IC的linebuffer（行缓冲）数据有N/2X条，gate驱动频率为2X*frame_rate。
当液晶面板的驱动架构采用1line架构时，在第1个1/2X帧的时间内，依次打开第一个栅线组中第1、3、5、7……行（即奇数行）的栅线行，向被打开的栅线行上的像素单元加载第一数据电压信号，此时linebuffer中存放有第一个栅线组中第2、4、6、8……行（即偶数行）栅线行的第二数据电压信号，在第2个1/2X帧的时间内，依次打开第一个栅线组中第2、4、6、8……（即偶数行）行的栅线行，向被打开的栅线行上的像素单元加载第二数据电压信号，此时linebuffer中无存储数据。
在第3个1/2X帧的时间内，依次打开第二个栅线组中第1、3、5、7……行（即奇数行）的栅线行，向被打开的栅线行上的像素单元加载第一数据电压信号，此时linebuffer中存放有第二个栅线组中第2、4、6、8……行（即偶数行）栅线行的第二数据电压信号，在第4个1/2X帧的时间内，依次打开第二个栅线组中第2、4、6、8……行（即偶数行）的栅线行，向被打开的栅线行上的像素单元加载第二数据电压信号，此时linebuffer中无存储数据。
……依次类推，直至在第（2X-1）个1/2X帧的时间内，依次打开第X个栅线组中第1、3、5、7……行（即奇数行）的栅线行，向被打开的栅线行上的像素单元加载第一数据电压信号，此时linebuffer中存放有第X个栅线组中第2、4、6、8……行（即偶数行）栅线行的第二数据电压信号，在第2X个1/2X帧的时间内，依次打开第X个栅线组中第2、4、6、8……行（即偶数行）的栅线行，向被打开的栅线行上的像素单元加载第二数据电压信号，此时linebuffer中无存储数据；从而在一帧内完成对X个栅线组的驱动电压极性反转操作。
当液晶面板的驱动架构采用2line架构时，在第1个1/2X帧的时间内，依次打开第一个栅线组中第1,2,5,6,9,10……行（即第1+4k,2+4k行，k为自然数）的栅线行，向被打开的栅线行上的像素单元加载第一数据电压信号，此时linebuffer中存放有第一个栅线组中第3,4,7,8,11,12……行（即第3+4k,4+4k行，k为自然数）栅线行的第二数据电压信号，在第2个1/2X帧的时间内，依次打开第一个栅线组中第3,4,7,8,11,12……行（即第3+4k,4+4k行，k为自然数）的栅线行，向被打开的栅线行上的像素单元加载第二数据电压信号，此时linebuffer中无存储数据。
在第3个1/2X帧的时间内，依次打开第二个栅线组中第1,2,5,6,9,10……行（即第1+4k,2+4k行，k为自然数）的栅线行，向被打开的栅线行上的像素单元加载第一数据电压信号，此时linebuffer中存放有第二个栅线组中第3,4,7,8,11,12……行（即第3+4k,4+4k行，k为自然数）栅线行的第二数据电压信号，在第4个1/2X帧的时间内，依次打开第二个栅线组中第3,4,7,8,11,12……行（即第3+4k,4+4k行，k为自然数）的栅线行，向被打开的栅线行上的像素单元加载第二数据电压信号，此时linebuffer中无存储数据。
……依次类推，直至在第（2X-1）个1/2X帧的时间内，依次打开第X个栅线组中第1,2,5,6,9,10……行（即第1+4k,2+4k行，k为自然数）的栅线行，向被打开的栅线行上的像素单元加载第一数据电压信号，此时linebuffer中存放有第X个栅线组中第3,4,7,8,11,12……行（即第3+4k,4+4k行，k为自然数）栅线行的第二数据电压信号，在第2X个1/2X帧的时间内，依次打开第X个栅线组中第3,4,7,8,11,12……行（即第3+4k,4+4k行，k为自然数）的栅线行，向被打开的栅线行上的像素单元加载第二数据电压信号，此时linebuffer中无存储数据；从而在一帧内完成对X个栅线组的驱动电压极性反转操作。
当液晶面板的驱动架构采用1+2line架构时，在第1个1/2X帧的时间内，依次打开第一个栅线组中第1,4,5,8,9……行（即第4+4k,5+4k行，k为自然数）的栅线行，向被打开的栅线行上的像素单元加载第一数据电压信号，此时linebuffer中存放有第一个栅线组中第2,3,6,7……行（即第2+4k,3+4k行，k为自然数）栅线行的第二数据电压信号，在第2个1/2X帧的时间内，依次打开第一个栅线组中第2,3,6,7……行（即第2+4k,3+4k行，k为自然数）的栅线行，向被打开的栅线行上的像素单元加载第二数据电压信号，此时linebuffer中无存储数据。
在第3个1/2X帧的时间内，依次打开第二个栅线组中第1,4,5,8,9……行（即第4+4k,5+4k行，k为自然数）的栅线行，向被打开的栅线行上的像素单元加载第一数据电压信号，此时linebuffer中存放有第二个栅线组中第2,3,6,7……行（即第2+4k,3+4k行，k为自然数）栅线行的第二数据电压信号，在第4个1/2X帧的时间内，依次打开第二个栅线组中第2,3,6,7……行（即第2+4k,3+4k行，k为自然数）的栅线行，向被打开的栅线行上的像素单元加载第二数据电压信号，此时linebuffer中无存储数据。
……依次类推，直至在第（2X-1）个1/2X帧的时间内，依次打开第X个栅线组中第1,4,5,8,9……行（即第4+4k,5+4k行，k为自然数）的栅线行，向被打开的栅线行上的像素单元加载第一数据电压信号，此时linebuffer中存放有第2,3,6,7……行（即第2+4k,3+4k行，k为自然数）栅线行的第二数据电压信号，在第2X个1/2X帧的时间内，依次打开第X个栅线组中第2,3,6,7……行（即第2+4k,3+4k行，k为自然数）的栅线行，向被打开的栅线行上的像素单元加载第二数据电压信号，此时linebuffer中无存储数据；从而在一帧内完成对X个栅线组的驱动电压极性反转操作。
以data驱动频率为frame_rate=60HZ，分辨率为3840*2160的液晶面板为例，将液晶面板栅线由上至下平均分为3个连续的栅线组，如图2所示。则Tcon IC的linebuffer（行缓冲）数据有2160/6=360条，gate驱动频率为6*60=360HZ。该面板驱动架构采用1line架构，采用本申请实施例的液晶面板驱动电压极性反转方法，第1个1/6帧至第6个1/6帧的极性示意图如图3（a）至图3（f）所示。
如图3（a），在第1个1/6帧的时间内，依次打开第一个栅线组（即1至720行的栅线行）中第1、3、5、7……717、719行的栅线行，向被打开的栅线行上的像素单元加载第一数据电压信号，该第一数据电压信号的电压极性为正；此时linebuffer中存放有第一个栅线组中第2、4、6、8……718、720行栅线行的第二数据电压信号，共360条，该第二数据电压信号的电压极性为负，如图3（b），在第2个1/6帧的时间内，依次打开第一个栅线组中第2、4、6、8……718、720行的栅线行，向被打开的栅线行上的像素单元加载第二数据电压信号，此时linebuffer中无存储数据。
如图3（c），在第3个1/6帧的时间内，依次打开第二个栅线组（即721至1440行的栅线行）中第1、3、5、7……717、719行的栅线行，向被打开的栅线行上的像素单元加载第一数据电压信号，此时linebuffer中存放有第二个栅线组中第2、4、6、8……718、720行栅线行的第二数据电压信号，共360条，如图3（d），在第4个1/6帧的时间内，依次打开第二个栅线组中第2、4、6、8……718、720行的栅线行，向被打开的栅线行上的像素单元加载第二数据电压信号，此时linebuffer中无存储数据。
如图3（e），在第5个1/6帧的时间内，依次打开第三个栅线组（即1441至2160行的栅线行）中第1、3、5、7……717、719行的栅线行，向被打开的栅线行上的像素单元加载第一数据电压信号，此时linebuffer中存放有第三个栅线组中第2、4、6、8……718、720行栅线行的第二数据电压信号，如图3（f），在第6个1/6帧的时间内，依次打开第3个栅线组中第2、4、6、8……718、720行的栅线行，向被打开的栅线行上的像素单元加载第二数据电压信号，此时linebuffer中无存储数据；从而在一帧内完成对3个栅线组的驱动电压极性反转操作。
本申请实施例另外提供了一种液晶面板驱动电压极性反转电路，该电路采用上面描述的液晶面板驱动电压极性反转方法，用于对液晶面板中的阵列基板进行驱动。
具体地，阵列基板包括：衬底基板和形成于衬底基板上的栅线和数据线，栅线和数据线限定像素单元。
该电路包括：与栅线连接的栅线驱动电路和与数据线连接的数据驱动电路。
栅线驱动电路用于在1/2X帧的时间内，依次打开某一栅线组中对应像素单元被施加第一数据电压信号的栅线行或对应像素单元被施加第二数据电压信号的栅线行。
数据驱动电路用于向被打开的栅线行上的像素单元加载第一数据电压信号或者向被打开的栅线行上的像素单元加载第二数据电压信号。
本申请实施例还提供了一种采用上面所述液晶面板驱动电压极性反转电路的液晶面板，关于液晶面板的具体限定可参见上文中对于液晶面板驱动电压极性反转方法和液晶面板驱动电压极性反转电路的限定，在此不再赘述。
以上对本申请所提供的液晶面板驱动电压极性反转方法及电路、液晶面板进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。。

Claims (20)

  1. 一种液晶面板驱动电压极性反转方法，其中，将液晶面板栅线分为X个连续的栅线组，所述X为不小于2的整数；
    对于一所述栅线组，依次打开对应像素单元被施加第一数据电压信号的栅线行，向被打开的所述栅线行上的像素单元加载第一数据电压信号后，再依次打开对应像素单元被施加第二数据电压信号的栅线行，向被打开的所述栅线行上的像素单元加载第二数据电压信号，所述第一数据电压信号和所述第二数据电压信号极性相反；
    对剩余每一所述栅线组进行与上一所述栅线组同样的驱动电压极性反转操作，直至在一帧内完成对X个所述栅线组的驱动电压极性反转操作。
  2. 如权利要求1所述的液晶面板驱动电压极性反转方法，其中，每个所述栅线组的栅线行的个数相同，每个所述栅线组的驱动电压极性反转操作在1/X帧的时间内完成，对于每个所述栅线组，首先在1/2X帧的时间内，依次打开对应像素单元被施加第一数据电压信号的栅线行，向被打开的所述栅线行上的像素单元加载第一数据电压信号后，再在1/2X帧的时间内，依次打开对应像素单元被施加第二数据电压信号的栅线行，向被打开的所述栅线行上的像素单元加载第二数据电压信号。
  3. 如权利要求1所述的液晶面板驱动电压极性反转方法，其中，由上至下依次对所述X个连续的栅线组进行驱动电压极性反转操作。
  4. 如权利要求1所述的液晶面板驱动电压极性反转方法，其中，所述第一数据电压信号的电压极性为正且所述第二数据电压信号的电压极性为负，或者所述第一数据电压信号的电压极性为负且所述第二数据电压信号的电压极性为正。
  5. 如权利要求1所述的液晶面板驱动电压极性反转方法，其中，对于一所述栅线组，向被打开的所述栅线行上的像素单元加载第一数据电压信号后，Tcon IC的行缓冲数据中只存储该所述栅线组中对应栅线行的第二数据电压信号，向被打开的所述栅线行上的像素单元加载第二数据电压信号后，所述Tcon IC的行缓冲数据中无存储数据。
  6. 如权利要求2所述的液晶面板驱动电压极性反转方法，其中，所述对应像素单元被施加第一数据电压信号的栅线行为对应所述栅线组中奇数行的栅线行；所述对应像素单元被施加第二数据电压信号的栅线行为对应所述栅线组中偶数行的栅线行。
  7. 如权利要求2所述的液晶面板驱动电压极性反转方法，其中，所述对应像素单元被施加第一数据电压信号的栅线行为对应所述栅线组中排序为1,2,5,6,9,10…1+4k,2+4k的栅线行；所述对应像素单元被施加第二数据电压信号的栅线行为对应所述栅线组中排序为3,4,7,8,11,12…3+4k,4+4k的栅线行；所述k为自然数。
  8. 如权利要求2所述的液晶面板驱动电压极性反转方法，其中，所述对应像素单元被施加第一数据电压信号的栅线行为对应所述栅线组中排序为1,4,5,8,9…4+4k,5+4k的栅线行；所述对应像素单元被施加第二数据电压信号的栅线行为对应所述栅线组中排序为2,3,6,7…2+4k,3+4k的栅线行；所述k为自然数。
  9. 一种液晶面板驱动电压极性反转电路，其中，所述电路采用权利要求1~8任一所述液晶面板驱动电压极性反转方法，用于对液晶面板中的阵列基板进行驱动，所述液晶面板驱动电压极性反转方法包括：
    将液晶面板栅线分为X个连续的栅线组，所述X为不小于2的整数；
    对于一所述栅线组，依次打开对应像素单元被施加第一数据电压信号的栅线行，向被打开的所述栅线行上的像素单元加载第一数据电压信号后，再依次打开对应像素单元被施加第二数据电压信号的栅线行，向被打开的所述栅线行上的像素单元加载第二数据电压信号，所述第一数据电压信号和所述第二数据电压信号极性相反；
    对剩余每一所述栅线组进行与上一所述栅线组同样的驱动电压极性反转操作，直至在一帧内完成对X个所述栅线组的驱动电压极性反转操作。
  10. 如权利要求9所述的液晶面板驱动电压极性反转电路，其中，每个所述栅线组的栅线行的个数相同，每个所述栅线组的驱动电压极性反转操作在1/X帧的时间内完成，对于每个所述栅线组，首先在1/2X帧的时间内，依次打开对应像素单元被施加第一数据电压信号的栅线行，向被打开的所述栅线行上的像素单元加载第一数据电压信号后，再在1/2X帧的时间内，依次打开对应像素单元被施加第二数据电压信号的栅线行，向被打开的所述栅线行上的像素单元加载第二数据电压信号。
  11. 如权利要求9所述的液晶面板驱动电压极性反转电路，其中，由上至下依次对所述X个连续的栅线组进行驱动电压极性反转操作。
  12. 如权利要求9所述的液晶面板驱动电压极性反转电路，其中，所述第一数据电压信号的电压极性为正且所述第二数据电压信号的电压极性为负，或者所述第一数据电压信号的电压极性为负且所述第二数据电压信号的电压极性为正。
  13. 如权利要求9所述的液晶面板驱动电压极性反转电路，其中，对于一所述栅线组，向被打开的所述栅线行上的像素单元加载第一数据电压信号后，Tcon IC的行缓冲数据中只存储该所述栅线组中对应栅线行的第二数据电压信号，向被打开的所述栅线行上的像素单元加载第二数据电压信号后，所述Tcon IC的行缓冲数据中无存储数据。
  14. 如权利要求10所述的液晶面板驱动电压极性反转电路，其中，所述对应像素单元被施加第一数据电压信号的栅线行为对应所述栅线组中奇数行的栅线行；所述对应像素单元被施加第二数据电压信号的栅线行为对应所述栅线组中偶数行的栅线行。
  15. 如权利要求14所述的液晶面板驱动电压极性反转电路，其中，当液晶面板的驱动架构采用1line架构时，在第（2X-1）个1/2X帧的时间内，依次打开第一个栅线组奇数行的栅线行，向被打开的栅线行上的像素单元加载第一数据电压信号，在第2X个1/2X帧的时间内，依次打开偶数行的栅线行，向被打开的栅线行上的像素单元加载第二数据电压信号。
  16. 如权利要求10所述的液晶面板驱动电压极性反转电路，其中，所述对应像素单元被施加第一数据电压信号的栅线行为对应所述栅线组中排序为1,2,5,6,9,10…1+4k,2+4k的栅线行；所述对应像素单元被施加第二数据电压信号的栅线行为对应所述栅线组中排序为3,4,7,8,11,12…3+4k,4+4k的栅线行；所述k为自然数。
  17. 如权利要求16所述的液晶面板驱动电压极性反转电路，其中，当液晶面板的驱动架构采用2line架构时，在第（2X-1）个1/2X帧的时间内，依次打开第一个栅线组中第1,2,5,6,9,10…1+4k,2+4k的栅线行，向被打开的栅线行上的像素单元加载第一数据电压信号，在第2X个1/2X帧的时间内，依次打开第一个栅线组中第3,4,7,8,11,12…3+4k,4+4k的栅线行，向被打开的栅线行上的像素单元加载第二数据电压信号。
  18. 如权利要求10所述的液晶面板驱动电压极性反转电路，其中，所述对应像素单元被施加第一数据电压信号的栅线行为对应所述栅线组中排序为1,4,5,8,9…4+4k,5+4k的栅线行；所述对应像素单元被施加第二数据电压信号的栅线行为对应所述栅线组中排序为2,3,6,7…2+4k,3+4k的栅线行；所述k为自然数。
  19. 如权利要求9所述的液晶面板驱动电压极性反转电路，其中，所述阵列基板包括：衬底基板和形成于所述衬底基板上的栅线和数据线，所述栅线和所述数据线限定像素单元；
    所述电路包括：与所述栅线连接的栅线驱动电路和与所述数据线连接的数据驱动电路；
    所述栅线驱动电路用于在1/2X帧的时间内，依次打开某一栅线组中对应像素单元被施加第一数据电压信号的栅线行或对应像素单元被施加第二数据电压信号的栅线行；
    所述数据驱动电路用于向被打开的所述栅线行上的像素单元加载第一数据电压信号或者向被打开的所述栅线行上的像素单元加载第二数据电压信号。
  20. 一种液晶面板，其中，所述液晶面板包括权利要求9或19所述的液晶面板驱动电压极性反转电路。
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CN103456277A (zh) * 2013-08-30 2013-12-18 合肥京东方光电科技有限公司 极性反转驱动方法和极性反转驱动电路

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