WO2022110172A1 - 数据处理方法及相关设备 - Google Patents

数据处理方法及相关设备 Download PDF

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Publication number
WO2022110172A1
WO2022110172A1 PCT/CN2020/132844 CN2020132844W WO2022110172A1 WO 2022110172 A1 WO2022110172 A1 WO 2022110172A1 CN 2020132844 W CN2020132844 W CN 2020132844W WO 2022110172 A1 WO2022110172 A1 WO 2022110172A1
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Prior art keywords
data
storage
read
storage controller
instruction
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PCT/CN2020/132844
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English (en)
French (fr)
Inventor
苏杰
刘光辉
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2020/132844 priority Critical patent/WO2022110172A1/zh
Priority to CN202080106444.7A priority patent/CN116368472A/zh
Publication of WO2022110172A1 publication Critical patent/WO2022110172A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation

Definitions

  • the present application relates to the field of storage technologies, and in particular, to a data processing method and related equipment.
  • a flash-based solid state disk is a computer storage device that mainly uses flash memory (nand flash) as permanent storage.
  • flash memory nand flash
  • the appearance of SSD can be made into various styles, such as: notebook hard disk, micro hard disk, memory card or U disk.
  • the biggest advantage of this kind of SSD is that it can be moved, and the data protection is not controlled by the power supply. Due to the characteristics of NAND media, the SSD needs to write data sequentially. When the processor randomly writes data to the SSD, some data in the written data may not be used again, and these data become invalid. Data, when invalid data occurs later, it is necessary to have redundant redundant space (over provision, OP) and garbage collection (garbage collection, GC) to sort out the space.
  • OP redundant redundant space
  • garbage collection garbage collection
  • the processor needs to issue a delete command to the invalid data of the SSD in time to ensure sufficient OP and reduce the amount of GC moving.
  • the deletion command needs to be issued again, and if the deletion command is not issued in time, the GC moving amount will increase, and the write amplification of the SSD will increase, that is, it will occupy more write times. Thereby reducing the lifespan of the SSD.
  • the present application provides a data processing method and related equipment, which saves command overhead and reduces write amplification by reducing command interaction and issuing delete commands in time.
  • a first aspect of the present application provides a data processing method.
  • the method includes: a master device determines an instruction command according to first data, where the first data is data to be read from a storage array managed by a storage controller, and the first data is For data that needs to be updated or discarded in the master device, the instruction command includes the logical address of the first data, a read instruction and a delete instruction; the master device sends an instruction command to the storage controller to instruct the storage controller to determine from the storage array according to the physical address.
  • the first data is read and returned according to the read instruction, and the first data is deleted from the storage array according to the delete instruction, and the physical address is obtained by the storage controller looking up the table according to the logical address.
  • the master device when the master device needs to read the first data from the storage array, since the first data needs to be updated or discarded by the master device, the old first data in the storage array will not be available.
  • the master device can directly send the instruction command including the logical address of the first data, the read instruction and the delete instruction to the storage controller. Write enlarged.
  • the first data may be instant data, and the instant data is data that will not be used again, which can improve the feasibility of the solution.
  • a second aspect of the present application provides a data processing method, the method includes: a storage controller receives an instruction command for first data from a master device, and the first data is to be read by the master device from a storage array managed by the storage controller
  • the instruction command includes the logical address, read instruction and delete instruction of the first data;
  • the storage controller obtains the physical address of the first data according to the logical address look-up table;
  • the storage controller determines the first data from the storage array according to the physical address, The first data is read and returned to the master device according to the read command, and the first data is deleted from the storage array according to the delete command.
  • the instruction command includes the logical address of the first data, the read instruction and the deletion instruction
  • the storage controller can directly read the data on the physical address obtained according to the logical address look-up table according to the instruction command and return it to the host. device, and delete the first data on the physical address, only one command interaction is required, which reduces the command overhead, and deletes the data in time, which can reduce write amplification.
  • the method before deleting the first data from the storage array in the above steps and according to the deletion instruction, includes: the storage controller determines that when executing the deletion of the second data read operation or write operation, then record the deletion operation of the first data in the log; the above steps and delete the first data from the storage array according to the deletion instruction, including: the storage controller performs the read operation on the second data or After the write operation, according to the record in the log, the delete operation of the first data is performed.
  • delete operations can avoid increasing the read and write latency of data.
  • a third aspect of the present application provides a data processing method, the method includes: a host device sends a write command of first data to a storage controller, the write command includes first data, a write command and a first logical address, the first data For the data that needs to be updated or discarded in the master device, the first physical address indicated by the first logical address is in the preset storage area in the storage array managed by the storage controller, and the preset storage area is the pre-configured data read. Then execute the deleted area.
  • the master device stores the first data in a preset storage area in the storage array managed by the storage controller based on an application scenario that needs to update or discard the first data, and the preset storage area Pre-configured for the master device, the data in the preset storage area needs to be deleted after being read, and the master device does not need to send a delete command to the storage controller, reducing command interaction.
  • the method further includes: the master device sends an instruction command to the storage controller for second data, where the second data is to be read by the processing device from the storage array managed by the storage management device
  • the data fetched, the instruction command includes the second logical address of the first data and a read instruction, to instruct the storage controller to determine the second data from the storage array according to the second physical address, read and return the second data according to the read instruction, and
  • the first data is deleted, and the second physical address is obtained by the storage controller looking up the table according to the second logical address.
  • the master device only needs to send a normal read command (instruction command) to the storage controller, when the second physical address in the storage array indicated by the second logical address in the read command is in the When the storage area is set, the master device does not need to send the delete command again, which reduces command interaction and command overhead.
  • a fourth aspect of the present application provides a data processing method, the method includes: a storage controller receives a write command from a master device, the write command includes first data, a write command and a first logical address, and the first data is to be stored in The data that is updated or discarded by the master device; the storage controller obtains the first physical address according to the first logical address look-up table, the first physical address is located in the preset storage area in the storage array managed by the storage controller, and the preset storage area is The deleted area is executed after reading the preconfigured data; the storage controller stores the first data in the storage location indicated by the first physical address according to the write instruction.
  • a preset storage area is preconfigured in the storage array managed by the storage controller, and the data in the preset storage area needs to be deleted after being read.
  • the master device sets the first physical address indicated by the first logical address in the write command in the preset storage area, and the storage controller can directly store the first data. stored in the storage location indicated by the first physical address.
  • the method further includes: the storage controller receives an instruction command for the second data from the master device, where the instruction command includes the second logical address of the first data and a read instruction; storing The controller obtains the second physical address of the first data according to the second logical address look-up table; if the second physical address is in the preset storage area, the storage controller determines the delete operation and the read operation corresponding to the read instruction; Two physical addresses determine the second data from the storage array, read and return the second data to the master device according to the read operation, and delete the second data according to the delete operation.
  • the instruction command sent by the master device only needs to indicate the second logical address of the second data and the read instruction.
  • the storage area it means that the second data needs to be updated or discarded in the master device, that is, the second data stored in the flash memory array is useless, and the flash device controller determines that the second data needs to be read and discarded.
  • the delete operation is performed without waiting for the delete command issued by the master device, which can reduce write amplification.
  • the method before deleting the first data in the above steps and according to the deleting operation, the method further includes: Record the deletion operation of the second data in the above steps and delete the second data according to the deletion operation, including: after the storage controller has performed the read operation or write operation to the third data, according to the record in the log, execute the operation of the third data. 2. Data deletion operation.
  • a fifth aspect of the present application provides a host device, and the storage management apparatus has the function of implementing the method of the first aspect, any possible implementation manner of the first aspect, the third aspect, or any possible implementation manner of the third aspect.
  • This function can be implemented by hardware or by executing corresponding software by hardware.
  • the hardware or software includes one or more modules corresponding to the above functions, such as a receiving unit and a processing unit.
  • a sixth aspect of the present application provides a storage controller, and the processing device has the function of implementing the method of the second aspect, any possible implementation manner of the second aspect, the fourth aspect, or any possible implementation manner of the fourth aspect.
  • This function can be implemented by hardware or by executing corresponding software by hardware.
  • the hardware or software includes one or more modules corresponding to the above functions, such as a sending unit and a processing unit.
  • a seventh aspect of the present application provides a computer device, the computer device comprising at least one processor, a storage system, an input/output (I/O) interface, and a computer stored in the storage system and executable on the processor Computer-executed instructions, when the computer-executed instructions are executed by the processor, the processor executes the method of the first aspect, any possible implementation manner of the first aspect, the third aspect, or any possible implementation manner of the third aspect.
  • processor comprising at least one processor, a storage system, an input/output (I/O) interface, and a computer stored in the storage system and executable on the processor
  • Computer-executed instructions when the computer-executed instructions are executed by the processor, the processor executes the method of the first aspect, any possible implementation manner of the first aspect, the third aspect, or any possible implementation manner of the third aspect.
  • An eighth aspect of the present application provides a computer device comprising at least one processor, a memory, an input/output (I/O) interface, and a computer executable stored in the memory and executable on the processor Instructions, when the computer-executed instructions are executed by the processor, the processor executes the method of the second aspect, any possible implementation manner of the second aspect, the fourth aspect, or any possible implementation manner of the fourth aspect.
  • a ninth aspect of the present application provides a computer-readable storage medium storing one or more computer-executable instructions.
  • the processor executes the first to fourth aspects or the first to fourth aspects above.
  • a tenth aspect of the present application provides a computer program product that stores one or more computer-executable instructions.
  • the processor executes the first to fourth aspects or the first to fourth aspects above.
  • FIG. 1 is a schematic diagram of a system framework for data reading and writing provided by an embodiment of the present application
  • FIG. 2 is a schematic diagram of a command interaction mode provided by an embodiment of the present application.
  • FIG. 3 is a flowchart of an embodiment of a data processing method provided by an embodiment of the present application.
  • FIG. 4 is a flowchart of another embodiment of the data processing method provided by the embodiment of the present application.
  • FIG. 5 is a schematic diagram of an embodiment of a master device provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of an embodiment of a storage controller provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of another embodiment of a master device provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of another embodiment of a storage controller provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of an embodiment of a computer device provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of another embodiment of a computer device provided by an embodiment of the present application.
  • Embodiments of the present application provide a data processing method and related equipment, which are used to save command overhead and reduce write amplification.
  • the embodiment of the present application can be applied to the system framework of data reading and writing as shown in FIG. 1 .
  • the system framework includes a main device 11 and a storage controller 12 , and the main device 11 can be a processor.
  • a host is used as the example.
  • the storage controller 12 may be a control device in a solid-state storage device using NAND media, and an exemplary embodiment of the present application takes a flash memory device controller (storage device controller) of a solid state disk (solid state disk, SSD) as an example.
  • the master device 11 determines the content to be read, it can send the read command to the storage controller 12.
  • the storage controller 12 After receiving the read command, the storage controller 12 can obtain the physical address according to the logical address lookup table carried by the read command to read.
  • the host device 11 can also send the new file to be added and the write command to the storage controller 12, and the storage controller 12 can perform the write operation of the new file according to the write command.
  • the host device 11 includes a real-time operating system (kernel) 111 , a driver (driver) 112 and a first interface (interface) 113 .
  • the storage controller 12 includes a second interface 121, a processor (central processing unit, CPU) 122, a static random access memory (static random access memory, SRAM) 123 and a nand controller (controller) 124, the system framework also includes flash memory A nand flash array 13, and a storage device 14 including a storage controller 12 and a flash array 13.
  • the real-time operating system 111 is used for address mapping of the read command or address allocation of the write command issued by the storage controller 12 .
  • the driver 112 is a program for data interaction with the storage controller 12 .
  • This procedure includes some configuration data on how to communicate with the memory controller 12, how to format the data, how to initialize, how to abort, etc.
  • the first interface 113 is used to transmit information exchange between the host device 11 and the storage controller 12 .
  • the second interface 121 is used to connect to the first interface 113 and undertake the function of data transmission.
  • Data is transmitted to and from the host through means such as universal flash storage (UFS), embedded mutlti-media card (EMMC), bus and interface standards (peripheral component interconnect express, PCIE).
  • UFS universal flash storage
  • EMMC embedded mutlti-media card
  • PCIE peripheral component interconnect express
  • the processor 122 is used to process data from the second interface 121 .
  • the SRAM 123 is used to speed up the transfer of data within the processor 122 .
  • the nand controller 124 is used to control and manage the nand.
  • the flash memory array 13 is a physical carrier for final storage of data, and usually includes a plurality of nand flash dies 131 .
  • the storage device 14 is used to carry the storage controller 12 and the flash memory array 13 .
  • the flash memory array space may be occupied and the write amplification of the device will increase.
  • the storage controller sends feedback information (response) to the master device, and the master device sends the storage controller to the storage controller.
  • the server sends the delete command (erase command), and accepts the feedback information (response) sent by the storage controller.
  • the master device needs to complete the delete operation after completing the reading in 2 steps.
  • the first step is to send a read command.
  • the logical block address (LBA) is 0 and the length is 0x100.
  • the second step informs the device that the LBA is 0 and the address with length 0x100 needs to be deleted, that is, it occupies an additional command channel, which is to reduce the use of the command channel, the embodiment of the present application provides a corresponding data processing method.
  • the method includes that the storage controller receives an operation command for the first data from the master device, and the first data is to be managed by the master device from the storage controller. the data read by the storage array; the storage controller determines to perform a read operation and a delete operation on the first data according to the operation command; the storage controller reads the first data from the storage array according to the read operation and sends it to the master device, and then performs A delete operation is performed on the first data stored in the storage array.
  • the above data processing method can also be applied to an application scenario in which the cache and secure interaction data are read and cleared at one time.
  • the memory controller of this embodiment can be any non-volatile memory (NVM) based on NAND flash, which does not need to periodically refresh the memory content, including all forms of read-only memory (read only memory).
  • ROM read only memory
  • ROM read only memory
  • PROM programmable read only memory
  • EPROM erasable programmable read only memory image
  • EEPROM electrically erasable read only memory
  • flash memory also including battery-powered random access memory (random access memory, RAM).
  • Data is usually stored and read in pages on the storage controller. Data is erased in blocks.
  • a block also called a physical block
  • a page (called a physical page) on a storage medium has a fixed size, eg 17664 bytes. Physical pages can also have other sizes.
  • the flash translation layer can be used to maintain the mapping information from logical addresses to physical addresses.
  • the logical address constitutes the storage space of the solid-state storage device perceived by upper-layer software such as the operating system.
  • the physical address is the address of the physical storage unit used to access the solid state storage device.
  • the address mapping can also be implemented using an intermediate address form. For example, a logical address is mapped to an intermediate address, and the intermediate address is further mapped to a physical address.
  • a table structure that stores mapping information from logical addresses to physical addresses is called an FTL table.
  • FTL tables are important metadata in solid-state storage devices.
  • the data item of the FTL table records the address mapping relationship in the unit of data unit in the storage controller.
  • the logical page in the FTL table corresponds to 4KB of storage space
  • the storage space of the physical page is also 4KB of storage space (including additional out-of-band storage space).
  • the FTL table provides a record for each 4KB data unit to record the mapping of its logical address to physical address.
  • the size of the storage space corresponding to the data unit is different from that of the physical page.
  • a physical page can accommodate multiple data units
  • the data unit corresponds to a 4KB storage space
  • the storage space of a physical page can accommodate multiple Data units (eg 4).
  • the FTL table includes a plurality of FTL table entries (or entries).
  • the correspondence between a logical page address and a physical page is recorded in each FTL table entry.
  • each FTL table entry records the correspondence between a plurality of consecutive logical page addresses and a plurality of consecutive physical pages.
  • each FTL table entry records the correspondence between the logical block address and the physical block address.
  • the FTL table records the mapping relationship between logical block addresses and physical block addresses, and/or the mapping relationship between logical page addresses and physical page addresses.
  • the master device may directly instruct the storage controller that the first data needs to perform a delete-on-read operation, or may indirectly instruct the storage controller that the data needs to be deleted after being read.
  • the master device directly instructs the storage controller that the data needs to be deleted after reading.
  • an embodiment of the data processing method in the embodiment of the present application includes:
  • the host determines an instruction command according to the first data.
  • the host may determine an instruction command according to an application scenario of the first data.
  • the application scenario may be that the first data needs to be updated or discarded on the host.
  • the host can determine that the first data in the storage array is data that is deleted after reading, and can determine that the first data corresponds to an instruction command that includes a logical address, a read instruction and a deletion instruction at the same time, and the instruction command only needs to occupy One command interaction.
  • the first data is data to be read from the nand array in the solid state disk.
  • the first data may be instant data or temporary buffered data.
  • SWAP mobile phone swap area
  • this function is estimated to bring a certain amount of writing every day, and this part of the writing amount will also be There is additional write amplification; after the SWAP data is swapped into the memory, this part of the data is instant data, and a delete command needs to be issued as soon as possible to delete this part of the data, otherwise it will cause invalid data movement on the device side, resulting in SWAP Use the scene's write magnification to get bigger.
  • Write amplification is the garbage collection (garbage collection, GC) garbage collection technology to move valid data to another block (block), the data that has already been written once, plus this relocation, one more time Write, constitute write amplification.
  • the host sends an instruction command to the flash memory device controller.
  • the host After the host determines the instruction command of the first data, it can transmit the instruction command through the interface between the host and the solid-state hard disk, and the instruction command can make the flash memory device controller obtain the logical address, read instruction and delete instruction in the instruction command .
  • the flash memory device controller determines the first data in the storage array according to the logical address.
  • the flash memory device controller can obtain the logical address in the instruction command, and then query the FTL table according to the logical address to obtain the physical address corresponding to the first data, so as to determine the first data.
  • the flash memory device controller sends a read command for reading the first data to the flash memory array according to the read command.
  • the flash memory device controller may read the first data from the physical address corresponding to the flash memory array in the solid state disk as a response to the read command.
  • the flash memory array sends the first data to the flash memory device controller.
  • the flash memory array After the flash memory array receives the read command about reading the first data sent by the flash memory device controller, the flash memory array can read the first data based on the physical address information carried in the read command, and then send it to the flash memory device controller. .
  • the flash memory device controller After the flash memory device controller reads the first data in the flash memory array based on the read operation of the read command, the first data may be sent to the host through the interface.
  • the flash memory device controller determines that when a read operation or a write operation on the second data is performed, the delete operation on the first data is recorded in a log.
  • the flash memory device controller After the flash memory device controller has performed the above read operation, it can judge whether the read command or write command about the second data sent by the host is still received, that is, it can judge whether the second data in the flash memory array still needs to be executed at present. read operation. If there is currently no read operation or write operation on the second data, the flash memory device controller may directly perform the delete operation on the first data of the nand array based on the physical address indicated by the delete operation; In order to avoid affecting the execution of the read operation or write operation of the second data, that is, to avoid affecting the processing delay, the flash memory device controller can record the delete operation in the log (log) for delay. deal with.
  • the second data is different data from the first data, and the second data may be one or more.
  • the flash memory device controller After performing the read operation or the write operation on the second data, the flash memory device controller performs the delete operation on the first data according to the record in the log.
  • the flash memory device controller after the flash memory device controller has performed the read operation or write operation on the second data, that is, it does not currently receive any data read or write command sent by the host, it can query the records in the log to perform the first read or write operation on the first data. Data deletion operations.
  • the flash memory device controller may perform the deletion operation on the nand array in sequence based on the time recorded in the log.
  • the instruction command sent by the host includes a read instruction and a deletion instruction at the same time, and the flash memory device controller performs a read operation on the first data and then performs a delete operation, and the host does not need to send the delete command again, which solves the problem of existing
  • the EMMC host needs to issue a command with high overhead, and the deletion command is issued in a more timely manner, which reduces the write amplification of the solid-state hard disk and improves the service life of the solid-state hard disk.
  • the master device indirectly instructs the storage controller that the data needs to be deleted after reading.
  • the master device preconfigures a preset storage area in the storage array, and only needs to send a read command.
  • another embodiment of the data processing method in the embodiment of the present application includes:
  • the host sends a write command of the first data to the storage controller.
  • the host stores the first data in a preset storage area in the flash memory array managed by the flash device controller, and the preset storage area is The host is pre-configured, and the data in the preset storage area needs to be deleted after being read.
  • the host may send a write command to the flash memory device controller, where the write command includes first data, a first logical address, and a write instruction, where the first logical address may indicate a first physical address in the preset storage area.
  • the flash device controller can receive the write command and take action accordingly.
  • the flash memory device controller obtains the first physical address according to the first logical address lookup table.
  • the flash memory device controller may query the FTL table according to the first logical address in the instruction command to obtain the first physical address corresponding to the first data.
  • the flash memory device controller stores the first data in the storage location indicated by the first physical address according to the write instruction.
  • the flash memory device controller may directly store the first data in the preset storage area.
  • the host sends an instruction command for the second data to the flash memory device controller.
  • the host When the host needs to read the second data in the flash memory array, it can send an instruction command including only the logical address and the read command to the flash memory device controller.
  • the flash memory device controller obtains the second physical address according to the second logical address look-up table, and determines the second data.
  • the flash memory device controller may query the FTL table according to the second logical address to obtain the physical address of the second data in the flash memory array, that is, determine the storage location of the second data.
  • the flash memory device controller determines the delete operation and the read operation.
  • the flash memory device controls The controller determines that a read operation needs to be performed on the second data and a delete operation is performed.
  • the flash memory device controller sends a read command for reading the second data to the flash memory array according to the read operation.
  • the flash memory array sends the second data to the flash memory device controller.
  • the flash memory device controller determines that a read operation or a write operation on the third data is being performed, and records the delete operation on the second data in a log.
  • the flash memory device controller After performing the read operation or the write operation on the third data, the flash memory device controller performs the delete operation on the second data according to the record in the log.
  • the second data is read and the second data in the flash memory array is deleted in steps 407-411 of this embodiment, and the first data is read and the flash memory array is deleted in steps 304-308 in the data processing method embodiment described with reference to FIG. 3
  • the relevant description of the first data in , and details are not repeated here.
  • the instruction command sent by the host includes a read instruction and a deletion instruction at the same time, and the flash memory device controller performs a read operation on the first data and then performs a delete operation, and the host does not need to send the delete command again, which solves the problem of existing
  • the EMMC host needs to issue a command with high overhead, and the deletion command is issued in a more timely manner, which reduces the write amplification of the solid-state hard disk and improves the service life of the solid-state hard disk.
  • FIG. 5 is a schematic diagram of an embodiment of a master device 50 in an embodiment of the present application.
  • an embodiment of the present application provides a master device, where the master device includes:
  • the determining unit 501 is configured to determine an instruction command according to first data, the first data is the data to be read from the storage array managed by the storage controller, and the first data is the data that needs to be updated or discarded in the master device, indicating The command includes a logical address of the first data, a read instruction and a delete instruction;
  • the sending unit 502 is configured to send an instruction command to the storage controller to instruct the storage controller to determine the first data from the storage array according to the physical address, read and return the first data according to the read instruction, and delete the first data from the storage array according to the delete instruction.
  • the first data is deleted, and the physical address is obtained by the storage controller according to the logical address look-up table.
  • the first data is instant data
  • the instant data is data that will not be used again.
  • the master device described above can be understood by referring to the corresponding content in the foregoing method embodiment section, and details are not repeated here.
  • FIG. 6 is a schematic diagram of an embodiment of the storage controller 60 in the embodiment of the present application.
  • an embodiment of the present application provides a storage controller, where the storage controller includes:
  • the receiving unit 601 is used to receive an instruction command for the first data from the master device, the first data is the data to be read by the master device from the storage array managed by the storage controller, and the instruction command includes the logical address of the first data, read command and delete command;
  • a query unit 602 configured to obtain the physical address of the first data according to the logical address look-up table
  • the processing unit 603 is configured to determine the first data from the storage array according to the physical address, read and return the first data to the master device according to the read instruction, and delete the first data from the storage array according to the deletion instruction.
  • the storage controller 60 further includes a recording unit 604, and the recording unit 604 is configured to determine that a read operation or a write operation on the second data is being performed, and then record the delete operation on the first data in the log; the processing unit 603 specifically It is used for: after the read operation or the write operation on the second data is performed, according to the record in the log, the delete operation on the first data is performed.
  • the storage controller described above can be understood by referring to the corresponding content in the foregoing method embodiment section, and details are not described here.
  • FIG. 7 is a schematic diagram of an embodiment of a master device 70 in an embodiment of the present application.
  • an embodiment of the present application provides a master device, where the master device includes:
  • the sending unit 701 is used for the master device to send a write command of the first data to the storage controller, the write command includes the first data, the write command and the first logical address, and the first data needs to be updated or discarded in the master device
  • the first physical address indicated by the first logical address is in a preset storage area in the storage array managed by the storage controller, and the preset storage area is an area where the preconfigured data is read and then deleted.
  • the sending unit 701 is further configured to send an instruction command to the storage controller for the second data
  • the second data is the data to be read by the processing device from the storage array managed by the storage management device
  • the instruction command includes the second data.
  • the second logical address and the read instruction are used to instruct the storage controller to determine the first data from the storage array according to the second physical address, read and return the first data according to the read instruction, and delete the first data.
  • the second physical address is The storage controller is obtained by looking up the table according to the second logical address.
  • the master device described above can be understood by referring to the corresponding content in the foregoing method embodiment section, and details are not repeated here.
  • FIG. 8 is a schematic diagram of an embodiment of a storage controller 80 in an embodiment of the present application.
  • an embodiment of the present application provides a storage controller, where the storage controller includes:
  • a receiving unit 801 configured to receive a write command from a master device, the write command includes first data, a write instruction and a first logical address, and the first data needs to be updated or discarded in the master device data;
  • a query unit 802 configured to obtain a first physical address according to the first logical address look-up table, where the first physical address is located in a preset storage area in a storage array managed by the storage controller, the preset The storage area is the area where the pre-configured data is read and then deleted;
  • a storage unit 803 configured to store the first data to a storage location indicated by the first physical address according to the write instruction.
  • the receiving unit 801 is further configured to receive an instruction command for the second data from the master device, the second data is the data to be read by the processing device from the storage array managed by the storage management device, and the instruction command includes the second data. the second logical address and the read instruction; the query unit 802 is further configured to obtain the second physical address of the second data according to the second logical address look-up table; the storage controller 80 further includes a processing unit 804 for when the second physical address is in the When the storage area is preset, the storage controller determines the delete operation and the read operation corresponding to the read instruction; the storage controller determines the second data from the storage array according to the second physical address, reads and returns the second data to the master device according to the read operation , and delete the second data according to the delete operation.
  • FIG. 9 is a schematic diagram of a possible logical structure of a computer device 90 according to an embodiment of the present application.
  • Computer device 90 includes a processor 901, a communication interface 902, a storage system 903, and a bus 904.
  • the processor 901 , the communication interface 902 and the storage system 903 are connected to each other through a bus 904 .
  • the processor 901 is configured to control and manage the actions of the computer device 90.
  • the processor 901 is configured to execute the steps performed by the storage controller in the method embodiments of FIG. 3 to FIG. 4 .
  • Communication interface 902 is used to support computer device 90 to communicate.
  • the storage system 903 is used to store program codes and data of the computer device 90 .
  • the processor 901 may be a central processing unit, a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array, or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It may implement or execute the various exemplary logical blocks, modules and circuits described in connection with this disclosure.
  • the processor 901 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a digital signal processor and a microprocessor, and the like.
  • the bus 904 may be a peripheral component interconnect standard (Peripheral Component Interconnect, PCI) bus or an Extended Industry Standard Architecture (Extended Industry Standard Architecture, EISA) bus or the like.
  • PCI peripheral component interconnect standard
  • EISA Extended Industry Standard Architecture
  • the sending unit 502 in the main device 50 is equivalent to the communication interface 902 in the computer device 90
  • the determining unit 501 in the storage controller 50 may be equivalent to the processor 901 .
  • the sending unit 701 in the host device 70 is equivalent to the communication interface 902 in the computer device 90 .
  • the computer device 90 in this embodiment may correspond to the master device in the above method embodiments, and the processor 901 and the communication interface 902 in the computer device 90 may implement the functions and/or functions of the master device in the above method embodiments. For the sake of brevity, various steps to be implemented are not repeated here.
  • FIG. 10 is a schematic diagram of a possible logical structure of the computer device 100 provided by the embodiment of the present application.
  • the computer device 100 includes a processor 1001 , a communication interface 1002 , a storage system 1003 and a bus 1004 .
  • the processor 1001 , the communication interface 1002 , and the storage system 1003 are connected to each other through a bus 1004 .
  • the processor 1001 is configured to control and manage the actions of the computer device 100.
  • the processor 1001 is configured to execute the steps performed by the master device in the method embodiments of FIG. 3 to FIG. 4 .
  • Communication interface 1002 is used to support computer device 100 to communicate.
  • the storage system 1003 is used to store program codes and data of the computer device 100 .
  • the processor 1001 may be a central processing unit, a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array, or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It may implement or execute the various exemplary logical blocks, modules and circuits described in connection with this disclosure.
  • the processor 1001 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a digital signal processor and a microprocessor, and the like.
  • the bus 1004 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (Extended Industry Standard Architecture, EISA) bus or the like.
  • PCI Peripheral Component Interconnect
  • EISA Extended Industry Standard Architecture
  • the receiving unit 601 in the storage controller 60 is equivalent to the communication interface 1002 in the computer device 100 , and the query unit 602 , the processing unit 603 and the recording unit 604 in the storage controller 60 may be equivalent to the processor 1001 .
  • the receiving unit 801 in the storage controller 80 is equivalent to the communication interface 1002 in the computer device 100 , and the query unit 802 , the storage unit 803 and the processing unit 804 in the storage controller 80 may be equivalent to the processor 1001 .
  • the computer device 100 in this embodiment may correspond to the storage controller in the above method embodiments, and the processor 1001 and the communication interface 1002 in the computer device 100 may implement the functions of the storage controller in the above method embodiments And/or the various steps implemented, for the sake of brevity, are not repeated here.
  • a computer-readable storage medium is also provided, where computer-executable instructions are stored in the computer-readable storage medium.
  • the processor of the device executes the computer-executable instructions
  • the device executes the above-mentioned FIG. 3 to The steps of the data processing method executed by the storage controller are shown in FIG. 4 .
  • a computer-readable storage medium is also provided, where computer-executable instructions are stored in the computer-readable storage medium.
  • the processor of the device executes the computer-executable instructions
  • the device executes the above-mentioned FIG. 3 to The steps of the data processing method performed by the master device in FIG. 4 .
  • a computer program product includes computer-executable instructions, and the computer-executable instructions are stored in a computer-readable storage medium; when a processor of a device executes the computer-executable instructions , the device executes the steps of the data processing method executed by the storage controller in the above-mentioned FIG. 3 to FIG. 4 .
  • a computer program product includes computer-executable instructions, and the computer-executable instructions are stored in a computer-readable storage medium; when a processor of a device executes the computer-executable instructions , the device executes the steps of the data processing method executed by the master device in the above-mentioned FIG. 3 to FIG. 4 .
  • the disclosed system, apparatus and method may be implemented in other manners.
  • the apparatus embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units may be implemented in the form of hardware, or may be implemented in the form of software functional units.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as an independent product, may be stored in a computer-readable storage medium.
  • the technical solutions of the present application can be embodied in the form of software products in essence, or the parts that contribute to the prior art, or all or part of the technical solutions, and the computer software products are stored in a storage medium , including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, read-only memory), random access memory (RAM, random access memory), magnetic disk or optical disk and other media that can store program codes .

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Abstract

本申请公开了一种数据处理方法及相关设备，该方法应用于计算机系统，当主设备要对第一数据进行更新或舍弃的时候，可以向存储控制器发送包括读指令和删除指令的指示命令，以使得存储控制器从所管理的存储阵列读取并返回第一数据，并删除该第一数据，该指示命令只进行一次交互，即可同时实现读指令和删除指令，减少了交互次数，并且存储控制器删除第一数据不需要等待主设备再次下发删除命令，可以减少写放大。

Description

数据处理方法及相关设备 技术领域
本申请涉及存储技术领域，尤其涉及一种数据处理方法及相关设备。
背景技术
基于闪存的固态硬盘(solid state disk，SSD)是一种主要以闪存(nand flash)作为永久性存储器的计算机存储设备。SSD的外观可以被制作成多种模样，例如：笔记本硬盘、微硬盘、存储卡或U盘等样式。这种SSD最大的优点就是可以移动，而且数据保护不受电源控制，能适应于各种环境，适合于个人用户使用，一般它擦写次数普遍为3000次左右。由于与非门(nand)介质的特性该SSD需要顺序写入数据，当处理器在SSD随机写入数据时，已写入的数据中有些数据可能不会再被使用，这些数据就成了无效数据,后期在出现无效数据时就需要有多余的冗余空间(over provision，OP)和垃圾回收(garbage collection，GC)的方式来整理空间。
现有技术中处理器需要及时对SSD的无效数据下发删除命令，以保证足够的OP和减少GC的搬移量。
但是现有技术中删除命令的下发需要再次下发命令，并且如果删除命令下发不及时，会导致GC搬移量增大，使SSD的写放大增大，即占用更多的写入次数，从而减少了SSD的使用寿命。
发明内容
本申请提供一种数据处理方法及相关设备，通过减少命令交互和及时下发删除命令，节省了命令开销和减少写放大。
本申请第一方面提供一种数据处理方法，该方法包括：主设备根据第一数据确定指示命令，第一数据为待从存储控制器所管理的存储阵列读取的数据，且第一数据为需要在主设备进行更新或舍弃的数据，指示命令包括第一数据的逻辑地址、读指令和删除指令；主设备向存储控制器发送指示命令，以指示存储控制器根据物理地址从存储阵列中确定第一数据，根据读指令读取并返回第一数据，并根据删除指令从存储阵列中删除第一数据，物理地址为存储控制器根据逻辑地址查表获得的。
上述第一方面中，主设备在需要从存储阵列中读取第一数据时，由于该第一数据为主设备需要对其进行更新或者舍弃的数据，存储阵列中的旧的第一数据就没有用处了，主设备可以直接向存储控制器发送包括第一数据的逻辑地址、读指令和删除指令的指示命令，该指示命令只占用一次命令交互，减少了命令开销，并且及时删除数据，可以减少写放大。
在第一方面的一种可能的实现方式中，第一数据可以为即时性数据，该即时性数据为不会被再次使用的数据，可以提高方案的可行性。
本申请第二方面提供一种数据处理方法，该方法包括：存储控制器接收来自主设备的对第一数据的指示命令，第一数据为主设备待从存储控制器所管理的存储阵列读取的数据， 指示命令包括第一数据的逻辑地址、读指令和删除指令；存储控制器根据逻辑地址查表获得第一数据的物理地址；存储控制器根据物理地址从存储阵列中确定第一数据，根据读指令读取并向主设备返回第一数据，并根据删除指令从存储阵列中删除第一数据。
上述第二方面中，指示命令包括第一数据的逻辑地址、读指令和删除指令，存储控制器可以直接根据该指示命令，读取根据逻辑地址查表获得的物理地址上的数据并返回给主设备，并对该物理地址上的第一数据进行删除，只需进行一次命令交互，减少了命令开销，并且及时删除数据，可以减少写放大。
在第二方面的一种可能的实施方式中，上述步骤并根据所述删除指令从所述存储阵列中删除所述第一数据之前，该方法包括：存储控制器确定在执行对第二数据的读操作或写操作，则在日志中记录对第一数据的删除操作；上述步骤并根据删除指令从存储阵列中删除第一数据，包括：存储控制器在执行完对第二数据的读操作或写操作后，根据日志中的记录，执行对第一数据的删除操作。
该种可能的实现方式中，在根据删除指令执行对第一数据的删除操作之前，还需要确认是否有除第一数据之外的其他数据(第二数据)在执行读操作或写操作，如果存在第二数据在执行读操作，可以将第一数据的删除操作记录在日志中，当第二数据的读操作或写操作执行完毕后，即可按照日志中记录的删除操作的记录顺序依次执行删除操作，可以避免增加数据的读写时延。
本申请第三方面提供一种数据处理方法，该方法包括：主设备向存储控制器发送第一数据的写入命令，写入命令包括第一数据、写指令和第一逻辑地址，第一数据为需要在主设备进行更新或舍弃的数据，第一逻辑地址所指示的第一物理地址处于存储控制器所管理的存储阵列中的预设存储区域，预设存储区域为预配置的数据读取后再执行删除的区域。
上述第三方面中，主设备基于需要对第一数据进行更新或舍弃的应用场景，将该第一数据存储到存储控制器所管理的存储阵列中的预设存储区域中，该预设存储区域为主设备预先配置的，该预设存储区域中的数据在进行读取后都需要执行删除操作，主设备可以不用向存储控制器发送删除命令，减少命令交互。
在第三方面的一种可能的实施方式中，该方法还包括：主设备向存储控制器发送对第二数据的指示命令，第二数据为处理装置待从存储管理装置所管理的存储阵列读取的数据，指示命令包括第一数据的第二逻辑地址和读指令，以指示存储控制器根据第二物理地址从存储阵列中确定第二数据，根据读指令读取并返回第二数据，并删除第一数据，第二物理地址为存储控制器根据第二逻辑地址查表获得的。
该种可能的实施方式中，主设备只需要向存储控制器发送正常的读取命令(指示命令)，当该读取命令中的第二逻辑地址指示的存储阵列中的第二物理地址处于预设存储区域时，主设备无需再次发送删除命令，减少了命令交互，减少命令开销。
本申请第四方面提供一种数据处理方法，该方法包括：存储控制器接收来自主设备的写入命令，写入命令包括第一数据、写指令和第一逻辑地址，第一数据为需要在主设备进行更新或舍弃的数据；存储控制器根据第一逻辑地址查表获得第一物理地址，第一物理地址位于存储控制器所管理的存储阵列中预设存储区域内，预设存储区域为预配置的数据读 取后再执行删除的区域；存储控制器根据写指令将第一数据存储到第一物理地址所指示的存储位置。
上述第四方面中，存储控制器所管理的存储阵列中预配置有一个预设存储区域，该预设存储区域中的数据需要在读取后则执行删除操作。主设备基于需要对第一数据进行更新或舍弃的应用场景，将写入命令中的第一逻辑地址指示的第一物理地址设置在预设存储区域内，存储控制器可以将该第一数据直接存储到该第一物理地址指示的存储位置上。
在第四方面的一种可能的实施方式中，该方法还包括：存储控制器接收来自主设备的对第二数据的指示命令，指示命令包括第一数据的第二逻辑地址和读指令；存储控制器根据第二逻辑地址查表获得第一数据的第二物理地址；如果第二物理地址处于预设存储区域，则存储控制器确定删除操作和读指令对应的读操作；存储控制器根据第二物理地址从存储阵列中确定第二数据，根据读操作读取并向主设备返回第二数据，并根据删除操作删除第二数据。
该种可能的实施方式中，主设备发送的指示命令只需要指示第二数据的第二逻辑地址和读指令，当存储控制器根据第二逻辑地址查表获得的第二物理地址位于上述预设存储区域时，则表示该第二数据需要在主设备进行更新或舍弃的数据，即闪存阵列中存储的第二数据没有用处了，则闪存设备控制器确定需要对该第二数据执行读操作并执行删除操作，无需等待主设备下发的删除命令，可以减少写放大。
在第四方面的一种可能的实施方式中，上述步骤并根据删除操作删除第一数据之前，该方法还包括：存储控制器确定在执行对第三数据的读操作或写操作，则在日志中记录对第二数据的删除操作；上述步骤并根据删除操作删除第二数据，包括：存储控制器在执行完对第三数据的读操作或写操作后，根据日志中的记录，执行对第二数据的删除操作。
该种可能的实施方式中，在读取并向主设备返回该第二数据后，删除存储阵列中的第二数据之前，还需要确认是否有除第二数据之外的其他数据(第三数据)在执行读操作或写操作，如果存在第三数据在执行读操作，可以将第二数据的删除操作记录在日志中，当第三数据的读操作或写操作执行完毕后，即可按照日志中记录的删除操作的记录顺序依次执行删除操作，可以避免增加其他数据的读写时延。
本申请第五方面提供一种主设备，该存储管理装置具有实现上述第一方面、第一方面任意一种可能实现方式、第三方面或第三方面任意一种可能实现方式的方法的功能。该功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。该硬件或软件包括一个或多个与上述功能相对应的模块，例如：接收单元和处理单元。
本申请第六方面提供一种存储控制器，该处理装置具有实现上述第二方面、第二方面任意一种可能实现方式、第四方面或第四方面任意一种可能实现方式的方法的功能。该功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。该硬件或软件包括一个或多个与上述功能相对应的模块，例如：发送单元和处理单元。
本申请第七方面提供一种计算机设备，该计算机设备包括至少一个处理器、存储系统、输入/输出(input/output，I/O)接口以及存储在存储系统中并可在处理器上运行的计算机执行指令，当计算机执行指令被处理器执行时，处理器执行如上述第一方面、第一方面 任意一种可能实现方式、第三方面或第三方面任意一种可能实现方式的方法。
本申请第八方面提供一种计算机设备，该计算机设备包括至少一个处理器、存储器、输入/输出(input/output，I/O)接口以及存储在存储器中并可在处理器上运行的计算机执行指令，当计算机执行指令被处理器执行时，处理器执行如上述第二方面、第二方面任意一种可能实现方式、第四方面或第四方面任意一种可能实现方式的方法。
本申请第九方面提供一种存储一个或多个计算机执行指令的计算机可读存储介质，当计算机执行指令被处理器执行时，处理器执行如上述第一方面至第四方面或第一方面至第四方面任意一种可能的实现方式的方法。
本申请第十方面提供一种存储一个或多个计算机执行指令的计算机程序产品，当计算机执行指令被处理器执行时，处理器执行如上述第一方面至第四方面或第一方面至第四方面任意一种可能的实现方式的方法。
附图说明
图1为本申请实施例提供的数据读写的系统框架示意图；
图2为本申请实施例提供的命令交互方式示意图；
图3为本申请实施例提供的数据处理方法一实施例流程图；
图4为本申请实施例提供的数据处理方法另一实施例流程图；
图5为本申请实施例提供的主设备的一实施例示意图；
图6为本申请实施例提供的存储控制器的一实施例示意图；
图7为本申请实施例提供的主设备的另一实施例示意图；
图8为本申请实施例提供的存储控制器的另一实施例示意图；
图9为本申请实施例提供的计算机设备的一实施例示意图；
图10为本申请实施例提供的计算机设备的另一实施例示意图。
具体实施方式
下面结合附图，对本申请的实施例进行描述，显然，所描述的实施例仅仅是本申请一部分的实施例，而不是全部的实施例。本领域普通技术人员可知，随着技术的发展和新场景的出现，本申请实施例提供的技术方案对于类似的技术问题，同样适用。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这里图示或描述的内容以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
本申请实施例提供了一种数据处理方法及相关设备，用于节省了命令开销和减少写放大。
本申请实施例可应用于如图1所示的数据读写的系统框架，该系统框架包括主设备11和存储控制器12，主设备11可以为处理器，本实施例以主机(host)为例。存储控制器12可以为以nand介质的固态存储设备中的控制装置，示例性的本申请实施例以固态硬盘(solid state disk，SSD)的闪存设备控制器(storage device controller)为例。主设备11在确定所要读取的内容后，可以将读命令发送给存储控制器12，存储控制器12在接收到该读命令后可以根据该读命令携带的逻辑地址查表获取物理地址以读取主设备11所需的内容。主设备11也可以将要添加的新文件和写命令发送给存储控制器12，存储控制器12可以根据写命令执行新文件的写入操作。主设备11包括实时操作系统(kernel)111、驱动程序(driver)112和第一接口(interface)113。存储控制器12包括第二接口121、处理器(central processing unit，CPU)122、静态随机存取存储器(static random access memory，SRAM)123和nand控制器(controller)124，本系统框架还包括闪存阵列(nand flash array)13，以及包括存储控制器12和闪存阵列13的存储设备14。
实时操作系统111用于对存储控制器12下发的读命令的地址映射或写命令的地址分配。
驱动程序112是一个和存储控制器12进行数据交互的程序。这个程序包括一些如何与存储控制器12传输信息，如何设置数据格式，如何进行初始化，如何中止等配置数据。
第一接口113用于传输主设备11和存储控制器12之间的信息交互。
第二接口121用以连接第一接口113，承担数据传输的功能。通过例如通用闪存存储(universal flash storage，UFS)、嵌入式多媒体卡(embedded mutlti-media card，EMMC)、总线和接口标准(peripheral component interconnect express，PCIE)等方式与主机传输数据。
处理器122用于处理来自第二接口121的数据。
静态随机存取存储器123用于加速处理器122内部数据的传输。
nand控制器124用于控制和管理nand。
闪存阵列13是数据最终存储的物理载体，通常包含有多个闪存裸片(nand flash die)131。
存储设备14用于承载存储控制器12和闪存阵列13。
当前，通过大数据和用户应用软件(application，APP)使用场景的统计中，手机用户每天新增几十个G的数据写入量，但产生的容量增长一般仅为数据写入量的5％以下，而且手机每天读取的数据量要多于写入的数据量，并且这些读取写入操作的地址重叠概率很高。因此实际上在手机用户使用过程中存在很多热数据或临时缓冲在数据读完之后处于无效状态，这些热数据或临时缓冲的物理地址已经可以被覆盖重新写入其他数据。主设备需要发布删除命令来告知存储控制器这些热数据或者临时缓冲为无效数据，若直接覆盖重新写入其他数据则可能会造成闪存阵列空间虚占，导致器件写放大增大。请参阅图2所示的现有技术的命令交互方式示意图，主设备向存储控制器发送读命令(read command)后，存储控制器向主设备发送反馈信息(response)，主设备再向存储控制器发送删除命令(erase command)，并接受存储控制器发送的反馈信息(response)。主设备需要通过2步 完成读完之后做删除操作。第一步发送读命令，逻辑区块地址(logical block address,LBA)为0，长度为0x100，第二步告知器件LBA为0，长度0x100的地址需要删除，即占用了额外的命令通道，为减少命令通道的使用，本申请实施例提供了相应的数据处理方法，该方法包括存储控制器接收来自主设备的对第一数据的操作命令，第一数据为主设备待从存储控制器所管理的存储阵列读取的数据；存储控制器根据操作命令确定对第一数据执行读操作和删除操作；存储控制器根据读操作将第一数据从存储阵列中读出并发送给主设备，再对存储阵列中存储的第一数据执行删除操作。
可选的，上述数据处理方法也可以应用在一次性读完并清除缓存和安全交互数据的应用场景中。
下面，基于上述的系统框架，下面对本申请实施例中的数据处理方法进行描述。
本实施例的存储控制器可以为所有基于与非门颗粒(nand flash)的非易失性存储器(nonvolatile memory，NVM)，它不用定期地刷新存储器内容，这包括所有形式的只读存储器(read only memory image，ROM)，像是可编程只读存储器(programmable read only memory image，PROM)、可擦可编程只读存储器(erasable programmable read only memory image，EPROM)、电可擦除只读存储器(electrically erasable programmable read only memory image，EEPROM)和闪存，也包括电池供电的随机存取储存器(random access memory，RAM)。
存储控制器上通常按页来存储和读取数据。而按块(block)来擦除数据。块(也称物理块)包含多个页。存储介质上的页(称为物理页)具有固定的尺寸，例如17664字节。物理页也可以具有其他的尺寸。
在存储控制器中，可以利用闪存转换层(flash translation layer，FTL)来维护从逻辑地址到物理地址的映射信息。逻辑地址构成了操作系统等上层软件所感知到的固态存储设备的存储空间。物理地址是用于访问固态存储设备的物理存储单元的地址。在相关技术中还可利用中间地址形态实施地址映射。例如将逻辑地址映射为中间地址，进而将中间地址进一步映射为物理地址。
存储了从逻辑地址到物理地址的映射信息的表结构被称为FTL表。FTL表是固态存储设备中的重要元数据。FTL表的数据项记录了存储控制器中以数据单元为单位的地址映射关系。在一个例子中，FTL表中的逻辑页对应4KB存储空间，而物理页的存储空间也为4KB(还包括附加的带外存储空间)。FTL表为每个4KB的数据单元提供一条记录，以记录其逻辑地址到物理地址的映射。在另一个例子中，数据单元对应的存储空间大小和物理页的存储空间大小不同，例如物理页可容纳多个数据单元，数据单元对应4KB的存储空间，而物理页的存储空间能够容纳多个数据单元(例如4个)。
FTL表包括多个FTL表条目(或称表项)。在一种情况下，每个FTL表条目中记录了一个逻辑页地址与一个物理页的对应关系。在另一种情况下，每个FTL表条目中记录了连续的多个逻辑页地址与连续的多个物理页的对应关系。在又一种情况下，每个FTL表条目中记录了逻辑块地址与物理块地址的对应关系。在依然又一种情况下，FTL表中记录逻辑块地址与物理块地址的映射关系，和/或逻辑页地址与物理页地址的映射关系。
本申请实施例中，主设备可以直接指示存储控制器第一数据需要执行读完即删除操作，也可以间接指示存储控制器该数据需要执行读完即删除操作。
一、主设备直接指示存储控制器该数据需要执行读完即删除操作。
本实施例中，主设备直接发送读命令和删除命令。请参阅图3，本申请实施例中数据处理方法一实施例包括：
301、host根据第一数据确定指示命令。
本实施例中，host在确定接下来要读取的第一数据后，可以根据该第一数据的应用场景确定指示命令，例如，该应用场景可以为第一数据为需要在host进行更新或舍弃的数据，则host可以确定该第一数据在存储阵列中为读完即删除的数据，可以确定第一数据对应的同时包括逻辑地址、读指令和删除指令的指示命令，该指示命令只需要占用一次命令交互。
第一数据为待从固态硬盘中的nand阵列中读取的数据。
该第一数据可以为即时性数据或者临时缓冲数据，示例性的，对于手机交换区(SWAP)应用场景，该功能预估会带来每天一定的写入量，而这部分写入量也会有额外的写放大；由于SWAP数据换入到内存后，这部分数据即为即时性数据，需要尽快下发删除命令对该部分数据做删除，否则就会造成器件侧的无效数据搬移，导致SWAP使用场景的写放大变大。
写放大即为垃圾回收(garbage collection，GC)垃圾回收技术中将有效的数据搬到另一个块(block)中，原本就已经写入过一次的数据再加上这次搬迁就又多了一次写入，构成了写入放大。
302、host向闪存设备控制器发送指示命令。
host在确定上述第一数据的指示命令后，可以通过host与固态硬盘之间的接口传输该指示命令，该指示命令可以使得闪存设备控制器获得该指示命令中的逻辑地址、读指令和删除指令。
303、闪存设备控制器根据逻辑地址确定存储阵列中的第一数据。
本实施例中，闪存设备控制器在接收到指示命令后，可以获取该指示命令中的逻辑地址，然后根据该逻辑地址查询FTL表以获得该第一数据对应的物理地址，即可确定该第一数据在闪存阵列中的存储位置。
304、闪存设备控制器根据读指令向闪存阵列发送读取第一数据的读取命令。
本实施例中，闪存设备控制器在确定物理地址后，可以从固态硬盘中的闪存阵列对应的物理地址上读取该第一数据作为对读指令的响应。
305、闪存阵列向闪存设备控制器发送第一数据。
闪存阵列在接收到闪存设备控制器发送的关于读取第一数据的读取命令后，闪存阵列可以基于该读取命令上携带的物理地址信息读取第一数据，然后发送给闪存设备控制器。
306、闪存设备控制器向host发送的第一数据。
闪存设备控制器在基于读命令的读操作执行对闪存阵列中的第一数据的读取之后，可以通过接口向host发送该第一数据。
307、闪存设备控制器确定在执行对第二数据的读操作或写操作时，则在日志中记录对第一数据的删除操作。
闪存设备控制器在执行完上述读操作后，可以判断当前是否还接收到host发送的关于第二数据的读命令或写命令，即可以判断当前是否还需执行对闪存阵列中的第二数据的读操作。如果当前没有关于第二数据的读操作或写操作，则闪存设备控制器可以直接基于该删除操作指示的物理地址执行对上述nand阵列的第一数据的删除操作；如果当前还存在关于第二数据的读操作或写操作，为避免影响第二数据的读操作或写操作的执行，即为避免影响处理时延，闪存设备控制器可以将该删除操作记录在日志(log)中，以便延后处理。
第二数据为与第一数据不同的数据，该第二数据可以为一个或多个。
308、闪存设备控制器在执行完对第二数据的读操作或写操作后，根据日志中的记录，执行对第一数据的删除操作。
本实施例中，闪存设备控制器在执行完对第二数据的读操作或写操作后，即当前没有接收到host发送的任何数据的读写命令，则可以查询日志中的记录以对第一数据的删除操作。可选的，日志中记录基于多个数据的删除操作时，闪存设备控制器可以基于日志中记录时间按顺序对nand阵列执行删除操作。
本申请实施例的技术方案中，host发送的指示命令中同时包括读指令和删除指令，闪存设备控制器对第一数据执行读操作后执行删除操作，host不需要再次发送删除命令，解决了现有技术中EMMC的host发布命令所需开销大的问题，并且删除命令下发更及时，减少固态硬盘的写放大，提升了固态硬盘的使用寿命。
二、主设备间接指示存储控制器该数据需要执行读完即删除操作。
本实施例中，主设备在存储阵列中预配置一个预设存储区域，只需发送读指令。请参阅图4，本申请实施例中数据处理方法另一实施例包括：
401、host向存储控制器发送第一数据的写入命令。
本实施例中，基于需要对第一数据进行更新或舍弃的应用场景，host将该第一数据存储到闪存设备控制器所管理的闪存阵列中的预设存储区域中，该预设存储区域为host预先配置的，该预设存储区域中的数据在进行读取后都需要执行删除操作。host可以向闪存设备控制器发送写入命令，该写入命令包括第一数据、第一逻辑地址和写指令，该第一逻辑地址可以指示处于该预设存储区域中的第一物理地址。闪存设备控制器可以接收该写入命令并执行相应操作。
402、闪存设备控制器根据第一逻辑地址查表获得第一物理地址。
闪存设备控制器可以根据指示命令中的第一逻辑地址查询FTL表获得第一数据对应的第一物理地址。
403、闪存设备控制器根据写指令将第一数据存储到第一物理地址所指示的存储位置。
闪存设备控制器在确定第一物理地址后，可以直接将该第一数据存储到预设存储区域中。
404、host向闪存设备控制器发送对第二数据的指示命令。
当host需要读取闪存阵列中的第二数据时，可以对闪存设备控制器发送只包括逻辑地址和读指令的指示命令。
405、闪存设备控制器根据第二逻辑地址查表获得第二物理地址，并确定第二数据。
闪存设备控制器可以根据该第二逻辑地址查询FTL表获得该第二数据在闪存阵列中的物理地址，即确定第二数据的存储位置。
406、如果第二物理地址处于预设存储区域，闪存设备控制器确定删除操作和读操作。
当第二数据的第二物理地址处于上述预设存储区域时，则表示该第二数据需要在host进行更新或舍弃的数据，即闪存阵列中存储的第二数据没有用处了，则闪存设备控制器确定需要对该第二数据执行读操作并执行删除操作。
407、闪存设备控制器根据读操作向闪存阵列发送读取第二数据的读取命令。
408、闪存阵列向闪存设备控制器发送第二数据。
409、闪存设备控制器向host发送的第二数据。
410、闪存设备控制器确定在执行对第三数据的读操作或写操作，则在日志中记录对第二数据的删除操作。
411、闪存设备控制器在执行完对第三数据的读操作或写操作后，根据日志中的记录，执行对第二数据的删除操作。
本实施例步骤407-411中读取第二数据并删除闪存阵列中的第二数据可以参照图3所述的数据处理方法实施例中的步骤304-308中读取第一数据并删除闪存阵列中的第一数据的相关描述，具体此处不再赘述。
本申请实施例的技术方案中，host发送的指示命令中同时包括读指令和删除指令，闪存设备控制器对第一数据执行读操作后执行删除操作，host不需要再次发送删除命令，解决了现有技术中EMMC的host发布命令所需开销大的问题，并且删除命令下发更及时，减少固态硬盘的写放大，提升了固态硬盘的使用寿命。
以上描述了数据处理方法，下面结合附图介绍本申请实施例的存储控制器和主设备。
图5为本申请实施例中主设备50的一实施例示意图。
如图5所示，本申请实施例提供了一种主设备，该主设备包括：
确定单元501，用于根据第一数据确定指示命令，第一数据为待从存储控制器所管理的存储阵列读取的数据，且第一数据为需要在主设备进行更新或舍弃的数据，指示命令包括第一数据的逻辑地址、读指令和删除指令；
发送单元502，用于向存储控制器发送指示命令，以指示存储控制器根据物理地址从存储阵列中确定第一数据，根据读指令读取并返回第一数据，并根据删除指令从存储阵列中删除第一数据，物理地址为存储控制器根据逻辑地址查表获得的。
可选的，第一数据为即时性数据，即时性数据为不会被再次使用的数据。
以上所描述的主设备可以参阅前述方法实施例部分的相应内容进行理解，此处不做过多赘述。
图6为本申请实施例中存储控制器60的一实施例示意图。
如图6所示，本申请实施例提供了一种存储控制器，该存储控制器包括：
接收单元601，用于接收来自主设备的对第一数据的指示命令，第一数据为主设备待从存储控制器所管理的存储阵列读取的数据，指示命令包括第一数据的逻辑地址、读指令和删除指令；
查询单元602，用于根据逻辑地址查表获得第一数据的物理地址；
处理单元603，用于根据物理地址从存储阵列中确定第一数据，根据读指令读取并向主设备返回第一数据，并根据删除指令从存储阵列中删除第一数据。
可选的，存储控制器60还包括记录单元604，记录单元604用于确定在执行对第二数据的读操作或写操作，则在日志中记录对第一数据的删除操作；处理单元603具体用于：在执行完对第二数据的读操作或写操作后，根据日志中的记录，执行对第一数据的删除操作。
以上所描述的存储控制器可以参阅前述方法实施例部分的相应内容进行理解，此处不做过多赘述。
图7为本申请实施例中主设备70的一实施例示意图。
如图7所示，本申请实施例提供了一种主设备，该主设备包括：
发送单元701，用于主设备向存储控制器发送第一数据的写入命令，写入命令包括第一数据、写指令和第一逻辑地址，第一数据为需要在主设备进行更新或舍弃的数据，第一逻辑地址所指示的第一物理地址处于存储控制器所管理的存储阵列中的预设存储区域，预设存储区域为预配置的数据读取后再执行删除的区域。
可选的，发送单元701还用于向存储控制器发送对第二数据的指示命令，第二数据为处理装置待从存储管理装置所管理的存储阵列读取的数据，指示命令包括第二数据的第二逻辑地址和读指令，以指示存储控制器根据第二物理地址从存储阵列中确定第一数据，根据读指令读取并返回第一数据，并删除第一数据，第二物理地址为存储控制器根据第二逻辑地址查表获得的。
以上所描述的主设备可以参阅前述方法实施例部分的相应内容进行理解，此处不做过多赘述。
图8为本申请实施例中存储控制器80的一实施例示意图。
如图8所示，本申请实施例提供了一种存储控制器，该存储控制器包括：
接收单元801，用于接收来自主设备的写入命令，所述写入命令包括第一数据、写指令和第一逻辑地址，所述第一数据为需要在所述主设备进行更新或舍弃的数据；
查询单元802，用于根据所述第一逻辑地址查表获得第一物理地址，所述第一物理地址位于所述存储控制器所管理的存储阵列中的预设存储区域内，所述预设存储区域为预配置的数据读取后再执行删除的区域；
存储单元803，用于根据所述写指令将所述第一数据存储到所述第一物理地址所指示的存储位置。
可选的，接收单元801还用于接收来自主设备的对第二数据的指示命令，第二数据为处理装置待从存储管理装置所管理的存储阵列读取的数据，指示命令包括第二数据的第二逻辑地址和读指令；查询单元802还用于根据第二逻辑地址查表获得第二数据的第二物理地址；存储控制器80还包括处理单元804，用于当第二物理地址处于预设存储区域时，存储控制器确定删除操作和读指令对应的读操作；存储控制器根据第二物理地址从存储阵列中确定第二数据，根据读操作读取并向主设备返回第二数据，并根据删除操作删除第二数据。
图9所示，为本申请的实施例提供的计算机设备90的一种可能的逻辑结构示意图。计算 机设备90包括：处理器901、通信接口902、存储系统903以及总线904。处理器901、通信接口902以及存储系统903通过总线904相互连接。在本申请的实施例中，处理器901用于对计算机设备90的动作进行控制管理，例如，处理器901用于执行图3至图4的方法实施例中存储控制器所执行的步骤。通信接口902用于支持计算机设备90进行通信。存储系统903，用于存储计算机设备90的程序代码和数据。
其中，处理器901可以是中央处理器单元，通用处理器，数字信号处理器，专用集成电路，现场可编程门阵列或者其他可编程逻辑器件、晶体管逻辑器件、硬件部件或者其任意组合。其可以实现或执行结合本申请公开内容所描述的各种示例性的逻辑方框，模块和电路。处理器901也可以是实现计算功能的组合，例如包含一个或多个微处理器组合，数字信号处理器和微处理器的组合等等。总线904可以是外设部件互连标准(Peripheral Component Interconnect，PCI)总线或扩展工业标准结构(Extended Industry Standard Architecture，EISA)总线等。总线可以分为地址总线、数据总线、控制总线等。为便于表示，图9中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
主设备50中的发送单元502相当于计算机设备90中的通信接口902，存储控制器50中的确定单元501可以相当于处理器901。
主设备70中的发送单元701相当于计算机设备90中的通信接口902。
本实施例的计算机设备90可对应于上述各个方法实施例中的主设备，该计算机设备90中的处理器901和通信接口902可以实现上述各个方法实施例中的主设备所具有的功能和/或所实施的各种步骤，为了简洁，在此不再赘述。
图10所示，为本申请的实施例提供的计算机设备100的一种可能的逻辑结构示意图。计算机设备100包括：处理器1001、通信接口1002、存储系统1003以及总线1004。处理器1001、通信接口1002以及存储系统1003通过总线1004相互连接。在本申请的实施例中，处理器1001用于对计算机设备100的动作进行控制管理，例如，处理器1001用于执行图3至图4的方法实施例中主设备所执行的步骤。通信接口1002用于支持计算机设备100进行通信。存储系统1003，用于存储计算机设备100的程序代码和数据。
其中，处理器1001可以是中央处理器单元，通用处理器，数字信号处理器，专用集成电路，现场可编程门阵列或者其他可编程逻辑器件、晶体管逻辑器件、硬件部件或者其任意组合。其可以实现或执行结合本申请公开内容所描述的各种示例性的逻辑方框，模块和电路。处理器1001也可以是实现计算功能的组合，例如包含一个或多个微处理器组合，数字信号处理器和微处理器的组合等等。总线1004可以是外设部件互连标准(Peripheral Component Interconnect，PCI)总线或扩展工业标准结构(Extended Industry Standard Architecture，EISA)总线等。总线可以分为地址总线、数据总线、控制总线等。为便于表示，图10中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
存储控制器60中的接收单元601相当于计算机设备100中的通信接口1002，存储控制器60中的查询单元602、处理单元603和记录单元604可以相当于处理器1001。
存储控制器80中的接收单元801相当于计算机设备100中的通信接口1002，存储控制器80中的查询单元802、存储单元803和处理单元804可以相当于处理器1001。
本实施例的计算机设备100可对应于上述各个方法实施例中的存储控制器，该计算机设备100中的处理器1001和通信接口1002可以实现上述各个方法实施例中的存储控制器所具有的功能和/或所实施的各种步骤，为了简洁，在此不再赘述。
在本申请的另一实施例中，还提供一种计算机可读存储介质，计算机可读存储介质中存储有计算机执行指令，当设备的处理器执行该计算机执行指令时，设备执行上述图3至图4中存储控制器所执行的数据处理方法的步骤。
在本申请的另一实施例中，还提供一种计算机可读存储介质，计算机可读存储介质中存储有计算机执行指令，当设备的处理器执行该计算机执行指令时，设备执行上述图3至图4中主设备所执行的数据处理方法的步骤。
在本申请的另一实施例中，还提供一种计算机程序产品，该计算机程序产品包括计算机执行指令，该计算机执行指令存储在计算机可读存储介质中；当设备的处理器执行该计算机执行指令时，设备执行上述图3至图4中存储控制器所执行的数据处理方法的步骤。
在本申请的另一实施例中，还提供一种计算机程序产品，该计算机程序产品包括计算机执行指令，该计算机执行指令存储在计算机可读存储介质中；当设备的处理器执行该计算机执行指令时，设备执行上述图3至图4中主设备所执行的数据处理方法的步骤。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请实施例的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统，装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出 来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，read-only memory)、随机存取存储器(RAM，random access memory)、磁碟或者光盘等各种可以存储程序代码的介质。

Claims (13)

  1. 一种数据处理方法，其特征在于，包括：
    主设备根据第一数据确定指示命令，所述第一数据为待从存储控制器所管理的存储阵列读取的数据，且所述第一数据为需要在所述主设备进行更新或舍弃的数据，所述指示命令包括第一数据的逻辑地址、读指令和删除指令；
    所述主设备向所述存储控制器发送所述指示命令，以指示所述存储控制器根据物理地址从所述存储阵列中确定所述第一数据，根据所述读指令读取并返回所述第一数据，并根据所述删除指令从所述存储阵列中删除所述第一数据，所述物理地址为所述存储控制器根据所述逻辑地址查表获得的。
  2. 根据权利要求1所述的数据处理方法，其特征在于，所述第一数据为即时性数据，所述即时性数据为不会被再次使用的数据。
  3. 一种数据处理方法，其特征在于，包括：
    存储控制器接收来自主设备的对第一数据的指示命令，所述第一数据为所述主设备待从存储控制器所管理的存储阵列读取的数据，所述指示命令包括第一数据的逻辑地址、读指令和删除指令；
    所述存储控制器根据所述逻辑地址查表获得所述第一数据的物理地址；
    所述存储控制器根据所述物理地址从所述存储阵列中确定所述第一数据，根据所述读指令读取并向所述主设备返回所述第一数据，并根据所述删除指令从所述存储阵列中删除所述第一数据。
  4. 根据权利要求3所述的数据处理方法，其特征在于，所述并根据所述删除指令从所述存储阵列中删除所述第一数据之前，所述方法还包括：
    所述存储控制器确定在执行对第二数据的读操作或写操作，则在日志中记录对所述第一数据的删除操作；
    所述并根据所述删除指令从所述存储阵列中删除所述第一数据，包括：
    所述存储控制器在执行完对所述第二数据的读操作或写操作后，根据所述日志中的记录，执行对所述第一数据的删除操作。
  5. 一种数据处理方法，其特征在于，包括：
    主设备向存储控制器发送第一数据的写入命令，所述写入命令包括所述第一数据、写指令和第一逻辑地址，所述第一数据为需要在所述主设备进行更新或舍弃的数据，所述第一逻辑地址所指示的第一物理地址处于存储控制器所管理的存储阵列中的预设存储区域，所述预设存储区域为预配置的数据读取后再执行删除的区域。
  6. 根据权利要求5所述的数据处理方法，其特征在于，所述方法还包括：
    所述主设备向所述存储控制器发送对第二数据的指示命令，所述第二数据为所述处理装置待从所述存储管理装置所管理的存储阵列读取的数据，所述指示命令包括所述第二数据的第二逻辑地址和读指令，以指示所述存储控制器根据第二物理地址从所述存储阵列中确定所述第一数据，根据所述读指令读取并返回所述第一数据，并删除所述第一数据，所述第二物理地址为所述存储控制器根据所述第二逻辑地址查表获得的。
  7. 一种数据处理方法，其特征在于，包括：
    存储控制器接收来自主设备的写入命令，所述写入命令包括第一数据、写指令和第一逻辑地址，所述第一数据为需要在所述主设备进行更新或舍弃的数据；
    所述存储控制器根据所述第一逻辑地址查表获得第一物理地址，所述第一物理地址位于所述存储控制器所管理的存储阵列中的预设存储区域内，所述预设存储区域为预配置的数据读取后再执行删除的区域；
    所述存储控制器根据所述写指令将所述第一数据存储到所述第一物理地址所指示的存储位置。
  8. 根据权利要求7所述的数据处理方法，其特征在于，所述方法还包括：
    所述存储控制器接收来自所述主设备的对第二数据的指示命令，所述第二数据为所述处理装置待从所述存储管理装置所管理的存储阵列读取的数据，所述指示命令包括所述第二数据的第二逻辑地址和读指令；
    所述存储控制器根据所述第二逻辑地址查表获得所述第二数据的第二物理地址；
    如果所述第二物理地址处于所述预设存储区域，则所述存储控制器确定删除操作和所述读指令对应的读操作；
    所述存储控制器根据所述第二物理地址从所述存储阵列中确定所述第二数据，根据所述读操作读取并向所述主设备返回所述第二数据，并根据所述删除操作删除所述第二数据。
  9. 根据权利要求8所述的数据处理方法，其特征在于，所述并根据所述删除操作删除所述第一数据之前，所述方法还包括：
    所述存储控制器确定在执行对第三数据的读操作或写操作，则在日志中记录对所述第二数据的所述删除操作；
    所述并根据所述删除操作删除所述第二数据，包括：
    所述存储控制器在执行完对所述第三数据的读操作或写操作后，根据所述日志中的记录，执行对所述第二数据的所述删除操作。
  10. 一种计算机设备，其特征在于，包括：处理器、存储器以及通信接口，
    所述处理器用于执行所述存储器中存储的指令，使得所述计算机设备执行权利要求1至2和5至6中任一项所述的方法。
  11. 一种计算机设备，其特征在于，包括：处理器、接口以及存储器，
    所述处理器用于根据所述接口传输的数据执行所述存储器中存储的指令，使得所述计算机设备执行权利要求3至4和7至9中任一项所述的方法。
  12. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质中保存有程序，当所述计算机执行所述程序时，执行如权利要求1至9中任一项所述的方法。
  13. 一种计算机程序产品，其特征在于，当所述计算机程序产品在计算机上执行时，所述计算机执行如权利要求1至9中任一项所述的方法。
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