WO2022107104A2

WO2022107104A2 - Multi-parallel and serial optical digital to analog conversion

Info

Publication number: WO2022107104A2
Application number: PCT/IB2021/060857
Authority: WO
Inventors: Moshe Nazarathy
Original assignee: Technion Research And Development Foundation Ltd.
Priority date: 2020-11-23
Filing date: 2021-11-23
Publication date: 2022-05-27
Also published as: WO2022107104A3

Abstract

An optical digital to analog converter (oDAC) that may include (a) multiple optical paths that are parallel to each other; (b) a combiner, (c) a splitter that is configured to receive an optical signal at a splitter input and split the optical signal between multiple splitter outputs to provide multiple path input signals to the multiple optical paths. The multiple optical paths are configured to optically process, in parallel, path input signals to provide path output signals. Each optical path is configured to apply an optical process that comprises applying optical modulation, by an optical gate of the optical path and under a control of an electrical modulator, to provide an optical signal having a value selected out of multiple constellation levels. The combiner is configured to add the multiple path output signals to provide an oDAC output signal having a value selected from values of a single quadrature constellation.

Description

Multi-parallel and serial optical digital to analog conversion CROSS REFERENCE This application claims priority from US provisional patent serial number 63/198,936 filing date November 23, 2020 which is incorporated herein in its entirety. BACKGROUND Electronic Digital to Analog Converters (DAC), abbreviated here as oDAC, are key interfaces from the digital to the analog domains. In high-speed Digital Optical transmission applications, the Digital to Optical (D/O) translation occurring in the optical transmitter typically entails D/A, i.e., electronic DAC (eDAC) conversion, followed by Analog-to-Optical (A/O) modulation. Thus, the state-of-the-art widespread solution is to realize D/O as an eDAC ^Optical-Modulator cascade. It would be advantageous, from the viewpoints of performance, energy efficiency, complexity and cost reduction, to consider direct conversion from the Digital to the Optical domain (D/O), eliminating or at least minimizing the eDACs intermediary, especially in ultra-high-speed applications where eDAC technology is hard to scale up in speed, in terms of power consumption and performance. BRIEF DESCRIPTION OF THE DRAWINGS The embodiments of the disclosure will be understood and appreciated more fully from the following detailed description, taken in conjunction with the drawings in which: FIG.1 illustrates an example of a SEMZM based SEMZM and an example of a MPMZM 3 bit ODAC; FIG.2 illustrates an example of a SEMZM based ODAC; FIG.3A illustrates an example of optical power distances; FIG.3B illustrates an example of optical field distances; FIG.4A illustrates an example of an angular constraint regions and maximin points; FIG.4B illustrates an example of a min distance function; FIG.5A illustrates an example of a min distance function; FIG.5B illustrates an example of a min distance function; FIG.6 illustrates an example of constellations;FIG.7A illustrates an example of a S-way MPoDAC; FIG.7B illustrates an example of a MPoDAC based 3-way ODAC; FIG.7C illustrates an example of a 2-way MPoDAC; FIG.8A illustrates an example of a 2-bit BiWgt PAM4 COH MPoDAC; FIG.8B illustrates an example of MPMZM based 2bit ODAC; FIG.9 illustrates examples of a min distance function; FIG.10 illustrates an example of a normalized constellation distances; FIG.11 illustrates an example of a normalized constellation distances; FIG.12 illustrates an example of a dual-parallel ODAC; FIG.13 illustrates an example of a 2-bit COH PAM4 MPMZM oDAC; FIG.14 illustrates an example of an Optically Amplified Recirculating Phase-Gate; FIG.15 illustrates an example of Phase gate modulation operating characteristics;FIG.16 illustrates an example of a VOA-MZM; FIG.17 illustrates an example of a MZM-with-VOA-MZMs; FIG.18 illustrates an example of a VOA-MZM-based Phase-Gate or intensity gate; FIG.19 illustrates an example of a VOA-MZM-based Phase-Gate or intensity gate; FIG.20A illustrates an example of a prior art variable 2x2 optical MIMO matrix; FIG.20B illustrates an example of an improved variable 2x2 optical MIMO matrix; FIG.21 illustrates an example of an Optical Signal Processor; FIG.22 illustrates an example of 3:3 and 4:4 Mode Converters; FIG.23 illustrates an example of variable 1:S splitters and S:1 combiners, for S=4 and S=3; FIG.24 illustrates an example of 3-bit BiWgt MPoDACs; FIG.25 illustrates an example of VAR 1:4 splitters; FIG.26 illustrates an example of VAR 1:5 splitters; FIGs.27A and 27B illustrate examples of tree block diagrams of 1:4 splitter embodiments of FIG. 26; FIG.28 illustrates an example of a Direct-Detection PAM4 constellation generator; FIG.29 illustrates an example of a min-distance function; FIG.30 illustrates an example of BiWgt 2MP PAM4 DD constellations; FIG.31 illustrates an example of a 3-bit BiWgt PAM8 DD MPODAC; FIG.32 illustrates an example of an angular constraint regions and maximin points; FIG.33 illustrates an example of an angular constraint regions and maximin points; FIG.34A illustrates an example of a DD-PAM4-3MP-embedded ODAC; FIG.34B illustrates an example of a DD-PAM4-3MP-embedded ODAC; FIG.35 illustrates an example of BiWgt 2MP PAM4 DD constellations; FIG.36 illustrates an example of a PAM4-DD 3MP; FIG.37 illustrates an example of a ThWgt 2-bit PAM4 DD 3-way MPoDAC; FIG.38A illustrates an example of a S-way Multi-Parallel-MPoDAC; FIG.38B illustrates an example of a 3-bit ODAC module; FIG.39 illustrates examples of Quadrature Multiplexers; FIG.40A illustrates an example of a IQ-MPoDAC QAM-2^2B generator; FIG.40B illustrates an example of a PDM 2xQAM-2^2B optical transmitter; FIG.40C illustrates an example of a PDM 2xQAM-2^2B optical transmitter; FIG.40D illustrates an example of modulators; FIG.41 illustrates an example of a 2-way PAM2|4 ML-driven reprogrammable MPoDAC; FIG.42 illustrates an example of a Optical monitors and slow phase actuators for the control plane of the MPoDAC of FIG.43; FIG.43 illustrates an example of a Generic S-way reprogrammable ML-driven MPoDAC; FIG.44 illustrates an example of a 3-way realization of Fig 43; FIG.45 includes an example of a table; FIG.46 includes an example of matrices; FIG.47 illustrates an example of a method; and FIG.48 illustrates an example of a ODAC. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, and components have not been described in detail so as not to obscure the present invention. The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings. It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements. Because the illustrated embodiments of the present invention may for the most part, be implemented using electronic components and circuits known to those skilled in the art, details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention. Any reference in the specification to a method should be applied mutatis mutandis to a device or system capable of executing the method and/or to a non-transitory computer readable medium that stores instructions for executing the method. Any reference in the specification to a system or device should be applied mutatis mutandis to a method that may be executed by the system, and/or may be applied mutatis mutandis to non-transitory computer readable medium that stores instructions executable by the system. Any reference in the specification to a non-transitory computer readable medium should be applied mutatis mutandis to a device or system capable of executing instructions stored in the non-transitory computer readable medium and/or may be applied mutatis mutandis to a method for executing the instructions. Any combination of any module or unit listed in any of the figures, any part of the specification and/or any claims may be provided. Electronic domain processors may be a processing circuitry. The processing circuitry may be implemented as a central processing unit (CPU), and/or one or more other integrated circuits such as application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), full-custom integrated circuits, etc., or a combination of such integrated circuits. It should be noted that for simplicity of explanation electrical domain drivers of various components are not shown for simplicity of explanation. Any combination of any steps of any method illustrated in the specification and/or drawings may be provided. Any combination of any subject matter of any of claims may be provided. Any combinations of systems, units, components, processors, sensors, illustrated in the specification and/or drawings may be provided. Figure 1 illustrates an example of a SEMZM based thermometer 11 and an example of a MPMZM 3 bit ODAC 12. Figure 2 illustrates an example of a SEMZM based thermometer 13. Figure 3A illustrates an example of a graph 31 of optical power distances. Figure 3B illustrates an example of a graph 32 of optical field distances. Figures 3A and 3B illustrate peaks of a constellation min-distance function, min[d₁, d₂ ]. It is noted that it may be beneficial to set the DD and COH PAM4 generating devices happen to occur at the same phase parameter optimizer value,

, for both the DD and the COH designs. Figure 4A illustrates an example of a graph 43 of an angular constraint regions and maximin points. Figure 4B illustrates an example of a graph 42 of a min distance function. _{Five local optimizer points}

_{corresponding to each of five regions (denoted #1,#2,…,#5)} symbolic-symmetric bubble-sort algorithm iterations which happen to yield non-zero constraint regions, are shown along with the partitioning into regions for 3SE DD SEMZM, in

Figures 4A and 4B. Figure 5A illustrates an example of a graph 51 of a min distance function. Figure 5B illustrates an example of a graph 52 of min distance function. Figures 5A and 5b illustrates 3SE DD SEMZM maximin distance solutions.(left): 3SE DD SEMZM maximin distance solutions (a recap of Figures 4A and 4B, for comparison). Figure 5A - 3SE COH SEMZM Maximin solutions are seen to occur at the same phases. However, inspection of the two scales of the contour plot levels indicate that the local maximins distances (and the global maximin) of the COH case are double those of the DD case. Figure 6 illustrates PAM8 DD and COH constellations – comparison of design options. The excessive non-uniform crowding of the naïve 4:2:1 segment designs is apparent. Note the geometrical similarity of the DD and COH designs which are on different full-scales. Figure 6 includes a graph 61 of said constellations. Figure 7A illustrates an example of a S-way MPoDAC 71. Figure 7B illustrates an example of a MPoDAC based 3-way ODAC 72. Figure 7C illustrates an example of a 2-way MPoDAC 73. Figure 8A illustrates an example of a 2-bit BiWgt PAM4 COH MPoDAC 81. Figure 8B illustrates an example of MPMZM based 2bit ODAC 82. Figure 9 illustrates examples of graphs 91, 92 and 93 of a min distance function. Figure 10 illustrates an example of a graph 101 of normalized constellation distances. Figure 11 illustrates an example of a graph 111 of normalized constellation distances. Figure 12 illustrates an example of a dual-parallel ODAC 121. Figure 13 illustrates an example of a 2-bit COH PAM4 MPMZM oDAC 131. Figure 14 illustrates an example of an Optically Amplified Recirculating Phase-Gate 143. Figure 15 illustrates an example of Phase gate modulation operating characteristics 151. Figure 15 illustrates phase gate modulation operating characteristics of conventional MZM vs. OAR-PG (family of curves). When both types of PG modulators are set to -3dB modulation backoff mode, the RF drive power is reduced by 9.9dB and our OAR-PG has its drive voltage reduced by a factor of ~3 (from 0.5 down to 0.16 voltage normalized units). Figure 16 illustrates an example of a VOA-MZM 161. Figure 17 illustrates an example of a MZM-with-VOA- MZMs 162. Figure 18 illustrates an example of a VOA-MZM-based Phase-Gate or intensity gate 181. Figure 19 illustrates an example of a VOA-MZM-based Phase-Gate or intensity gate 191. Figure 20A illustrates an example of a prior art variable 2x2 optical MIMO matrix 201. Figure 20B illustrates an example of an improved variable 2x2 optical MIMO matrix 202. Figure 21 illustrates an example of an Optical Signal Processor 221. Figure 22 illustrates an example of 3:3 and 4:4 Mode Converters collectively denoted 221. Figure 23 illustrates an example of variable 1:S splitters and S:1 combiners, for S=4 and S=3 collectively denoted 231. Figure 24 illustrates an example of 3-bit BiWgt MPoDACs collectively denoted 243. Figure 25 illustrates an example of VAR 1:4 splitters collectively denoted 251. Figure 26 illustrates an example of VAR 1:5 splitters collectively denoted 261. FIGs.27A and 27B illustrate examples of tree block diagrams 271 and 272 of 1:4 splitter embodiments of Figure 26. Figure 28 illustrates an example of a Direct-Detection PAM4 constellation generator 281. Figure 29 illustrates an example of a graph 291 of min-distance function – it shows a W-U plane plot of the min-distance function. Following the contour lines, the min-distance is maximized at the bright point marked on the 45^o diagonal. This indicates that the optimum realizing W and U parameters, must be equal, i.e., it is the ‘matched-splitter-combiner’ taps that is optimal. Figure 30 illustrates an example of a graph 301 of BiWgt 2MP PAM4 DD constellations. Figure 31 illustrates an example of a 3-bit BiWgt PAM8 DD MPODAC 311. Figure 32 illustrates an example of a graph 321 of angular constraint regions and maximin points – especially 3SE DD local solutions and the global one. The six (triangular) constraint regions, each with a locally-optimal solution point therein. Note that the values of the per-region local at the 6 locally-optimal points are all either h in regions #1,#4,#6 or H in regions #2,#3,#5. (right): Contour plot of the value of the min-distance of the constellation (prior to applying the outer Max[]), as a function of W0, W1 over regions #1,#2. The contour plot verifies the validity of the locally-optimal solutions in regions #1,#2. Similar plots may be made for the other regions. Figure 33 illustrates an example of a graph 331 of angular constraint regions and maximin points. Figure 34A illustrates an example of a DD-PAM4-3MP-embedded ODAC 343. Figure 34B illustrates an example of a DD-PAM4-3MP-embedded ODAC 342. Figure 35 illustrates an example of a graph 351 of BiWgt 2MP PAM4 DD constellations. Figure 36 illustrates an example of a PAM4-DD 3MP 361. Figure 37 illustrates an example of a ThWgt 2-bit PAM4 DD 3-way MPoDAC 371. Figure 38A illustrates an example of a S-way Multi-Parallel-MPoDAC 381. Figure 38B illustrates an example of a 3-bit ODAC module 382. Figure 39 illustrates examples of Quadrature Multiplexers collectively denoted 391.Figure 40A illustrates an example of a IQ-MPoDAC QAM-2^2B generator 401. Figure 40B illustrates an example of a PDM 2xQAM-2^2B optical transmitter 402. Figure 40C illustrates an example of a PDM 2xQAM-2^2B optical transmitter 403. Figure 40D illustrates an example of modulators 404. Figure 43 illustrates an example of a 2-way PAM2|4 ML-driven reprogrammable MPoDAC 431. Figure 42 illustrates an example of a Optical monitors 421 and slow phase actuators for the control plane of the MPoDAC of Figure 43. Figure 43 illustrates an example of a Generic S-way reprogrammable ML- driven MPoDAC 431. Figure 44 illustrates an example of a 3-way realization 443 of Fig 43. Figure 45 includes an example of a table 451. Figure 46 includes an example of matrices 461. Figure 47 illustrates an example of a method 470. Figure 48 illustrates an example of a ODAC 481. There may be provided an optical unit that may include a variable optical modulator, the variable optical modulator may include an input splitter, a first optical path, a second optical path (there may be more than two optical paths and a combiner. The first optical path is formed between a first output of the input splitter and a first input of the combiner. The second optical path is formed between a second output of the input splitter and a second input of the combiner. The first optical path may include a first variable optical attenuator (VOA of figures 16 -20B), a first phase modulator and a first phase shifter; wherein the second optical path may include a second variable optical attenuator, a second phase modulator and a second phase shifter. The rate of modulation of the first and second phase modulators exceeds a phase shift rate of the first and second phase shifters. Each of the first and second variable optical attenuators may be a Mach-Zehnder-Modulator. Each Mach-Zehnder-Modulator may be an auxiliary output for providing an optical sample to a monitor. The optical unit may include a controller that is configured to determine, based on monitoring results related to the first and second variable optical attenuators, an attenuation of at least one of the first and second variable optical attenuators. The optical unit may be the variable optical modulator, a variable phase gate, may include multiple variable optical modulators, and the like. Figure 14 illustrates an optically amplified recirculating (OAR) phase gate, comprising: a first Mach-Zehnder-Modulator (MZM), a second MZM and a feedback amplifier; wherein an output of the first MZM is coupled to an input of the second MZM, wherein the feedback amplifier is coupled between an output of the second MZM and an input of the first MZM; wherein the second MZM comprises a phase modulator. The first MZM may include an additional input for receiving an input signal; wherein the second MZM comprises another output for outputting an output signal of the OAR. The feedback amplifier may be a semiconductor optical amplifier (SOA) that has an input coupled to the output of the second MZM and an output coupled to the input of the first MZM. Each one of the first MZM and the second MZM may include a phase shifter. The first MZM may include an additional output for providing an optical sample to a monitor. Figure 14 may include an optical processor that may include a sequence of units that comprises an input unit, one or more intermediate units and an output unit; wherein the input unit and each intermediate unit comprises a first variable optical attenuator followed by a first phase modulator and a second variable attenuator followed by a second phase modulator; wherein each intermediate unit comprises an input splitter that precedes the first variable optical attenuator and the second variable optical attenuator; wherein the output unit comprises a combiner that is followed by a pair of phase modulators. The optical processor may be configured to perform endless phase shifting without reset. At least some of the units may include one or more additional outputs for providing one or more optical samples to one or more monitors. There may be provided an optical digital to analog converter (oDAC) that may include multiple optical paths that are parallel to each other; a combiner that may include multiple combiner inputs and a combiner output; and a splitter that is configured to receive an optical signal at a splitter input and split the optical signal between multiple splitter outputs to provide multiple path input signals to the multiple optical paths; wherein the multiple optical paths are formed between the multiple splitter outputs and the multiple combiner inputs. The multiple optical paths are configured to optically process, in parallel, path input signals to provide path output signals; wherein each optical path is configured to apply an optical process that comprises applying optical modulation, by an optical gate of the optical path and under a control of an electrical modulator, to provide an optical signal having a value selected out of multiple constellation levels. The multiple optical paths may be configured to output multiple path output signals to the multiple combiner inputs. The combiner may be configured to add the multiple path output signals to provide an oDAC output signal having a value selected out of values of a single quadrature constellation. The optical process applied by each optical path may be a single quadrature optical process. Electronic Digital to Analog Converters (eDAC), are key interfaces from the digital to the analog domains. In optical transmitters generating multilevel constellations an optical modulator is preceded by an eDAC. It is advantageous to use Optical Digital to Analog Converters, which do not require eDACs in order to convert a digital bitstream into a multilevel optical signal, e.g. PAM or QAM. The prevalent state-of-the-art oDAC for optical PAM-2^B generation is essentially a Segmented Mach Zehnder Modulator (SEMZM), wherein multiple modulation segments are strung together alongside a pair of optical waveguides. A different prior art structure brings together two modulated parallel 1-bit modulators for PAM4 generation for direct-detection. Here we optimize certain low order SEMZM structures showing that improved performance may be extracted out of them. We then proceed to generalize the aforementioned oDAC structure with two parallel modulated paths, in terms of allowing for an arbitrary number of paths for constellations of higher-order than PAM4, allowing for coherent-detection, and operating the disclosed Multi-Parallel oDACs (MPoDAC) as chirp-free. There is provided opto-electronic devices (as well as perfecting state-of-the-art devices), directly driven by digital bitstreams structured as binary codewords, to be directly mapped onto discrete levels of optical power or complex optical field. Such devices, referred to here as optical Digital-to-Analog Converters (oDAC), would amount to optical constellation generators. Driven by binary codewords, with their constituent bits mapped into two-level voltage waveforms, an oDAC directly generates a multi-level optical signal, assuming values in a set of discrete powers (for optical direct detection) or optical complex amplitudes (for optical coherent detection). An optical constellation generator may eliminate the intermediary eDACs altogether – and according to one embodiment - directly use digital binary driver arrays, preferably implemented as state-of-the-art CMOS low voltage swings. We also aim to eliminate or at least minimize, inside the oDAC, additional power-intensive high-speed digital hardware mappers or encoders. It is would be most advantageous to be able to apply the individual bits of the incoming codewords directly to an array of elementary 1-bit modulators comprised in the oDAC – a trait referred to here as Direct Binary Drive. According to another embodiment the digital binary driver arrays are replaced by multi-bit driver arrays. Figure 1 illustrates oDAC alternatives for PAM8 generation (for either direct-detection or coherent- detection: (a): Prior-art Segmented Modulator (SEMZM) with 8 segments 11.(b): MPMZM oDAC 12 as disclosed in this work. Optical Digital to Analog Converter (oDAC) - constellation generator Henceforth in this work the term ‘constellation’ means an optical one-dimensional (1D) constellation, i.e. a collection of points along the real-axis, corresponding to real-time values referred to as ‘constellation levels’, specified either in the optical field domain or in the optical power domain (the square of the field amplitude, thus the power constellations are non-negative, while the field constellations are typically bipolar – have both signs – when used for coherent-detection). There may be provided three main oDAC architecture types: (i) Serial (SE) structure: combining two or more gates in tandem, typically using phase gates in order to additively superpose their phase contributions along the serial optical path). The linear superposition optical phase DOFs is usually translated by means of optical interference to optical amplitude. The SEMZM belongs to this class of structures. (ii) Multi-Parallel (MP) structure: combining the outputs of two or more optical gates in parallel, with their output terminated in a passive optical combiner device to optically interfere (superpose) the output fields of the individual gates. The MPoDAC structures disclosed in this work are of this type. The optical binary DOFs being combined here are the optical fields (even when the MPoDAC is intended for DD), and the additive combination is linear superposition of fields (we avoid very high optical power and special optical materials which may elicit nonlinearity). (iii) Combinations thereof, e.g. MP combinations of SE structures; or compound recursive structures in which MP structures are again MP combined; or MP combinations of MP combinations of SE structures. Different examples provide constellations of different parameters – for example constellations of different order or size of the constellation (be it 1D or 2D, DD or COH) is defined as the number of constellation output levels, C, which is also the size (code length) of the ‘oDAC code’, defined as the collection of binary codewords used to drive the individual single-bit DOFs – the optical gates. Another key parameter is the number S of single-bit DOFs (optical gates). Thus each codeword comprises S bits (one drive bit per gate). These two numbers, C and S, are related as described below. In this work we are interested in dyadic-sized oDAC constellations (‘dyadic’ meaning integer powers of two):

Then

is an integer denoting the intrinsic number of bits needed to specify the code size, C in binary notation. Note: B=1 is not interesting oDAC in itself, that is a single-bit modulator. The B-count starts from 2, i.e.4-level, 8-level, etc.. Equivalently, B is the size in bits of a digital pointer (a B-bits bitstring) specifying the address of each of the C codewords in the code table. Here the ‘code table’ is defined as the set of the C codewords driving the oDAC 1-bit modulator array. Each codeword is of size S bits, i.e. we have S 1-bit gates (each of the S bits of the codeword drives one of these S gates), but the codeword address requires B bits to specify (as there C=2^B distinct codewords, each of length S bits). In fact, the code table may be viewed as an C × S = 2 ^B × S matrix, B, having Boolean values (‘bits’) as elements. The row index c=1,2,…,C-1, selects a codeword, while the column index, s=1,2,…,S selects a bit within the codeword, driving the s- th 1-bit gate. The ‘bits’ of the code table or code matrix, are either {0,1} for DD oDACs or {±1} for COH oDACs. The digital electrical input of the oDAC consists of B digital lines each carrying a single bit, to form a length-B bitstring forming the integer index, c, an address pointing to one of the C=2^B digital codewords which are stored in the code table, each of length S-bits. The number of bits in each codeword, S, is equal to or larger than the number of bits in the address of the codeword, i.e. we always have B ≤ S . Evidently, we also have C = 2 ^B > S i.e., the code matrix, B is either square or ‘tall’. The digital circuit in the oDAC electrical front-end, digitally generating the code (storing the code table or synthesizing it in digital logic), is referred to here B:S encoder or as B-bits:S-bits mapper. Actually, an oDAC may operate without a B.S encoder, provided that S=B. In this special case, conceptually, the address of the codeword is actually written in the bits of the codeword. The code table consists of the bits of the binary representations of each of the successive2^fi numerals, c 6 {0,1,2, . . . , C — 1} = {0,1,2, . . . , 2^B — 1}, labeling the codewords and the oDAC levels, as each codeword applied to the 1 -bit gates array elicits a particular level of the C-levels constellation. The condition S=B, implies that the number S of 1 -bit modulating gates, each corresponding to the number additive DOFs of the oDAC, equals the number of input bits, B = log2 C, presented in parallel at the oDAC input Hardware-wise, each incoming B -bit input word packet presented on the B input digital lines is just routed to drive the respective S=B 1 -bits gates of the oDAC structure. There is no need for addition HW (the B:S encoder) as now we just drive the 1 -bit gates by the input binary lines

This leads us to yet another classification of oDACs in terms of the relation between the number of input bits, B (equal to log ₂of the constellation size or of the code size), vs the number of bits S driving the oDAC additive DOFs (via S gates):

(A) An oDAC with B=S just described, not requiring a B.S encoder, as the B input bits are directly applied to drive the same number of 1 -bit optical gates, will be henceforth referred to as “Binary Weighted” (BiWgt) oDAC. This type of drive referred to here as “direct binary drive” (or “direct digital driving” in the terminology used in [17][ 18]) Its advantage is that that the opto-electronics is least complex, as the number of parallel paths is the least. Its disadvantage is that the oDAC linearity may be impaired - the constellation gets are crowded and distorted when fewer bits are available.

(B) An oDAC with S B requires a B.S encoder, which turns out to be a non-negligible source of energy consumption and is better avoided. Nevertheless, adding additive DOFs redundancy, i.e. increasing the number S of additive DOFs, beyond the minimal number B required to specify the distinct codewords in the code table, has the general effect of improving oDAC linearity, i.e., getting a higher-quality constellation. Thus, a tradeoff is set up between constellation quality (attained higher S), at the expense of accompanying increased complexity and power consumption increase, stemming from having more 1 -bit gates and requiring the B.S encoder, which is power-hungry at high-speed (in fact, already as soon as S=B+1, a digital encoder is needed).

It is then seen that B = log₂ C is a lower bound for S (one cannot uniquely specify any codeword out of the size C = 2^B code without having at least B bits in the codeword pointer. But redundant bits are allowed and will be seen to be beneficial in reducing nonlinear distortion (enabling the constellation to be closer to equi-spaced). The question is whether there is an upper limit to be imposed on S. It may be proven that it is senseless to use more than S — C — 1 = 2^B — 1 1 -bit gates. This indicates yet another member of the oDACs classification above, based on the relation between oDAC input bits and oDAC gate-bits: (C) The extreme case S = 2^B − 1still requiring a B:S encoder, but enjoying best performance and most flexibility, will be referred to as “Thermometer-Weighted” (ThWgt) oDAC. This case will be shown to lead to complete removal of intrinsic constellation nonlinear distortion, be intrinsically loss- free (i.e. stretch its constellation over the max-full-scale) and enable synthezing an arbitrarily specified target field-domain or power-domain constellation, in particular an equi-spaced max-full-scale one (but any desired non-equi-spaced constellation is also also synthesizable) . The cost to be incurred in exchange of these benefits of the ThWgt design is that for larger sized oDACs the large size of S (as S now depends nearly exponentially on the number of bits, B) require a sharp increase (approximately exponential in B, especially for larger B) in opto-electronic complexity and footprint, excess power consumption in the B:S encoder and in the oDAC photonic circuit with its high number of 1-bit drivers for the gates, cross-talk between the multiple RF lines, timing skews, and additional impairments. Therefore, we deem the ThWgt option as undesirable with the exception of the lowest constellation size, C=4, B=2, i.e. PAM4. SEMZM- Segmented Mach-Zehnder Modulators (SEMZM) To reduce and ultimately avoid loss of performance due to non-linear distortion and intrinsic loss, there may be provided a SEMZM with more that the common number of segments – we need to add in more segments, resort to non-BiWgt SEMZMs with S>B, but then we require a digital B:S encoder which at ultra-high-speed is power hungry, the more so the higher S is. But the higher S is, the lower the nonlinear distortion. At the other extreme, when S is increased up to 2^B-1, we may design the SEMZM as a ThWgt oDAC (akin to a thermometer-coded eDAC), providing ideally distortion-free performance. It was found that a ThWgt segmented MZM should not be possibly run “all-optically”, since a power- hungry Bbits:Sbits encoder (mapper) digital circuit at ultra-high bitrate must necessarily be included to match the input B-bit binary word to S binary signals to drive the electrode segments (we note that in an electronic DAC the mapper accounts for about half the power consumption). Ideally, a segmented electrode Mach-Zehnder Modulator (SEMZM) should paired up with a dedicated driver IC to generate multi-level optical signals from multiple binary electrical drive signals, using only binary signals from the driver array, a feature we referred to as Direct Binary Drive, but this throws us back to the other extreme, the BiWgt oDAC, which was seen to feature intrinsic loss and high nonlinearity. In addition – it should be beneficial to have chirp-free SEMZMs, i.e. the transmission phase does not vary from one transmitted constellation symbol to the next, as this would cause excessive Inter-Symbol- Interference. Figure 2 depicts an exemplary S=8 segment ThWg SEMZM optical structure 13, aiming to implement oDAC functionality. The contiguous MZM electrodes are partitioned into S segments. Each segment acts a “partial MZM” with push-pull drive, having its upper and lower electrodes driven by a pair of (variable) voltages preferably antipodal voltages (as shown below). When all the segments are modulated in unison, driven by properly synchronized binary signals, the total differential phase along the device may assume multiple values, inducing by interference in the output coupler multiple optical levels at the device output. Each level is determined by the combination of polarities of voltages applied to the various segments, as detailed below. Figure 2 illustrates a segmented MZM (SEMZM) with seven segments oDAC architecture - optimized Thermometer-Weighted (ThWgt) DAC structure -the seven electrode segment lengths are shown to scale for ThWgt SEMZM operation - the guard spaces between segments not shown to scale. Multi-Parallel MZM (MP-MZM) based oDAC – structure and operation It has been found that in order to construct an oDAC as eDAC direct analogue, linear superposition of weighted bits in oDAC ought to inherently occur in the optical field domain. Based on this insight, we propose a new Multi-Parallel-oDAC (MPoDAC) structure, capable of all-optically synthesizing a 2^S-PAM constellation based on a parallel array of S MZMs or more generally of S 1-bit optical gates (to be defined further below). In this proposed structure, the inherent sine nonlinearity of the MZM is bypassed by superposing binary weighted bits linearly (and in phase) in the optical field domain, using each MZM as the source of a single “optical bit”. The proposed field domain superposition paradigm holds for two types of variants we propose, namely Coherent (COH) MPoDAC (i.e., constellation generator for coherent detection), and Direct-Detection (DD) MPoDAC (i.e., constellation generator for direct-detection). In both cases we focus for design purposes of the target constellation formulated in the field domain, and evidently the COH and DD field-domain constellations differ even for a specified number of constellation levels (the DD field constellation, upon having its levels squared should yield the target power-domain DD constellation). Our most general disclosed S-way Multi-Parallel optical DAC (MPoDAC) structure (for the generation of both DD and COH constellations) comprises S parallel paths ( ^^^^ ≥ 2) each containing a 1-bit gate (see Fig.7A). The S parallel paths are sandwiched between a 1:S optical splitter and an S:1 optical combiner. Light is split by the 1:S to feed the S parallel paths, each of which are 1-bit modulated and then coherently (in phase) superposed in the optical combiner to generate a single useful output beam (excess light may emerge and be terminated at other ports of the combiner). In addition to the 1-bit gates which are inserted in all S paths, at least S-1 of the paths also contain slow phase modulation means to bring and maintain all optical fields in-phase at the internal point of superposition in the optical combiner. Moreover, means are to be provided to tune (optimize) the paths phase shifts to achieve coherent in-phase superposition of the 1-bit-gated paths (as it occurs in the output optical combiner). In addition, the 1:S splitting ratio and S:1 combining ratio, referred to as ‘taps’, should be accurately set (if the splitter or combiner is fixed) or be actuated to be stabilized, maintained at target values (if the splitter or combiner has adjustable, tunable taps). The target output constellation uniquely determines the tap values to be instilled in the devices. For example, for the generation of a PAM8 COH constellation, the taps should be in ratios 4:2:1). Fortunately, the environmental disturbances affecting the stability of the taps are slow (sub-Hz to KHz order of magnitude) thus, the stabilization may be performed by low-bandwidth electronics and control algorithms. The 1-bit gates shown in Figure 7A are implemented in our preferred embodiments as 1-bit BPSK modulators (referred to here as Phase-Gates (PG)) in COH MPoDACs, or as 1-bit OOK modulators (referred to here as Intensity-Gates (IG)) in DD MPoDACs. As elaborated in 5.1, both PGs and IGs may be implemented as MZMs (with different voltage drives in the two cases). When the 1-bit gates in Fig.7A are realized as MZMs, the MPoDAC is referred to as Multi-Parallel MZM (MPMZM). Two embodiments of MPMZMs are shown in Fig.7A and Fig.7B for S=3 parallel paths and S=2 paths, parallel respectively. Each parallel path now comprises an MZM to be used as PG or IG (for COH or DD). These exemplary cases of S=3 and S=2 shown in Fig.7(b,c), illustrates the features of the most general structure with S paths, except that in these special case there are three and two parallel paths, respectively. In Fig.7B the optical fan-out is performed by a 1:3 (1:2) splitter while the optical fan-in is performed by a 3:1 (2:1) combiner, respectively. The slow PMs (also referred to as phase shifters) for tuning the phase of each paths are not explicitly shown. Note: It is also possible to apply a common mode voltage inside each MZM, to effect the slow PM functionality. In addition to tuning the slow phases of the parallel paths, the coherent fan-out/fan-in technology for slow (typically ~kHz rate) precise tuning of split /combine ratios and phase alignments and appropriate control are evidently essential enablers for this multi-parallel oDAC architecture. The 1:S and S:1 may be realized on a SiP platform as meshes of slow thermo-optic (TO) MZMs and PMs, as elaborated in 5.4.2.3. In such splitter/combiner structures, the taps tuning is implemented by the tuning of the control phases of the constituent MZMs and PMs forming the splitter and combiner (the internals of the 1:S and S:1 are not shown in the figure) . Our MPoDAC structure, as disclosed above, functioning as constellation generator in the optical transmitter, may be parameterized to achieve two types of reception functionality: coherent detection (COH) for direct detection (DD). As already mentioned, these two classes may require similar photonic structures, differing just in the nature of their parallelized 1-bit gates building blocks (BB) and also differing in their split and combine parameter settings and their ancillary electronics: the type of binary voltage drives for the respective 1-bit gates. There may also be differences in the implementation of the control and calibration systems, but in both cases the general objective is to stabilize the relative phases of the paths for in-phase coherent combination in the S:1 combiner, and to accurately set the splitter and combiner taps to their target values (which values may be differ in the DD and COH cases). In terms of the 1-bit gates, the COH MPoDAC uses Phase-Gates (PG), whereas the DD MPoDAC uses Intensity- Gates (IG). The two types of gates are elaborated below, but we show that our gate embodiment is based on a simple MZM for both the PG and the IG (albeit with different voltage drives in the two cases). An MPoDAC (be it DD or COH), wherein the 1-bit gates are implemented as simple MZM is henceforth referred to as Multi-Parallel MZM (MPMZM) – this is our novel counterpart to the prior art SEMZM, adopting the multi-parallel structure rather than the prior serial structure. Having specified the optical architecture just above, we must recall that the MPoDACs are integrated electro-optical devices, not just photonic ones. We reiterate the ancillary electrical subsystems which are further required: the electronic drives for the fast (1-bit gates), the slow electro-optical controls (including sensing means such as monitor photodiodes and TIAs) for the phase shifters and the slow internal modulation constituents of the tunable splitters and/or combiners, as well as control and calibration analog and digital subsystems for all slow modulations just mentioned. The splitting and/or the combining ratios may be either tunable or fixed (tunable splitter/combiner embodiments may be more optimally set and stabilized, fixed embodiments are easier to fabricated but may be less accurately set and maintained over environmental disturbances). Some preferred embodiments will use a fixed splitter (or combiner) and a tunable combiner (or splitter), respective. The S-way MPoDAC parameters design aims for the determination of the optimal splitting and combining ratios to achieve a given target constellation; The novel methodology for such parameter designs, their optimization and multiple embodiments of MPoDACs based on the optimized parameters is an important enabling disclosure, elaborated in the sequel. In the primary MPoDAC architecture disclosed above, the number of parallel paths each comprising a 1-bit gate, equals the number of paths, S. Yet another variant of MPoDAC, which we disclose for DD applications removes the 1-bit gate(s) from at least one of the paths (but evidently not from all the paths; at least two paths must retain their 1-bit gates, else the light would not be modulated at all or would not be multilevel-modulated). This modification is called “constellation embedding” for reasons that will become apparent once we disclose embodiments of DD MPoDACs of this type. Thus, an S- way MPoDAC with embedding operates with S-1 gating degrees of freedom (but at least a pair of 1-bit modulation degrees of freedom is retained). 1-bit Gates building blocks specified: Phase Gates (PG) and Intensity Gates (IG) The 1-bit gates are taken as Phase-Gate (PG) BBs, may be defined as chirp-free Binary-Phase-Shift Keying (BPSK) modulators. In the DD case, the 1-bit gates may be Intensity-Gate (IG) BBs, defined either as On-Off-Keying (OOK) or Amplitude Shift Keying (ASK) modulator structures, which should also be chirp-free, as elaborated below. For COH MPoDACs the generic 1-bit gates are taken as phase-gates. These are the MP-oDAC broadband phase-switching elements, needed in each of the S parallel paths. A Phase-Gate (PG) is defined here as a ‘bi-phase’ optical modulator, emitting optical field ± E ₀ (0^°/180^° phase transitions, maintaining constant envelope, ideally, when driven by a bipolar ± V ₀ -valued NRZ input waveform (which in practice does not switch instantaneously between the two bipolar levels but experiences amplitude transition ‘notches’ around the instants of NRZ polarity switching). In the jargon of coherent optical communication, the PG amounts to a Binary Phase Shift Keying (BPSK) modulator – known as a ‘workhorse’ of coherent transmission. An intensity gate is essentially an OOK modulator. When intensity gates are provided in the MPoDAC parallel paths, the light is either let through or blocked. Two main technology candidates for realizing OOK switching are Electro-Absorption Modulation (EAM) and MZM. Chirp-free MPoDAC is based on chirp-free 1-bit phase and intensity gates A Phase-Gate (PG)may be a bi-phase (BPSK) modulator, switching the phase of the optical field between two levels in the phase-domain, which are π radians apart (e.g., between 0 phase, i.e. positive field , E ₀ > 0 and 180^o (or -180^o which is the same) phase, i.e. negative antipodal field − E ₀ < 0 . We impose on our PGs (to be used as BBs in our MPoDACs) the chirp-free requirement that biphase generation be chirp-free, i.e. ideally not be accompanied by time-varying phase modulation (apart from abrupt, discontinuous phase jumps of 180^o stemming from the sign change of the optical field undergoing a zero-crossings, which is inherent to field sign switching). The alternative realizations of the PG may include: (i) A Mach-Zehnder Modulator (driven to switch between two states on both sides of its null output point). (ii) Optically Amplified Recirculating Phase Gate (OAR-PG) – disclosed embodiment (see 5.4.1). Electro-optic driver implementation options for the MZM-based chirp-free phase-gates As each of the two capacitors around the top and bottom phase-modulation waveguides of the MZM has two electrodes or ‘plates’ (on either side of each waveguide) thus a full-specification of the voltage driving sub-system should list all four plate potentials (first pair of plates for top, 2^nd pair of electrodes for bottom).

We may electrically short out the lower-top and upper-bottom plates, having them form a common inner ‘mid-electrode’ in between the two waveguides, so there are three electrodes, effectively. In the GSGdesign, the outer electrodes are always grounded (G), whereas the mid electrode is active (S). In the SSSdesign, the outer electrodes S are at any instance antipodal (opposite in sign) to the inner electrode, 5.

In the GSG design the inner mid-electrode is driven by the

(denoted “S”) whereas outer top-upper plate and the bottom-lower plates are at ground (null) potential, V_top_(t) = Vbot+(0 = 0 (denoted “G”).

In the SSSdesign, the “outer” top-upper plate and and the bottom-lower plates are driven by

whereas the inner mid-electrode is driven by the —

signa

A variant of the GSGdesign is the SGSdesign whereby the driven electrodes are now the outer ones (both driven by the “S” signal) whereas the inner common electrode is grounded now: unipolar sub-embodiment of PG drives 'SGS':

Thus, for multiple PGs inserted in the paths of our disclosed COH MPoDACs, we may then use either one of the alternative drives GSG, SSS with a preference to SSS when high peak high speed electrical potentials are hard to generate

MPoDAC parameters

Let the S; 1 splitter have field splitting coefficients (referred to as taps) assumed real (as

their phases area lumped with the path phase factors) , and accordingly power splitting taps (splitter power ratios) The combiner respective real-valued field combining and

power combining taps (combiner power ratios) are denoted

We assume that the following ‘unitarity constraints’ hold i.e. the splitter and combiner are effectively lossless.

It should be noted that the multilevel generation action of the MPoDAC is based on applying various suitable bitstrings to the array of S 1 -bit gates, one bitstring for each output level. These bitstring are called the ‘codewords’, and their collection is referred to as the oDAC ‘code’. To distinguish the C codewords (C being the code size or code order), let us label them by an index,

such that the c-th codeword (when represented as row vector) is denoted as follows

with the S individual bits also labelled by the codeword index, c (note that the bits are labeled from right to left with the LSB bit on the extreme right and the MSB bit on the extreme left). Thus, the codewords are S-bit strings and there are C of them. The DD codewords are then {0,1}-bitstrings of length S, while the COH codewords are {-1,+1}- bitstrings of length S. The codeword index, c, also labels the field level, generated when the c-th codeword is applied,

now written:

where in the last equality we expressed the field split and combine taps in terms of the corresponding power taps:

Lets assume that the splitter taps respectively equal the combiner taps. This is called “matched” design (in the sense that the combiner is matched to the splitter like a matched filter in MIMO theory): m^{atched taps design:}

The c-th field level now assumes the simple form of an inner product

of the c-th codeword, b [ c ], with the taps vector, W ,

In the elements of these vectors we reversed of the order of increasing indexes, in order to have the elements correspond to the ordering of the bits from LSB (rightmost) to MSB (leftmost ) in the codewords. The field levels may be a linear functional the power splitting (power combining ratios) taps, and may be compactly represented as a linear transformation of the power taps vector W into an optical field levels vector (alternatively called the constellation vector), where

we dropped the ‘matched’ label for brevity. This linear transformation may be written as a matrix- vector multiplication, using a [ C × S ]’code matrix’, B ,collecting the codewords in its rows, i.e. the c-th row of B is b ^T [ c ] , namely the c-th codeword - a binary string of S bits: F = BW The three integer parameters characterising any novel MPoDAC design are C,B,S. C was defined as the code length, i.e. the number of digital codewords and also the number of output optical levels (assumed dyadic – an integer power-of-two, C = 2 ^B ). C is also the vertical dimension of the B matrix, having the codewords as rows. ^^^^is defined as B ≡ log ₂ , i.e., the minimum number of bits required to uniquely label all codewords in the code by binary-valued B-tuples. Thus, evidently, B < C = 2 ^B , B = 1,2,3, ... , C = 2,4,8, .... ^^^^ is defined as the number of binary-modulated Optical Degrees of Freedom (DOF) participating in generating the oDAC code, be it the number of serial MZM segments in the SEMZM oDAC (equal to the length of segment phases vector, Φ ) , or the number of parallel paths in the MPoDAC. In particular, for MPoDACs, S is also the length of the matched split/combine taps vector, W . S is also the number of bits (each associated with a binary-modulated optical DOF) participating in each codeword, i.e. the length of each codeword (also equal to the horizontal dimension of the B matrix). The three parameters, B, S, C may satisfy the following order relations:

Note: In an eDAC, S would equivalently represent the number of electrical additive binary DOFs (corresponding to switch current or voltage sources or switched resistances) to be internally added up upon forming the DAC analog output. Here the electrical additive DOFs are replaced by optical additive DOFs, be they optical phases for the SEMZM or optical fields for the MPMZM. We shall see that a tradeoff exists between complexity and energy-efficiency, favoring lower S, on one hand, vs. oDAC linearity, i.e., lower-nonlinear distortion as well as optical insertion loss favoring higher S, on the other hand. In particular, the following two extremes of the range of feasible S values are of special interest. At the lowest-S extreme, S=B attains the least electro-optic complexity and lowest electrical power dissipation, often at the expense of nonlinear distortion and higher optical power loss. This design is referred to as Binary Weighted (BiWgt). The BiWg is the simplest to realize. To see this note that the “user” input into any DAC (be it eDAC or oDAC) is to be presented as a B-bit binary word, one of C = 2 ^B B-bit binary strings, uniquely inducing generation of one of C = 2 ^B analog levels at the DAC output. However, when S>B, the oDAC (or eDAC) must internally comprise an electronic B-bits:S-bits digital encoder, one-to-one mapping the C = 2 ^B user-input labels (each consisting of B-bit strings), into C = 2 ^B codewords (each consisting of S-bit strings (with S ≥ B ) to be applied to the S optical binary additive DOFs internally used in the oDAC (be they serial segments or parallel paths) in order to generate one of C = 2 ^B codewords, each of length S>B, which are seen to form a subset of the full set of 2 ^S S-bit-strings (as we have 2 ^B < 2 ^S whenever B<S). It is this judiciously selected subset of codewords, out of all possible ones, that constitutes the oDAC code. One design decision is to select the oDAC code, which is non-trivial. But or a BiWgt oDAC we have S=B, thus, the BiWgt code consists of all possible 2 ^B B-bit strings. At the highest-S extreme, S=C-1 it is in principle possible to have the oDAC operate intrinsically distortion-free and optical modulation-loss-free operation. This may be achieved by means of the so- called Thermometer-Weighted (ThWgt) design, which is well known for eDACs. Here we shall propose the counterpart of that design, albeit for MPoDACs. The problem with the ThWgt (especially for designs featuring oDAC code orders or number of bits, B), be it for segmented or multi-parallel oDACs, is that its nice distortion-free and optical-loss-free desirable intrinsic qualities are attained at the expense of highest complexity and highest energy-inefficiency (and the complexity brings along with it additional performance impairments), the more so the higher the number of bits (or levels) of the DAC (be it eDAC or oDAC of the SEMZM or MPoDAC type). In between the two extreme cases, i.e. when we have B < S < C − 1 , we may tune S up or down to have a variable tradeoff between low complexity and low power on one hand vs. low-nonlinearity and low-optical loss on the other hand. Besides having more segments (for SEMZM) or more parallel paths (for MPoDAC), which increases power consumption of the electrical drivers proportionally to S, an additional effect is that for S exceeding B (even by one unit, i.e. for S satisfying B + 1 ≤ S ≤ C − 2 ) a digital encoder is needed (only the extreme case S=B, i.e. the BiWgt design is digital encoder free, a quality we referred to as “Direct Binary Drive” (DBD) quality, as the individual S=B segments may be driven (almost) directly from the B binary signals entering the oDAC input (we say ‘almost’ since unipolar to bipolar voltage mapping and electrical analog amplification might be optionally needed. However, for low- V _π modulation segments (in the SEMZM case) or phase-gates (in the MPoDAC case), we might be able to drive the single-bit optical DOFs directly from CMOS logic levels. As for the digital B:S encoder (B bits to S bits encoder, needed whenever B + 1 ≤ S ), its power consumption rapidly increases with increasing S (since as B is increased, S increases almost exponentially starting from B up to 2 ^B − 1 . The complexity and power consumption roughly increase at least by this factor. Direct-Detection (DD) vs Coherent (COH) S-way MPoDACs – linear models The MPoDAC design parameters are the oDAC codewords and the split tap vectors:

Let us recap the linear equations derived above for generally unmatched taps ( U ≠ W ), and for matched taps ( U = W ):

matched:

with B a CxS matrix the rows of which are

These linear models actually apply to both DD as well as COH MPoDACs. However, a key distinction between the DD and COH cases is in the domain of definition of the 1D target constellation. COH constellations are stated in the optical field domain, whereas DD constellations are stated in the optical power domain (the square of the field). Thus, a COH constellation is denoted by the field constellation vector with its elements being the optical field levels, whereas a DD

constellation is denoted by the power constellation vector with its elements

being the optical power levels. The DD MPoDACs we disclose here are still coherent optical devices, and considering the optical fields underlying target optical power levels is essential for the design. A^{ssociated with the DD power constellation vector there is a DD field vector, F DD =}

_{, with the two DD power and DD field constellations in a quadratic relation:}

Thus, for the purpose of DD design, the specified target power-domain constellation, P ^DD, should be mapped back to the optical field domain, as the MPoDAC intrinsically functions coherently, interfering parallel optical paths linearly in optical field. Thus, designing for a DD power constellation P ^DDamounts to using for an effective field constellation

For a target DD constellation (in the power domain) P ^DD, using the “unipolar” ({0,1} valued) DD code,

the following linear equations hold for the MPoDAC taps:

These are then the linear equations applicable for DD MPoDACs (unmatched and matched). For COH oDACs we may still use (217) or (218), wherein we might as well label all quantities by the COH superscript. For coherent detection (COH), for which it suffices that we primarily consider the BiWgt MPoDAC, which are of special interest in the COH case. For given (dyadic) code size, they have the lowest number of paths, S=B, thus are the least complex and most energy efficient (and least affected by various other impairments). The BiWgt COH MPoDACs are capable of ideally losslessly synthesizing at desired symmetric max-full-scale field domain constellation. In particular “perfect” equi-spaced max-full-scale constellations may be synthesized by COH MPoDACs. The ThWgt MPoDAC need not be considered for COH, since, fortunately, the BiWgt COH B-way MPoDAC is capable of generating inherently “perfect” max-full-scale equi-spaced COH PAM-2^B constellations, as shown in this subsection. Moreover, for the generation of a given C=2^B number of levels, MPoDAC with least number of paths is the BiWgt one, with just S=B paths, thus it is the least complex and has the highest energy efficiency, whereas all other MPoDAC types require more paths (S>B) thus are more complex than the BiWgt MPoDAC. Thus, it is not worth considering any other type of MPoDAC besides the Biwgt one, which is the simplest and best performance one. We have seen that B is the intrinsic number of bits, i.e. the base-2 log of the number of constellation levels, C. For the B-bits BiWgt COH MPoDACs we have B paths, 1:B splitter fan-out, B:1 combiner fan-in, and in this case required 1-bit gates are of gates – in a preferred implementation of the MPMZM COH MPoDAC the phase-gates are MZM-based. The MPoDAC transfer factor depends on the (quasi-)static settings of the 1:B splitter and the B:1 combiner. We denote by the power tap vectors - the field transfer

factors through the splitter and combiner. For BiWgt B-bits MPoDACs the code matrices are 2 ^B × B sized. We derive some specific properties (unique to the BiWgt case) of the BiWgt MPoDAC with matched-taps. We recall that the matrix equations in the COH and DD respective cases are:

For the B ^DD|COHcode matrix (with DD|COHmeaning DD or COH), the rows

of the code matrices, i.e., the codewords, consist of all possible B-bit binary bitstrings ( C = 2 ^B of them). In this respect, the sole difference between DD and COH codes is in the two values assumed by each “bit” of the code. For DD, the bits are {0,1}-valued whereas for COH they are ±1-valued. Let us separately treat the properties of the solutions for the DD and COH BiWgt cases in the following subsections, showing that the properties in the COH case may be derived from those of the DD. BiWgt COH MPoDAC as perfect equi-spaced constellations generator The next two subsections disclose two examples of BiWgt B-bit COH MPoDAC designs, the first one for equi-spaced max-full-scale constellations, while the second preferred solutions trades some performance for design simplicity and robustness. BiWgt B-bit COH MPoDAC with matched taps - equi-spaced max-full-scale constellation We now disclose our first preferred BiWgt COH MPoDAC design with ‘matched-split-combine taps’, (i.e. using identical tap vectors for the splitter and combiner: , optimizing the

field transfer factor over the vector ^^^^of B matched tap parameters in order to inherently (i.e., ideally losslessly ) generate a “perfect” equi-spaced max-full-scale C=2^B level constellation. In this case the output field levels are:

The COH codewords may be readily generated by first writing down the DD “binary counting codes” and affine mapping these DD codes by the substitution 0 ^-1. E.g., for the BiWgt 3-bit DD MPoDAC, ( B^{=3, C=8) we use the following DD code:}

T^{he resulting BiWgt COH code is}

Collecting all the resulting DD field levels in a vector (i.e., a finite sequence)

Thus this DD field domain constellation, which we may synthesize using the DD ({0,1}-valued) BiWgt codewords, is evidently a perfect equi-spaced max-full-scale DD one, over the FS range [0,1]. Note that we are usually interested in equi-spaced DD constellation in the power-domain rather than the field domain, e.g. PAM8:

The COH MPoDAC embodiment for B-bit (COH PAM-2^B) constellation generation, is based on using the photonic structure of Fig.7A with S=B paths, setting the slow phases in the B paths to be all equal (i.e. ensure coherent “in-phase” addition of all paths in the optical combiner), then tuning the splitter and combiner to assume the dyadic power splitting taps (i.e. have the ratio of the power split and power combine tap values to be forming a geometric sequence 2 ^{B −1}: ... ,4: 2: 1 and have the splitting and combining taps be matched, i.e. be equal for each of the paths in turn. Then apply the COH code to the device by driving the B phase-gates with bipolar voltages ensuring chirp-free operation. Each of the C=2^B codewords of the oDAC code elicits a particular output field level of the COH PAM-2^B constellation. When the MPoDAC is realized with bipolar driven MZM phase gates we refer to it as MPMZM. The phase gates (BPSK modulators) are realized as MZM modulators driven by

antipodal voltages corresponding to the codewords (e.g. for a B=3, PAM8 generator, we have 3 paths and the three MZMs in the paths will be driven by the following 8 triplets – which the triplets ideally generating the successive equi-spaced levels of the field constellation:

For minimizing the modulation loss, the peak drive voltage should be taken as ,i.e., each MZM

be driven we have backoff – the constellation still comes out equispaced, but the

full scale shrinks down by a factor equal to

BiWgt B-bit COH MPoDAC with uniform fixed splitter or combiner for equi-spaced constellation A second MPoDAC design disclosed here gains in simplicity and robustness at the expense of giving up some performance (incurring some inherent loss). This design simply takes the splitter as fixed, uniform, with all its taps equal (thus have equal splitting ratios

then proceeding to optimize the combining taps, U . Conversely, it is possible to take the

combiner as fixed, uniform, with all its taps equal (thus have equal combining ratios

but then optimize over the splitting taps, W .

The performance in the two cases is inherently identical, as it depends just on the products

Modeling the case of a BiWgt design (S=B) with fixed splitter taps we substitute this fixed

value into MPoDAC equation, yielding

Here are the combiner “field tap”, i.e., the transfer from the s-th input port to of the combiner

to its output – the optimization proceeds over these combiner “field taps”. To determine the actual values of the taps, we recall the unitary constraint for an ideally lossless combiner, namely,

The power combining taps should be in ratios which are the squares of the field combining caps,

_, The sum of these ratio terms is

N^{ormalizing by this sum yields:}

These coefficients form a geometric sequence and their sum of squares is unity (consistent with the unitary condition) T^{aking the square root of this sequence of ratios yields}

Returning to substitute these field combining taps into (215) yields

The MSB field level is obtained by taking all signs to be positive yielding It is seen that for PAM4 and PAM8 generation the inherent modulation losses of the fixed-splitter BiWgt MPoDACs are moderate (of the order of 0.5dB and 1dB), thus the tradeoff between performance and complexity may be worthwhile. The COH PAM8 and COH PAM4 MPoDAC are special cases (both embodiments: matched taps vs. with fixed splitter or combiner) are important since they are the least complex to implement. We defer the detailed treatment of the photonic circuit for the COH PAM83-bit MPMZM until after we will have treated the embodiments of 1:3 splitters and 3:1 combiners. However, we are in a position to already treat here the COH PAM42-bit solution, which we do in the next subsection. The MPMZMs considered here are ideally lossless (and common phase constants are ignored) thus the evaluated field transfer factors and normalized MSBs represent upper bounds on actual performance. The analysis effectively assumed setting the input field into the lossless MPMZM to unity, R _in = 1 , such that the generated constellations emerge in standardized form (field transfer factors). 2-bit COH-PAM4 MPMZM – an MPoDAC using 2 parallel MZMs based on ‘matched-taps’ The COH 2MP photonic structure combines two BPSK modulators (aka ‘phase gates’) in parallel (Figures 8A and 8B), to generate an ‘inherently perfect’ (i.e. max-full-scale equi-spaced) COH PAM4 constellation (bipolar PAM4) in the optical field domain. Fig.1A illustrates a multi-parallel (MPMZM) 2bit oDAC architecture for COH PAM4 generation. PG=Phase Gate. PM=Phase Modulator. MC=Mode-Converter. VAR=Variable (tunable). Figure 8B - Multi-Parallel MZM (MPMZM) implementation of the 2-bit MPoDAC of the (left) diagram. Here the PGs are implemented as MZMs as shown. In fact, this structure supports not just COH PAM4 generation but also DD PAM4 generation, since the two MZMs may be used as OOK Intensity Gates (IG). Thus, the MZMs may be used either as PG (BPSK) or IG (OOK) modulators, depending on their electrical drives. Thus, 2-bit MPMZM in the (right) diagram is usable for the agile generation of a unipolar/bipolar-PAM4 constellation. This disclosed embodiment of the 2MP COH (PAM4), a special case (for B=2) of the B-bit COH BiWgt MPoDAC, is of practical technological importance, as the least complex MPoDAC to realize (having just two parallel paths) while maximizing the relative benefit in data rate (doubling spectral efficiency) w.r.t. to a BPSK-based coherent transmitter, or w.r.t. incumbent single-bit DD modulation technology, which is based on OOK modulators. Moreover, a pair of COH 2MP devices may be used to efficiently generate a 16-QAM constellation for coherent transmission, see 5.9.2. Rather than just specializing the general B-bits results to the special case B=2, it is instructive to swiftly rederive anew the model for this embodiment, in order to gain additional insight and validate the heretofore derived general B formulas. The embodiment of this section is based on ‘matched taps’. The splitter (1:2) and combiner (2:1) are enabled to feature variable split/combine ratios – these ratios, the ‘taps’ are tunable parameters to be adjusted in the performance optimization. An optimal design for synthesizing a max-full-scale equi- spaced bipolar-symmetric constellation) is enabled by ‘matching’ the combining taps to the splitting taps, in the sense of having them equal, for each of the two paths:

As the unitarity constraint stipulates that , it suffices to adjust a single

splitter tap (say ^^^^₀ ) and have the corresponding combiner tap, U ₀ , adjusted satisfy U _{W 0}. We have already derived in (248) the optimal tap vector solution for this MPoDAC for the target COH PAM4 equi-spaced max-full-scale constellation. The taps vector ^^^^should be set to

The power splitting taps are in the ratio, ^ and since their sum is unity, they must be

given by respectively. The generation of the equi-space max-full-scale field constellation is:

2-bit (COH-PAM4) MPMZM oDAC using 2-way MZMs based on ‘fixed-split (or combine)’ This embodiment is based on essentially the same block diagram (Figures 8A and 8B) as the ‘matched taps’ embodiments of the last subsection (as both have B=2 two parallel paths) but here we stipulate that either the splitter or the combiner be ‘fixed’, i.e. have taps that are correctly set in fabrication (and hopefully vary little due to environmental disturbances). Accordingly, either the combiner or the splitter will be variable, tunable in its splitting ratio (we do not advocate having both the splitter and the combiner fixed, just one of them ought to be fixed to enable mitigation of environmental disturbances). Moreover, for enhanced simplicity and robustness, we prefer to specify that the fixed splitter or combiner taps be “50:50” or close to this value. The main advantage of this embodiment is complexity reduction at the expense of a moderate reduction in performance. This 2-bit embodiment may be viewed as a special case of the BiWgt B-bit COH MPoDAC with uniform fixed splitter or combiner. Let us assume we take the 1:2 splitter as fixed 50:50, i.e., and let us optimize over the

two U-taps at the output side. This will provide:

This resulting PAM4 COH constellation is evidently equi-spaced, but it is not max-full-scale. The MSB (equal to the intrinsic modulation loss) is given by

In contrast, the PAM4 COH constellation generated by the ‘matched split/combine’ design is max-full scale, i.e. its intrinsic modulation loss is 0 dB. However, the ‘fixed’ design is a less complex one, as there is nothing to tune in the 50:50 uniform splitter, and there is essentially one combiner tap to tune 0as the other one completes it to unity ideally) and one phase to tune in one of the two paths (as just the differential phase matters). The 2: 1 combiner may be realized here as a slowly tunable MZM.

As a variant on this fixed 2-bit COH PAM-4 embodiment, in case that we have some ability to target particular splitting ratios for the 1 :2 fixed splitter, and have the designed-in value be reproduced relatively accurately in fabrication, it may be worth targeting not a fixed 50:50 splitter but a

attempt to fabricate a fixed splitter with the optimal splitting taps, an at the

input side, such that upon optimization of the adjustable //-taps at the output side, the resulting constellation would be not just equi-spaced but also closer to being max-full-scale. To understand the degree by which we may improve the design, it is worth working out the tolerance to deviation from the optimal splitter setting (while the //-taps are reoptimized for each tried-out value of the W -taps and performance is assessed). This will provide A PAM4 COH constellation, now parameterized by W₀, U₀, is obtained by using the 2-bit COH code,

The W₀tap of the fixed splitter is taken as a (“fixed” though not precisely known) parameter - ideally we would like it to be for optimal max-full-scale constellation, but due to the fabrication tolerances

(and possibly also environmental temperature dependence) the value of W_omay move around the target 1

- (or we intentionally set W₀ at a nominal value , that is convenient to us (even that may move

around, e.g. a nominal 50:50 splitter may come with fabrication errors, say ±10%i.e., we may get

[0.45,0.55]). Likewise, even when we aim to use the optimal nominal splitter, we may get

±10% fabrication error, such that This indicates the usefulness of a

tolerance analysis, whereby we will have W₀ as a settable parameter, say anywhere in the range of [0.25,0.55], and for each specific fixed value of the splitter tap, W₀, we shall optimize the PAM4 constellation “performance” over the tunable combiner tap parameter , U₀

Figure 12 illustrates a PAM4 COH 2-bit MPMZM with fixed splitter. The splitter fixed tap is somewhere in the range as explained above, with selected as per Table 3 or

figure 10 or figure 11, based on the target NFOM spec. The fixed splitter feeds two parallel fast MZM, preferably implemented as plasmonic ultra-high-speed MZMs (though any MZM implementation is allowed) In fact, we may replace the two MZMs by other types of phase-gates, in particular have them replaced by our two OAR-PG devices. In the implementation we use a pair simple MZMs for the PGs. The two outputs of the two MZM PGs are used as follows. Two outputs, one from each PG, are combined in a third slow MZM (the last one on the RHS), which is used as a variable combiner, tuned by changing the relative phase of the two phase shifters in the two arms by means of inserted slow phase modulators Note: slow phase shifters are denoted by small hollow black rectangles. Fast phase modulators as used in the MZM phase-gates are denoted by the electrodes marked ‘S’. One version of the proposed multi-parallel ODAC 2-bit PIC structure, (i.e.4-level constellations) is depicted in Figure 12 (an alternative design is shown in Figure 13. Either of these photonic layout are electronically reconfigurable for both PAM4 COH or PAM4 DD transmission, see also optical programmability in 5.10.1. The top (bottom) high-speed MZM in Figure 12 is driven by the MSB (LSB) bit, as elaborated in the figure caption along with additional details. The relative optical phase between the two parallel paths of figure 12 is stabilized to null while the ratio of magnitudes of two optical fields is calibrated and stabilized to an appropriate design value, to ensure the output 4-level constellation is as uniform as possible. E.g., in the case of coherent transmission, the two superposed fields from the two plasmonic MZM are in the ratio of 2:1, such that four field levels are uniformly spaced: [±3A,±A]=[+3A,+A,-A,-3A]. It is the task of the control-plane to calibrate and stabilize (track) the relative phase and relative magnitudes between the two paths, as actuated by the bias of the slow combining MZM and the two phase modulators in the two paths. The sensing points are the optical monitors at the three free-ports. It is the task of the control plane to calibrate and stabilize (track) the relative phase and relative combining magnitudes between the two paths (i.e. the combining ratio of the variable combiner MZM), as actuated by the bias of the slow combining MZM and of the two phase slow modulators in the two paths. The control plane is also tasked with having the two fast phase-gate MZMs correctly biased. The relative optical phase between the top and bottom phase-gate MZM paths is stabilized to null, while the ratio of combining magnitudes of the two optical fields is calibrated and stabilized to an appropriate design values to ensure the 4-level output constellation is as uniform as possible on the largest possible full-scale (ideally the output COH PAM4 constellation is perfectly equi-spaced and max-full-scale). The various slow phase controls in the diagram are used as follows: The two phase shifters inside each of the two fast MZMs (the phase-gates) are used to tune each MZM to balanced bias point (such that the output which leads to the combiner would be null in the absence of modulation and the two field levels respectively generated by the two antipodal voltages are of equal magnitude (but opposite signs). The other two outputs of the two fast MZM PGs are optionally sent out to feed two slow photodiodes (PD) plus Trans-Impedance-Amplifiers (TIAs) which are used for monitoring. When each of these two phase shifters is correctly tuned for the condition above, then no light emerges at the corresponding monitor port (the upper and lower PD+TIA). Ahead of the first coupler of the slow MZM used a combiner there are two slow phase shifters on the two input waveguides. Conceptually, those phase shifters are not part of the MZM combiner, but they are rather used for tuning the relative phase between the two paths (each path going through a particular phase-gate). This relative phase would ideally be stabilized to null. The two phase shifters inside the combiner MZM (in between its two couplers) is used to tune the combiner tap, denoted in the analysis above as U ₀ . The middle PD+TIA used for monitoring is fed by the other output port of the variable combiner MZM. When the combiner tap is properly tuned (assuming that the phase-gate fast MZMs are also properly tuned to have balanced optical paths), ideally all the light emerge at the PAM4 output, which would be maximized and none of the light would emerge at the monitor port feeding the middle PD+TIA. At the very input of the device, prior to entering the fixed splitter we may optionally insert a phase modulator or an amplitude modulator (the case of phase modulator is shown), used to additively inject a weak sinusoidal pilot tone to be used for monitoring. As already mentioned for the general case of B-bits COH MPoDAC, an alternative design sets the combiner as fixed while tuning the splitter. The splitter and combiner taps now just exchange roles. It is the power-splitting taps that should now be in the ratio . The resulting equi-spaced

field constellation is identical to the one above (and the insertion loss is evidently 0.46 dB as well). In fact, the analyses and designs described in this section remain valid if we exchange the words “splitter” and “combiner” while we also exchange the symbols and values

. What this implies for the block diagram of Figure 13, is that the optical flow first goes through a variable splitter feeding a pair of phase gates, and then we terminate the two paths in a fixed combiner. Figure 13 is an alternative embodiment of 2-bit COH PAM4 MPMZM oDAC with fixed combiner (and variable splitter realized as a tunable slow MZM). This embodiment is the dual of figure 12 in the sense that the splitter and combiner roles are interchanged. 3-bit (COH-PAM8) MPMZM oDAC using 3-wayMZMs based on the ‘fixed-split (or combine)’ Consider a PAM8 COH design based on a fixed-uniform-split design, namely a1:3 splitter with fixed- taps, . The 3:1 combiner is made tunable, with taps ,

selected such that that the end-to-end field transfer factors along the three paths (the end-to-end transfer factors of the three paths including the splitter and combiner contributions, as well as the backoff attenuation factor g of the PGs) are actually just the contributions of the splitter and combiner taps to the transfer factors are):

The full-scale is now which is -1.1 dB lower than the ideal

max-full-scale of 2. Additional building blocks for MPoDAC Optically Amplified Recirculating (OAR) PG There may be provided a compound photonic circuit built around a basic bipolar-driven MZM (preferably of the plasmonic type) realizing a new type of PG, which may be designed for reduced insertion loss and/or for reduced V _π (lower power). This device, referred to as Optically Amplified Recirculating Phase Gate (OAR-PG), exceeds the State-of-the-Art (SotA) performance of plain MZM PGs, by significantly improving the modulation Loss-V tradeoff. Our disclosed novel PG structure (Fig. 14) is based on a core MZM enhanced by photonic circuitry comprising optically amplified feedback to compensate most of the cavity Round-Trip Loss (RTL). The optical amplification may be achieved by means of hybrid-integrated a tightly controlled active gain Semiconductor Optical Amplifier (SOA). Alternatively, other types of optical amplifiers may be used. The advantage may be claimed as either a reduction in PG drive-power (at same electrode length as for a standalone P-MZM used for bi-phase switching; in this example a ~10× reduction), or as a reduction in P-MZM electrode length (at fixed drive power; in this example ~3x reduction, also hence ~3x reduction in modulation loss in dB). This novel PG structure retains the full bandwidth (e.g., of the order of 100GHz for a SotA plasmonic modulator) of the core MZM around which the compound PG is built. 1:S splitters, S:1 combiners, N:M mode converters Variable and/or fixed multiport splitters/combiners are used as building blocks (BB) for performing the multi-parallel fan-out and fan-in functionalities (the 1:S splitters and S:1 combiners) in our disclosed MPoDAC schemes. More generally, we consider tunable N:M mode converters. Mode-Converters (MC): We refer to an optical device with N input waveguides and M output waveguides (and no other port to leak light out) as an N:M Mode Converter (MC). (the multiport splitters or combiners are special cases of the N:M MCs, taking N=1 or M=1, i.e.1:N or M:1). The splitter and combiner MCs are BBs in our MPoDACs, and in many cases splitter and combiner MCs are based on more M:N MCs with M>1,N>1, hence we consider multi-input multi-output MCs. Tunable 2x2 MCs as BBs: Tunable multiport splitters/combiners, and more generally, tunable N:M MCs, may be realized as meshes of simpler BBs: generic 2:2 MC with a tunable 2x2 transfer matrix, the matrix elements of which may be arbitrarily tuned subject to a unitarity constraint (apart from a common phase factor which may remain fixed, or vary in a particular deterministic relationship with the other tuned parameters). Figure 16 is an example of a VOA-MZM. VOA stands for Variable Optical Attenuator. This is essentially an MZM with a pair of VOAs inserted in the two MZM branches. With the two VOAs incorporated (to actuate the α _Δ parameter of the MZM by the joint setting of the two VOAs), the resulting overall 2:2 MC may in principle attain perfect extinction at a selected output port (when exciting the overall 2:2 at just one input port) by tuning the two VOAs in opposite directions (reducing attenuation in one VOA while increasing attenuation in the other one, or viceversa) while monitoring the optical power of the selected output ports for its “level of extinction”, i.e., minimizing the power at that port by means of tuning the essentially minimizing the output power at the

selected port over the space of the two parameters

. Both VOAs are needed when we do not know the sense of the built-in loss asymmetry. In practice we may start by tuning

for minimal output power, then hold

fixed and tune ^^^^by means of ‘push-pull’ tuning of the VOAs, and iterate until converging to a minimum (ideally zero) power. Any state-of-the-art VOA may be used, e.g. for improving an integrated optics MZM structure we may insert electro-absorptive modulators in the two phase modulation paths of the MZM. We also note that VOA impairments such as non-pure amplitude attenuation (by which we mean that the variable attenuation is accompanied by variable phase modulation) may be counteracted by the phase shift errors that were introduced in the two arms. In a preferred embodiment we may use MZMs for the two VOAs as well. Thus, we end up with a “recursive-MZM” type of structure – the ‘MZM-with-VOA MZMs’ preferred embodiment of Fig.17 - wherein in the two interfering paths of the “outer MZM”, further to the two PMs we inserted two additional MZMs used as VOAs. This figure may then be viewed as a special case embodiment of the VOA-MZM of Fig.18, with the VOA also implemented here as an MZM. Thus, we have here a pair of inner MZMs and the outer MZM. We note that the presence of mild impairments in the two “VOA-MZMs”, in particular their finite extinction ratios, would not typically matter for nulling out, in principle, the extinction ratio of the overall 2:2 MC. This is due to the amplitude attenuation factor of MZMs (used as VOAs here) being monotonic functions on some phase sub-domains, hence being tunable in either desired direction (increase or decrease). Moreover, any variable phase shifts accompanying the variable attenuations of the VOAs (e.g. “chirp” of the MZMs used as VOAs) may be counteracted by tuning the two phases of the two PMs, as the VOAs are varied. To recap, the advantage of these two embodiments of “enhanced MZM” beyond a plain MZM, is that the extinction ratios of these improved devices may be brought down to negligible or at least reduced levels by proper tuning of the two VOAs and the two phase shift errs in the outer MZM branches. These two disclosed embodiments VOA-MZM and its special case, the MZM-with-VOA-MZMs are useful high-precision BBs for multiple applications. However, our main application here for VOA-MZM (in the context of MPoDACs, though for other applications as well), is to have the VOA-MZMs implement high-precision Phase-Gates (PG) or Intensity-Gates (IG). The VOA-MZM and MZM-with-VOA-MZMs devices disclosed above, may readily be driven electrically to realize either a PG or an IG, since the transfer factor characteristic of any properly tuned VOA-MZM is essentially that of a conventional MZM (in fact, the VOA-MZM realizes a better approximation of the ideal model of an MZM, since the extinction ratio is brought down to negligible levels by proper tuning of the two VOAs and the two phase shift errs in the outer MZM branches). To realize improved PG or IG we have two alternative embodiments: (i) A fast-modulated MZM, albeit with the simple fixed 1:2 splitter and 2:1 combiner replaced by a pair of VOA-MZMs, in particular by a pair of MZM-with-VOA-MZMs. See figure 18. (ii) (ii) A VOA-MZM with fast phase modulators inserted in the two arms. See figure 19 for this embodiment II. These two disclosed devices may then be viewed as fast-modulated-MZMs with enhanced precision (with the ability to have their extinction ratio further tuned out, reduced). To run these devices as chirp- free, the first condition is to bias the outer MZM to generate null field when the differential voltage is null. The second condition is to use antipodal push-pull drives which introduced the MZM-based chirp- free PG and IG. Figure 21 is an example of an Optical Signal Processor (OSP) that as cascade of MZM-of-VOA-MZMs BBs (with redundant 2:2 MCs eliminated as explained in the text. An application of this OSP is as a precision variable 2x2 MIMO matrix with endless tracking. Due to its complexity this photonic structure is to be typically implemented as a Photonic integrated Circuit (PIC) device. This compound structure essentially cascades a chain of VOA-MZMs (actually VOA-MZMs of the MZM-with-VOA-MZMs type of Fig.17) in order to obtain a high-precision 2x2 MIMO block. Note that in this disclosed implementation of the cascade of VOA-MZM stages we made the following modification: when the N-th VOA-MZM is followed by the N+1-th VOA-MZM, then either the output side 2:2 combiner of the N-th stage or the input side 2:2 splitter of the N+1-st stage is discarded from the chain (it suffices to retain just one of these 2:2 MCs. Thus, the chain consists of: VOAs ^phase- shifters ^2:2_MC ^VOAs ^phase-shifters ^2:2_MC ^VOAs ^phase-shifters ^2:2_MC ^… At the end of the chain we add, following the last 2:2 MC, an extra pair of phase shifters. An advantage of this cascade (besides its very low extinction ratio) is that since there is redundancy in having multiple VOA-MZMs, therefore it is possible to adjust the settings of the phase parameters of the individual stages such as to achieve endless tracking of any target 2:2 MIMO transfer matrix, without experiencing resets of the voltage drivers at the edges of the voltage ranges of the drivers, in case the phases need to evolve monotonically in one direction over multiple successive spans of ^^^^ ^^^^. Figure 22 is an example of 3:3 and 4:4 Mode Converters, implementing 4x4 and 3x3 optical MIMO, constructed out of VAR 2:2 MCs BBs, as per Reck’s work. The 2:2 MCs may be variously implemented in prior art as tunable 2:2 MZMs. To obtain higher precision and more tunability (realization of arbitrary MIMO matrices, not necessarily unitary) the 2:2 MC BBs may be taken as VOA MZMs (MZM-with-VOA-MZMs in particular) as disclosed above. Improved accuracy arbitrarily programmable S:S MC building blocks may be realized by using variable 2:2 MCs based on VOA-enhanced MZMs. In figure 23 our disclosed variable 4x4 optical MIMO matrix, unitary or non-unitary (tunable 4:4 MC), albeit with just some of the 4:4 ports used, may be constructed as a mesh of 2:2 VOA-MZMs BB (and in turn the VOAs may be realized as MZMs inside each of the VOA-MZMs BBs). Such arbitrarily variable high-precision SxS optical matrices may be used in quantum photonics or all- optical MIMO equalization for example. We may also use them as the starting point for realizing ultra- high-precision 1:S splitters and S:1 combiners, see next. Finally, improved 2:2 MC may be used to make improved extinction high-speed MZMs. Tunable 1:S splitters and S:1 combiners as meshes of arbitrarily tunable 2:2 MC BBs Evidently, tunable S:S MCs could be reduced to S:1 and 1:S MCs (combiners and splitters). However, it would be wasteful to fabricate full S:S MC and then not excite S-1 input ports upon realizing a multiport splitter, and likewise it would be useful to provide for S-1 output ports which are not used. Thus, a simplification of the original S:S MC full structure is possible, by removing all internal building blocks which solely participate in processing light from unused input ports or feeding unused output ports. Thus, we may remove some of 2:2 MCs of the full S:S MC used as 1:S splitter (remove those directly connected to unused inputs as well as additional ones downstream connected to the those directly connected to unused inputs) , and likewise re the unused outputs when a full S:S MC is used as a combiner. Efficient realizations of variable 1:S and variable S:1 modules may be conceptually generated by starting with a S:S and deleting the unused 2:2 MCs that are directly or indirectly fully connected to the unused ports. The resulting 1:S and S:1 structures, efficiently realized out of 2:2 BBs, are shown in figure 23 per the Reck structure and in bottom row for S=3 and S=4 (1:3 and 1:4 splitters and 3:1 and 4:1 combiners). Figure 24 illustrates an example of a 3-bit BiWgt MPoDAC (both the DD and COH versions) using a VAR 1:3 splitter and a VAR 3:1 combiner just as in the last figure. The difference between DD and COH is the nature of the 1-bit gates (OOK IG vs BPSK PG). The 1:S and S:1 splitter and combiner Reck-based embodiment exemplified for S=3 in the bottom row of figure 23), are incorporated in our 3-bit BiWgt PAM8 DD and COH MPoDACs in figure 24. Evidently, this may be extended for any S. Here we use the Reck structures for the 1:S and S:1. In the next subsection we disclosed some alternative structures for the 1:S, S:1. Tunable 1:S splitters and S:1 combiners based on the “tree” structure Here we disclose a generic mesh of variable 2:2 MCs structure capable of implementing a variable 1:S splitter or a variable S:1 combiner. We shall describe the generic 1:S splitter, since, by reciprocity, the S:1 combiner is essentially obtained from the same structure traversed in reverse. Four examples are described in figure 25 and figure 26, wherein we start from a single 2:2 MC used as a 1:2 splitter and successively generate several alternative 1:3, 1:4 and 1:5 structures. To construct a 1:S splitter the idea is to array the 2:2 BBs in a tree structure and start traversing the tree from the root towards the leaves aiming to have S distinct trajectories, ending in precisely S different leaves. There are multiple tree structures ending in S leaves, but some of them topologically identical to others, while the others are mutually distinct. For the case of S=3, all the ways are topologically equivalent to the VAR 1:3 splitter shown in figure 23. However, for S=4 we have two classes, one equivalent to the VAR 1:4 splitter shown in figure 23(made out of two VAR 2:2 MCs), while the other class consists of the symmetric tree solution shown in figure 24 (right). Both structures utilize three VAR 2:2 MC building blocks, but VAR 1:4 splitter II solution (figure 25 (right)), which we disclose, has the advantage of “uniform depth”. The total loss through the VAR 1:4 SPLITTER II is the same along all four lightpaths leading from the input to the four outputs – which is not the case with the VAR 1:4 SPLITTER I solution (figure 25 (left)), which features non-uniform losses from the root to the four leaves (output ports). The lightpaths leading to the upper port has the highest losses. In fact, ordering the output ports from the bottom up, we have increasing loss. As for S=5, i.e.1:5 splitters (see figure 26), as we need one more output relative to the 1:4 splitter, we may simply append a 2:2 on either one of the four outputs of the schemes in figure 25. It then seems that are a total of 8 different ways for it, but they fall into 4 topological equivalence classes, one representative for each of which is shown in figure 26. The first representative(upper left corner) is a Reck-based realization of the 1:5 splitter, essentially obtained by appending the 2:2 to the upper port of VAR 1:4 splitter I. The next appending the 2:2 to port #3 of VAR 1:4 splitter I, is topologically equivalent to the first one. The next two representatives are distinct. Then we proceed to place a 2:2 in turn onto one of the four outputs of VAR 1:4 splitter II. Here due to the symmetry all four ways are topologically equivalent, so they contribute a single representative. Specifying the proposed construction in generality, we start with a “root 2:2 MC”, we use one of its inputs (which becomes the input of the 1:S under construction) leaving free the other input port of the 2:2. Onto the two outputs of the 2:2, we either connect one of the inputs of another 2:2 or we just declare that output port of the 2:2 to be one of the output ports of the target 1:S . This procedure is recursively repeated, terminating it at any desired point. Once we add a new 2:2 onto one of the outputs of any interim 2:2, we may elect to use either both of its outputs or just one of its outputs as overall outputs of the target 1:S . Any outputs that are not allocated to the overall output are further split via new 2:2 and the process is repeated until we choose to terminate it. The Sx1 power transfer matrix (a column) describing the tree-based 1:S splitter, is readily obtained by inspection. Its elements (power transfer factors from the input of the 1:S splitter to each of the splitter outputs, are the splitter taps, W = [ W _{S − 1} , ... , W ₁ , W ₀ ] Since the path through the tree, connecting the overall input port to any 1:S splitter output port, say the j-th one, is unique, we may follow this path in the diagram, list the field transfer factors through each of the traversed 2:2 MCs (or rather 1:2 splitters) and simply multiply these field transfer factors. The power transfer function from the input to the j-th output is the square of the corresponding field transfer factor, therefore it is also equal to the product of the power transfer function along the path from the input to the j-th output. As for the phase of the field transfer factor, we may sum up the phases of the field transfer factors through each of the 2:2 MCs along the path. Note that none of the splitter lightpaths from the input to any output are interfering, therefore, the determination of power proceeds independently of the phase, which is irrelevant in this case. We now show how to synthesize any desired taps vector, w , i.e., design for any target power splitting ratio at the S outputs (subject to the unitarity constraint, assuming the splitter is lossless). As the 1:S splitter is made of 2:2 MC BBs, the design outcome is the determination of the individual 2:2 power splitting ratios (their phase shifts are irrelevant). Let us assume the input power into the root 2:2 MC of the lossless 1:S splitter is unity. In this case the specified taps coincide with the

optical powers at the 1:S splitter outputs. The idea is to utilize the conservation of power, working our way from the output backward to the input, tracing in reverse the forward flow of power. The proposed methodology for designing any tree-based 1:S splitter (composed of 1:2 MCs) is to propagate the specified output powers,

, back to the inputs of any of the 1:2 splitters encountered in the backpropagation processes, “collecting powers” this way until we reach the root of the tree, where we should have unity power. When done, we will have evaluated the powers at all the I/O ports of all the splitters. Thus, power at the beginning and end of each branch in the tree is known, therefore the splitting ratios of each 1:2 are readily formulated as ratios of output to input power of each branch. This construction establishes that any tree-based 1:S splitter design (based on 1:2 tunable splitters) is in principle realizable – there is always a solution. We shall present two examples, which are readily generalized to any 1:S splitter realized as a tree of 1:2 splitter BBs. The first S=4 example is the symmetric tree structure of the VAR 1:4 splitters of Fig.25 (right). Figure 27A is the tree schematic corresponding to Fig.25(right). The 1:2 splitter at the root has power splitting ratios

where the bar notation means here

The two following 1:2 splitters are denoted (here the double index labeling

designates the pair of output ports of the overall 1:4 that are fed by of each of these two splitters). Figure 27B i a tree block diagrams of 1:4 splitter embodiments, enabling evaluation of the X-taps – the splitting ratios of the constituent 1:2 splitter building blocks given target taps W0,W1,W2,W3: (left): VAR 1:4 SPLITTER I tree schematic. (right): VAR 1:4 SPLITTER II tree schematic. Thus, all the 1:2 splitting ratios (the X-taps) are marked on the arrows. The backpropagated powers (expressed in terms of the W-taps) are then added up and marked in Figures 27A and 27B at each of the tree nodes. The X-taps, i.e., the 6 splitting ratios of the three 1:2 splitter BBs are then readily written as ratios of the powers listed at the output and input nodes of each branch:

Next consider the asymmetric tree Reck-like design, VAR 1:4 splitter II of figure 25(left). Figure 27A is the tree schematic corresponding to Figure 25 (left), again denoting the 1:2 splitter at the root as

The two following 1:2 splitters are denoted (the subscripts

refer to the indexes of all the output nodes that may be reached via the two branches of each of these 1:2 splitters). Backpropagating the W-powers, we obtain the node powers. The ratio of node powers at the output and input of each branch again yields the X-taps, i.e. the 6 splitting ratios of the three 1:2 splitter BBs:

As for S:1 combiners, those are the reciprocal duals of 1:S splitters, hence given the task of combining S beams with power combining taps,

, we view the system as a reverse flow splitting power rather than combining it, and perform the design as if we have splitter rather than a combiner – the W-taps resulting from such equivalent designs are then assigned as the desired U-taps of the combiner. F^{or any of our disclosed MPoDACs, the procedures above then map any specified taps vector,}

^{, of the 1:S splitter and any specified taps vector of the S:1 combiner,}

_{into the splitting ratios (X-taps) required to be set for each of the constituents 2:2} MC BBs of the splitter and combiner. The proviso is that the splitter and combiner are realized as trees of 2:2 MC BBs. The key structural difference between the COH and DD cases is in the nature of the gates fanning the light into and out of the parallel paths. In the COH case we have seen that phase gates (BPSK modulators) are used, whereas for DD we shall have the phase gates replaced by intensity gates (OOK modulators). In this case, we may optimize the oDAC parameters for best performance and show that perfect linearity and zero intrinsic modulation loss of the MPoDAC are no longer possible. The objective is to maximize performance of the various disclosed MPoDACs over their design parameters, for optimal performance. Once we are done, it will become apparent that for DD applications, the comparison between the MPoDAC and the SEMZM is no longer clear-cut (as it was for COH applications), since each of the two alternative oDAC approaches (parallel vs. serial) features advantages and disadvantages. The decision which solution be preferred will be seen to depend on the balance of all the performance factors and all technology options w.r.t. the two alternatives. We shall see that adoption of modern photonic technology options such as plasmonic modulation and optical amplification makes the MPoDAC more favorable, leveraging more benefit than SEMZM when all the engineering tradeoffs are considered Optimization of DD BiWgt 2-MP oDAC as PAM4 DD constellation generator Constellation distance optimization In terms of optimization criterion, it is the max-full-scale equi-spaced constellation that has the maximal minimum distance, out of all possible constellations of the DD type. Thus, as measure of performance for synthesizable constellations, we shall adopt the minimum distance of the constellation, i.e. the least of the C-1 Nearest Neighbor (NN) distances between adjacent pairs of constellation levels in the optical power domain. We wish to maximize this worst-case distance, i.e. we adopt a optimization criterion, to be used for all our disclosed DD MPoDACs. Our distance optimization strategy for DD MPoDACs effectively aims to get as close as possible to the upper bound on distance (equal to 1/3 for a PAM4 DD max-full-scale equi-spaced constellation). It should be noted that for the COH MPoDACs this optimization criterion is not generally necessary as we have already disclosed the optimal binary weighted designs attaining “perfect” generation of equi-spaced constellations. For our DD MPoDAC designs, the distance criterion will turn out to lead to a quadratic programming problem with linear (equality and inequality) constraints). The case of the DD 2MP (PAM4) optimization, derived below, is technologically important, as it is the simplest MPoDAC to realize (as it has just two parallel paths) while maximizing highest relative benefit in data rate (doubling spectral efficiency) w.r.t. the incumbent single-bit DD modulation technology that is based on OOK modulators. The DD 2MP photonic structure simply combines two such OOK modulators (aka ‘intensity gates’) in parallel, to generate an imperfect PAM4 constellation in the optical domain, and we aim here to make it “least imperfect”, by judicious design of the MPoDAC parameters. We derive here the optimal operating parameters for the 2MP oDAC for its operation as DD PAM4 generator, based on the distance optimization criterion. Our generic MP2 structure consists, at its top level, figure 28 of a pair of OOK modulators (MOD) aka intensity gates, ‘sandwiched’ between a 2x2 variable splitter and a 2x2 variable combiner. Any method of electro-optical on-off switching may be used for the Intensity Gates (OOK MODs). Two particular embodiments of the OOK intensity-gates consist of either EAM or as MZM. When the MZM is used as intensity-gate, it is to be biased such that it emit no light at null differential drive voltage, and is switched from unmodulated null output state to an amplitude level, which for full scale would ideally equal unity (in the absence of excess losses and modulation backoff). As the quasi-static phase-shifts in the two arms are always antipodal, their sum is zero at all times (except if there are any drive imbalances during the state transients), thus no chirp is generated in any individual modulator, though chirp may still be generated by coherently combining the modulator paths via the splitter and combiner ‘sandwiching’ the two parallel paths. The 2MP-DD, feeds the two parallel paths though a fixed adjustable (tunable) splitter (the 2:2 MC with one input port left free) and recombines them via a combiner (2:2 MC with one output port left free), the joint settings of which determine the binary weights (referred to as taps) with which the three modulation paths phase bias path are combined. To control the generated 8-point 1D constellation the taps values must be accurately set. In addition to the 1:2 splitter and 2:1 combiner inserted in at least one of the two paths slow phase modulators (PM) to control the relative phases between the 1:2 outputs and/or the 2:1 inputs, to enable coherently superposing the three paths, in phase in our preferred embodiment (the phase modulations in the three paths may also be an inherent feature of the splitter and/or combiner). The joint action of the splitter, phase modulators and combiner, referred to as coherent fan-out/fan-in may be adjusted at relatively slow rate (~Hz to ~kHz) for precise tuning of split /combine ratios and phase alignments and appropriate control are evidently essential enablers for this multi-parallel oDAC architecture. Evidently, to control the generated 4-point 1D constellation, the taps values should be relatively accurately set. To this end, at least one slow phase modulator (PM) is to be provided to control the relative phases between the two paths, to enable coherently superposing them in definite relative phase relations. In most of our embodiments we combine the two paths ‘in phase’,

. As seen in figure 28, slow phase-shifter(s) aka phase modulators (PM) are to be provisioned in at least one of the waveguide paths in between the splitter and combiner (the figure provisioned slow PMs in both paths – when a single slow phase modulator is used its phase swing must be double than that of the pair of slow phase modulators driven in push-pull). Equivalently, slow PMs may be placed at the outputs of the splitter or the inputs of the combiner or within both arms of the MZMs. T^{o recap, the optimal matched taps in an PAM4 DD design are}

A suboptimal embodiment for equi-spaced DD 2MP PAM4 constellation generation A suboptimal design may generate an equi-spaced DD PAM4 constellation with the same distance

_{as our preferred optimal design, however in this new} design all three NN distances are equal

Heretofore we needed to have both the 1:2 splitter and 2:1 combiner tunable in order to set the optimal values - in our optimal preferred DD PAM4 design as well as for our equi-spaced DD PAM4 design (301). Both designs were seen to require matched splitter and combiner, set to a particular (irrational n_{umber) tap value,}

Attaining accurate particular values for a splitter or combiner tap and maintaining them steady, generally requires tunable taps and a calibration and/or control electro-optic subsystem (tuning and control electronic circuitry, electro-optic phase actuation methods, optical monitor points etc.). Such tunability of splitter/combiner taps is evidently a more complex than the alternative of using either a fixed splitter (and variable combiner) or a fixed combiner (and variable splitter) (“fixed” means static, non-tunable, fabricated aiming to attain a prescribed splitting ratio). The problem with fixed splitters or combiners is that they are hard to trim in fabrication, in order to attain the prescribed splitting or combining power ratio. Moreover the power splitting/combining ratio (the tap) may display environmental dependence (vary over temperature and mechanical stress). Nevertheless, one particular value of fixed splitter (or combiner) which is more readily attained and retained is the tap value i.e.

‘50-50’ MC used for either splitting or combining, e.g. a Multi-Mode-Interference (MMI) device, tending to attain 50-50 stable operation by virtue of its structural symmetry. It is useful to explore whether one of the two tunable MCs of the MPoDAC, be it the splitter or the combiner may be replaced by a simple 50-50 , without substantially degrading performance. This is idea behind our following disclosed embodiment referred to as ’50-502MP DD’ replacing either the splitter or the combiner in our original preferred design by a simple 50-50 splitter and combiner, then returning to optimize performance over the remaining tunable MC. We disclose the following lower complexity suboptimal design parameters for of DD PAM4 MPoDAC structure with fixed splitter or combiner, in two flavors: using either a 50-50 splitter and a tunable optimized combiner or a tunable optimized splitter and a 50-50 combiner. In fact, the block diagrams for these two cases (not shown) may be readily obtained as a modification of figure 28, taking either the splitter or the combiner to be a FIXED 2:2 MC rather than a VAR 2:2 MC. Alternatively we may take the circuits of figure 13 or 14 and use the MZMs as Intensity Gates (IG, i.e., OOK modulators) rather than Phase Gates (PG, i.e., BPSK modulators) in the COH case. Both design flavors are disclosed to use null relative phase between the two optical paths,

. Our 50:50 DD PAM4 MP2 oDAC structure is reusable for coherent detection of bipolar PAM4 Another useful aspect of the ’50:50 preferred’ BiWgt 2MP oDAC design just introduced just above, is that the same photonic structure, setting one fixed 50:50 tap and null relative phase parameter, , is reusable in a sub-optimal (though nearly optimal) design for

coherent detection as well (provided that U is reoptimized for COH operation). As we successively go through the four codewords the

expression cycles through the four equi-spaced values . Thus, we have

generated an equi-spaced COH constellation, but not that it is not a max-full-scale one, since the

_{0.948 factor in (315) (equal to -0.23 dB) scales the constellation down from max-full-scale (FS= 2) to} (again a loss of -0.23 dB in the FS and in the distance).

A common physical embodiment, based on a pair of parallel MZMs, with a 50:50 splitter and a variable (tunable) combiner set to either respectively, may dually serve both 2MP DD and 2MP COH

generation of PAM4 or bipolar PAM4. 3-bit BiWgt MPoDAC PAM8 direct-detection constellation generator (3MP-DD) We disclose a BiWgt 3MP oDAC structure at 3bit resolution, optimizing it as PAM8 generator for direct-detection. Its photonic architecture is the multi-parallel one assumed for all our MPoDACs heretofore, specialized to 1:3 ^3path ^3:1 i.e. using S=B=3 bits and paths to generate C=8 constellation levels, the optimization criterion for which is again the distance. The resulting DD PAM8 generator structure (see figure 24 (top)) along with its essential parameter settings is henceforth labeled as ‘3MP-DD’. This figure, already presented in the context of the 1:S and S:1 splitter/combiner, is repeated in figure 31 for ready access here. This 3MP-DD photonic structure is similar to the one disclosed for coherent detection, except that its three modulators in the three parallel paths are no longer ‘phase-gates’ (BPSK modulators) but are rather ‘intensity gates’ (OOK modulators). The three parallel paths are sandwiched between a fixed or preferably adjustable splitter (1:3) and combiner (3:1), the joint settings of which determine the binary weights (referred to as taps) with which the two modulation paths and the bias path are combined. Thus, to control and optimize the generated 8-point 1D constellation, the taps values must be accurately set (as usual with our MPoDAC disclosed designs). Compared with our 2MP-DD earlier disclosed photonic structure we just add a third parallel intensity gated path (now requiring to use 1:3 and 3:1 MCs). Apart from now having 3 parallel paths, the full structural and functional description of the 2MP-DD (which had 2 paths) applies here as well, including the remarks there concerning the phase and taps tuning control and calibration electronics. In particular, least two of the three paths should be equipped with phase modulators (PM) to control the relative phases between the 1:3 outputs and/or the 3:1 inputs, to enable coherently superposing the three paths, in phase. The coherent fan-out/fan-in technology for slow (~kHz rate) precise tuning of split /combine ratios and phase alignments and appropriate control are evidently essential enablers for this multi-parallel oDAC architecture. The techniques of the patent application [43] may be used in order to calibrate and stabilize the coherent fan-out/fan-in. Once the relative phase-shifts between the paths are set to have all three paths coherently superposed in phase (i.e the common phases of each of the three paths are maintained equal), the field domain taps e^{ffectively become real-valued, given by for the splitter (1:3) and}

_{for the combiner (3:1) (wherein the W-s and U-s denote the power-domain taps,} hence the square root). The taps are adjustable by tuning the 1:3 and 3:1 modules, enabling to adjust the splitting/combining ratios of either the 1:3 or 3:1 modules or both. In case the MC (splitter or combiner) is not tunable, it should be fabricated to high precision, trimmed to the correct fixed target values and device temperature might need to be stabilized. Deriving the power-distances vector for the constellation yields

DD embedded-PAM4-3MP oDAC (2bits over 3 paths) One way of realizing a B-bit oDAC is to take a higher-order B+1 bits BiWgt oDAC with codeword length one unit higher than that of the target oDAC but “freeze” one of the bits of the higher-order oDAC (typically the frozen bit is the MSB or LSB) – “freezing” a bit means setting it to unity, while still letting the remaining B bits assume all bit combinations. This effectively amounts to a simplification of the optical structure: as the gate corresponding to the always-on bit always guides light, we might as well remove the 1-bit gate (the one associated with the frozen bit) in the corresponding path, which reduces to an unmodulated ‘through’ waveguide. We refer to this construction as “oDAC embedding”. The investment in complexity accompanied with embedding (having B+1 rather than B paths, albeit one of them unmodulated, which requires 1:(B+1) and (B+1):1 splitter an combiner rather than 1:B and B:1) is warranted by improved performance of the DD MPoDAC. We disclose here a similar concept of “SEMZM embedding”: a BiWgt B-bit SEMZM may be realized with better performance by having it embedded in a B+1-bit BiWgt SEMZM, provided that one of its segments is frozen at fixed potential difference or equivalently a sub-wavelength difference in the two optical paths of the BiWgt SEMZM is structurally induced and optionally phase-bias stabilized. The differential phase of the extra fixed-bias segment or of the path differential also participates in the segment phase optimization along with the segment phases of the other B-bit actively switched segments. This construction, whether applied to SEMZM or to MPMZM generally tends to improve performance (increase the oDAC maximin distance and its NFOM figure of merit). Back to the embedded MPoDAC, here is an exemplary disclosed embodiment of a DD-PAM4 optical generator: A 2MP oDAC is embedded within a 3MP one. In this case, we start with a 3-way oDAC block diagram (the 3MP photonic structure discussed in the last section, but without committing to the taps optimization carried out there) and consider effectively setting to unity one bit out of the three bits of the 3MP oDAC, by modifying the diagram to have the corresponding 1-bit modulating gate removed, leaving a free waveguide for that path. E.g, let us set b ₂ = 1 (while still having W ₂ > 0 , with W ₂ optimized in the sequel). Figures 34A and 34B provide a comparison of DD PAM4 generation options with BiWgt 2-bit MPoDACs (adding our embedded PAM4-DD-MP to the design options already presented in Fig.30). In the examples of figures 34A and 34B we may give up on the constraint of zero extinction ratio (null LSB level). However, in so doing we actually gain in the maxi-min distance. The tradeoff here is between extinction and minimal distance performance. We now show a remarkable property of embedded MPoDACs: it is possible to operate an embedded B- bit BiWgt DD MPoDAC with a COH code rather than with its original DD code, attaining identical performance to that attained with the original code. This property may be useful in some situations, e.g. to make this type of oDAC reprogrammable, reconfiguring at will between COH and DD transmission. Simplified variant of PAM4-DD-3MP-embedded based on a fixed 50:50 splitter Referring to figure 35 - the CW path is the MSB path (the top unmodulated path of the three parallel paths of Fig.35), its bit effectively set to unity, being fed 42.5% of the input light power. This suggests that a simpler somewhat suboptimal design would feed 50% of the light to the CW path (the top one), leaving 50% to be partitioned between the lower two paths. The 50% light splitting would be generated by a fixed 50:50 splitter one output of which would feed the CW path, while the other 50%-50% splitter output would feed another variable splitter, the two taps of which would be optimized to yield the optimal (given the 50-50 splitting) maximin distance performance. At the other side, for matched taps, we would use a combiner-structure which is a mirror image of the splitters-structure (comprising a variable combiner followed by a 50%-50% combiner). Converting the data-unmodulator bias path of the embedded MPoDAC into a slow pilot injector Finally, we disclose that we may take advantage of the ‘bias path’ i.e. the path that does not comprise a high-speed IG, in order to insert into that path a relatively slow phase modulator or amplitude modulator for the purpose of injecting a pilot tone which may assist in the calibration and control of the embedded MPoDAC. The slow phase modulator may be for example a thermo-optic or electro-optic modulator. The slow amplitude modulator may be an MZM biased half wave between its on and off states. Both of these modulator types may be driven by and driven by a low amplitude sinusoidal tones or superpositions thereof. Non-Binary-Weighted MPoDAC designs Binary-weighted (BiWgt) MPoDACs were seen to have their number of parallel paths, S, equal to , the intrinsic number of bits associated with the oDAC code. We disclose here optical

constellation generation based on non-binary-weighted (nonBiWgt) MPoDACs, are defined as having “more paths than intrinsic bits”: nonBiWgt oDAC:

The nonBiWgt structure comprises “as usual” in our embodiments, a 1:C splitter feeding S=C-1 parallel paths, followed by superposing the paths back by means of a C:1 combiner. Unlike in BiWgt oDACs relation between C and B is no longer

.The new feature here is the provision of an excess multiplicity of parallel paths such that S will always exceed (we

recall that B is the minimum number of bits needed to represent C, i.e. for all ThWgt MP oDACs we have (while for the BiWgt oDACs family we had

nonBiWgt MPoDACs are seen to provide a “larger than needed” multiplicity, S, of parallel paths. As each path comprises an intensity gate (for DD), driven by one bit, the actual numbers of driving bits is also S – seen to exceed the minimum needed number of bits B. As we use “more bits than needed” in each of its C binary codewords of length

, we may, in principle, adopt any subset of size C of “codewords” out of the full collection of 2 ^S binary strings of S bits each. A design decision for any nonBiWgt oDAC (be it MPoDAC or SEMZM) is to select the oDAC code, i.e. the said collection of C codewords out of all possible 2 ^S possible codewords driving the S binary additive degrees of freedom of the oDAC. We note that the input into any DAC (be eDAC or oDAC) almost always consists of

(if the number of levels C is an integer power-of-two then the ceiling

function may be dropped - we simply have

These B-bit-strings simply label each of the C levels of the DAC, “telling” it which level to generate. Each B-bit triplet should internally generate a unique S-bit codeword (with S>B). Taking an B-bit-string and generating a unique S-bit-string requires a digital logic implementation of a Boolean vector function, mapping B-bit words to S-bit words, to which we refer as the “B:S digital encoder” or “Bbit:Sbit mapper”:

It is apparent that upon transitioning from BiWgt to nonBiWgt MPoDACs we give up on the “Direct Binary Drive” quality, as now the B bit words should be mapped into S bit words. The problem with the B:S mapper in ultra-fast DACs, is that its power consumption may be excessive, the more so the larger B and/or S are. This indicates that the BiWgt oDACs (be they MPoDACs or prior art SEMZMs) have an inherent advantage in energy efficiency. However, we have already seen that BiWgt oDACs display “oDAC nonlinearity” (interpreted in DAC terminology as deviation of the synthesized constellation (collection of analog output levels) from an ideal max-full-scale equi-spaced constellation. This nonlinearity may be alleviated by migrating from BiWgt MPoDACs to nonBiWgt ones, though as soon as S>B (even for S=B+1) we already need a B:S digital encoder, which degrades energy efficiency. However, for relatively small B and S and for modest increments of S above B (e.g., S=B+1 or S=B+2) the power consumption of the B:S digital encoder might be tolerable. As a concrete example of nonBiWgt MPoDAC we may contemplate a 4:8 embedded oDAC, meaning B=3 bits, S=4 paths, C=2^B=2³ =8 levels. We note that a B=3 bits BiWgt MPoDAC to generate an 8- level constellation, C=8, was disclosed above using just S=B=3 levels, but here we add an extra bit to each codeword (which requires adding an extra path, having 4 paths rather than 3). We also note that with S=4 paths, had we opted for a BiWgt design we could have generated a 2⁴ =16 level code, however in our nonBiWgt design, we are content with generating a 2³ =8 level code. This means that we have to give up 8 levels out of the 16 level code, or equivalently select 8 levels out of 16, which best approximate our target 8-level constellation. Thermometer-Weighted (ThWgt) C-level MPoDACs embodiments In this section we disclose the structure and design of a Thermometer-Weighted (ThWgt) family of MPoDACs. The ThWgt MPoDACs are a subset of the larger family of nonBiWgt MPoDACs. Thus, the number of paths S should satisfy (360)

In fact, for a given number of constellation levels, C, the ThWgt MP oDAC for a size C constellation uses S=C-1 paths. The S=C-1 setting automatically satisfies the nonBiWgt condition, as the following identity is readily verified

Note that in ThWgt implementations it is not necessary to have C dyadic. Non-power-of-2 code sizes are allowed. These design guidelines effectively specify the dimensions of the code matrix B, as being

Exemplary embodiments: ThWgt MPoDAC for 4-level constellations; two parallel paths:

3-level ThWgt MPoDAC with 2 paths:

8-level ThWgt MPoDAC with 7 paths:

To complete the BiWgt family structural description, we should specify the Thermometer-Codes: The ThWgt DD MPoDAC has C-1 paths and the code has size C. Its constructed as follows:

The c-th row of the matrix, c=1,2,…,C, has its first c-1 elements 1, while the rest of the elements in the row (C-c of them) are zero (this implies that the top row is all-zero, while the bottom row is all-ones). An alternative description: Start with a lower triangular matrix (i.e. all ones on its diagonal and under it, all-zeros above it) and atop it append an all-zeros row. Examples:

Here we also disclose alternative structures of ThCode matrices, obtained from basic ThWgt matrix structures described above. One way to generate new ThCode matrices is to reverse the columns (last column becomes the first one, etc.). A more general way is to perform any permutation on the columns. Note that these operations preserve the first row (the all-zeroes one) and the last row (the all-ones one). More generally permutations of all rows possibly compounded by the previously mentioned transformations are also allowed.. Note: beware that some of the reversible transformations (the ones including row permutations) require accompanying reversals or permutations of the W vector and/or the

to generate meaningful solutions of the equation , i.e. the two said vectors may

no longer be monotonically ordered when the modified matrices are used. Yet another way of generating new ThWgt matrices is to start from any invertible matrix with elements {0,1}, provided that this matrix contains an all-ones row (not necessarily at the top or bottom of the invertible matrix). If we retain just the matrices with the {1,1,1} row at the bottom, we get the following 18 matrices, any of which may be used as codes for ThWgt MPoDAC (and a solution is assured to exist for arbitrary constellation generation with each of them, since the lower 3x3 block obtained after removing the top all-zeros row, is an invertible matrix – the linear algebraic argument why the solution always exists for arbitrary constellation is made below for the “classical” ThCode in (362) but the same argument

pertains for any of the matrices below, all of which have their last three rows forming invertible sub- matrices – of figure 46). All resulting matrix variants described above may be adopted as ThCodes and will exhibit, in principle, essentially identical performance. Now that we have specified the ThWgt MPoDACs, structurally, and stated a multitude of code variants, let us investigate the attainable performance and derive the optimal split/combine tap parameters. The key benefit of the C-level DD ThWgt MPoDAC (which has C-1 parallel paths) is its capability of generating any desirable max-full-scale C-level constellation, by judicious setting of its matched split/combine tap parameters. Thus, are no there are no max-full scale DD constellations (with C levels) that cannot be synthesized by the ThWgt MPoDAC with C-1 parallel paths. In particular, the max-full-scale C-level equi-space constellation is always attainable with a C-1 paths ThWgt MPoDAC. A^{n example of a target power-domain max-full-scale DD PAM4 constellation,}

The downside of ThWgt designs is that they are energy-inefficient and are have higher complexity, the more so the larger the code size (constellation size), C, is. The energy inefficiency stems from both the necessity of having a B:(C-1) bits digital encoder, as well as requiring multiple modulator drivers, S=C- 1 of them, one for each parallel path. However, for low values of C, as disclosed here, these deficiencies would not typically place a heavy burden. The 3-way 2-bit ThWgt PAM4 DD is presented in figure 36. To generate PAM4 DD, (C=4) with the ThWgt MPoDAC we require S=3 paths – to be compared with the corresponding BiWgt MPoDAC, which requires just paths. Therefore, by adding in just a single path to the BiWgt 2-

path DD design, we attain inherently perfect linearity and maximal dynamic range (inherently generate equi-spaced max-full-scale operation). In contrast, the original BiWgt has its min-distance downgraded relative to a perfect constellation. Note that the optical layout of the 3-way 2-bit ThWgt PAM4 DD embodiment introduced here (figure 36) is identical to that of the 3-bit (3-way) BiWgt PAM8 DD MPoDAC – both devices features 3 parallel paths, however the ThWgt generates just a 2-bit (PAM4 DD) constellation, whereas the BiWgt device generates a 3-bit constellation (PAM8 DD). What is gained with the ThWgt MPoDAC that constellation may be synthesized inherently perfectly, in particular a equi-spaced max-full-scale one. In terms of added complexity, to enjoy the high accuracy of the ThWgt constellation, the original two- way structure needed for a BiWgt PAM-4 DD MPoDAC should be augmented by one more path. Moreover, the ThWgt PAM4 DD oDAC requires now 1:3 splitters and 3:1 combiners (rather than 2:1 and 1:2), and is also less energy-efficient since we have 3 modulators to drive rather than 2 of them, and the ThWgt design also requires the 2:3 digital encoder to map 2-bits (specifying PAM4) into 3-bits (to drive the three paths). Such encoder may be realized with a small number of digital gates, albeit hard to implement at ultra-high-speed for an ultra-fast oDAC. The photonic layout of the ThWgt PAM4 (figure 36) is essentially identical to that figure 31 (the PAM8 DD BiWgt MPoDAC), but now we are able to generate a ‘perfect’ PAM4 DD constellation rather than a somewhat distorted PAM8 DD one. It is also worth comparing the ThWht DD-PAM4 design of figure 36 with that of figure 33 (the DD-PAM4-3MP-embedded oDAC). Both these oDAC designs generate PAM4, but the ThWgt option trades off having to use an electronic 2bit:3bit encoder in exchange for attaining a ‘perfect’ constellation, whereas the embedded DD-PAM4-3MP MPoDAC uses “Direct Binary Drive” of two bits, but has its constellation distorted. MPoDACs augmented by other photonic technologies MPoDACs with internal (Semiconductor) Optical Amplification ((S)OA) Optical modulators generally suffer from large excess losses. e.g. plasmonic modulators are highly useful for high modulation bandwidth and low drive voltages, but the downside is that they suffer from large modulation loss. Likewise, Silicon Photonic and Indium Phosphide (InP) based modulators may exhibit relatively large losses. Moreover, oDAC structures tend to further exacerbate modulation losses due to losses stemming from the oDAC structure. Fortunately, MPoDACs turn out to be highly compatible with Optical Amplification (OA). In particular in integrated photonic MPoDAC structure, Semiconductor Optical Amplifiers (SOA) may be beneficially integrated (typically hybridly) in preferred configurations disclosed in this subsection. It turns out that combining MPoDACs with (S)OAs, in the way disclosed below, yields much improved performance than that delivered by combining SEMZM oDACs with SOA. We preview here that the reason is that the MPoDACs inherently enable accommodating SOAs internally at locations in the optical flow which are more amenable to improved tolerance to the patterning-effect impairments of SOAs, whereas no such locations exist in SEMZMs. MPoDAC patterning effect advantage SOA patterning effect brief background: The SOA is a nonlinear element with memory [44]. The nonlinearity of the SOA is mainly due to carrier depletion induced saturation, whereas its memory is due to its finite carrier lifetime. The signal-dependent instantaneous gain of the saturated SOA results in non-Gaussian statistics at the output, and the finite memory of the SOA leads to bit patterning effects, thus resulting in “nonlinear”, i.e., signal-dependent enhancement of the intersymbol interference (ISI), on top of the “linear” ISI enhancement stemming from fiber dispersion, optical and electrical filters. The bandwidth limitation in all-optical signal processing based on SOAs is attributed to the patterning effect in the output pulse sequence, namely the decay of amplitudes for subsequent mark bits. Patterning-free operation requires a full recovery of the carriers between subsequent pulses, i.e., the delay between two consecutive pulses has to be larger than the carrier recovery time of the SOA. Pattern effects result from long recovery times of gain and carrier induced phase change, inducing penalties due to the non-instantaneous recovery dynamics of the cross-phase and cross-gain modulation. The operating speed is limited by the recovery of the carrier density, which takes place on a time scale of typically 20-100 ps, and leads to patterning effects on the switched signal, which become detrimental at high bitrates. Patterning effects are manifested as having response to a bit depends on the prior sequence of bits, i.e. they generate a form of (non-linear) Inter-Symbol-Interference (ISI). For an Intensity Gate (OOK modulator) followed by a SOA the patterning effect is largest for a long sequence of 1’s followed by a long sequence of 0’s, or vice versa. The patterning effect is more pronounced for signals with large peak to average ratio, such as higher-order multilevel signal constellations. This indicates that generally multi-level oDACs may not be compatible (i.e. may not work well) with SOA. If a SOA is inserted externally, at the multi-level modulated output of any oDAC (be it conventional SEMZMs or our MPoDACs) considerable distortion is generated due to patterning effects induced in the SOA, given the relative high Peak-to-Average-Power Ratio (PAPR) of the multi-level constellation at the oDAC output. SOA inserted intra-MPoDAC: Fortunately, the MPoDAC architecture (MPMZM in particular) enables an alternative to inserting SOAs not at the oDAC output – in MPoDACs, SOAs (or other OA types) may preferentially be inserted within each of the multiparallel optical paths (between the splitter and combiner corresponding ports), whereat the signals are ideally constant envelope BPSK, thus ideally free-of-patterning effects. Inside each path the SOA may be inserted either before or after each PG or IG MZM. To compensate for PG losses, an array of SOAs is most favorably inserted right at the outputs of each of the 1-bit gate array outputs or anywhere else between the 1-bit gates and the combiner inputs. The principle is to insert the SOAs before high PAPR is being generated by the combiner superposing the fields from the multiple incoming paths (since the patterning effect is lower for a low PAPR signal). See figure 37(top) for a generic COH MPoDAC wherein the PG array is implemented as an MZM array and the active gain array is inserted right thereafter. Figure 37 (bottom) shows an exemplary embodiment of a 3-way MPMZM-with-SOA. This MPoDAC uses an array of three MZMs for the 1-bit gates (PGs for COH or IGs for DD) followed by an array of three SOAs. The VAR 1:3 splitter and VAR 3:1 combiner are implemented based on the Reck structure of 5.4.2, as a mesh of slow tunable MZM and PM building blocks, but other variable splitter/combiner implementations are possible. To elaborate on the reduction of the patterning effect, once our COH MPoDACs are equipped with SOAs, the field waveform amplitude at the output of an IG (OOK modulator) varies rapidly during bit transitions. But for a PG, its BPSK modulated field has constant amplitude, except during the transients, which may be relatively brief for ultra-high-speed modulators (such as plasmonic modulators). Thus, SOA patterning effects may not be totally eliminated for a COH MPoDAC (which inserts a SOA to follow each BPSK PGs in each path), nevertheless, SOA patterning effects are greatly reduced (relative to a configuration having a SOA inserted at the multilevel signal output). Another way to quantify the low level of patterning is to note that BPSK signals (their switching transients included) exhibit the lowest Peak-to-Average-Power-Ratio (PAPR) - significantly lower than that of multilevel signals. Moreover, for our preferred embodiments of MPMZM which are based on ultrafast plasmonic MZMs, the durations of the level transients are even shorter than usual, further reducing the impact of the deleterious patterning effect. This discussion indicates that yet another advantage of our disclosed MPoDAC structures is their amenability to optical amplification with the patterning effect impairment substantially reduced. For sufficiently high SOA gain, SOA-MPoDACs may yield net modulation gain rather than just reduced net modulation loss. This advance, relative to the prior-art SEMZM oDAC technology (which is unable to exploit SOAs effectively due to patterning effects) is enabled by the multi-parallel oDAC structure, the only structure amenable to inserting the SOAs right at in the path of low PAPR optical components. PAM4-DD MP3-embedded with SOA: It is also possible to insert SOAs following the Intensity Gates (OOK modulators) in a DD MPoDAC, but this is less advantageous (yet preferable over inserting the SOA to the output of the DD MPoDAC). Despite the matched taps design having no intrinsic modulation loss, when it comes to using OA in MPoDACs, the reduction of intrinsic loss by matched taps yields a marginal benefit. It is preferable to adopt a fixed uniform splitter along with the SOA (in fact, in figure 37(top) we provisioned for this option when we labelled the 1:S splitter as either VAR or fixed). A fixed uniform fixed splitter assists the OA design by providing equal powers at the SOA inputs, which helps prevent SOA saturation when the optical levels at the splitter output are disparate in level due to the spread in the 1:S splitter taps values. The intrinsic modulation loss of the uniform design would typically be offset by the much larger SOA gain, which may even saturate to a fixed value when the input level into the SOA is not too low. Moreover, by giving up on variable splitter taps, we circumvent the need the calibration and control of the matched-taps MPoDAC design for both the splitter and combiner. In any case we still have to calibrate and control the combiner taps. Plasmonic MZM based MPoDACs (MPMZMs) Any of the MPoDACs embodiments disclosed in this work may be specifically realized as MPMZMs based on using plasmonic MZMs for their phase gates or intensity gates, as applicable. Having mentioned the high optical loss of plasmonic MZMs, the rationale of our (S)OA-P-MZM embodiment is to mitigate the high modulation loss when plasmonic MZM 1-bit gates are used in our disclosed MPMZM oDACs, by also incorporated (S)OA gain, in order to compensate in this case for the excessive plasmonic modulation loss. At the subsystem level, we propose embodiments jointly leveraging the three elements of Plasmonic Modulation, (S)OA and MPMZM oDACs. In particular, we disclose a (S)OA-Plasmonic-MPMZM ((S)OA-P-MZM) oDAC structure, which is an MPMZM with (semiconductor) optical amplifiers inserted after the plasmonic-MZM 1-bit gates in each of the parallel paths. Figure 37 (bottom) may also be used, as is, to illustrate this embodiment (in the exemplary case of S=3, which may be readily extended to a different number of paths), with the proviso that the MZM modulators depicted in that figure are plasmonic ones. Since >100GHz bandwidth per each 1-bit gate will needed in next product generations of optical interconnects, plasmonic MZMs are beneficial to adopt as ultra-fast PGs at reasonable ^^^^ _^^^^, but would still be affected by quite high modulation loss (of the order of 8-12 dB) in the plasmonic active region. Alternatively, plasmonic MZMs may be designed with shorter electrodes, to reduce loss, albeit at the expense of increased drive power (fixed ^^^^ _^^^^-Length product). Note 1: we have the (S) of SOA encircled in brackets as we may also consider future non-SOA based OAs such as in-waveguide optical amplification, to be inserted following the (plasmonic-)MZMs in each of the multi-parallel paths. Note 2: The OAR-PG may be a more efficient alternative PG compound structure based on an MZM with optically amplified feedback. In that embodiment having the high-speed MZM be of the plasmonic type, would also be highly beneficial. However, in this subsection we assume for the PG or IG recurring building blocks in our MPoDAC, a simple conventional MZM (albeit realized with plasmonics). Nevertheless, whenever PGs are used, throughout this work, this section included, the more complex yet better performing OAR-PGs could be substituted for them. MPMZM tuning: off-line calibration, online tracking control Our BiWgt MPMZM oDAC, uses B MZMs for a B-bits (PAM-2^B) constellations, thus requires no B:C encoder. The only required electronics a low-rate controller for calibration and real-time stabilization. Inherent to our opto-electronic architecture (for the BiWgt MPMZM as well as that of our other disclosed variants) is the relatively slow tuning of the splitter and combiner taps (which should have prescribed values for optimal performance, as extensively derived in this work for our multiple embodiments) as well as the tuning of the relative phases between the multi-parallel paths (which should be set and stabilized to null). A key advantage of our disclosed architecture is that the slow Calibration & Control electronic plane is totally decoupled from the ultra-high speed electrical data path – the voltages modulating the 1-bit gates according to the incoming codewords. Essentially, the MPMZM is offline- and online-tuned by adjusting the optical splitter and optical combiner settings at very slow speed (sub-Hz rates to mitigate temperature-induced drifts and up to KHz rates to counteract acoustically-induced disturbances), by means of calibration and control techniques. This inherent decoupling of the ultra-high-speed modulation vs the ultra-slow-speed calibration and control implies in our MPMZM oDAC architecture, enables high-precision calibration of the oDAC along with arbitrary reprogram ability of its (non)linear (“staircase”) transfer function, which in principle may be perfectly linearized; alternatively it may be predistorted in any prescribed way to mitigate another nonlinearity in the transmission chain (though the BPSK MZM operation is inherently linear in our case). To implement the Control & Calibration (C&C) of our MPMZM oDAC, we actuate multi-parametric control of multiple phase degrees of freedom (“phase knobs”) in large-scale PICs, based on multi- parametric extremum-seeking control. In order to calibrate and track the photonic circuit of an MPMZM (e.g., the MPoDAC devices of figures 7A – 7C or many other similar figures in this work) we use monitor PDs as slow probes at any free output ports of the system (and if such free output ports are not available, then we optically tap the output or internal waveguide of interest, to syphon off a small fraction of the light to be photo detected at slow speed to be used as monitor point. C&C optimal actuation of K phase knobs is feasible by sensing far fewer than K optical monitor points by using the methodology of “extremum-seeking control”. To “self-configure” the optimal split / combine ratios, we sense the photonic circuit state by injecting an optical pilots on the input or at other critical points in the photonic circuit, supplemented by weak orthogonal dithering at slow rates, additively applied into all Phase Modulator and MZM phase biases and synchronously detecting harmonic and inter-modulation products due to the individual or joint modulations at any of the slow and/or fast active modulation devices, using for the sensing of the harmonics and intermodulation, the PDs+TIAs at any available monitor points (see above), performing synchronous detection using as electrical mixing references signals at the frequencies of the injected sinusoidal pilot tones. QAM generation by IQ-MPoDACs Additional building blocks (BB) arising in vector (complex, 2D, IQ) MPoDACs Quadrature Multiplexer (QMUX) BB The QMUX is defined here as a 2:1 module superposing two optical inputs in quadrature (Fig 38A) . One of the two inputs into the QMUX is shifted by ± π / 2 and then combined with the other input through a 2:150:50 combiner). The ± π / 2 phase-shift may be achieved by a single slow phase-shifter or a pair of them, or it may be structurally achieved by having one arm a quarter-wavelength longer or shorter than the other arms. The linear I/O model of the QMUX is a linear combination of the two inputs, with taps given by . This linear combination of two signals, I(t),

Q(t) will be referred to as “quadrature multiplexing”. The

phase-shift may be achieved by a single slow phase-shifter or a pair of them, or it may be structurally achieved by having one arm a quarter-wavelength longer or shorter than the other arms. Figure 38A illustrates a Quadrature Multiplexer (QMUX) building block – linear I/O model. Bias electrodes (not shown) could be added to the two arms for phase stabilization. Figure 38B illustrates a Prior-art QPSK modulator MOD, comprising on a pair of parallel PGs (BPSK modulators) feeding a QMUX. QAM MPoDACs - quadrature modulation by a pair of 1D COH PAM oDACs A pair of COH 1D oDACs or may be used as In-phase and In-Quadrature (IQ) tributaries to generate a QAM modulated optical signal, in which both the amplitude and the phase of the light are varied from symbol to symbol. This is actually prior art. QAM generation by nesting pairs of IQ SEMZMs, to double spectral efficiency, was already demonstrated. Here we disclose in particular multiplexing pairs of our PAM MPoDACs to generate 2^2B-QAM, for B=2,3,4,…. See figure 39 for a QAM generator based on nesting a pair of COH PAM-2^B MPoDACs, by feeding the two MPoDACs into a QMUX (i.e., introducing 90^o phase difference between the two COH PAM outputs prior to summing them up in a 50:50 combiner). The two subsystems used as IQ tributaries (namely those are our disclosed MPoDACs, not in their system-level IQ combining) are unique. Thus, quadrature multiplexing of two PAM-2^B constellation generators by means of a QMUX, generates a 2^2B-QAM constellations (4QAM, 16QAM, 64QAM, 256QAM,….). As an example, for B=3, let us derive the transfer factor of a 64QAM generator based on quadrature-multiplexing two PAM8 COH constellations, generated using our disclosed 3-way MPoDACs with matched-taps design (assuming as usual that the splitters, combiners and phase-gate MZMs are lossless and we operate the MZM phase-gates in the two I and Q MPoDACs without backoff, i.e. treating the ideal case):

where the subscript denotes the 6-vector (string) of bipolar (±1) bits

driving the three PGs of the I-MPoDAC and the three PGs of the Q-MPoDAC, and in last expression in (369) the sum of two sets of numbers is defined as an “outer sum” or “set sum”: the set of all possible sums of elements from the first and second set. Thus, a 64QAM equi-spaced constellation is expressed as the “outer-sum” of two PAM-8 equi-spaced constellations along the I and Q complex plane axes. The multiple factors of occurring in the first equality above are accounted for as follows: The

preceding and following the two curly brackets are the IQ splitter and QMUX combiner transfer factors. The preceding and following the two sums inside the curly brackets are the transfer factors

of the 1:2 splitters and 2:1 combiners within the two paths internal to each of the two PAM-8 MPoDACs. Note that the QAM constellation that may be generated this way are sized

. In order to generate we may use a 2^2B-QAM

generator (as disclosed above), but have its electrical driver system preceded by a digital encoder (different than the one referred to heretofore) to ban certain 1D symbol combinations in the two PAM- 2^B MPoDACs working in unison, thus providing the mapping from the integer index labeling each of the constellation symbols, 2^{2 B −1} to the pair of indexes labeling the 2 ^{^^^^}levels of individual I and Q PAM MPoDACs. In simple terms, to generate 2^{2 B −1}-QAM, certain combinations of levels of the two I and Q PAM MPoDACs (in fact, half of them)are removed. The IQ-multiplexing of a pair of PAM-C COH generators to form C²-QAM is essentially known art. It follows that we may generate, in principle, using a pair of our MPoDAC tributaries, QAM constellations of any size (our novelty is in the usage of the two subsystems, not in their system-level IQ combining). Moreover, we may combine multiple degrees of freedom of multiplexing MPoDAC-generated QAM signal tributaries, each generated out of pairs of MPoDACs. We may use Wavelength Division Multiplexing (WDM) and/or Spatial Division Multiplexing (SDM) and/or Polarization Division Multiplexing (PDM) (also known as Dual Polarization Multiplexing (DPM), as exemplified in Figures 40A- 40B for PDM-64QAM based on four nested 2-bit MPoDACs. We may also directly multiplex 1D MPoDAC -generated PAM signal tributaries (be they COH or DD) onto these multiplexing DOFs, e.g. modulate independent PAM-2^B MPoDAC 1D constellations onto multiple CW subcarriers of different frequencies (FDM), or inject two independent PAM-2^B MPoDAC 1D constellations onto the X and Y polarization components (PDM), or inject independent PAM-2^B MPoDAC 1D constellations onto multiple cores of a multicore-fiber (SDM). Figure 40A discloses the PIC core architecture of a single carrier (CW laser fed) optical transmitter based on four PAM-2^B tributaries successively multiplexed in IQ-phase (using a pair of QMUXes) and in polarization (using a Polarization Division Multiplexer (PDM)), in order to generate a PDM-QAM— 2^2B output optical signal. Figure 40B illustrates a preferred embodiment for B=2 bits per MPoDAC: Four 2-way BiWgt MPoDACs of the MPMZM type, each internally comprising two parallel plasmonic MZMs used as PGs, assuming state-of-the-art 200 Msym/sec modulation rate for plasmonic MZMs, each of the four MPoDAC lanes generates a Bx200 Mb/s = 400 Mb/s PAM-4 COH optical signal. IQ-multiplexing these PAM-4 COH signals in pairs via the two QMUXes, (IX and QX via the first QMUX, IY and QY via the second QMUX) generates a pair of QAM-16 optical signals labeled X and Y, each at the rate of 2x400 Mb/s = 800Mb/s. Finally, multiplexing these two optical signals via the PDM generates 2xQAM-16 the output signal on the output fiber, carrying two independent 800Mb/s signals on each of the X and Y polarizations. Its aggregate rate is 1.6Tb/s for this single carrier signal, which has spectral efficiency of 8bits/symbol. Optical Programmability for 1D and 2D MPoDACs (PAM and QAM) Optical programmability is a recent trend whereby optical constellation generators are designed with the ability to modify their constellation parameters (in particular the constellation size). We have already disclosed MPoDAC for PAM-2^B fixed constellation generation, in particular MPMZM oDACs featuring B parallel MZMs. Yet another advantage of these disclosed structures is their amenability to agile optical programmability with little extra conditioning– it turns out that it is possible to arbitrarily (re)configure, on-the-fly, not just of the shape of the oDAC staircase transfer function (the positions of the constellation points along the optical field axis), and/or the constellation size (number of steps in the staircase). This optical re-programmability applies to both COH as well as DD MPoDACs. Moreover, it is possible to readily switch the between the COH to DD MPoDAC functionalities – transitioning from having a prescribed bipolar constellation in field-domain to a prescribed unipolar one in the power domain. Typically (but not necessarily) the constellations in each switching state (each corresponding to the selected number of levels COH/DD optical domain) are specified as equi-spaced max-full-scale ones. In fact, in the disclosures heretofore and their models, we adopted tunable MPoDAC splitter and/or combiner, and have seen that the “oDAC staircase”, i.e. the values of the optical levels, is determined the taps vector settings, typically subject to certain constraints on the positions of the field or power constellation levels. The modification of the oDAC levels (for a fixed number, of levels C=2^B) is ‘Mode-I’ of optical programmability. ‘Mode-II’ is the reprogramming of the PAM constellation size, C=2^B, i.e., effecting agile switching of the number of constellation levels, in the field optical domain for COH, in the field optical power for DD. ‘Mode-III’ is the switching between the COH and DD target optical domains. As for mode-II programmability, switching the constellation size , S=2^B , is not entirely arbitrary, but there is an obvious constraint set by the initially invested opto-electronic resource – the number of provided parallel paths, equipped with PG or IG drivers, in the opto-electronic hardware. An oDAC photonic circuit nominally designed for B-bits, may then be reconfigured to operate as an b-bits oDAC, for any b satisfying with b ≤ B . Thus, the MPoDAC is reprogrammable, on-the-fly, to switch between multiple constellations of different sizes, provided these sizes are no larger than 2^B , with B the number of parallel optical paths provided in the oDAC optical layout. Thus, all PAM-2^b formats for b=1,2,…,B- 1 may be switched among. As particular examples, a PAM16 (COH or DD) MPMZM may also generate (COH or DD) PAM8, PAM4, and PAM2 (which is BPSK or OOK). A PAM8 (COH or DD) MPMZM may also generate (COH or DD respectively) PAM4 or PAM2 (note: COH PAM2 = BPSK; DD PAM3 = OOK). Mode II programmable MPoDAC with variable splitter or combiner (matched taps) We exemplify our disclosure of mode-II optical reprogram ability for a BiWgt MPMZM oDAC initially designed as a COH PAM8 generator (the general case for any B is readily extrapolated from this B=3 embodiment). Starting with a 3-way MPMZM, nominally used as 3-bit (COH PAM8) BiWgt MPoDAC, the constellation size may be reprogrammed from PAM8 (B=3) down to PAM4 (b=2) or even BPSK (b=1), by setting new appropriate values for the split & combine taps of the three-path MPoDAC, adjusting the taps to extinguish light via some of the three MZMs. E.g., to switch from PAM8 to PAM4 we turn off the top MZM, nulling out the upper tap

in both the splitter and the c^{ombiner, while we distribute the light power in a 2:1 ratio to the remaining two paths, setting} ._{This taps-reconfigured 3-way system is ideally}

indistinguishable from a 2-way system with just two paths and with its 1:2 splitter and 2:1 combiner set to (note that in both cases the taps vector satisfy the unitarity condition). This

establishes that the 3-way system having its matched taps values switched from the

will accordingly switch from COH PAM8 to COH PAM4. If we wish to have this MPMZM switch to PAM2 COH, i.e. to BPSK 2-point constellation transmission, we simply reconfigure the tunable splitter and combiner taps to the values

i.e., in effect we turn-off the upper two MZMs, having all the light traverse the bottom MZM which acts as a phase-gate, i.e. a BPSK modulator. Thus, the 3-bit MPMZM optical layout of Fig.7B, nominally designed as a 3-bit MPMZM, is actually programmable, by means of modifying its electronics to switch to any of the following COH constellations, compactly written COH PAM-8|4|2 (here | denotes “or”):

One impairment especially degrading the quality of higher-order constellations is having an extinction ratio at the upper port which is not sufficiently low (due to imperfect setting not precisely

nulled out). Thus, a residual low-level modulated signal may leak from the upper path (which was supposed to be cut off) into the desired PAM4 signal generated at the mid-port and upper-port. This extinction ratio leakage is modelled as having the three taps be

) , with X being measure of extinction, equal the actual residual power ratio at the

upper port of the 1:3 when we command W ₂ = 0 at that port (note: this is a somewhat simplistic model, ignoring possible finite extinction at the mid-port and bottom port of the splitter as well, but the source of impairment is apparent). The imperfect extinction impairment, degrading the switched lower order constellation, may be alleviated by one of two methods: (i) by detuning the phase bias(es) of the MZM PG(s) (nominally supposed to be turned-off) to have null output, i.e. steering the residual light (leaking from the upper port of the 1:3 splitter) to the unused port of the MZM used as the PG of the upper path. (ii) by turning off the bipolar signal voltage driving the MZM used as the PG of the upper path. The rationale is that the PG model is (203) may be rewritten in more physical detail, using for the backoff factor the expression is the actual peak voltage driving the MZM (the actual

applied voltage is is the differential phase bias between the two arms of the MZM:

Thus, by reducing V _d down to null or close to it (method (ii)) or by tuning the MZM phase bias such that we would ideally null out the transfer factor through the

MZM, thus get no light at its output even when there is leakage of light from the splitter to the MZM output (note: to null out the MZM transfer factor, we may also aim fo ). Actually,

since neither of the methods (i) and (ii) may be perfectly tuned, both methods may be used in unison to compound their attainable suppressions of the residual leakage However, method (ii) may be harder to implement than method (i), since it requires complicating the high-speed mixed-signal driver circuitry, from having 2-state bipola drive voltages to having drive voltages (note: since the

tuning of the splitter and combiner may typically be relatively slow, of the order of 0. 1 — 1 msecwhich sets an upper bound on the reprogramming transient, a simpler way to turn off the voltage driver may be to disconnect the DC power supply to the fast electronic gates).

Mode II programmable MPoDAC with fixed splitter or combiner

We mention that the most effective reprogram ability is afforded when both the splitter and combiner taps are tunable, as we have heretofore used in our matched-taps designs. If either the splitter or the combiner is fixed (while the combiner or splitter are variable, respectively) we have seen that we may get a reasonable constellation (albeit somewhat degraded) relative to the matched-taps case, but for a fixed constellation size as treated heretofore. If we attempt to reprogram such device, e.g. one with a fixed splitter, for generating a constellation having fewer bits (a lower B-value), we must null out some of the parallel paths, i.e. but that is not possible from the splitter side (as we have assumed the splitter to be fixed). We may still null out the paths that need nulling out, but then the collection of light from the splitter will be less efficient. Thus, we conclude that such a device, with fixed splitter may still be switched to a lower-order constellation but inefficiently so. For example, let us model the programmability performance of the COH PAM8 MPoDAC, which was based on a uniform-split design (l:3 splitter with fixed-taps, , a 3: l combiner with tunable taps ideally

in the fixed-uniform split design. Evidently, we are not able to switch off either of the three paths by means of tuning the splitting ratios which are now fixed, . We may, however, select one of the

three paths, say the bottom one, as the one to be blocked at the tunable combiner, accepting a loss of a factor of power at the splitter (as the light split at the lower path, via the tap is wasted, since

the light in this path is to be blocked further downstream by setting the bottom tap of the combiner to null, and/or by turning off the MZM PG of the lower path by methods (i) and/or (ii) above (bias phase detuning and/or drive voltage nulling). In addition, to handle the useful light, both the splitter and combiner remaining taps (the upper and mid ones) are to be set in in a 2: 1 ratio, i.e. the taps of tunable 3: 1 combiner are set to the values whereas for the fixed uniform splitter we

evidently have The end-to-end transfer factors of the three paths (including

the splitter and combiner contributions, excluding backoff attenuation factor g of the PGs, i.e., taking g = 1 ) is then

The generated constellation is then

The full-scale is now which is -2.2 dB lower than the ideal

max-full-scale of 2. In contrast, in the case of the matched-splitter-combiner design of the programmable PAM-8|4|2 COH constellation generator, as disclosed above, we have 0 dB intrinsic max-full-scale loss, i.e., switching from PAM8 to PAM4 we remain at max-full-scale. We conclude that the programmable PAM-8|4|2 COH constellation generator with uniform-fixed-splitter, although feasible, it does not provide sufficient performance, falling 2.2 dB in full-scale under the alternative PAM-8|4|2 COH constellation generator with matched-splitter-combiner taps, which was seen to feature a max-full-scale constellation, thus constitutes our preferred embodiment for programmable PAM-8|4|2 COH. We conclude that to realize the constellation programmability, it is best to use both splitter and combiners which are tunable, rather than using a uniform splitter (or combiner). Nevertheless, the extra losses associated with reprogrammability may still be tolerable in certain cases. Thus, the optimal design methodology for programmability is to adopt here matched-split-combine designs for the optically programmable oDAC. Mode II programmable DD MPMZMs Let us now consider DD designs of programmable MPMZMs. For this case we disclose a similar methodology to that developed above for programmability of COH MPMZMs. Starting from a B-way BiWgt DD MPMZM generating a (B-bit) PAM-2^B constellation may be also developed for programmable DD MPMZMs. Here is an exemplary embodiment for B=3: G^{iven a 3-way BiWgt MPMZM with matched taps,}

designed for optimal PAM8 DD generation as in 5.5.3, we have three paths equipped with IGs (OOK modulators). We may also reconfigure this structure for PAM-4 DD and PAM-2 DD (which amounts to OOK) as follows: The three matched taps are then reconfigured (switched), away from the values disclosed in 5.5.3 to the following values, whereby the upper tap is taken null, to turn off the upper path, while the mid and bottom taps are taken to correspond to the optimal matched taps for a PAM4 D_{D constellation (}

If we wish to have this MPMZM switch to PAM2 DD, i.e. to an OOK 2-point constellation transmission, we simply reconfigure the tunable splitter and combiner taps to the values (W ₂ , W ₁ , W ₀ )= ( U ₂ , U ₁ , U ₀ ) = (0,0,1) , i.e., in effect we turn-off the upper two MZMs, have all the light traversing the bottom MZM which acts as an intensity-gate, i.e. as an OOK modulator. Mode-III programmability: Switching BiWgt MPoDACs between COH and DD Finally, we consider switching the 3-bit BiWgt MPMZM between programmable COH and DD PAM- 8|4|2 modes. An evident way to do this is to use a common 3-way MPMZM photonic layout, while equipping the driver electronics with the ability to switch between three states, {± V _d , 0}supporting both bipolar {± V _d } (for COH) and unipolar {0, V _d } (for DD) drives. In effect this reconfigures the 1-bit gate functionalities of the three MZMs between PG and IP. The settings of the matched taps for the respective COH and DD cases have already been described. We now have a full solution for COH|DD PAM-8|4|2 programmability (6 states in total). However, programmability solutions based on switchable ultra-high-speed electronics (having the drivers switch between {±V_d } and {0,V_d } ) are more complex and prone to impairment than a solution solely based on switching just the tap values in low-speed electronics (reconfiguring the taps values at kHz to MHz rates), while leaving the ultra-high speed electronics unchanged. Fortunately, in 5.5.4.1. we have already outlined a methodology to use bipolar drives (COH codes) for DD PAM generation. In the context of optical programmability, this enables performing the DD ^ ^COH reprogramming transient without affecting the high-speed electronics at all, just switching the MPMZM taps entirely at relatively low rate (kHz to MHz), reconfiguring just the oDAC taps within about a msec or less. The high-speed electronics continues operating based on bipolar analog drivers circumventing the need to switch between unipolar (for DD) and bipolar (for COH) drivers. We now detail the design of programmable MPMZM oDACs (solely driven by COH codes, no DD/COH code switching) which are most readily reconfigurable (reprogrammable) to switch between COH and DD constellation. This DD ^ ^COH reprogrammability methodology is applicable just for embedded systems. As a consequence, our target DD PAM or COH PAM programmable constellation orders are b-bits (2^b levels) with b ≤ B , (including transitions between DD and COH constellations of 2^b levels), yet we require a B+1-way MPMZM oDAC photonic structure, having one path unmodulated (acting as “optical bias” in the DD mode, while we deplete this path of light in the COH mode) while the other paths are all equipped with PGs to perform BPSK modulations (see the embedded MPoDAC concept in 5.5.4), enabling to switch between any b-bits COH constellation (which may

attain optimal max-full-scale performance by proper selection of its tap vector) vs. any b’-bits DD constellation, with b ^′ ≤ B (the DD constellation will be bounded to have an FS less than max-full- scale, but may nevertheless be optimized for maximin operation, attaining at the same maximin distance that a standalone embedded DD MPMZM system would attain). In any case in both the DD PAM-2^b and COH PAM-2^b modes of this reprogrammable system, we invariably use the COH binary code (even for DD) fed into the B bipolar electronic drivers (with the B+1-th path, say the top one, left unmodulated). Another even more flexible variant (albeit somewhat more complex as it requires an extra PG) of the MPMZM system just described, also uses just COH codes to programmably select to output either COH or DD constellations, but invests in adding an extra PG (relative to the previous variant above), replacing the unmodulated path by a BPSK modulated path, as well, such that now we have a total of B+1 PG modulated paths (such that the device appears as a standard B+1-bit BiWgt MPMZM). We are now able to operate this B+1-way device in two modes, transitioning between them on-the-fly: (i): COH PAM-2^b constellation generator (now with b ≤ B + 1). (ii): embedded DD PAM-2^b constellation generator (now with b ^′ ≤ B ). In COH mode (i), in case we aim for max constellation size, i.e., b = B + 1, we just use the BiWgt design as earlier disclosed in this work (setting the matched taps accordingly), whereas when we aim for a lower constellation order, i.e., b ≤ B + 1we just turn off B+1-b of the PGs, leaving just b of the PGs on (as disclosed earlier in this subsection, by nulling out the corresponding taps, optionally also by detuning the individual MZM biases to steer the light to the free port, optionally also by turning off the RF drives – the optional measures increasing the light extinction in the turned off paths). In order to switch to DD mode (ii), we digitally modify the COH code to consist of a B-bit COH counting code augmented by another all-ones column, such that the MSB (left-most) of each codeword be unity, such that the top path PG be now invariably driven by the MSB=1 bit, behaving as if it is unmodulated (we still reserve its ability to be modulated, to be used when switching to mode (i) again). In addition, we now input, for this mode (ii), the proper taps vector W _COHembDD (353), which is evaluated as shown there, in terms of the taps vector W _DDthat would have been selected in case we implemented a ‘straightforward’ B-bits BiWgt MPMZM. A specific example follows for B=3. This programmable MPMZM oDAC, reconfigurable for up-to-3- bit-COH/up-to-2-bit-DD , is based on a 3-way standard BiWgt COH MPMZM structure, i.e. having three parallel paths, each equipped with a PG (Figure 7A and 7B). When used in COH mode (i), it generates a 3-bit PAM-8 COH constellation as described in 5.3.4.5, while it may also be reconfigured as 2-bit PAM-4 COH generator by neutralizing one of the three paths (say the top one) or as a BPSK COH generator by neutralizing two of the three paths (using binary weighted taps active paths, whether there are three or two paths or just one). To reprogram the device to DD mode (ii), wherein PAM4-DD or OOK are the programmable sub- options, the driving bit of the upper path PG is set to unity (i.e., a fixed voltage bias V _d is applied to the upper PG). In order to configure PAM4-DD operation, the remaining two PGs are driven by the 2-bit bipolar counting code,{{-1, -1},{-1,1}, {1,-1}, {1,1}} (each codeword corresponds to a PAM4-DD level). We also need to reprogram the three matched taps to [0.663, 0.212, 0.126]. We may also reprogram the device to operate as an OOK generator by having the upper path PG set to unity (i.e., a fixed voltage bias V_d is applied to the upper PG), disabling one of the two remaining paths (just as described above for path cutoff in the COH mode) while using the third path PG as a BPSK modulator (i.e. bipolarly driven by the {±1} code). The key to intuitively, grasp how BPSK modulation may generate OOK, is the role of bias light from the upper path that is unmodulated, “lifting” the BPSK field to unipolar OOK. In terms of the taps setting for DD OOK operation (driven by the bipolar {±1} code) we have (assuming the actively modulated path is the bottom one – in case

the actively modulated path is the mid one we then use the taps . In any case we

neutralize one path, have one path as CW bias and have one path BPSK modulated ). Note: The tap values here may be shown to formally be a special case of the general B-bit embedding , as treated in 5.5.4, however, the intuitive CW-bias based explanation above is more illuminating. To wrap-up this subsection on 1D PAM DD/COH constellations, we note that the programmability of the prior-art SEMZM oDACs is much more limited, due to the fact that in that system there is no easy analog for the capability of tuning MPoDAC taps, on-the-fly. To tune the differential phase contributions of MPMZM segments, the only recourse is modifications of the peak drive voltages, but that is difficult to implement at ultra-high-speed (and costly to duplicate the electronic attenuator HW for all segments). The comments above pertain mainly to non-ThWgt BiWgt SEMZM (e.g. BiWgt SEMZM). For ThWgt SEMZM, the tunability of the constellation size is easier, by turning off the ultra- high-speed drivers to certain of the multiple SEMZM segments, but the drawback may be that the ThWgt has many more segments, thus the electronic overhead of variable attenuators in the RF path, for tuning the phase, may be excessive. Enhanced performance of programmable modes-II,III by shutting down in 1-bit gates We mention that the performance (constellation quality) of reprogrammable modes II and III may be enhanced by optionally taking additional measures beyond the retuning of the split and combine taps, as described above. In addition, we may cut off the RF path of certain of the MZM PG or IG drivers (those belonging to the paths of which need to be disabled in the course of “constellation demotion”) and/or optionally detune the MZM to steer its residual modulated light to the free output port of each MZM PG or IG driver). Doing so for all the 1-bit gates in all the paths would actually results in nulling out (turning off) the MPoDAC output. In fact this may be augmented by setting just one of the taps of the splitter and combiner to unity and making sure that the respective taps nulled out in the splitter and combiner do not have identical indexes. This ‘total shutdown’ capability is also useful for enabling the ability to shut-down the MPoDAC output (without turning off the CW light source). Mode-I reprogrammability: modifying the constellation shape at fixed number of levels. Further to programming oDAC resolution ( b ≤ B ), the shape of the QAM constellation is also programmable (this was referred to as Mode-I programmability) by fine-tuning the split / combine ratios and possibly the peak drive voltages. Moreover, for any b ≤ B , we may reconfigure the oDAC output characteristic, reprogramming any 1D constellation with S=2 ^b points which are either ‘regular’ (equi-spaced) bi-polar symmetric ones, or are nonuniformly distributed, specifying offsets and nearest- neighbor separations. Thus, the locations of the constellation points along the optical field axis may be varied, to possibly realize or best-approximate the desired non-linear oDAC response (e.g. to compensate for some other nonlinearity in the system). However, it will become apparent that positions of the constellation points are not entirely amenable to arbitrary specification, as there are mathematical constraints imposed by the multi-parallel binary weighted structure which may not be satisfied. We have seen that these constraints may be relieved, in principle, by adopting a thermometer-weighted (ThWgt) multiparallel structure, at the expense of increasing the MPoDAC complexity by requiring more paths and also requiring additional digital electronics (a B:S encoder to generate the thermometer code). Multiplexing of 1D (PAM) programmable constellation generators Once the programmability of a single carrier MPoDACs is enabled, it is useful to combine multiple degrees of freedom in order to multiplex, i.e. aggregate multiple programmable PAM signal tributaries, (each tributary being generated out of pairs of IQ MPoDACs, as described above) in order to obtain highly flexible variable rate optical signals. We may multiplex programable PAM tributaries via Wavelength Division Multiplexing (WDM), and/or Frequency Division Multiplexing (FDM), i.e. sub- carrier multiplexing, and/or Spatial Division Multiplexing (SDM), and/or Polarization Division Multiplexing (PDM) (also known as Dual Polarization Multiplexing (DPM). We may also directly multiplex 1D MPoDAC -generated PAM signal tributaries (be they COH or DD) onto these multiplexing DOFs, e.g. modulate independent PAM-2^B MPoDAC 1D constellations onto multiple CW subcarriers of different frequencies (FDM), or inject two independent PAM-2^B MPoDAC 1D constellations onto the X and Y polarization components (PDM), or inject independent PAM-2^B MPoDAC 1D constellations onto multiple cores of a multicore-fiber (SDM). Another degree of optical multiplexing, not listed above, is (quadrature) phase multiplexing. The phase degrees of freedom, the I and Q quadratures, are the multiplexed physical quantities in this case, which deserves special attention and is treated in the next subsection. Programmable optical QAM generators – by IQ muxing 1D MPoDACs To generate C²-QAM (with C=2^B), for COH transmission, we may provide IQ-multiplexing a pair of our MPoDACs, each generating C-PAM COH. The two MPoDACs are IQ-nested via a 1:2 splitter and a QMUX combiner, as shown in figure 39, to generate 2^2B-QAM by having the two IQ tributary PAM- 2^B COH fields superposed in quadrature (with 90^o phase difference). This QAM-generator structure will be referred to here as ‘IQ MPoDAC’. In particular 64-QAM may be optically generated by an IQ MPoDAC comprising a pair of 3bit BiWgt COH MPMZMs, each generating PAM-8 COH, combined in quadrature via a QMUX. As soon as the two IQ-nested MPMZMs are made programmable, the size of our QAM constellation may then be reconfigured by using suitable electronics (to tune the splitter/combiner taps, and optionally to shut down individual PG gates of the two IQ tributary PAM COH oDACs. Here we disclose how an IQ-MPoDAC photonic structure designed to generate 2^2B-QAM may have its ancillary electronics equipped to enable programmability in the two IQ tributary MPMZM, in order to be able to switch back and forth to lower-order QAM constellations. We have already shown in the last section how to make the PAM output of a single B-way MPMZM “resolution-programmable” in the sense of reconfiguring any of the constellations PAM-2^b, b=1,2,…,B. For reprogrammability of the PAM COH constellation size, the ancillary electronics should enable retuning the split and combine taps and optionally shutting down the RF path of some of the MZM PG drivers and/or optionally detuning the MZM to steer its residual modulated light to the free output port of each MZM PG driver. This is the electronic enablement required to convert a fixed COH PAM-2^B MPoDAC into a COH PAM-2^b one (for b=1,2,…,B). We disclose here such MPMZMs, each being electronically enabled to be reprogrammed to generate PAM-2^b (b=1,2,…,B), are IQ-combined to generate programmable 2^2b-QAM constellations (for b=1,2,…,B - with B the number of parallel paths in each of the two I and Q MPoDACs). E.g., having a pair PAM-8 COH MPMZMs IQ-nested via a 1:2 splitter and a QMUX combiner, once the two I and Q MPMZMs are electronically enabled to switch among PAM-8, PAM-4 or PAM-2 (=BPSK) (all three being symmetric coherent constellations, in the PAM COH sense defined in this work), then their IQ- nesting yields either 64QAM or 32QAM or 4QAM (which amounts to QPSK). To recap, the structure of figure 39, specialized to B=3, and equipped with suitable electronics becomes and agile 64|16|4- QAM IQ-MPoDAC (where 4-QAM means QPSK). Back to the generic 2^2B-QAM IQ-MPoDAC, electronically equipped for programmability, we have just seen that the QAM constellation that may be generated this way are sized 2^{2 b} , with for b=1,2,…,B e.g. QPSK, 16QAM, 64QAM, 256QAM… . But how about 8QAM, 32QAM, 128QAM, 512QAM? In order to generate 2^2b-1-QAM, B-2,3,4…, we use a 2^2b-QAM, (with b=1,2,…,B), programmable generator (as disclosed above), but have its electrical driver system preceded by a digital encoder to ban certain 1D symbol combinations in the two PAM-2^b MPoDACs working in unison, thus providing the mapping from the integer index labeling each of the constellation symbols, 2^{2 b −1} to the pair of indexes labeling the 2 ^b levels of individual I and Q PAM MPoDACs. In simple terms, to generate 2^{2 b −1}-QAM, certain combinations of levels of the two I and Q PAM MPoDACs (in fact, half of them) are removed. It follows that we may generate, in principle, using a pair of our B-way MPoDAC tributaries (having B parallel paths with PGs in each), QAM constellations of order 2 ^β , β = 2,3,4, ... ,2 B − 1,2 B , i.e., 4|8|16|32|64|128|256|…-QAM. Generating the orders 8,32,128,… require an encoder, the orders 16,64,256,… do not (these QAM constellation sizes just require Direct Binary Drives applying the codewords directly to the two BiWgt IQ tributary MPMZMs), thus we may arrange for a bypass in the digital encoder, when needed to switch to these constellations, engage the encoder back when the orders 8,32,128,..., are needed. Moreover, we may utilize various types of optical degrees of freedom for multiplexing programmable QAM signal tributaries, (each tributary being generated out of pairs of IQ MPoDACs, as described above). Thus, we disclose multiplexing our programmable QAM tributaries via either Frequency Division Multiplexing (FDM) and/or Spatial Division Multiplexing (SDM) (e.g. multiple modes or cores of an optical fiber) and/or Polarization Division Multiplexing (PDM) (also known as Dual Polarization Multiplexing (DPM), e.g. consider Fig..40 (top), specializing it to PDM-64QAM (i.e. B=3 bits for each of the four MPMZM MPoDACs) based on four nested MPMZMs each with 1|2|3-bits, i.e. four such IQ-XY multiplexed lanes exhibit a programmable aggregate spectral efficiency of 4|6|8|10|12bits/symbol. The first two lanes are IQ-multiplexed via a QMUX to generate two 64QAM tributaries. These two tributaries are then polarization-multiplexed. This could be the basis for a highly efficient agilely-programmable coherent optical transmitter: it is energy-efficient, as it operates with direct-binary-drive, thus eliminating the need for electronic DACs or other forms of less efficient oDACs; it is optical power efficient as we have shown that there is no intrinsic loss for COH constellation generation with MPMZMs. It is spectrally efficient when promoted to use all MPoDAC multipath resources, but it may trade off spectral efficiency for optical power efficiency, i.e., OSNR by demoting the constellation size via the agile programming. The constellations quality is high since the 1D (single quadrature, single polarization) COH MPMZMs intrinsically operate to generate ‘perfect’ max-full-scale field domain 1D PAM COH constellations. Another interesting feature of this MPMZMs based PDM-64QAM transmitter is that its calibration and testing is facilitated by the capability to completely turn off one or more or all of the four single- quadrature-single-polarization lanes (the four COH PAM-8 MPMZMs. Heretofore, for programmability of MPMZMs we have not had the need to turn off all MZMs at once, but here we disclose that this might be achieved, with high extinction ratio, as follows: The 1:B splitter is retuned to have all the input CW power steered to one of its taps, say the top one, which is set equal to unity; the other taps are then necessarily null, ideally. The B:1 combiner is set to have just one of its taps set to unity, provided that this combiner tap is not connected to the same path leading from the splitter tap that was set to unity. Say, the combiner tap set to unity is the bottom one. This ensures that any path is either fed from or feeds into a zero tap. Optionally, we may also steer the modulated optical power of each MZM-based PG to the free port of the MZM, and/or turn off the RF drive to each of the MZM-based PGs. This output shutdown capability has already been described for 1D constellations in 5.10.1.5. Here this is applied to the I and Q tributary MPoDACs. Another aspect disclosed here is programmability and/or modular manufacturing enablement at the top subsystem level, e.g. on-the-fly converting the PDM-QAM transmitter into a quad of DD PAM-4 independent transmitters. Since we are now able to either turn off each one of the four lanes, or turn off pairs or triplets lanes at a time, we may perform testing and calibration of the individual quadrature MPMZMs for individual X or Y polarizations. In effect this is an additional form of programmability, enabling to switch from either dual polarization QAM to single polarization QAM or to any of four independent PAM I or Q tributaries of the two polarizations for the purpose of testing or calibrating them independently. Our scope is single-carrier scheme, and the [Y]-scheme depicted in Figure 40D is also a single-carrier one. We note that beyond single carrier embodiments, the [Y]-scheme also comprises embodiments intended to perform Frequency Division Multiplexing (FDM) or WDM of multiple C-QAM signals (C=4,8,16,32,…). However, these multi-carrier embodiments are outside our comparison scope, which is single-carrier optical constellation generation - in each of our embodiments, all our MPoDACs are assumed to have their optical input fed by a common CW monochromatic (single-frequency) signal. To recap, figure 39 illustrates a QAM scheme generation in which the modulator arrays are proper BPSK ones (in our I and Q tributary 1D COH PAM MPoDACs), and not a QPSK one. The QAM generator scheme just uses a single QMUX multiplexing two MPoDACs wherein each of which there is a modulator array of BPSK modulators that are all summed up in-phase w.r.t. one another, in each of the I and Q tributaries MPoDACs that are quadrature-multiplexed. In the MPoDACs-based QAM generator, the QMUX is performed at the very end, after the two individual PAM-8 I and Q tributaries have been generated (with B:1 combiners, internally). The power combining taps of the B:1 splitter(s) as well the B:1 combiner(s) used in both schemes should be BinaryWeighted in the sense that they must form a geometric series. We have seen this in the case of a single PAM-8 MPoDAC. Multi-bit (multi-level) Optical Gates (OG) We now disclose an oDAC generalization, referred to as Multi-Level (ML)-driven Multiparallel oDAC (ML-driven MPoDAC) whereby the multiple parallel paths may contain multi-bit OGs. The term 1-bit Optical Gate (OG) was originally coined in this invention to describe a two-level optical modulator, be it an Intensity modulator, OOK (referred to here as intensity gate (IG)) or a phase modulator, BPSK (referred to here as phase gate (PG)). The disclosed Multi-Parallel oDAC essentially consisted of an interferometer with S-paths, each comprising a 1-bit OG. Let us now extend the 1-bit OG concept to a multi-bit (or multi-level) OG defined as means to have the input lightwave modulated to one of _{C G} discrete amplitude levels, as actuated by a string of _{β G} bits, referred to as the ‘driving bits’, forming the OG-code. The original 1-bit OG features _{β G = 1} ^{bit, and} _{C G = 2} levels, but a ‘proper’ multi-bit OG is driven by an OG-code comprising at least two bits, i.e.,_{β G ≥ 2} ^and _{C G ≥ 3} ^{. A generic multi-bit OG, including the 1-bit OG as a special case, is defined as} having _{β G ≥ 1} ^and _{C G ≥ 2} ^{. The special case} _{β G = 1} ^, _{C G = 2} ^{retrieves the single-bit OG, introduced in} previous disclosed embodiments of the invention, namely either the Intensity Gate (IG) for DD or the Phase Gate (PG) for COH. Thus, a multi-level OG includes the two-level (1-bit) OGs, namely our earlier introduced ‘phase-gates’ and ‘intensity gates’ as special cases. The code length, in bits, is obtained denoting the ceiling operation. In

particular, we are interested in embodiments based on ‘dyadic codes’ whereby _{C G} ^{is an integer power-} ^{of-two, C} _G ^{∈ {2,4,8,16, ... }, in which case,} _{β G =log 2C G ≥ 1} ^. The ‘multi-level OG’, may be equivalently referred as ‘multi-bit OG’. A ‘proper’ multi-bit OG is an optical modulation means driven by 2 or more actuating bits Sophisticated ML-driven OGs e.g., 3-level OGs for duo-binary generation are feasible and useful for optical transmission with direct-detection, as a replacement for our 1-bit plain Intensity Gates. A 3- level OG is driven by β _G = ⌈3⌉ = 2bits (its 3 levels are in one-to-one correspondence with by 3 of the 4 possible bit pairs). However, in the sequel we focus in particular on usage of ‘dyadic’ ML-driven OGs, wherein C _G = 2 ^{β G} , β _G ∈ Integers, i.e., these OGs generate 4,8,16,… levels, as actuated by 2,3,4,… bits. Hardware-wise, the multi-bit OG includes the modulation means plus its particular driver. Those two elements, together, are considered to constitute the OG (thus, the OG is actually an Electro-Optic-Gate driven by multiple electrical levels to generate a discrete optical output. In the simplest form an OG consists of a simple modulator (MOD), in particular an MZM, and a multi-level electrical driver. The electrical multi-level signal driving the MOD to generate _{C G} ^{discrete optical levels, is referred to in the} communication literature as Pulse Amplitude Modulator (PAM), and the generated waveform is PAM- C _G , an electrical signal with C _G electrical voltage levels. Since we now deal with PAM signals in both the electrical and optical domains, it is useful to distinguish between them by adopting the nomenclature of ePAM (electrical PAM) and oPAM (optical PAM). E.g., an MZM-based multi-level OG is essentially an MZM driven by an ePAM signal, such as to generate a corresponding oPAM signal of the same order (number of levels). In these definitions the multi-level OGs may be based on any modulation means + electrical PAM driver that is electrically driven by a string of bits to generate multiple optical levels. The modulation means may be either a simple modulator, such as an MZM or EAM, driven by an ePAM signal, or a compound oDAC structure and its driver, e.g., one of the oDAC structures disclosed in this invention (including the structures disclosed in this section, i.e., the OG definition is recursive). Multi-Level-driven MultiParallel oDAC (ML-driven MPoDAC) Let us now disclose and define the ML-driven MPoDAC, as a multi-parallel oDAC with S ≥ 2 paths, where the paths have general structure as the ones disclosed heretofore (in the case of 1-bit OGs), albeit having the 1-bit PG or IG in at least one of the paths replaced by a proper ML-driven OG . Thus, at least one of the S paths must have its field modulated to more than two levels (the rest of the paths may have their fields modulate to two levels or more). For dyadic MPoDACs proper ML-driven PAM- OG(s) use 4, 8,… levels, thus at least one of the parallelized OGs is has to have its number of levels from the set {4,8,…}, whereas each of the other OGs have a number of levels from the set {2,4,8,…}. E.g. for a are valid level-counts for the four

parallelized OGs. The corresponding bit-counts are . The code is the 7-bits

binary string , partitioned into sub-codes of lengths , with

each subcode driving one of the four OGs (the substrings of the sub-codes are delineated by dots for clarity). For an ML-driven MPoDAC wherein the OG in the s-th path generates C _s ≡ 2 ^{β s}-levels oPAM , assuming that the device be designed such that all output levels of the multi-level driven MPoDAC are d^{istinct (do not coincide), then the total number of output optical levels is}

T_{hus, the levels of each path get multiplied, whereas the bits-per-path contributions get added up:}

In particular, for S=2, (i.e., two paths, two-way ML-driven MPoODAC) the rule for parallelizing the pair of multi-level OGs is (with ‘||’ denoting ‘in-parallel with’): oPAM[ C ₁]||oPAM[ C ₂] = oPAM[ C ₁ C ₂]. In words, having the two paths comprise OGs generating ^{optical levels each (e.g. a pair of}

MZMs driven by respective RF PAM signals with C ₁, C ₂electrical levels, the ML-driven oDAC then generates optical PAM at C = C ₁ C ₂levels. The corresponding bit-counts describing the two partial RF DACs are . Thus, one path (driven by one

of the RF PAM drivers) contributes β ₁ bits, the other path (driven by the other RF PAM driver) contributes ^^^^₂bits, such that the overall optical PAM generator features β ₁ + β ₂ In fact, this rule is valid even if one or both paths are actually realized as compound oDACs, in particular ML-driven- oDACs. All MPoDACs comprise a photonic circuit and an electronic driver circuit. Some examples of the ML- driven MPoDACs and a general case are depicted in Figures.43- 44. Figure 43 and Figure 42 depict a S=2 (two-way, i.e. two paths) realization, Figure 43 depicts the general S-paths case and Figure 44 depicts a 3-way realization. The drivers in this systems are assumed agile (reconfigurable), such that the generated ePAM orders may be electronically reprogrammed in hardware, e.g., the drivers in Figure 43 and Figure 42 consist of ePAM generator pairs which may be independently reconfigured as either PAM2 or PAM4 (compactly denoted PAM2|4, where ‘|’ means OR). As visible in the figures, and more generally for all our ML-driven MPoDACs, their photonic structures comprise (just like their earlier counterparts based on 1-bit gates) means to split the input light into the S-paths (1:S-split), means to combine the light of the S-paths (S:1-split); moreover, in at least S-1 of the paths (preferably in all S paths) means are provided for slow phase modulation and possibly multi-tone phase dithering means, in order to bring all paths in a definite phase relationship, typically in phase, but it is also possible to bring some paths in anti-phase, to the others, i.e., to have their relative phases flipped 180^o relative to the other paths (using anti-phase in some path amounts to reversing the sign of

^{for dyadic versions).} In fact, all the considerations in optical modeling of the MPoDACs and their operational use of the , carry over here from MPoDAC based on 1-bit OGs to the MPoDAC variants based on multi-level OGs. In particular, the most useful photonic designs are obtained by setting and maintaining the oDAC parameters such as to achieve the following conditions: (i) Coherent addition of fields of the S-paths in the S:1 combiner. (ii) matched splitter-combiner design: The optical-power split/combine ratios ^{(referred to as ‘taps’ ) of the 1:S and S:1 are identical:}

^{. Note: In idealized design the} unitary constraint ^{is used. The field transfer factors for the 1:S and S:1 are then also}

_{matched: . (iii) Optimization be performed over S-1 of matched-taps W s}

(unitarity makes one ratio redundant). E.g., if S=1 it suffices to optimize over the _{W 1} ^parameter. The structural specification of the multi-level driven MPoDACs (e.g., as in the figures) must be augmented by a parametric specifications: (i) the overall target oPAM constellation of the MPoDAC and whether it is for DD or COH. (ii) the optical amplitude levels to be generated by the constituent multi-level OGs (the oPAM constellations for each OG) (iii) the optimal setting of the MPoDAC splitting and combining ratios _{{W 1 , W 2 ,..., WS − 1 }} ^{. It may then be analytically or numerically verified that} at least the inherent (subject to ideal conditions) physical model for the topological structure generates useful constellations of output levels. ‘Perfect’ Non-negative (PNN), DD, COH PAM – optimal levels & taps Heretofore we have not specified the multi-level (i.e., PAM) constellations involved in these descriptions (apart from labeling them as electrically generated (ePAM) or optically generated (oPAM), which is an operational distinction). We further distinguish between Nonnegative (NN) PAM (with all its levels non-negative) and Bipolar (BI) PAM with its levels real-valued of any sign (some levels non- negative, other levels negative). Optical fields are generally complex-valued but since the disclosed MPoDAC brings all fields in phase or in anti-phase, thus after undergoing phase alignments and derogating the common phase, the fields are real-valued. respectively. There are two optical transmission modes, either use Intensity Modulation with Direct Detection (IM- DD simply abbreviated here DD) or use Coherent detection (COH). The optimal DD and COH

We have already seen in our treatment of MPoDACs with 1-bit gates, that, surprisingly, PNN constellations, despite being ‘perfect’, are not actually useful to generate for transmission with Direct- Detection (DD). The non-negativity of these constellation befits DD, but the fact that the optical field PNN constellations are equi-spaced is actually non-optimal for DD, since the optimal DD constellation is actually equi-spaced and full-scale in the intensity (optical power) domain. But the MPoDAC devices are coherent ones, always superposing fields in-phase or possibly in anti-phase Therefore, a PNN constellation in the power-domain must be mapped back to underlying field levels by taking the square root. E.g., a DD PAM8 ideal constellation in the field domain would be obtained:

_{-bits code of respective lengths} ^{, there are C = 2 β possible}

codewords corresponding to the levels of the output oPAM constellation. It is useful to relate

the codewords to the sub-codes generated by each of the S OGs. Let the β bits of the MPoDAC be marked by the OG they belong to (using bracketed superscripts, ^{(s )} , whereas all bits are contiguously counted from right to left, starting with 0 and ending up in :

Finally, the reconfigurable structure (Figure 43) is also capable of being reprogrammed to generate opt PAM16, by parallelizing two PAM4 driven OGs to tile up four copies of the ₁ ³ 5_PAM4 , each of span 3- LSB-intervals (LSBs referred to the target PAM16 constellation) by applying successive shifts of 4- LSB-intervals (the effect of the outer sum with the . The drivers for the bottom and top

OGs are now both configured such as to drive both OGs by independent RF PAM4 signals. The power s^{plit/combine matched taps for this option are set to .The field taps of the matched} ^{splitter/combine are then}

^{. Another option may involve a provision of an RF} PAM8 generator for one of the paths in Figure 43 (which may be strenuous upon electronic technology for energy-efficient ultra-high-speed drivers for datacenters) or alternatively adopt the topologies as depicted in Figures 43 and 44. E.g., Figure 44 is obtained by recursively using our opt PAM8 ML- driven-MP oDAC, as the OG of the top path, whereas the bottom path is driven by a PAM2 generator (i.e., we have a 1-bit OG in the other path). Other examples of Multi-Level driven MPoDAC (ML-MPoDAC) to be potentially developed per this invention, may be based on relatively low count number of levels per path and on a low count of parallel paths. The least complex, preferred embodiments to be realized in a technology evolution scenario, are depicted in Figure 43 for the fast data path level and in Figure 42 for the control level, for the two-way ML-MPoDAC, and in Figure 44 for three-way ML-MPoDAC, whereas Figure 43 depicts a generic architecture with S paths. The disclosed architecture enables making these oDACs reprogrammable (reconfigurable) if any combination of ePAM2 or ePAM4 drives is allowed for the individual multi-level OGs, i.e., if the paths are driven by reconfigurable ePAM2|4 electrical (RF) generators. Another example of ML-driven MPoDACs with PAM2|4 drivers The case when all OGs are driven by PAM2 electrical signals reproduces the 1-bit-OG based MPoDACs. There is provided a 2-way ML-MPoDAC (S=2 paths) driven by a pair of RF PAM2|4 generators. An ePAM4 generator is a 4-level electrical DAC, actuated by a pair of bits specifying the four PAM levels, which may be either unipolar (for DD) or bipolar (for COH). An ePAM2 generator is just a two-level driver (the levels may be unipolar {0,1} or bipolar, {-1,1}, in normalized form). ePAM2|4 generator is any prior art agile DAC that may generate either four levels (in response to codewords 00, 01,10, 11 for example) or just generate the two extreme (MSB and LSB) levels, if the actuating bit-pairs are restricted to only 00,11, i.e., just the MSB and LSB are transmitted. Thus, the structure disclosed in Fig. 43, 42 features a reconfigurable, ML-driven MPoDAC, flexibly re-programmable on-the-fly to generate PAM4|8|16 as follows (here ‘||’ denotes ‘in parallel’, i.e., two paths): ePAM2 || ePAM2 → oPAM 4 [ C 1 , C 2 ] = [2, 2] ∴ C = 2 ⋅ 2 = 4 levels ePAM2 || ePAM4 = oPAM 8 [ C 1 , C 2 ] = [2, 4] ∴ C = 2 ⋅ 4 = 8 levels ePAM4 || ePAM2 = oPAM 8 [ C 1 , C 2 ] = [4, 2] ∴ C = 4 ⋅ 2 = 8 levels ePAM4 || ePAM4 = oPAM 16 [ C 1 , C 2 ] = [4,4] ∴ C = 4 ⋅ 4 = 16 levels The oDAC is driven by a pair of independent RF PAM2|4 electrical units (typically in a mixed-signal ASIC referred to as driver, which may include RF amplification for the modulators of the OGs). ePAM4 drivers, which are ‘reprogrammable’ to be reconfigured on-the-fly between ePAM2 and ePAM4, are readily realized starting from a PAM4 DAC core. E.g., if 00,01,10,11 bit-pairs activate the generation of the four PAM levels (say, sorted in increasing order) then simply not feeding the 01, 10 combinations to the PAM4 unit has it effectively converted into a PAM2 driver (at the same full-scale), as the LSB and MSB levels are then generate. As in the earlier disclosed 1-bit based MPoDACs, a slow digital controller should be provisioned to supervise the integrity of the coherent combination of paths in a prescribed ratio (set the slow phases for coherent optical superposition, and set and stabilize the split/combine ratios), ensuring that imperfections in the optical combination minimally degrade the DAC staircase linearity (uniformity). The preferred modulators used in the ML-driven MPoDACs are of the MZM type, in which case we refer to the resulting oDACs as ‘ML-driven MPMZM’. For the MZM (in fact for other types of modulators as well, e.g. EAM) the modulator transfer characteristic is nonlinear. Therefore, generating electrical PAM levels to generate prescribed optimal constellations for the OGs of the various paths requires accounting for the sine-shaped nonlinear characteristic of the MZM (this issue, is associated with multi-level operation but does not arise in the earlier disclosed MPMZMs based on two-level OGs). The driver technology most suited for this application (in fact for conventional generation of a multilevel optical signal by a multilevel DAC) must then have the ability to tune or ‘tweak’ the electrical levels of the constellations driving each of the OGs in the ML-driven MPMZM. Evidently, a single ML-MPoDAC device generates the optical multilevel constellation for one optical transmission lane at a time. Multiple ML-MPoDACs may be arrayed in parallel to generate multi-lane signals to be multiplexed over wavelength and/or polarization and/or or optical quadratures. E.g., IQ- nesting a pair of ML-MPoDACs of the same order of their output optical PAM constellations a QAM signal would be generated. Interestingly, the structure of the two-way ML-driven oDAC of Fig 43 is akin to an IQ modulator. In fact, we may flexibly reprogram the device of Fig 43 to cease its PAM generation functionality and generate instead QAM4 (QPSK) and QAM16 COH constellations. This is simply achieved by tuning the relative phase between the two paths to be 90^o rather than 0^o (or 180^o) and tuning the input and output splitter/combine to 50-50 (3 dB) settings. The selection between QAM4 and QAM16 is then activated by switching the ePAM drivers from ePAM2 to ePAM4. Optimized DD constellation generation using the ML-driven-MPoDACs The resulting constellations, heretofore generated in the descriptions above, have been a unipolar (non- negative, equi-spaced), which are of theoretical value. Inspection of ideal DD field constellations indicates that in order to obtain reasonable quality constellations for DD it is imperative to deviate from the equi-spaced constellations paradigm (i.e., not actually generate PNN constellations for DD). In the case of PAM8 DD generation, we should design an RF constellation by theoretically assuming adjustable levels to be optimized, along with the taps which no longer have the values evaluated for the PNN and COH cases :

Although the RHS is an 8-vector (as generated by the outer-linear-combination of a 2-vector and a 4- vector) and there are 2+4+1=7 parameters to optimize in the RHS (which is a nonlinear function of these parameters, thus we do not have enough degrees of freedom. Moreover, eight equations equating corresponding elements on both sides are nonlinear. An optimization criterion should not be getting the two 8-vectors on the RHS and LHS close to each other (e.g., in the mean-square sense), but it is rather maximizing the minimal distance of the constellation, a maxi-min problem as amply explained in the case of 1-bit gates based MPoDAC. The optimization should be conducted over the 4 levels of the adjustable PAM4, the two levels of the adjustable PAM2 and one tap (7 parameters totally). The quasi- optimal methodology one disclosed in this proposal for the MPoDACs based on 1-bit OGs carries over to this case (though the mathematical model is different now): the minimal distance of the constellation is to be maximized over the optimization parameters. The mathematics of such optimization will not be pursued here. Fortunately, the optimization of the taps does not impact the topology of the ML-driven-MPoDAC itself. In particular, the photonic layout structures of Fig 1-4 are suitable for both DD and COH optical PAM generation, irrespective of the optimal tap parameter (which are different for DD and COH, they are only identical for PNN and COH). The only difference is generation of either unipolar or bipolar ePAM RF signals in the two drivers. It is possible to combine the two types of signals in a single driver with parallel ePAM4 DD or COH circuit units, to dually serve both DD and COH DD ML-driven MPoDACs. MPoDAC tradeoffs between using single-bit and multi-bit OGs Finally, let us compare MPoDACs (MP-MZM) in particular, based on single-bit OGs vs their counterparts based on multi-bit OGs. For a given order, say PAM16, the single-bit MPoDAC disclosed ^{design requires having} _{log 216 = 4} ^{parallel paths. The splitter and combiner are now 1:4 and 4:1, i.e.} there is a higher optical and taps control complexity than the two-path solution driven by two ePAM4 generators (and the misalignment impairment of contributed by the four optical paths is expected greater than that of in two optical paths case). On the other hand, four ePAM2 generators are much simpler (and have lower electrical power consumption altogether) than a pair of ePAM4 generators. We conclude that the single-bit vs. multi-bit OGs tradeoff implies tradeoffs between electrical and optical complexities, and different levels optical power consumptions. Nevertheless, since the generation of ePAM4 has matured in recent years, the usage of two ePAM4 generators while reducing the optical complexity to just two-paths may represent a sweet-point of the optical-electronic tradeoffs at this point. As experience is going to be accrued on realization of 1:S and S:1 tunable split/combine functionality, the tradeoff may evolve in favor of the single-bit OG based solutions. Figure 47 illustrates an example of method 470 for optical digital to analog conversion. Method 470 may include a sequence of steps 471, 472, 473 and 474. Step 471 may include receiving an input optical signals. Step 472 may include splitting, by a combiner, an input optical signal to multiple path input signals. Step 473 may include optically processing, the multiple path input signals, by the multiple optical paths, in parallel to provide path output signals. Step 473 may include applying optical modulation by optical gates of the multiple optical paths and under a control of multiple electrical modulators, to provide optical signals having a value selected out of multiple constellation levels. Step 473 may include at least one out of: (a) Preprocessing, before the optical modulation by the optical gate, the input path signals.(b) Post-processing the output signals outputted from the optical gate. The pre-and/or post processing may include amplifying and/or attenuating and/or phase amendments and the like. Step 474 may include combining, by a combiner, multiple path output signals that may be outputted from the multiple optical paths to provide an oDAC output signal. The values of the oDAC may be values of a single quadrature constellation. Method 470 may include one or more of the following steps: (a) Step 481 of configuring the optical gates to operate while driven by electrical modulators as phase gates or as intensity gates. (b) Step 482 of measuring, by a measurement circuit, different signals within an optical digital to analog converter that may include the multiple optical paths. (c) Step 483 of tuning, by a tuning circuit, phase differences between different optical paths. (d) Step 484 of tuning, by a tuning circuit, the splitter and the combiner. (e) Step 485 of compensating for temperature induced drifts and for compensating for acoustically induced disturbances. (f) Step 485 may include compensating for temperature induced drifts at a first compensation frequency and compensating for acoustically induced disturbances at a second compensation frequency that may be at least one hundred time bigger than the first compensation frequency. SEMZM oDACs serially accumulate the binary-modulated optical phases induced in each of the modulation segments to form multilevel phase-domain samples, to be mapped, via optical interference, into multilevel optical amplitude (or power) levels arrayed in an Optical Constellation (OC). PAM4 SEMZM analytical model for DD and COH

When the electrical drive scheme for the SEMZM modulation segments ensures no-chirp, the OC field levels are real-valued. Physically, the argument of the sine models the phase accrual over the two m^{odulation segments, which individually contribute phases for DD OC generation, and}

Optimization of the PAM4 DD constellations using the Segmented MZM serial oDAC We are now ready to optimize the DD PAM4 constellation over the power-domain NN distances between the OC power levels. We adopt min-distance (MD) as the PAM4 OC figure of merit to optimize over, since Bit Error Rates (BER) over the optical transmission link is dominated by the least of distances between Nearest Neighbors (NN) pairs of OC levels, the so-called Minimal-Distance (MD). As the two NNs spaced at MD are the ‘weakest link’ of the OC, predominantly degrading BER, it makes sense to maximize the MD. Thus, we adopt ‘maximize-MD’ or in brief ‘maximin-distance’ as our oDAC optimization criterion, which turns out analytically tractable for PAM4. It is beneficial to maximize the OC Full-Scale (FS). For a ‘dyadic’ SEMZM designs, modulation backoff is counterproductive (as far as BER is concerned), despite seemingly improving oDAC linearity). It is preferable to have the OC stretched to its max-full-scale (assuming power consumption may be afforded). A max-full-scale constraint is then imposed on our DD PAM4 design, to ensure that the LSB is 0 and the MSB is unity, yielding FS=MSB- LSB of unity. Moreover, it now suffices to optimize the OC maximin design over a single parameter, say .The maximin optimization problem for a generic 4-level OC is then:

While the foregoing written description of the invention enables one of ordinary skill to make and use what is considered presently to be the best mode thereof, those of ordinary skill will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiment, method, and examples herein. The invention should therefore not be limited by the above described embodiment, method, and examples, but by all embodiments and methods within the scope and spirit of the invention as claimed. In the foregoing specification, the invention has been described with reference to specific examples of embodiments of the invention. It will, however, be evident that various modifications and changes may be made therein without departing from the broader spirit and scope of the invention as set forth in the appended claims. Those skilled in the art will recognize that the boundaries between logic blocks are merely illustrative and that alternative embodiments may merge logic blocks or circuit elements or impose an alternate decomposition of functionality upon various logic blocks or circuit elements. Thus, it is to be understood that the architectures depicted herein are merely exemplary, and that in fact many other architectures may be implemented which achieve the same functionality. Any arrangement of components to achieve the same functionality is effectively "associated" such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality may be seen as "associated with" each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being "operably connected," or "operably coupled," to each other to achieve the desired functionality. Any reference to comprising, including, comprises, comprise and having may be applied mutatis mutandis to consisting and/or may be applied mutatis mutandis to consisting essentially of. Furthermore, those skilled in the art will recognize that boundaries between the above described operations merely illustrative. The multiple operations may be combined into a single operation, a single operation may be distributed in additional operations and operations may be executed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments. Also for example, in one embodiment, the illustrated examples may be implemented as circuitry located on a single integrated circuit or within a same device. Alternatively, the examples may be implemented as any number of separate integrated circuits or separate devices interconnected with each other in a suitable manner. However, other modifications, variations and alternatives are also possible. The specifications and drawings are, accordingly, to be regarded in an illustrative rather than in a restrictive sense. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word ‘comprising’ does not exclude the presence of other elements or steps then those listed in a claim. Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles "a" or "an" limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an." The same holds true for the use of definite articles. Unless stated otherwise, terms such as “first" and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage. While certain features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention. It is appreciated that various features of the embodiments of the disclosure which are, for clarity, described in the contexts of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features of the embodiments of the disclosure which are, for brevity, described in the context of a single embodiment may also be provided separately or in any suitable sub- combination. It will be appreciated by persons skilled in the art that the embodiments of the disclosure are not limited by what has been particularly shown and described hereinabove. Rather the scope of the embodiments of the disclosure is defined by the appended claims and equivalents thereof.

Claims

WE CLAIM 1. An optical digital to analog converter (oDAC), comprising: multiple optical paths that are parallel to each other; a combiner that comprises multiple combiner inputs and a combiner output; a splitter that is configured to receive an optical signal at a splitter input and split the optical signal between multiple splitter outputs to provide multiple path input signals to the multiple optical paths; wherein the multiple optical paths are formed between the multiple splitter outputs and the multiple combiner inputs; wherein the multiple optical paths are configured to optically process, in parallel, path input signals to provide path output signals; wherein each optical path is configured to apply an optical process that comprises applying optical modulation, by an optical gate of the optical path and under a control of an electrical modulator, to provide an optical signal having a value selected out of multiple constellation levels; wherein the multiple optical paths are configured to output multiple path output signals to the multiple combiner inputs; and wherein at least the combiner is configured to add the multiple path output signals to provide an oDAC output signal having a value selected out of values of a single quadrature constellation.

2. The oDAC according to claim 1 wherein the optical process applied by each optical path is a single quadrature optical process.

3. The oDAC according to claim 1 wherein the optical modulation is an optical pulse amplitude modulation (PAM).

4. The oDAC according to claim 1 wherein the optical gates are 1-bit modulated by the electrical modulators.

5. The oDAC according to claim 1 wherein the optical gates are multi-bit modulated by the electrical modulators.

6. The oDAC according to claim 1 wherein the optical gates are Mach-Zehnder-Modulators.

7. The oDAC according to claim 1 wherein the multiple optical paths are configured to introduce either (a) a zero phase difference or (b) one hundred eighty degree phase difference between pairs of output path output signals.

8. The oDAC according to claim 1 wherein the multiple optical paths are configured to introduce a zero phase difference between the optical path output signals.

9. The oDAC according to claim 1 wherein the optical gates are followed by phase shifters, wherein the modulation rates of the phase shifters are a fraction of a modulation rate of the optical gates.

10. The oDAC according to claim 1 wherein the optical gates are followed by slow phase modulators, wherein the modulation rates of the slow phase modulators are a fraction of a modulation rate of the optical gates.

11. The oDAC according to claim 1 wherein at least one of the optical paths comprises an optical amplifier.

12. The oDAC according to claim 1 wherein the optical gates are phase gates.

13. The oDAC according to claim 12 wherein the multiple constellation levels belong to a coherent constellation.

14. The oDAC according to claim 12 wherein the multiple constellation levels are equally spaced apart from each other.

15. The oDAC according to claim 14 wherein the multiple optical paths are multiple (S) optical paths, and wherein the multiple constellation levels, normalized to unity maximum level, equal s/(S-1), wherein s ranges from zero to S-1.

16. The oDAC according to claim 1 wherein the optical gates are intensity gates.

17. The oDAC according to claim 16 wherein the multiple constellation levels belong to a direct detection constellation.

18. The oDAC according to claim 16 wherein the multiple constellation levels are proportional to square roots of values that are evenly spaced apart from each other.

19. The oDAC according to claim 18 wherein the multiple optical paths are multiple (S) optical paths, and wherein the multiple constellation levels equal square roots of s/(S-1), whereas s ranges from zero to S-1.

20. The oDAC according to claim 1 wherein the optical gates are configurable gates that are configured to operate while driven by electrical modulators as either phase gates or as intensity gates.

21. The oDAC according to claim 1 wherein the optical gates are Mach-Zehnder-Modulators that comprise variable optical attenuators in multiple branches.

22. The oDAC according to claim 21 wherein the optical gates further comprise phase shifters in the multiple branches.

23. The oDAC according to claim 1 wherein the splitter exhibits optical power split ratios that equal corresponding optical power combing ratios of the combiner.

24. The oDAC according to claim 1 wherein the splitter exhibits optical power split ratios that equal each other.

25. The oDAC according to claim 1 wherein the splitter exhibits optical power split ratios, wherein at least one optical power split ratio differs from at least one other power split ratio.

26. The oDAC according to claim 1 wherein the splitter exhibits optical power split ratios, at least one of the optical split ratios differs from at least one of corresponding optical power combing ratios of the combiner.

27. The oDAC according to claim 1 wherein two optical paths of the multiple optical paths apply different optical modulations.

28. The oDAC according to claim 1 comprising an additional optical path formed between an additional splitter output and an additional combiner input, wherein the additional optical path is without an optical gate.

29. The oDAC according to claim 1 wherein all of the multiple constellation levels are of a same polarity.

30. The oDAC according to claim 1 wherein at least one of the multiple constellation levels is positive and at least another one of the multiple constellation levels is negative.

31. The oDAC according to claim 1 wherein at least two of the multiple optical gates are controlled by at least two electrical modulators.

32. A method for optical digital to analog conversion, the method comprises: splitting, by a combiner, an input optical signal to multiple path input signals; optically processing, the multiple path input signals, by the multiple optical paths, in parallel to provide path output signals; wherein the optically processing comprises applying optical modulation by optical gates of the multiple optical paths and while driven by multiple electrical modulators, to provide optical signals; and combining, by a combiner, multiple path output signals that are outputted from the multiple optical paths to provide an oDAC output signal having a value selected out of values of a single quadrature constellation.

33. The method according to claim 32 comprising 1-bit modulating the optical gates by the electrical modulators.

34. The method according to claim 32 comprising multi-bit modulating the optical gates by the electrical modulators.

35. The method according to claim 32 comprising introducing, by means of the multiple optical paths, either (a) a zero phase difference or (b) one hundred eighty degree phase difference between pairs of output path output signals.

36. The method according to claim 32 comprising introducing, by the multiple optical paths, a zero phase difference between the output path output signals.

37. The method according to claim 32 comprising phase modulating the optical signals having the values selected out of multiple constellation levels.

38. The method according to claim 37 comprising slow phase modulating the optical signals having the value selected out of multiple constellation levels, wherein a modulation rate of a slow phase modulator is a fraction of a modulation rate of the optical gates.

39. The method according to claim 38 wherein the optical gates are phase gates.

40. The method according to claim 39 wherein the multiple constellation levels belong to a coherent constellation.

41. The method according to claim 39 wherein the multiple constellation levels are equally spaced apart from each other.

42. The method according to claim 41 wherein the multiple optical paths are S optical paths, and wherein the multiple constellation levels, normalized to unity maximum level, equal s/(S-1), wherein s ranges from zero to S.

43. The method according to claim 32 wherein the optical gates are intensity gates.

44. The method according to claim 43 wherein the multiple constellation levels belong to a direct detection constellation.

45. The method according to claim 44 wherein the multiple constellation levels are proportional to square roots of values that are evenly spaced apart from each other .

46. The method according to claim 45 wherein the multiple optical paths are S optical paths, and wherein the multiple constellation levels equal a square root of s/(S-1), whereas s ranges from zero to S-1.

47. The method according to claim 32 comprising configuring the optical gates to operate while driven by electrical modulators as phase gates or as intensity gates.

48. The method according to claim 32 wherein the splitter is a configurable splitter.

49. The method according to claim 32 wherein the combiner is a configurable combiner.

50. The method according to claim 32 wherein the optical gates are Mach-Zehnder-Modulators that comprise variable optical attenuators in multiple branches.

51. The method according to claim 32 wherein the optical gates further comprise phase shifters in the multiple branches.

52. The method according to claim 32 wherein the splitter exhibits optical power split ratios that equal the corresponding optical power combing ratios of the combiner.

53. The method according to claim 32 wherein the splitter exhibits optical power split ratios that equal each other.

54. The method according to claim 32 wherein the splitter exhibits optical power split ratios, wherein at least one optical power split ratio differs from at least one other power split ratio.

55. The method according to claim 32 wherein the splitter exhibits optical power split ratios that differs from corresponding optical power combing ratios of the combiner.

56. The method according to claim 32 wherein two optical paths of the multiple optical paths apply different optical modulations.

57. The method according to claim 32 comprising passing an additional path input signal over an additional optical path to provide an additional path output signal.

58. The method according to claim 32 wherein all of the multiple constellation levels are of a same polarity.

59. The method according to claim 32 wherein at least one of the multiple constellation levels is positive and at least another one of the multiple constellation levels is negative.

60. The method according to claim 32 wherein at least two electrical modulators are mutually independent.

61. The method according to claim 32 comprising measuring, by a measurement circuit, different signals within an optical digital to analog converter that comprises the multiple optical paths.

62. The method according to claim 32 comprising tuning, by a tuning circuit, phase differences between different optical paths.

63. The method according to claim 32 comprising tuning, by a tuning circuit, the splitter and the combiner.

64. The method according to claim 32 comprising compensating for temperature induced drifts and for compensating for acoustically induced disturbances.

65. The method according to claim 32 comprising compensating for temperature induced drifts at a first compensation frequency and compensating for acoustically induced disturbances at a second compensation frequency that is at least one hundred time bigger than the first compensation frequency.

66. The method according to claim 32 wherein an optical processing applied by at least one of the optical paths comprises optical amplification.

67. The method according to claim 32 wherein the combiner exhibits optical power combining ratios that equal each other.

68. The method according to claim 32 wherein the combiner exhibits optical power combining ratios, wherein at least one power combining ratio differs from another power combining ratio.

69. The method according to claim 32 wherein the optical processing applied by each optical path is a single quadrature optical process.

70. An optical unit that comprises a variable optical modulator, the variable optical modulator comprises: an input splitter, a first optical path, a second optical path and a combiner; wherein the first optical path is formed between a first output of the input splitter and a first input of the combiner; wherein the second optical path is formed between a second output of the input splitter and a second input of the combiner; wherein the first optical path comprises a first variable optical attenuator, a first phase modulator and a first phase shifter; wherein the second optical path comprises a second variable optical attenuator, a second phase modulator and a second phase shifter.

71. An optically amplified recirculating (OAR) phase gate, comprising: a first Mach-Zehnder- Modulator (MZM), a second MZM and a feedback amplifier; wherein an output of the first MZM is coupled to an input of the second MZM, wherein the feedback optical amplifier is coupled between an output of the second MZM and an input of the first MZM; wherein the second MZM comprises a phase modulator.

72. An optical processor that comprises a sequence of units that comprises an input unit, one or more intermediate units and an output unit; wherein the input unit and each intermediate unit comprises a first variable optical attenuator followed by a first phase modulator and a second variable attenuator followed by a second phase modulator; wherein each intermediate unit comprises an input splitter that precedes the first variable optical attenuator and the second variable optical attenuator; wherein the output unit comprises a combiner that is followed by a pair of phase modulators.

73. A segmented first Mach-Zehnder-Modulator (MZM), comprising a splitter, a combiner, and two optical paths formed between the splitter and the combiner; wherein each optical path comprises a first phase modulator and a second phase modulator; wherein the phases ratio between the phase induced by the first phase modulator and the phase induced by a second phase modulator ranges between 1.4 and 1.8.

74. The segmented MZM according to claim 73 wherein the phases ratio ranges between 1.5 and 1.6.

75. The segmented MZM according to claim 73 wherein the phases ratio equals 1.55.

76. The segmented MZM according to claim 73 wherein the lengths ratio between the length of the first phase modulator and the second phase modulator equals the phase ratio.

77. The segmented MZM according to claim 73 wherein the first phase modulator and the second phase modulators are independently driven by on-off keying signals.