WO2022104750A1 - 显示装置及其驱动方法 - Google Patents

显示装置及其驱动方法 Download PDF

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Publication number
WO2022104750A1
WO2022104750A1 PCT/CN2020/130658 CN2020130658W WO2022104750A1 WO 2022104750 A1 WO2022104750 A1 WO 2022104750A1 CN 2020130658 W CN2020130658 W CN 2020130658W WO 2022104750 A1 WO2022104750 A1 WO 2022104750A1
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WIPO (PCT)
Prior art keywords
switch
pixel
display
sub
control signal
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PCT/CN2020/130658
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English (en)
French (fr)
Inventor
宗少雷
孙继刚
蒋伟信
王斌
孙伟
段欣
于淑环
郝可歆
范嘉琪
谷朝芸
张少如
王铁石
彭宽军
董学
秦纬
刘伟星
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080002922.XA priority Critical patent/CN114945972B/zh
Priority to PCT/CN2020/130658 priority patent/WO2022104750A1/zh
Priority to US18/037,043 priority patent/US20230410761A1/en
Publication of WO2022104750A1 publication Critical patent/WO2022104750A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N13/00—Stereoscopic video systems; Multi-view video systems; Details thereof
    • H04N13/30—Image reproducers
    • H04N13/302—Image reproducers for viewing without the aid of special glasses, i.e. using autostereoscopic displays
    • H04N13/305—Image reproducers for viewing without the aid of special glasses, i.e. using autostereoscopic displays using lenticular lenses, e.g. arrangements of cylindrical lenses
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N13/00—Stereoscopic video systems; Multi-view video systems; Details thereof
    • H04N13/30—Image reproducers
    • H04N13/361—Reproducing mixed stereoscopic images; Reproducing mixed monoscopic and stereoscopic images, e.g. a stereoscopic image overlay window on a monoscopic image background
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N13/00—Stereoscopic video systems; Multi-view video systems; Details thereof
    • H04N13/30—Image reproducers
    • H04N13/366—Image reproducers using viewer tracking
    • H04N13/383—Image reproducers using viewer tracking for tracking with gaze detection, i.e. detecting the lines of sight of the viewer's eyes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N13/00—Stereoscopic video systems; Multi-view video systems; Details thereof
    • H04N13/30—Image reproducers
    • H04N13/398—Synchronisation thereof; Control thereof
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2354/00—Aspects of interface with display user

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display device and a driving method thereof.
  • Glasses-free 3D technology refers to a 3D display technology with spatial and depth perception that can be obtained without any auxiliary equipment. As users have higher and higher requirements for viewing experience, high-definition display resolution and naked-eye 3D display technology are gradually being applied to display screens.
  • the resolution of the high-definition display can reach 4K or higher.
  • the naked-eye 3D technology combined with the high-definition display can achieve a high-definition stereoscopic display effect.
  • the data bandwidth required for full-screen high-definition 3D display is very large, and the human eye can only focus on a small area of the screen, so there is unnecessary waste of data resources in the non-gazing area.
  • Embodiments of the present disclosure provide a display device, including:
  • a plurality of pixel islands are located on the base substrate; the pixel islands include a plurality of sub-pixels of different colors, all the sub-pixels are arranged in an array along the first direction and the second direction, and one pixel island has the same color
  • the sub-pixels are arranged in a row along the first direction, the sub-pixel rows of different colors are arranged along the second direction, and the first direction and the second direction intersect;
  • a multiplexing circuit located on one side of the area where all the pixel islands are located along the second direction; the data lines are respectively connected to the multiplexing circuit;
  • a driving chip located on the side of the multiplexing circuit away from the pixel island along the second direction, and the multiplexing circuit is connected to the driving chip;
  • a controller connected to the driving chip, configured to provide a driving signal to the driving chip
  • the microlens layer is located on the side of the pixel island away from the base substrate, and the microlens layer modulates the outgoing light of the pixel island, so that the sub-pixels in the pixel island are mapped into a pixel array and Realize three-dimensional display;
  • the sub-pixel columns in one of the pixel islands are divided into a plurality of sub-pixel groups along the first direction, and the number of sub-pixel columns included in each of the sub-pixel groups is equal;
  • the multiplexing circuit includes a plurality of first multiplexing units arranged along the first direction, the first multiplexing unit includes an input terminal and a plurality of output terminals; one of the first multiplexing units The multiplexing unit is correspondingly connected to one of the sub-pixel groups, the output terminals of the first multiplexing unit are respectively connected to the data lines corresponding to the sub-pixel groups, and the input terminals of the first multiplexing unit are respectively connected. Connect the driver chip.
  • the multiplexing circuit further includes:
  • first switch control signal lines extending along the first direction and being arranged along the second direction;
  • the first multiplexing unit includes: a plurality of first switch transistors, the control electrodes of the first switch transistors are connected to the first switch control signal line, and the first electrodes of the first switch transistors are connected to the first switch transistors.
  • the output end of the first multiplexing unit, the second pole of the first switching transistor is connected to the input end of the first multiplexing unit;
  • control electrodes of each of the first switch transistors are respectively connected to different first switch control signal lines, and the first electrodes of each of the first switch transistors are respectively connected to the Different outputs of the first multiplexing unit.
  • the multiplexing circuit further includes:
  • control unit located on the side of the first multiplexing unit away from the pixel island along the second direction, the control units are arranged along the first direction;
  • the control unit includes an input terminal and an output terminal; one of the control units is correspondingly connected to one of the first multiplexing units, the output terminal of the control unit is connected to the input terminal of the first multiplexing unit, and the input terminal of the control unit is connected to the input terminal of the first multiplexing unit.
  • the terminal is connected to the driver chip.
  • the multiplexing circuit further includes:
  • the control unit includes: a control switch transistor; the control pole of the control switch transistor is connected to the control signal line, the first pole of the control switch transistor is connected to the output end of the control unit, and the first pole of the control switch transistor is connected to the output end of the control unit.
  • a diode is connected to the input of the control unit.
  • the multiplexing circuit further includes:
  • the second multiplexing unit includes a plurality of input ends and a plurality of output ends, the number of the input ends is smaller than the number of the output ends; one of the second multiplexing units is correspondingly connected along the first A plurality of the pixel islands arranged in one direction, the output ends of the second multiplexing unit are respectively connected to the data lines corresponding to each sub-pixel column in each of the pixel islands, and the second multiplexing unit
  • the input terminals are respectively connected to the driver chips.
  • the multiplexing circuit further includes:
  • the second switch control signal lines extending along the first direction and being arranged along the second direction;
  • third switch control signal lines extending along the first direction and being arranged along the second direction;
  • the second multiplexing unit includes: a plurality of second switch transistors and a plurality of third switch transistors;
  • the control electrode of the second switch transistor is connected to the second switch control signal line, the first electrode of the second switch transistor is connected to the output end of the second multiplexing unit, and the second switch transistor is connected to the output end of the second multiplexing unit.
  • the second pole is connected to the first pole of the third switch transistor; the control pole of the third switch transistor is connected to the third switch control signal line, and the second pole of the third switch transistor is connected to the second multiple The input terminal of the multiplexing unit;
  • control electrodes of the second switch transistors connected to the same pixel island are connected to the same second switch control signal line, and are connected to all the different pixel islands.
  • the control electrodes of the second switch transistors are connected to different second switch control signal lines; the second electrodes of the second switch transistors connected to the sub-pixel columns at the same position in each of the pixel islands are connected to each other;
  • each of the third switching transistors corresponds to one of the pixel islands connected to the second multiplexing unit; the pixel island corresponds to the third switching transistor and the second multiplexing unit.
  • the first poles of the third switch transistors are respectively connected to the second poles of the second switch transistors;
  • the third switch transistors are divided into a plurality of third switch transistor groups along the first direction, and the number of the third switch transistor groups is the same as that in one of the pixel islands.
  • the number of included sub-pixel groups is equal;
  • control electrodes of the third switch transistors are respectively connected to different third switch control signal lines, and the second electrodes of the third switch transistors are connected to the second multiple transistors. the same input of the multiplexing unit.
  • it also includes:
  • a plurality of gate lines extending along the first direction and arranged along the second direction; the sub-pixels arranged in the same row along the first direction are connected to the same gate line;
  • a gate driving circuit located on one side or both sides of the region where the pixel island is located along the first direction; the gate lines are respectively connected to the gate driving circuit;
  • the gate drive circuit includes a plurality of gate drive units arranged along the second direction, each of the gate drive units is cascaded with each other along the second direction, and each of the gate drive units scans the corresponding Subpixel row.
  • it also includes:
  • a camera configured to photograph the eyes of the user, so that the controller determines the gaze area of the user on the display device according to the image photographed by the camera, and controls the driver chip to drive the gaze area and the non-gazing area Image display at different resolutions.
  • the microlens layer includes at least one liquid crystal lens layer.
  • the pixel island includes sixteen red sub-pixels, sixteen green sub-pixels and sixteen blue sub-pixels, the red sub-pixels, the green sub-pixels and the blue sub-pixels
  • the sub-pixels are arranged in three rows along the first direction, and arranged in sixteen columns along the second direction; one of the pixel islands is mapped by the microlens layer to form sixteen pixels arranged in four rows and four columns ;
  • the sub-pixels in one of the pixel islands are divided into four sub-pixel groups along the first direction, and each of the sub-pixel groups includes four sub-pixel columns;
  • the multiplexing circuit includes four first switch control signal lines, and one first multiplexing unit includes four first switch transistors; the control electrodes of the four first switch transistors are respectively connected to the four first switch transistors.
  • the first switch control signal line, the first poles of the four first switch transistors are respectively connected to the data lines corresponding to the four sub-pixel columns in one of the sub-pixel groups; the second poles of the four first switch transistors connected to each other and to the driver chip.
  • a first multiplexing unit is connected to the driving chip through one of the control units;
  • the multiplexing circuit includes a control signal line, and each of the control units includes a control switch transistor; the control electrodes of each of the control switch transistors are connected to the control signal line, and the control unit in one of the control units The first poles of the control switch transistors are connected to the second poles of the four first switch transistors in one of the first multiplexing units, and the second poles of the control switch transistors are connected to the driving chip.
  • the multiplexing circuit includes two second switch control signal lines and four third switch control signal lines;
  • One of the second multiplexing units is correspondingly connected to the two pixel islands arranged along the first direction, and the two pixel islands are the first pixel island and the second pixel island;
  • One of the second multiplexing units includes thirty-two second switch transistors; sixteen of the second switch transistors in one of the second multiplexing units are correspondingly connected to the first pixel island. data lines, and another sixteen of the second switch transistors are correspondingly connected to the data lines of the second pixel island;
  • the control electrodes of the sixteen second switch transistors corresponding to the first pixel island are all connected to one of the second switch control signal lines, and the sixteen second switch transistors corresponding to the second pixel island are connected to one of the second switch control signal lines.
  • the control poles of the switch transistors are all connected to the other second switch control signal line; the first poles of the second switch transistors corresponding to the first pixel island are respectively connected to the data lines of the first pixel island , the first poles of the second switching transistors corresponding to the second pixel island are respectively connected to the data lines of the second pixel island; the first pixel island and the second pixel island are located in the same
  • the second poles of the two second switching transistors corresponding to the sub-pixel columns of the positions are connected to each other;
  • One of the second multiplexing units includes sixteen third switch transistors; sixteen of the third switch transistors correspond to the first pixel islands; sixteen of the third switch transistors along the first pixel island; One direction is divided into four third switch transistor groups;
  • Control electrodes of the four third switch transistors in one of the third switch transistor groups are respectively connected to the four third switch control signal lines, corresponding to the second electrodes of the second switch transistors in the same sub-pixel column
  • the first poles of the third switch transistors are connected, and the second poles of the four third switch transistors are connected to each other and connected to the driving chip.
  • Embodiments of the present disclosure also provide a driving method based on any of the above-mentioned display devices, including:
  • the gaze area is driven to display an image at a first resolution
  • the non-gazing area is driven to display an image at a second resolution; the first resolution is higher than the second resolution.
  • the display device includes a camera
  • the real-time determination of the gaze area and the non-gazing area of the user on the display device includes:
  • An area other than the gaze area in the display device is determined as a non-gazing area.
  • the determining of the gaze area of the user on the display device according to the image captured by the camera includes:
  • the user's left eye and right eye relative to the display surface of the display device, and the distance between the user and the display device, it is respectively determined that the user's left eye is in the left eye gaze area and the left eye of the display device. the user's right eye is in the right eye gaze area of the display device;
  • the overlapping area of the left eye gaze area and the right eye gaze area is taken as the gaze area of the user on the display device.
  • the following formula is used to determine the gaze area of a single eye of the user on the display device:
  • S represents the gaze area of the user's single eye on the display device
  • A represents the distance between the user and the display device
  • the method before the driving the gaze area to perform image display at a first resolution and driving the non-gazing area to perform image display at a second resolution, the method further includes:
  • the driving of the gaze area to perform image display at a first resolution, and driving the non-gazing area to perform image display at a second resolution includes:
  • the display mode selected by the user is a two-dimensional display mode, driving the gaze area to display a two-dimensional image at a first resolution, and driving the non-gazing area to display a two-dimensional image at a second resolution;
  • the gaze area is driven to display a three-dimensional image at a first resolution, and the non-gazing area is driven to display a two-dimensional image at a second resolution;
  • the display mode is the three-dimensional display mode, the gaze area is driven to display a three-dimensional image at a first resolution, and the non-gazing area is driven to display a three-dimensional image at a second resolution.
  • the gaze area is driven to perform two-dimensional image display at a first resolution
  • the non-gazing area is driven to perform two-dimensional image display at a second resolution.
  • dimensional image display including:
  • each of the first switch control signal lines corresponding to the gaze area Controlling each of the first switch control signal lines corresponding to the gaze area to output active level signals in turn, so that each first switch transistor in the first multiplexing unit is turned on in turn to transmit different two-dimensional image data , control each of the first switch control signal lines corresponding to the non-gazing area to output an active level signal at the same time, so that each first switch transistor in the first multiplexing unit is turned on at the same time to transmit the same two-dimensional image data, so as to drive the gaze area to perform two-dimensional image display at the first resolution, and drive the non-gazing area to perform two-dimensional image display at the second resolution.
  • the gazing area is driven to perform 3D image display at a first resolution
  • the non-gazing area is driven to perform 3D image display at a second resolution
  • each of the first switch control signal lines corresponding to the gaze area Controlling each of the first switch control signal lines corresponding to the gaze area to output active level signals in turn, so that each first switch transistor in the first multiplexing unit is turned on in turn to transmit different three-dimensional image data, Controlling each of the first switch control signal lines corresponding to the non-gazing area to output an active level signal at the same time, so that each first switch transistor in the first multiplexing unit is turned on at the same time to transmit the same three-dimensional image data , so as to drive the gaze area to perform 3D image display at a first resolution, and drive the non-gazing area to perform 3D image display at a second resolution.
  • the gazing area is driven to display 3D images at a first resolution
  • the non-gazing area is driven to display 2D images at a second resolution display, including:
  • each of the first switch control signal lines corresponding to the gaze area Controlling each of the first switch control signal lines corresponding to the gaze area to output active level signals in turn, so that each first switch transistor in the first multiplexing unit is turned on in turn to transmit different three-dimensional image data, Controlling each of the first switch control signal lines corresponding to the non-gazing area to output an active level signal at the same time, so that each first switch transistor in the first multiplexing unit is turned on at the same time to transmit the same two-dimensional image data, so as to drive the gaze area to perform three-dimensional image display at a first resolution, and drive the non-gazing area to perform two-dimensional image display at a second resolution.
  • the scanning duration of the gate driving unit corresponding to the gaze region is greater than the scanning duration of the gate driving unit corresponding to the non-gazing region.
  • the driving method further includes:
  • the driving current of the driving chip to the non-gazing region is increased, so that the difference between the charging levels of the sub-pixels in the watching region and the non-gazing region is smaller than a set threshold.
  • the gate driving circuit of the display device includes a plurality of gate driving units, and the multiplexing circuit of the display device further includes a plurality of second multiplexing units and a plurality of control units ;
  • the driving method includes:
  • control switch transistors that drive each of the control units are kept off;
  • the output signals of the gate driving unit connected to the nth row of sub-pixels and the gate drive unit connected to the n+3th row of sub-pixels are controlled to be the same; n is greater than or an integer equal to 1; control each second switch control signal line to output an active level signal at the same time, so that each second switch transistor in the second multiplexing unit is turned on at the same time, so as to realize a plurality of adjacent pixel islands
  • the loaded image data is the same;
  • each second switch control signal line is controlled to output active level signals in sequence, so that the second switch transistors in the second multiplexing unit connected to different pixel islands are sequentially Open to realize that the image data loaded by each pixel island is different;
  • the driving method for the same pixel island includes:
  • each third switch control signal line Controlling each third switch control signal line to output an effective level signal at the same time, so that each third switch transistor in the second multiplexing unit is turned on at the same time to transmit the same image data;
  • each third switch control signal line is controlled to output active level signals in sequence, so that each third switch transistor in the second multiplexing unit is turned on in sequence to transmit different image data.
  • FIG. 1 is one of the schematic structural diagrams of a display device provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic cross-sectional structure diagram of a display device according to an embodiment of the present disclosure
  • 3a is a schematic diagram of a sub-pixel arrangement structure of a pixel island provided by an embodiment of the present disclosure
  • FIG. 3b is a schematic diagram of a pixel arrangement structure after pixel island mapping according to an embodiment of the present disclosure
  • FIG. 4 is one of the partial enlarged views of the display device provided by the embodiment of the present disclosure.
  • FIG. 5 is a second partial enlarged view of a display device provided by an embodiment of the present disclosure.
  • FIG. 6 is a partial enlarged view of a second multiplexing unit provided by an embodiment of the present disclosure.
  • FIG. 7 is a third partial enlarged view of a display device provided by an embodiment of the present disclosure.
  • FIG. 8 is a flowchart of a method for driving a display device according to an embodiment of the present disclosure
  • FIG. 9a is one of the schematic diagrams of generating a gaze area for a human eye according to an embodiment of the present disclosure.
  • FIG. 9b is the second schematic diagram of a human eye generating a gaze area according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a display partition of a display device according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of a display effect of the display device shown in FIG. 10;
  • FIG. 12a is one of the driving timing diagrams corresponding to the gaze area provided by the embodiment of the present disclosure.
  • FIG. 12b is one of the driving timing diagrams corresponding to the non-gazing area provided by the embodiment of the present disclosure.
  • FIG. 13a is the second driving timing diagram corresponding to the gaze area provided by the embodiment of the present disclosure.
  • FIG. 13b is the second driving timing diagram corresponding to the non-gazing area provided by the embodiment of the present disclosure.
  • FIG. 14 is a comparison diagram of charging voltages in a gaze area and a non-gaze area provided by an embodiment of the present disclosure
  • FIG. 15a is the third driving timing diagram corresponding to the gaze area provided by the embodiment of the present disclosure.
  • FIG. 15b is the third driving timing diagram corresponding to the non-gazing area provided by the embodiment of the present disclosure.
  • FIG. 16 is a schematic diagram of a system architecture of a display device according to an embodiment of the present disclosure.
  • the 3D display device designed according to this principle usually needs to cooperate with glasses and other equipment to separate the light incident to the left eye and the right eye, so as to achieve the effect of three-dimensional display.
  • the 3D stereoscopic display implemented in the above manner usually focuses the human eyes on the same position for a long time, which will cause visual fatigue, and then cause the user to experience bad experiences such as dizziness.
  • 3D display based on light field technology can overcome the above problems and realize naked eye 3D display.
  • Light field display is to set a microlens array on the light-emitting side of the display panel.
  • the outgoing light of the display panel is modulated by the microlens array to form multiple viewpoints and enter the human eye.
  • the images viewed by the human eye come from different viewpoints, so the The images come from different directions, which is similar to the situation when the human eye watches the real scene, which overcomes the problem of visual fatigue.
  • FIG. 1 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic cross-sectional structural schematic diagram of the display device provided by an embodiment of the present disclosure.
  • the display device provided by the embodiment of the present disclosure includes:
  • the base substrate 10 is generally located at the bottom of the display device, and has the function of supporting and carrying other components.
  • the size of the base substrate 10 is generally substantially the same as that of the display device, and the shape is usually set to be rectangular. When the display device is a special-shaped display device, the shape and size of the base substrate are adapted to the display device.
  • the material of the base substrate is usually glass, which is not limited here.
  • a plurality of pixel islands 20 are located on the base substrate 10; the pixel islands 20 include a plurality of sub-pixels p of different colors, all the sub-pixels p are arranged in an array along the first direction x and the second direction y, and one pixel island 20 is arranged in an array.
  • the sub-pixels p of the same color are arranged in a row along the first direction x, and the rows of sub-pixels p of different colors are arranged along the second direction y, and the first direction x and the second direction y intersect.
  • each pixel island 20 may be consistent, and each pixel island 20 is arranged in an array along the first direction x and the second direction y.
  • FIG. 3 a is a schematic diagram of a sub-pixel arrangement structure of a pixel island provided by an embodiment of the present disclosure.
  • a pixel island 20 may include sub-pixels of three primary colors.
  • the pixel island 20 includes a red sub-pixel pr, a green sub-pixel pg, and a blue sub-pixel pb.
  • the number of red sub-pixels pr, green sub-pixels pg and blue sub-pixels pb is the same; the red sub-pixels pr are arranged in a row along the first direction x, the green sub-pixels pg are arranged in a row along the first direction x, and the blue sub-pixels
  • the pixels pb are arranged in a row along the first direction x; the red sub-pixel row, the green sub-pixel row and the blue sub-pixel row are arranged along the second direction y, so that the sub-pixels in the pixel island 20 are arranged in an array.
  • the above-mentioned first direction x and second direction y may be two directions perpendicular to each other, wherein the first direction x may be a horizontal direction
  • the display device provided by the embodiment of the present disclosure further includes: a microlens layer 30 .
  • the microlens layer 60 is located on the side of the pixel island 20 away from the base substrate 10 .
  • the microlens layer 30 is composed of a microlens array, and the microlens layer 30 can modulate the light emitted from the pixel island 30, so that the pixel island 20 is mapped to a pixel array for image display.
  • the imaging resolution can be improved on the basis of reaching the limit of the physical arrangement of the sub-pixels.
  • FIG. 3b is a schematic diagram of a pixel arrangement structure after pixel island mapping according to an embodiment of the present disclosure.
  • the pixel arrangement structure shown in FIG. 3b can be formed. It can be seen from FIG. 3b that the mapped red sub-pixels pr, The green sub-pixel pg and the blue sub-pixel pb are arranged in a fixed order, and adjacent one red sub-pixel pr, one green sub-pixel pg and one blue sub-pixel pb constitute one pixel.
  • the mapped pixels are the same as the traditional pixel arrangement structure, and one pixel island can be mapped into a pixel array composed of multiple pixels, so that the pixel island structure can improve the display resolution of the image.
  • the microlens layer 30 is not only used to perform pixel mapping on the sub-pixels in the pixel island, but also can modulate the outgoing light of the pixel island, so that the final display data of the pixel island forms multiple viewpoints, thereby realizing three-dimensional light field display.
  • the microlens layer 30 may adopt at least one liquid crystal lens.
  • the liquid crystal molecules can be controlled to generate a set phase retardation, which is equivalent to the function of a lens.
  • the above-mentioned microlens layer can also directly use a microlens array composed of microlenses having a predetermined shape to achieve the same function, which is not limited herein.
  • the structure and function of the microlens layer will be described below by using a liquid crystal lens as the microlens layer.
  • the arrangement and principle of the solid microlens are similar to those of the liquid crystal lens, and will not be described in detail.
  • the microlens layer 30 may only include one liquid crystal lens, which is equivalent to a microlens array composed of hemispherical microlenses, and the liquid crystal lens simultaneously performs pixel mapping and realizes three-dimensional light field display. After passing through the liquid crystal lens, the light emitted from the sub-pixels in the pixel island can be mapped into a pixel array and form multiple viewpoints, thereby realizing a three-dimensional light field display.
  • the microlens layer 30 can be (or equivalently) arranged in an array of 16 hemispherical microlenses on the light-emitting side of the pixel island 20, so that the pixel island can be 20 is mapped to the pixel array shown in Fig. 3b, forming a maximum of 16 viewpoints to realize the three-dimensional display of the light field.
  • the microlens layer 30 can also use two layers of liquid crystal lenses, wherein the liquid crystal lens on the side close to the pixel island can play the role of pixel mapping, and the other liquid crystal lens on the side far from the pixel island can reflect the outgoing light. Modulation is performed to realize three-dimensional light field display. Both the two layers of lenses can adopt a hemispherical micro-lens structure, and the number of micro-lenses matches the number of sub-pixels in the pixel island, which is not limited herein.
  • one layer of liquid crystal lenses is used for a microlens array formed by equivalent hemispherical microlenses, and the other layer of liquid crystal lenses is used for equivalent It is a microlens array composed of cylindrical lenses.
  • the two liquid crystal lenses are not controlled at the same time, and the modulation principles of light are different. 3D display of viewpoints.
  • one layer of liquid crystal lenses can be equivalent to 16 cylindrical lenses, corresponding to different sub-pixel columns, so that the outgoing light of the pixel island can be mapped as shown in FIG. 3b
  • a part of the light is deflected toward the left eye at the same time, and another part of the light is deflected toward the right eye, thereby realizing three-dimensional display.
  • Another layer of liquid crystal lenses can be equivalent to 16 hemispherical microlenses arranged in an array on the light-emitting side of the pixel island 20, so that the pixel island 20 can be mapped to the pixel array shown in FIG. 3D display of the light field.
  • the embodiments of the present disclosure do not limit the number of sub-pixels in the pixel island, the number of corresponding liquid crystal lenses used, and the operation means of how to control the liquid crystal lenses to realize three-dimensional display.
  • the display device further includes:
  • the plurality of data lines 40 are arranged along the first direction x and extend along the second direction y; the sub-pixels arranged in the same column along the second direction y are connected to the same data line 40 .
  • the data line 40 is used to transmit image data to the sub-pixels, and the sub-pixels are displaying the corresponding brightness of the image data.
  • the multiplexing circuit 50 is located on one side of the region where all the pixel islands 20 are located along the second direction y. Each data line 40 is connected to the multiplexing circuit 50, respectively.
  • a small number of driving pins can be used to drive different data lines in a time-sharing manner, thereby reducing the number of driving pins used and saving resources.
  • the driving chip 60 is located on the side of the multiplexing circuit 50 away from the pixel island 20 along the second direction y.
  • the multiplexing circuit 50 is connected to the driving chip 60 .
  • the driving chip 60 has a plurality of connection pins, the input terminal of the multiplexing circuit 50 is connected to the pins of the driving chip 60, and the output terminal of the multiplexing circuit 50 is connected to each data line 40 in turn, wherein the number of input terminals is small. the number of outputs.
  • the image data output by the pins of the driving chip 60 can be transmitted to each data line 40 through the multiplexing circuit 50 , so that one pin of the driving chip 60 can control multiple data lines 40 .
  • the controller 70 connected to the driving chip 60 , is configured to provide the driving signal to the driving chip 60 .
  • the controller 70 may receive two-dimensional image data or three-dimensional image data for image display, and the controller 70 determines whether the current display mode is the three-dimensional display mode or the two-dimensional display mode according to the user's selection. Then, the corresponding image data is provided to the driver chip 60 according to the predetermined display partition, and the driver chip 60 provides image data to each data line with a set driving current according to the control of the controller 70.
  • the central area of the display device can be used as a high-definition display area, and other areas except the central area can be used as auxiliary display areas; thus, the central area can display images with high resolution, and the auxiliary display area can display images with low resolution. display, which can save power consumption without reducing the display effect.
  • the display device provided by the embodiment of the present disclosure may further include a camera c, and the camera c is configured to photograph the user's eyes, so that the controller 70 determines the user's gaze area on the display device according to the image captured by the camera c, and controls the driver chip 60
  • the gaze area is driven to display an image at a high resolution
  • the non-gazing area is driven to display an image at a low resolution.
  • FIG. 4 is one of partial enlarged views of a display device provided by an embodiment of the present disclosure.
  • the sub-pixel columns in one pixel island 20 are divided into a plurality of sub-pixel groups 21 along the first direction x, and the number of sub-pixel columns included in each sub-pixel group 21 is equal.
  • the multiplexing circuit 50 includes a plurality of first multiplexing units 51 arranged along the first direction x, and the first multiplexing unit 51 includes an input terminal 51i and a plurality of output terminals 51o; a first multiplexing unit 51
  • the multiplexing unit 51 is connected to one sub-pixel group 21 correspondingly, the output terminal 51o of the first multiplexing unit 51 is respectively connected to the data line 40 corresponding to the sub-pixel group, and the input terminal 51i of the first multiplexing unit 51 is connected to the driving chip 60.
  • the image data written by one sub-pixel group 21 is transmitted through one first multiplexing unit 51 .
  • the output terminals 51o of the first multiplexing unit 51 are turned on in sequence, the image data input from the input terminal 51i can be sequentially transmitted to the different data lines 40 corresponding to the sub-pixel groups 21, so that the different data lines 40 can be directed to Subpixels transmit different image data.
  • the maximum number of viewpoints can be formed, so that high-resolution image display can be performed.
  • the image data input from the input terminal 51i is simultaneously transmitted to the different data lines 40 corresponding to the sub-pixel groups 21, so that the different data lines 40 can connect to the sub-pixel groups 21.
  • Pixels transmit the same image data.
  • the same image data is written to the sub-pixels in the same sub-pixel group 21, it is equivalent to that multiple pixels are used to display the same image data, which can reduce the number of viewpoints and thus perform low-resolution image display.
  • the gazing area of the display device it is possible to control the gazing area of the display device to perform high-resolution image display, and control the non-gazing area to perform low-resolution image display, thereby reducing the amount of data transmission in the non-gazing area and reducing the amount of data transmission in the non-gazing area.
  • Pixel charging time the saved time is used to improve the refresh rate of the image, so that the gaze area has a better display effect, and at the same time, the power consumption of the display device is reduced.
  • the multiplexing circuit 50 further includes: a plurality of first switch control signal lines l1, and the first switch control signal lines l1 extend along the first direction x and are arranged along the second direction y.
  • the first multiplexing unit 51 includes: a plurality of first switching transistors T1, the control electrodes of the first switching transistors are connected to the first switching control signal line l1, and the first electrodes of the first switching transistors are connected to the first multiplexing unit
  • the output terminal 51o of the first switching transistor is connected to the input terminal 51i of the first multiplexing unit.
  • the number of the first switching transistors T1 included in one first multiplexing unit 51 is equal to the number of the first switching control signal lines 11 .
  • the control electrodes of each first switch transistor T1 are respectively connected to different first switch control signal lines l1, and the first electrodes of each first switch transistor T1 are respectively connected to the first multiplexer.
  • the different output terminals 51o of the unit and the second pole of each first switching transistor T1 are connected to the input terminal 51i of the first multiplexing unit.
  • Each first switch transistor T1 in the first multiplexing unit 51 is turned on or off under the control of each first switch control signal line 11 .
  • each of the first switch control signal lines 11 outputs an effective level signal in turn, so that each of the first switch transistors T1 is turned on in turn, the signal of the input terminal 51i is transmitted to the first pole through the second pole of each first switch transistor T1 in turn.
  • different image data can be sequentially transmitted to different data lines connected to the first switching transistors T1 , so that multiple columns of sub-pixels can write different image data to perform high-resolution image display.
  • each first switch transistor T1 When each first switch signal line 11 outputs an effective level signal at the same time, each first switch transistor T1 can be controlled to be turned on at the same time, then the signal of the input terminal 51i is transmitted to the first pole through the second pole of each first switch transistor T1, Therefore, each of the first switching transistors T1 can be output to a plurality of data lines 40 at the same time, so that the sub-pixels in multiple columns can simultaneously write the same image data to perform low-resolution image display.
  • FIG. 5 is a second partial enlarged view of a display device provided by an embodiment of the present disclosure.
  • the multiplexing circuit 50 further includes: a plurality of control units c.
  • the control unit c is located on the side of the first multiplexing unit 51 away from the pixel island 20 along the second direction y, and the control unit c is arranged along the first direction x.
  • the control unit c includes an input end ci and an output end co; a control unit c is correspondingly connected to a first multiplexing unit c, and the output end co of the control unit is connected to the input end 51i of the first multiplexing unit 51, The input end ci of the control unit c is connected to the driving chip 60 .
  • the first multiplexing unit 51 is connected to the driving chip 60 through the control unit c, and the control unit c is used to control whether to start the first multiplexing unit 51 to transmit image data to the data line 40 .
  • the control unit c is equivalent to the switch of the first multiplexing unit 51, and the first multiplexing unit 51 can realize the above driving only when the control unit c is in the on state; when the control unit c is in the off state, Then the first multiplexing unit 51 cannot be controlled.
  • the multiplexing circuit 50 further includes: a control signal line lc extending along the first direction x.
  • the control unit c includes: the control switch transistor Tc; the control pole of the control switch transistor Tc is connected to the control signal line lc, the first pole of the control switch transistor Tc is connected to the output end co of the control unit, and the second pole of the control switch transistor Tc is connected to the control unit the input ci.
  • the control switching transistor Tc is turned on or off under the control of the control signal line lc.
  • the control signal line lc outputs an effective level signal
  • the control switch transistor Tc is turned on, and the signal at the input end ci is transmitted to the first electrode through the second pole of the control switch transistor Tc, so that the image data output by the driver chip can pass through the control switch transistor.
  • Tc is transmitted to the first multiplexing unit 51 , and then transmitted to each data line 40 connected thereto through the first multiplexing unit 51 .
  • the control switch transistor Tc is turned off, and the image data output by the driving chip can no longer be transmitted to the first multiplexing unit 51 through the control switch transistor Tc.
  • the multiplexing unit 51 is invalid.
  • the above-mentioned display device provided by the embodiment of the present disclosure can perform three-dimensional light field display, and the number of viewpoints can be controlled by controlling the first switching transistor T1 in the first multiplexing unit 51, thereby controlling the display resolution of the display device.
  • the multiplexing circuit 50 may further include: a plurality of second multiplexing units 52 .
  • the second multiplexing units 52 are along the second direction y is located on the side of the first multiplexing unit 51 away from the pixel island 20, and the second multiplexing unit 52 is arranged along the first direction x.
  • the second multiplexing unit 52 includes a plurality of input ends 52i and a plurality of output ends 52o, and the number of the input ends 52i is smaller than the number of the output ends 52o; one second multiplexing unit 52 is arranged along the first direction x corresponding to the connection
  • the output terminals 52o of the second multiplexing unit 52 are respectively connected to the data lines 40 corresponding to each sub-pixel column in each pixel island, and the input terminals 52i of the second multiplexing unit 52 are respectively connected to the plurality of pixel islands 20.
  • driver chip 60 is a driver chip 60 .
  • the second multiplexing unit 52 connects a plurality of pixel islands 20 at the same time. Through such a connection relationship, different image data can be transmitted to each pixel island 20 in sequence, or the same image data can be transmitted to a plurality of pixel islands 20 at the same time.
  • the resolution of the data transmitted by the pixel island 20 can be controlled while controlling the number of viewpoints generated by the pixel island, thereby controlling the image resolution of the display device.
  • the multiplexing circuit 50 further includes:
  • the second switch control signal lines l2 extend along the first direction x and are arranged along the second direction y;
  • a plurality of third switch control signal lines 13 extend along the first direction x and are arranged along the second direction y.
  • the extension directions of the first switch control signal line l1, the second switch control signal line l2, the second switch control signal line l3 and the control signal line lc are the same, and they can all extend along the first direction x along the first direction x.
  • the two directions are arranged in the y direction.
  • the second multiplexing unit 52 includes: a plurality of second switching transistors T2 and a plurality of third switching transistors T3.
  • the control electrode of the second switch transistor T2 is connected to the second switch control signal line 12
  • the first electrode of the second switch transistor T2 is connected to the output end 52o of the second multiplexing unit 52
  • the second switch transistor T2 is connected to the output end 52o of the second multiplexing unit 52.
  • the pole is connected to the first pole of the third switch transistor T3; the control pole of the third switch transistor T3 is connected to the third switch control signal line 13, and the second pole of the third switch transistor T3 is connected to the input end of the second multiplexing unit 52 52i.
  • the number of second switching transistors T2 included in one second multiplexing unit 52 is equal to the number of data lines 40 connected to one second multiplexing unit 52 .
  • one second multiplexing unit 52 connects two pixel islands 20, each pixel island 20 includes 16 columns of sub-pixels, then one pixel island 20 is connected to 16 data lines, and two pixel islands 20 are connected to 32 data lines, Then, the second multiplexing unit 52 includes 32 second switching transistors T2.
  • the number of third switching transistors T3 included in one second multiplexing unit 52 is equal to the number of sub-pixel columns included in one pixel island 20 . For example, if one pixel island 20 includes 16 columns of sub-pixels, then the second multiplexing unit 52 includes 16 third switching transistors T3.
  • control electrodes of the second switch transistors T2 connected to the same pixel island 20 are connected to the same second switch control signal line 12, and are connected to the second switch transistors T2 of different pixel islands 20.
  • the control electrodes are connected to different second switch control signal lines 12 ; the second electrodes of the second switch transistors T2 connected to the sub-pixel columns at the same position in each pixel island 20 are connected to each other.
  • FIG. 6 is a partial enlarged view of a second multiplexing unit according to an embodiment of the present disclosure.
  • each pixel island includes 16 columns of sub-pixels, and the multiplexing circuit includes two second switch control signal lines (121 and l22); the control electrodes of the 16 second switching transistors T21 connected to the first pixel island 201 are connected to the first second switching control signal line l21, which are connected to the 16 second switching transistors T22 of the second pixel island 202. The control electrode is connected to the second second switch control signal line 122 .
  • the second pole of the second switch transistor T21 connected to the first column of sub-pixels of the first pixel island 201 is connected to the second pole of the second switch transistor T22 of the first column of sub-pixels of the second pixel island 202; connected
  • the second pole of the second switch transistor T21 of the second column of sub-pixels of the first pixel island 201 is connected to the second pole of the second switch transistor T22 of the second column of sub-pixels of the second pixel island 202;
  • the second poles of the second switch transistors connected to the first pixel island are respectively connected to the second poles of the second switch transistors connected to the same position of the second pixel island.
  • image data can be transmitted to the first pixel island 201 and the second pixel island 202 respectively.
  • first second switch control signal line 121 transmits an active level signal
  • second second switch control signal line 122 has no signal
  • each second switch transistor T21 connected to the first pixel island 201 is turned on
  • each of the second switching transistors T22 connected to the second pixel island 202 is turned off.
  • the image data output by the driving chip 60 can be transmitted to each data line of the first pixel island 201 through the second switch transistors T21 connected to the first pixel island 201.
  • each second switch transistor T21 connected to the first pixel island 201 is turned off, and the second switch transistor T21 connected to the first pixel island 201 is turned off.
  • the second switching transistors T22 of the two pixel islands 202 are turned on.
  • the image data output by the driving chip 60 can be transmitted to each data line of the second pixel island 202 through the second switch transistors T22 connected to the second pixel island 202 .
  • different image data can be written into the first pixel island 201 and the second pixel island 202 respectively.
  • the same image data can be transmitted to the first pixel island 201 and the second pixel island 202 respectively at the same time.
  • each second switch transistor T21 of the first pixel island 201 is connected to the first The second switching transistors T22 of the two pixel islands 202 are simultaneously turned on.
  • the image data output by the driving chip 60 can be transmitted to the data lines of the first pixel island 201 through the second switch transistors T21 connected to the first pixel island 201 , and can be transmitted through the second switches connected to the second pixel island 202 at the same time.
  • the transistor T22 transmits to each data line of the second pixel island 202 .
  • the image data written in the first pixel island 201 and the second pixel island 202 are the same.
  • the size of the pixel for image display is increased, and the image resolution is reduced.
  • each third switch transistor T3 corresponds to one of the pixel islands 20 connected to the second multiplexing unit 52; the pixel island 20 corresponds to the third switch Among the transistors T2 and the second switching transistors T3, the first poles of the third switching transistors T3 are respectively connected to the second poles of the second switching transistors T2.
  • the second switch control signal line transmits an effective level signal, so that the purpose of writing data to a plurality of pixel islands can be achieved, thereby saving driving pins.
  • the number of the third switching transistors T3 is equal to the number of sub-pixel columns included in one pixel island 20 .
  • the first pixel island includes 16 columns of sub-pixels
  • 32 second switching transistors T2 and 16 third switching transistors are required.
  • the first poles of the 16 third switching transistors T3 are respectively connected to the second poles of the 16 second switching transistors T2 connected to one pixel island. In this way, image data can be transmitted to the second switching transistor T2 through the third switching transistor T3.
  • the third switch transistor T3 is divided into a plurality of third switch transistor groups T3s along the first direction x, and the number of the third switch transistor groups T3s is the same as that of one pixel island.
  • the number of sub-pixel groups 21 included in 20 is equal; in a third switch transistor group T3s, the control electrodes of each third switch transistor T3 are respectively connected to different third switch control signal lines 13, and the third switch transistor T3
  • the diodes are connected to the same input terminal 52i of the second multiplexing unit 52 .
  • the image data written in one sub-pixel group 21 is controlled and transmitted through one third switch transistor group T3s, so the number of the third switch transistor group T3s included in one second multiplexing unit 52 is the same as that of the third switch transistor group T3s.
  • One pixel island 20 includes the same number of sub-pixels and 21 .
  • the number of third switch transistors T3 included in each third switch transistor T3s is the same as the number of third switch control signal lines 13 included in the multiplexing circuit 50 .
  • Each third switching transistor T31 is turned on or off under the control of each third switching control signal line 13.
  • each third switch control signal line 13 outputs an effective level signal in turn, so that each third switch transistor T3 is turned on in turn, the signal of the input terminal 52i is transmitted to the first pole through the second pole of each third switch transistor T31 in turn.
  • different image data can be sequentially transmitted to each of the second switching transistors T2 connected thereto.
  • the image data is controlled to be transmitted to different pixel islands simultaneously or sequentially.
  • each third switch transistor T3 When each third switch signal line 13 outputs an effective level signal at the same time, each third switch transistor T3 can be controlled to be turned on at the same time, then the signal of the input terminal 52i is transmitted to the first pole through the second pole of each third switch transistor T3, Thus, the same image data can be simultaneously transmitted to each of the second switching transistors T2 connected thereto. Further, under the control of the second switch control signal line 12, the image data is controlled to be transmitted to different pixel islands simultaneously or sequentially.
  • the display device provided by the embodiment of the present disclosure further includes: a gate driving circuit 80 and a gate line 800 . in:
  • a plurality of grid lines 800 extend along the first direction x and are arranged along the second direction y; the sub-pixels arranged in the same row along the first direction c are connected to the same grid line 800;
  • the gate driving circuit 80 is located on one side or both sides of the region where the pixel island 20 is located along the first direction x; the gate lines 800 are respectively connected to the gate driving circuit 80 .
  • the gate driving circuit 80 includes a plurality of gate driving units 81 arranged along the second direction y, the gate driving units 81 are cascaded with each other along the second direction y, and each gate driving unit 81 scans the corresponding sub-pixel row independently.
  • the image data in the driving chip 60 needs to be written into the pixel island 20 in conjunction with the scanning signal output by the gate driving circuit 80 .
  • the gate driving circuit 80 transmits the scanning signal to the gate, the transmission of the row of sub-pixels at the gate 800 is effective.
  • the image data can be written into each sub-pixel of the row through the data line 40 only when the level signal is required.
  • the image data of the sub-pixel islands in multiple rows and columns can be controlled at the same time, so that the resolution can be adjusted to a greater extent.
  • the above-mentioned display device may be driven by the first multiplexing unit 51 , or may be driven by the second multiplexing unit 52 .
  • each control unit c remains open, and the second multiplexing unit 52 has no signal transmission.
  • the display device can be controlled to switch the number of viewpoints, so as to achieve adjustment The purpose of display resolution; when the second multiplexing unit 52 is used for driving, each control unit c remains in a closed state, and the first multiplexing unit 51 has no signal transmission.
  • the display device can be controlled to perform viewpoints at the same time The number and pixel island resolution switch, so as to achieve the purpose of adjusting the display resolution.
  • the embodiment of the present disclosure uses a specific example to describe the circuit connection relationship.
  • FIG. 7 is a third partial enlarged view of a display device provided by an embodiment of the present disclosure.
  • FIG. 7 shows the circuit connection relationship of four adjacent pixel islands
  • the display device includes a plurality of units shown in FIG. 7 .
  • the display device includes a plurality of pixel islands, each pixel island includes sixteen red sub-pixels r, sixteen green sub-pixels g and sixteen blue sub-pixels b, red sub-pixels r, green sub-pixels
  • the g and blue sub-pixels b are arranged in three rows along the first direction x and arranged in sixteen columns along the second direction y.
  • One pixel island is mapped by the microlens layer to form sixteen pixels arranged in four rows and four columns.
  • the subpixels in one pixel island are divided into four subpixel groups 21 along the first direction x, and each subpixel group 21 includes four subpixel columns.
  • the multiplexing circuit 50 includes a plurality of first multiplexing units 51 , and one pixel island corresponds to four first multiplexing units 51 .
  • the multiplexing circuit 50 includes four first switch control signal lines l1, and one first multiplexing unit 51 includes four first switch transistors T1; A switch control signal line 11, the first poles of the four first switch transistors are connected to the data lines 40 corresponding to the four sub-pixel columns in one sub-pixel group 21 in a one-to-one correspondence; the second poles of the four first switch transistors T1 are mutually connect.
  • the multiplexing circuit 50 includes a control unit c, and one pixel island corresponds to four control units c.
  • a first multiplexing unit 51 is connected to the driving chip 60 through a control unit c.
  • the multiplexing circuit 50 includes a control signal line lc, a control unit c includes a control switch transistor Tc; the control electrodes of each control switch transistor Tc are connected to the control signal line lc, and the control switch transistor Tc in one control unit c
  • the first poles are connected to the second poles of the four first switching transistors T1 in one first multiplexing unit 51 , and the second poles of the control switching transistors Tc are connected to the driving chip 60 .
  • the multiplexing circuit 50 includes a plurality of second multiplexing units, and one second multiplexing unit 52 is correspondingly connected to two pixel islands arranged along the first direction x, and the two pixel islands are divided into first pixel islands. 201 and the second pixel island 202.
  • the multiplexing circuit 50 includes two second switch control signal lines l2 and four third switch control signal lines l3.
  • a second multiplexing unit 52 includes 32 second switching transistors T2, the data lines of the first pixel island 201 are correspondingly connected to 16 second switching transistors T2, and the number lines of the second pixel island 202 are correspondingly connected to 16 second switching transistors T2. switching transistor T2.
  • the control electrodes of the 16 six second switching transistors T2 corresponding to the first pixel island 201 are all connected to one of the second switching control signal lines l2, and the control electrodes corresponding to the 16 six second switching transistors T2 of the second pixel island 202 Both are connected to another second switch control signal line l2.
  • the first poles of the second switching transistors T2 corresponding to the first pixel island 201 are connected to the data lines of the first pixel island 201 in a one-to-one correspondence, and the first poles of the second switching transistors T2 corresponding to the second pixel island 202
  • the data lines of the second pixel islands 202 are connected in a one-to-one correspondence.
  • the second pole of the second switch transistor T2 connected to the sub-pixels of the first column of the first pixel island 201 is connected to the second pole of the second switch transistor T2 connected to the sub-pixels of the first column of the second pixel island 202.
  • the second pole of the second switch transistor T2 connected to the sub-pixels of the second column of 201 is connected to the second pole of the second switch transistor T2 connected to the sub-pixels of the second column of the second pixel island 202, and so on.
  • the second pole of the second switching transistor T2 connected to the sub-pixels in the sixteenth column of 201 and the second pole of the second switching transistor T2 connected to the sub-pixels of the sixteenth column of the second pixel island 202 are connected to each other.
  • a second multiplexing unit 52 includes 16 third switching transistors T3, the 16 third switching transistors T3 correspond to the first pixel island 201, and the 16 third switching transistors T3 are divided into four third switching transistors along the first direction x. Three switch transistor group.
  • the control poles of the four third switch transistors T3 in a third switch transistor group T3s are connected to the four third switch control signal lines 12 in a one-to-one correspondence, and the second poles of the second switch transistors T2 corresponding to the same sub-pixel column are connected to the first switch.
  • the first poles of the three switch transistors T3 and the second poles of the four third switch transistors T3 are connected to each other and connected to the driving chip 60 .
  • the display device further includes a gate drive circuit located on one side of the pixel island along the first direction x, the gate drive circuit includes a plurality of gate drive units (811-816) cascaded with each other, and the gate drive circuit includes a plurality of gate drive units (811-816).
  • the cells are respectively connected with a row of sub-pixels through a gate.
  • the gate driving units (811-816) output scan signals to the corresponding gates, under normal circumstances, the gates corresponding to the sub-pixels in each row transmit active level signals in sequence.
  • the first row of sub-pixels can write the image data on the corresponding data line into the sub-pixels during the period when the gate line transmits the active level signal; after the first row of sub-pixels finishes writing the image data, the second row of sub-pixels The image data on the corresponding data line is written into the sub-pixels during the period when the gate line transmits the active level signal; and so on, after all the sub-pixels have written the image data, one frame of image display can be realized.
  • the control switch transistor Tc when the first multiplexing unit 51 is used for driving, the control switch transistor Tc is kept on, and the second multiplexing unit 52 has no signal transmission.
  • the four first switching transistors T1 in the first multiplexing unit 51 can be controlled to be turned on in sequence, so that the corresponding four columns of sub-pixels can write image data in sequence.
  • high-resolution image display or by controlling the four first switching transistors T1 to be turned on at the same time, so that the corresponding four columns of sub-pixels can write the same image data at the same time, at this time, the number of viewpoints generated by one pixel island can be reduced, and low-resolution Image display.
  • the control switch transistor Tc When the second multiplexing unit 52 is used for driving, the control switch transistor Tc is kept in an off state, and the first multiplexing unit 51 has no signal transmission. At this time, the 16 second switching transistors T2 corresponding to the first pixel island 201 can be controlled to be turned on first, image data can be written to the first pixel island 201, and then the 16 second switching transistors T2 corresponding to the second pixel island 202 can be controlled to be turned on , write image data to the second pixel island 202, keep the image data written in different pixel islands different, and perform high-resolution image display; The second switch transistor T2 is turned on at the same time, the same image data is written to the first pixel island 201 and the second pixel island 202, the image resolution is reduced while the number of viewpoints generated by the pixel island remains unchanged, and a low-resolution image is displayed.
  • the gate driving units 801 and 804 it is also possible to control the gate driving units 801 and 804 to transmit the same scan signal, the gate driving units 802 and 805 to transmit the same scan signal, and the gate driving units 803 and 806 to transmit the same scan signal, so that the first The pixel island 201 , the second pixel island 202 , the third pixel island 203 and the fourth pixel island 204 write the same image data to further reduce the image resolution.
  • the four third switching transistors T3 in one third switching transistor group T3s can also be controlled to be turned on in sequence, so that The corresponding 4-column sub-pixels are sequentially written with image data, and at this time, one pixel island generates multiple viewpoints; or by controlling the 4 third switching transistors T3 to be turned on at the same time, the corresponding 4-column sub-pixels can simultaneously write the same image data , the number of viewpoints generated by the pixel island can be reduced.
  • the above-mentioned display device provided by the embodiment of the present disclosure can adjust the above-mentioned image resolution, so as to realize high-resolution image display in the display area that is watched by the user, and realize low-resolution image display in other display areas, thereby ensuring the user On the premise of experience, reduce power consumption and achieve a reasonable allocation of resources.
  • FIG. 8 is a flowchart of the method for driving a display device according to an embodiment of the present disclosure.
  • the driving method of the display device includes:
  • the first resolution is higher than the second resolution.
  • the embodiment of the present disclosure determines the gaze area and the non-gazing area of the image displayed by the display device by setting means, drives the gaze area to display images with high resolution, and drives the non-gazing area to display images with low resolution, so as to ensure that the attention is paid to.
  • the image display quality of the fixation area is improved, and the image resolution of the non-fixation area is reduced, thereby reducing the overall power consumption and avoiding the waste of resources.
  • step S10 determining in real time the gaze area and the non-gazing area of the user on the display device, including:
  • An area other than the gaze area in the display device is determined as a non-gazing area.
  • the display image of the display device is usually large, and the human eye can only focus on a local area of the displayed image. Therefore, in this embodiment of the present disclosure, a camera is set on the display device, or an external camera is used to track the movement of the human eye on the display device in real time.
  • the gaze area is driven in real time to display an image at a high resolution, and the non-gaze area is driven to display an image at a low resolution, thereby avoiding resource waste.
  • determining the gaze area of the user on the display device according to the image captured by the camera including:
  • the user's left eye and right eye According to the positions of the user's left eye and right eye relative to the display surface of the display device, and the distance between the user and the display device, it is respectively determined that the user's left eye is in the left eye gaze area of the display device and the user's right eye is displaying The right eye gaze area of the device;
  • the overlapping area of the left eye gaze area and the right eye gaze area is taken as the gaze area of the user on the display device.
  • the gaze area of the user's single eye on the display device can be determined by the following formula:
  • S represents the gaze area of the user's single eye on the display device
  • A represents the distance between the user and the display device.
  • FIG. 9a is one of the schematic diagrams of generating a gaze area for a human eye according to an embodiment of the present disclosure
  • FIG. 9b is the second schematic diagram of a human eye generating a gaze area according to an embodiment of the present disclosure.
  • the human eye usually has a limit viewing angle when viewing the display device, that is, when the position of the human eye relative to the display surface of the display device is fixed, the human eye can only see the range of the viewing angle when looking at the display device. content within. Under normal circumstances, the viewing angle generated by a single eye is about 30 degrees.
  • the left eye gaze area on the display device is sl1
  • the right eye is on the display device.
  • the generated right eye gaze area is sr1
  • the overlapping area sx1 of the left eye gaze area and the right eye gaze area is determined as the gaze area of the user's eyes on the display device.
  • the left eye gaze area generated by the left eye on the display device is sl2
  • the right eye gaze area generated by the right eye on the display device is sr2
  • the left eye gaze area is sr2.
  • the overlapping area sx2 of the area and the right eye gaze area is determined as the gaze area of the user's eyes on the display device.
  • the gaze area generated on the display device is reduced from sx1 to sx2, calculated based on the viewing angle of one eye being 30 degrees. It can be seen that the gaze area generated by the user's eyes on the display device depends on the viewing angle and the distance from the user to the display device. Under the premise of a fixed viewing angle, the farther the user is from the display device, the larger the gaze area generated.
  • the gaze area After determining the gaze area of the user on the display device, the gaze area can be driven to perform high-definition display, while other non-gazing areas are displayed in low-definition, thereby saving resources.
  • FIG. 10 is a schematic diagram of a display partition of a display device according to an embodiment of the present disclosure
  • FIG. 11 is a schematic diagram of a display effect of the display device shown in FIG. 10 .
  • the display area can be divided into multiple areas along the extension direction of the gate driving circuit.
  • the embodiment of the present disclosure can divide the display area into 16 partitions, 16 partitions 16 gate drive units (GOA1-GOA16) are used to drive independently.
  • the gate driving units GOA5-GOA9 After writing image data to each sub-pixel in the fixation area and the non-fixation area, the display effect is shown in Figure 11.
  • the fixation area displays high-definition images
  • the non-fixation area displays low-definition images, thereby saving resources and power consumption.
  • the driving mode of the corresponding area is changed in real time, so as to realize dynamic adjustment of high-definition images and low-definition images.
  • the image data input by the display device is two-dimensional image data.
  • the image data input by the display device is for 3D image data.
  • step S20 driving the gaze area to perform image display at the first resolution, and driving the non-gazing area to perform image display at the second resolution, specifically includes:
  • the display mode selected by the user is a two-dimensional display mode, driving the gaze area to display a two-dimensional image with a first resolution, and driving the non-gazing area to display a two-dimensional image with a second resolution;
  • the display mode selected by the user is the three-dimensional display mode, driving the gaze area to display a three-dimensional image at a first resolution, and driving the non-gazing area to display a two-dimensional image at a second resolution;
  • the gaze area is driven to display the three-dimensional image at the first resolution
  • the non-attention area is driven to display the three-dimensional image at the second resolution.
  • the image data input by the display device is two-dimensional image data
  • the display image the user wishes to watch is a two-dimensional image
  • the user only looks at a part of the display device on the display device, Then, at this time, the two-dimensional image display is performed with high resolution for the gaze area, and the two-dimensional image display is performed with low resolution for the non-gazing area, so as to avoid waste of resources.
  • the image data input by the display device is the 3D image data
  • the display image the user wants to watch is the 3D image
  • the user only looks at a part of the display device on the display device, then at this time , display 3D images with high resolution for the gaze area, and perform 2D image display or 3D image display at low resolution for the non-gazing area, thereby ensuring that the gaze area has a better display effect and reducing the data of the non-gazing area.
  • Transfer volume and charging time save power consumption.
  • driving the gaze area to perform two-dimensional image display at a first resolution, and driving the non-gazing area to perform two-dimensional image display at a second resolution including:
  • the first switch control signal lines corresponding to the gaze area are controlled to output active level signals in turn, so that each first switch transistor in the first multiplexing unit is turned on in turn to transmit different two-dimensional image data, and the control signal corresponding to the non-gazing area is controlled.
  • Each of the first switch control signal lines of the first switch control signal line simultaneously outputs an active level signal, so that each first switch transistor in the first multiplexing unit is turned on at the same time to transmit the same two-dimensional image data, so as to realize driving the gaze area with the first resolution
  • the two-dimensional image display is performed at the second resolution, and the non-gazing area is driven to perform the two-dimensional image display at the second resolution.
  • driving the gaze area to perform 3D image display at the first resolution, and driving the non-gazing area to perform 3D image display at the second resolution including:
  • the first switch control signal lines corresponding to the gaze area are controlled to output active level signals in turn, so that the first switch transistors in the first multiplexing unit are turned on in turn to transmit different three-dimensional image data, and the control signal lines corresponding to the non-gazing area are controlled.
  • Each first switch control signal line outputs an active level signal at the same time, so that each first switch transistor in the first multiplexing unit is turned on at the same time to transmit the same three-dimensional image data, so as to realize the driving of the gaze area with the first resolution.
  • the non-gazing area is driven to perform three-dimensional image display at the second resolution.
  • driving the gaze area to display a three-dimensional image at a first resolution, and driving the non-gazing area to display a two-dimensional image at a second resolution including:
  • the image rendering of the first resolution is carried out to the three-dimensional image data for the gaze area, and the image rendering of the second resolution is carried out to the two-dimensional image data for the non-attention area;
  • the first switch control signal lines corresponding to the gaze area are controlled to output active level signals in turn, so that each first switch transistor in the first multiplexing unit is turned on in turn to transmit different three-dimensional image data, and the control signal lines corresponding to the non-gazing area are controlled.
  • Each first switch control signal line outputs an active level signal at the same time, so that each first switch transistor in the first multiplexing unit is turned on at the same time to transmit the same two-dimensional image data, so as to realize driving the gaze area with a first resolution 3D image display is performed, and the non-gazing area is driven to perform 2D image display at the second resolution.
  • the first multiplexing unit can be used to drive the above-mentioned image display, and the specific driving circuit can adopt the structure shown in 4 .
  • FIG. 12a is one of the driving timing diagrams corresponding to the gaze area provided by the embodiment of the present disclosure
  • FIG. 12b is one of the driving timing diagrams corresponding to the non-gazing area provided by the embodiment of the present disclosure.
  • each pixel island is connected to four first multiplexing units 51 , each first multiplexing unit 51 includes four first switching transistors T1 , and the multiplexing circuit includes four first multiplexing units 51 .
  • the switch control signal line 11 and the switch control signals output by the four first switch control signal lines are respectively SW1-SW4 shown in FIG. 12a.
  • the scanning signals transmitted by the gates corresponding to the sub-pixels in each row are G1, G2 . . . shown in FIG. 12a, respectively, and the image data output by the driving chip is D shown in FIG. 12a.
  • the four first switch control signal lines 11 are made to output active level signals (high level signals) in sequence, so that the corresponding four A switch transistor T1 is turned on in turn for outputting different image data to the sub-pixels in each column of the pixel island.
  • the other gate line output scan signals are at a low level.
  • the first first switch control signal line first outputs a high level signal (SW1 is at a high level), and the other three first switch control signal lines all output a low level signal (SW2-SW41 are low level), at this time, only the first switch transistor connected to the first first switch control signal line is turned on, and the image data output by the driver chip is transmitted to the first switch transistor of the pixel island through the first first switch transistor.
  • the second first switch control signal line outputs a high level signal (SW2 is high level), and the other three first switch control signal lines all output low level signals (SW1, SW3, SW4 are low level signals)
  • SW2 high level
  • SW3 high level
  • SW4 fourth first switch controls the signal line Output high level signal
  • SW1-SW3 fourth first switch controls the signal line Output high level signal
  • the second gate line output scan signal G2 becomes an active level (high level), and each first multiplexer The multiplexing unit repeats the above operations, and so on, so that each sub-pixel in the gaze area writes image data in sequence, so as to realize the high-resolution image display of the gaze area.
  • the four first switch control signal lines l1 output active level signals (high level signals) at the same time, so that the corresponding four The first switching transistors T1 are simultaneously turned on for outputting the same image data to the sub-pixels in each column of the pixel island.
  • the other gate line output scan signals are at a low level.
  • the four first switch control signal lines simultaneously output high-level signals (SW1-SW4 are high level), and at this time, the four first switch control signal lines are connected to the fourth One switch transistor is turned on at the same time, and the image data output by the driving chip is simultaneously transmitted to the four columns of sub-pixels of the pixel island through the four first switch transistors.
  • the multiplexing unit repeats the above operations, and so on, so that every four columns of sub-pixels in the non-gazing area simultaneously write the same image data, thereby reducing the image resolution by 4 times and realizing low-resolution image display in the non-gazing area.
  • the image data transmitted by the driving chip through each of the first multiplexing units is two-dimensional image data, and both the gaze area and the non-gaze area are displayed with two-dimensional images, and the gaze area is displayed in two dimensions.
  • the image resolution of is greater than that of the non-fixation area.
  • both the gaze area and the non-gazing area can display 3D images, or the gaze area can perform 3D image display, and the non-gazing area can perform 2D image display.
  • the driving chip transmits the three-dimensional image data to the gaze area through each of the first multiplexing units, and transmits the three-dimensional image data or the two-dimensional image data to the non- gaze area.
  • the image source input by the controller is 3D image data or 2D image data
  • 3D image display is performed in the gaze area
  • 2D image display is performed in the non-gazing area
  • the 3D image data in the non-gazing area needs to be converted into
  • the two-dimensional image data is then transmitted to each first multiplexing unit corresponding to the non-gazing area.
  • the controller will perform corresponding image rendering on the image data, and the rules of image rendering can refer to the prior art, which will not be repeated here.
  • the display device provided by the embodiment of the present disclosure may include a first multiplexing unit and a second multiplexing unit at the same time, and the embodiment of the present disclosure may also use the first multiplexing unit to cooperate with the second multiplexing unit to drive
  • the specific driving circuit can adopt the structure shown in 5.
  • FIG. 13a is the second driving timing diagram corresponding to the gaze area provided by the embodiment of the present disclosure
  • FIG. 13b is the second driving timing diagram corresponding to the non-gazing area provided by the embodiment of the present disclosure.
  • Each first multiplexing unit 51 includes four first switch transistors T1, and the multiplexing circuit includes four first switch control signal lines l1, and the switch control signals output by the four first switch control signal lines l1 are shown in Fig. SW1-SW4 shown at 13a.
  • Each second multiplexing unit 52 includes 32 second switching transistors T2, 16 third switching transistors T3 and one control switching transistor Tc; the multiplexing unit includes two second switching control signal lines l2, four The third switch controls the signal line l3 and one control signal line lc.
  • the switch control signals output by the two second switch control signal lines 12 are respectively SWO-SWE shown in FIG. 13a, and the switch control signals output by the four third switch control signal lines 13 are respectively SWb-SWe shown in FIG. 13a.
  • the switch control signal output by the signal line lc is SWa shown in FIG. 13a.
  • the scanning signals transmitted by the gates corresponding to the sub-pixels in each row are G1, G2 . . . shown in FIG. 13a, respectively, and the image data output by the driving chip is D shown in FIG. 13a.
  • control signal line lc can be made to output a valid level signal (high level signal), and each second switch control signal line 12 and each third switch control signal line 13 output a low level, As a result, the second multiplexing unit 52 is turned off, and the first multiplexing unit is used for driving.
  • the four first switch control signal lines l1 are made to output active level signals (high level signals) in turn, so that the corresponding four first switch transistors T1 are turned on in turn for sending signals to the pixel island.
  • Each column of sub-pixels outputs different image data.
  • the other gate line output scan signals are at a low level.
  • the first first switch control signal line first outputs a high level signal (SW1 is at a high level), and the other three first switch control signal lines all output a low level signal (SW2-SW41 are low level), at this time, only the first switch transistor connected to the first first switch control signal line is turned on, and the image data output by the driver chip is transmitted to the first switch transistor of the pixel island through the first first switch transistor.
  • the second first switch control signal line outputs a high level signal (SW2 is high level), and the other three first switch control signal lines all output low level signals (SW1, SW3, SW4 are low level signals)
  • SW2 high level
  • SW3 high level
  • SW4 fourth first switch controls the signal line Output high level signal
  • SW1-SW3 fourth first switch controls the signal line Output high level signal
  • the second gate line output scan signal G2 becomes an active level (high level), and each first multiplexer The multiplexing unit repeats the above operations, and so on, so that each sub-pixel in the gaze area writes image data in sequence, so as to realize the high-resolution image display of the gaze area.
  • the four first switch control signal lines 11 are made to output active level signals (high level signals) at the same time, so that the corresponding four first switch transistors T1 are simultaneously turned on for sending signals to the pixels
  • the sub-pixels in each column of the island output the same image data.
  • the other gate line output scan signals are at a low level.
  • the four first switch control signal lines simultaneously output high-level signals (SW1-SW4 are high level), and at this time, the four first switch control signal lines are connected to the fourth One switch transistor is turned on at the same time, and the image data output by the driving chip is simultaneously transmitted to the four columns of sub-pixels of the pixel island through the four first switch transistors.
  • the multiplexing unit repeats the above operations, and so on, so that every four columns of sub-pixels in the non-fixation area simultaneously write the same image data, thereby reducing the image resolution by 4 times and realizing low-resolution image display in the non-fixation area.
  • the charging time of the sub-pixels in the non-gazing area is 1/4 of the charging time of the sub-pixels in the watching area, then the scanning time of the gate driving unit corresponding to the watching area will be longer than the scanning time of the gate driving unit corresponding to the non-gazing area. duration. Specifically, the duration of the gate drive unit corresponding to the non-gazing area outputting the active level can be shortened to 1/4 of the duration of the gate driving unit corresponding to the gaze area outputting the effective level, and the first multiplexing unit of the non-gazing area Compared with the gaze area, the number of turns on is reduced by 3/4, and the power consumption is reduced by 1/4 of the original. Since the charging time of the non-gaze area is shortened, the time saved can be used to increase the refresh rate of the displayed image, or it can also be used to increase the refresh rate of the gaze area, thereby improving the display effect.
  • the gaze area includes 1,000 rows of sub-pixels
  • the non-gaze area includes 1,000 rows of sub-pixels.
  • the required charging time is 1000*4*t
  • 4K image data can generate 16 viewpoints, while achieving an image refresh rate of 20Hz; using the driving scheme shown in Fig. 13b to drive the display device, 4K image data can generate 4 viewpoint, while achieving an image refresh rate of 80Hz. It can be seen that when reducing the number of viewpoints (reducing the image resolution), the time saved can be used to increase the image refresh rate.
  • FIG. 14 is a comparison diagram of charging voltages in a gaze area and a non-gaze area provided by an embodiment of the present disclosure.
  • the charging voltage (4p) after four columns of sub-pixels are charged at the same time is lower than the charging voltage (1p) after each column of sub-pixels is charged sequentially, because the load generated when four columns of sub-pixels are charged at the same time If it is larger, then using the same driving current to drive four columns of sub-pixels to charge at the same time will cause insufficient charging of the four columns of sub-pixels, that is, when the same driving current is used to charge the sub-pixels in the fixation area and the non-attention area, it will cause insufficient charge in the non-attention area. The problem that causes the screen to display unevenly.
  • the embodiment of the present disclosure adjusts the driving current of the driving chip, and increases the driving current of the driving chip to the non-gazing area, so that the difference between the charging levels of the sub-pixels in the watching area and the non-gazing area is less than the set value
  • the threshold value can be set to a small value, so that the charging levels of the sub-pixels in the gaze area and the non- gaze area tend to be equal.
  • the drive current of the fixation area can be adjusted to 60%-80% of the original drive current, and the drive current of the non-fixation area can be adjusted to 100%-120% of the original drive current
  • the display device is driven so that the sub-pixels in the gazing area and the non-gazing area can be fully charged, so as to avoid the problem of uneven display of the picture.
  • the controller can send a control instruction to the register connected to the bias circuit of the driver chip according to the CHPI protocol, so that the driver chip can distinguish the gaze area and the non-gazing area using the drive current stored in the register to respectively control the gaze area and the non-gazing area. to drive.
  • the display device provided by the embodiment of the present disclosure may also be driven by using the second multiplexing unit 52 .
  • the specific drive circuit can adopt the structure shown in 7.
  • FIG. 15a is the third driving timing diagram corresponding to the gaze area provided by the embodiment of the present disclosure
  • FIG. 15b is the third driving timing diagram corresponding to the non-gazing area provided by the embodiment of the present disclosure.
  • the gate driving circuit of the display device includes a plurality of gate driving units ( 811 - 816 ), and each gate driving unit outputs a scan signal to a corresponding sub-pixel row respectively.
  • the connection relationship between each pixel island and the first multiplexing unit 51 and the second multiplexing unit 52 is the same as that in FIG. 5 , which is not repeated here.
  • the control signal line always outputs a low level (SWa), so that the control switch transistor Tc is kept in an off state, and the signal cannot be It is transmitted to the first multiplexing unit 51 , and the transmission of the image data is controlled by the second multiplexing unit 52 .
  • SWa low level
  • Using the second multiplexing unit 52 to drive the display device can not only transmit image data to multiple pixel islands in sequence, but also transmit the same image data to multiple pixel islands simultaneously.
  • each second switch control signal line is controlled to output an active level signal (SWO and SWE are high level signals) at the same time, so that the The second switching transistors T2 in the second multiplexing unit are turned on at the same time; at the same time, the outputs of the gate driving unit connected to the sub-pixels in the nth row and the gate driving units connected to the sub-pixels in the n+3th row are controlled.
  • the signals are the same; where n is an integer greater than or equal to 1.
  • the first gate line output scan signal G1 when the four adjacent pixel islands 20 in two rows and two columns are driven to load the same image data, when the first gate line output scan signal G1 is in the active level period (high level period), the The scanning signals G4 output by the four gate lines are the same as G1, and the output scanning signals of the other gate lines are low level. Each gate line maintains an active level for a period of 1t.
  • the two second switch control signal lines both output high-level signals (both SWO and SWE are high-level), at this time, the above-mentioned four All 32 second switching transistors T2 of the pixel island are turned on.
  • Image data can be transmitted to four pixel islands at the same time, and the image data loaded by the four pixel islands is the same, then the four pixel islands can be used as one large pixel island, thereby reducing the overall resolution.
  • the above driving method can be applied to the non-gazing area for low-resolution image display.
  • the four third switch control signal lines to output high-level signals (SWb-SWe are both high-level), and at this time, four of the third switch transistor groups T3s
  • the third switching transistors T3 are turned on at the same time, and the same data signals are simultaneously transmitted for the four columns of sub-pixels in each pixel island, which can further reduce the number of viewpoints generated by the pixel island, that is, reduce the resolution in the pixel island.
  • the method can be applied to non-gazing regions for low-resolution image display.
  • the period when the first gate line output scan signal G1 is at an active level ends, the second gate line output scan signal G2 becomes an active level (high level), and the fifth gate line
  • the output scan signal G5 is the same as G2, and each second multiplexing unit repeats the above operations, and so on, to achieve low-resolution image display in the non-gazing area.
  • each second switch control signal line is controlled to output an effective level signal (high level signal) in turn, so that the second multiplexing unit in the The second switching transistors connected to different pixel islands are turned on in turn for transmitting different image data.
  • the scan signal G1 output by the first gate line is an active level period (high level period)
  • the scan signal G4 output by the fourth gate line is the same as G1
  • the scan signal output by the second gate line The effective level period of G2 is 1t later than that of G1
  • the scanning signal output by the fifth gate line is the same as that of G2; and so on.
  • the duration of each gate line maintaining a high level is the duration required for the four columns of sub-pixels to be charged in sequence (the duration of maintaining a high level is 4t).
  • the signal output by the fourth gate line is the same as that of the first gate line, and the two second switch control signal lines output active level signals in turn, that is, the first second switch
  • the control signal line first outputs a high level signal (SWO is high level), the second second switch control signal line outputs a low level signal (SWE is low level), and then the second second switch control signal line outputs The active level signal (SWE high level signal), the first second switch control signal line outputs a low level signal (SWO is low level); the duration of each second switch control signal line outputting an effective level is The duration required for charging a column of sub-pixels (the active level duration is 1t).
  • the 16 second switch transistors T2 connected to the first pixel island are turned on under the control of the first second switch control signal line
  • the 16 second switch transistors T2 connected to the second pixel island are turned on in the second
  • the 16 second switching transistors T2 connected to the first pixel island are turned on.
  • the two switching transistors T2 are turned off under the control of the first on-control signal line, thereby realizing sequentially loading image data to each pixel island.
  • each second switch transistor T2 performs the above-mentioned driving
  • the four third switch control signal lines sequentially output active level signals (high level signals), and each third switch control signal line maintains a high level
  • the duration of the flat signal is 2t.
  • the first third switch control signal line When the first third switch control signal line outputs a valid level signal (SWb is high level), the other three third switch control signal lines all output low level signals (SWc-SW4e are low level). Only the third switch transistor connected to the first third switch control signal line is turned on, and the image data output by the driver chip is transmitted to the sub-pixels in the first column of the first pixel island through the first third switch transistor, and the image output by the driver chip The data is then transmitted to the sub-pixels of the first column of the second pixel island through the first third switching transistor. Then the second third switch control signal line outputs a high level signal (SWc is high level), and the other three third switch control signal lines all output low level signals (SWb, SWd, SWe are low level).
  • the third switch transistor connected to the second third switch control signal line is turned on, and the image data output by the driver chip is transmitted to the sub-pixels in the second column of the first pixel island through the second third switch transistor.
  • the image data is then transmitted to the second column of sub-pixels of the second pixel island through the second third switching transistor.
  • the third third switch control signal line outputs a high level signal (SWd is high level), and the other three third switch control signal lines all output low level signals (SWb, SWc, SWe are low level).
  • SWd high level
  • SWb, SWc, SWe all output low level signals
  • the image data is then transmitted to the third column sub-pixels of the second pixel island through the third third switching transistor.
  • the fourth third switch control signal line outputs a high-level signal (SWe is a high level), and the other three third switch control signal lines all output a low-level signal (SWb-SWd is a low level).
  • the third switch transistor connected to the fourth third switch control signal line is turned on, and the image data output by the driver chip is transmitted to the fourth column sub-pixels of the first pixel island through the fourth third switch transistor, and the image data output by the driver chip It is then transmitted to the fourth column sub-pixels of the second pixel island through the fourth third switching transistor.
  • 2K image data can generate 4 viewpoints, while achieving an image refresh rate of 80Hz; using the driving scheme shown in Figure 15b to drive the display device, 2K image data can generate 16 viewpoint, while achieving an image refresh rate of 80Hz. It can be seen that by controlling multiple pixel islands to charge at the same time, the number of viewpoints can also be adjusted.
  • FIG. 16 is a schematic diagram of a system architecture of a display device according to an embodiment of the present disclosure.
  • the image data of the 2D video source is received; when the user selects the 3D display mode, the image data of the 3D video source is received.
  • the camera monitors the position of the human eye in real time, thereby determining the coordinates of the gaze point of the human eye on the display device and analyzing the number of people watching the display device. After determining the gaze position of the human eye on the display device, the display image is divided into a gaze area and a non-gazing area, and a high-resolution image rendering is performed on the gaze area according to the user's selection mode, and a low-resolution image is performed on the non-gazing area.
  • the image data after image rendering is sent to the driver chip of the display panel, so that the display panel is driven according to the instruction.
  • the liquid crystal lens can be controlled to load an appropriate scan drive signal, so that high-resolution image display is performed in the gaze area, and low-resolution image display is performed in the non-gazing area, thereby reducing the user experience. Power consumption, to achieve a reasonable allocation of resources.
  • controller may be a display chip (Graphics Processing Unit, referred to as GPU) and/or Field-Programmable Gate Array (Field-Programmable Gate Array, referred to as FPGA) , which is not limited here.
  • GPU Graphics Processing Unit
  • FPGA Field-Programmable Gate Array

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Abstract

一种显示装置及其驱动方法，包括：实时确定用户在显示装置的注视区域和非注视区域(S10)；驱动注视区域以第一分辨率进行图像显示，驱动非注视区域以第二分辨率进行图像显示(S20)；第一分辨率高于第二分辨率。显示装置可以分区域对图像分辨率进行调整，以在被用户注视的显示区域实现高分辨的图像显示，在其它显示区域实现低分辨率的图像显示，由此在保证用户体验的前提下降低功耗，达到资源的合理分配。

Description

显示装置及其驱动方法 技术领域
本公开涉及显示技术领域，尤其涉及一种显示装置及其驱动方法。
背景技术
裸眼3D技术是指在不借助任何辅助设备的情况下就可以获得具有空间和深度感知的3D显示技术。随着用户对观察体验的越来越高的要求，高清显示分辨率及裸眼3D显示技术正在逐步应用在显示屏幕上。
高清显示屏的分辨率可以达到4K或更高，为了给用户更逼真的显示效果体验，裸眼3D技术结合高清显示屏可以实现高清立体显示效果。然而全屏高清3D显示所需传输的数据带宽非常大，而人眼只会注视屏幕的区域较少，那么在非注视区存在不必要的数据资源浪费。
发明内容
本公开实施例提供一种显示装置，包括：
衬底基板；
多个像素岛，位于所述衬底基板上；所述像素岛包括多个不同颜色的子像素，所有子像素沿第一方向和第二方向呈阵列排布，一个所述像素岛中颜色相同的子像素沿所述第一方向排列成一行，不同颜色的子像素行沿所述第二方向排列，所述第一方向和所述第二方向交叉；
多条数据线，沿所述第一方向排列且沿所述第二方向延伸；沿所述第二方向排列成同一列的子像素连接同一条所述数据线；
多路复用电路，沿所述第二方向位于所有像素岛所在区域的一侧；所述数据线分别连接所述多路复用电路；
驱动芯片，沿所述第二方向位于所述多路复用电路背离所述像素岛的一侧，所述多路复用电路连接所述驱动芯片；
控制器，连接所述驱动芯片，被配置为向所述驱动芯片提供驱动信号；
微透镜层，位于所述像素岛背离所述衬底基板的一侧，所述微透镜层对所述像素岛的出射光线进行调制，以使所述像素岛中的子像素映射为像素阵列并实现三维显示；
一个所述像素岛中的子像素列沿所述第一方向分为多个子像素组，每个所述子像素组中包括的子像素列的数量相等；
所述多路复用电路包括多个沿所述第一方向排列的第一多路复用单元，所述第一多路复用单元包括一个输入端和多个输出端；一个所述第一多路复用单元对应连接一个所述子像素组，所述第一多路复用单元的输出端分别连接所述子像素组对应的数据线，所述第一多路复用单元的输入端连接所述驱动芯片。
本公开一些实施例中，所述多路复用电路还包括：
多条第一开关控制信号线，所述第一开关控制信号线沿所述第一方向延伸沿所述第二方向排列；
所述第一多路复用单元包括：多个第一开关晶体管，所述第一开关晶体管的控制极连接所述第一开关控制信号线，所述第一开关晶体管的第一极连接所述第一多路复用单元的输出端，所述第一开关晶体管的第二极连接所述第一多路复用单元的输入端；
一个所述第一多路复用单元中，各所述第一开关晶体管的控制极分别连接不同的所述第一开关控制信号线，各所述第一开关晶体管的第一极分别连接所述第一多路复用单元的不同的输出端。
本公开一些实施例中，所述多路复用电路还包括：
多个控制单元，沿所述第二方向位于所述第一多路复用单元背离所述像素岛的一侧，所述控制单元沿所述第一方向排列；所述控制单元包括一个输入端和一个输出端；一个所述控制单元对应连接一个所述第一多路复用单元，所述控制单元的输出端连接所述第一多路复用单元的输入端，所述控制单元的输入端连接所述驱动芯片。
本公开一些实施例中，所述多路复用电路还包括：
控制信号线，沿所述第一方向延伸；
所述控制单元包括：控制开关晶体管；所述控制开关晶体管的控制极连接所述控制信号线，所述控制开关晶体管的第一极连接所述控制单元的输出端，所述控制开关晶体管的第二极连接所述控制单元的输入端。
本公开一些实施例中，所述多路复用电路还包括：
多个第二多路复用单元，沿所述第二方向位于所述第一多路复用单元背离所述像素岛的一侧，所述第二多路复用单元沿所述第一方向排列；所述第二多路复用单元包括多个输入端和多个输出端，所述输入端的数量小于所述输出端的数量；一个所述第二多路复用单元对应连接沿所述第一方向排列的多个所述像素岛，所述第二多路复用单元的输出端分别连接各所述像素岛中的各子像素列对应的数据线，所述第二多路复用单元的输入端分别连接所述驱动芯片。
本公开一些实施例中，所述多路复用电路还包括：
多条第二开关控制信号线，所述第二开关控制信号线沿所述第一方向延伸沿所述第二方向排列；
多条第三开关控制信号线，所述第三开关控制信号线沿所述第一方向延伸沿所述第二方向排列；
所述第二多路复用单元包括：多个第二开关晶体管和多个第三开关晶体管；
所述第二开关晶体管的控制极连接所述第二开关控制信号线，所述第二开关晶体管的第一极连接所述第二多路复用单元的输出端，所述第二开关晶体管的第二极连接所述第三开关晶体管的第一极；所述第三开关晶体管的控制极连接所述第三开关控制信号线，所述第三开关晶体管的第二极连接所述第二多路复用单元的输入端；
一个所述第二多路复用单元中，连接同一个所述像素岛的所述第二开关晶体管的控制极连接同一条所述第二开关控制信号线，连接不同的所述像素 岛的所述第二开关晶体管的控制极连接不同的所述第二开关控制信号线；连接各所述像素岛中相同位置的子像素列的所述第二开关晶体管的第二极相互连接；
一个所述第二多路复用单元中，各所述第三开关晶体管与所述第二多路复用单元所连接的其中一个所述像素岛对应；该像素岛对应第三开关晶体管和第二开关晶体管中，各所述第三开关晶体管的第一极分别连接各所述第二开关晶体管的第二极；
一个所述第二多路复用单元中，所述第三开关晶体管沿所述第一方向分为多个第三开关晶体管组，所述第三开关晶体管组的数量与一个所述像素岛中包括的子像素组的数量相等；
一个所述第三开关晶体管组中，各所述第三开关晶体管的控制极分别连接不同的所述第三开关控制信号线，各所述第三开关晶体管的第二极连接所述第二多路复用单元的同一个输入端。
本公开一些实施例中，还包括：
多条栅线，沿所述第一方向延伸且沿所述第二方向排列；沿所述第一方向排列成同一行的子像素连接同一条所述栅线；
栅极驱动电路，沿所述第一方向位于所述像素岛所在区域的一侧或两侧；所述栅线分别连接所述栅极驱动电路；
所述栅极驱动电路包括多个沿所述第二方向排列的栅极驱动单元，各所述栅极驱动单元沿所述第二方向相互级联，各所述栅极驱动单元单独扫描对应的子像素行。
本公开一些实施例中，还包括：
摄像头，被配置为对用户的眼睛进行拍摄，以使所述控制器根据所述摄像头拍摄的图像确定用户在所述显示装置的注视区域，控制所述驱动芯片驱动所述注视区域和非注视区域以不同分辨率进行图像显示。
本公开一些实施例中，所述微透镜层包括至少一个液晶透镜层。
本公开一些实施例中，所述像素岛包括十六个红色子像素、十六个绿色 子像素和十六个蓝色子像素，所述红色子像素、所述绿色子像素和所述蓝色子像素沿所述第一方向排列成三行，沿所述第二方向排列成十六列；一个所述像素岛经过所述微透镜层的映射形成排列为四行四列的十六个像素；
一个所述像素岛中的子像素沿所述第一方向分为四个子像素组，每个所述子像素组包括四个子像素列；
所述多路复用电路包括四条第一开关控制信号线，一个所述第一多路复用单元包括四个第一开关晶体管；四个所述第一开关晶体管的控制极分别连接四条所述第一开关控制信号线，四个所述第一开关晶体管的第一极分别连接一个所述子像素组中的四个子像素列对应的数据线；四个所述第一开关晶体管的第二极相互连接，连接至所述驱动芯片。
本公开一些实施例中，一个第一多路复用单元通过一个所述控制单元连接至所述驱动芯片；
所述多路复用电路包括一条控制信号线，一个所述控制单元包括一个控制开关晶体管；各所述控制开关晶体管的控制极均连接所述控制信号线，一个所述控制单元中的所述控制开关晶体管的第一极连接一个所述第一多路复用单元中的四个所述第一开关晶体管的第二极，所述控制开关晶体管的第二极连接所述驱动芯片。
本公开一些实施例中，所述多路复用电路包括两条第二开关控制信号线和四条第三开关控制信号线；
一个所述第二多路复用单元对应连接沿所述第一方向排列的两个所述像素岛，两个所述像素岛为第一像素岛和第二像素岛；
一个所述第二多路复用单元包括三十二个第二开关晶体管；一个所述第二多路复用单元中的十六个所述第二开关晶体管对应连接所述第一像素岛的数据线，另外十六个所述第二开关晶体管对应连接所述第二像素岛的数据线；
对应于所述第一像素岛的十六个所述第二开关晶体管的控制极均连接其中一条所述第二开关控制信号线，对应于所述第二像素岛的十六个所述第二开关晶体管的控制极均连接另一条所述第二开关控制信号线；对应于所述第 一像素岛的各所述第二开关晶体管的第一极分别连接所述第一像素岛的各数据线，对应于所述第二像素岛的各所述第二开关晶体管的第一极分别连接所述第二像素岛的各数据线；所述第一像素岛和所述第二像素岛中位于相同位置的子像素列所对应的两个所述第二开关晶体管的第二极相互连接；
一个所述第二多路复用单元包括十六个第三开关晶体管；十六个所述第三开关晶体管对应于所述第一像素岛；十六个所述第三开关晶体管沿所述第一方向分为四个第三开关晶体管组；
一个所述第三开关晶体管组中的四个所述第三开关晶体管的控制极分别连接四条所述第三开关控制信号线，对应于同一个子像素列的所述第二开关晶体管的第二极连接所述第三开关晶体管的第一极，四个所述第三开关晶体管的第二极相互连接，连接至所述驱动芯片。
本公开实施例还提供一种基于上述任一显示装置的驱动方法，包括：
实时确定用户在所述显示装置的注视区域和非注视区域；
驱动所述注视区域以第一分辨率进行图像显示，驱动所述非注视区域以第二分辨率进行图像显示；所述第一分辨率高于所述第二分辨率。
本公开一些实施例中，所述显示装置包括摄像头；
所述实时确定用户在所述显示装置的注视区域和非注视区域，包括：
控制所述摄像头实时对用户的眼睛进行拍摄；
根据所述摄像头拍摄的图像确定用户在所述显示装置的注视区域；
将所述显示装置中除所述注视区域以外的其它区域确定为非注视区域。
本公开一些实施例中，所述根据所述摄像头拍摄的图像确定用户在所述显示装置的注视区域，包括：
根据所述摄像头拍摄的图像分别确定用户的左眼和右眼相对于所述显示装置的显示面的位置；
根据用户的左眼和右眼相对于所述显示装置的显示面的位置，以及用户与所述显示装置之间的距离，分别确定出用户的左眼在所述显示装置的左眼注视区域和用户的右眼在所述显示装置的右眼注视区域；
将所述左眼注视区域和所述右眼注视区域的交叠区域作为所述用户在所述显示装置的注视区域。
本公开一些实施例中，采用以下公式确定用户的单个眼睛在所述显示装置的注视区域：
S＝π(A tan15°) 2；
其中，S表示用户的单个眼睛在所述显示装置的注视区域，A表示用户与所述显示装置之间的距离。
本公开一些实施例中，在所述驱动所述注视区域以第一分辨率进行图像显示，驱动所述非注视区域以第二分辨率进行图像显示之前，还包括：
确定用户选择的显示模式；
所述驱动所述注视区域以第一分辨率进行图像显示，驱动所述非注视区域以第二分辨率进行图像显示，包括：
在用户选择的显示模式为二维显示模式时，驱动所述注视区域以第一分辨率进行二维图像显示，驱动所述非注视区域以第二分辨率进行二维图像显示；
在用户选择的显示模式为三维显示模式时，驱动所述注视区域以第一分辨率进行三维图像显示，驱动所述非注视区域以第二分辨率进行二维图像显示；或者，在用户选择的显示模式为三维显示模式时，驱动所述注视区域以第一分辨率进行三维图像显示，驱动所述非注视区域以第二分辨率进行三维图像显示。
本公开一些实施例中，在用户选择的显示模式为二维显示时，所述驱动所述注视区域以第一分辨率进行二维图像显示，驱动所述非注视区域以第二分辨率进行二维图像显示，包括：
接收二维图像数据，针对所述注视区域对所述二维图像数据进行第一分辨率的图像渲染，针对所述非注视区域对所述二维图像数据进行第二分辨率的图像渲染；
控制所述注视区域对应的各所述第一开关控制信号线依次输出有效电平 信号，以使所述第一多路复用单元中的各第一开关晶体管依次打开传输不同的二维图像数据，控制所述非注视区域对应的各所述第一开关控制信号线同时输出有效电平信号，以使所述第一多路复用单元中的各第一开关晶体管同时打开传输相同的二维图像数据，以实现驱动所述注视区域以所述第一分辨率进行二维图像显示，驱动所述非注视区域以第二分辨率进行二维图像显示。
本公开一些实施例中，在用户选择的显示模式为三维显示时，所述驱动所述注视区域以第一分辨率进行三维图像显示，驱动所述非注视区域以第二分辨率进行三维图像显示，包括：
接收三维图像数据，针对所述注视区域对所述三维图像数据进行第一分辨率的图像渲染，针对所述非注视区域对所述三维图像数据进行第二分辨率的图像渲染；
控制所述注视区域对应的各所述第一开关控制信号线依次输出有效电平信号，以使所述第一多路复用单元中的各第一开关晶体管依次打开传输不同的三维图像数据，控制所述非注视区域对应的各所述第一开关控制信号线同时输出有效电平信号，以使所述第一多路复用单元中的各第一开关晶体管同时打开传输相同的三维图像数据，以实现驱动所述注视区域以第一分辨率进行三维图像显示，驱动所述非注视区域以第二分辨率进行三维图像显示。
本公开一些实施例中，在用户选择的显示模式为三维显示时，所述驱动所述注视区域以第一分辨率进行三维图像显示，驱动所述非注视区域以第二分辨率进行二维图像显示，包括：
接收三维图像数据，将所述非注视区域对应的三维图像数据转化为二维图像数据；
针对所述注视区域对所述三维图像数据进行第一分辨率的图像渲染，针对所述非注视区域对所述二维图像数据进行第二分辨率的图像渲染；
控制所述注视区域对应的各所述第一开关控制信号线依次输出有效电平信号，以使所述第一多路复用单元中的各第一开关晶体管依次打开传输不同的三维图像数据，控制所述非注视区域对应的各所述第一开关控制信号线同 时输出有效电平信号，以使所述第一多路复用单元中的各第一开关晶体管同时打开传输相同的二维图像数据，以实现驱动所述注视区域以第一分辨率进行三维图像显示，驱动所述非注视区域以第二分辨率进行二维图像显示。
本公开一些实施例中，所述注视区域对应的栅极驱动单元的扫描时长大于所述非注视区域对应的栅极驱动单元的扫描时长。
本公开一些实施例中，所述驱动方法还包括：
提高所述驱动芯片对所述非注视区域的驱动电流，以使所述注视区域和所述非注视区域内的子像素的充电程度的差值小于设定阈值。
本公开一些实施例中，所述显示装置的栅极驱动电路包括多个栅极驱动单元，所述显示装置的多路复用电路还包括多个第二多路复用单元和多个控制单元；所述驱动方法包括：
驱动各所述控制单元的控制开关晶体管保持关闭；
在驱动相邻的多个像素岛加载相同的图像数据时，控制第n行子像素连接的栅极驱动单元和第n+3行子像素连接的栅极驱动单元的输出信号相同；n为大于或等于1的整数；控制各第二开关控制信号线同时输出有效电平信号，以使所述第二多路复用单元中的各第二开关晶体管同时打开，实现相邻的多个像素岛加载的图像数据相同；
在驱动各像素岛加载不同的图像数据时，控制各第二开关控制信号线依次输出有效电平信号，以使所述第二多路复用单元中的连接不同像素岛的第二开关晶体管依次打开，实现各像素岛加载的图像数据不同；
其中，针对同一个像素岛的驱动方法包括：
控制各第三开关控制信号线同时输出有效电平信号，以使所述第二多路复用单元中的各第三开关晶体管同时打开传输相同的图像数据；
或者，控制各第三开关控制信号线依次输出有效电平信号，以使所述第二多路复用单元中的各第三开关晶体管依次打开传输不同的图像数据。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对本公开实施例中所需要使用的附图作简单地介绍，显而易见地，下面所介绍的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的显示装置的结构示意图之一；
图2为本公开实施例提供的显示装置的截面结构示意图；
图3a为本公开实施例提供的像素岛的子像素排列结构示意图；
图3b为本公开实施例提供的像素岛映射后的像素排列结构示意图；
图4为本公开实施例提供的显示装置的局部放大图之一；
图5为本公开实施例提供的显示装置的局部放大图之二；
图6为本公开实施例提供的第二多路复用单元的局部放大图；
图7为本公开实施例提供的显示装置的局部放大图之三；
图8为本公开实施例提供的显示装置的驱动方法的流程图；
图9a为本公开实施例提供的人眼产生注视区域的原理图之一；
图9b为本公开实施例提供的人眼产生注视区域的原理图之二；
图10为本公开实施例提供的显示装置的显示分区示意图；
图11为图10所示显示装置的显示效果示意图；
图12a为本公开实施例提供的注视区域对应的驱动时序图之一；
图12b为本公开实施例提供的非注视区域对应的驱动时序图之一；
图13a为本公开实施例提供的注视区域对应的驱动时序图之二；
图13b为本公开实施例提供的非注视区域对应的驱动时序图之二；
图14为本公开实施例提供的注视区域和非注视区域的充电电压对比图；
图15a为本公开实施例提供的注视区域对应的驱动时序图之三；
图15b为本公开实施例提供的非注视区域对应的驱动时序图之三；
图16为本公开实施例提供的显示装置的系统架构示意图。
具体实施方式
为使本公开的上述目的、特征和优点能够更为明显易懂，下面将结合附图和实施例对本公开做进一步说明。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开更全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。在图中相同的附图标记表示相同或类似的结构，因而将省略对它们的重复描述。本公开中所描述的表达位置与方向的词，均是以附图为例进行的说明，但根据需要也可以做出改变，所做改变均包含在本公开保护范围内。本公开的附图仅用于示意相对位置关系不代表真实比例。
人眼在观察现实世界的时候，依靠双目视差产生立体视觉。依据该原理设计的3D显示装置通常需要配合眼镜等设备，将入射给左眼和右眼的光线分开，从而达到三维显示的效果。上述方式实现的三维立体显示通常将人眼长期聚焦在同一位置，这会造成视觉疲劳，进而使用户产生眩晕等不良体验。
基于光场技术的三维显示可以克服以上问题，实现裸眼3D显示。光场显示是在显示面板的出光侧设置微透镜阵列，显示面板的出射光经过微透镜阵列的调制形成多个视点入射到人眼，人眼观看到的图像来自于不同视点，因此观看到的图像来源于不同方向，与人眼观看真实景物的情形类似，克服视觉疲劳的问题。
图1为本公开实施例提供的显示装置的结构示意图之一，图2为本公开实施例提供的显示装置的截面结构示意图。
如图1和图2所示，本公开实施例提供的显示装置，包括：
衬底基板10，衬底基板10一般位于显示装置的底部，具有支撑以及承载其它部件的作用。衬底基板10的尺寸通常与显示装置的尺寸基本相同，形状通常情况下设置为矩形。当显示装置为异形显示装置时，衬底基板的形状和尺寸与显示装置相适应。衬底基板的材料通常情况下采用玻璃，在此不做限定。
多个像素岛20，位于衬底基板10上；像素岛20包括多个不同颜色的子 像素p，所有子像素p沿第一方向x和第二方向y呈阵列排布，一个像素岛20中颜色相同的子像素p沿第一方向x排列成一行，不同颜色的子像素p行沿第二方向y排列，第一方向x和第二方向y交叉。
在具体实施时，每个像素岛20的结构可以一致，各像素岛20沿第一方向x和第二方向y呈阵列排布。
图3a为本公开实施例提供的像素岛的子像素排列结构示意图。
如图3a所示，一个像素岛20中可以包括三基色的子像素，例如，像素岛20包括红色子像素pr、绿色子像素pg和蓝色子像素pb。其中，红色子像素pr、绿色子像素pg和蓝色子像素pb的数量相同；红色子像素pr沿第一方向x排列成一行，绿色子像素pg沿第一方向x排列成一行，蓝色子像素pb沿第一方向x排列成一行；红色子像素行、绿色子像素行和蓝色子像素行沿第二方向y排列，从而使像素岛20中的子像素呈阵列排布。上述的第一方向x和第二方向y可以为相互垂直的两个方向，其中第一方向x可以为水平方向，第二方向y可以为竖直方向，在此不做限定。
如图2所示，本公开实施例提供的显示装置还包括：微透镜层30。微透镜层60位于像素岛20背离衬底基板10的一侧。微透镜层30由微透镜阵列构成，微透镜层30可以对像素岛30的出射光线进行调制，从而使像素岛20映射为进行图像显示的像素阵列。采用像素岛20配合微透镜层30的结构，可以在达到子像素物理排列极限的基础上提高成像的分辨率。
图3b为本公开实施例提供的像素岛映射后的像素排列结构示意图。
当采用图3a所示结构的像素岛，在配合微透镜层30进行像素映射之后，可以形成如图3b所示的像素排列结构，由图3b中可以看出，映射后的红色子像素pr、绿色子像素pg和蓝色子像素pb按照固定顺序进行排列，且相邻的一个红色子像素pr、一个绿色子像素pg和一个蓝色子像素pb构成一个像素。映射后的像素与传统的像素排列结构相同，一个像素岛可以映射为多个像素构成的像素阵列，从而采用像素岛结构可以提高图像的显示分辨率。
微透镜层30不仅用于对像素岛中的子像素进行像素映射，还能够对像素 岛的出射光线进行调制，从而使最终的像素岛的显示数据形成多个视点，从而实现三维光场显示。
在具体实施时，微透镜层30可以采用至少一个液晶透镜。通过对液晶透镜施加电信号可以控制液晶分子产生设定的相位延迟，从而等效为透镜的作用。当然，上述微透镜层也可以直接采用具有设定形状的微透镜构成的微透镜阵列实现相同的功能，在此不做限定。如下以微型透镜层采用液晶透镜的情形对微透镜层的结构以及功能进行说明，采用实体微透镜的设置方式以及原理与液晶透镜类似，不进行具体赘述。
微透镜层30可以仅包括一个液晶透镜，该液晶透镜等效为半球形的微透镜构成的微透镜阵列，该液晶透镜同时起到像素映射和实现三维光场显示。像素岛中的子像素的出射光线在经过液晶透镜之后，可以映射为像素阵列，且形成多个视点，从而实现三维光场显示。
例如，当像素岛20采用图3a所示的结构时，微透镜层30可以采用(或等效)为16个半球形微透镜呈阵列排布于像素岛20的出光侧，从而可以使像素岛20映射为图3b所示的像素阵列，形成最多16个视点，实现光场三维显示。
在另一些实施例中，微透镜层30也可以采用两层液晶透镜，其中靠近像素岛一侧的液晶透镜可以起到像素映射的作用，远离像素岛一侧的另一个液晶透镜可以对出射光线进行调制，实现三维光场显示。两层透镜均可以采用半球形微透镜结构，微透镜的数量与像素岛中的子像素数量相匹配，在此不做限定。
在另一些实施例中，微透镜层30包括的两层液晶透镜中，其中一层液晶透镜用于等效为半球形的微透镜构成的微透镜阵列，而另一层液晶透镜用于等效为柱状透镜构成的微透镜阵列，两个液晶透镜不同时被控制，对光线的调制原理不同，采用半球形透镜的微透镜阵列可以实现三维光场显示，采用柱状透镜的微透镜以实现超多视点的三维显示。
例如，当像素岛20采用图3a所示的结构时，其中一层液晶透镜可以等 效为16个柱状透镜，分别对应不同的子像素列，从而使像素岛的出射光可以被映射为图3b所示的像素阵列，同时实现一部分光线向左眼的方向偏折，而另一部分光线向右眼的方向偏折，从而实现三维显示。另一层液晶透镜可以等效为16个半球形微透镜呈阵列排布于像素岛20的出光侧，从而可以使像素岛20映射为图3b所示的像素阵列，形成最多16个视点，实现光场三维显示。
本公开实施例不对像素岛中的子像素数量及其对应的液晶透镜的使用数量，以及如何控制液晶透镜以实现三维显示的操作手段进行限定。
如图1所示，在显示装置包括采用上述像素岛的像素排列结构的基础上，显示装置还包括：
多条数据线40，沿第一方向x排列且沿第二方向y延伸；沿第二方向y排列成同一列的子像素连接同一条数据线40。数据线40用于向子像素传输图像数据，子像素在显示出图像数据相应的亮度。
多路复用电路50，沿第二方向y位于所有像素岛20所在区域的一侧。各数据线40分别连接多路复用电路50。多路复用电路50应用于显示装置中，可以采用少量的驱动引脚分时驱动不同的数据线，由此减少驱动引脚的使用数量，节省资源。
驱动芯片60，沿第二方向y位于多路复用电路50背离像素岛20的一侧。多路复用电路50连接驱动芯片60。驱动芯片60具有多个连接引脚，多路复用电路50的输入端连接到驱动芯片60的引脚，多路复用电路50的输出端依次连接各数据线40，其中，输入端的数量少于输出端的数量。驱动芯片60的引脚输出的图像数据可以通过多路复用电路50向各数据线40进行传输，这样驱动芯片60的一个引脚可以控制多条数据线40。
控制器70，连接驱动芯片60，被配置为向驱动芯片60提供驱动信号。控制器70可以接收用于图像显示的二维图像数据或三维图像数据，控制器70根据用户选择的确定当前的显示模式为三维显示模式还是二维显示模式。再根据预先确定出的显示分区把相应的图像数据提供给驱动芯片60，驱动芯片 60根据控制器70的控制以设定的驱动电流向各数据线提供图像数据。
在具体实施时，可以将显示装置的中心区域作为高清显示区，除中心区域以外的其它区域作为辅助显示区；从而使得中心区域以高分辨率进行图像显示，辅助显示区以低分辨率进行图像显示，这样可以在不降低显示效果的同时节省功耗。
本公开实施例提供的显示装置还可以包括摄像头c，摄像头c被配置为对用户的眼睛进行拍摄，以使控制器70根据摄像头c拍摄的图像确定用户在显示装置的注视区域，控制驱动芯片60驱动注视区域以高分辨率进行图像显示，驱动非注视区域以低分辨率进行图像显示。
图4为本公开实施例提供的显示装置的局部放大图之一。
如图4所示，一个像素岛20中的子像素列沿第一方向x分为多个子像素组21，每个子像素组21中包括的子像素列的数量相等。
多路复用电路50包括多个沿第一方向x排列的第一多路复用单元51，第一多路复用单元51包括一个输入端51i和多个输出端51o；一个第一多路复用单元51对应连接一个子像素组21，第一多路复用单元51的输出端51o分别连接子像素组对应的数据线40，第一多路复用单元51的输入端51i连接驱动芯片60。
在本公开实施例中，一个子像素组21写入的图像数据通过一个第一多路复用单元51进行传输。当第一多路复用单元51的输出端51o依次打开时，输入端51i输入的图像数据可以依次地传输到子像素组21对应的不同的数据线40上，这样不同的数据线40可以向子像素传输不同的图像数据。当一个像素岛20内的各子像素写入不同的图像数据时，可以形成的视点数量最多，从而进行高分辨率的图像显示。而当第一多路复用单元51的输出端51o同时打开时，输入端51i输入的图像数据同时传输到子像素组21对应的不同的数据线40上，这样不同的数据线40可以向子像素传输相同的图像数据。当一个子像素组21内的同行子像素写入相同的图像数据时，相当于多个像素用于显示相同的图像数据，这样可以降低视点的数量，从而进行低分辨率的图像 显示。
根据上述驱动规则，可以控制显示装置被用户注视的注视区进行高分辨率的图像显示，控制非注视区进行低分辨的图像显示，从而可以降低非注视区的数据传输量，减少非注视区的像素充电时间，将节省下来的时间用于提高图像的刷新率，从而使得注视区具有较佳的显示效果，同时降低显示装置的功耗。
可选地，如图4所示，多路复用电路50还包括：多条第一开关控制信号线l1，第一开关控制信号线l1沿第一方向x延伸沿第二方向y排列。
第一多路复用单元51包括：多个第一开关晶体管T1，第一开关晶体管的控制极连接第一开关控制信号线l1，第一开关晶体管的第一极连接第一多路复用单元的输出端51o，第一开关晶体管的第二极连接第一多路复用单元的输入端51i。
如图4所示，一个第一多路复用单元51中包含的第一开关晶体管T1的数量与第一开关控制信号线l1的数量相等。一个第一多路复用单元51中，各第一开关晶体管T1的控制极分别连接不同的第一开关控制信号线l1，各第一开关晶体管T1的第一极分别连接第一多路复用单元的不同的输出端51o，各第一开关晶体管T1的第二极均连接至第一多路复用单元的输入端51i。
第一多路复用单元51中的各第一开关晶体管T1在各第一开关控制信号线l1的控制下打开或关闭。这样当各第一开关控制信号线l1依次输出有效电平信号，以使各第一开关晶体管T1依次打开时，输入端51i的信号依次通过各第一开关晶体管T1第二极向第一极传输，从而可以依次向各第一开关晶体管T1连接的不同的数据线传输不同的图像数据，使得多列子像素写入不同的图像数据进行高分辨率的图像显示。当各第一开关信号线l1同时输出有效电平信号时，可以控制各第一开关晶体管T1同时打开，那么输入端51i的信号通过各第一开关晶体管T1的第二极向第一极传输，从而可以通过各第一开关晶体管T1向多条数据线40同时输出，使得多列子像素可以同时写入相同的图像数据进行低分辨率的图像显示。
图5为本公开实施例提供的显示装置的局部放大图之二。
如图5所示，多路复用电路50还包括：多个控制单元c。控制单元c沿第二方向y位于第一多路复用单元51背离像素岛20的一侧，控制单元c沿第一方向x排列。控制单元c包括一个输入端ci和一个输出端co；一个控制单元c对应连接一个第一多路复用单元c，控制单元的输出端co连接第一多路复用单元51的输入端51i，控制单元c的输入端ci连接驱动芯片60。
由图5可以看出，第一多路复用单元51是通过控制单元c与驱动芯片60连接的，控制单元c用于控制是否启动第一多路复用单元51向数据线40传输图像数据，即控制单元c相当于第一多路复用单元51的开关，只有当控制单元c处于开启状态下，第一多路复用单元51才可以实现上述驱动；当控制单元c处于关闭状态，则无法控制第一多路复用单元51。
可选地，多路复用电路50还包括：沿第一方向x延伸的控制信号线lc。
控制单元c包括：控制开关晶体管Tc；控制开关晶体管Tc的控制极连接控制信号线lc，控制开关晶体管Tc的第一极连接控制单元的输出端co，控制开关晶体管Tc的第二极连接控制单元的输入端ci。
控制开关晶体管Tc在控制信号线lc的控制下打开或关闭。当控制信号线lc输出有效电平信号时，控制开关晶体管Tc打开，输入端ci的信号通过控制开关晶体管Tc的第二极向第一极传输，使得驱动芯片输出的图像数据可以通过控制开关晶体管Tc传输给第一多路复用单元51，再经过第一多路复用单元51传输给其连接的各数据线40。当控制信号线lc未输出有效电平信号时，控制开关晶体管Tc关闭，则驱动芯片输出的图像数据无法再通过控制开关晶体管Tc向第一多路复用单元51传输，此时第一多路复用单元51无效。
本公开实施例提供的上述显示装置可以进行三维光场显示，通过控制第一多路复用单元51中的第一开关晶体管T1可以实现视点数量的控制，从而控制显示装置的显示分辨率。
如图5所示，在本公开实施例提供的显示装置中，多路复用电路50还可以包括：多个第二多路复用单元52.第二多路复用单元52沿第二方向y位于 第一多路复用单元51背离像素岛20的一侧，第二多路复用单元52沿第一方向x排列。第二多路复用单元52包括多个输入端52i和多个输出端52o，输入端52i的数量小于输出端52o的数量；一个第二多路复用单元52对应连接沿第一方向x排列的多个像素岛20，第二多路复用单元52的输出端52o分别连接各像素岛中的各子像素列对应的数据线40，第二多路复用单元52的输入端52i分别连接驱动芯片60。
第二多路复用单元52同时连接多个像素岛20，通过这样的连接关系可以依次向各像素岛20传输不同的图像数据，或同时向多个像素岛20传输相同的图像数据，由此可以在控制像素岛产生的视点数量的同时控制像素岛20传输数据的分辨率，从而控制显示装置的图像分辨率。
可选地，如图5所示，多路复用电路50还包括：
多条第二开关控制信号线l2，第二开关控制信号线l2沿第一方向x延伸沿第二方向y排列；
多条第三开关控制信号线l3，第三开关控制信号线l3沿第一方向x延伸沿第二方向y排列。
由图5可以看出，第一开关控制信号线l1、第二开关控制信号线l2、第二开关控制信号线l3以及控制信号线lc的延伸方向相同，均可以沿第一方向x延伸沿第二方向y排列。
第二多路复用单元52包括：多个第二开关晶体管T2和多个第三开关晶体管T3。
其中，第二开关晶体管T2的控制极连接第二开关控制信号线l2，第二开关晶体管T2的第一极连接第二多路复用单元52的输出端52o，第二开关晶体管T2的第二极连接第三开关晶体管T3的第一极；第三开关晶体管T3的控制极连接第三开关控制信号线l3，第三开关晶体管T3的第二极连接第二多路复用单元52的输入端52i。
在本公开实施例中，一个第二多路复用单元52中包含的第二开关晶体管T2的数量与一个第二多路复用单元52连接的数据线40的数量相等。例如， 一个第二多路复用单元52连接两个像素岛20，每个像素岛20包括16列子像素，那么一个像素岛20连接16条数据线，两个像素岛20连接32条数据线，则第二多路复用单元52中包含32个第二开关晶体管T2。
一个第二多路复用单元52中包含的第三开关晶体管T3的数量与一个像素岛20包括的子像素列的数量相等。例如，一个像素岛20包括16列子像素，那么第二多路复用单元52中包含16个第三开关晶体管T3。
一个第二多路复用单元52中，连接同一个像素岛20的第二开关晶体管T2的控制极连接同一条第二开关控制信号线l2，连接不同的像素岛20的第二开关晶体管T2的控制极连接不同的第二开关控制信号线l2；连接各像素岛20中相同位置的子像素列的第二开关晶体管T2的第二极相互连接。
图6为本公开实施例提供的第二多路复用单元的局部放大图。
如图6所示，以一个第二多路复用单元同时控制两个像素岛为例，每个像素岛包括16列子像素，多路复用电路中包含两条第二开关控制信号线(l21和l22)；连接第一个像素岛201的16个第二开关晶体T21的控制极连接第一条第二开关控制信号线l21，连接第二个像素岛202的16个第二开关晶体管T22的控制极连接第二条第二开关控制信号线l22。连接第一个像素岛201的第一列子像素的第二开关晶体管T21的第二极与连接第二个像素岛202的第一列子像素的第二开关晶体管T22的第二极连接在一起；连接第一个像素岛201的第二列子像素的第二开关晶体管T21的第二极与连接第二个像素岛202的第二列子像素的第二开关晶体管T22的第二极连接在一起；以此类推，使得连接第一个像素岛的各第二开关晶体管的第二极分别与连接第二个像素岛相同位置的各第二开关晶体管的第二极相互连接。
当两条第二开关控制信号线依次传输有效电平信号时，可以分别向第一个像素岛201和第二个像素岛202传输图像数据。具体地，当第一条第二开关控制信号线l21传输有效电平信号，而第二条第二开关控制信号线l22无信号时，连接第一个像素岛201的各第二开关晶体管T21打开，连接第二个像素岛202的各第二开关晶体管T22关闭。那么驱动芯片60输出的图像数据可 以通过连接第一个像素岛201的各第二开关晶体管T21向第一像素岛201的各数据线进行传输。当第一条第二开关控制信号线l21无信号，而第二条第二开关控制信号线l22传输有效电平信号时，连接第一个像素岛201的各第二开关晶体管T21关闭，连接第二个像素岛202的各第二开关晶体管T22打开。那么驱动芯片60输出的图像数据可以通过连接第二个像素岛202的各第二开关晶体管T22向第二像素岛202的各数据线进行传输。由此实现第一像素岛201和第二像素岛202分别写入不同的图像数据。
当两条第二开关控制信号线同时传输有效电平信号时，可以同时别向第一个像素岛201和第二个像素岛202传输相同图像数据。具体地，当第一条第二开关控制信号线l21和第二条第二开关控制信号线l22同时传输有效电平信号时，连接第一个像素岛201的各第二开关晶体管T21和连接第二个像素岛202的各第二开关晶体管T22同时打开。那么驱动芯片60输出的图像数据可以通过连接第一个像素岛201的各第二开关晶体管T21向第一像素岛201的各数据线进行传输，同时通过连接第二像素岛202的各第二开关晶体管T22向第二个像素岛202的各数据线进行传输。此时，第一个像素岛201和第二像素岛202写入的图像数据相同，在进行图像显示时，相当于增大了进行图像显示的像素的尺寸，降低了图像分辨率。
如图5所示，一个第二多路复用单元52中，各第三开关晶体管T3与第二多路复用单元52所连接的其中一个像素岛20对应；该像素岛20对应第三开关晶体管T2和第二开关晶体管T3中，各第三开关晶体管T3的第一极分别连接各第二开关晶体管T2的第二极。
由于对应不同像素岛相同位置的子像素列的多个第二开关晶体管T2的第二极连接在一起，因此只需要对一个像素岛对应的第二开关晶体管T2的第二极传输图像数据，配合第二开关控制信号线传输有效电平信号，就可以达到对多个像素岛进行数据写入的目的，由此可以节省驱动引脚。
在本公开实施例中，第三开关晶体管T3的数量与一个像素岛20包括的子像素列的数量相等。例如，一个第二多路复用单元52连接两个像素岛，第 一个像素岛包括16列子像素，那么需要采用32个第二开关晶体管T2，采用16个第三开关晶体管。16个第三开关晶体管T3的第一极分别与连接一个像素岛的16个第二开关晶体管T2的第二极连接。这样可以通过第三开关晶体管T3向第二开关晶体管T2传输图像数据。
如图5所示，一个第二多路复用单元52中，第三开关晶体管T3沿第一方向x分为多个第三开关晶体管组T3s，第三开关晶体管组T3s的数量与一个像素岛20中包括的子像素组21的数量相等；一个第三开关晶体管组T3s中，各第三开关晶体管T3的控制极分别连接不同的第三开关控制信号线l3，各第三开关晶体管T3的第二极连接第二多路复用单元52的同一个输入端52i。
在本公开实施例中，一个子像素组21写入的图像数据通过一个第三开关晶体管组T3s进行控制传输，因此一个第二多路复用单元52包含的第三开关晶体管组T3s的数量与一个像素岛20包含的子像素且21的数量相等。除此之外，每个第三开关晶体管T3s中包含的第三开关晶体管T3的数量与多路复用电路50包含的第三开关控制信号线l3的数量相同。
各第三开关晶体管T31在各第三开关控制信号线l3的控制下打开或关闭。这样当各第三开关控制信号线l3依次输出有效电平信号，以使各第三开关晶体管T3依次打开时，输入端52i的信号依次通过各第三开关晶体管T31第二极向第一极传输，从而可以依次向其连接的各第二开关晶体管T2传输不同的图像数据。进一步地，在第二开关控制信号线l2的控制下控制图像数据同时或依次传输给不同的像素岛。当各第三开关信号线l3同时输出有效电平信号时，可以控制各第三开关晶体管T3同时打开，那么输入端52i的信号通过各第三开关晶体管T3的第二极向第一极传输，从而可以同时向其连接的各第二开关晶体管T2传输相同的图像数据。进一步地，在第二开关控制信号线l2的控制下控制图像数据同时或依次传输给不同的像素岛。
如图6所示，本公开实施例提供的显示装置，还包括：栅极驱动电路80和栅线800。其中：
多条栅线800，沿第一方向x延伸且沿第二方向y排列；沿第一方向c排 列成同一行的子像素连接同一条栅线800；
栅极驱动电路80，沿第一方向x位于像素岛20所在区域的一侧或两侧；栅线800分别连接栅极驱动电路80。栅极驱动电路80包括多个沿第二方向y排列的栅极驱动单元81，各栅极驱动单元81沿第二方向y相互级联，各栅极驱动单元81单独扫描对应的子像素行。
驱动芯片60中的图像数据需要配合栅极驱动电路80输出的扫描信号写入到像素岛20中，当栅极驱动电路80向栅极传输扫描信号时，该行子像素在栅极800传输有效电平信号时才能将图像数据通过数据线40写入到该行的各子像素中。在本公开实施例中，通过控制相邻多行子像素岛的扫描信号相同，可以实现同时控制多行多列子像素岛的图像数据，从而可以更大程度地分辨率调节。
需要说明的是，本公开实施例提供的上述显示装置可以采用第一多路复用单元51进行驱动，也可以采用第二多路复用单元52进行驱动。当采用第一多路复用51单元进行驱动时，各控制单元c保持打开状态，第二多路复用单元52均无信号传输，此时可以控制显示装置进行视点数量的切换，从而达到调整显示分辨率的目的；当采用第二多路复用单元52进行驱动时，各控制单元c保持关闭状态，第一多路复用单元51均无信号传输，此时可以控制显示装置同时进行视点数量以及像素岛分辨率的切换，从而达到调整显示分辨率的目的。
本公开实施例以一个具体实例对电路连接关系进行说明。
图7为本公开实施例提供的显示装置的局部放大图之三。
图7示出了相邻的四个像素岛的电路连接关系，在显示装置中包括多个图7所示的单元。具体来说，显示装置包括多个像素岛，每个像素岛包括十六个红色子像素r、十六个绿色子像素g和十六个蓝色子像素b，红色子像素r、绿色子像素g和蓝色子像素b沿第一方向x排列成三行，沿第二方向y排列成十六列。一个像素岛经过微透镜层的映射形成排列为四行四列的十六个像素。
一个像素岛中的子像素沿第一方向x分为四个子像素组21，每个子像素组21包括四个子像素列。
多路复用电路50包括多个第一多路复用单元51，一个像素岛对应四个第一多路复用单元51。
多路复用电路50包括四条第一开关控制信号线l1，一个第一多路复用单元51包括四个第一开关晶体管T1；四个第一开关晶体管T1的控制极一一对应连接四条第一开关控制信号线l1，四个第一开关晶体管的第一极一一对应连接一个子像素组21中的四个子像素列对应的数据线40；四个第一开关晶体管T1的第二极相互连接。
多路复用电路50包括控制单元c，一个像素岛对应四个控制单元c。一个第一多路复用单元51通过一个控制单元c连接至驱动芯片60。
多路复用电路50包括一条控制信号线lc，一个控制单元c包括一个控制开关晶体管Tc；各控制开关晶体管Tc的控制极均连接控制信号线lc，一个控制单元c中的控制开关晶体管Tc的第一极连接一个第一多路复用单元51中的四个第一开关晶体管T1的第二极，控制开关晶体管Tc的第二极连接驱动芯片60。
多路复用电路50包括多个第二多路复用单元，一个第二多路复用单元52对应连接沿第一方向x排列的两个像素岛，两个像素岛区分为第一像素岛201和第二像素岛202。
多路复用电路50包括两条第二开关控制信号线l2和四条第三开关控制信号线l3。一个第二多路复用单元52包括32个第二开关晶体管T2，第一像素岛201的数据线对应连接16个第二开关晶体管T2，第二像素岛202的数量线对应连接16个第二开关晶体管T2。对应于第一像素岛201的16六个第二开关晶体管T2的控制极均连接其中一条第二开关控制信号线l2，对应于第二像素岛202的16六个第二开关晶体T2的控制极均连接另一条第二开关控制信号线l2。对应于第一像素岛201的各第二开关晶体管T2的第一极一一对应连接第一像素岛201的各数据线，对应于第二像素岛202的各第二开关晶体管 T2的第一极一一对应连接第二像素岛202的各数据线。第一像素岛201的第一列子像素连接的第二开关晶体管T2的第二极与第二像素岛202的第一列子像素连接的第二开关晶体管T2的第二极相互连接，第一像素岛201的第二列子像素连接的第二开关晶体管T2的第二极与第二像素岛202的第二列子像素连接的第二开关晶体管T2的第二极相互连接，以此类推，第一像素岛201的第十六列子像素连接的第二开关晶体管T2的第二极与第二像素岛202的第十六列子像素连接的第二开关晶体管T2的第二极相互连接。
一个第二多路复用单元52包括16个第三开关晶体管T3，16个第三开关晶体管T3对应于第一像素岛201，16个第三开关晶体管T3沿第一方向x分为四个第三开关晶体管组。
一个第三开关晶体管组T3s中的4个第三开关晶体管T3的控制极一一对应连接四条第三开关控制信号线l2，对应于同一个子像素列的第二开关晶体管T2的第二极连接第三开关晶体管T3的第一极，4个第三开关晶体管T3的第二极相互连接，连接至驱动芯片60。
如图7所示，显示装置还包括沿第一方向x位于像素岛一侧的栅极驱动电路，栅极驱动电路包括多个相互级联的栅极驱动单元(811-816)，栅极驱动单元分别通过一条栅极与一行子像素连接。当栅极驱动单元(811-816)向对应的各栅极输出扫描信号时，通常情况下各行子像素对应的栅极中依次传输有效电平信号。第一行子像素在栅线传输有效电平信号的时段可以将对应的数据线上的图像数据写入到子像素中；在第一行子像素写入图像数据结束之后，第二行子像素在栅线传输有效电平信号的时段将对应的数据线上的图像数据写入到子像素中；以此类推，在所有的子像素均写入图像数据之后可以实现一帧图像显示。
在本公开实施例提供的上述显示装置中，当采用第一多路复用单元51进行驱动时，控制开关晶体管Tc保持打开状态，第二多路复用单元52无信号传输。此时可以通过控制第一多路复用单元51中的4个第一开关晶体管T1依次打开，以使对应的4列子像素依次写入图像数据，此时一个像素岛产生 多个视点，进行高分辨率图像显示；或者可以通过控制4个第一开关晶体管T1同时打开，以使对应的4列子像素同时写入相同的图像数据，此时可以减少一个像素岛产生的视点数量，进行低分辨率图像显示。
当采用第二多路复用单元52进行驱动时，控制开关晶体管Tc保持关闭状态，第一多路复用单元51无信号传输。此时可以通过控制对应第一像素岛201的16个第二开关晶体管T2先打开，向第一像素岛201写入图像数据，再控制对应第二像素岛202的16个第二开关晶体管T2打开，向第二像素岛202写入图像数据，保持不同的像素岛写入的图像数据不同，进行高分辨率图像显示；或者可以通过控制对应第一像素岛201和第二像素岛202的32个第二开关晶体管T2同时打开，向第一像素岛201和第二像素岛202写入相同的图像数据，在保持像素岛产生视点数量不变的情况下降低图像分辨率，进行低分辨率图像显示。与此同时，还可以控制栅极驱动单元801和804传输相同的扫描信号，栅极驱动单元802和805传输相同的扫描信号，栅极驱动单元803和806传输相同的扫描信号，以使第一像素岛201、第二像素岛202、第三像素岛203和第四像素岛204写入相同的图像数据，进一步降低图像分辨率。
在控制第一像素岛201和第二像素岛202对应的第二开关晶体管T2依次打开或同时打开时，还可以控制一个第三开关晶体管组T3s中的4个第三开关晶体管T3依次打开，以使对应的4列子像素依次写入图像数据，此时一个像素岛产生多个视点；或者可以通过控制4个第三开关晶体管T3同时打开，以使对应的4列子像素同时写入相同的图像数据，此时可以减少像素岛产生的视点数量示。
本公开实施例提供的上述显示装置可以进行上述图像分辨率的调整，以在被用户注视的显示区域实现高分辨的图像显示，在其它显示区域实现低分辨率的图像显示，由此在保证用户体验的前提下降低功耗，达到资源的合理分配。
基于上述显示装置结构，本公开实施例还提供一种显示装置的驱动方法， 图8为本公开实施例提供的显示装置的驱动方法的流程图。
如图8所示，本公开实施例提供的显示装置的驱动方法包括：
S10、实时确定用户在显示装置的注视区域和非注视区域；
S20、驱动注视区域以第一分辨率进行图像显示，驱动非注视区域以第二分辨率进行图像显示。
其中，第一分辨率高于第二分辨率。
本公开实施例通过设定手段确定出显示装置所显示图像的注视区域和非注视区域，驱动注视区域以高分辨率进行图像显示，驱动非注视区以低分辨率进行图像显示，从而保证被关注的注视区域的图像显示质量，降低非注视区的图像分辨率，从而降低整体功耗，避免资源浪费。
在上述步骤S10中，实时确定用户在显示装置的注视区域和非注视区域，包括：
控制摄像头实时对用户的眼睛进行拍摄；
根据摄像头拍摄的图像确定用户在显示装置的注视区域；
将显示装置中除注视区域以外的其它区域确定为非注视区域。
在具体实施时，显示装置的显示图像通常较大，人眼只会注视显示图像的局部区域，因此本公开实施例通过在显示装置上设置摄像头，或外接摄像头实时地跟踪人眼在显示装置的注视区域，从而实时地驱动注视区域以高分辨率进行图像显示，驱动非注视区域以低分辨率进行图像显示，避免资源浪费。
具体地，根据摄像头拍摄的图像确定用户在显示装置的注视区域，包括：
根据摄像头拍摄的图像分别确定用户的左眼和右眼相对于显示装置的显示面的位置；
根据用户的左眼和右眼相对于显示装置的显示面的位置，以及用户与显示装置之间的距离，分别确定出用户的左眼在显示装置的左眼注视区域和用户的右眼在显示装置的右眼注视区域；
将左眼注视区域和右眼注视区域的交叠区域作为用户在显示装置的注视 区域。
其中，用户的单个眼睛在显示装置的注视区域可以采用以下公式确定：
S＝π(A tan15 °) 2；
S表示用户的单个眼睛在显示装置的注视区域，A表示用户与显示装置之间的距离。
图9a为本公开实施例提供的人眼产生注视区域的原理图之一，图9b为本公开实施例提供的人眼产生注视区域的原理图之二。
如图9a和图9b所示，人眼观看显示装置时通常会具有一极限视角，即人眼在相对于显示装置的显示面的位置固定时，在注视显示装置时只能观看到视角范围之内的内容。通常情况下单眼产生的视角约为30度，如图9a所示，当用户的双眼到显示装置的距离为A1时，左眼在显示装置上产生左眼注视区域为sl1，右眼在显示装置产生的右眼注视区域为sr1，左眼注视区域和右眼注视区域的交叠区域sx1确定为用户双眼在显示装置的注视区域。如图9b所示，当用户的双眼到显示装置的距离为A2时，左眼在显示装置上产生左眼注视区域为sl2，右眼在显示装置产生的右眼注视区域为sr2，左眼注视区域和右眼注视区域的交叠区域sx2确定为用户双眼在显示装置的注视区域。对比图9a和图9b，当用户到显示装置的距离由A1减小到A2时，按照单眼的视角为30度来计算，在显示装置产生的注视区域从sx1缩小为sx2。由此可见，用户双眼在显示装置产生的注视区域取决于视角以及用户到显示装置的距离，在视角固定的前提下，用户距离显示装置越远，产生的注视区域越大。
在确定出用户在显示装置的注视区域之后，可以驱动注视区域进行高清显示，而其它非注视区域进行低清显示，从而节省资源。
图10为本公开实施例提供的显示装置的显示分区示意图，图11为图10所示显示装置的显示效果示意图。
如图10所示，可以将显示区域沿着栅极驱动电路的延伸方向划分为多个区域，以图10所示的结构，本公开实施例可以将显示区域划分为16个分区，16个分区分别采用16个栅极驱动单元(GOA1-GOA16)独立驱动。如果通 过摄像头等设备确定出的用户在显示装置的注视区域为图10中黑色框所对应的区域，那么注视区域受栅极驱动单元GOA5-GOA9驱动。对注视区域和非注视区域内的各子像素写入图像数据之后，显示效果如图11所示，注视区域进行高清图像显示，非注视区域进行低清图像显示，由此节省资源和功耗。当用户的注视相对于显示装置的注视位置产生变化时，实时变更相应区域的驱动方式，实现高清图像和低清图像的动态调整。
在进行图像显示之前，还需要确定用户选择的显示模式，当用户选择二维显示模式时，显示装置输入的图像数据为二维图像数据，当用户选择三维显示模式时，显示装置输入的图像数据为三维图像数据。
因此，在上述步骤S20中，驱动注视区域以第一分辨率进行图像显示，驱动非注视区域以第二分辨率进行图像显示，具体包括：
在用户选择的显示模式为二维显示模式时，驱动注视区域以第一分辨率进行二维图像显示，驱动非注视区域以第二分辨率进行二维图像显示；
在用户选择的显示模式为三维显示模式时，驱动注视区域以第一分辨率进行三维图像显示，驱动非注视区域以第二分辨率进行二维图像显示；
或者，在用户选择的显示模式为三维显示模式时，驱动注视区域以第一分辨率进行三维图像显示，驱动非注视区域以第二分辨率进行三维图像显示。
当用户选择的显示模式为二维显示模式时，显示装置输入的图像数据为二维图像数据，用户希望观看的显示图像为二维图像，而用户在显示装置只会注视显示装置的部分区域，那么此时，针对注视区域以高分辨率进行二维图像显示，针对非注视区域以低分辨率进行二维图像显示，可以避免资源浪费。
当用户选择的显示模式为三维显示模式时，显示装置输入的图像数据为三维图像数据，用户希望观看的显示图像为三维图像，而用户在显示装置只会注视显示装置的部分区域，那么此时，针对注视区域以高分辨率进行三维图像显示，针对非注视区域可以低分辨率进行二维图像显示或三维图像显示，由此保证注视区域具有较好的显示效果，同时降低非注视区域的数据传输量 和充电时间，节省功耗。
具体来说，在用户选择的显示模式为二维显示时，驱动注视区域以第一分辨率进行二维图像显示，驱动非注视区域以第二分辨率进行二维图像显示，包括：
接收二维图像数据，针对注视区域对二维图像数据进行第一分辨率的图像渲染，针对非注视区域对二维图像数据进行第二分辨率的图像渲染；
控制注视区域对应的各第一开关控制信号线依次输出有效电平信号，以使第一多路复用单元中的各第一开关晶体管依次打开传输不同的二维图像数据，控制非注视区域对应的各第一开关控制信号线同时输出有效电平信号，以使第一多路复用单元中的各第一开关晶体管同时打开传输相同的二维图像数据，以实现驱动注视区域以第一分辨率进行二维图像显示，驱动非注视区域以第二分辨率进行二维图像显示。
在用户选择的显示模式为三维显示时，驱动注视区域以第一分辨率进行三维图像显示，驱动非注视区域以第二分辨率进行三维图像显示，包括：
接收三维图像数据，针对注视区域对三维图像数据进行第一分辨率的图像渲染，针对非注视区域对三维图像数据进行第二分辨率的图像渲染；
控制注视区域对应的各第一开关控制信号线依次输出有效电平信号，以使第一多路复用单元中的各第一开关晶体管依次打开传输不同的三维图像数据，控制非注视区对应的各第一开关控制信号线同时输出有效电平信号，以使第一多路复用单元中的各第一开关晶体管同时打开传输相同的三维图像数据，以实现驱动注视区域以第一分辨率进行三维图像显示，驱动非注视区域以第二分辨率进行三维图像显示。
在用户选择的显示模式为三维显示时，驱动注视区域以第一分辨率进行三维图像显示，驱动非注视区域以第二分辨率进行二维图像显示，包括：
接收三维图像数据，将非注视区域对应的三维图像数据转化为二维图像数据；
针对注视区域对三维图像数据进行第一分辨率的图像渲染，针对非注视 区域对二维图像数据进行第二分辨率的图像渲染；
控制注视区域对应的各第一开关控制信号线依次输出有效电平信号，以使第一多路复用单元中的各第一开关晶体管依次打开传输不同的三维图像数据，控制非注视区域对应的各第一开关控制信号线同时输出有效电平信号，以使第一多路复用单元中的各第一开关晶体管同时打开传输相同的二维图像数据，以实现驱动注视区域以第一分辨率进行三维图像显示，驱动非注视区域以第二分辨率进行二维图像显示。
本公开实施例可以采用第一多路复用单元驱动实现上述图像显示，具体的驱动电路可以采用4所示的结构。图12a为本公开实施例提供的注视区域对应的驱动时序图之一，图12b为本公开实施例提供的非注视区域对应的驱动时序图之一。
如图4所示，每个像素岛连接四个第一多路复用单元51，每个第一多路复用单元51包括四个第一开关晶体管T1，多路复用电路包括四条第一开关控制信号线l1，四条第一开关控制信号线输出的开关控制信号分别为图12a所示的SW1-SW4。各行子像素对应的栅极传输的扫描信号分别为图12a所示的G1、G2…，驱动芯片输出的图像数据为图12a所示的D。
如图12a所示，对于注视区域内的各第一多路复用单元51，使四条第一开关控制信号线l1依次输出有效电平信号(高电平信号)，从而使对应的四个第一开关晶体管T1依次打开用于向像素岛各列子像素输出不同的图像数据。
具体来说，当第一条栅线输出扫描信号G1为有效电平时段(高电平时段)时，其它栅线输出扫描信号为低电平。在第一条栅线输出有效电平时段期间，第一条第一开关控制信号线先输出高电平信号(SW1为高电平)，其它三条第一开关控制信号线均输出低电平信号(SW2-SW41为低电平)，此时只有连接第一条第一开关控制信号线的第一开关晶体管打开，驱动芯片输出的图像数据通过第一个第一开关晶体管传输给像素岛的第一列子像素；而后第二条第一开关控制信号线输出高电平信号(SW2为高电平)，其它三条第一开关控制信号线均输出低电平信号(SW1、SW3、SW4为低电平)，此时只有连接第二 条第一开关控制信号线的第一开关晶体管打开，驱动芯片输出的图像数据通过第二个第一开关晶体管传输给像素岛的第二列子像素；而后第三条第一开关控制信号线输出高电平信号(SW3为高电平)，其它三条第一开关控制信号线均输出低电平信号(SW1、SW2、SW4为低电平)，此时只有连接第三条第一开关控制信号线的第一开关晶体管打开，驱动芯片输出的图像数据通过第三个第一开关晶体管传输给像素岛的第三列子像素；而后第四条第一开关控制信号线输出高电平信号(SW4为高电平)，其它三条第一开关控制信号线均输出低电平信号(SW1-SW3为低电平)，此时只有连接第四条第一开关控制信号线的第一开关晶体管打开，驱动芯片输出的图像数据通过第四个第一开关晶体管传输给像素岛的第四列子像素。在完成上述图像数据的传输之后，第一条栅线输出扫描信号G1为有效电平时段结束，第二条栅线输出扫描信号G2变为有效电平(高电平)，各第一多路复用单元重复上述操作，以此类推，使注视区域内的各子像素依次写入图像数据，实现注视区域的高分辨率的图像显示。
如图12b所示，对于非注视区域内的各第一多路复用单元51，使四条第一开关控制信号线l1同时输出有效电平信号(高电平信号)，从而使对应的四个第一开关晶体管T1同时打开用于向像素岛各列子像素输出相同的图像数据。
具体来说，当第一条栅线输出扫描信号G1为有效电平时段(高电平时段)时，其它栅线输出扫描信号为低电平。在第一条栅线输出有效电平时段期间，四条第一开关控制信号线同时输出高电平信号(SW1-SW4为高电平)，此时连接四条第一开关控制信号线的四个第一开关晶体管同时打开，驱动芯片输出的图像数据通过四个第一开关晶体管同时传输给像素岛的四列子像素。在完成上述图像数据的传输之后，第一条栅线输出扫描信号G1为有效电平时段结束，第二条栅线输出扫描信号G2变为有效电平(高电平)，各第一多路复用单元重复上述操作，以此类推，使非注视区域内的每四列子像素同时写入相同的图像数据，从而使图像分辨率降低4倍，实现非注视区域的低分辨率的图像显示。
当用户选择的显示模式为二维显示模式时，驱动芯片通过各第一多路复用单元传输的图像数据为二维图像数据，注视区域和非注视区域均进行二维图像显示，且注视区域的图像分辨率大于非注视区域的图像分辨率。当用户选择的显示模式为三维显示模式时，注视区域和非注视区域可以均进行三维图像显示，或者注视区域可以进行三维图像显示，非注视区域可以进行二维图像显示。针对上述两种情况，驱动芯片通过各第一多路复用单元向注视区域传输三维图像数据，向非注视区域传输三维图像数据或二维图像数据。然而控制器输入的图像源为三维图像数据或二维图像数据，那么在注视区域进行三维图像显示，而在非注视区域进行二维图像显示时，需要将非注视区域内的三维图像数据转化为二维图像数据之后再向非注视区域对应的各第一多路复用单元传输。另外，控制器在将图像数据输出给驱动芯片之前，会对图像数据进行相应的图像渲染，图像渲染的规则可以参见已有技术，在此不做赘述。
本公开实施例提供的显示装置可以同时包括第一多路复用单元和第二多路复用单元，本公开实施例也可以采用第一多路复用单元协同第二多路复用单元驱动实现上述图像显示，具体的驱动电路可以采用5所示的结构。图13a为本公开实施例提供的注视区域对应的驱动时序图之二，图13b为本公开实施例提供的非注视区域对应的驱动时序图之二。
如图5所示，每个像素岛连接四个第一多路复用单元51，每两个像素岛连接一个第二多路复用单元52。每个第一多路复用单元51包括四个第一开关晶体管T1，多路复用电路包括四条第一开关控制信号线l1，四条第一开关控制信号线l1输出的开关控制信号分别为图13a所示的SW1-SW4。每个第二多路复用单元52包括32个第二开关晶体管T2、16个第三开关晶体管T3和一个控制开关晶体管Tc；多路复用单元包括两条第二开关控制信号线l2、四条第三开关控制信号线l3和一条控制信号线lc。两条第二开关控制信号线l2输出的开关控制信号分别为图13a所示的SWO-SWE，四条第三开关控制信号线l3输出的开关控制信号分别为图13a所示的SWb-SWe，控制信号线lc输出的 开关控制信号为图13a所示的SWa。各行子像素对应的栅极传输的扫描信号分别为图13a所示的G1、G2…，驱动芯片输出的图像数据为图13a所示的D。
如图13a和图13b所示，可以使控制信号线lc输出有效电平信号(高电平信号)，各第二开关控制信号线l2和各第三开关控制信号线l3均输出低电平，由此使第二多路复用单元52关闭，采用第一多路复用单元进行驱动。
如图13a所示，针对注视区域，使四条第一开关控制信号线l1依次输出有效电平信号(高电平信号)，从而使对应的四个第一开关晶体管T1依次打开用于向像素岛各列子像素输出不同的图像数据。
具体来说，当第一条栅线输出扫描信号G1为有效电平时段(高电平时段)时，其它栅线输出扫描信号为低电平。在第一条栅线输出有效电平时段期间，第一条第一开关控制信号线先输出高电平信号(SW1为高电平)，其它三条第一开关控制信号线均输出低电平信号(SW2-SW41为低电平)，此时只有连接第一条第一开关控制信号线的第一开关晶体管打开，驱动芯片输出的图像数据通过第一个第一开关晶体管传输给像素岛的第一列子像素；而后第二条第一开关控制信号线输出高电平信号(SW2为高电平)，其它三条第一开关控制信号线均输出低电平信号(SW1、SW3、SW4为低电平)，此时只有连接第二条第一开关控制信号线的第一开关晶体管打开，驱动芯片输出的图像数据通过第二个第一开关晶体管传输给像素岛的第二列子像素；而后第三条第一开关控制信号线输出高电平信号(SW3为高电平)，其它三条第一开关控制信号线均输出低电平信号(SW1、SW2、SW4为低电平)，此时只有连接第三条第一开关控制信号线的第一开关晶体管打开，驱动芯片输出的图像数据通过第三个第一开关晶体管传输给像素岛的第三列子像素；而后第四条第一开关控制信号线输出高电平信号(SW4为高电平)，其它三条第一开关控制信号线均输出低电平信号(SW1-SW3为低电平)，此时只有连接第四条第一开关控制信号线的第一开关晶体管打开，驱动芯片输出的图像数据通过第四个第一开关晶体管传输给像素岛的第四列子像素。在完成上述图像数据的传输之后，第一条栅线输出扫描信号G1为有效电平时段结束，第二条栅线输出扫描信号 G2变为有效电平(高电平)，各第一多路复用单元重复上述操作，以此类推，使注视区域内的各子像素依次写入图像数据，实现注视区域的高分辨率的图像显示。
如图13b所示，针对非注视区域，使四条第一开关控制信号线l1同时输出有效电平信号(高电平信号)，从而使对应的四个第一开关晶体管T1同时打开用于向像素岛各列子像素输出相同的图像数据。
具体来说，当第一条栅线输出扫描信号G1为有效电平时段(高电平时段)时，其它栅线输出扫描信号为低电平。在第一条栅线输出有效电平时段期间，四条第一开关控制信号线同时输出高电平信号(SW1-SW4为高电平)，此时连接四条第一开关控制信号线的四个第一开关晶体管同时打开，驱动芯片输出的图像数据通过四个第一开关晶体管同时传输给像素岛的四列子像素。在完成上述图像数据的传输之后，第一条栅线输出扫描信号G1为有效电平时段结束，第二条栅线输出扫描信号G2变为有效电平(高电平)，各第一多路复用单元重复上述操作，以此类推，使非注视区域内的每四列子像素同时写入相同的图像数据，从而使图像分辨率降低4倍，实现非注视区域的低分辨率的图像显示。
对比图12a和图12b，以及对比图13a和图13b可知，每列子像素的充电时间为1t，当一个第一多路复用单元51中的四个第一开关晶体管T1依次打开分别为四列子像素充电时，需要的时长为4t；当一个第一多路复用单元51中的四个第一开关晶体管同时打开同时为四列子像素充电时，需要的时长为1t。由此可见，非注视区域的子像素充电时长为注视区域的子像素充电时长的1/4，那么注视区域对应的栅极驱动单元的扫描时长将大于非注视区域对应的栅极驱动单元的扫描时长。具体地，非注视区域对应的栅极驱动单元输出有效电平的时长可以缩短为注视区域对应的栅极驱动单元输出有效电平时长的1/4，非注视区域的第一多路复用单元的开启次数相比注视区域降低3/4，功耗降低为原来的1/4。由于非注视区域的充电时间缩短，节省下来的时间可以用于提高显示图像的刷新率，或者也可以用于增加注视区域的刷新率，从而提 高显示效果。
举例来说，如果显示装置包括2000行子像素，其中注视区域包括1000行子像素，非注视区域包括1000行子像素。每个子像素的充电时间为t。那么如果按照传统的驱动方法对每个子像素依次充电，那么充电时间需要2000*4*t＝8000t；而采用本公开实施例提供的上述驱动方案，对于注视区域，控制各列子像素依次充电，需要的充电时间为1000*1*t，对于非注视区域，控制多列子像素同时充电，需要的充电时间为1000*4*t，总的充电时间为1000*1*t+1000*4*t＝5000t。由此可见，采用本公开实施例提供的驱动方案可以缩短整体充电时间，那么节省的时间可以用来提高显示装置的刷新频率，根据上述举例可以将整体刷新频率提高到8/5倍。
采用图13a所示的驱动方案驱动显示装置，4K的图像数据可以产生16个视点，同时实现20Hz的图像刷新率；采用图13b所示的驱动方案驱动显示装置，4K的图像数据可以产生4个视点，同时实现80Hz的图像刷新率。由此可见，当降低视点数量(降低图像分辨率)时，可以将节省的时间用于提高图像刷新率。
图14为本公开实施例提供的注视区域和非注视区域的充电电压对比图。
如图14所示，当栅极驱动单元输出扫描信号G的有效电平时段结束时，子像素的充电动作结束，然而由于本公开实施例对非注视区域的多列子像素同时充电，从图14中可以看出，四列子像素同时充电后的充电电压(4p)相比于各列子像素依次充电后的充电电压(1p)要更低，这是因为同时对四列子像素进行充电时产生的负载更大，那么采用同样的驱动电流同时驱动四列子像素充电会造成四列子像素充电不足，即采用相同的驱动电流对注视区域和非注视区域的子像素进行充电时，会造成非注视区域充电不足导致画面显示不均的问题。
本公开实施例为了克服上述问题，对驱动芯片的驱动电流进行调整，提高驱动芯片对非注视区域的驱动电流，以使注视区域和非注视区域内的子像素的充电程度的差值小于设定阈值，该设定阈值可以设置为一较小值，从而 使注视区域和非注视区域内的子像素的充电程度趋于相等。例如，在确定出注视区域和非注视区域之后，可以将注视区域的驱动电流调整为原本驱动电流的60％-80％，将非注视区域的驱动电流调整为原本驱动电流的100％-120％对显示装置进行驱动，以使注视区域和非注视区域内的子像素均能够充电充足，避免画面显示不均的问题。
具体地，控制器可以根据CHPI协议向驱动芯片的偏置电路连接的寄存器发送控制指令，以使驱动芯片可以区分注视区域和非注视区域采用寄存器中存储的驱动电流分别对注视区域和非注视区域进行驱动。
本公开实施例提供的显示装置还可以采用第二多路复用单元52进行驱动。具体的驱动电路可以采用7所示的结构。图15a为本公开实施例提供的注视区域对应的驱动时序图之三，图15b为本公开实施例提供的非注视区域对应的驱动时序图之三。
如图7所示，显示装置的栅极驱动电路包括多个栅极驱动单元(811-816)，各栅极驱动单元分别向对应的子像素行输出扫描信号。每个像素岛与第一多路复用单元51和第二多路复用单元52的连接关系与图5相同，在此不做赘述。
如图15a和图15b所示，当采用第二多路复用单元52驱动显示装置时，控制信号线始终输出低电平(SWa)，从而使得控制开关晶体管Tc保持关闭状态，此时信号无法传输到第一多路复用单元51，通过第二多路复用单元52控制图像数据的传输。采用第二多路复用单元52驱动显示装置，不仅可以将图像数据依次传输给多个像素岛，还可以将相同的图像数据同时传输给多个像素岛。
如图15a所示，在驱动相邻的多个像素岛20加载相同的图像数据时，控制各第二开关控制信号线同时输出有效电平信号(SWO和SWE为高电平信号)，以使第二多路复用单元中的各第二开关晶体管T2同时打开；与此同时，控制第n行子像素连接的栅极驱动单元和第n+3行子像素连接的栅极驱动单元的输出信号相同；其中，n为大于或等于1的整数。
具体来说，在驱动两行两列的四个相邻的像素岛20加载相同的图像数据时，当第一条栅线输出扫描信号G1为有效电平时段(高电平时段)时，第四条栅线输出的扫描信号G4与G1相同，其它栅线输出扫描信号为低电平。各栅线保持有效电平的时长为1t。
在第一条栅线和第四条栅线输出有效电平时段期间，两条第二开关控制信号线均输出高电平信号(SWO和SWE均为高电平)，此时控制上述四个像素岛的32个第二开关晶体管T2全部打开。图像数据可以同时传输给四个像素岛，且四个像素岛加载的图像数据相同，那么四个像素岛可以被当作一个大的像素岛使用，从而降低整体分辨率。上述驱动方法可以应用于非注视区域进行低分辨率的图像显示。
与此同时，如图15a所示，还可以控制四条第三开关控制信号线均输出高电平信号(SWb-SWe均为高电平)，此时每个第三开关晶体管组T3s中的四个第三开关晶体管T3同时打开，同时为每个像素岛中的四列子像素同时传输相同的数据信号，这样可以进一步降低像素岛产生的视点数量，即减小像素岛内的分辨率，上述驱动方法可以应用于非注视区域进行低分辨率的图像显示。
在完成上述图像数据的传输之后，第一条栅线输出扫描信号G1为有效电平时段结束，第二条栅线输出扫描信号G2变为有效电平(高电平)，第五条栅线输出的扫描信号G5与G2相同，各第二多路复用单元重复上述操作，以此类推，实现非注视区域的低分辨率的图像显示。
如图15b所示，在驱动各像素岛加载不同的图像数据时，控制各第二开关控制信号线依次输出有效电平信号(高电平信号)，以使第二多路复用单元中的连接不同像素岛的第二开关晶体管依次打开，用于传输不同的图像数据。
具体来说，当第一条栅线输出扫描信号G1为有效电平时段(高电平时段)时，第四条栅线输出的扫描信号G4与G1相同；第二条栅线输出的扫描信号G2的有效电平时段相对于G1错后1t，第五条栅线输出的扫描信号与G2相同；以此类推。每条栅线保持高电平的时长为四列子像素依次进行充电所需 要的时长(保持高电平的时长为4t)。
在第一条栅线输出有效电平时段期间，第四条栅线输出的信号与第一栅线相同，两条第二开关控制信号线依次输出有效电平信号，即第一条第二开关控制信号线先输出高电平信号(SWO为高电平)，第二条第二开关控制信号线输出低电平信号(SWE为低电平)，而后第二条第二开关控制信号线输出有效电平信号(SWE高电平信号)，第一条第二开关控制信号线输出低电平信号(SWO为低电平)；其中每条第二开关控制信号线输出有效电平的时长为一列子像素进行充电所需要的时长(有效电平时长为1t)。此时，连接第一个像素岛的16个第二开关晶体管T2在第一条第二开关控制信号线的控制下打开时，连接第二个像素岛的16个第二开关晶体管T2在第二条开控制信号线的控制下关闭；连接第二个像素岛的16个第二开关晶体管T2在第二条第二开关控制信号线的控制下打开时，连接第一个像素岛的16个第二开关晶体管T2在第一条开控制信号线的控制下关闭，由此实现依次向各像素岛加载图像数据。
如图15b所示，在各第二开关晶体管T2进行上述驱动的同时，四条第三开关控制信号线依次输出有效电平信号(高电平信号)，每条第三开关控制信号线保持高电平信号的时长为2t。
当第一条第三开关控制信号线输出有效电平信号(SWb为高电平)时，其它三条第三开关控制信号线均输出低电平信号(SWc-SW4e为低电平)，此时只有连接第一条第三开关控制信号线的第三开关晶体管打开，驱动芯片输出的图像数据通过第一个第三开关晶体管传输给第一个像素岛的第一列子像素，驱动芯片输出的图像数据再通过第一个第三开关晶体管传输给第二个像素岛的第一列子像素。而后第二条第三开关控制信号线输出高电平信号(SWc为高电平)，其它三条第三开关控制信号线均输出低电平信号(SWb、SWd、SWe为低电平)，此时只有连接第二条第三开关控制信号线的第三开关晶体管打开，驱动芯片输出的图像数据通过第二个第三开关晶体管传输给第一个像素岛的第二列子像素，驱动芯片输出的图像数据再通过第二个第三开关晶体 管传输给第二个像素岛的第二列子像素。而后第三条第三开关控制信号线输出高电平信号(SWd为高电平)，其它三条第三开关控制信号线均输出低电平信号(SWb、SWc、SWe为低电平)，此时只有连接第三条第三开关控制信号线的第三开关晶体管打开，驱动芯片输出的图像数据通过第三个第三开关晶体管传输给第一个像素岛的第三列子像素，驱动芯片输出的图像数据再通过第三个第三开关晶体管传输给第二个像素岛的第三列子像素。而后第四条第三开关控制信号线输出高电平信号(SWe为高电平)，其它三条第三开关控制信号线均输出低电平信号(SWb-SWd为低电平)，此时只有连接第四条第三开关控制信号线的第三开关晶体管打开，驱动芯片输出的图像数据通过第四个第三开关晶体管传输给第一个像素岛的第四列子像素，驱动芯片输出的图像数据再通过第四个第三开关晶体管传输给第二个像素岛的第四列子像素。由此实现对不同像素岛的各子像素依次加载不同的图像数据的目的，上述驱动方法可以用于驱动注视区域进行高清图像显示。
采用图15a所示的驱动方案驱动显示装置，2K的图像数据可以产生4个视点，同时实现80Hz的图像刷新率；采用图15b所示的驱动方案驱动显示装置，2K的图像数据可以产生16个视点，同时实现80Hz的图像刷新率。由此可见，通过同时控制多个像素岛同时进行充电，也可以做到对视点数量的调整。
图16为本公开实施例提供的显示装置的系统架构示意图。
如图16所示，在用户选择的2D显示模式时，接收2D视频源的图像数据；在用户选择3D显示模式时，接收3D视频源的图像数据。摄像头实时监测人眼的位置，从而确定出人眼在显示装置的注视点坐标以及分析出观看显示装置的人数。在确定出人眼在显示装置的注视位置之后将显示图像拆分为注视区域和非注视区域，并根据用户的选择模式对注视区域进行高分辨率的图像渲染，对非注视区域进行低分辨率的图像渲染，再将图像渲染后的图像数据发送给显示面板的驱动芯片，从而使显示面板根据指令进行驱动。与此同时，可以控制液晶透镜加载相适应的扫描驱动信号，从而在注视区域进行 高分辨率的图像显示，在非注视区域进行低分辨率的图像显示，由此在保证用户体验的前提下降低功耗，达到资源的合理分配。
上述数据处理和发送指令的操作均由本公开实施例的控制器实现，控制器可以为显示芯片(Graphics Processing Unit，简称GPU)和/或现场可编程门阵列(Field-Programmable Gate Array，简称FPGA)，在此不做限定。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (23)

  1. 一种显示装置，其中，包括：
    衬底基板；
    多个像素岛，位于所述衬底基板上；所述像素岛包括多个不同颜色的子像素，所有子像素沿第一方向和第二方向呈阵列排布，一个所述像素岛中颜色相同的子像素沿所述第一方向排列成一行，不同颜色的子像素行沿所述第二方向排列，所述第一方向和所述第二方向交叉；
    多条数据线，沿所述第一方向排列且沿所述第二方向延伸；沿所述第二方向排列成同一列的子像素连接同一条所述数据线；
    多路复用电路，沿所述第二方向位于所有像素岛所在区域的一侧；所述数据线分别连接所述多路复用电路；
    驱动芯片，沿所述第二方向位于所述多路复用电路背离所述像素岛的一侧，所述多路复用电路连接所述驱动芯片；
    控制器，连接所述驱动芯片，被配置为向所述驱动芯片提供驱动信号；
    微透镜层，位于所述像素岛背离所述衬底基板的一侧，所述微透镜层对所述像素岛的出射光线进行调制，以使所述像素岛中的子像素映射为像素阵列并实现三维显示；
    一个所述像素岛中的子像素列沿所述第一方向分为多个子像素组，每个所述子像素组中包括的子像素列的数量相等；
    所述多路复用电路包括多个沿所述第一方向排列的第一多路复用单元，所述第一多路复用单元包括一个输入端和多个输出端；一个所述第一多路复用单元对应连接一个所述子像素组，所述第一多路复用单元的输出端分别连接所述子像素组对应的数据线，所述第一多路复用单元的输入端连接所述驱动芯片。
  2. 如权利要求1所述的显示装置，其中，所述多路复用电路还包括：
    多条第一开关控制信号线，所述第一开关控制信号线沿所述第一方向延 伸沿所述第二方向排列；
    所述第一多路复用单元包括：多个第一开关晶体管，所述第一开关晶体管的控制极连接所述第一开关控制信号线，所述第一开关晶体管的第一极连接所述第一多路复用单元的输出端，所述第一开关晶体管的第二极连接所述第一多路复用单元的输入端；
    一个所述第一多路复用单元中，各所述第一开关晶体管的控制极分别连接不同的所述第一开关控制信号线，各所述第一开关晶体管的第一极分别连接所述第一多路复用单元的不同的输出端。
  3. 如权利要求2所述的显示装置，其中，所述多路复用电路还包括：
    多个控制单元，沿所述第二方向位于所述第一多路复用单元背离所述像素岛的一侧，所述控制单元沿所述第一方向排列；所述控制单元包括一个输入端和一个输出端；一个所述控制单元对应连接一个所述第一多路复用单元，所述控制单元的输出端连接所述第一多路复用单元的输入端，所述控制单元的输入端连接所述驱动芯片。
  4. 如权利要求3所述的显示装置，其中，所述多路复用电路还包括：
    控制信号线，沿所述第一方向延伸；
    所述控制单元包括：控制开关晶体管；所述控制开关晶体管的控制极连接所述控制信号线，所述控制开关晶体管的第一极连接所述控制单元的输出端，所述控制开关晶体管的第二极连接所述控制单元的输入端。
  5. 如权利要求4所述的显示装置，其中，所述多路复用电路还包括：
    多个第二多路复用单元，沿所述第二方向位于所述第一多路复用单元背离所述像素岛的一侧，所述第二多路复用单元沿所述第一方向排列；所述第二多路复用单元包括多个输入端和多个输出端，所述输入端的数量小于所述输出端的数量；一个所述第二多路复用单元对应连接沿所述第一方向排列的多个所述像素岛，所述第二多路复用单元的输出端分别连接各所述像素岛中的各子像素列对应的数据线，所述第二多路复用单元的输入端分别连接所述驱动芯片。
  6. 如权利要求5所述的显示装置，其中，所述多路复用电路还包括：
    多条第二开关控制信号线，所述第二开关控制信号线沿所述第一方向延伸沿所述第二方向排列；
    多条第三开关控制信号线，所述第三开关控制信号线沿所述第一方向延伸沿所述第二方向排列；
    所述第二多路复用单元包括：多个第二开关晶体管和多个第三开关晶体管；
    所述第二开关晶体管的控制极连接所述第二开关控制信号线，所述第二开关晶体管的第一极连接所述第二多路复用单元的输出端，所述第二开关晶体管的第二极连接所述第三开关晶体管的第一极；所述第三开关晶体管的控制极连接所述第三开关控制信号线，所述第三开关晶体管的第二极连接所述第二多路复用单元的输入端；
    一个所述第二多路复用单元中，连接同一个所述像素岛的所述第二开关晶体管的控制极连接同一条所述第二开关控制信号线，连接不同的所述像素岛的所述第二开关晶体管的控制极连接不同的所述第二开关控制信号线；连接各所述像素岛中相同位置的子像素列的所述第二开关晶体管的第二极相互连接；
    一个所述第二多路复用单元中，各所述第三开关晶体管与所述第二多路复用单元所连接的其中一个所述像素岛对应；该像素岛对应第三开关晶体管和第二开关晶体管中，各所述第三开关晶体管的第一极分别连接各所述第二开关晶体管的第二极；
    一个所述第二多路复用单元中，所述第三开关晶体管沿所述第一方向分为多个第三开关晶体管组，所述第三开关晶体管组的数量与一个所述像素岛中包括的子像素组的数量相等；
    一个所述第三开关晶体管组中，各所述第三开关晶体管的控制极分别连接不同的所述第三开关控制信号线，各所述第三开关晶体管的第二极连接所述第二多路复用单元的同一个输入端。
  7. 如权利要求6所述的显示装置，其中，还包括：
    多条栅线，沿所述第一方向延伸且沿所述第二方向排列；沿所述第一方向排列成同一行的子像素连接同一条所述栅线；
    栅极驱动电路，沿所述第一方向位于所述像素岛所在区域的一侧或两侧；所述栅线分别连接所述栅极驱动电路；
    所述栅极驱动电路包括多个沿所述第二方向排列的栅极驱动单元，各所述栅极驱动单元沿所述第二方向相互级联，各所述栅极驱动单元单独扫描对应的子像素行。
  8. 如权利要求1-7任一项所述的显示装置，其中，还包括：
    摄像头，被配置为对用户的眼睛进行拍摄，以使所述控制器根据所述摄像头拍摄的图像确定用户在所述显示装置的注视区域，控制所述驱动芯片驱动所述注视区域和非注视区域以不同分辨率进行图像显示。
  9. 如权利要求1-7任一项所述的显示装置，其中，所述微透镜层包括至少一个液晶透镜层。
  10. 如权利要求7所述的显示装置，其中，所述像素岛包括十六个红色子像素、十六个绿色子像素和十六个蓝色子像素，所述红色子像素、所述绿色子像素和所述蓝色子像素沿所述第一方向排列成三行，沿所述第二方向排列成十六列；一个所述像素岛经过所述微透镜层的映射形成排列为四行四列的十六个像素；
    一个所述像素岛中的子像素沿所述第一方向分为四个子像素组，每个所述子像素组包括四个子像素列；
    所述多路复用电路包括四条第一开关控制信号线，一个所述第一多路复用单元包括四个第一开关晶体管；四个所述第一开关晶体管的控制极分别连接四条所述第一开关控制信号线，四个所述第一开关晶体管的第一极分别连接一个所述子像素组中的四个子像素列对应的数据线；四个所述第一开关晶体管的第二极相互连接，连接至所述驱动芯片。
  11. 如权利要求10所述的显示装置，其中，一个第一多路复用单元通过 一个所述控制单元连接至所述驱动芯片；
    所述多路复用电路包括一条控制信号线，一个所述控制单元包括一个控制开关晶体管；各所述控制开关晶体管的控制极均连接所述控制信号线，一个所述控制单元中的所述控制开关晶体管的第一极连接一个所述第一多路复用单元中的四个所述第一开关晶体管的第二极，所述控制开关晶体管的第二极连接所述驱动芯片。
  12. 如权利要求11所述的显示装置，其中，所述多路复用电路包括两条第二开关控制信号线和四条第三开关控制信号线；
    一个所述第二多路复用单元对应连接沿所述第一方向排列的两个所述像素岛，两个所述像素岛为第一像素岛和第二像素岛；
    一个所述第二多路复用单元包括三十二个第二开关晶体管；一个所述第二多路复用单元中的十六个所述第二开关晶体管对应连接所述第一像素岛的数据线，另外十六个所述第二开关晶体管对应连接所述第二像素岛的数据线；
    对应于所述第一像素岛的十六个所述第二开关晶体管的控制极均连接其中一条所述第二开关控制信号线，对应于所述第二像素岛的十六个所述第二开关晶体管的控制极均连接另一条所述第二开关控制信号线；对应于所述第一像素岛的各所述第二开关晶体管的第一极分别连接所述第一像素岛的各数据线，对应于所述第二像素岛的各所述第二开关晶体管的第一极分别连接所述第二像素岛的各数据线；所述第一像素岛和所述第二像素岛中位于相同位置的子像素列所对应的两个所述第二开关晶体管的第二极相互连接；
    一个所述第二多路复用单元包括十六个第三开关晶体管；十六个所述第三开关晶体管对应于所述第一像素岛；十六个所述第三开关晶体管沿所述第一方向分为四个第三开关晶体管组；
    一个所述第三开关晶体管组中的四个所述第三开关晶体管的控制极分别连接四条所述第三开关控制信号线，对应于同一个子像素列的所述第二开关晶体管的第二极连接所述第三开关晶体管的第一极，四个所述第三开关晶体管的第二极相互连接，连接至所述驱动芯片。
  13. 一种基于权利要求1-12任一项所述的显示装置的驱动方法，其中，包括：
    实时确定用户在所述显示装置的注视区域和非注视区域；
    驱动所述注视区域以第一分辨率进行图像显示，驱动所述非注视区域以第二分辨率进行图像显示；所述第一分辨率高于所述第二分辨率。
  14. 如权利要求13所述的驱动方法，其中，所述显示装置包括摄像头；
    所述实时确定用户在所述显示装置的注视区域和非注视区域，包括：
    控制所述摄像头实时对用户的眼睛进行拍摄；
    根据所述摄像头拍摄的图像确定用户在所述显示装置的注视区域；
    将所述显示装置中除所述注视区域以外的其它区域确定为非注视区域。
  15. 如权利要求14所述的驱动方法，其中，所述根据所述摄像头拍摄的图像确定用户在所述显示装置的注视区域，包括：
    根据所述摄像头拍摄的图像分别确定用户的左眼和右眼相对于所述显示装置的显示面的位置；
    根据用户的左眼和右眼相对于所述显示装置的显示面的位置，以及用户与所述显示装置之间的距离，分别确定出用户的左眼在所述显示装置的左眼注视区域和用户的右眼在所述显示装置的右眼注视区域；
    将所述左眼注视区域和所述右眼注视区域的交叠区域作为所述用户在所述显示装置的注视区域。
  16. 如权利要求15所述的驱动方法，其中，采用以下公式确定用户的单个眼睛在所述显示装置的注视区域：
    S＝π(A tan 15°) 2；
    其中，S表示用户的单个眼睛在所述显示装置的注视区域，A表示用户与所述显示装置之间的距离。
  17. 如权利要求13所述的驱动方法，其中，在所述驱动所述注视区域以第一分辨率进行图像显示，驱动所述非注视区域以第二分辨率进行图像显示之前，还包括：
    确定用户选择的显示模式；
    所述驱动所述注视区域以第一分辨率进行图像显示，驱动所述非注视区域以第二分辨率进行图像显示，包括：
    在用户选择的显示模式为二维显示模式时，驱动所述注视区域以第一分辨率进行二维图像显示，驱动所述非注视区域以第二分辨率进行二维图像显示；
    在用户选择的显示模式为三维显示模式时，驱动所述注视区域以第一分辨率进行三维图像显示，驱动所述非注视区域以第二分辨率进行二维图像显示；或者，在用户选择的显示模式为三维显示模式时，驱动所述注视区域以第一分辨率进行三维图像显示，驱动所述非注视区域以第二分辨率进行三维图像显示。
  18. 如权利要求17所述的驱动方法，其中，在用户选择的显示模式为二维显示时，所述驱动所述注视区域以第一分辨率进行二维图像显示，驱动所述非注视区域以第二分辨率进行二维图像显示，包括：
    接收二维图像数据，针对所述注视区域对所述二维图像数据进行第一分辨率的图像渲染，针对所述非注视区域对所述二维图像数据进行第二分辨率的图像渲染；
    控制所述注视区域对应的各所述第一开关控制信号线依次输出有效电平信号，以使所述第一多路复用单元中的各第一开关晶体管依次打开传输不同的二维图像数据，控制所述非注视区域对应的各所述第一开关控制信号线同时输出有效电平信号，以使所述第一多路复用单元中的各第一开关晶体管同时打开传输相同的二维图像数据，以实现驱动所述注视区域以所述第一分辨率进行二维图像显示，驱动所述非注视区域以第二分辨率进行二维图像显示。
  19. 如权利要求17所述的驱动方法，其中，在用户选择的显示模式为三维显示时，所述驱动所述注视区域以第一分辨率进行三维图像显示，驱动所述非注视区域以第二分辨率进行三维图像显示，包括：
    接收三维图像数据，针对所述注视区域对所述三维图像数据进行第一分 辨率的图像渲染，针对所述非注视区域对所述三维图像数据进行第二分辨率的图像渲染；
    控制所述注视区域对应的各所述第一开关控制信号线依次输出有效电平信号，以使所述第一多路复用单元中的各第一开关晶体管依次打开传输不同的三维图像数据，控制所述非注视区域对应的各所述第一开关控制信号线同时输出有效电平信号，以使所述第一多路复用单元中的各第一开关晶体管同时打开传输相同的三维图像数据，以实现驱动所述注视区域以第一分辨率进行三维图像显示，驱动所述非注视区域以第二分辨率进行三维图像显示。
  20. 如权利要求17所述的驱动方法，其中，在用户选择的显示模式为三维显示时，所述驱动所述注视区域以第一分辨率进行三维图像显示，驱动所述非注视区域以第二分辨率进行二维图像显示，包括：
    接收三维图像数据，将所述非注视区域对应的三维图像数据转化为二维图像数据；
    针对所述注视区域对所述三维图像数据进行第一分辨率的图像渲染，针对所述非注视区域对所述二维图像数据进行第二分辨率的图像渲染；
    控制所述注视区域对应的各所述第一开关控制信号线依次输出有效电平信号，以使所述第一多路复用单元中的各第一开关晶体管依次打开传输不同的三维图像数据，控制所述非注视区域对应的各所述第一开关控制信号线同时输出有效电平信号，以使所述第一多路复用单元中的各第一开关晶体管同时打开传输相同的二维图像数据，以实现驱动所述注视区域以第一分辨率进行三维图像显示，驱动所述非注视区域以第二分辨率进行二维图像显示。
  21. 如权利要求18-20任一项所述的驱动方法，其中，所述注视区域对应的栅极驱动单元的扫描时长大于所述非注视区域对应的栅极驱动单元的扫描时长。
  22. 如权利要求21所述的驱动方法，其中，所述驱动方法还包括：
    提高所述驱动芯片对所述非注视区域的驱动电流，以使所述注视区域和所述非注视区域内的子像素的充电程度的差值小于设定阈值。
  23. 如权利要求13所述的驱动方法，其中，所述显示装置的栅极驱动电路包括多个栅极驱动单元，所述显示装置的多路复用电路还包括多个第二多路复用单元和多个控制单元；所述驱动方法包括：
    驱动各所述控制单元的控制开关晶体管保持关闭；
    在驱动相邻的多个像素岛加载相同的图像数据时，控制第n行子像素连接的栅极驱动单元和第n+3行子像素连接的栅极驱动单元的输出信号相同；n为大于或等于1的整数；控制各第二开关控制信号线同时输出有效电平信号，以使所述第二多路复用单元中的各第二开关晶体管同时打开，实现相邻的多个像素岛加载的图像数据相同；
    在驱动各像素岛加载不同的图像数据时，控制各第二开关控制信号线依次输出有效电平信号，以使所述第二多路复用单元中的连接不同像素岛的第二开关晶体管依次打开，实现各像素岛加载的图像数据不同；
    其中，针对同一个像素岛的驱动方法包括：
    控制各第三开关控制信号线同时输出有效电平信号，以使所述第二多路复用单元中的各第三开关晶体管同时打开传输相同的图像数据；
    或者，控制各第三开关控制信号线依次输出有效电平信号，以使所述第二多路复用单元中的各第三开关晶体管依次打开传输不同的图像数据。
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