WO2022104731A1 - 异构系统的安全防护方法、装置及处理器 - Google Patents

异构系统的安全防护方法、装置及处理器 Download PDF

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Publication number
WO2022104731A1
WO2022104731A1 PCT/CN2020/130574 CN2020130574W WO2022104731A1 WO 2022104731 A1 WO2022104731 A1 WO 2022104731A1 CN 2020130574 W CN2020130574 W CN 2020130574W WO 2022104731 A1 WO2022104731 A1 WO 2022104731A1
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Prior art keywords
configuration file
unclonable function
physical unclonable
function circuit
processor
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PCT/CN2020/130574
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English (en)
French (fr)
Inventor
魏祥野
修黎明
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京东方科技集团股份有限公司
北京京东方技术开发有限公司
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Priority to US18/034,051 priority Critical patent/US20230394137A1/en
Priority to CN202080002890.3A priority patent/CN114830598B/zh
Priority to PCT/CN2020/130574 priority patent/WO2022104731A1/zh
Publication of WO2022104731A1 publication Critical patent/WO2022104731A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/55—Detecting local intrusion or implementing counter-measures
    • G06F21/552—Detecting local intrusion or implementing counter-measures involving long-term monitoring or reporting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/03—Indexing scheme relating to G06F21/50, monitoring users, programs or devices to maintain the integrity of platforms
    • G06F2221/034—Test or assess a computer or a system

Definitions

  • the invention relates to the technical field of information security, and in particular, to a security protection method, device and processor of a heterogeneous system.
  • the Physical Unclonable Function came into being.
  • the Physical Unclonable Function is a hardware function implementation circuit that depends on the characteristics of the chip. It has uniqueness and randomness. The deviation of the process parameters can realize the unique function of the excitation signal and the response signal.
  • criminals attack the system by modeling the PUF and establishing the PUF model based on the used CRP (Challenge Response Pair, stimulus response pair), which makes the system security not high.
  • the present invention aims to solve one of the technical problems in the related art at least to a certain extent. Therefore, the first purpose of the present invention is to propose a security protection method for a heterogeneous system, when an external attack is detected, the physical unclonable function is reconstructed, so that the attacker cannot reconstruct the physical unclonable function after the reconstruction. Circuits are modeled to improve the safety of the system.
  • a second object of the present invention is to provide a computer-readable storage medium.
  • the third object of the present invention is to provide an electronic device.
  • the fourth object of the present invention is to provide a safety protection device for heterogeneous systems.
  • a fifth object of the present invention is to propose a processor.
  • an embodiment of the first aspect of the present invention proposes a security protection method for a heterogeneous system.
  • the heterogeneous system includes a processor, the processor includes a first area, and the first area includes a physical unclonable function circuit.
  • a configuration file is obtained, wherein the obtained configuration file is different from the configuration file of the running physical unclonable function circuit;
  • mapping relationship of the physical unclonable function circuit is reconstructed on the processor according to the obtained configuration file.
  • the configuration file when an external attack is detected on the heterogeneous system, the configuration file is re-acquired, and the obtained configuration file is different from the configuration file of the running physical unclonable function.
  • the configuration file reconstructs the mapping relationship of the physical unclonable function on the processor.
  • the mapping relationship of the reconstructed physical unclonable function is different from the mapping relationship of the original physical unclonable function. Therefore, even if the same stimulus is input, the two generated It also responds differently, so that the attacker cannot model the reconstructed physical unclonable function circuit, which improves the security of the system.
  • the embodiment of the second aspect of the present invention provides a computer-readable storage medium on which a security protection program of a heterogeneous system is stored, and the security protection program of the heterogeneous system is executed by a processor.
  • the computer-readable storage medium of the embodiment of the present invention through the aforementioned security protection method for heterogeneous systems, when it is detected that the heterogeneous system is attacked from outside, the physical unclonable function circuit is reconstructed, and the attacker cannot The physical unclonable function circuit is modeled, which improves the security of the system.
  • an embodiment of the third aspect of the present invention provides an electronic device, including a memory, a processor, and a security protection program for a heterogeneous system stored in the memory and running on the processor, the processor executing When the security protection program is used, the security protection method of the aforementioned heterogeneous system is realized.
  • the electronic device of the embodiment of the present invention through the aforementioned security protection method for a heterogeneous system, when it is detected that the heterogeneous system is attacked by an external, the physical unclonable function circuit is reconstructed, and the attacker cannot make the reconstructed physical unclonable function circuit.
  • the function circuit is modeled, which improves the security of the system.
  • a fourth aspect of the present invention provides a security protection device for a heterogeneous system.
  • the heterogeneous system includes a processor, the processor includes a first area, and the first area includes a physical unclonable function circuit.
  • Guards include:
  • the detection module is used to detect whether the input of the heterogeneous system is abnormal
  • an acquisition module configured to acquire a configuration file when the input of the heterogeneous system is abnormal, and the acquired configuration file is different from the configuration file of the running physical unclonable function circuit;
  • the reconstruction module is used to reconstruct the mapping relationship of the physical unclonable function circuit on the processor according to the obtained configuration file.
  • the security protection device for a heterogeneous system when an external attack is detected on the heterogeneous system, the physical unclonable function circuit is reconstructed, and the attacker cannot model the reconstructed physical unclonable function circuit. Improve the security of the system.
  • a fifth aspect of the present invention provides a processor, including:
  • the programmable logic part includes a first area, and the first area includes a physical unclonable function circuit;
  • the detector is used to detect whether the processor is attacked
  • the operation part is used to obtain a configuration file when the processor is attacked, and reconstruct the mapping relationship of the physical unclonable function circuit in the programmable logic part according to the obtained configuration file, wherein the obtained configuration file Different from the configuration file of the running physical unclonable function circuit.
  • the processor of the embodiment of the present invention when it is detected that the heterogeneous system is attacked from the outside, the physical unclonable function circuit is reconstructed, and the attacker cannot model the reconstructed physical unclonable function circuit, which improves the security of the system sex.
  • FIG. 1 is a schematic block diagram of a heterogeneous system according to an embodiment of the present invention.
  • FIG. 2 is a flowchart of a security protection method for a heterogeneous system according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a partition of a processor according to an embodiment of the present invention.
  • FIG. 4 is a schematic block diagram of a physical unclonable function circuit based on time-averaged frequency pulse direct synthesis of a processor according to an embodiment of the present invention
  • FIG. 5 is a schematic diagram of the working principle of a time-averaged frequency-based direct pulse synthesizer according to an embodiment of the present invention
  • FIG. 6 is a Hamming distance statistical diagram before and after reconstruction of a physical unclonable function circuit based on time-averaged frequency pulse direct synthesis of a processor according to an embodiment of the present invention
  • FIG. 7 is a flowchart of a security protection method for a heterogeneous system according to a specific embodiment of the present invention.
  • FIG. 8 is a schematic block diagram of a safety protection device of a heterogeneous system according to an embodiment of the present invention.
  • FIG. 9 is a block diagram of a processor according to an embodiment of the present invention.
  • a heterogeneous system includes a processor for running a physically unclonable function circuit.
  • the processor may be a programmable logic array (Field Programmable Gate Array, FPGA).
  • FPGA Field Programmable Gate Array
  • the heterogeneous system also includes a central processing unit (Central Processing Unit, CPU), a graphics processing unit (Graphics Processing Unit, GPU), and a digital signal processing unit (Digital Signal Process, DSP), which are used to meet different requirements under the Internet of Everything.
  • CPU Central Processing Unit
  • GPU Graphics Processing Unit
  • DSP Digital Signal Process
  • FPGA includes programmable logic part (Programmable Logic, PL) and program system (Process System, PS) part.
  • the PL part includes a first area, and the first area includes a physical unclonable function circuit.
  • the security protection methods for heterogeneous systems include:
  • Step S100 detecting whether the input of the heterogeneous system is abnormal.
  • Heterogeneous systems include detectors, such as AI (Artificial Intelligence) detectors, which are used to detect whether the input of the system is abnormal.
  • AI Artificial Intelligence
  • the physical unclonable function circuit configured in the first area of the PL part of the FPGA starts to work.
  • the AI detector detects in real time whether there is an external attack on the system, such as whether the discarded CRP has been used for multiple application verifications, whether the heterogeneous system software detects external access, and whether the temperature and temperature of the heterogeneous system are detected.
  • the physical parameters such as voltage are abnormally jittered, etc., if the above conditions exist, it can be determined that the input of the heterogeneous system is abnormal, that is, the heterogeneous system encounters an external attack.
  • Step S200 when an abnormal input of the heterogeneous system is detected, obtain a configuration file, wherein the obtained configuration file is different from the configuration file of the running physical unclonable function circuit.
  • Configuration files are used to configure the device placement and routing of physically unclonable function circuits in the FPGA.
  • the FPGA erases the running physical unclonable function circuit and re-acquires the configuration file.
  • the obtained configuration file is different from the configuration file of the running physical unclonable function circuit, so that the Refactoring Physically Unclonable Function Circuits in .
  • obtaining the configuration file includes: obtaining a pre-stored configuration file, wherein the obtained pre-stored configuration file is different from the configuration file of the running physical unclonable function circuit.
  • a plurality of different configuration files are pre-stored in the storage module of the heterogeneous system, so that when the heterogeneous system is attacked, a new configuration file can be obtained, and the physical inaccessibility of different layouts can be reconstructed according to the new configuration file. Clone function circuit.
  • acquiring the configuration file includes: regenerating the configuration file, and the regenerated configuration file is different from the configuration file of the running physical unclonable function circuit.
  • the system can directly generate configuration files, and use the regenerated configuration files to build a physical unclonable function circuit in the FPGA, so that the attacker cannot Unclonable function circuits are used for traversal attacks, thereby improving the security of heterogeneous systems.
  • Step S300 reconstruct the mapping relationship of the physical unclonable function circuit on the FPGA according to the obtained configuration file.
  • mapping relationship includes the relationship between the excitation and response of the physical unclonable function circuit, and the mapping relationship can be specifically expressed as:
  • c is the abbreviation of challenge, which represents incentive, that is, the verification code sent by the user or the requester
  • r is the abbreviation of response, that is, the response generated by the verification party according to the incentive
  • f() reflects the mapping relationship.
  • Different physical unclonable functions have different process deviations and different mapping relationships.
  • the FPGA can read the configuration file and select an area according to the configuration file to layout and connect the logic elements of the selected area to reconstruct the mapping relationship of the physical unclonable function circuit.
  • the configuration file is re-acquired, and the obtained configuration file is different from the configuration file of the running physical unclonable function. Reconstruct the mapping relationship of the physical unclonable function.
  • the mapping relationship of the reconstructed physical unclonable function is different from the mapping relationship of the original physical unclonable function. Therefore, even if the same stimulus is input, the responses generated by the two are different, which makes the attack.
  • the author cannot model the reconstructed physical unclonable function circuit, which improves the security of the system.
  • reconstructing the mapping relationship of the physical unclonable function circuit in different layouts on the processor according to the acquired configuration file includes: compiling the physical unclonable function circuit according to the acquired configuration file and then re-creating the physical unclonable function circuit. Design; store the result of the design to the processor to reconstruct the mapping of the physical unclonable function circuit.
  • redesigning the physical unclonable function circuit after compiling refers to designing the layout and wiring method of the physical unclonable function circuit, and storing the design result on the processor, so that the reconstructed physical unclonable function circuit can be stored on the processor.
  • storing the result of the design to the processor to reconstruct the mapping relationship of the physical unclonable function circuit includes: storing the result of the design in the first area of the processor or different from the first area to reconstruct the mapping relationship of the physical unclonable function circuit.
  • the present application can not only run the reconstructed physical unclonable function circuit in the first region where the original physical unclonable function circuit runs, but also run the reconstructed physical unclonable function circuit in the second region different from the first region.
  • the cloned function circuit and even other areas can also run the reconstructed physical unclonable function circuit, as long as the reconstructed physical unclonable function circuit has a different design from the original physical unclonable function circuit, that is, the layout and wiring methods are different. .
  • FPGA includes PS part and PL part.
  • the PS part is used to complete software algorithms or special control, and there is a real-time operating system in it, while the PL part is used for programmable logic, which can implement different logic circuits or operations on the PL.
  • both the first region and the second region are located in the PL portion.
  • the physical unclonable function circuit can be implemented in the FPGA with less overhead.
  • the first area and the second area can be set in the PL part, and the physical unclonable function circuit can be partially reconfigurable in the first area of the PL. Or run on a second zone or other zone.
  • the size of the physical unclonable function circuit can be designed according to the requirements.
  • Table 1 The relationship between the excitation of the physical unclonable function circuit and the excitation-response pair generated according to the excitation can be referred to as shown in Table 1:
  • the areas of the first region and the second region are both larger than the physical unclonable function circuit.
  • the area of the first region and the second region can be designed to be no less than 1.5 times the area occupied by the physical unclonable function circuit, so as to provide sufficient space margin for the reconstructed physical unclonable function .
  • the security protection method of the above heterogeneous system can be reconstructed in the first area running the original physical unclonable function circuit, or in the second area or even other areas different from the first area, so that it can be used for processing.
  • the controller provides unlimited stimulus-response pairs, making it impossible for external attackers to conduct modeling or traversal attacks, improving the security of heterogeneous systems.
  • the first area or the second area can be configured with an infinite variety of physical unclonable function circuits of different structures, and furthermore, with a smaller
  • the overhead realizes the reconstruction of the physical unclonable function circuit of various structures, which can reduce the cost.
  • the physical unclonable function circuit is a physical unclonable function circuit (Time-Average-Frequency Direct Period Synthesis Physical Unclonable Function, TAF-DPS-PUF) based on time-averaged frequency pulse direct synthesis.
  • TAF-DPS-PUF can construct a mapping relationship according to the following steps: extract the first parameters through the symmetrical first time-averaged frequency-based pulse direct synthesizer and the second time-averaged frequency-based pulse direct synthesizer, respectively, to generate corresponding features A bit stream; a mapping relationship is constructed according to the delay characteristics of the output characteristic bit streams of the first time-averaged frequency pulse direct synthesizer and the second time-averaged frequency pulse direct synthesizer.
  • the physical unclonable function circuit based on time-averaged frequency pulse direct synthesis includes a symmetrical first time-averaged frequency-based pulse direct synthesizer 310 and a second time-averaged frequency-based pulse direct synthesizer 320, Trigger 330.
  • TAF-DPS time-averaged frequency pulse direct synthesizer
  • the two time periods can be synthesized through the period synthesis technique to obtain a clock signal whose period is the target period, and the target period T TAF can satisfy:
  • T TAF (1-r)*TA+r*TB Formula (3)
  • T TAF (I+r)* ⁇ Formula (4)
  • r can control the probability of TB occurrence, that is, the switching frequency between the control period TA and TB.
  • the frequency f TAF of the clock signal output by the TAF-DPS frequency synthesizer can be further calculated as:
  • the TAF-DPS frequency synthesizer can generate any frequency given a sufficient number of bits in r in the control word F.
  • the first time-averaged frequency pulse direct synthesizer 310 and the second time-averaged frequency pulse synthesizer 320 have the same type, quantity and layout of logic units, and both form a delay path with the same structure.
  • the physical unclonable function circuit based on time-averaged frequency pulse direct synthesis further includes an oscillator 340 and a control module 350.
  • the oscillator 340 is connected to the first time-averaged frequency-based direct pulse synthesizer 310 and the second time-averaged frequency-based direct pulse synthesizer 320.
  • the control module 350 connects the oscillator 330 with the first time-averaged frequency-based pulse direct synthesizer 310 and the second time-averaged frequency-based pulse direct synthesizer 320, for controlling the oscillator 330 to the first time-averaged frequency-based pulse direct synthesizer 310 and the second time-averaged frequency-based pulse direct synthesizer 320 input the same initial pulse frequency, and the control module 330 is also configured to input the same initial pulse frequency to the first time-averaged frequency-based pulse direct synthesizer 310 and the second time-averaged frequency-based pulse direct synthesizer 320 Enter the control word.
  • the same input signal (ie, excitation) is input to the symmetrical first time-averaged frequency-based pulse direct synthesizer 310 and the second time-averaged frequency-based pulse direct synthesizer 320, the first time-averaged frequency-based pulse direct
  • the time-averaged frequency pulse synthesizer 320 is used to extract the first parameter, that is, the process deviation of the extraction circuit, and digitally convert it into a characteristic bit stream.
  • the flip-flop 330 compares the first direct synthesizer based on time-averaged frequency pulse with the first 2. Based on the delay of the characteristic bit stream output by the time-averaged frequency pulse synthesizer, and the output response, the mapping relationship can be constructed by the physical unclonable function circuit directly synthesized by the time-averaged frequency pulse.
  • Fig. 6 is the Hamming distance statistic diagram of the reconstructed physical unclonable function circuit based on the direct synthesis of time-averaged frequency pulses and the physical unclonable function circuit based on the direct synthesis of time-averaged frequency pulses before reconstruction, the horizontal axis is Hamming Distance, the vertical axis is the number of bits of response, and the calculation formula of Hamming distance is as follows:
  • HDRC is the Hamming distance of the response generated when the same excitation is input to the physical unclonable function circuit directly synthesized based on the time-averaged frequency pulse after reconstruction and before reconstruction
  • FFB(F, SADR)nA is the basis before reconstruction
  • the response of the physical unclonable function circuit directly synthesized by the time-averaged frequency pulse, FFB(F, SADR)nB is the response of the physical unclonable function circuit directly synthesized based on the time-averaged frequency pulse after reconstruction, and l is the bit length of the response.
  • FIG. 7 is a security protection method for a heterogeneous system provided by a specific embodiment of the present application.
  • the FPGA reads the configuration file from the FLASH or other storage modules, and stores the A physical unclonable function circuit is configured in an area, the physical unclonable function circuit starts to work, and the system detects whether the external input is normal in real time. If yes, then the physical unclonable function circuit generates the corresponding output according to the excitation. If an external input abnormality is detected, a new configuration file is obtained. The new configuration file is different from the configuration file of the running physical unclonable function circuit.
  • the new configuration file in the first area or the second area different from the first area Regions reconstruct physically unclonable function circuits with different layout layouts. In this way an infinite number of virtual stimulus-response pairs can be provided for the entire system.
  • the excitation-response pair of a physical unclonable function circuit is limited, but when it is attacked, reconstruction is equivalent to virtual expansion of its excitation-response pair.
  • This method can not only provide higher security for heterogeneous systems It also has the characteristics of low power consumption and low cost. This method can effectively deal with brute force attacks by criminals and improve the security and life cycle of products.
  • the dynamic heterogeneous security system based on the physical unclonable function circuit directly synthesized by the time-averaged frequency pulse can self-adjust and configure itself when attacked, and realize the dynamic reconstruction of hardware security primitives, thereby enhancing the security of the system.
  • the method can not only increase the safety level, but also effectively prolong the product life cycle.
  • FIG. 8 another embodiment of the present application provides a security protection device for a heterogeneous system, wherein the heterogeneous system includes a processor, the processor includes a first area, and the first area runs a physical unclonable system A functional circuit, the safety protection device includes: a detection module 110 , an acquisition module 120 and a reconstruction module 130 .
  • the detection module 110 is used to detect whether the input of the heterogeneous system is abnormal, and the acquisition module 120 is used to obtain a configuration file when the input of the heterogeneous system is abnormal, and the obtained configuration file is different from the configuration of the running physical unclonable function circuit file, the reconstruction module 130 is configured to reconstruct the mapping relationship of the physical unclonable function circuit on the processor according to the acquired configuration file.
  • the aforementioned security protection device for heterogeneous systems through the aforementioned security protection method, re-acquires a configuration file when detecting that the heterogeneous system is attacked from outside, and reconstructs the mapping relationship of physical unclonable functions on the processor according to the obtained configuration file, Since the mapping relationship of the reconstructed physical unclonable function is different from the mapping relationship of the original physical unclonable function, even if the same stimulus is input, the responses generated by the two are different, so that the attacker cannot attack the reconstructed physical unclonable function.
  • the clone function circuit is modeled, which improves the security of the system.
  • FIG. 9 another embodiment of the present application provides a processor including a programmable logic part 210 , a detector 220 and an operation part 230 .
  • the processor may be an FPGA.
  • the programmable logic part 210 includes a first area, and the first area runs a physical unclonable function circuit.
  • the detector 220 is used to detect whether the FPGA is attacked.
  • the operation unit 230 is configured to obtain a configuration file when the FPGA is attacked, and reconstruct the mapping relationship of the physical unclonable function circuit in the programmable logic unit 210 according to the obtained configuration file, wherein the obtained configuration file is different from the running physical configuration file. Configuration files for unclonable function circuits.
  • the control unit 230 when the detector 220 detects an external attack, the control unit 230 obtains the configuration file again, and reconstructs the mapping relationship of the physical unclonable function on the programmable logic unit 210 according to the obtained configuration file.
  • the mapping relationship of the constructed physical unclonable function is different from the mapping relationship of the original physical unclonable function. Therefore, even if the same stimulus is input, the responses generated by the two are different, which can resist external attackers through the original physical unclonable function.
  • the function circuit modeling attacks the processor and improves the security of the system.
  • the operation unit 230 is further configured to compile and redesign the physical unclonable function circuit according to the acquired configuration file, and store the design result in the programmable logic unit, so as to reconstruct the physical unclonable function circuit mapping relationship.
  • the operation part 230 is used to store the design result in the first area of the programmable logic part or the second area different from the first area, so as to reconstruct the physical unclonable function circuit. It can be understood that, in addition to running the physical unclonable function circuit, the programmable logic unit 210 can also run logic circuits with other functions at the same time.
  • the areas of the first region and the second region are not smaller than the area of the physical unclonable function circuit.
  • the areas of both the first region and the second region are not less than 1.5 times the area occupied by the physical unclonable function circuit, so that the first region or the second region can provide sufficient space for the reconstruction of the physical unclonable function circuit. space margin.
  • the physical unclonable function circuit and the logic circuit of other functions can simultaneously run on the programmable logic part, wherein the physical unclonable function circuit runs on the first area or the second area, and the first area and the second area
  • the area of the two regions is not smaller than the area occupied by the physical unclonable function circuit, so that the first region or the second region can be configured with an infinite variety of physical unclonable function circuits of different structures, and thus realizes a variety of structures with a small overhead. Reconstruction of physically unclonable function circuits can reduce costs.
  • the physical unclonable function circuit is a physical unclonable function circuit directly synthesized based on time-averaged frequency pulses.
  • the structure of the physical unclonable function circuit based on the direct synthesis of time-averaged frequency pulses is shown in FIG.
  • the acquired configuration file is a pre-stored configuration file
  • the pre-stored configuration file is different from the configuration file of the running physical unclonable function circuit.
  • the processor further includes a storage unit for storing the configuration file.
  • the acquired configuration file is a regenerated configuration file
  • the regenerated configuration file is different from the configuration file of the running physical unclonable functional circuit.
  • control part when an external attack is detected, the control part re-acquires the configuration file, and reconstructs the physical unclonable function with different layouts on the programmable logic part according to the obtained configuration file, so as to resist external attackers through the original
  • another embodiment of the present application provides a computer-readable storage medium on which a security protection program of a heterogeneous system is stored, and when the security protection program of the heterogeneous system is executed by a processor, realizes the foregoing protection of the heterogeneous system
  • a security protection program for the description of the operation of the security protection program of the heterogeneous system in this application, please refer to the description of the security protection method of the heterogeneous system in this application, and details are not repeated here.
  • the above computer-readable storage medium through the aforementioned security protection method for heterogeneous systems, reconstructs physical unclonable function circuits with different layouts when detecting that the heterogeneous system is attacked from outside, so that the attacker cannot attack the reconstructed physical unclonable function circuit.
  • the clone function circuit is modeled, which improves the security of the system.
  • another embodiment of the present application provides an electronic device, including a memory, a processor, and a security protection program for a heterogeneous system stored on the memory and running on the processor, and the processor executes the security protection of the heterogeneous system During the program, the aforementioned security protection method of the heterogeneous system is implemented, and details are not repeated here.
  • the electronic device of the embodiment of the present invention through the aforementioned security protection method for heterogeneous systems, when it is detected that the heterogeneous system is attacked from outside, the physical unclonable function circuit is reconstructed with different layouts, and the attacker cannot The physical unclonable function circuit is modeled, which improves the security of the system.
  • a "computer-readable medium” can be any device that can contain, store, communicate, propagate, or transport the program for use by or in connection with an instruction execution system, apparatus, or apparatus.
  • computer readable media include the following: electrical connections with one or more wiring (electronic devices), portable computer disk cartridges (magnetic devices), random access memory (RAM), Read Only Memory (ROM), Erasable Editable Read Only Memory (EPROM or Flash Memory), Fiber Optic Devices, and Portable Compact Disc Read Only Memory (CDROM).
  • the computer readable medium may even be paper or other suitable medium on which the program may be printed, as the paper or other medium may be optically scanned, for example, followed by editing, interpretation, or other suitable medium as necessary process to obtain the program electronically and then store it in computer memory.
  • various parts of the present invention may be implemented in hardware, software, firmware or a combination thereof.
  • various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system.
  • a suitable instruction execution system For example, if implemented in hardware, as in another embodiment, it can be implemented by any one or a combination of the following techniques known in the art: Discrete logic circuits, application specific integrated circuits with suitable combinational logic gates, Programmable Gate Arrays (PGA), Field Programmable Gate Arrays (FPGA), etc.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature delimited with “first”, “second” may expressly or implicitly include at least one of that feature.
  • plurality means at least two, such as two, three, etc., unless otherwise expressly and specifically defined.
  • the terms “installed”, “connected”, “connected”, “fixed” and other terms should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection , or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between the two elements, unless otherwise specified limit.
  • installed may be a fixed connection or a detachable connection , or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between the two elements, unless otherwise specified limit.

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Abstract

本发明提供一种异构系统的安全防护方法、装置及处理器，本申请中异构系统的安全防护方法，当检测到异构系统受到外部攻击时，重新获取配置文件，获取的配置文件不同于已运行的物理不可克隆函数的配置文件，根据获取的配置文件在处理器上重新构建物理不可克隆函数的映射关系，重新构建的物理不可克隆函数的映射关系与原有的物理不可克隆函数的映射关系不同，因此即使输入同样的激励，两者产生的也响应不同，使攻击者无法对重构后的物理不可克隆函数电路进行建模，提高了系统的安全性。

Description

异构系统的安全防护方法、装置及处理器 技术领域
本发明涉及信息安全技术领域，尤其涉及一种异构系统的安全防护方法、装置及处理器。
背景技术
随着5G和物联网的发展，信息呈指数式爆发。物联网终端设备的数量也随之上升，越来越多的设备连入网络，使不法分子拥有更多的入口入侵网络系统。在物联网时代，硬件安全是网络安全的基础，由于物联网中每个设备都具有产生数据、处理数据、发射数据等功能，这将为安全带来巨大挑战。
解决安全问题，物理不可克隆函数(Physical Unclonable Function，PUF)应运而生，物理不可克隆函数是一种依赖芯片特征的硬件函数实现电路，具有唯一性和随机性，通过提取芯片制造过程中必然引入的工艺参数偏差，实现激励信号与响应信号唯一对应的函数功能。传统技术中，不法分子通过对PUF进行建模，根据已使用过的CRP(Challenge Response Pair，激励响应对)建立PUF的模型对系统进行攻击，使得系统安全性不高。
发明内容
本发明旨在至少在一定程度上解决相关技术中的技术问题之一。为此，本发明的第一个目的在于提出一种异构系统的安全防护方法，当检测到外部攻击时对物理不可克隆函数进行重构，使攻击者无法对重构后的物理不可克隆函数电路进行建模，以提高系统的安全性。
本发明的第二个目的在于提出一种计算机可读存储介质。
本发明的第三个目的在于提出一种电子设备。
本发明的第四个目的在于提出一种异构系统的安全防护装置。
本发明的第五个目的在于提出一种处理器。
为达到上述目的，本发明第一方面实施例提出了一种异构系统的安全防护方法，异构系统包括处理器，处理器包括第一区域，第一区域包括物理不可克隆函数电路，该方法包括：
检测异构系统的输入是否异常；
当检测到异构系统的输入异常时，获取配置文件，其中，所述获取的配置文件不同于已运行的物理不可克隆函数电路的配置文件；
根据所述获取的配置文件在处理器上重新构建物理不可克隆函数电路的映射关系。
根据本发明实施例的异构系统的安全防护方法，当检测到异构系统受到外部攻击时，重新获取配置文件，获取的配置文件不同于已运行的物理不可克隆函数的配置文件，根据获取的配置文件在处理器上重新构建物理不可克隆函数的映射关系，重新构建的物理不可克隆函数的映射关系与原有的物理不可克隆函数的映射关系不同，因此即使输入同样的激励，两者产生的也响应不同，使攻击者无法对重构后的物理不可克隆函数电路进行建模，提高了系统的安全性。
为达到上述目的，本发明第二方面实施例提出了一种计算机可读存储介质，其上存储有异构系统的安全防护防护程序，该异构系统的安全防护程序被处理器执行时实现前述异构系统的安全防护方法。
根据本发明实施例的计算机可读存储介质，通过前述的异构系统的安全防护方法，在检测到异构系统受到外部攻击时，重新构建物理不可克隆函数电路，攻击者无法对重构后的物理不可克隆函数电路进行建模，提高了系统的安全性。
为达到上述目的，本发明第三方面实施例提出了一种电子设备，包括存储器、处理器及存储在存储器上并可在处理器上运行的异构系统的安全防护程序，所述处理器执行所述安全防护程序时，实现前述异构系统的安全防护方法。
根据本发明实施例的电子设备，通过前述的异构系统的安全防护方法，在检测到异构系统受到外部攻击时，重新构建物理不可克隆函数电路，攻击者无法对重构后的物理不可克隆函数电路进行建模，提高了系统的安全性。
为达到上述目的，本发明第四方面实施例提出了一种异构系统的安全防护装置，异构系统包括处理器，处理器包括第一区域，第一区域包括物理不可克隆函数电路，该安全防护装置包括：
检测模块，用于检测异构系统的输入是否异常；
获取模块，用于在异构系统的输入异常时，获取配置文件，所述获取的配置文件不同于已运行的所述物理不可克隆函数电路的配置文件；
重构模块，用于根据获取的配置文件在处理器上重新构建物理不可克隆函数电路的映射关系。
根据本发明实施例的异构系统的安全防护装置，在检测到异构系统受到外部攻击时，重新构建物理不可克隆函数电路，攻击者无法对重构后的物理不可克隆函数电路进行建模，提高了系统的安全性。
为达到上述目的，本发明第五方面实施例提出了一种处理器，包括：
可编程逻辑部，可编程逻辑部包括第一区域，第一区域包括物理不可克隆函数电路；
检测器，检测器用于检测处理器是否被攻击；
操作部，操作部用于在处理器被攻击时，获取配置文件，并根据所述获取的配置文件在可编程逻辑部重新构建物理不可克隆函数电路的映射关系，其中，所述获取的配置文件不同于已运行的物理不可克隆函数电路的配置文件。
根据本发明实施例的处理器，在检测到异构系统受到外部攻击时，重新构建物理不可克隆函数电路，攻击者无法对重构后的物理不可克隆函数电路进行建模，提高了系统的安全性。
本发明附加的方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本发明的实践了解到。
附图说明
图1为根据本发明实施例的异构系统的模块示意图；
图2为根据本发明实施例的异构系统的安全防护方法的流程图；
图3为根据本发明实施例的处理器的分区示意图；
图4为根据本发明实施例的处理器的基于时间平均频率脉冲直接合成的物理不可克隆函数电路的模块示意图；
图5为根据本发明实施例的基于时间平均频率脉冲直接合成器的工作原理示意图；
图6为根据本发明实施例的处理器的基于时间平均频率脉冲直接合成的物理不可克隆函数电路重构前和重构后的汉明距离统计图；
图7为根据本发明一个具体实施例的异构系统的安全防护方法的流程图；
图8为根据本发明实施例的异构系统的安全防护装置的模块示意图；
图9为根据本发明实施例的处理器的模块示意图。
具体实施方式
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，旨在用于解释本发明，而不能理解为对本发明的限制。
下面参考附图描述本发明实施例提出的异构系统的安全防护方法、装置及处理器。
在本申请中，参考图1所示，异构系统包括处理器，用于运行物理不可克隆函数电路。本实施例中，处理器可以是可编程逻辑阵列(Field Programmable Gate Array，FPGA)。除FPGA外，异构系统还包括中央处理器(Central Processing Unit，CPU)、图形处理器(Graphics Processing Unit，GPU)、数字信号处理单元(Digital Signal Process，DSP)，用于满足万物联网下不同场景的需求，比如某些算法迭代速度过快，不适合做成专用芯 片，将由FPGA来完成运算，有些电路数据格式统一，重复性很高，将由GPU完成计算，整个系统可以满足各种计算的需求。
FPGA包括可编程逻辑部分(Programmable Logic，PL)和程序系统(Process System，PS)部分。其中，PL部分包括第一区域，第一区域包括物理不可克隆函数电路。如图2所示，异构系统的安全防护方法包括：
步骤S100，检测异构系统的输入是否异常。
异构系统包括检测器，如AI(Artificial Intelligence，人工智能)检测器，检测器用于检测系统的输入是否异常。系统上电后，配置于FPGA上PL部分的第一区域内的物理不可克隆函数电路开始工作，每次通过CRP完成身份验证或数据加密，每一对CRP使用后丢弃，并记录。当系统上电工作时，AI检测器实时检测外部是否有对系统进行攻击，例如是否有使用过被丢弃的CRP多次申请验证、异构系统软件是否发现外部访问、以及异构系统的温度和电压等物理参数是否发生异常抖动等，若存在上述情况，则可以判定异构系统输入异常，也即异构系统遭遇外部攻击。
步骤S200，当检测到异构系统的输入异常时，获取配置文件，其中，获取的配置文件不同于已运行的物理不可克隆函数电路的配置文件。
配置文件用于配置FPGA中物理不可克隆函数电路的器件布局和布线。当检测到异构系统输入异常时，FPGA将已运行的物理不可克隆函数电路抹除，并重新获取配置文件，获取的配置文件不同于已运行的物理不可克隆函数电路的配置文件，以便在FPGA中重构物理不可克隆函数电路。
在其中一个实施例中，获取配置文件包括：获取预存的配置文件，其中，获取的预存的配置文件不同于已运行物理不可克隆函数电路的配置文件。本实施例中，异构系统的存储模块中预先存储有多个不同的配置文件，以便异构系统被攻击时，获取新的配置文件，并根据新的配置文件重新构建不同布局版图的物理不可克隆函数电路。
在另一个实施例中，获取配置文件包括：重新生成配置文件，且重新生成的配置文件不同于已运行的物理不可克隆函数电路的配置文件。具体来说，当异构系统中存储的配置文件均被攻击不可使用时，系统可直接生成配置文件，利用重新生成的配置文件在FPGA中构建物理不可克隆函数电路，使得攻击者无法对所有物理不可克隆函数电路进行遍历攻击，进而提高异构系统的安全性。
步骤S300，根据获取的配置文件在FPGA上重新构建物理不可克隆函数电路的映射关系。
其中，映射关系包括物理不可克隆函数电路的激励与响应之间的关系，映射关系具体可以表示为：
f(c)＝r
其中，c是challenge的缩写，代表激励，即用户或请求方发送的验证码，r是response的缩写，即验证方根据激励所产生的响应，f()反应的是映射关系。不同的物理不可克隆函数其工艺偏差不同，映射关系也不同。FPGA可以读取配置文件并根据配置文件选定区域后对该选定区域的逻辑元件进行布局、连线，以重新构建物理不可克隆函数电路的映射关系。
上述异构系统的安全防护方法，当检测到异构系统受到外部攻击时，重新获取配置文件，获取的配置文件不同于已运行的物理不可克隆函数的配置文件，根据获取的配置文件在FPGA上重新构建物理不可克隆函数的映射关系，重新构建的物理不可克隆函数的映射关系与原有的物理不可克隆函数的映射关系不同，因此即使输入同样的激励，两者产生的也响应不同，使攻击者无法对重构后的物理不可克隆函数电路进行建模，提高了系统的安全性。
在其中一个实施例中，根据获取的配置文件在处理器上以不同布局版图的方式重新构建物理不可克隆函数电路的映射关系包括：根据获取的配置文件，对物理不可克隆函数电路进行编译后重新设计；将设计的结果存储至处理器，以重新构建物理不可克隆函数电路的映射关系。
具体来说，异构系统在受到外部攻击时，抹除原有的物理不可克隆函数电路，并根据获取的配置文件进行编译，重新对器件进行设计，以重新构建物理不可克隆函数电路的映射关系。其中，对物理不可克隆函数电路进行编译后重新设计指的是设计物理不可克隆函数电路的布局布线方式，将设计的结果存储至处理器上，使得重构的物理不可克隆函数电路在处理器上运行，由于重构的物理不可克隆函数电路中逻辑元件的布局布线结构与原有的物理不可克隆函数电路中逻辑元件的布局布线结构不同，电路的偏差也不同，即使输入同样的激励，产生的响应也不同，进而使外部攻击者无法进行建模，以提高异构系统的安全性。
进一步地，在其中一个实施例中，将设计的结果存储至处理器，以重新构建物理不可克隆函数电路的映射关系包括：将设计的结果存储至处理器的第一区域或不同于第一区域的第二区域，以重新构建物理不可克隆函数电路的映射关系。
具体来说，本申请不仅可以在运行原有物理不可克隆函数电路的第一区域运行重构的物理不可克隆函数电路，也可以在不同于第一区域的第二区域上运行重构的物理不可克隆函数电路，甚至其他区域上也可运行重构物理不可克隆函数电路，只要重构的物理不可克隆函数电路与原有的物理不可克隆函数电路的设计不同，也即布局布线的方式不同即可。
如图3所示，FPGA包括PS部分和PL部分。其中PS部分用来完成软件算法或特殊控制，在其内部存在一个实时操作系统，而PL部分则用于可编程逻辑，可以在PL上，实现不同逻辑电路或运算。本实施例中，第一区域和第二区域均位于PL部分。物理不可克隆函数电路可以以较小的开销在该FPGA中实现，例如可在PL部分设置第一区域和第二区域，物理不可克隆函数电路可以以部分可重构的方式在PL的第一区域或第二区域或其他区域上运行。并且，可以根据需求设计物理不可克隆函数电路的大小，其中，物理不可克隆函数电路的激励与根据激励产生的激励响应对的关系可参考表1所示：
表1
Figure PCTCN2020130574-appb-000001
可以理解的是，为了存储重构的物理不可克隆函数电路的设计，第一区域和第二区域的面积均大于物理不可克隆函数电路。本实施例中，第一区域和第二区域的面积的面积可以设计为均不小于物理不可克隆函数电路所占面积的1.5倍，以便为重构后的物理不可克隆函数提供足够的空间裕度。
上述异构系统的安全防护方法，既可以在运行原有物理不可克隆函数电路的第一区域重构，也可以在不同于第一区域的第二区域甚至其他区域上重构，从而可以为处理器提供无限的激励响应对，使外部攻击者无法进行建模或遍历攻击，提高异构系统的安全性。另外，由于第一区域和第二区域的面积均大于物理不可克隆函数电路所占面积，从而第一区域或第二区域可以配置无限多种不同结构的物理不可克隆函数电路，进而以较小的开销实现了多种结构的物理不可克隆函数电路的重构，可以降低成本。
在其中一个实施例中，物理不可克隆函数电路为基于时间平均频率脉冲直接合成的物理不可克隆函数电路(Time-Average-Frequency Direct Period Synthesis Physical Unclonable Function,TAF-DPS-PUF)。其中，TAF-DPS-PUF可以根据以下步骤构建映射关系：通过对称的第一基于时间平均频率脉冲直接合成器和第二基于时间平均频率脉 冲直接合成器分别提取第一参数，以生成对应的特征比特流；根据第一基于时间平均频率脉冲直接合成器和第二基于时间平均频率脉冲直接合成器输出特征比特流的延迟特性构建映射关系。
具体来说，参考图4所示，基于时间平均频率脉冲直接合成的物理不可克隆函数电路包括对称的第一基于时间平均频率脉冲直接合成器310和第二基于时间平均频率脉冲直接合成器320、触发器330。其中，该结合图5说明该基于时间平均频率脉冲直接合成器(TAF-DPS)的可选实现过程：TAF-DPS频率合成器分别接收基本时间单元Δ和控制字F＝I+r，其中I代表整数部分，r代表小数部分，F通常由用户根据频率需要而输入，基本时间单元Δ通常根据电路设计的需要而设计，则通过该TAF方式可以输出两种时间周期TA和TB：
TA＝I*Δ    公式(1)；
TB＝(I+1)*Δ    公式(2)；
将该两种时间周期通过周期合成技术可以合成得到一个周期为目标周期的时钟信号，且该目标周期T TAF可以满足：
T TAF＝(1-r)*TA+r*TB    公式(3)；
将公式(1)和公式(2)代入公式(3)可以得到：
T TAF＝(I+r)*Δ    公式(4)；
根据公式(4)可以看出，r可以控制TB出现的概率，即控制周期TA和TB之间的切换频率。
基于公式(4)可以进一步计算出TAF-DPS频率合成器输出的时钟信号的频率f TAF为：
f TAF＝1/T TAF＝1/[(I+r)*Δ]    公式(5)；
只要给定控制字F中的r足够的位的数目，TAF-DPS频率合成器可以生成任何频率。
本实施例中，第一基于时间平均频率脉冲直接合成器310和第二基于时间平均频率脉冲合成器320具有相同的逻辑单元种类、数量和布局布线方式，两者形成相同结构的时延路径。基于时间平均频率脉冲直接合成的物理不可克隆函数电路还包括振荡器340和控制模块350，振荡器340连接第一基于时间平均频率脉冲直接合成器310和第二基于时间平均频率脉冲直接合成器320，控制模块350连接振荡器330和第一基于时间平均频率脉冲直接合成器310和第二基于时间平均频率脉冲直接合成器320，用于控制振荡器330向第一基于时间平均频率脉冲直接合成器310和第二基于时间平均频率脉冲直接合成器320输入同一初始脉冲频率，同时控制模块330还用于向第一基于时间平均频率脉冲直接合成器310和第二基于时间平均频率脉冲直接合成器320输入控制字。相同 的输入信号(也即激励)输入对称的第一基于时间平均频率脉冲直接合成器310和第二基于时间平均频率脉冲合成器320，第一基于时间平均频率脉冲直接合成器310和第二基于时间平均频率脉冲合成器320用于分别提取第一参数，也即提取电路的工艺偏差，并将其数字化转换成特征比特流，触发器330通过比较第一基于时间平均频率脉冲直接合成器和第二基于时间平均频率脉冲合成器输出的特征比特流的延迟，输出响应，即可通过时间平均频率脉冲直接合成的物理不可克隆函数电路构建映射关系。由于重构前和重构后物理不可克隆函数电路的版图不同，工艺偏差不同，内部连线的延迟不同，进而映射关系也不同，从而攻击者无法对重构的物理不可克隆函数电路进行建模，提高了异构系统的安全性。
图6为重构后的基于时间平均频率脉冲直接合成的物理不可克隆函数电路和重构前的基于时间平均频率脉冲直接合成的物理不可克隆函数电路的汉明距离统计图，横轴为汉明距离，纵轴为响应的位数，其中汉明距离的计算公式如下：
Figure PCTCN2020130574-appb-000002
上述公式中，HDRC是重构后和重构前基于时间平均频率脉冲直接合成的物理不可克隆函数电路输入相同激励时产生的响应的汉明距离，FFB(F,SADR)nA是重构前基于时间平均频率脉冲直接合成的物理不可克隆函数电路的响应，FFB(F,SADR)nB是重构后基于时间平均频率脉冲直接合成的物理不可克隆函数电路的响应，l是响应的位长。由图5可以看出，重构后和重构的汉明距离大于50％，因此重构后和重构前基于时间平均频率脉冲直接合成的物理不可克隆函数电路在相同激励下产生的响应完全不同。
如图7所示，图7为本申请的一个具体实施例提供的异构系统的安全防护方法，在系统上电后，FPGA从FLASH或其他存储模块中读取配置文件，并在PL的第一区域上配置物理不可克隆函数电路，物理不可克隆函数电路开始工作，系统实时检测外部输入是否正常，若外输入正常，表明外部无非法侵入，则判断是否有激励输入物理不可克隆函数电路，若有，则物理不可克隆函数电路根据激励产生相应并输出。若检测到外部输入异常，则获取新的配置文件，新的配置文件不同于已运行的物理不可克隆函数电路的配置文件，根据新的配置文件在第一区域或不同于第一区域的第二区域以不同布局版图重新构建物理不可克隆函数电路。通过这种方法可以为整个系统提供无限的虚拟激励响应对。一个物理不可克隆函数电路的激励响应对是有限的，但当其受到攻击时，进行重构，相当于对其激励响应对进行了虚拟扩展，该方法不仅能为异构系统提供较高的安全性，同时还有低功耗、低成本等特点。该方法能够有效应对不法分子的暴力攻击，提高产品的安全性和生命周期。基于时间平均频率脉冲直接合成的物理不可克隆函数电路的 动态异构安全系统在遭受攻击时能够自我调节，配置，实现硬件安全原语动态重构，进而增强系统的安全性。本方法不但能够增加安全等级，还能够有效延长产品生命周期。
另外，如图8所示，本申请的又一实施例提供一种异构系统的安全防护装置，其中，异构系统包括处理器，处理器包括第一区域，第一区域运行有物理不可克隆函数电路，该安全防护装置包括：检测模块110、获取模块120和重构模块130。其中，检测模块110用于检测异构系统的输入是否异常，获取模块120用于在异构系统的输入异常时，获取配置文件，获取的配置文件不同于已运行的物理不可克隆函数电路的配置文件，重构模块130用于根据获取的配置文件在处理器上以重新构建物理不可克隆函数电路的映射关系。
需要说明的是，关于本申请中的异构系统安全防护装置的描述，请参考本申请中关于的异构系统安全防护方法的描述，具体这里不再赘述。
上述异构系统的安全防护装置，通过前述安全防护方法，当检测到异构系统受到外部攻击时，重新获取配置文件，根据获取的配置文件在处理器上重新构建物理不可克隆函数的映射关系，由于重新构建的物理不可克隆函数的映射关系与原有的物理不可克隆函数的映射关系不同，因此即使输入同样的激励，两者产生的也响应不同，使攻击者无法对重构后的物理不可克隆函数电路进行建模，提高了系统的安全性。
此外，如图9所示，本申请的又一实施例提供一种处理器，包括可编程逻辑部210、检测器220和操作部230。本实施例中，处理器可以是FPGA。其中，可编程逻辑部210包括第一区域，第一区域运行有物理不可克隆函数电路。检测器220用于检测FPGA是否被攻击。操作部230用于在FPGA被攻击时，获取配置文件，并根据获取的配置文件在可编程逻辑部210重新构建物理不可克隆函数电路的映射关系，其中，获取的配置文件不同于已运行的物理不可克隆函数电路的配置文件。
上述实施例提供的处理器，当检测器220检测到外部攻击时，控制部230重新获取配置文件，根据获取的配置文件在可编程逻辑部210上重新构建物理不可克隆函数的映射关系，由于重新构建的物理不可克隆函数的映射关系与原有的物理不可克隆函数的映射关系不同，因此即使输入同样的激励，两者产生的也响应不同，从而可以抵御外部攻击者通过原有的物理不可克隆函数电路建模对处理器进行攻击，提高了系统的安全性。
在其中一个实施例中，操作部230还用于根据获取的配置文件对物理不可克隆函数电路进行编译后重新设计，并将设计的结果存储至可编程逻辑部，以重新构建物理不可克隆函数电路的映射关系。
在另一个实施例中，操作部230用于将设计的结果存储至可编程逻辑部的第一区域或不同于第一区域的第二区域，以重新构建物理不可克隆函数电路。可以理解的是，可 编程逻辑部210上除运行物理不可克隆函数电路外，还可同时运行其他功能的逻辑电路。
可以理解的是，为存储物理不可克隆函数电路，第一区域和第二区域的面积均不小于物理不可克隆函数电路的面积。本实施例中，第一区域和第二区域的面积均不小于物理不可克隆函数电路所占面积的1.5倍，从而第一区域或第二区域可以为物理不可克隆函数电路的重构提供足够的空间裕度。
上述实施例提供的处理器，可编程逻辑部上可以同时运行物理不可克隆函数电路和其他功能的逻辑电路，其中物理不可克隆函数电路在第一区域或第二区域上运行，第一区域和第二区域的面积均不小于物理不可克隆函数电路所占面积，从而第一区域或第二区域可以配置无限多种不同结构的物理不可克隆函数电路，进而以较小的开销实现了多种结构的物理不可克隆函数电路的重构，可以降低成本。
在其中一个实施例中，物理不可克隆函数电路为基于时间平均频率脉冲直接合成的物理不可克隆函数电路。基于时间平均频率脉冲直接合成的物理不可克隆函数电路的结构如图4所示，其工作原理参见前段描述，在此不再赘述。
在其中一个实施例中，获取的配置文件为预存的配置文件，且预存的配置文件不同于已运行的物理不可克隆函数电路的配置文件。可以理解的是，处理器还包括存储单元，用于存储配置文件。
在另一种实施例中，获取的配置文件为重新生成的配置文件，重新生成的配置文件不同于已运行的物理不可克隆函数电路的配置文件。当预存的配置文件全部被攻击不可使用时，处理器还可以直接生成新的配置文件，使得攻击者无法进行遍历攻击。
上述处理器，当检测到外部攻击时，控制部重新获取配置文件，根据获取的配置文件在可编程逻辑部上以不同布局版图重新构建物理不可克隆函数，从而能够抵御外部攻击者通过原有的物理不可克隆函数电路建模对处理器进行攻击，提高了处理器的安全性。
另外，本申请的又一实施例提供一种计算机可读存储介质，其上存储有异构系统的安全防护程序，该异构系统的安全防护程序被处理器执行时实现前述的异构系统的安全防护方法，关于本申请中异构系统的安全防护程序运行的描述，请参考本申请中关于异构系统的安全防护方法的描述，具体这里不再赘述。
上述计算机可读存储介质，通过前述异构系统的安全防护方法，在检测到异构系统受到外部攻击时，以不同布局版图重新构建物理不可克隆函数电路，攻击者无法对重构后的物理不可克隆函数电路进行建模，提高了系统的安全性。
此外，本申请的又一实施例提供一种电子设备，包括存储器、处理器及存储在存储器上并可在处理器上运行的异构系统的安全防护程序，处理器执行异构系统的安全防护 程序时，实现前述的异构系统的安全防护方法，具体这里不再赘述。
根据本发明实施例的电子设备，通过前述的异构系统的安全防护方法，在检测到异构系统受到外部攻击时，以不同布局版图重新构建物理不可克隆函数电路，攻击者无法对重构后的物理不可克隆函数电路进行建模，提高了系统的安全性。
需要说明的是，在流程图中表示或在此以其他方式描述的逻辑和/或步骤，例如，可以被认为是用于实现逻辑功能的可执行指令的定序列表，可以具体实现在任何计算机可读介质中，以供指令执行系统、装置或设备(如基于计算机的系统、包括处理器的系统或其他可以从指令执行系统、装置或设备取指令并执行指令的系统)使用，或结合这些指令执行系统、装置或设备而使用。就本说明书而言，"计算机可读介质"可以是任何可以包含、存储、通信、传播或传输程序以供指令执行系统、装置或设备或结合这些指令执行系统、装置或设备而使用的装置。计算机可读介质的更具体的示例(非穷尽性列表)包括以下：具有一个或多个布线的电连接部(电子装置)，便携式计算机盘盒(磁装置)，随机存取存储器(RAM)，只读存储器(ROM)，可擦除可编辑只读存储器(EPROM或闪速存储器)，光纤装置，以及便携式光盘只读存储器(CDROM)。另外，计算机可读介质甚至可以是可在其上打印所述程序的纸或其他合适的介质，因为可以例如通过对纸或其他介质进行光学扫描，接着进行编辑、解译或必要时以其他合适方式进行处理来以电子方式获得所述程序，然后将其存储在计算机存储器中。
应当理解，本发明的各部分可以用硬件、软件、固件或它们的组合来实现。在上述实施方式中，多个步骤或方法可以用存储在存储器中且由合适的指令执行系统执行的软件或固件来实现。例如，如果用硬件来实现，和在另一实施方式中一样，可用本领域公知的下列技术中的任一项或他们的组合来实现：具有用于对数据信号实现逻辑功能的逻辑门电路的离散逻辑电路，具有合适的组合逻辑门电路的专用集成电路，可编程门阵列(PGA)，现场可编程门阵列(FPGA)等。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在本发明的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。
在本发明中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系，除非另有明确的限定。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
尽管上面已经示出和描述了本发明的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本发明的限制，本领域的普通技术人员在本发明的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (16)

  1. 一种异构系统的安全防护方法，其特征在于，所述异构系统包括处理器，所述处理器包括第一区域，所述第一区域包括物理不可克隆函数电路，所述方法包括：
    检测所述异构系统的输入是否异常；
    当检测到所述异构系统的输入异常时，获取配置文件，其中，所述获取的配置文件不同于已运行的所述物理不可克隆函数电路的配置文件；
    根据所述获取的配置文件在所述处理器上重新构建所述物理不可克隆函数电路的映射关系。
  2. 根据权利要求1所述的安全防护方法，其特征在于，根据所述获取的配置文件在所述处理器上重新构建所述物理不可克隆函数电路的映射关系，包括：
    根据所述获取的配置文件，对所述物理不可克隆函数电路进行编译后重新设计；
    将所述设计的结果存储至所述处理器，以重新构建所述物理不可克隆函数电路的映射关系。
  3. 根据权利要求2所述的安全防护方法，其特征在于，将所述设计的结果存储至所述处理器，以重新构建所述物理不可克隆函数电路的映射关系包括：
    将所述设计的结果存储至至所述处理器的所述第一区域或者不同于所述第一区域的第二区域，以重新构建所述物理不可克隆函数电路的映射关系。
  4. 根据权利要求1-3中任一项所述的安全防护方法，其特征在于，所述物理不可克隆函数电路为基于时间平均频率脉冲直接合成的物理不可克隆函数电路。
  5. 根据权利要求4所述的安全防护方法，其特征在于，所述基于时间平均频率脉冲直接合成的物理不可克隆函数电路根据以下步骤构建映射关系：
    通过对称的第一基于时间平均频率脉冲直接合成器和第二基于时间平均频率脉冲直接合成器分别提取第一参数，以生成对应的特征比特流；
    根据所述第一基于时间平均频率脉冲直接合成器和所述第二基于时间平均频率脉冲直接合成器输出特征比特流的延迟特性构建映射关系。
  6. 根据权利要求1所述的安全防护方法，其特征在于，当检测到所述异构系统的输入异常时，获取配置文件，包括：
    获取预存的配置文件，其中，获取的预存的配置文件不同于已运行的所述物理不可克隆函数电路的配置文件；或
    重新生成配置文件，其中，重新生成的配置文件不同于已运行的所述物理不可克隆函数电路的配置文件。
  7. 一种计算机可读存储介质，其特征在于，其上存储有异构系统的安全防护防护程序， 该异构系统的安全防护程序被处理器执行时实现如权利要求1-6中任一项所述的异构系统的安全防护方法。
  8. 一种电子设备，其特征在于，包括存储器、处理器及存储在存储器上并可在处理器上运行的异构系统的安全防护程序，所述处理器执行所述安全防护程序时，实现如权利要求1-6中任一项所述的异构系统的安全防护方法。
  9. 一种异构系统的安全防护装置，其特征在于，所述异构系统包括处理器，所述处理器包括第一区域，所述第一区域包括物理不可克隆函数电路，所述安全防护装置包括：
    检测模块，用于检测所述异构系统的输入是否异常；
    获取模块，用于在所述异构系统的输入异常时，获取配置文件，所述获取的配置文件不同于已运行的所述物理不可克隆函数电路的配置文件；
    重构模块，用于根据获取的配置文件在所述处理器上重新构建所述物理不可克隆函数电路的映射关系。
  10. 一种处理器，其特征在于，包括：
    可编程逻辑部，所述可编程逻辑部包括第一区域，所述第一区域包括物理不可克隆函数电路；
    检测器，所述检测器用于检测所述处理器是否被攻击；
    操作部，所述操作部用于在所述处理器被攻击时，获取配置文件，并根据所述获取的配置文件在所述可编程逻辑部重新构建所述物理不可克隆函数电路的映射关系，其中，所述获取的配置文件不同于已运行的所述物理不可克隆函数电路的配置文件。
  11. 根据权利要求10所述的处理器，其特征在于，所述操作部还用于根据所述获取的配置文件，对所述物理不可克隆函数电路进行编译后重新设计，并将所述设计的结果存储至所述可编程逻辑部，以重新构建所述物理不可克隆函数电路的映射关系。
  12. 根据权利要求10所述的处理器，其特征在于，所述操作部还用于将所述设计的结果存储至所述可编程逻辑部的第一区域或不同于所述第一区域的第二区域，以重新构建所述物理不可克隆函数电路的映射关系。
  13. 根据权利要求10-12中任一项所述的处理器，其特征在于，所述物理不可克隆函数电路为基于时间平均频率脉冲直接合成的物理不可克隆函数电路。
  14. 根据权利要求13所述的处理器，其特征在于，所述基于时间平均频率脉冲直接合成的物理不可克隆函数电路包括：
    对称的第一基于时间平均频率脉冲直接合成器和第二基于时间平均频率脉冲直接合成器，所述第一基于时间平均频率脉冲直接合成器和第二基于时间平均频率脉冲直接合成器用于分别提取第一参数，以生成对应的特征比特流；
    触发器，所述触发器用于根据所述第一基于时间平均频率脉冲直接合成器和所述第二基于时间平均频率脉冲直接合成器输出特征比特流的延迟特性产生特征响应。
  15. 根据权利要求10所述的处理器，其特征在于，所述获取的配置文件为预存的配置文件，且所述预存的配置文件不同于已运行的所述物理不可克隆函数电路的配置文件。
  16. 根据权利要求10所述的处理器，其特征在于，所述获取的配置文件为重新生成的配置文件，且所述重新生成的配置文件不同于已运行的所述物理不可克隆函数电路的配置文件。
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